Mohamad El-Roz
email: mohamad.elroz@ensicaen.fr

Philippe Bazin

Marco Daturi

Frederic Thibault-Starzyk

Operando IR coupled to SSITKA for photocatalysis: reactivity and mechanistic studies

Keywords: IR-operando, SSITKA, photocatalysis, TiO 2, methanol photooxidation, methyl formate, CO 2 -selectivity, air purification

This paper reports the coupling of operando IR and SSITKA (Steady State Isotopic Transient Kinetic Analysis) for air purification studies from VOCs by photocatalysis. Methanol photooxidation has been used as a model reaction. A new photocatalyst (TiO 2 -L) has been studied and compared to the reference material TiO 2 -P25. The TOF and reaction rate have been calculated and compared. We show that TOF values are not really available in heterogeneous photocatalysis where the number of active site can vary from one TiO 2 material to the other and from one experimental setup to the other. The influence of methanol concentration and reaction temperature on photocatalytic activity and on selectivity was also investigated. TiO 2 -L is more active than TiO 2 -P25 at low methanol concentration and more selective at high methanol concentrations. SSITKA clarified the role of the surface formate species in the reaction mechanism. Most of these formate species are spectators and are not the main intermediates in alcohol photooxidation. A graduation was found in the efficiency of active sites on photocatalyst surfaces.

Introduction

The exponential growth of population accompanied with a high increase of industrial and military activities have caused a rapid degradation of air and water quality in the last few years. Consequently, environmental pollution is now a major global priority, requiring a considerable research effort. New analytical, biochemical, and physicochemical methods are developed and studied for the characterization and elimination of hazardous chemical compounds from air, soil, and water. Advanced oxidation processes (AOPs), and especially heterogeneous photocatalysis, are intended to be both supplementary and complementary to some of the more conventional approaches to the destruction and/or transformation of hazardous chemical wastes such as filtration 1 , anaerobic digestion 2 , and conventional physicochemical treatment [3][4][5][6] . In the field of air cleaning technologies, heterogeneous photocatalysis is a well established and widely investigated process for the oxidation of many pollutants in air, especially indoor air where pollution can be even more important. 7,8 More than 2000 companies now commercialize different photocatalytic products, mainly for selfcleaning applications. [7][8][9] Therefore, the developments of new techniques and methods to investigate photocatalytic activity of solids, in water and/or air, become more and more important. During the last decade, more than 22 10 3 papers on photocatalysis have been published, out of which only ~5% deal with its application to air purification versus more than 32% for water purification. [START_REF]Web of knowledge[END_REF][START_REF]Scifinder® site[END_REF] The reasons for this could well be experimental difficulties, since studying heterogeneous photocatalysis is often more difficult in the gas phase than in the liquid phase:

(i) contrarily to water purification where the photocatalyst can be used as a suspension, photocatalysis processes (or studies) for air purification require the fixation of the photocatalyst on a support or/and on the reactor surface. This needs, in most cases, the use of a binder, which could influence photocatalytic activity;

(ii) a homogenous and reproducible irradiation of the photocatalyst surfaces is needed in order to have reproducible experiments and results;

(iii) the amount of photocatalyst used must be known accurately and the loss of material during the reaction must be kept to a minimum; (iv) for spectroscopic studies, the design of the reactor can be difficult, and, for example, the internal volume of the reactor must be kept as small as possible to minimize the optical pathway in the gas phase and to decrease residence time;

(v) the reaction parameters (e.g. air composition, air flow (or contact time), temperature, irradiation intensity…) must be easily and accurately controlled, etc… For these reasons, we have developed recently a new operando IR reactor for studying photocatalytic processes for air purification. [START_REF] El-Roz | [END_REF]13 This technique presents several advantages: (i) the photocatalyst is used and studied under the form of thin pellets, which allows limiting the mass loss, with an accurate control of the photocatalyst mass, and which ensures a homogenous irradiation of the photocatalyst surface;

(ii) the irradiation intensity can be easily controlled and the irradiation source can be changed (to mono or polychromatic irradiations, UV and/or visible light sources…) without changing the photoreactor;

(iii) the dead volume is reduced to about 0.4 ml (residual space between each sample face and the photoreactor windows);

(iv) the reactor is coupled to on line analysis techniques, such as IR gas cell and mass spectroscopy (or GC-MS), which provides photocatalytic activity and selectivity data with high precision;

(v) the heating temperature of the reactor-cell can be controlled from RT to 600°C, and the VOCs (volatile organic compounds) or different gas concentrations from a few ppm to a few %. The air composition (VOCs mixture, humidity, toxic gas…) and the gas flow (from 1 to 50 cm 3 /min) can reproduce the real conditions of the photocatalytic reaction and the influence of these parameters on photocatalytic activities and selectivities is easily studied. This paper demonstrates the reliability of this technique in the study of the photoactivity and selectivity of a newly elaborated TiO 2 photocatalyst (TiO 2 -L) and of TiO 2 -P25 (Evonik-Degussa) in the purification of air from methanol used as a model molecule for VOCs. We already presented previously the role of surface sites for the adsorption of reactants and for the formation of intermediates in room temperature methanol photooxidation [START_REF] El-Roz | [END_REF] . The usually accepted mechanism involves formate species as main intermediates (as is the case for thermal oxidation 14 ), since these formates were detected by IR spectroscopy on the surface, but no kinetic proof for the validation of this hypothesis has ever been reported. [START_REF] El-Roz | [END_REF]15,16 For these reasons, we further investigated this system using the SSITKA approach (isotopic exchange techniques ( 12 CH 3 OH/ 13 CH 3 OH)) combined with infrared (IR) operando analysis system, a methodology which has already shown excellent results in methanol oxidation studies 17 but was up to now not accessible in photocatalysis. We also report the influence of some other parameters on the CO 2 -selectivity and activity of TiO 2 , like the temperature and the methanol concentration of.

Experimental section

Synthesis and characterization of TiO 2 -L

Hierarchical TiO 2 (TiO 2 -L) has been synthesized and characterized as described in reference [18]. The seeding of natural Luffa sponge (used as biotemplate) with TiO 2 anatase was accomplished by a 24 h hydrothermal synthesis at 100°C, under autogeneous pressure. A synthesis mixture with the following composition 10Ti(OEt) 4 :45C 2 H 5 OH:45H 2 O (vol.%) was used. The precursor solution was stirred with the Luffa sponges at room temperature for 1 h.

Then, 100 ml of the solution (together with 500 mg of Luffa sponge) was poured into Teflonlined stainless steel autoclaves. After the synthesis, the Luffa sponges were removed from the autoclaves, thoroughly cleaned (in order to remove the excess of TiO 2 seeds loosely bound on the substrate) with ethanol and water, and dried overnight at 60°C. After rinsing, the samples (TiO 2 /Luffa) were calcined under air: 5 h ramp to 500°C and 5 h dwell time. A macro-tubular TiO 2 shape with macro-channel was obtained after removal of the natural organic support (replica of luffa fibers) (Figure S-1). Then, TiO 2 -L samples were characterized using XRD, N 2 sorption and UV-vis spectroscopy; 18 the results are collected in Table 1. As a comparison, the photooxidation was also performed on a commercial TiO 2 from Evonik-Degussa (TiO 2 -P25).

Photocatalysis

The photocatalytic oxidation of methanol was performed using the new operando IR reactor described in reference [13]. The TiO 2 -L and TiO 2 -P25 (Degussa) were pressed into selfsupported wafers (Ø = 16 mm, m = ~10 mg/cm 2 ; thickness = 50-60µm (measured by Micromaster-IP54)). The cell was connected to gas lines with gas mixing devices and mass flow controllers. The two gas mixtures, so called activation and reaction flows, could be prepared and sent independently to the reactor cell. Exhaust gases (reactive and/or reaction products) can be analyzed by a Quadrupole Mass Spectrometer (Pfeiffer Omnistar GSD 301), while complementary information on the gas phase can be gained by IR spectroscopy through a gas micro-cell. IR spectra (64 scans per spectrum) of the catalyst under working conditions were collected at a time resolution of 1 spectrum each 2 minutes with a Thermo Scientific Nicolet 6700 spectrometer, equipped with a MCT detector. More details can be found in the following references for both the operando IR system [19-21] and the modified IR reactor-cell [12]. All IR spectra are displayed as absorbance. For this specific study, the system was equipped with two saturators in the same thermostatic bath (at exactly the same temperature), in order to send, via a 4 ways valve, a fixed concentration of vaporized methanol, either in its natural form or 99.0% 13 C enriched, provided by Cambridge Isotope Laboratories. The flow conditions were as follows: 400-1200 ppm CH 3 OH, 20% oxygen in Argon at 60,000 h -1 constant gas hourly space velocity. A calibration curve was drawn to establish the linear relationship between the concentration of methanol and the MS (at m/z=29) and IR (at 1038-1026 cm -1 ) signals (Figure S-1). The reaction was studied at RT. A monochromatic UV irradiation at 365 nm with I 0 ~11 mW/cm 2 was used in order to simplify the discussion of the results. It was applied with a Xe-Hg lamp (LC8 Spot Light Hamamatsu, L10852, 200 W) and a 365 nm band pass filter (Hamamatsu). A UV-light guide (A10014-50-0110) mounted at the entrance of a modified operando IR cell was used to establish a homogeneous irradiation, (as shown in Scheme S1 in supplementary information). N.B.: under polychromatic irradiation (reference 13), TiO 2 presents a higher activity and selectivity than here under monochromatic irradiation. Under the same irradiation conditions, TiO 2 -25 presented the same activity here as in our previous work. The methanol conversion and CO 2 -selectivity were calculated as reported in our previous work. [START_REF] El-Roz | [END_REF]

Results and discussion

photocatalytic activity and selectivity of TiO 2 -L and TiO 2 -P25 and effect of the methanol concentration

In order to compare photocatalytic activity and selectivity for TiO 2 -L and TiO 2 -P25, the photooxidation of methanol was performed under the same conditions for different methanol concentrations ([MeOH]). The concentration of methanol in the gas was measured using the surface area of the MeOH-IR band at 1090-950 cm -1 and the MeOH-MS signal at m/z=29 (a calibration curve is presented in Figure S-2). Selectivity for CO 2 (selectivity of the reaction for a complete methanol mineralization) was determined using the IR band area at 2395-2182 cm -1 and/or the MS signal at m/z=44. Figure 1 presents the evolution of methanol conversion and CO 2 -selectivity versus MeOH concentration. For each concentration, methanol conversion and CO 2 -selectivity were calculated after the stabilization of the gas phase IR spectra and MS signals, i.e. 30min to 1h irradiation time after each flow modification (Figure S-3). As reported in our previous work, 13 the methanol concentration can influence significantly the activity and the selectivity of the reaction. For a concentration lower than 600 ppm, TiO 2 -L shows a higher activity and similar CO 2 -selectivity than TiO 2 -P25 (Figure 1). In this range of concentration, the CO 2 -selectivity is slightly affected for both TiO 2 -L and TiO 2 -P25. For a concentration higher than 600 ppm, the methanol conversion on TiO 2 -L is lower than on TiO 2 -P25. An important decrease in the CO 2 -selectivity could be also observed, less pronounced on TiO 2 -L than on TiO 2 -P25. New IR bands at 1755 cm -1 and 1890 cm -1 , assigned respectively to ν(C=O) and ν(C-O) vibration modes of methyl formate [START_REF] El-Roz | [END_REF] are observed in the reaction gas phase (Figure 2). The increase of these bands (and the m/z=60 MS signal) with methanol concentration explains the decrease of CO 2 -selectivity. The maximum amount of converted methanol (Table S1 in supplementary information) is about 700 ppm/min (with ~55% CO 2 -selectivity) for TiO 2 -L and about 800 ppm/min for TiO 2 -P25 (with 50% CO 2selectivity). Therefore, the maximum amount of "mineralized" methanol on both TiO 2 -L and TiO 2 -P25 is about 400 ppm/min (under the experiment conditions described in the experimental part). These results show that the increase in methanol concentration promotes the formation of methylformate by increasing surface coverage by methanol.

The turnover frequency (TOF) is important for comparing heterogeneous catalysts. 22 As in enzymatic or homogeneous catalysis, the turnover frequency corresponds to the number of molecules converted per second and per active site (or per catalytic molecule). [START_REF] Boudart | Cinétique des réactions en catalyse hétérogène[END_REF] In heterogeneous catalysis, TOF is often more difficult to determine and the number of active sites can be largely unknown and it is generally overestimated, considering all the theoretically calculated sites on the sample as accessible and active. In the case of solid/gas photocatalysis it could be even worse: the actual operating surface is not known since some parts of photocatalyst particles are not illuminated (inhomogeneous irradiation) as a consequence of internal shading. 22,[START_REF] Parmon | [END_REF]25 In our case, the use of the photocatalyst under the form of a thin pellet (~40 µm) allows a homogenous, reproducible and total illumination of the photocatalyst. On the other hand, the possibility of internal shading of the TiO 2 particles does not preclude the comparison between two photocatalysts where the effect will be same.

Consequently, a more reliable estimation of the TOF will be used in this study for an additional comparison of TiO 2 -L and TiO 2 -P25. Practically, we used the surface density of titanol groups Ti-OH (equal to 5×10 18 OH/m 2 or 5 OH/nm 2 , 26 ) as the upper limit for the number of active sites n sites . The methanol conversion rate (V MeOH ) corresponds to the amount of methanol converted (in ml) per gram of photocatalyst (g -1 cat ) per minute of irradiation time (min -1 ). The results for TOF and V MeOH are presented in Figure 3 and Table S-1. Conversion rates are similar for both photocatalysts, but since TiO 2 -L has a higher specific surface area (Table 1), the TOF for TiO 2 -L is 2 to 3 times lower than for TiO 2 -P25. This means that the active sites are less efficient on TiO 2 -L than on TiO 2 -P25 or that only a fraction of the sites are accessible or active. In the last case, the use of the theoretically estimated number of active sites is not acceptable.

Operando IR in the photocatalytic reactor shed some more light on these reactions. During UV irradiation, new bands appeared (Figures 4 andS-4), assigned to mono and bidentate formate species adsorbed on the catalyst surface. [START_REF] El-Roz | [END_REF]13,27,28 These species are commonly described as intermediates in the photooxidation of alcohols. [START_REF] El-Roz | [END_REF]15,16,[29][30][31][32][33][34] We observed different vibration bands for bidentate formates on TiO 2 -L (maxima at 1600, 1373 and 1356 cm -1 ) and on TiO 2 -P25 (maxima at 1570, 1379, 1362 cm -1 ), probably because of a difference in the nature of the formation/adsorption site. In addition, the IR intensity of these bands is much higher on TiO 2 -L than on TiO 2 -P25 (Figure 4). This could be due to (i) the higher specific surface of TiO 2 -L (~1.6 times higher than TiO 2 -P25) leading to a higher formation of formate species and/or to (ii) a stronger adsorption of bidentate formate species on TiO 2 -L than on TiO 2 -P25, thus reducing their transformation.

The increase of methanol concentration led to a simultaneous increase of some corresponding IR band intensities, more important on TiO 2 -L than on TiO 2 -P25, with a maximum at 800 ppm (Figure 5A and5B). The same catalytic activities were observed on both photocatalysts when working in reverse concentration order, from higher to lower MeOH concentrations, which rules out surface deactivation at high methanol concentration.

These results raise the question about the alleged role of intermediates for the formates on TiO 2 surface.

Influence of temperature on the activity of TiO 2 -L

The influence of temperature on the activity of TiO 2 -P25 has already been discussed (under polychromatic irradiation) in a previous work [START_REF] El-Roz | [END_REF] . Results for TiO 2 -L are reported in Figure 6.

Both activity and selectivity increase with temperature, like on TiO 2 -P25. [START_REF] El-Roz | [END_REF] For T > 75°C, methanol conversion is higher than 90% (vs. ~55% at RT), with complete mineralization (vs.

60% CO 2 -selectivity at RT). Following the formate species on TiO 2 -L with temperature is easy due to the high intensity of the corresponding IR bands (Figure 7). An important decrease is observed with increasing temperature, with a maximum between 75°C and 100°C.

This apparent decrease of surface formates with increasing temperature (and activity) already raises the question about the role of the formates in the photocatalytic oxidation of methanol (and alcohols) and of their true intermediate nature. In addition, stationary IR bands could also be observed even at high temperature, showing the formation and presence of stable species on the photocatalyst during photooxidation.

Role of formate species in methanol photooxidation: a complementary study by SSITKA

SSITKA is a methodology for obtaining transient conditions while remaining under the required chemical and/or kinetic steady state environment for a given reaction. It is already used in some operando studies for a better understanding or for clarifying the mechanism of a catalytic reaction, and sometimes to determine the activation energy. [35][36][37][38][39] In our case, SSITKA experiments were performed to clarify the role of formate species in methanol photooxidation.

Two reaction flows in our operando system have been used, each of them equipped with a saturator containing either natural or 13 C enriched methanol (Scheme S1). A four ways valve allows instantaneous switching from one flow to the other under the same experimental conditions (flow: 25 cm 3 /min, concentration: 1200 ppm, temperature: RT, UV irradiation intensity: I 0(366) ~11 mW/cm 2 ; λ = 366 nm and air composition: 20% oxygen in Ar), and the reaction remains chemically identical in both cases. The chosen methanol concentration led to incomplete conversion and partial mineralization of methanol (Figure 1), which allowed following the isotopic exchange of all species including reactants with the on-line gas analyses. The switch from [START_REF] El-Roz | [END_REF] C to 13 C-substituted methanol was done during the photooxidation reaction and the switching time was used as t = 0. The results presented here were obtained on TiO 2 -P25, and those with TiO 2 -L are presented in supplementary information.

Starting from the chemical steady state (t = 0), the reaction flow was switched from natural to labeled methanol. Consequently, the bands of adsorbed 13 C-methoxy (1090 cm -1 ) and 13 C-formates (1340 and 1515 cm -1 ) species progressively replaced those of the unlabeled species (Figure 8AI), giving rise to several isosbestic points. On the time traces (Figure 9A), surface methoxy groups is coherent with the kinetics of the changes in the reactor exhaust, but formate species are clearly reacting too slowly compared to the speed of CO 2 and methyl formate productions. These results show that the majority of formate species, formed on the TiO 2 surface, are spectators. This conclusion is in agreement with the relatively lower activity founded on TiO 2 -L, at high methanol concentration, despite the higher amount of formate species observed on the surface of this material (compared to TiO 2 -P25). In addition adsorbed methoxy, which presents a similar isotopic exchange kinetic than that of final products, could rather be an effective intermediate in methanol photooxidation.

However, even after a complete replacement of 13 CH 3 OH by [START_REF] El-Roz | [END_REF] CH 3 OH in the gas phase (after t = 8 min, Figure S-6), traces of 12 CO 2 could still be observed at t = 360 min, due to the slow decomposition of unlabeled surface formates. Two reaction pathways thus exist on the surface for the photocatalytic oxidation of methanol: a fast (and major) one, and a side-path, via the slow decomposition of surface formates. The fast reaction could go via some of the formates (could be the formates formed on the surface exposed directly to the light) or via surface carbonates, but no carbonate bands were detected. A slower rate for the isotopic exchange of surface formates was observed on TiO 2 -L (crossing point at t >75 min vs. 18 min for TiO 2 -P25). Switching to pure air, with zero methanol concentration, under UV irradiation, does not change the rate for formates removal from the surface. In addition, persistent IR bands were detected on the photocatalysts after isotopic exchange, due to stable formates formed on the surface after irradiation (in agreement with the observed influence of temperature).

Infrared spectra for TiOH groups on the surface during the photocatalytic process give information on the possible sites for the formation of weakly or not active formate species (Figure 10). The evolution of the IR spectra of TiO 2 in real time is presented in Figure S-7.

Methanol adsorption led to the perturbation of surface TiOH groups and to the total disappearing of the IR bands at 3720 cm -1 and 3690 cm -1 assigned to the vibration bands of Figure 10B shows the linear relationship between the IR-bands of surface formate species and that of Ti(III)OH.

This shows the role of TiOH functions in the stabilization of the formate on the photocatalyst surface. The higher band intensity for formates on TiO 2 -L is thus due to a larger amount of TiOH sites on the surface of the solid. It should be noted that the higher absorption in the visible for TiO 2 -L is linked to the presence of oxygen vacancies and/or of Ti(III)-OH, resulting in an absorbance red-shift (Table 1).

Conclusion

The new operando-IR technique presented here shows high performance to highlight the activity of the photocatalyst, the selectivity of the reaction and the role of the surface species in the reaction mechanism. However, in situ identification of the species formed on the photocatalyst surface is not enough to determine their role in the reaction. We used the new technique to study the activity and selectivity of a new photocatalyst (TiO 2 -L), with methanol photooxidation as model reaction for air purification from VOCs. TiO 2 -P25 (Evonik-Degussa)

was used as reference under the same reaction conditions. TiO 2 -L presents a higher activity at low methanol concentration and higher selectivity at high methanol concentration compared to TiO 2 -P25. The TOF of the reaction were calculated using a theoretical number of active site in TiO 2 anatase. It is 2 to 3 times lower in the case of TiO 2 -L than for TiO 2 -P25. This was assigned to an overestimation of the number of active sites in TiO 2 -L and showed that the real number is lower than estimated. A similar methanol conversion rate (ml g TiO2 -1 min -1 ) was found for both photocatalysts. The photooxidation activity and CO 2 -selectivity of TiO 2 increase with temperature. Formate species are formed and adsorbed in higher amounts on points between methoxy and final products were observed on both photocatalysts, suggesting methoxy as intermediates in methanol photooxidation. Operando IR is thus demonstrated as an important technique in photocatalysis, unveiling more information than other sometimes more expensive techniques. In the future, operando IR will be coupled with SSITKA using different methanol isotopes (CH 3 18 OH and CD 3 OH) in order to determine the real intermediates and global mechanism in methanol photooxidation.

Tables.

Table 1. Characteristic of TiO 2 -L and TiO 2 -P25 photocatalysts used in this work. S BET : BET surface; V meso : mesoporous volume; λ: wave lengths of the photocatalyst absorbance.

Photocatalyst

Figures caption

Figure 1: influence of methanol concentration on methanol conversion and CO 2 -selectivity for methanol photooxidation reaction using TiO 2 -L (square) and TiO 2 -P25 (circle) photocatalysts. (20% O 2 /Ar vol.%; flow = 25 cm 3 /min; RT; I 0(366) ~10 mW/cm 2 ; λ = 366 nm). 1.0x10 1.2x10 -7

Figures.

1.4x10 -7

1.6x10 -7

1.8x10 -7

2.0x10 [START_REF] El-Roz | [END_REF] CO 2 (m/z=44), and 13 CO 2 (m/z=45) during a SSITKA experiment of methanol photooxidation.(same conditions as mentioned in Figure 9).

  crossing points are observed at t ~5 min and t ~18 min (> 75min for TiO 2 -L; Figure S-5) for adsorbed methoxy and formate species respectively. The on-line analyses of the exhaust gases show similar isosbestic and crossing points (at t~3.7) for methanol, carbon dioxide and carbonyl compounds (methyl formate with trace of formaldehyde and/or formic acid) (Figures 8B-I, 9B, S-5). Similar results were obtained on TiO 2 -L (Figure S-4). The kinetic behavior of

  Ti(III)-OH and Ti(IV)-OH, respectively (Figure S-4). After irradiation, the Ti(IV)OH band was recovered while the Ti(III)OH band remained perturbed (Figure S-8).

TiO 2 -

 2 L than on TiO 2 -P25. A 40 cm -1 shift could be also observed between IR spectra of TiO 2 -P25 and TiO 2 -L surfaces. SSITKA experiments allowed establishing relationships between surface species and final products. Formates formed on TiO 2 -L are more stable than on TiO 2 -P25. Most of formates observed by IR are spectator species. A relationship between the formation of formate and the disappearing of Ti(III)-OH was also observed, showing the role of defects and TiOH sites in the stabilization of low active formate on the surface. Isosbestic

  PhotocatalystCrystallinity Morphology

Figure 2 :

 2 Figure 2: Original IR spectra of the gas phase during the photocatalytic reaction at RT, at different methanol concentrations. "a" corresponds to the IR spectrum of 1000 ppm of methanol before photooxidation.

Figure 3 :

 3 Figure 3: Influence of methanol concentration on turnover frequency (TOF; close symbol) and on methanol conversion rate (in ml per gram of photocatalyst per minutes; open symbol)for the methanol photooxidation reaction using TiO 2 -P25 (square) and TiO 2 -L (circle) as photocatalysts. (20%O 2 /Ar vol.%; flow=25 cm 3 /min; RT; I 0(366) ~10 mW/cm 2 ; λ =366 nm).

Figure 4 :Figure 5 :

 45 Figure 4: IR spectra of TiO 2 -L (A) and TiO 2 -P25 (B) before (a) and after (b) 60 minutes of UV irradiation . (1200ppm of methanol in synthetic air; flow=25 cm 3 /min; RT; I 0(366) ~10 mW/cm 2 ; λ =366 nm)

Figure 6 :

 6 Figure6: A) Evolution of the gas phase IR spectra vs reactor temperature for the methanol photooxidation reaction using TiO 2 -L as photocatalyst. B) Evolution of methanol conversion (calculated using the IR band at 1090-950 cm -1 ) and the IR band areas of CO 2 (2395-2182 cm -1 ) and carbonyl species (R 2 C=O; 1810-1717 cm -1 ) at different temperatures. ([MeOH] = 1200ppm; I 0(366) ~10mW/cm 2 ; λ=366nm; flow= 25 cm 3 /min; heating rate = 1°C/min and stabilization for ~1 h/temperature step).

Figure 7 :

 7 Figure 7: A) Evolution of the IR band area of formate species at 1605cm -1 and their derivative versus the temperature (d(IR band area)/dT) using TiO 2 -L as photocatalyst.Figure

Figure

(

  B) corresponds to the original IR spectra of TiO 2 -L surface at different temperatures of methanol photooxidation.

Figure 8 :

 8 Figure 8: IR spectra of TiO 2 -P25 (A) and of the reaction gas phase (B) during a SSITKA experiment for which an initial flow of 1200 ppm of 12 CH 3 OH, 20% of oxygen diluted in Ar (total flow = 25 cm 3 min -1 ) was switched to a similar but labeled ( 13 CH 3 OH) flow (the spectrum recorded at t=0 was used as background). Figures (AII) and (BII) correspond to the original IR spectra of TiO 2 -P25 and of the reaction gas phase, respectively, during the SSITKA experiment at t= 0 and 120 min.

Figure 9 :

 9 Figure 9: Evolution of the IR band intensities for adsorbed species on TiO 2 -P25 (A) and for final products detected in the gas phase (B) vs. irradiation time.

Figure 10 :

 10 Figure 10: (A) Evolution of the IR band of Ti(III)OH at 3690 cm -1 and of formate species at 1602 cm -1 during methanol photooxidation. (B) Evolution of the formate species IR-band vs Ti(III)OH IR-band during methanol photooxidation.

  Figure 2

Figure S- 3 .Figure S- 4 .

 34 Figure S-3. Evolution of the methanol conversion (calculated using m/z=29 MS signal), the MS signal of CO 2 (m/z=44) and of H 2 O (m/z=18) versus different methanol concentrations and irradiation time.

Figure S- 5 .Figure S- 6 .

 56 Figure S-5. IR spectra of TiO 2 -L (A) and of the reaction gas phase (B) recorded at 25°C during a SSITKA experiment for which an initial flow made of 1200 ppm of 12 CH 3 OH, 20% of oxygen diluted in Ar (total flow = 25 cm 3 min -1 ) was switched to a similar labeled ( 13 CH 3 OH) flow (Spectra subtracted from the spectrum recorded at t = 0, which corresponds to the switch moment of 12 CH 3 OH/ 13 CH 3 OH). Figures (AII) and (BII) corresponds to the evolution of the IR band intensities of the species adsorbed on the photocatalyst surface and to those of final products detected in the gas phase, respectively, vs. irradiation time.

Figure S- 7 :Figure S- 8 :

 78 Figure S-7: IR spectra of the methanol photooxidation gas phase recorded at different times of SSITKA experiment.

Table S - 1 .

 S1 Data obtained in the photooxidation of different methanol concentrations using TiO 2 -P25 and TiO 2 -L photocatalysts.

				TiO 2 -P25					TiO 2 -L
	[MeOH]	Conv.	CO2-	TOF	VMeOH	Conv.	CO2-	TOF	VMeOH
			selectivity					selectivity
	(ppm)	(%)	(%)	(molecules/s/active		(ml g -	(%)		(molecules/s/active	(ml g -
				site)	1	cat min -		(%)	site)	1	cat min -
						1 )				1 )
	250	87	99	0.24		0.27	97	95	0.17	0.30
	350	87	99	0.34		0.38	96	90	0.23	0.42
	500	86	90	0.49		0.54	90	88	0.31	0.56
	600	85	86	0.57		0.64	89	77	0.37	0.67
	700	85	80	0.67		0.74	85	72	0.41	0.74
	800	84	74	0.76		0.84	79	68	0.43	0.79
	900	80	63	0.85		0.9	76	60	0.48	0.85
	1000	81	50	0.91		1.0	71	57	0.49	0.89
	1200	73	39	0.84		1.1	54	57	0.45	0.81

Supplementary information

Flytzani-Stephanopoulos, M. J. Catal. 2007, 247, 277-287.

39 Wang, J.; Kispersky, V. F.; Delgass, W. N.; Ribeiro, F. H. J. Catal. 2012, 289, 171-178.

TOC

Evolution of IR spectra of TiO 2 surface and reaction gas phase after CH 3 OH/ 13 CH 3 OH isotopic exchange during methanol photooxidation (t=0 correspond to exchange moment).


M Dahoumane
email: mokrane.dahoumane@ires.in2p3.fr

J Bouvier

Daniel Dzahini

L Gallin-Martel

E Lagorio

J-Y Y Hostachy

Y Hu

L Gallin Martel

A very

de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

A very low power and low signal 5 bit 50 M samples/s double sampling pipelined ADC for Monolithic Active Pixel Sensors in high energy physics and biomedical imaging applications

I. INTRODUCTION

MOS Monolithic Active Pixel Sensors (MAPS) are charged particle tracking devices, integrating on the same silicon substrate radiation sensitive detector elements with its front-end readout electronics. Fabricated in standard CMOS technology, MAPS offer well known advantages like low power, low cost fabrication, high spatial resolution, flexibility, radiation hardness, compactness, random access and fast readout. Compared to the existing detectors like Charge coupled Devices (CCD) or Hybrid pixel Detectors (HPD), MAPS are an attractive alternative to fulfill the requirements of Vertex Detector in the future high energy physics and biomedical imaging applications. However, the use of MAPS in different applications will strongly depend on a successful implementation of an on-chip read-out electronics. This is not a trivial task because of different constraints on the A/D converter design. The pixel signal is very low in the range of millivolts, which are the same order of magnitude as transistor threshold variations of a CMOS process. In order to obtain a high speed and a pixel level integration, the sampling rate is set at 10 M samples/s. The consumption of pixel column ADC must be less than 500 µW. The layout has to be adjusted to the small pixel pitch (20 µm × 20 µm).

In this paper, a 50 M samples/s double sampling analog to digital converter is described. It is designed according to the requirements of pixel arrays developed at IPHC-Strasbourg in collaboration with DAPNIA-Saclay, in perspective of the Linear Collider vertex detector [START_REF] Winter | A swift and slim flavour tagger exploiting the CMOS sensor technology[END_REF], [START_REF] Li | CMOS sensors for the vertex detector of the future international linear collider[END_REF]. Figure 1 shows the global architecture of the planned MAPS chip comprising the pixel array with its associated read-out electronics and A/D conversion stages. These MAPS are currently being developed and characterized at IPHC/Strasbourg in collaboration with CEA/Saclay and manufactured by TSMC through MOSIS [START_REF] Degerli | A fast monolithic active pixel sensor with pixel-level reset noise suppression and binary outputs for charged particle detection[END_REF], [START_REF] Fourches | Fast neutron irradiation of Monolithic Active Pixel Sensors dedicated to particle detection[END_REF]. They are based on DC pixel architecture which comprises in-situ a first conditioning micro-circuit. Figure 2 shows a structure of an active pixel. When a particle (electron, photon…) traverses the pixel, it generates electron-hole pairs C in the sensitive volume. The electrons are then collected by the n-well. The charge is converted to voltage by the "pn" junction. The signal at the analog output of the pixel is the difference between a reference level (calibration) and the readout signal (read). This leads to the signal extraction and a reduction of the output pedestals (offsets). The pixel columns are read in parallel with a frequency in excess of 10 kHz. Thus, the pixel read out frequency is 10 MHz; this depends on the number of lines of the pixel matrix [START_REF] Degerli | A fast monolithic active pixel sensor with pixel-level reset noise suppression and binary outputs for charged particle detection[END_REF]. Each column is presently followed by a discriminator, which will be replaced in future by an ADC. In our application, each ADC converts 4 columns with an equivalent frequency of 10 M samples/s each column. The pixel column width amounts to 25 µm at present, but it should become 20 µm in the next prototypes.

II. DESIGN ARCHITECTURE

A Small size, a low power, a high speed and a high accuracy are the criteria which determine the ADC architecture to be chosen. A pipelined architecture provides a good deal between all these requirements. An overview block diagram of a 5 bit pipelined ADC is shown in figure 3 [5], [START_REF] Cho | A 10-bit, 20-MS/s, 35-mW pipeline A/D converter[END_REF] [7], [START_REF] Bouvier | A Low Power and low signal 5bit 25MS/s Pipelined ADC for Monolithic Active Pixel Sensors[END_REF]. The scheme includes 2 sample and hold circuits which compose the first stage of the design. A sample and hold amplifier (SHA) stage is needed to maintain the signal stable during the conversion time. The pixel common mode voltage fluctuation, the small value of the Least Significant Bit (LSB ~1mV) and the offset make the design of this first stage of the converter very critical. The SHA stage samples, holds and amplifies by 4 the analog input signal. It is followed by three successive 1.5 bit pipelined stages and a 2 bit flash stage. Each pipelined stage produces a digital estimate of an incoming held signal, then converts this estimate back to the analog, subtracts the result from the held input. This residue is then amplified before being transferred to the next stage. The last stage, which is a 2 bit flash ADC, determines the LSB. The successive digital results from the ADC stages are appropriately delayed throughout a bit alignment network. Then a digital error correction stage is added to leave room for the comparator offset correction. Therefore, the comparator constraints are relaxed and the power consumption is reduced.

The following sections describe each stage of this converter and some testing results will be presented.

III. THE SAMPLE AND HOLD AMPLIFIER CIRCUIT

A charge redistribution non-inverting architecture is used to design this stage [START_REF] Johns | Analog integrated circuit design[END_REF]. Figure 4 illustrates the sampling phase (phi2 is ON). The intensity signal (Vin+) is stored onto the set of 4 sampling capacitors (C37...C40) and the common mode signal (Vin-) is stored onto the capacitors (C33…C36). Then during the HOLD phase (phi1 is ON), the charge is transferred to the feedback capacitor C23. This results to amplification by 4 of the differential signal between the reference (dark level) and the intensity level. Each capacitor unit in this scheme is 107 fF. These capacitor values are chosen in function of the surface limitation and kT/C noise factor. SHA1 and SHA2, as shown in figure 3, sample in opposite clock phases at 25 MHz frequency. So, the following ADC has a sampling rate of 50 MS/s which is performed by using the double sampling technique.

The particular requirements of the Vertex detector application make the design of the circuit very critical. The restrictions in terms of power consumption and area make this design sensitive to different offset sources:

1. OTA input offset 2. Switch charge injection offset 3. Input common mode voltage fluctuation The SHA stage has already been integrated and tested in our previous designs. The actual SHA is an improved version [START_REF] Bouvier | A Low Power and low signal 5bit 25MS/s Pipelined ADC for Monolithic Active Pixel Sensors[END_REF], [START_REF] Dahoumane | A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors[END_REF].

A. Design of the amplifier

To design a high performance SHA, it is imperative to have an operational transconductance amplifier (OTA) of high gainband-width (GBW) and fast settling behavior. Telescopic cascode architecture of the OTA is selected and implemented. The design of the OTA is shown in figure 5 [START_REF] Dzahini | Auto-zero stabilized CMOS amplifiers for very low voltage or current offset[END_REF]. This amplifier is used in both SHA stage and pipelined stages.

The current mirror load is a so called "wide swing cascode" [START_REF] Lewis | 10-b 20-Msample/s analog-to-digital converter[END_REF]. It improves the dynamic range better than a basic cascode and makes the design robust for low voltage design. Bode diagram simulation results show that the amplifier achieves a 48.5 dB open loop gain and 160 MHz unity gain frequency with 75° phase margin. These results are obtained with a 1 pF load capacitance and 260 µW power dissipation at 2 V power supply.

A highest accuracy is needed in the first stage in order to achieve the required resolution of the ADC which follows. Keeping in mind this characteristics, the successive stages of the pipelined ADC use the same OTA architecture, but consume decreasingly (by a factor of 2) through the successive stages. The double sampling technique consists of sharing the active components between two adjacent ADC channels. In this section, each block of the design will be detailed. The double sampling design keys will be given. To have a better insight into the double sampling principle, traditional pipelined architecture is firstly described. The maximum comparator offset value tolerated is Vref/8 = ± 16 mV. Vref is the full range dynamic of this converter (Vref = 128 mV). A simplified schematic of the comparator is given in figure 8. It consists of a low gain and low offset differential preamplifier followed by a latched folded cascode comparator to optimize the performance between the speed and the power consumption [START_REF] Dzahini | A high speed low power CMOS comparator[END_REF]. The residue transfer curve is obtained by a precise multiplier sample and hold switched capacitor circuit shown in figure 9. The incoming signal is sampled during phase "ø1". It is amplified by charge redistribution during phase "ø2". During the amplification phase, the bottom plate of the sampling capacitor (Cs) is connected to a reference voltage Vrefi which will be subtracted from the amplified signal. The residue values from this operation are transmitted to the next stage. The value for Vrefi is respectively 0, Vref/2 or Vref depending on the comparator outputs (see figure 6). Vref is the dynamic range of the converter, with reference to the virtual ground.

A. 1.5 bit pipelined stage implementation

B. Double sampling stage design

In the final design of the MAPS, at the bottom of each pixel column of the matrix there will be an ADC. So, the ADCs are disposed in parallel (figure 1). This feature can be exploited in the double sampling architecture [START_REF] Nagaraj | A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers[END_REF].

The property of the successive ADC stages working in opposite clock phases can be exploited by sharing the operational amplifier, the comparators and the all the logic part between two parallel component ADCs. This approach uses the well known double-sampling concept of switched capacitor circuits. By using double-sampling, the equivalent sampling rate is doubled, but still the power dissipation remains almost the same as for an ADC having traditional single sampled pipeline stages with a half sample rate. The surface is reduced by ~ 40%. In contrast, the complexity of the pipeline stage is increased and more clock signals with different phases are needed.

Scheme of the double sampling multiplying D/A converter is shown in figure 10. The capacitors of two parallel channels working on opposite clock phases share the same amplifier. Due to the very low incoming signal, each ADC channel has its own SHA stage. While the "pipeline1" samples the Vin1 signal onto the Cs and Cf capacitors independently of the amplifier, the "pipeline2" switches to the amplification phase.

Two important side effects are caused by the amplifier sharing. First, the amplifier load capacitance is increased and affects its bandwidth. Second, the amplifier input offset is never reset; this can be tolerated by an adequate amplifier open loop DC-gain. The second one is very critical in this design because of the non differential architecture used here, and thereby no symmetric compensation is possible. Although algorithms of offset correction are available [START_REF] Conroy | An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS[END_REF], but they are both area and power consuming. In this design, an auxiliary input is added to adjust manually the level of the common mode for each pipeline stage.

C. Design limitations

The conversion speed is limited by the settling time of the operational amplifier used in the S/H circuits. The use of double sampling and parallelism introduces several limitations traduced by errors. These errors include offsets, gain and timing mismatches of the parallel channels. In this design the threshold and reference voltages are generated out side of the prototype circuit. The large number of pipeline stages using the common reference voltages increases the capacitive load in the reference nodes. To guarantee that the reference does not limit the settling speed, its output impedance has to be very low (couple of tens of ohms).

V. TESTING RESULTS

A prototype has been designed in a CMOS 0.35µm process from Austria Micro System. It includes 16 channels of the described double sampling ADC. A photo of the chip is shown in figure 11. The dimensions of one full channel including the sample & hold amplifier stage are 80 µm × 1.4 mm. One may notice also that the surface occupied by the first stage (SHA) is about 1/4 of the full channel. The circuit has been tested successfully at 50 MHz; doublesampling concept is taken in count. In simulation, the ADC power dissipation at 2 V power supply is 0.69 mW this corresponds to the consumption of 2 pixel columns ADCs. But in the test, in order to compensate offsets, the power supply is set to 2.95 V. and consequently, the power dissipation is increased.

In figure 12 is shown the fast Fourier transform (FFT) spectrum for a 1 MHz sine wave input signal. The ADC achieves a dynamic range (SFDR) of 29 dB. The dynamic study is done with Lab View signal analysis tools. The table 1 shows a summary of measured dynamic parameters. For this test, the input signal is a sine wave with a peak-topeak amplitude close to the ADC full-scale range. Then a statistical analysis method is applied to the output data. A maximum DNL error of 0.7 LSB and a maximum INL error of 1.2 LSB have been measured using a cumulative histogram method [START_REF] Dallet | Dynamic Characterization of Analogue-to-Digital Converters[END_REF]. The DNL refers to the irregularity in the width of the quantization, while the INL quantifies the displacement of the transition levels from their nominal positions. Even if the INL and DNL errors are slightly superior to ½ LSB, no missing code is observed on the histogram of ADC out put code (figure 14). Theoretically to assure no missing code, the DNL and INL errors have to be less than ½ LSB [START_REF]INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs)", Maxim > Designer's Library > App Notes > A[END_REF]. For the next ILC experiment, the beam duty cycle will be very low (~1%). It is therefore worthy to switch on the analog part of the circuit only when used, thus making the total power dissipation directly proportional to the beam duty cycle. This circuit includes such fast and efficient "power ON" capability. The analog bias settling and ADC wakening time result is given in figure 15. This bias pulsing circuit has already been integrated and tested in our precedent version of ADC [START_REF] Bouvier | A Low Power and low signal 5bit 25MS/s Pipelined ADC for Monolithic Active Pixel Sensors[END_REF], [START_REF] Dahoumane | A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors[END_REF]. From the falling edge of a pulsing clock, the ADC begin to convert properly only after 14 µs. In the standby idle mode (pulsing clock at high level), the full analog part of the converter is switched OFF and the analog power dissipation is reduced to a ratio better than 1/1000. The characteristics of the design and some testing results are summarized in the table 2.

M

  . Dahoumane, J. Bouvier, D. Dzahini, L. Gallin Martel, E. Lagorio, J-Y. Hostachy and Y. Hu Abstract-The use of CMOS Monolithic Active Pixel Sensors (MAPS) for high precision minimum ionizing particle tracking has been proven to be a viable and powerful novel experimental technique. Possible applications will strongly depend on a successful implementation of on-chip hit recognition and sparsification schemes. For this aim, a 5 bit very low power and low level signal analog to digital converter (ADC) using a double sampling switched capacitor technique has been implemented in 0.35µm CMOS technology. A non-resetting sample and hold stage is integrated. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of three successive 1.5 bit pipeline stages followed by a 2 bit flash stage. The prototype consists of 16 ADC double-channels; each one is sampling at 50 MS/s and dissipates only 1.38 mW at 2 V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1 µs. The size of the ADC is 80 µm × 1.4 mm. This corresponds to the pitch of 4 pixel columns in which each one is 20 µm wide and can be easily integrated in the MAPS.

Fig. 1 .

 1 Fig. 1. Global architecture of MAPS and integrated readout electronics.

Fig. 2 .

 2 Fig. 2. Active pixel principle.

Fig. 3 .

 3 Fig. 3. General block diagram of a 5 bit pipelined converter.

Fig. 4 .

 4 Fig. 4. Sample and hold amplifier scheme.

Fig. 5 .

 5 Fig. 5. A wide swing telescopic OTA.

Figure 6

 6 Figure 6 illustrates the implementation of a 1.5 bit pipeline stage. The A/D block consists of two comparators. The D/A conversion, subtraction, amplification, and S/H functions are performed by a switched capacitor circuit with a resolution of 1.5 bit per stage and an interstage gain of 2. Hence, the transfer function of this stage is Vs = 2×Vin -Vref i where Vref i are the reference voltages selected by the DAC depending on the sub-ADC output code (b1b0).

Fig. 6 .

 6 Fig. 6. Block diagram of 1.5 bit pipelined stage. The characteristics of the transfer function for a 1.5 bit stage is shown in figure 7. The expression "1.5 bit" is used to indicate that only 3 combinations of the 4 are acceptable for the output codes. The (1, 1) code is avoided, thereby the interstage amplifier should not saturate and this leaves room for the digital error correction.

Fig. 7 .

 7 Fig. 7. A 1.5 bit residue transfer curve

Fig. 8 .

 8 Fig. 8. Simplified comparator scheme.

Fig. 9 .

 9 Fig. 9. The switched capacitor multiplier sample and hold scheme.

Fig. 10 .

 10 Fig. 10. A double sampling principle scheme.

Fig. 11 .

 11 Fig. 11. Photo of the realized prototype.

Fig. 12 .

 12 Fig. 12. FFT spectrum for a 1 MHz sine wave.

Fig. 13 .

 13 Fig. 13. DNL and INL results.

Fig. 14 .

 14 Fig. 14. ADC output histogram.

Fig. 15 .

 15 Fig. 15. Analog bias settling time and full ADC wakening results.

  VI. CONCLUSION For Monolithic active pixel sensors, a 5 bit 50 MHz doublesampling A/D converter has been implemented in 0.35 µm CMOS technology. It achieves 29 dB of SFDR with a typical DC dissipation of 1.38 mW per 4 pixel columns; this corresponds to 0.35 mW/column. It is designed in perspective of the next linear collider (ILC). The full ADC includes an amplification sample and hold stage. A 1.5 bit/stage architecture is used for the converter in a non differential configuration. The size of one channel layout is 80 µm × 1.4 mm. A very efficient fast power pulsing is integrated with this circuit to reduce the total DC power dissipation according to the beam low duty cycle. Due to its high performances, this ADC can be widely used in high energy physics and biomedical imaging applications.

TABLE I I

 I ADC PERFORMANCE SUMMARY

ACKNOWLEDGMENT

We would thank Marc Winter, Christine Hu, Isabelle Valin, Claude Colledani, Frederic Morel and all CMOS group members from the IPHC / IN2P3 laboratory in Strasbourg for many discussions on MAPS design constraints. We thank also electronic group and all the staff of LPSC/IN2P3 laboratory in Grenoble.


Qunshan Shen

Guillaume Martinez

Hongbin Liu

Julie Beurois

Huan Wu

Amir Amiri-Yekta

Dan Liang

Zine-Eddine Kherraf

Marie Bidart

Caroline Cazin

Bi-allelic truncating variants in CFAP206 cause male infertility in human and mouse

ou non, émanant des établissements d'enseignement et de recherche


Roman Bourgade

Clément Ballabriga

Hugues Cassé

Christine Rochange

Pascal Sainrat

Accurate analysis of memory latencies for WCET estimation

est destinée au dépôt

Introduction

As part of the design of a critical system, the Worst-Case Execution Time (WCET) of all the tasks with hard real-time constraints must be evaluated. The often huge number of possible execution paths in a task (related to the large number of possible input values) makes it impossible to determine the longest execution time by measurements if the WCET must be absolutely guaranteed as safe. This is why techniques based on static code analysis that allow deriving safe WCET upper bounds have been proposed [START_REF] Engblom | Towards Industry-Strength Worst Case Execution Time Analysis[END_REF]. Three steps are required: (1) information about the control flow must be provided by the user (through code annotations [START_REF] Kirner | WCET Analysis: The Annotation Language Challenge[END_REF]) or extracted automatically from the code [START_REF] Altenbernd | On the false path problem in hard realtime programs[END_REF][5] [START_REF] Ermedahl | Loop Bound Analysis based on a Combination of Program Slicing, Abstract Interpretation, and Invariant Analysis[END_REF] [START_REF] Holsti | Analysing Switch-Case Tables by Partial Evaluation[END_REF]; [START_REF] Altenbernd | On the false path problem in hard realtime programs[END_REF] the execution times of sequential parts of code (basic blocks) must be determined taking into account the parameters of the target hardware [START_REF] Engblom | Processor Pipelines and and Static Worst-Case Execution Time Analysis[END_REF][13] [START_REF] Rochange | A Context-Parameterized Model for Static Analysis of Execution Times[END_REF] [START_REF] Thesing | Safe and Precise WCET Determination by Abstract Interpretation of Pipeline Models[END_REF]; [START_REF] Ballabriga | Improving the First-Miss Computation in Set-Associative Instruction Caches[END_REF] an upper bound of the execution time of the longest path must be derived from the results of steps 1 and 2. This final step is commonly done using the Implicit Path Enumeration Technique [START_REF] Li | Performance Analysis of Embedded Software using Implicit Path Enumeration[END_REF] that expresses the WCET computation problem as an Integer Linear Program. The objective function is to maximize the task execution time computed as the sum of the basic block execution times weighted by their execution counts. Constraints on these execution counts are built from the flow analysis. This is illustrated in Figure 1.

Now, several factors might make the execution times of basic blocks variable. In a pipelined processor, the state of the pipeline at the start of the block execution can affect the instruction scheduling and latencies (the state of the pipeline depends on the prefix path). The presence of history-based devices, like cache memories, also induces variable instruction latencies. The estimation of a block execution time (step 2) must take these factors into account. The result of this step can be the maximum execution time value of the basic block, which might lead to overestimate the task WCET, or the set of possible execution time values. In the latter case, the block execution count must be split into several counts related to the different execution time values and, in step 3, specific constraints on these counts must be derived. To illustrate this, let us consider a basic block that contains a single instruction, in a task that is to be executed on a microcontroller that features an instruction cache. We assume that the execution latency of the instruction is fixed. Then the basic block might have two different execution times, depending on whether the instruction fetch hits (t b h ) or misses (t b m ) in the instruction cache. In the objective function of the ILP formulation, the term x b .t b is replaced by x b m ! M if an analysis of the cache behavior shows that the worst-case number of cache misses when fetching the instruction of block b is M. Note that if the processor is simple enough (in particular, if it executes instructions in the program order, as considered in the experimental part of this paper), the effect of a cache miss can be simply taken into account by adding the miss penalty (t p ) due to the access memory, i.e. t b m = t b h + t p . The problem of estimating the worst-case number of cache misses has been addressed in many papers: we will review them in Section 2. However, as far as we know, all these studies consider a fixed cache miss penalty, i.e. a fixed memory access time. Now, modern DRAM devices support the open page policy that reduces the latencies of sequential accesses to a same DRAM row (also called page). This scheme is sometimes called row buffer.

max T=x A .c A + x B .c B + x C .c C + x D .c D + x E .c E x A = 1 x A = x AB x B = x AB + x EB x B = x BC + x BD x C = x BC x C = x CE x D = x BD x D = x DE x E = x CE + x DE x E = 1 + x EB flow analysis x EB ! 255 x BC ! 0.5 x B low-level analysis c A = … c B = … c C = … c D = … c E = … 1100101 ILP solver T max = … (WCET) with: x A = … x B = … x C = … x D = … x E = … solution N = input data
In this paper, our objective is to propose a technique to include tightly analyzed memory latencies in WCET estimations. Our algorithm is based on abstract interpretation [START_REF] Cousot | Static Determination of Dynamic Properties of Programs[END_REF] and is based on methods previously proposed to analyze instruction caches [START_REF] Alt | Cache Behavior Prediction by Abstract Interpretation[END_REF][9][15] [START_REF] Ballabriga | Improving the First-Miss Computation in Set-Associative Instruction Caches[END_REF]. Our contribution lies in the fact that we combine both analyses (at cache and memory levels).

The paper is organized as follows. Section 2 gives some background information on the memory open page policy and on state-of-the-art techniques used for the analysis of the instruction cache worst-case behavior. In Section 3, we explain our algorithm to analyze jointly the instruction cache and the memory row buffer. Section 4 provides some experimental results that show the improvement of the tightness of WCET estimations due to considering tight memory latencies. In Section 5, we discuss about possible extensions of our method. Finally, concluding remarks are given in Section 6.

Background

Memory hierarchy

The memory hierarchy is composed of several levels of storage, where the components at level n+1 generally have a slower data rate but a larger capacity than those at level n, and where the data at level n are the copies of a subset of the data stored at level n+1. Usually, the lowest (fastest) levels correspond to cache memories and the highest level is some permanent storage (e.g. a disk or flash memory). The reason why the use of a memory hierarchy improves the average performance is that memory references are generally localized both in time and space.

Cache memories (particularly instruction caches) have been widely studied in the context of WCET estimation and techniques to analyze their behavior will be overviewed in Section 2.2. Here, we focus on the memory (DRAM) level.

Figure 2 gives an overview of the main memory organization. On a cache miss, the main memory is accessed through the memory controller. It usually includes one or several memory modules, each of them being composed of several DRAM chips accessed in parallel to provide data of the desired width. Each of these chips is composed of one or several arrays of memory cells, accessed synchronously (then each chip provides several bits of data). A memory cell is made of a transistor-capacity pair. An access (read) to a memory array requires the following steps. First, all the bit lines must be precharged to a logic level halfway between 0 and 1. Then the row containing the data (determined from the highest-order bits of the data address) is selected and all the bit values of this row (also called page) are recovered from the values stored on the capacitors through sense amplifiers. The lowest-order address bits are then used to select the bit (column) to be read.

The use of a row buffer consists in maintaining the last accessed row active. Whenever the next access is to the same row (row hit), only the selection of the new column is necessary. Otherwise (row miss), a new row must be read after a DRAM precharge. As a consequence, the latency of an access to the main memory depends on the content of the row buffer. On a row hit, the latency is reduced to t CAS (time interval between the column access command and the start of data return). On a row miss, the latency is given by t RP + t RCD + t CAS where t RP is the time required to precharge a DRAM array and t RCD is the time interval between the row access command and the data ready at the sense amplifiers. Usual values for t CAS , t RCD and t RP are 2, 3 and 2 memory clocks respectively.

Figure 3. Latency of a memory access

Figure 3 shows how the latency of a cache block fill from the main memory can be computed. In this example, we assume that a cache block is four times as wide as the memory bus. In the first case (upper chart), the access to the first part of the block is a row hit and then has a latency of t CAS . In the second case, it is a miss and the latency of the first read is t RP + t RCD + t CAS . Note that only the access to the first part of the block might miss in the row buffer (the other parts always hit) because of the following reasons: (a) each access concerns a single bit in the buffer (each bit of a word is in a different memory array and then in a different row buffer); (b) the number of bits in a row buffer required to fill a cache block is usually between 2 and 16; (c) common row widths are multiples of 16. Considering the timing parameters numerical values given above, the possible latencies of a cache block fill are given in Table 1.

Techniques for instruction cache analysis

In this section, we review the main state-of-the-art techniques proposed to analyze the behavior of the instruction cache for WCET estimation. These techniques are based on the classification of instruction fetches into categories (firstly defined in [START_REF] Mueller | Fast Instruction Cache Analysis via Static Cache Simulation[END_REF]): Always Hit (when each fetch is guaranteed to hit the cache), Always Miss and Not Classified (when the analysis is not able to predict a fixed behavior for this fetch). These categories are then used to build the ILP formulation as described in Section 1.

To improve the tightness of the analysis, the additional Persistent category (sometimes called First-Miss) can be considered. It concerns instructions that belong to a loop body and remain in the cache between successive iterations (but might miss at the first iteration). Several techniques have been proposed to identify Persistent instructions [START_REF] Ferdinand | Applying Compiler Techniques to Cache Behavior Prediction[END_REF][15] [START_REF] Ballabriga | Improving the First-Miss Computation in Set-Associative Instruction Caches[END_REF].

The categories are determined by performing an abstract interpretation [START_REF] Cousot | Static Determination of Dynamic Properties of Programs[END_REF] on a Control Flow Graph (CFG). Abstract Cache States (ACS) are computed in input and output of each basic block: an ACS is the set of concrete cache states that are possible at a given point during the execution of the program [START_REF] Alt | Cache Behavior Prediction by Abstract Interpretation[END_REF]. Two functions are used: the Update function computes the output ACS of a basic block from its input ACS, and the Join function merges the output ACS of all the predecessors of a basic block to produce its input ACS. The Update and Join functions are applied repeatedly until the algorithm reaches a fix point.

Three different analyses are done: the May, Must, and Persistence analyses. In each case, an ACS associates a set s of l-blocks1 (each one labeled with an age a) to each cache line. In the May (resp. Must) analysis, set s contains the l-blocks that may (resp. must) be in the cache, and the age a " [0 ,A[ of an l-block block is its youngest (resp. oldest) possible age. In the Persistence analysis, set s contains the l-blocks that may be in the cache, and the age a " [0 ,A[ U l T of an l-block is its oldest possible age. The additional

Tight analysis of memory latencies

The row buffer behaves like a very simple cache that would have a single cache line. Then, at first sight, it should be analyzable using the same methods as for the instruction cache. Yet, the position of the row buffer in the memory hierarchy, behind the cache, requires taking the cache behavior into account.

Influence of the cache behavior

The memory row buffer behaves as a single-line direct-mapped cache. If an access to memory references the row that is active in the row buffer, its latency is shorter than when referencing another row. We use the following categories to analyze the worstcase behavior of the row buffer: -Always Hit (RAH): the access is always fast because the row is active, -Always Miss (RAM): the access is always slow because it never hits in the row buffer, -Not Classified (RNC): if none of the previous categories applies (the behavior of the access is too complex to predict). Since the row buffer is only accessed on cache misses, it should be analyzed with the same granularity as the cache, i.e. at the l-block level.

We introduce a new category: Row buffer Not Used (RNU) for the instructions fetches that hit in the cache. They do not have any effect on the row buffer state.

The category of an l-block is determined from its cache category and from the row buffer state before the l-block is fetched from memory.

The most trivial case is when the access is categorized AH in the cache: it is a cache hit and the row buffer is not accessed, which matches the definition of the RNU category.

An AM access always goes to the memory. If it can be proved that the referenced memory row is active in the buffer, the access category is RAH. On the contrary, if it can be proved that the row is not in the buffer, it is a RAM. Otherwise, we get an RNC.

The last cache-related category to consider is the less accurate one: NC (note that we do not handle loops in this analysis, so the cache FM category is considered as NC). It means that the access may result either in a hit or in a miss (at different times). A trivial solution is to consider that the behavior of the row buffer cannot be predicted in this case and to select the RNC category.

To determine the state of a cache by static analysis, two analyses are performed: -

the Must analysis determines the cache state values at each program point, that are true whatever the execution path (the results of this analysis are used for classification to Always Hit), -

the May analysis computes the different possible values of the cache state at each program point considering all the possible execution paths (an access is categorized as Always Miss if the memory row is not in none of the possible states). In the simple case of the memory row buffer, only the May analysis is required, as shown in the following. Since the row buffer contains a single memory row, the May state consists in a set of possible rows. If it contains a single row, it means that all the paths access the same row and then the Must set equals the May set. On the contrary, if the May set contains several rows, it means that at least two execution paths load different rows and then, there is no way to prove that the row is active in the buffer before the access. For these reasons, we only need to perform the May analysis, as presented in the next section.

Analysis by abstract interpretation

Before starting the analysis, the list of memory rows involved in the execution of the program (MR) must be determined. This set is easily obtained by examining the program instructions addresses. Next, the concrete domain D where the real work is done can be defined. At any time, the row buffer contains a single memory row, then D = MR.

The abstract domain D' gives the state of the row buffer at a program point for the abstract interpretation. As, the program usually contains many paths leading to that point, the state may contain a set of rows: D' = 2 MR . In the concrete domain, an Update function changes the state of the row buffer according to the memory accesses. It is very simple: if the row r " MR is read by the cache, the row buffer contents are replaced by r. In the abstract domain, it must be known (1) when a memory access is performed, according to the cache category and (2) which memory row is accessed (this is trivially deduced from the address).

Formally, the Update function U: D' x MR#D' defined as specified in the Table below (r is the memory row of the processed l-block):

cache category U(d, r) AH d AM {r} FM, NC d U {r}
The two first rows are self explicit: cache category AH does not generate any memory access and the row buffer state is not changed; category AM results in a memory access and the referenced memory row becomes active in the row buffer. The last table row states that, since a memory access may or may not be generated for cache categories FM and NC, either the row buffer state is not changed, or the row is read. Thus the abstract domain of the May set contains the rows before the update and the referenced row.

Since the static analysis considers all the possible execution paths, path junction points (after a selection or at a loop entry, for example) can be identified. A Join function is required to merge the results of two joining paths: J: D' x D' # D'. In the May analysis, this function simply makes the union of the possible contents of the row buffer on both paths:

J(d 1 , d 2 ) = d 1 U d 2
Finally, the abstract function $: D # D' must be defined and used to prove the consistency of the analysis, i.e. that the Update and Join functions are monotonic on D' so that the abstract result ever includes the concrete one. A complete partial order ) , , ' ( ! " D is also required and U and J must be checked. Since states are sets of memory rows, $ can be easily defined as $ = {r}. The inclusion can be used as the order and ! is the empty set. The Join function (set union) is monotonic by definition. The monotonicity of the Update is showed below:

cache category AH U(d, r)= d and U(d', r)= d' If d d # ' then ) , ( ) , ' ( r d U r d U # . AM U(d, r) = {r} and U(d', r)= {r} If d d # ' , then ) , ( ) , ' ( r d U r d U $ FM, NC U(d, r) = d U {r} and U(d', r) = d' U {r} If d d # ' , then ) , ( ) , ' ( r d U r d U #
Once the May sets have been determined at each point of the program, they are used with the cache categories to derive the row buffer categories as explained in Section 3.1. The last step is to use these categories to improve the WCET ILP system.

ILP Formulation

Usually, the cost of cache misses for a given l-block is included in the WCET expression by adding the miss penalty (t p ) weighted by the number of misses (x i cmiss ). The IPET objective function is then: According to the row buffer category of the l-block, some constraints can be added: the RAH category indicates that no row buffer miss can occur, then x i rmiss = 0. the RAM category states that the memory row reference always causes a miss, then x i rhit = 0. the RNU category implies that x i rhit = x i rmiss = 0. the NC category does not impose any constraint on the ILP system. As in the initial cache system, we can spare some variables by removing the x i rhit . This is because the ILP solver will minimize x i rhit and maximize x i rmiss that has a greater weight (t p rmiss ). The objective function becomes:

WCET =
WCET = max ( % x i .t i + % t p rhit . x i cmiss + % (

t p rmiss -t p rhit ) . x i rmiss )

The trivial constraint becomes x i rmiss ! x i cmiss and the constraint related to category RAM becomes x i rmiss = x i cmiss .

Experimental results

In this section, we provide some experimental results that show how an accurate modeling of the memory system is necessary to get tight WCET estimates.

Methodology

The algorithm presented in this paper has been implemented within the OTAWA2 framework dedicated to static WCET analysis. The Worst-Case Execution Time of a task is estimated using the IPET algorithm [START_REF] Li | Performance Analysis of Embedded Software using Implicit Path Enumeration[END_REF].The worst-case execution costs of the basic blocks are derived from execution graphs [START_REF] Rochange | A Context-Parameterized Model for Static Analysis of Execution Times[END_REF] and the ILP formulation is augmented with constraints that bound the number of instruction cache misses and the number of memory row buffer misses. These numbers come from an analysis of the instruction cache similar to that described in [START_REF] Ballabriga | Improving the First-Miss Computation in Set-Associative Instruction Caches[END_REF] and from the analysis of the memory row buffer proposed in this paper, respectively.

Hardware parameters.

The experiments reported in this paper were carried out considering an in-order superscalar processor with the parameters given in Table 2. The processor includes a 2-way setassociative instruction cache with 16-byte cache lines and a capacity of 2 Kbytes. Note that the cache size has been set at deliberately small value to be significant with respect to the (small) size of the benchmarks (nevertheless the hit rate is the same as with a larger instruction cache for most of the benchmarks). It is assumed that no data cache is enabled and that the data are stored in an independent memory featuring a fixed access latency.

1 1 1 1 1
Table 3 lists the memory latencies considered for the experiments. We considered a memory clock cycle four times longer than the processor clock cycle, then the latencies are four times longer than those computed in Table 1. We considered four different memory row sizes: 128, 256, 512 and 1024 bytes.

Benchmarks. We used some benchmarks from the SNU suite 3 . They are listed in Table 4.

Performance of the algorithm

Before examining how taking the presence of a row buffer into consideration can improve WCET estimates, let us have a look at the ratio of l-blocks concerned by our analysis. They are the l-blocks that are likely to access memory after a cache miss, i.e. the l-blocks that are not categorized as Always Hit by the cache analysis. Figure 4 shows the ratios observed for all the benchmarks used in our experiments. On average, 44% of the l-blocks must be categorized with respect to the row buffer.

3 http://archi.snu.ac.kr/realtime/benchmark/ Figure 5 plots the different categories found for the different benchmarks, considering 128-and 1024-byte memory row sizes (note that the bus width has an impact on the memory latencies but not on the block categories). For all the applications, the ratio of l-blocks categorized as RowBuffer Not Classified (RNC) is significantly reduced when the memory row size is increased (on a mean, 14% of the l-blocks are RNC for a 128-byte memory row, and this number falls down to 8% for a 1024-byte memory row). The decrease is particularly significant for the minver, qurt and select codes. An explanation to this might be that the core of these codes fit in a 1024-byte memory row and then the l-blocks become categorizable. Note that, for all the benchmarks, the improvement of the categorization rate is in favor of the RowBuffer Always Hit (RAH) category. This is due to the fact that wide memory rows are better to capture spatial locality.

Figure 4. Ratio of l-blocks that might use the row buffer

The categories determined by our algorithm are used to include precise values for the memory latencies in WCET estimates (a short latency is considered for the l-blocks that are found to always hit in the row buffer). In Figure 6, the improvement of WCET estimates reached with our algorithm on is shown as a function of the size of the memory row and of the bus width. As expected, the gain is higher for a wide bus: this is because the number of memory accesses required for a cache block fill is smaller and then the overhead of a miss in the row buffer is lower compared to the global latency (20 cycles over 24 for a 64-bit bus, against 20 cycles over 72 for a 16-bit bus, as specified in Table 3. As a result, systematically considering long latencies (when the row buffer is not taken into account) is more pessimistic for wide busses. and Figure 8 show the impact of those two parameters (row size and bus width) on each of the benchmarks. The value of the second parameter (which is fixed here) has no impact on the shape of the curves. It can be observed that the improvement increases with the bus width for all the benchmarks. Most of the benchmarks also draw a benefit from the analysis of the row buffer that is more significant when the memory row is wide. This is due to the fact that large row sizes allow a more precise categorization of the memory accesses. The improvement is spectacular for the minver, qurt and select application that have a sensibly better ratio of categorization for a 1024-byte row than for a 128-byte row.

Possible extensions of this work

Although it seems that the analysis of a memory row buffer has not been investigated yet, Mueller has proposed to apply its cache abstract simulation to L2 instruction caches [START_REF] Mueller | Timing Predictions for Multi-Level Caches[END_REF]. He proposed two techniques to compute the categories for L2 cache accesses but no experimentation results are provided. As far as we know, L2 caches have still not been analyzed using techniques based on abstract interpretation. At first sight, the memory row buffer analyzed in this paper is not very different from a cache (it can be seen as a cache with a single cache line). Then the analysis of an instruction cache coupled to a memory row buffer does not seem very different from a 2-level cache hierarchy (except that our second level is extremely simple here). In this section, we discuss whether our algorithm used to analyze the row buffer could be used or extended to analyze a two-level cache hierarchy. We highlight two main issues that might prevent from such a generalization.

First, there is a significant difference between the L1 cache and row buffer analyses: the latter is performed through the filter made of the categories determined by the former. The row buffer analysis is indeed impacted by the inaccuracies introduced by its own passes on one hand, and by the L1 cache analysis on the other hand. For example, each time an l-block is categorized as NC or FM for the L1 cache, two cases must be considered: the memory row may or not be active in the row buffer. The extreme simplicity of the row buffer (a single active row) reduces the range of the error as it is likely that the next memory access quickly results in a precise state that bounds the impact of the inaccuracy. If the algorithm proposed in this paper was to be extended to support L2 caches (instead of a memory row buffer), it would be necessary to evaluate the negative impact of both analyses to assert that the approach still gives useful results.

The second issue concerns the use of the Persistence analysis to get tight results in the cache analysis. The Persistence analysis allows benefiting from the code temporal locality and earlier work has shown that it can significantly improve the accuracy of WCET estimates [START_REF] Ferdinand | Applying Compiler Techniques to Cache Behavior Prediction[END_REF] [START_REF] Ballabriga | Improving the First-Miss Computation in Set-Associative Instruction Caches[END_REF]. We have not used the Persistence analysis in our row buffer analysis as accesses to the memory (on cache misses) are not likely to exhibit as much temporal locality as accesses to the cache. To extend our approach to support L2 caches, it would be necessary to implement the Persistence analysis. Determining whether the results obtained through the filter of the L1 categories remain useful is left for future work.

Another issue would be to take into account the accesses to data. In this paper, we have considered separate instruction and data memories so that the behavior of the row buffer for instruction accesses is not disturbed by data accesses. Taking into account the interferences due to data loads could be challenging. However, before tackling this problem, it is necessary to be able to analyze data caches, which is still an open issue at this time due to the difficulty of determining some of the data addresses during static analysis (however, some techniques provide some support for simple data indexing [14][18]).

Conclusion

To compute a safe and tight estimation of the Worst-Case Execution Time of a critical task, it is necessary to take into account every parameter of the target hardware. Various approaches have been proposed these last years to analyze the worst-case behavior of modern processors that include one or several pipelines, a branch predictor, cache memories, a dynamic instruction scheduler, etc. On the other hand, the memory system has not been much studied so far and the latency of memory accesses is generally considered as a fixed value. Now, modern DRAM devices support some mechanisms that improve the access rate by exploiting the temporal and spatial locality of the references. The row buffer, also referred to as open page policy, is one of these mechanisms. Whenever a piece of data is accessed, the entire memory row is maintained active until the next reference which can be served faster if it addresses the same row.

If the target processor does not have an instruction cache, the row buffer can be analyzed the same way as a very simple cache. But, when coupled to an instruction cache, the analysis of the row buffer requires a specific algorithm since not all of the instructions fetches go to memory (only those that miss in the instruction cache). In this paper, we have proposed such an algorithm based on an abstract interpretation of the application code.

Experimental results show that our algorithm is efficient in categorizing the behavior of the row buffer for a significant ratio of the accesses to memory. On average, 63% (84%) of the l-blocks are classified as RowBuffer Always Hit or RowBuffer Always Miss for a 128-byte (resp. 1024-byte) memory row width. The ratio of l-blocks that are determined as always hitting in the row buffer is very high (on average, 53% for a 128-byte row and 80% for a 1024-byte row). For each of the corresponding memory accesses, a short latency is accounted for in the estimated WCET. As a result, the estimated WCET is tighter as when the row buffer is ignored. Our results show that the mean improvement ranges from 6% (128-byte memory row and 16-bit bus) to 15% (1024-byte memory row and 64-bit bus). For some benchmarks, it reaches up to 34%.

As discussed in the paper, extending the proposed solution to support multi-level cache hierarchies would require further investigation, mainly to assert whether the accuracy of the results is acceptable. This will be part of our future work.

Figure 1 .

 1 Figure 1. Overview of the IPET method to estimate Worst-Case Execution Times x b h .t b h + x b m .t b m and some constraints are added: x b h + x b m = x b and, for example,x b m ! M if an analysis of the cache behavior shows that the worst-case number of cache misses when fetching the instruction of block b is M. Note that if the processor is simple enough (in particular, if it executes instructions in the program order, as considered in the experimental part of this paper), the effect of a cache miss can be simply taken into account by adding the miss penalty (t p ) due to the access memory, i.e. t b m = t b h + t p . The problem of estimating the worst-case number of cache misses has been addressed in many papers: we will review them in Section 2. However, as far as we know, all these studies consider a fixed cache miss penalty, i.e. a fixed memory access time. Now, modern DRAM devices support the open page policy that reduces the latencies of sequential accesses to a same DRAM row (also called page). This scheme is sometimes called row buffer.In this paper, our objective is to propose a technique to include tightly analyzed memory latencies in WCET estimations. Our algorithm is based on abstract

Figure 2 .

 2 Figure 2. Main memory organization

Figure 5 .

 5 Figure 5. Categories found for 128-and 1024-byte memory row sizes

Figure 7

 7 Figure7and Figure8show the impact of those two parameters (row size and bus width) on each of the benchmarks. The value of the second parameter (which is fixed here) has no impact on the shape of the curves. It can be observed that the improvement increases with the bus width for all the benchmarks. Most of the

Figure 7 .Figure 8 .

 78 Figure 7. WCET improvement as a function of the bus width (256-byte memory row)

Table 1 . Latencies of memory accesses

 1

	block size /	hit latency	miss latency
	mem. width	(mem. clocks)	(mem. clocks)
	2	6	11
	4	10	15
	8	18	23

Table 2 . Processor configuration Fetch stage width 4 Decode/rename/commit stage width 2 Fetch queue size 8 Issue queue size 8 Functional units (latency) integer ALU (1 cycle) fp ALU (3 cycles) multiplier (6 cycles) divider (15 cycles) memory (2 cycles)

 2

Table 3 . Memory access latencies

 3

			bus1 bus2 bus3
	memory bus width (bits)	16	32	64
	bus width / cache block size	2	4	8
	latencies	hit	24	40	72
	(processor clocks)	miss	44	60	92

Table 4 . Benchmarks benchmark function # l-blocks

 4

bs Binary search 25 crc CRC cyclic-redundancy check 167 fft1 Fast-Fourier transform using Cooly-Turkey algorithm 792 fibcall Fibonacci series 15 fir FIR filter with Gaussian number generation 607 insertsort Insertion sort 37 jfdctint JPEG slow-but-accurate integer implementation of the forward DCT 115 lms LMS adaptative signal enhancement 457 ludcmp LU decomposition 315 matmul Matrix product 76 minver Matrix inversion 442 qurt Root computation of quadratic equations 245 select N-th largest number selection 160

An l-block results from the projection of the CFG on the cache block map: a cache block that contains instructions belonging to n different basic blocks is considered as n lblocks.(oldest) virtual age l T stands for the l-blocks that may have been fetched into the cache, and subsequently replaced. An l-block is persistent if it is in the Persistence ACS, and its age is not l T (i.e. once the block has been fetched, it can never be replaced).Once built, the ACS are used to derive the instruction categories listed above.

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