Med Fehmi Chatmen

Adel Baganne

Rached Tourki

Low latency multicasting architecture implemented using new network topology

an important service in distributed systems, as multiprocessors, is the ability to transmit multicast messages. Cache coherence protocols and parallel algorithms are examples of applications requiring multicast messages. Several algorithms have been developed to implement multicasting namely the path based, and the tree based. These algorithms were able to ease the rapid saturation effect generated by such type of transmission. However, for some applications, these algorithms are not always efficient, and the multicast service might still generate the network saturation for low data loads. That's why recent studies have tried to apply these routing algorithms using a new network topology based on 3D integrated circuit technology (3DIC) . However, the 3DIC has not reached maturity because of the use of multiple number of TSV (through silicon vias). In this paper, we demonstrate the benefits of implementing adaptive multicast algorithm on a VRNOC architecture. Simulations and hardware synthesis results show that the proposed on-chip network architecture provides significant improvements in average network latency (15 %) and resources (33 % in number of links) than a fully 3D NOC.

1.INTRODUCTION

.

Figure 1.TSV landing pad et TSV keep out zone is A few times larger than gates & memory cells [8]

There are two types of on chip data traffic; the unicast and the multicast. the unicast is data exchange between two cores whereas the multicast is the fact to transmit the same packet from one source to multiple destinations (one to many communication); this type of traffic presents 5 to 10 % of the network traffic in communication traces of different cache coherence protocols and operand network [START_REF] Jerger | Virtual Circuit Tree Multicasting[END_REF] .the multicast communication implies an excessive use of network resources and a major occupation of bandwidth (occupancy of network interconnections links). Several studies [START_REF] Wang | Design and realization of 3D NOC multicast router base on multicast rotational routing arithmetic[END_REF][START_REF] Meena | A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip[END_REF][START_REF] Moosavi | Enhancing Performance of 3D Interconnection Networks using Efficient Multicast Communication Protocol[END_REF][START_REF] Moosavi | An efficient implementation of Hamiltonian path based multicast routing for 3D interconnection networks[END_REF][START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF][START_REF] Nasiri | Reconfigurable multicast routing for Networks on Chip[END_REF] proposed algorithmic solution to implement this service with standard 2D NOC or with the 3D architecture. these works ignored the limitations presented by both architectures.

Our 2D VRNOC topology [START_REF] Fehmi Chatmen | New design of Network on Chip Based on Virtual Routers[END_REF] take into consideration the limitations presented by both: classic 2D network and 3D ones. the VRNOC is generic and is simple to adopt for any routing scheme; it consists of dividing the network on a set of subnetworks that can only communicate via network interfaces (NI). the number of cores (processors) connected to each NI is equal to the number of subnetworks (so all cores can transmit packet simultaneously to their destinations). The NI consists then of N to N switching unit that ensure communication between the N connected cores to the N subnetworks. In the first part of this paper we demonstrate how to transform any 3D network (regardless the router structure or the routing algorithm) on VRNOC [START_REF] Fehmi Chatmen | New design of Network on Chip Based on Virtual Routers[END_REF]. Since our well performed VRNOC is generic, we attempt to use it to the implement an adaptive routing algorithm [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] for multicast transmission. the purpose is offering a low-cost multicast solution that can possibly replace the classic ones.

SIMILAR WORKS

Several studies have tried to propose algorithmic solutions to implement the multicast service. The purpose of these algorithms was to pass packets to multiple destinations using the minimum of branches (interconnections links) and to reduce the number of duplications of the transmitted packet to reduce the occupation of network bandwidth and the transmission cost. This improves the average latency of the network, comparatively to the multi-unicast algorithm. These algorithms could be classified into two main types The first one is based on the principle of routing tree (tree based) [START_REF] Enright-Jerger | Virtual circuit tree multicasting: A case for on chip hardware multicast support[END_REF]. This type of algorithm is suffering from an extra latency used to establish the tree before starting the sending of the packet, and the tree is found only if all its branches are free (the tree-based path is reserved and ready for packet transmission). This algorithm demands that each router must implement a routing table which requires more resources to read and update the table. Finally, we can say that this type of algorithm is interesting in the use of the network bandwidth (less branches are used) but presents a considerable network average latency.

The second type is path based [START_REF] Daneshtalab | Low distance path-based multicast routing algorithm for network-onchips[END_REF][START_REF] Wang | Efficient lookahead routing and header compression for multicasting in networks-on-chip in :Architectures for Networking and Communications Systems (ANCS)[END_REF][START_REF] Lin | Multicast communication in multicomputer networks[END_REF][START_REF] Boppana | Resource deadlocks and performance of wormhole multicast routing algorithms[END_REF][START_REF] Carara | Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Networks-on-Chip[END_REF]; this type of algorithm is based on the Hamilton principle. The packet follows a path across the network with a low number of duplications. With this type of algorithm, we avoid both the live lock and the dead lock issues, but we suffer from a significant latency especially for nodes that are distant from each other.

There are also other algorithms used to implement the multicast service that are based on the principle of RPM [START_REF] Wang | Recursive partitioning multicast: a bandwidth efficient routing for Networks-on-Chip[END_REF]. The principle is to divide the network into eight parts at the current router (the last router receiving the packet) and to forward the packet to the various parts according to certain rules in order to optimize the number of duplications.

Recent works such as [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] and [START_REF] Nasiri | Reconfigurable multicast routing for Networks on Chip[END_REF] proposed a reconfigurable multicast routing for mesh 2D network on chip, these works presented interesting solutions to achieve performances improvement on the network average latency and power consumption for medium sized networks compared to deterministic ones.

All these previous works have implemented their solutions adopting a 2D dimensional network, but with the advantages brought by the 3D IC technology, works such as [START_REF] Harutyunyan | Two New Multicast Algorithms in 3D Mesh and Torus Networks[END_REF][START_REF] Liu | Adaptive unicast and multicast in 3D mesh networks[END_REF][START_REF] Wei | An equilibrium partitioning method for multicast traffic in 3D NoC architecture[END_REF][START_REF] Ebrahimi | Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing[END_REF] used this technology to implement their solutions for the multicast service, these works showed a better performance in terms of the average latency, power and surface consumption and the throughput compared to those adopting the 2D structure. However, these works did not take in consideration the issue of the indispensable reduced number of TSV considered by works such as [START_REF] Ghidini | Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy[END_REF][START_REF] Ghidini | TSV Multiplexing: A 3D NoC Occupancy Analysis[END_REF][START_REF] Liu | Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip[END_REF][START_REF] Dubois | Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs[END_REF][START_REF] Bartzas | Three-dimensional Networks-on-Chip architectures[END_REF]. They used simply a fully connected structure of 3D network In this paper, we present a novel solution for implementing the multicast service, this solution is done in a way to evade the limitations showed by both classic 2D structure and the 3D network.

This paper contains three parts:

In the first part, we present the virtual router concept In the second part, we show how we implemented the reconfigurable architecture presented in using our VRNOC topology In the third part, we highlight the architecture performances in terms of latency and surface consumption

A. VIRTUAL NOC CONCEPTS

Our virtual network (VRNOC) [START_REF] Fehmi Chatmen | New design of Network on Chip Based on Virtual Routers[END_REF] is a 2D NOC architecture with the advantages of the 3D NOC communication behavior. The main idea of the proposed VRNOC is the abandon of the TSV in NOC design while keeping a 3D-Like processing and communication. VRNOC uses specific routers -called Global Routers that manage packet data communication -in similar way to basic 3D NOC, Through Virtual Layers. VRNOC architecture is generic and it doesn't depend on neither the router structure nor the routing algorithm. VRNOC design is generic and can easily be derived from any fully 3D NOC. the design flow for transforming fully connected 3D NOC to a VRNOC is defined as follow:

VIRTUAL NOC GENERATION

• TSV removing

The VRNOC generation process begins by removing TSV. Hence all vertical links within the 3D NOC and the associated Crossbars are then removed, which offers a large gain in used resources. (See figure 2

.b)

• Global Router design After removing the TSV links, the vertically adjacent routers are, assembled together to form a Global Router GR (see figure 2.c). Thus each global router is composed of N elementary routers -we called Virtual Routers VR. All the obtained GR are stacked in a single 2D .So, for a 3D network with a size of (NxNxN) we will obtain NxN Global Router. Notice that VR routers inside a GR don't communicate to each other's. For the rest of the paper we denote: GR(x,y) : global router with (x,y) coordinates VR(x,y,i) :virtual router with index i inside GR(x,y) Notes that VR(x,y,i) corresponds to R(x,y,i) in the initial fully connected 3D NOC GR(x,y) = {VR(x,y,i) , 0<=i<N-1}

• Virtual Layer specification The objective of this task is to retrieve the layer structures of the initial 3D NOC within the set of the obtained Global routers. So every set of routers that belong to the same layer in the initial 3D NOC are linked together to form a separated virtual layer (see figure 2.d) .This process is done according to the elementary router index within the global router. Hence all the obtained N virtual layers will constitute our generated VRNOC. VLi= {VR (x,y,i) , 0<=x<N-1, 0<=y <N-1} With VLi is the ith virtual layer VRNOC (NxN)= {Vli , 0<=i , i<N-1}

In our VRNOC virtual layers are separated and they are only connected to the network interface NI. Each GR node of the VRNOC communicates directly with N IP cores through the NI. Hence our VRNOC is connected to N 3 IP cores, which is the same scheme as a traditional fully connected 3D NOC. For any transmission, an IP core can use any virtual level to deliver packet to destination. To get to destination IP core, the packet must reach the corresponding GR via one virtual layer. The virtual layer selection and packet transmission are carried out by the network interface (see figure 5). The pseudo code of the VRNOC generation process is detailed in Figure 3 As described above, the proposed design flow is generic and can be applied to any 3D NOC and with any router structure

EXAMPLE: 3X3 VRNOC GENERATION FROM A 3X3X3 3D NOC

Let's consider 3x3x3 3D NOC to illustrate our design process. The TSV removing task allows a reduction of 18 bidirectional links from the initial 3D NOC from a total of 54 links.

The resulting global router GR is formed by a set of 3 virtual routers (see figure 5.b). Also, we have 3 virtual layers: one base layer (z=0) ) and two other layers ( z= 1 and 2). The obtained 3x3 VRNOC is then composed by 9 global routers associated to 3 virtual layers. It has 9 NI that are connected to the 9 GR. Thus, the generated VRNOC has 27 connected cores IP, which is the same number for the considered (3x3x3) 3D NOC. To show the importance of the latency reduction of our network compared to the 3D conventional network, we will use the following example (see figure 6 and7) : consider the 3D network of size 3x3x3 and the router with address (0, 2, 0) sends a packet to the router designated by the address (1, 1, 2), and the latency to transmit a Flit from an input port to an output port is 1 cycle, then we have four routers to cross from the source to the destination which induces a latency of 4 cycles. This communication is similar as transmitting the packet from GR router with coordinates (0,2) to the GR router with coordinates (1,1) within a network with virtual routers with a dimension of 3x3. Then we have a path with only two hops, which induces a latency of 2 cycles.

The proposed VRNOC is generic in terms of router architecture and routing strategies so it can be easily adapted to implement other network architectures and routing schemes. In that, the second part of this paper deals with the multicast implementation using the VRNOC architecture

In the second part of this paper, we detail the implementation of the multicast algorithm presented in [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] using our VRNOC architecture in the goal of assembling the advantages brought by both architectures.

B. IMPLEMENTING THE ADAPTIVE PARTITION-BASED MULTICAST ROUTING ARCHITECTURE USING VRNOC TOPOLOGY B.1 ADAPTIVE PARTITION-BASED MULTICAST ROUTING ARCHITECTURE

The authors of [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] propose a self-adaptive partition-based algorithm for routing multicast traffic based on LADPM in a 2 D mesh network: the adopted routing algorithm as in LAPDM divides the whole network into at most 8 parts. The packets in the network are classified into two categories based on the relative location of the destination nodes. These two kinds of packets are transmitted in two separated virtual networks and two simple and efficient turn models -North-Last and West-Last turn models are used in these two virtual networks respectively to avoid deadlocks. North-Last and West-Last turn models are no cycle dependency by forbidding two turns respectively to avoid deadlock The improvement brought by [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] compared to the LAPDM algorithm is the possibility to find alternative routing paths without increasing the path length. They used the method based in the VN bit calculation to identify the chance of adaptive routing: If more horizontal links can be shared, the VN bit is set to 0; while if more vertical links can be shared the VN bit is set to 1; the VN bit is used to decide to which virtual network the multicast packet belongs, and in a certain condition, which path is used for packet delivery. If there are more than one path available, the routing scheme chooses the one with the maximum number of empty channel buffer slots. Each virtual layer of the VRNOC has almost the same entities of the network architecture presented in [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF]; so one virtual layer is formed by two virtual networks; North-Last and West-Last based turn models are used in virtual network 0 and virtual network 1, respectively. In the North-Last algorithm, more horizontal links can be shared (VN is set to 0), whereas in the West-Last algorithm, more vertical links can be shared (VN is set to 1). The only difference between both architectures is that in our case the VN bit calculation is done at the network interfaces; The reason is that only one virtual layer is used to deliver packet to all destination nodes, so the NI calculates the VN bit based on Global routers addresses.

B.2 ADOPTING THE SELF-ADAPTIVE PARTITION-BASED ALGORITHM WITH THE VRNOC ARCHITECTURE

B.2 .1-PACKET FORMAT

The main advantage of implementing multicast algorithm using VRNOC is that only one virtual layer is used to deliver packet to all destinations. In that the packet header contains one or more Flit compared to [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] (depends on the network size) to indicate the addresses of Global routers concerned by the multicast transmission see figure 8. Only this Flit is used to route the packet in the selected virtual layer. The calculation of the VN bit is based on the addresses of these Global routers. A global router is concerned with the multicast packet if one or more elementary routers are destinations nodes. This leads in an important reduction on the number of cycles required for reading the packet header; since only the global router must read it on behalf of all correspondent elementary routers The global routers destinations addresses are stored in the additional header Flit in fields GDST1 to GDSTn using the bit-string coding method; where n is the number of global routers in the whole network. If the value of field GDSTi is set to 1, this means Global router i is included in destination set. Besides the destination set, Flit Type and VN are two fields that are included in the additional header Flit. Flit Type, which is a 2 bits field, is used to indicate whether this Flit is an additional head Flit, head Flit or a body Flit. The VN filed is used to identify the virtual network since the proposed routing algorithm uses two virtual networks to avoid deadlocks. The packet size field (4 bits) is used to indicate the packet size, so there is no need for a packet tail (compared to [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF]). The S.node field (11 bits ) is used to define the address of source node of the multicast packet . the figure 9 shows the S.node field format

Figure.9. S.node field format

The S.node field consists of 2 parts; the first part (8 bits) defines the global routers XY coordinates to which the source node is connected. the second part (3 bits) is used to define the source node address. The rest of the header Flits is used by the NI to deliver packet to destination nodes, where DST11 to DSTn8 are the destinations addresses of the multicast packet using the bit-string coding method and by considering the global router to which it belongs: DSTij : is one bit filed and it is set to 1 if the node j of the global router i is concerned by the multicast packet , and it is set to 0 if not .

B.2 .2-VN BIT CALCULATION

As it is described in B.2 .1-the VN bit is used for identifying the virtual network to which the multicast packet will be injected. So in each virtual layer two types of traffic are transmitted in two separated virtual networks to avoid deadlock and packet transmission from one virtual network to another one is not permitted for deadlock avoidance. Packet transmission from one virtual layer to another is also not permitted. Once the packet is injected into the network, the VN field will never be changed by any intermediate router in the whole transmission process. We used the same strategy of [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] in the calculation of the VN bit; the idea is to calculate the link utilization of the packet under XY and YX routing schemes: in that two multicast trees -XY tree and YX tree are constructed . In the XY tree, all of the paths from source node to destination nodes follow XY routing algorithm. While in YX tree, all the paths follow the YX routing algorithm than the number of used links in each multicast tree is calculated. If this number in the XY tree is smaller, the VN bit is 0; otherwise, the VN bit is 1. The author of [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] has well described the idea behind the use of the VN bit but he didn't tackle the cost of its calculation since the way how to calculate the link utilization according to destination addresses was not detailed. (there is a huge number of possible combinations for calculating the number of links) In our case, the VN bit calculation is done at the NI: We first attribute to each node (global router) a variable (NL) that defines the number of links that separates it from the source node. Than we reduce the set of the destination based on their locations (we don't need all the destinations set for constructing the trees):

• for the XY tree we conserve just the routers, having the same x coordinates, and that are most distant to source node according to y axis (see figure 10) • for the YX tree we conserve just the routers, having the same y coordinates, and that are most distant to source node according to x axis (see figure 11)

RDS=∅; Lu=∅;ld=∅; XYSNL=0; --constructing the reduced destination set (RDS) -For (i=x@S ,i<N,i++) For (j= y@S,j<N,j++) If (GR(i,j) ∈ DS) then Lu(i)=j; End if; End for;

RDS=RDS+GR(i,lu(i))

For (j= y@S,j>=0,j--) If (GR(i,j) ∈ DS) then Ld(i)=j; End if;

RDS=RDS+GR(i,lu(i))

For (j= y@S,j>=0,j--) If (GR(i,j) ∈ DS) then Ld(i)=j; End if; End for;

RDS=RDS+GR(i,ld(i))

End for; ---calculating the number of horizontal and vertical link ----For (i=0 ,i<N,i++)

For (j=0 ,j<N,j++) If (GR(i,j) ∈ RDS) then XYSNL= XYSNL

Our routing algorithm for the multicast packet transmission is almost the same as presented in [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] with one exception; that the VN bit-based algorithm, in our VRNOC architecture, is applied in all different virtual layers.

Our elementary router (see figure 12), is then similar to the router presented in [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] with some differences (the number of used VC); It is formed by an input queues, Routing Computation (RC) module, Virtual Channel (VC) allocator, Switch allocator and Crossbar. In our router 10 virtual channels are used. In each input port, we associate 2 VC; the first one is used for the first virtual network (VN=0). the second one is used for the second virtual network (VN=1).

The switching protocol adopted by our router is the credit based, and the switching mechanism is the wormhole which explains the presence of VCs.

Figure .12 Router architecture And since the two turn models in our proposed routing algorithms are used in two separated virtual networks, no cycle dependency exists in the network and our multicast routing algorithm is deadlock-free

B.2 .4-network interface

The network interface in our architecture has several functions; it selects the virtual layer in which the multicast packet will be injected. also, it calculates the VN bit value and then according to it, it defines which virtual network and routing algorithm to use to deliver packet to their destinations The figure 13 presents our network interface structure for 3x3 VRNOC architecture The packet header reconstructing unit adds the VN bit value to the packet header. The interface input controller and the interface output controller are used to establish communication between the network and the IP cores. There are no VC in our network interfaces to moderate its surface consumption. The VN bit calculation unit calculates the VN bit value according to the steps described in B.2 .2. The virtual layer selection unit indicates witch virtual network to use based on the VN bit value, and this is only for the packet coming from the local port. Elsewhere, the receiving router must read the packet header to define the appropriate virtual network.

C. SIMULATION RESULTS AND DISCUSSION

For appraising the efficiency of the proposed method, we have developed a cycle accurate systemC model for our VRNOC architecture. The packet switching technique being adopted is wormhole and the packet latency is defined as the number of cycles spent between the generation of the multicast message until the last flit reaches the last destination.

C.1 LATENCY

First, we compare the latency performance of our multicast routing algorithm for 4x4x4 VRNOC with the 2D adaptive partition-based multicast [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] for a 8x8 sized network under different unicast traffic percentage and injection rate and different number of destinations (since our VRNOC is also a 2D network). The multicast traffic follows a random distribution with each node having equal probability to be selected as the destination. In our simulations, we use the following three unicast traffic patterns: uniform, bit-complement and transpose. The configuration parameters are shown in Table I. configuration parameters Later, we compare the latency performance of our multicast routing algorithm with other 3D multicast-based networks. [START_REF] Wang | Low Latency and Energy Effcient Multicasting Schemes for 3D NoC-based SOCs[END_REF] Figure .14 latency of (4*4*4) VRNOC with 2 VC for each input port compared with the 8*8 2D adaptive partition-based multicast with 4VC for each input port Figure. [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] shows the latency performance of the 2D adaptive partition-based multicast and our proposed routing algorithm under 50% unicast traffics with different traffic patterns and 3-Flit-long packets. The buffer length in this simulation is set to 5, and the configuration of this simulation is 4 destinations. For the 2D adaptive partition-based multicast the number of VCs is set to 4 for each input port. while, for our network the VCs number is set to 2 .As can be seen from Figure 14, our routing algorithm outperforms the 2D adaptive partition-based multicast under each kind of mixed traffics. Also, it can be seen from Figure 15 that the saturation point for our network is at 0.05 while it is at 0.04 for the 2D one. This can be explained by the fact that our network offers always a shorter path for packet delivery when compared with the 2D one even if this latter has more VC per input port. Considering the same configuration parameters, we also compared our solution with the 2D adaptive partitionbased multicast when the number of VC for each input port is set to 8. As can be seen from Figure 15, our routing algorithm outperforms the 2D adaptive partitionbased multicast under each kind of mixed traffics for low injection rate but after (for higher injection rates) the 2D adaptive algorithm outperforms our scheme. this can be explained by the fact that the 2D adaptive algorithm offers more paths (virtual paths) thanks to the important number of VC which is 8 per input port. This shows the effectiveness of the VCs in preventing the network saturation when used in an important number. Figure 16 shows the latency performance of 2D adaptive structure and our proposed routing algorithm with 50% unicast traffics and 3-Flit-long packets. The buffer length in this simulation is set to 5, and the configuration of this simulation is 4 destinations. As can be seen from Figure 17, our routing algorithm outperforms 2D adaptive architecture under each kind of mixed traffics regardless the value of the injection rate. In order to evaluate our network performance in terms of latency with a fully connected 3D network we considered the work of [START_REF] Wang | Low Latency and Energy Effcient Multicasting Schemes for 3D NoC-based SOCs[END_REF] . in this work MXYZ algorithm is used for multicast packet transmission. We also implemented the MXYZ algorithm using our VRNOC topology (elementary routers that belong to the same global router are considered as the routers having the same z link) . the configuration parameters used for this evaluation is shown by table 2. As can be seen from Figure 17, our routing algorithm adopting the VRNOC (with adaptive multicast algorithm) outperforms both VRNOC MX and the MXYZ architectures even if this latter is implemented using a fully connected 3D network and with 33% less connected cores.

C.2. DESIGN IMPLEMENTATION USING FPGA BOAR

C.2.1. IMPLEMENTATION OF THE DESIGNED ROUTERS

We have implemented various elementary routers on an FPGA boardVIRTEX6XC6VLX760 using the XILINXISE14. The implementation of different routers shows tha the number of ports and Flit's size have major effects on routers performance in terms of surface consumption (consumed lut) and maximum execution frequency.

C.2.2. IMPLEMENTATION OF THE NETWORK INTERFACES

As described in section B.2.4 our network interface carried out virtual layer selection for packet routing. Such processing replaces all crossbars used for transmitting data towards vertical directions-in the classic fully connected 3D networks. We implemented VRNOC interfaces using the same FPGA board and the table 5 shows the obtained results for different network size.

The results show that our network interfaces consume a very low surface compared to our five ports router (90% much lower in terms of consumed (LUTs) which means that the added resources in our new topology are assumed acceptable. Figure 19 shows that our network interfaces area get slightly bigger when the size of the network increased. In this paper we have introduced a low latency network architecture dedicated to the multicast service. We adopted the adaptive multicast routing algorithm presented in [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] for multicast packet delivery. we implemented this algorithm with our virtual router based topology.

D. CONCLUSION

The proposed network solution took the advantage of the well performed multicast (VN bit based) algorithm which offers the possibility to find alternative routing paths without increasing the path length. and the advantage of the VRNOC based topology in avoiding the limitations showed by both classic 2D and 3D structures. it is noticeable that the obtained results are considerable when compared with our referenced works [START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF][START_REF] Wang | Low Latency and Energy Effcient Multicasting Schemes for 3D NoC-based SOCs[END_REF].

The proposed VRNOC is generic in terms of router architecture and routing strategies so it can be easily adapted to implement other network architectures and routing schemes. In our future works, we attempt to improve our routing algorithm using contention aware and lookahead techniques for virtual layer selection. Also, real workload traffic and illustrative applications will be considered to evaluate the network performances.

Figure. 2 .

 2 Figure.2. NOC transformation to a virtual NOC

Figure 5 .

 5 Figure 5. Case of transmission between GR routers : (GR (0, 2), IP2) and (GR (2, 0), IP3)

Figure. 6 .Figure. 7 .

 67 Figure.6. Example of a communication within a classic 3D network

Figure. 8 Figure. 8 .

 88 Figure.8. packet format

Figure. 13

 13 Figure.13 Network interface architecture

  Figure.[START_REF] Gu | An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip[END_REF] shows the latency performance of the 2D adaptive partition-based multicast and our proposed routing algorithm under 50% unicast traffics with different traffic patterns and 3-Flit-long packets. The buffer length in this simulation is set to 5, and the configuration of this simulation is 4 destinations. For the 2D adaptive partition-based multicast the number of VCs is set to 4 for each input port. while, for our network the VCs number is set to 2 .As can be seen from Figure14, our routing algorithm outperforms the 2D adaptive partition-based multicast under each kind of mixed traffics. Also, it can be seen from Figure15that the saturation point for our network is at 0.05 while it is at 0.04 for the 2D one. This can be explained by the fact that our network offers always a shorter path for packet delivery when compared with the 2D one even if this latter has more VC per input port. Considering the same configuration parameters, we also compared our solution with the 2D adaptive partitionbased multicast when the number of VC for each input port is set to 8. The results are shown by the figure15.

Figure. 15

 15 Figure.15 latency of (4*4*4) VRNOC with 2 VC for each input port compared with the 8*8 2D adaptive partition-based multicast with 8VC for each input port

Figure. 16

 16 Figure.16 latency performance under different unicast traffic for the (8x8) 2D adaptive network and the (4x4x4) Virtual router-based network

Figure. 17

 17 Figure.17 latency of (4x4) VRNOC self-adaptive multicast compared with the 8*8 3D MXYZ based multicast and 4x4 VRNOC MXY, with a 30% of multicast packet.

Table 5 .Figure 19 .Figure18.

 519 Figure 19.Schematic presentation of the consumed Area for network interfaces with different network sizes

Table I

 I

	Packet length (Flits)	3
	Multicast traffic	Random distribution
	Unicast traffic	Uniform, bit-complement, transpose
	Topology	4x4x4 VRNOC
	VCs	2 per input port
	VC depth	5

  1 tool see table 3Table3 Area and frequency of our different routers In order to identify the impact of buffer size and Flit size in our network design, we have implemented our 5 ports router with different Flit size[START_REF] Bartzas | Three-dimensional Networks-on-Chip architectures[END_REF] 64,128) and with different input buffer size. (see figure18 and table 4).

		Type of elementary router	3 PORTS ROUTER	4PORTS ROUTER	5PORTS ROUTER
		frequency (MHZ)	463	193	75
			Area(LUT)	3400	7800	27000
		FPGA DEVICE	VIRTEX 6	VIRTEX 6	VIRTEX 6
	Flit size	Vc size	Area(consumed lut)
	32	16	27500
		8	24100
		4	22284
	64	16	38827
		8	34434
		4	31000
	128	16	44100
		8 16

End for; RDS=RDS+GR(i,ld(i))

End for; For (i=x@S ,i>0,i--)

For (j= y@S,j<N,j++) If (GR(i,j) ∈ DS) then Lu(i)=j; End if; End for;

+NLGR(i,j))

End if ; End for ; End for ; With: RDS: reduced destination set Lu: last addressed node at the up direction Ld: last addressed node at the down direction GR(i,j): global router with (i,j) coordianates NLGR(i,j)): number of links separating the source node to the GR( i,j) router. XYSNL:number of links for the XY tree Figure.10 Pseudo code of VN bit calculation process for the XY tree RDS=∅; Lu=∅;ld=∅; YXSNL=0; --constructing the reduced destination set (RDS) -For (i=y@S ,i<N,i++)

For (j= x@S,j<N,j++) If (GR(j,i) ∈ DS) then Lu(i)=j; End if; End for; RDS=RDS+GR(lu(i),i)

For (j= x@S,j>=0,j--) If (GR(j,i) ∈ DS) then Ld(i)=j; End if; End for; RDS=RDS+ GR(ld(i),i) End for; For (i=y@S ,i>0,i--)

For (j= x@S,j<N,j++) If (GR(j,i) ∈ DS) then Lu(i)=j; End if; End for; RDS=RDS+GR(lu(i),i) For (j= x@S,j>=0,j--)

If (GR(j,i) ∈ DS) then Ld(i)=j; End if; End for; RDS=RDS+ GR(ld(i),i) End for; ---calculating the number of horizontal and vertical link ----For (i=0 ,i<N,i++)

For (j=0 ,j<N,j++) If (GR(i,j) ∈ RDS) then YXSNL= YXSNL +NLGR(i,j)) End if ; End for ; End for ; With: YXSNL:number of links for the YX tree Figure .11 Pseudo code of VN bit calculation process for the YX tree Finally, we calculate the sum of the number of links for both trees to define the VN bit value. the value of VN bit determines the routing algorithm (the North-Last or the West-Last turn model) that will be applied to route the multicast packet. This method, based on reducing the set of the destinations to establish the VN bit value, induces a large gain in the calculation complexity.

B.2 .3-PROPOSED ROUTER STRUCTURE