Mojtaba Mahdavi

Liang Liu

Ove Edfors

Michael Lentmaier

Norbert Wehn
email: wehn@eit.uni-kl.de

Stefan Weithoffer
email: ‡stefan.weithoffer@imt-atlantique.fr

Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes

Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.

I. INTRODUCTION

Support for extreme data rates in wireless systems beyond 5G (B5G) is essential for many new applications, such as data kiosks, high capacity wireless backhauls, and wireless virtual and augmented reality [START_REF] Weithoffer | Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding (EPIC)[END_REF]. These demanding throughput requirements directly translate to the digital baseband signal processing where channel coding is a main contributor of computational complexity [START_REF] Kestel | When channel coding hits the implementation wall[END_REF] and is subject to major restrictions in terms of silicon area. Achieving Tbps throughputs with FEC schemes that rely on soft decoding require highly parallel and deeply pipelined decoder hardware architectures. Although fully pipelined turbo decoders are expected to reach Tbps for medium block sizes and low number of iterations, they suffer from a large silicon area for block sizes above 100 bits [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF], [START_REF] Weithoffer | Fully pipelined iteration unrolled decoders the road to TB/S turbo decoding[END_REF]. Spatially coupled schemes, allowing construction of a larger code of almost arbitrary length from a much smaller code, may offer a way around this block size limitation.

From a code design perspective, it has been shown that spatial coupling improves the decoding threshold of LDPC codes [START_REF] Kudekar | Threshold saturation via spatial coupling: Why convolutional LDPC ensembles perform so well over the BEC[END_REF], [START_REF] Lentmaier | Iterative decoding threshold analysis for LDPC convolutional codes[END_REF]. Similarly, the concept of spatial coupling has been applied to turbo-like codes, where threshold saturation has also been proven [START_REF] Moloudi | Spatially coupled turbo-like codes[END_REF]. It has been shown that the performance improvement through spatial coupling is more pronounced in serially concatenated codes (SCCs) compared to the parallel concatenated codes (PCCs) [START_REF] Moloudi | Spatially coupled turbo codes[END_REF]. Due to closeto-capacity performance and low error floor, spatially coupled SCCs (SC-SCCs) are selected as the focus of this paper.

From a hardware design perspective, it is worth mentioning that decoding of spatially coupled codes can be done block- wise using window decoding [START_REF] Hassan | Fully parallel window decoder architecture for spatially-coupled LDPC codes[END_REF], [START_REF] Zhu | Braided convolutional codes with sliding window decoding[END_REF], which allows the decoder to be constructed from a set of traditional decoders working on the block size of the smaller code, called subdecoders. These sub-decoders are then chained together and coupled accordingly. This streaming-like decoding has the potential to combine good error correction performance with high throughput and lends itself to a pipelined implementation. However, limitations for fully pipelined hardware architectures with the highest throughput, that already exist for the uncoupled case, such as maximum block size and maximum number of iterations also exist for the coupled case. On the other hand, classical window decoding for spatially coupled turbo-like codes either imposes a minimum block size or a large number of decoding iterations per sub-block of each window. Both may render an implementation ineffective.

In this work we present jumping window decoding (JWD), a new decoding schedule for window decoding of SC-SCC turbo codes that enables, for the first time, fully pipelined implementation. We discuss a conceptual hardware architecture and give implementation estimates for the 12nm technology node based on a characterization of the compute kernels. The remainder of this paper is structured as follows: Section II gives background on SC-SCCs and Section III discusses the classical window decoding and its applicability to fully pipelined decoder hardware architectures. Then, Section IV introduces the proposed JWD, along with a detailed performance evaluation for hardware friendly code design and decoding schedule parameters, as well as 12nm implementation estimates for a fully pipelined decoder hardware architecture with JWD scheduling.

II.SPATIALLY COUPLED SERIALLY CONCATENATED CODES A. Serially Concatenated Codes (SCCs)

SCCs can be described by a compact graph [START_REF] Moloudi | Spatially coupled turbo-like codes: A new trade-off between waterfall and error floor[END_REF] as shown in Fig. 1(a), where the information and parity sequences are rep- The outer encoder receives the information sequence, u t , of length K bits and produces the K-bit outer parity sequence, p O t . Then, the information and outer parity sequences are reordered by the interleaver, Π, to generate

q O t = Π(u t , p O t ). (1)
The inner encoder gets the 2K-bit sequence q O t and produces the inner parity sequence, p I t , of length 2K bits. Finally, the output of the SCC encoder is v t = (u t , p O t , p I t ), which is called a code block and will be transmitted over the channel.

To decode the inner and outer trellises the BCJR algorithm can be employed. To support efficient hardware implementation, the BCJR counterpart in the logarithmic domain, the Log-MAP algorithm, and its simplified version max-Log MAP (MLM) algorithm [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF], [START_REF] Weithoffer | Fully pipelined iteration unrolled decoders the road to TB/S turbo decoding[END_REF] are typically used.

B. Spatially Coupled Serially Concatenated Codes (SC-SCCs)

The SC-SCC encoder is constructed by coupling m + 1 component encoders, where m is the coupling memory. Fig. 2 illustrates the compact graph representation of an SC-SCC with coupling memory m = 1. Each component encoder consists of an outer encoder, an inner encoder, a demultiplexer, and two interleavers, which are connected together as follows.

At time instant t the outer encoder receives a block of information bits, u t , and generates the outer parity sequence, p O t . Then, the pair of (u t , p O t ) are permuted by Interleaver 1 to generate a 2K-bit sequence,

q O t = Π 1 (u t , p O t ).
For coupling memory m, this sequence is divided into m + 1 subsequences of equal length, i.e., q O t,0 , q O t,1 , . . . , q O t,m . The first subsequence, i.e. q O t,0 , is used as a part of the input of the inner encoder at time t and the other ones, q O t,1 , . . . , q O t,m , are used to generate the input of the next inner encoders at time t + 1, . . . , t + m, respectively. Therefore, at time t the sequence is produced by the current and previous m component encoders, which will be permuted using Interleaver 2 (Π 2 ). The permuted sequence is sent to the inner encoder at time t to produce the inner parity sequence, p I t (see Fig. 2). Finally, the output of the SC-SCC encoder at time t is v t = (u t , p O t , p I t ). Since the RSC encoder in Fig. 1(b) has the code rate R = 1/2, the overall rate of the SCC and SC-SCC encoders is R = 1/4. To achieve R = 1/3, which is considered in the following, a part of p I t is punctured. Moreover, we consider a non-terminated encoder, in which the final states of inner and outer encoders at time t are used as the initial states of the inner and outer encoders at time t+1. This concept is shown by double circles (state variable nodes) in Fig. 2.

qO t = (q O t,0 , q O t-1,1 , . . . , q O t-m,m ) (2)

III. FULLY PIPELINED WINDOW DECODING A. Window Decoding

To decode a stream of spatially coupled code-blocks, the window decoding (WD) approach has been proposed [START_REF] Zhu | Braided convolutional codes with sliding window decoding[END_REF], [START_REF] Mahdavi | The effect of coupling memory and block length on spatially coupled serially concatenated codes[END_REF]. To give an example, we consider a decoding window of length W =4 code blocks, which starts at time t and ends at t+W -1, as shown by a solid rectangle in Fig. 2. The leftmost block in the window is referred to as the target block. For all blocks with indices t = t, • • • , t + W -1, first the inner, then the outer decoder perform decoding as follows.

The inner decoder at time t is fed by three sequences: the LLRs of the inner parity bits, the LLRs of the sequence defined in [START_REF] Kestel | When channel coding hits the implementation wall[END_REF], and the a-priori LLRs. The inner decoder then produces the extrinsic LLRs and sends them back to the connected outer decoders. Similarly, the outer decoder receives three sequences: the LLRs of information bits, the LLRs of outer parity bits, and a-priori LLRs. It produces extrinsic LLRs and sends them to the connected inner decoders. Here, the a-priori LLRs of inner(outer) decoder are obtained using extrinsic LLRs of its coupled outer(inner) decoders (for simplicity, the extrinsic LLR exchange is not shown in Fig. 2). This process is repeated I WD times for the current window, to decode the target block, u t , where I WD is the number of iterations per window position. Then, the window is moved by one block to decode the target block u t+1 (see dashed rectangle in Fig. 2).

In the literature, most evaluations of the finite length performance have considered only coupling memory m = 1 [START_REF] Zhu | Braided convolutional codes with sliding window decoding[END_REF], [START_REF] Moloudi | Spatially coupled turbo-like codes: A new trade-off between waterfall and error floor[END_REF], although the asymptotic thresholds are slightly improved for larger m [START_REF] Moloudi | Spatially coupled turbo-like codes[END_REF]. We have demonstrated in [START_REF] Mahdavi | The effect of coupling memory and block length on spatially coupled serially concatenated codes[END_REF] how to use higher coupling memories without increasing the complexity and latency. To this end, for a certain coupling memory, m, the window size should be chosen as W = 2m + 1, which as Π1 to be decoded already decoded 4. High-level schematic of a decoder pipeline for fully pipelined decoding of SC-SCCs with alternating HI pipelines functioning as inner-and outer decoders connected through interleavers, Π, and deinterleavers, Π -1 . In this example, n HI = 8, I eff = 4 are considered and the code blocks are color coded.

Π1 Π1 Π1 Π1 Π1 Π1 Π1 Π2 Π2 Π2 Π2 Π2 Π2 Π2 Π2 -1 -1 -1 -1 -1 -1 -1 -1 W =8 K K Fig.
we have shown in [START_REF] Mahdavi | The effect of coupling memory and block length on spatially coupled serially concatenated codes[END_REF], leads to the best possible performance in the corresponding latency of

L = K • W = K • (2m + 1), (bits). (3)
This enables us to trade between coupling memory and block length in a fixed latency without sacrificing the code strength. Thus, a given latency can be achieved by either large or small blocks. Fig. 3(a) and (b) illustrate this concept for two cases with {W = 4, K} and {W = 8, K = K/2}, respectively, which both have the same latency of L = 4K and their optimal coupling memories are determined by [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF].Since there is W -1 blocks overlap between successive windows, the larger window size, e.g., Fig. 3(b), leads to a larger complexity if the same I WD is used. We define an effective number of iterations,

I eff = W • I WD , (4)
which specifies how often the BCJR is run to decode a certain block. As a result, to have the same complexity in different SC-SCC scenarios, the same I eff should be used, which can be achieved by either small W and large I WD or large W and small I WD as imposed by (4).

B. Fully Pipelined Iteration Unrolled Hardware Architecture

Decoding at more than 100 Gbps has been demonstrated for PCCs in a fully pipelined iteration unrolled XMAP decoder architecture (UXMAP) [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF], [START_REF] Weithoffer | Fully pipelined iteration unrolled decoders the road to TB/S turbo decoding[END_REF]. In this architecture the decoding of the PCC is unrolled onto a pipeline with several halfiteration (HI) stages corresponding to the iterative processing. The HI stages themselves are pipelined implementations of the MLM algorithm. Assuming a completely filled pipeline, this leads to one decoded block per clock cycle at the output. In [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF], the HI stages were implemented not as monolithic pipelines, but as P parallel pipelines, each processing subblocks of K/P for K = 128, and [START_REF] Weithoffer | Fully pipelined iteration unrolled decoders the road to TB/S turbo decoding[END_REF] investigated optimal sizes for K/P for K ≤ 512. In contrast to [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF], [START_REF] Weithoffer | Fully pipelined iteration unrolled decoders the road to TB/S turbo decoding[END_REF], a UXMAP decoder architecture for SC-SCCs needs two different types of HI stages. One for the inner decoder, which processes 2K bits, and one for the outer decoder, processing K bits. Consequently, for a given K, the area complexity of an SCC-UXMAP decoder can be expected to be at least 1.5× that of a PCC-UXMAP, which further limits the maximum block size and the number of iterations. Due the unevenness in the trellis length of the inner and outer decoder iteration stages, the inner decoder iteration stages must, in addition, be implemented with different degrees of parallelism (i.e., via [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF]) for full pipeline utilization. Moreover, in order to realize the spatial coupling, the feedback connections need to be introduced between the HI stages, as illustrated in Fig. 4. For simplicity, there is no distinction made in Fig. 4 between connections for extrinsic, parity, and channel values and, a coupling depth of m = 1 is assumed. The lower bound on the required number of HI stages, n HI , is given by (4) to I eff = W • I WD , provided m ≤ I eff = W • I WD . Thus, at least I eff sub-blocks of an SC-SCC encoded data stream are present in the decoder pipeline with n HI HI stages. In order to fully utilize the pipeline, while preserving the spatial coupling, the number of independently coupled streams fed to the decoder must equal to the pipeline depth of the HI stages.

C. Challenges for Fully Pipelined Classical Window Decoding

In summary, the classical window decoding of SC-SCCs in a fully pipelined decoder architecture is even more constrained in terms of block size, K, and effective number of iterations, I eff , than in the PCC case. Moreover, in case of large decoding windows, W , constraining I eff leads to a very low number of iterations within each decoding window, I WD , following from (4), which results in a poor error correcting performance. To avoid this, larger I WD and consequently larger I eff should be used, which in turn increases the complexity. On the other hand, limiting the decoder to smaller values of W , which would allow for larger I WD , would require larger blocks to benefit from a larger overlap between decoding windows and to keep latency unchanged according to (3). However, the larger block lengths increase the silicon area significantly, as discussed in Section IV-B. Also, small window sizes prevent from employing higher coupling memories since W is upper bounded to 2m + 1 as discussed in Section III.

Moreover, since I WD depends on W and consequently the block length (see ( 4)), the architecture of WD has to be flexible to adjust I WD according to K, which increases hardware cost. To overcome these challenges, we propose below jumping window decoding, a schedule that enables a fixed I eff without sacrificing I WD or requiring large K.

Ieff = 8 Ieff =12 Ieff =16 =1024 =2048 =4096 K=256,W=8 K=128,W=16 K=64, W=32 K=32, W=64 Ieff = 8 Ieff =12 Ieff =16 K=256,W=16 K=128,W=32 K=64, W=64 K=32,W=128 Ieff = 8 Ieff =12 Ieff =16 Threshold(SCC) Threshold(SC-SCC) (a) Eb/N0 (dB) =1024,K=256, W=4 =2048,K=256, W=8 =4096,K=256,W=16 JWD, Ieff =16 WD , Ieff =16

IV. PROPOSED JUMPING WINDOW DECODING (JWD)

The key idea of jumping window decoding (JWD) is to move the decoding window such that the same number of iterations per window position is used for any SC-SCC scenario, regardless of its block length, window size, and latency. This scheme demonstrates that employing small block lengths in a certain latency does not imply that the window has to be moved by small steps, which as stated in (4) leads to a large I eff .

We consider the classical window decoding for the SC-SCCs with the smallest coupling memory, i.e., m = 1, as the reference design where the decoding window is moved by one block. According to (3) for a given latency this is corresponding to the smallest window size, i.e., W ref = 4, and the biggest block and consequently the largest step size for shifting the window (see Fig. 3(a)). Our scheme makes it possible to perform the same number of iterations per window position, I JWD , for an SC-SCC with arbitrary W and K, where

I JWD = I eff W ref . (5)
Accordingly, after I JWD iterations, the window is moved by

∆ = W W ref × K (bits). (6)
Thus, in case of equal latencies in the JWD the window is moved by the same step size, ∆, which is not necessary equal to one block and can be flexible while in the classical WD it is moved by one block, i.e, ∆ = K bits. The processing flow of JWD is illustrated in Fig. 5, where the same SC-SCC scenario as the one in Fig. 3(b) is used. We will show in Section IV-B, a reduced I eff without loss in error correcting performance, which reduces the silicon area of a pipelined architecture.

To clarify the concept of JWD, we present three groups of SC-SCCs in Table I, corresponding to L = 1024, 2048, 4096, where each group includes several combinations of K and W . As an example, I eff = 16, 12, and 8 are assumed to fix the complexity. It can be seen that the number of iterations per window in the traditional scheme, obtained from (4), is very low for small blocks. Also, I WD should be rounded to the nearest integer, which leads to unequal complexity. Moreover, in many cases like the ones with K = 32 and 64 the traditional WD becomes impractical since I WD < 1, which means the complexity budget has to be increased. By employing JWD, the number of iterations per window will be independent of K and W and thus the same number of iterations per window, I JWD , is used for all scenarios in Table I. In this table, I WD , I JWD , and ∆ are calculated using (4), [START_REF] Kudekar | Threshold saturation via spatial coupling: Why convolutional LDPC ensembles perform so well over the BEC[END_REF], and (6), respectively by considering W ref = 4 as the reference. However, other window sizes can alternatively be considered as the reference.

A. Performance Evaluation

We have evaluated the performance of JWD in the SC-SCC scenarios listed in Table I. In each scenario, we use a coupling memory of m = W/2 -1, which has been shown to give the best performance for a given {K, W } [START_REF] Mahdavi | The effect of coupling memory and block length on spatially coupled serially concatenated codes[END_REF]. Fig. 6(a) depicts the BER performance of a JWD and a traditional WD for the SC-SCCs in the first column of Table I. In case of L = 1024 the BER curves of WD and JWD are exactly the same since W = W ref and therefore ∆ = K for both cases. Also, Fig. 6(a) shows that JWD improves the performance by 0.5-0.9 dB and lowers the error floor, e.g., from 10 -3 to lower than 10 -6 in L = 4096. However, it is worth noting that the performance improvement is not the only benefit of using JWD. As discussed in Section III-C, employing the traditional WD for small K is not possible if I eff < W , i.e., low to moderate complexity budget. In such cases, even the lowest number of iterations, I WD =1, results in a large I eff =W , which increases the complexity significantly, prohibiting efficient hardware implementation and achieving high throughput. The proposed scheme, on the other hand, makes it possible to perform decoding for very short block lengths with a lower I eff , i.e., lower complexity, while the performance is equal to or better than the traditional WD approach. Fig. 6(b) illustrates the performance of the proposed scheme and the uncoupled codes, SCCs, for different latencies. Also, the corresponding decoding thresholds, i.e., theoretical limit on the performance [START_REF] Moloudi | Spatially coupled turbo-like codes: A new trade-off between waterfall and error floor[END_REF], are shown by vertical lines. It can be seen that in all cases the proposed scheme outperforms the SCCs by 0.2-0.8 dB. Note, that to have a fair comparison the same complexity is assumed by employing I eff =16 for coupled and uncoupled codes and also the same latency is considered by adjusting K in the SCC equal to L in the SC-SCC.We have investigated the impact of I eff on the performance of JWD for the scenarios listed in Table I. Fig. 6(c), (d), and (e) illustrate the BER curves for L = 1024, 2048, and 4096, respectively. It can be seen that the performance gap between I eff = 8 and I eff = 12 is larger than the gap between I eff = 12 and I eff = 16. Also, as expected, the performance is improved by increasing the latency. Note that the reason of the performance gap between different block lengths at a given latency is the poor performance of short interleavers. This gap could be smaller if the interleavers are designed jointly. The effective number of iterations trades between performance and silicon area, i.e., number of pipeline stages in Fig. 4. Thus, depending on the application, the most efficient value of I eff is specified by considering a performance-area tradeoff.

B. Area Complexity Estimations

To illustrate this tradeoff and demonstrate the impact of JWD, we give hardware estimations for fully pipelined SC-SCCs. It is well established, that the area of fully pipelined implementations for the MLM is dominated by the compute kernels of the MLM [START_REF] Weithoffer | Advanced hardware architectures for turbo code decoding beyond 100 Gb/s[END_REF], [START_REF] Weithoffer | Fully pipelined iteration unrolled decoders the road to TB/S turbo decoding[END_REF], [START_REF] Weithoffer | Advanced wireless digital baseband signal processing beyond 100 Gbit/s[END_REF]: The branch metric unit (BMU), recursion unit (RU) and the soft output unit (SOU) largely determine the area of the inner and outer HI stages:

A inner HI =2 • K • (2 • A BMU + 2 • A RU + A SOU I ) + A FIFO , A outer HI =K • (2 • A BMU + 2 • A RU + A SOU O ) + A FIFO ( 7
)
where the outer decoder stages use SOUs that generate extrinsic information on parities as well (SOU O ) and the inner decoder stages use SOUs, which only generate extrinsics on the information bits (SOU I ). Table II gives placed and route results for radix-4 compute kernels of a UXMAP decoder in 12nm technology for a target frequency of 1000 MHz. The overall area estimate for selected coding scenarios is given in Table III calculated from [START_REF] Moloudi | Spatially coupled turbo-like codes[END_REF] and the total number of HI stages n HI = 2 • I eff . Note, that for this qualitative estimate, A FIFO is not taken into account. However, together with the error correcting performance results for the proposed JWD these qualitative estimates indicate, that the area consumption for a fully pipelined SC-SCC decoder can be drastically reduced through a reduction in I eff without loss in BER performance.

V. CONCLUSION

In this paper, we highlighted the challenges of employing classical WD for the SC-SCCs. We proposed a new decoding approach, called jumping window decoding (JWD), which opens the door for the practical pipelined implementation of the SC-SCCs. We disscussed the necessary modifications to the UXMAP architecture and gave area estimates derived for different SC-SCCs based on PnR results in 12nm technology. Moreover, BER results show that our scheme achieves better performance compared to the classical WD of SC-SCCs and uncoupled SCCs. As such, JWD enables fully pipelined implementation for high throughput decoding of SC-SCCs.

Fig. 1 .

 1 Fig. 1. (a) Compact graph representation of SCC. (b) Structure of RSC encoder, which is used for the inner and outer encoders.

Fig. 2 .

 2 Fig. 2. Compact graph representation of an infinite chain of SC-SCC for m= 1 and block length of K. Two decoding windows with W =4 are shown.

Fig. 3 .

 3 Classical window decoding (WD) for SC-SCC with a latency of 4K bits. (a) {W = 4, K, L = 4K} and (b) {W = 8, K = K/2, L = 4K}.

Fig. 5 .

 5 Fig. 5. Proposed JWD for SC-SCC in Fig. 3(b) with {W = 8, K = K/2}.

Fig. 6 .

 6 Fig. 6. (a) Performance comparison between proposed JWD and traditional WD. (b) Performance comparison of SC-SCC (with JWD) and uncoupled SCCs. Performance evaluation of JWD for different values of I eff , W , and K in latency of (c) L = 1024, (d) L = 2048, and (e) L = 4096 bits.

TABLE I SC

 I -SCC SCENARIOS WITH FIXED LATENCY AND COMPLEXITY.

		I eff	16, 12, 8	16, 12, 8	16, 12, 8	16, 12, 8
		K (bits)	256	128	64	32
	L = 1024	W m I WD I JWD	4 1 4, 3, 2 4, 3, 2	8 3 2, 1.5, 1 4, 3, 2	16 7 1, 0.75, 0.5 4, 3, 2	32 15 0.5, 0, 0 4, 3, 2
		∆ (bits)	256	256	256	256
		K (bits)	256	128	64	32
	L = 2048	W m I WD I JWD	8 3 2, 1.5, 1 4, 3, 2	16 7 1, 0.75, 0.5 4, 3, 2	32 15 0.5, 0, 0 4, 3, 2	64 31 0, 0, 0 4, 3, 2
		∆ (bits)	512	512	512	512
		K (bits)	256	128	64	32
	L = 4096	W m I WD I JWD	16 7 1, 0.75, 0.5 4, 3, 2	32 15 0.5, 0, 0 4, 3, 2	64 31 0, 0, 0 4, 3, 2	128 63 0, 0, 0 4, 3, 2
		∆ (bits)	1024	1024	1024	1024

TABLE III AREA

 III AND THROUGHPUT OF PIPELINES FOR DIFFERENT I eff . Area estimated based on TableII and (7), †: K/Freq.

	Block Size (K)	256	128	64	32
	I eff		Area (mm 2 ) ‡
	16	26.66	13.33	6.66	3.33
	12	20.00	10.00	5.00	2.50
	8	13.33	6.66	3.33	1.66
	Throughput † (Gbps)	204.8	102.4	51.2	25.6

‡

ACKNOWLEDGMENT This work was partially funded by the French National

Research Agency TurboLEAP project (ANR-20-CE25-0007).


François Stoffelbach

Rinaldo Poli
email: poli@lcc-toulouse.fr

ORG/ELECTRONICFILES FOR DETAILS Al(OPr i ) 3 -catalysed halogen exchange processes of relevance to atom transfer radical polymerization: the effect depends on the metal electronic structure

published or not. The documents may come

Al(OPri)3-catalysed halogen exchange processes of relevance to atom transfer radical polymerization: the effect depends on the metal electronic structure

Whether tri(isopropoxo)aluminium catalyses or not halogen exchange for an ATRP catalyst depends on the number of valence electrons.

Since its discovery in 1995, 1, 2 Atom Transfer Radical Polymerisation (ATRP) has become the most actively investigated controlled radical polymerization process. With this technique, the bimolecular terminations are reduced in importance relative to the chain propagation by involving the reactive radicals in a rapid and thermodynamically favourable atom transfer equilibrium by the action of a halogenated spin trap M-X, producing halogen-terminated dormant chains R-X (Scheme 1).

The role of species M, a transition metal complex capable of increasing its formal oxidation state and coordination number by one unit, is to catalyse the chain growth from the dormant species. Thus, ATRP depends critically on transition metal catalysis and a number of studies have been devoted to understanding its mechanistic details. 3,4 It has been shown that the addition of certain Lewis acids, most notably Al(OPr i )3, in conjunction with a number of catalysts such as RuCl2(PPh3)3, 5 CpFeX(CO)2 (X = Br, I), 6 NiBr2(PPh3)2, 7 Ni(PPh3)4, 8 ReIO2(PPh3)2, 9 and CuBr/bipy, 10 results in faster polymerisations and also narrower MW distributions for the resulting polymer. The detailed mechanism of action of this additive, however, is not completely understood, though it appears to be confined to the atom transfer step rather than to the free radical chain propagation. 4 Parallel work has shown that Al(OPr i )3 has no effect on the halogen exchange rate between the RuCl2(PPh3)3 catalyst and a bromide initiator, RBr. 11 This is a relevant observation, because the simplest possible halogen exchange mechanism involves the ATRP intermediates, Scheme 2. Thus, the fact that Al(OPr i )3 accelerates ATRP but not halogen exchange appears rather puzzling.

We have recently shown that a family of half-sandwich Mo(III) complexes catalyzes the ATRP of styrene and acrylates, and that this is accelerated by Al(OPr i )3. 12-14 We wish to report here, using CpMoX2(Pr i 2dad) (X = Cl/I; Pr i 2dad = Pr i N=CH-CH=NPr i ) as a case study, that Al(OPr i )3 does catalyse the halogen exchange process for an ATRP catalyst, and to rationalize the difference relative to RuCl2(PPh3) 3. 11 The accelerating effect of Al(OPr i )3 on the CpMoCl2(Pr i 2dad)- catalysed ATRP of methyl acrylate (MA), initiated by ethyl 2iodopropionate (IEA) was shown previously. 14 In order to gain insight on the Al(OPr i )3 mechanism of action for this ATRP process, a number of EPR investigations were carried out as shown in Figure 1. Warming the solution of the complex under typical ATRP conditions, with or without the IEA initiator, but in the absence of Al(OPr i )3, did not yield any spectral change, (a). In the presence of 1 equiv of Al(OPr i )3, a new peak assigned to the new complex CpMoICl(Pr i 2dad) became evident (b), revealing the catalytic activity of Al(OPr i )3 on the halide exchange. † The nature of the mixed halogen species is proven by the exchange with NaI in THF, which leads, through the same complex (c), to the corresponding diiodide, CpMoI2(Pr i 2dad) (d). The latter has been isolated and fully characterized. § Complex CpMoI2(Pr i 2dad) is a better ATRP catalyst than the dichloride analogue. Under the same experimental conditions (MA/Mo/IEA = 165/1/1 in toluene, 30% v/v, 80°C) the apparent polymerization rate constant kapp is 5.0x10 -5 min -1 with no Al(OPr i )3 and 1.9x10 -3 min -1 with 1 equiv of Al(OPr i )3 [cf. 3.7x10 -4 min -1 for the CpMoCl2(Pr i 2dad)-catalyzed process]. 14 Thus, kapp increases by a factor of 5 on going from the dichloride to the diiodide catalyst. For the Al-containing polymerization, a conversion of 87% was achieved in 19 h, leading to a PMA with PDI = 1.22 (as low as 1.11 at intermediate conversions), see Figure 2. The measured (SEC) n M are only slightly lower than theory, indicating the possible intervention of catalyzed chain transfer. ‡ Unlike the CpMoCl2(Pr i 2dad)-catalyzed process, 14 nothing indicates an initiator efficiency factor f lower than 1.

The observed catalytic action of Al(OPr i )3 on both the ATRP of MA (the dormant species being a -CH2-CH(I)-COOMe terminated polymer) with either CpMoCl2(Pr i 2dad) or CpMoI2-(Pr i 2dad), and on the halogen exchange between CpMoCl2-(Pr i 2dad) and CH3CH(I)COOEt, provides persuasive evidence that the processes involve the same intermediates (Scheme 2).

M-X + R-Y + R M-Y + R-X M X Y Scheme 2.

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Now the interesting question is why the RuCl2(PPh3)3 system exhibits a selective acceleration of ATRP with no effect on halogen exchange. The logical explanation is that a second halogen exchange pathway, at lower energy, is viable for the Ru complex, but not for the Mo complex, and that this second pathway is not catalyzed by Al(OPr i )3. Complexes of type RuX2L3 have a 16-electron configuration and are in principle capable to coordinate an additional 2-electron donor ligand. We can therefore easily imagine an equilibrium involving coordination of the halogenated dormant species to the Ru(II) centre, enhancing the C atom electrophilicity and triggering an internal nucleophilic substitution (SNi), see Figure 3.

Complexes of type CpMoX2L2, on the other hand, have a 17electron configuration, thus addition of a 2-electron donor would lead to an unstable 19-electron complex. In order to obtain supporting evidence for this hypothesis, DFT calculations & were carried out on the model systems RuCl2(PH3)3 and CpMoCl2(PH3)2 (a model of CpMoCl2(PMe3)2, which also acts an ATRP catalyst) 12 and on their adducts with RCl [R = CH3, CH(CH3)COOCH3] as models of initiators or dormant polymer chains.

As expected, the addition of either RCl molecule to the 17electron Mo complex turned out repulsive. No stable local minimum for a 19-electron CpMoCl2(PH3)2(RCl) complex could be optimized. Conversely, addition of RCl to RuCl2(PH3)3 afforded stable adducts, as shown in Figure 4. These adducts are in fact lower in energy than the sum of the separated molecules, though a large negative entropy results in a positive free energy at 298 K for the addition process [calculated G°298 = 7.3 and 3.9 kcal mol -1 for R = CH3 and CH(CH3)COOCH3, respectively]. Isomeric adducts where RCl occupies a position trans to a Cl ligand are also local minima, but slightly higher in energy.

The Lewis acidic Al(OPr i )3 can in principle interact only with nucleophilic centers, such as the negatively polarized halogen ligands. Therefore, it seems logical that the presence of Al(OPr i )3 would have no effect on the SNi mechanism. The question remains of how this additive catalyzes the atom transfer process. A possibility that should be considered is a greater Lewis acid-base interaction with the halogen lone pairs in the MXY intermediate (Scheme 2) and also in the transition state that leads to it, where these atoms are more negatively polarized relative to the organic initiator/dormant chain. Additional calculations are in progress to verify this hypothesis, as well as to probe the entire reaction coordinate for the different mechanisms (atom transfer and SNi) leading to halogen exchange.

We thank the CNRS and the Conseil Régional de Bourgogne for financial support and for a Ph.D. fellowship to FS, CINES and CICT for granting free computational time, Mr B. Rebière for the X-ray analysis, and Dr. José Mata for a verification experiment.

Notes and references † The same phenomenon was observed for the Cl/Br exchange using BrEA. § Cyclic voltammetry (THF): irreversible oxidation at Ep,a = 0,17 V. A single crystals used for the X-ray investigation were obtained by slowly cooling a saturated toluene solution to -30°C.

Fig. 1

 1 Scheme 1.

  Crystal data: C13H21I2N2Mo, M = 555.06, orthorhombic, a = 12.4552(3), b = 17.2336(6), c = 7.7943(2) Å, U = 1673.03(8) Å 3 , T = 110(2) K, space group Pnma (no. 62), Z = 4, µ(Mo-K) = 4.462 mm -1 , 6813 reflections measured, 1983 unique (Rint = 0.0338) which were used in all calculations. The final wR(F 2 ) was 0.0478 (all data). The data have been deposited with the Cambridge Crystallographic Data Centre (number CCDC-243377) ‡ The growth of PDI at high conversions in the presence of transfer to monomer is well understood, see K. Matyjaszewski, ACS Symposium Series 1998, 685, 2. & Geometry optimizations were carried out at the B3LYP level. The LANL2DZ basis, augmented with an f polarization punction ( = 0.8) was used for Mo and Ru. All other atoms were described with 6-31G* bases. No symmetry constraints were used and all normal modes had positive frequencies for all converged geometries. T. Ando, M. Kamigaito, and M. Sawamoto, Macromolecules, 2000, 33, 2819. 12 E. Le Grognec, J. Claverie, and R. Poli, J. Am. Chem. Soc., 2001, 123, 9513. 13 F. Stoffelbach, R. Poli, and P. Richard, J. Organometal. Chem., 2002, 663, 269. 14 F. Stoffelbach, D. M. Haddleton, and R. Poli, Eur. Polym. J., 2003, 39, 2099.

Fig. 2 .Fig. 3 .

 23 Fig. 2. Left: n M (diamonds) and PDI (triangles) against conversion for PMA obtained from CpMoI2( i Pr2-dad)/Al(O i Pr)3/IEA (MA/Mo/IEA/Al = 165/1/1/1) in toluene (30% v/v) at 80 °C. The line corresponds to the theoretical n M . Right: first order kinetics.

Fig. 4 .

 4 Fig. 4. DFT study of the RCl addition to RuCl2(PH3)3 (R = CH3, CH(CH3)COOCH3)

Graphical Content Entry

Text for graphical abstract:

Tri(isopropoxo)aluminium is found to catalyse halogen exchange between metal complex and organic halide initiator, as well as ATRP, when using a 17-electron half-sandwich molybdenum(III) compound.