Prologue

This document presents my research activities since my recruitment at the University of Nantes in September 2004. These activities were successively carried out within the IREENA laboratory (Institute for Research in Electronics and Electrotechnics of Nantes Atlantique) until 2012, then within the IETR laboratory (Institute of Electronics and Digital Technologies). The scope of these activities corresponds to the design of hardware and software architectures of embedded electronic systems. In this context, my research activities have focused on the definition of methods favouring the modelling and simulation of hardware and software architectures in order to optimize them under time, cost and energy constraints.

In this document, during the presentation of each of the covered topics, I report on the framework of this work, the nature of the contributions made and the approach undertaken. In doing so, I also explain my role in the supervision of the students who participated and contributed to this work and more broadly the collaborations set up. This synthesis tries to reconcile clarity and precision of the explanations. This document has three main parts. The first part corresponds to a detailed CV, summarizing in particular my professional experience with regard to the various activities carried out in research and teaching. The second part details in five chapters the research activities carried out since obtaining the doctoral degree, retracing the most significant results. Finally, the third part presents an assessment of the activities carried out and establishes a potential research program taking into account the identified prospects. Attached to this document is a detailed list of my publications.

B Summary of teaching activities B.1 Teachings

Since my recruitment in 2004 at the University of Nantes, my teaching activities have mainly been carried out at Polytech Nantes, the engineering school of the University of Nantes. These activities are divided into two distinct formations: within the Electronics and Digital Technologies (ETN) department preparing for the engineering degree and within the framework of the International Master program in Wireless Embedded Technologies (WET) (formerly Electronic Systems and Electrical Engineering, SEGE) from the University of Nantes. I participate to these two formations through different modules related to the field of embedded computer systems. By way of example, Table 1 indicates the distribution of courses I taught during the 2019-2020 academic year. These different courses are divided into lectures, tutorials, practical work and projects. Since 2004, my teaching load corresponds to an average annual volume of 275 hours (tutorial hours). I describe here more particularly the courses for which I am currently responsible or for which I significantly contribute.

• Design of digital circuits: this course focuses on methods, languages and tools for the design, simulation and production of digital circuits. I am responsible of lectures, tutorials, practical work as well as introduction sessions for incoming students in the fourth year of the ETN department. Over the years, the changes that I have made to this teaching relate to different aspects: teaching in English for a group of tutorials, introduction sessions for incoming international students, evolution of the progress of the project in order to ensure better acquisition with students, rewriting and reorganization of course material, addition of online tests for student self-assessment.

• Microprocessor systems: this course focuses on learning the operation of hardware and software resources that constitute a microprocessor system. I provide lectures, tutorials and practical work. Over the years, I have developed this teaching on different aspects: teaching in English for a tutorial group, change of microcontroller boards and development tools used in practical work, management of the electronic boards loan to the students (Microchip SAMD21), rewriting and reorganization of the course material, the content of the tutorials and the project covered in practical work, addition of online tests for student self-assessment.

• SoC design: this course focuses on learning advanced methods for designing systems on chips. This teaching is provided within a last year option of the ETN department (entitled Real-Time Embedded Systems). I provide the lectures, the follow-up of the case-studies approached by the students and the practical work. Over the years, I have developed this teaching on the following aspects: rewriting and 1 Modules for which I am responsible reorganization of the course material, use of new FPGA-based electronic boards (Xilinx ML402, Xilinx Zedboard), setting up of practical work sessions on the design of SoC using the Mentor Graphics and Xilinx Vivado suite of tools, conference by an engineer from industry on the subject of circuit testing.

• Hardware/software codesign: this course focuses on methods and languages (SystemC) for the joint design and verification of hardware/software resources of embedded systems. This teaching is provided within a last year option of the ETN department. I provide lectures and practical work. Over the years, I have developed this teaching on the following aspects: rewriting and reorganization of the course material, use of new FPGA-based electronic boards (Xilinx ML402, Xilinx Zedboard), set up of new practical works on SystemC.

• Architecture of embedded systems: this course focuses on the use of advanced resources of a microcontroller (sensor management, optimization of consumption, use of a DMA controller). This teaching is provided within the last Real-Time Embedded System option of the ETN department. For this teaching, I set up and I take care of the practical work sessions. I also set up a conference given by an engineer from industry on the subject of power management within embedded systems.

• Digital circuit design methodology: this course focuses on methods, languages and tools for the design, simulation and production of digital circuits. This teaching is given in English to students of the Master WET program. I set up this module and I provide lectures and practical work.

• Evaluation of the performance of embedded system architectures: this course focuses on learning the methods used to analyze the temporal properties of embedded system architectures (discrete event simulation, formal analysis methods). This teaching is given in English to students of the Master WET program. It is intended to be complementary to the teaching of codesign provided in the engineering degree with a particular focus on certain research works in this field. I set up this module and I provide the lectures.

In summary, my teaching activities focus on the use and design of the typical hardware and software resources of embedded systems. The following figure illustrates the distribution of the various lessons carried out, also positioning those carried out more episodically since 2004.

Hardware resources specification

Software resources specification

Requirements

System specification

Hardware/software resources definition and partitioning

Logic gates Assembly code

Validation and verification on real prototype

Detailed verification

Hardware description language Programming language Low level verification

B.2 Responsibilities and services to the community

I participate in the organisation of the ETN department of Polytech Nantes. I was thus able to take on the following responsibilities:

• 2005-2006: Responsible for international internships for the ETN department. This responsibility consisted of supporting students in their search for an international internship.

• 2006-2012: Responsible for the 3rd year of training within the ETN department. This responsibility involved setting up timetables, organizing semester juries and monitoring students.

• since 2015: Responsible for monitoring end-of-study internships for the ETN department. This responsibility consists of supporting students in their search for internships, the distribution of internship offers, the assignment of supervisors, the intervention of industrial partners presenting the electronics professions, interaction with the 'Company relationship' service of Polytech Nantes.

I was in charge of the organization and animation of two improvement councils of the ETN department. The first council took place in April 2017 and focused on the theme of follow-up and evaluation of internships. It allowed an assessment of the systems put in place within the ETN department in the monitoring of internships during the three years of training. The second council took place in October 2019 and focused on the theme of entrepreneurship. It allowed an assessment of the various actions implemented within the ETN department and to identify the changes required to raise awareness among students in the department about business creation.

From the 2017-2018 school year, I ensured the implementation of a new procedure for monitoring and evaluating end-of-study internships based on skills. This procedure was initially applied to the ETN department and then extended to Polytech Nantes. At Polytech Nantes, I have been part of the working group on internships since 2018. Since 2021, I have participated in the working group on the creation of a FabLab at Polytech Nantes. I participated in the implementation of two partnership agreements between companies (ReflexCES and STMicroelectronics) and the Polytech Nantes school. Since 2017-2018, I have been organizing with the company MicroChip, a half-day visit to the Nantes site of this company for final year students of the ETN department. This visit is an opportunity for a presentation of the different activities of the company and potential positions. The constructive collaborations with these companies have benefited the students of the ETN department (technical projects, end-of-study internships, hiring) and the school (numerous donations of materials used in teaching and research, conferences by industrial speakers). I participated in the seminar organized in November 2017 by the RFI Ouest Industries Créatives, on the theme "Creative methods used in educational transformation". The objective was to work on the redesign of teaching modules by adopting creative methods.

Every year, I participate in the school's various recruitment and promotion actions: open days, student fairs, recruitment interviews, presentations at IUTs (institutions of higher education providing technician level training). As such, in 2016 and 2017, I made various films for the presentation of the ETN department, final year options and student projects. These films are currently available on the school's website 2

C Summary of research activities C.1 Addressed area of research

The topic addressed in the context of my doctoral thesis was the optimization and implementation of digital communication algorithms on heterogeneous platforms, combining programmable signal processing processors and dedicated hardware resources. This experience was an opportunity to discover the many facets and research issues associated with the design of embedded system architectures. This area of research evolves according to the requirements in applications and possibilities of execution platforms. Thus, since the early 2000s, the constant increase in the dissemination of embedded systems, described in particular in [1], has led to the emergence and concretization of concepts such as the Internet of Things, data science and embedded artificial intelligence. This development requires mastering the complexity of the hardwaresoftware architectures of embedded systems in order to allow the design of devices operating under numerous constraints (functionalities, cost, size, reliability, execution time, power and energy consumption, etc.). The field of research in the design of embedded system architectures contributes to this in particular by proposing approaches, methods, models and tools used by the various participants in the design process.

Since my integration at the University of Nantes in 2004, my research activity has gradually focused on system-level design and on the evaluation of the performance of hardware and software architectures. The objective of this work is to promote the modelling and analysis of architectures in order to allow optimized definition of resources under time, power consumption and cost constraints. The positioning of the work carried out in this context is illustrated in Figure 2.

Hardware resources specification

Software resources specification

Requirements

System specifications

Hardware/software resources definition and partitioning

Logic gates Assembly code

Validation and verification on real prototype

Detailed verification

Hardware description language Programming language Low level verification

High level verification

 System-level modelling and simulation The objective of this work relates to the definition of methods favouring the creation of performance models used for the definition of hardware and software resources of architectures. The originality of this work lies in the combination of the aspects covered: simulation, formal modelling, static analysis and online management, implementations and measurements on real targets. Also, this work was inspired by case studies from different fields of application (mobile radiocommunication, automotive, image processing). This work and the contributions made are detailed in the following chapters of this document. The supervision activities and collaborations set up are listed below.

C.2 Supervision activities

C.4 Publications

Over the period 2004-2021, since my installation at the University of Nantes, my scientific publications are distributed as follows:

• 7 publications in international journals • 24 publications in international conferences • 5 publications in national conferences

• 6 technical reports and project deliverables

The publications made as part of my doctoral thesis from 2000 to 2003 are divided into: 2 publications in international journals, 1 publication in a national journal, 3 publications in international conferences.

The full list of these publications is given in the appendix to this document.

C.5 Member of boards and committees

Introduction

This chapter introduces and positions my research activities carried out since my installation at the University of Nantes in 2004. This work falls within the field of the design of hardware and software architectures of embedded systems. It focuses more particularly on design activities at the so-called system level, that is to say located at the earliest stage of the design process, where the choices of architectures are initially made. The challenges associated with this field of research come from the need to master the complexity of designing architectures. This complexity is induced by the constant increase in the density and diversity of the hardware and software resources that constitute architectures. Therefore, the objective of this work is to improve design practices by proposing methods used for defining under constraints and verifying the non-functional requirements of the architectures (in our work, time, power consumption and cost). This chapter first presents the context of the research work as well as the addressed issues. The nature of the contributions made is then presented. Finally, the organization of this document is explained.

Context

Evolutions and trends in the design of hardware-software architectures of embedded systems

A simple observation of the objects manipulated by everyone in our everyday life underlines the strong dissemination of electronic devices. These devices are embedded in equipment belonging to numerous and varied fields of application. The notion of embedded system designates those devices for which the internal architecture consists of an association of hardware and software resources. The design of these architectures strongly depends on the constraints specific to the field of application: constraints on the cost of the solution, execution time, electrical power consumption, robustness, security, dependability. Gradually, the evolution of manufacturing technologies [2] has led to hardware resources that are ever denser in number of transistors and therefore capable of supporting many uses. These hardware resources then make it possible to support the execution of software whose complexity is measured in terms of millions of lines of code that can be executed. This technological evolution is accompanied by a necessary evolution of design practices. This allows the complexity of the designed systems to be controlled. These practices are essential in order to guarantee the development of hardware and software architectures under specific constraints and this according to constrained development time and costs.

In 1983, Daniel Gajski and Robert Kuhn proposed in [3] to organize electronic circuit design practices according to three complementary points of view: the physical point of view, the behavioural point of view and the structural. It was proposed to consider these points of view according to three levels of detail according to which the hardware resources of a circuit can be described: the transistor level, the logic gate level, and the architectural level (also called register transfer level). The design process of hardware resources can thus be presented as a transformation of a behavioural representation (the what) into a structural representation (the how) which, associated with a progressive refinement from the architectural level to the transistor level, leads to an actual realization in a given manufacturing technology. This proposal underlines the need to organize the design based on structuring principles that can guide the designer in his work.

During the 1990s, integrated circuits made it possible to support complete systems on a chip, combining processor cores, local memories and dedicated hardware resources. To appropriately design these systemson-chips (SoCs) and meet the related constraints, the selection of hardware and software resources must be carefully optimized. Different approaches, such as those presented in [4], emerged in order to guide the designer in the phases preceding the partitioning between hardware and software and the joint optimization of resources (hardware-software codesign) . Various proposals were made in order to establish levels of abstraction higher than the architectural level [5], [6] in order to capture the specificities of hardware and software resources at the earliest stage of the design process. Also, given the preponderant influence of interactions between resource categories, the importance of distinguishing computation mechanisms from communication mechanisms as soon as possible was highlighted [7], [8]. Added to these trends is the need to promote the reuse of existing resources (Intellectual Property, IP), at the different levels of abstraction in the design process. The concept of platform-oriented design (platform-based design) emerged [9] in order to have generic and easily adaptable execution supports according to application needs.

During the 2000s, systems-on-chip integrated several heterogeneous processors whose characteristics differ according to the specificities of the software to be executed. These years saw the emergence of so-called system-level design languages (SLD) including SystemC, standardized in 2012 [10], SystemVerilog [11] and SpecC [12]. These languages are adapted to the description of the characteristics of hardware and software resources. They notably support the separation of communication and calculation mechanisms as well as the possibility of modelling and simulating an architecture according to different levels of abstraction. Thus, these languages were used to carry out various design activities (resource sizing, software modelling and validation using virtual prototypes, integration of hardware-software resources) and were adopted by industry [13].

The evolution observed during the 2010s tends towards the integration of multi-core processors and an ever-increasing number of hardware resources within systems on chips. As underlined in [14] and [15], this constant increase in the complexity of systems justifies consolidating the methods used at the system level in order to favour the dimensioning under constraints of hardware-software architectures. According to these tendencies, system-level design therefore plays an essential role in the design process due to the fact that any modification of the initial choices generates additional costs that are all the higher as they are detected late.

Principles of electronic system-level design

As mentioned previously, electronic system-level design (ESL) aims to establish a hardware-software resource architecture that meets the different requirements of the system under study. Figure 1.1 illustrates some of the principles previously mentioned through the Y diagram used in 2009 by Gajski in [16] 1 . This figure positions in particular the design activities at the system level. These activities assume the use of models capturing the different aspects of the studied architecture and making it possible to estimate its particular properties and to check compliance with the constraints. As illustrated in Figure 1.1, modelling a hardware-software architecture supposes to consider the following different aspects2 :

• Functional view: it is described independently of the targeted technologies, focusing on the expected functionalities for the studied system. This view is represented according to two complementary approaches: structural and behavioural. This representation is generally based on the use of a computational model (MoC, model of computation) adapted to the characteristics of the functionalities to be described [18].

• Executive view: it displays the components capable of realizing the elements of the functional view. These components are conventionally classified into computation resources, communication resources and storage resources. Subsequently, we will also use the term platform to refer to this view.

• Physical view: designates the result of the deployment, the allocation, of the elements described in the functional view onto the components of the executive view. The Y diagram with detailed at the system level, inspired from [16]. The main activities led at the system level are identified.

Physical description

Structural description

Behavioral description

Circuits

As indicated in Figure 1.1, complementary activities are associated with the establishment of these views, in order to favour the selection of resources (through the estimation of the complexity of the elements of the functional architecture) and to establish policies for arbitration and scheduling of shared resources.

The obtained physical architecture corresponds to a description of the hardware and software resources that will have to be implemented in given hardware description and programming languages. To evaluate the relevance of the architecture choices, the physical architecture is used beforehand in order to evaluate the performances delivered: we then speak of a performance model. The term performance here designates any property that can be estimated (e.g., end-to-end latency, input or output throughput, energy consumed). This representation is used in order to evaluate the relevance of the architecture choices and to carry out an appropriate dimensioning. As we will detail later, this representation requires prior estimations made in order to characterize each element of the model (e.g., execution time of a function of the functional view on a computation resource of the executive view). These estimates come from knowledge on the elements of the model (resulting from measurements on target or from results of detailed simulations). The analysis of these models therefore makes it possible to quantify the performances achieved. By considering different configurations of physical architectures, it is therefore possible to explore a given design space in order to identify an optimized architectural solution that best satisfies the constraints considered.

Different approaches can be adopted in order to analyze the properties of the performance models thus created. As illustrated in Figure 1.2, the efficiency of these analysis methods can be judged considering the criteria of accuracy and speed of analysis. As presented in [19], it is common to classify these approaches into two categories:

• Simulation-based approaches: they consider a performance model that can be executed and thus allow the analysis of the evolution of the architecture model according to different operating scenarios. However, they suppose an intensive evaluation in order to be able to cover many possible operating situations, without guaranteeing an identification of the worst execution cases. Part (a) of Figure 1.2 illustrates the effectiveness of simulation-based performance evaluation methods according to the level of abstraction considered. It is commonly established that an accuracy of the order of 10 % can be achieved with such models and this for a reduction of a factor greater than 1000 in simulation time compared to models accurate to the cycle of clock near [16]. Examples of academic approaches based on system-level simulation are presented in [20]. As illustrated in Figure 1.2, simulation traditionally leads to underestimating the properties with regard to the worst case of operation. This is especially due to the difficulty in establishing the required stimuli allowing to identify the boundary situations.

• The so-called formal approaches: these consider an expression of the properties of the architecture studied according to a precise mathematical formalism. Two categories of formal approaches can be identified: those based on analytical expressions of the properties to be evaluated (analytical approaches) and those based on the exploration of the space of possible operating states (state-based approaches). Such approaches are notably presented in [21], [22]. Notably, some of these approaches allow a more exhaustive exploration of the possible operating situations in order to allow the evaluation of the worst execution cases. Part (b) of the figure 1.2 illustrates the relative position of these different evaluation approaches according to the criteria of accuracy and analysis effort. Analytical approaches (distinguished between holistic and compositional in the figure 1.2) traditionally lead to over-estimates with respect to the worst operating case. So-called state-based approaches turn out to be limited in terms of the complexity of the systems that can be considered given the explosion of the space of states to be analyzed.

In [R1-1], we detailed and compared different approaches recently used for performance evaluation of multiprocessor architectures of embedded systems. As discussed in the next section, the nature of the platforms considered and the way their basic components are associated significantly influence the effectiveness of these approaches.

Issues and addressed problems

The functional and non-functional requirements applied to embedded systems lead to an increase in the complexity of the platforms used. This complexity is reflected both in the micro-architecture of the processors and in the overall architecture of the platforms. Current trends correspond in particular to an increase in the execution parallelism offered. Thus, these platforms are increasingly multiprocessor and multicore in nature in order to deliver high computing performance and optimized energy consumption. The organization of these platforms then consists of a set of processors, of identical or distinct natures, interconnected through networks or communication buses and having different levels of memory hierarchy [23], [24]. In this context, the complexity of design lies in the number and diversity of resources to be apprehended but also in the nature of the interactions between resources. The influence of possible interactions between computing resources can be evaluated according to the so-called compositionality criterion (compositionality) [25]. This criterion expresses the degree to which the behavior of a given system can be induced from the behaviors of each of its constituents. This property depends on the influence of shared resources and therefore on the level of interdependence between components. Figure 1.3, inspired by the classification proposed in [26], positions the possible organizations of a multiprocessor system according to the degree of compositionality and the influences of the shared resources. According to this classification, a so-called fully compositional organization (fully timing compositional) presents limited interactions allowing to deduce the global properties of the architecture taking into account the properties of each elementary component. Conversely, an organization that does not present the property of compositionality will bring into play phenomena that do not allow such a deduction, further complicating the prediction of non-functional properties. The complexity of the architectures to be considered leads to a difficult coverage of the operating cases which can lead to the non-detection of problematic situations and therefore a non-respect of certain constraints. Late detection in the design process of such defects can lead to additional costs for projects or even serious failures in the case of systems in operation. Thus, the quality of the system-level models used for the prediction of the non-functional properties of the architectures proves to be essential in order to allow an analysis and an effective dimensioning. There are two observations that motivate my work:

• the modeling effort at the system level must be controlled while allowing the creation of models presenting a satisfactory compromise in terms of speed of analysis and precision.

• The effort of analysis (of simulation in the case of the work presented below) must be mastered to allow the study of ever more complex architectures within reasonable timeframes.

These two points motivate the contributions made in order to favor the analysis and the optimization of the performances of the architectures during the design of the systems. In addition to these two axes, the dynamic management of resources (that is to say during operation) also represents an interesting approach in order to promote the optimization of the performance of architectures. In the field of multiprocessor architectures, such an approach leads to adapting the use of hardware resources in order to optimize the overall performance under constraints of execution time or power consumption. Thus, through certain co-supervised theses, I was also able to take an interest in this field both in order to propose original management strategies and also in order to promote the modelling and simulation of such management. The contributions developed in the context of my research therefore fall within these three axes. As mentioned previously, the research work carried out was organized around three complementary axes: the creation of performance models, the improvement of simulation efficiency and the study of online resource management. Each co-supervised thesis was an opportunity to approach these axes in an original way.

Contributions to improving system-level simulation efficiency

Given the increasing complexity of embedded system architectures, improving simulation efficiency is an important issue. A first contribution focused on the definition of a simulation approach and aimed at reducing the required analysis times while preserving the accuracy of the estimates obtained. This approach is hybrid in nature: it combines simulation and formal models. This approach aims to reduce the number of calls to the simulation engine by disregarding the many processes generated by traditional simulation approaches at the system level. The principles associated with this method are detailed in Chapter 2 of this document.

Different case studies made it possible to quantify the potential contribution of the proposed simulation approach. These case studies focus on different hardware-software architectures of embedded systems. Two case studies of significant complexity are presented in Chapter 3 of this document. The first presented case-study corresponds to the analysis of a distributed architecture of embedded controllers for the automotive field. The second presented case-study focuses on the analysis of a multiprocessor architecture built around the ARM AXI4-Lite bus standard.

Secondly, I was interested in the adoption of statistical model-checking simulation (SMC) methods for the analysis of the temporal properties of multiprocessor architectures. The interest of such methods is to control the coverage of the simulations carried out on performance models. The adoption of these methods and the associated modelling flow are presented in Chapter 5.

Contributions to the creation of system-level models of hardware-software architectures

First, a generic execution model has been proposed to serve as a basis for modelling and simulation at the system level. The objective of this model is to favour the creation of simulable models used for performance evaluation of hardware-software architectures. The principle of this model is presented in Chapter 2 of this document in connection with the proposed simulation approach.

Different case studies have validated the proposed generic model. A first case study is presented in Chapter 3 and concerns the modelling of communication resources for multiprocessor architectures. A second case study concerns the modelling of computing resources for systems in the field of mobile radiocommunication. This case study is presented in Chapter 4 of this document.

Secondly, I was interested in the contribution of probabilistic models and their creation according to an approach based on measurement (measurement-based probabilistic timing analysis) within the framework of the study of multiprocessor systems. The purpose of this approach is to obtain reliable estimates used to correctly calibrate performance models. The approach developed is presented in Chapter 5. The accuracy and speed of the models created are evaluated on case studies in the field of image processing.

Contributions to online management of hardware-software architectures

A first line of work focused on the modeling of systems for which the nature of the functionalities supported, and therefore the workloads induced, evolve during operation. A first contribution focused on extending the modelling and simulation possibilities of such architectures within the CoFluent Studio environment. This contribution was then used in the so-called software radio context in order to allow the performance analysis of a mobile radio terminal according to different use cases. This work is presented in Chapter 4.

Secondly, still in connection with the study of systems whose supported functionalities evolve during operation, different allocation and scheduling strategies have been proposed in order to optimize the energy efficiency of multiprocessor platforms. These strategies were applied within homogeneous and heterogeneous sets of processors. This work was evaluated by the study of different data flow oriented applications in the multimedia domain. Also, a simulation approach has been proposed in order to allow the simulation of the online management of computing resources. The proposed strategies and the simulation approach are presented in Chapter 4 of this document.

Organization of the document

The following four chapters detail the contributions made. Chapter 2 presents the principles associated with the hybrid modelling and simulation approach proposed in order to favour the creation of hardware-software architecture models with increased simulation speed and a preserved level of precision. Chapter 3 deals with the study of hardware-software architectures for which the modelling of communication resources is essential. The contribution of the approach presented previously is thus illustrated and the gains in terms of simulation speed are evaluated. Chapter 4 presents the work carried out for the modelling of computation and memory loads as well as the online management of the computing resources of multiprocessor architectures. Chapter 5 presents the adoption of probabilistic models and methods for the analysis of the temporal properties of MPSoC architectures. Finally, in the appendix to this document, the list of publications and references used in this document are given.

Publications related to Chapter 1

Research report Chapter 2

Contributions to system-level modelling and simulation

Introduction

This chapter presents the work carried out in the field of system level design in order to improve the efficiency of the models used for the evaluation of the performances of the hardware-software architectures of embedded systems. In this field, many approaches have been proposed to promote the creation of simulable models of such architectures [20]. These models are used to estimate and compare the performance of candidate architectures early in the design process; they thus make it possible to explore the design space. In the case of simulation-based approaches, the models are executed according to the principles of discrete-event simulation in order to account for parallelism and synchronizations within the studied architectures [28]. In this context, the role of the simulation engine resides in the advancement of the simulation time and the management of the various processes constituting the models created. The proposal made in this work aims to limit the number of calls to the discrete-event simulation engine while seeking to preserve the accuracy of the models considered.

The work carried out led to the definition of a hybrid approach, combining simulation and calculations, and leading to significant gains in terms of simulation speed while preserving the accuracy of the estimates. This chapter specifies the nature of the contribution made and the methods and models proposed. We also discuss some results illustrating the potential and limitations of this approach.

This work finds its origin in some of the proposals of the thesis of Mr. Anthony Barreteau carried out from 2007 to 2010 and during preliminary discussions with Professor Jean-Paul Calvez. The research leave conducted in 2012-2013 was an opportunity to develop and concretize these ideas. Since then, this approach has been extended and tested through various case studies and also as part of Mr. Dharmender Singh's Master's internship in 2018.

Addressed issue

The principles related to the modeling of a physical architecture at the system level have been mentioned in chapter 1. The functional view of an architecture is organized in the form of elements subsequently called functions or actors, interacting through coupling relationships. Function behavior typically corresponds to a sequence of computational and communication primitives. Control statements (e.g., finite iteration, infinite iteration, alternate) are used to establish the sequence of these primitives. At this stage, we are not making any assumptions about the nature of the communication mechanisms used, as these may be of different natures (synchronization without data exchange, shared variable, message queue, appointment). Part (a) of the 2.1 figure gives an example of the organization of a physical architecture represented from the functional and executive views.

The functional structure represented comprises four functions, noted from F 1 to F 4 , interacting through coupling relations, M 1 to M 6 . These elements are allocated on the resources of an executive platform Executable model described in a system level language made of two computation resources (here, programmable processors) connected through communication resources (interfaces, bus and shared memory). It is important to understand that such models do not necessarily integrate the functionalities provided by the application: they express the workloads induced by the application (workload model). Part (b) of figure 2.1 illustrates the behavioral description of functions using a computation primitive (Execute) and two primitives for writing and reading through message queues (WriteToken, ReadToken). Such a description serves as the basis for the creation of executable models described in a programming language supporting the mechanisms expressed within the architecture model (e.g., SystemC, SpecC). Among the approaches in the academic field that implement these principles, we can cite SCE [START_REF] Dömer | System-on-chip environment: A specc-based framework for heterogeneous mpsoc design[END_REF], Sesame [START_REF] Erbas | A framework for system-level modeling and simulation of embedded systems architectures[END_REF], SystemCoDesigner [START_REF] Keinert | Systemcodesigneran automatic esl synthesis approach by design space exploration and behavior synthesis for streaming applications[END_REF] as well as those presented in quoteKangas-06,Kreku-08,Arpinen-09. Among the industrial approaches, we can cite the Intel CoFluent Studio [27], Space Codesign [32] and Visualsim from Mirabilis Design [33] environments. These approaches differ in particular according to the model of computation considered to describe the applications, the programming language used to describe the executable models or the possibility of automatically generating lower-level descriptions.

Discrete event simulation kernel

During the execution of such a model, each primitive involves a workload on the communication and computational resources of the platform (e.g., number of operations to be performed, size of data to be swap). The computation or communication times associated with these workloads must therefore be established. Their values typically come from analyzes carried out elsewhere, through measurements on real prototypes, detailed simulations or static analyzes of the codes associated with each function, as illustrated in [START_REF] Kreku | Combining uml2 application and systemc platform modelling for performance evaluation of real-time embedded systems[END_REF]. The evolution over time of an architecture model thus formed reflects the workloads successively induced by the application, and this taking into account the limited capacities of the resources of the platform. Figure 2.2 illustrates such an evolution for the example of figure 2.1.

Platform resource usage is observed as the application runs. The specific simulation instants, symbolized by vertical arrows, correspond to the start and end times of the execution of the computation and communication primitives of the application. They correspond to the instants of call to the simulation kernel in charge of the execution of the processes that constitute the executable model and the advancement of the simulation time t s . Thereafter, the specific simulation instants of the studied model will be noted in the form x i (k). By way of example, x W rM2S (k) designates the k-th instant at which the write operation within the relation M 2 begins. More specifically, we note u the instants corresponding to the inputs of the studied system and y the instants corresponding to the outputs. Thus, in the figure 2.2, u(k) designates the k-th instant at which the function F 1 receives data through the relation M 1 and y(k) the k-th instant at which F 4 produces data through the relation noted M 6 .

Simulation time t s u(k)=x M1 (k)

x M1 (k+1) =u(k+1)

x WrM2S (k)

x M3 (k)

F1:Read(); F1:Execute();

P1

Platform resources

x M4 (k) x M5 (k) x M6 (k) =y(k) y(k+1)=x M6 (k+1)
Calls to the simulation kernel Such an execution makes it possible in particular to analyze the impact of the resources of the platform on the execution of the application, this taking into account the platform arbitration strategies. Additional delays are thus introduced into the execution of the elements of the application due to concurrent access to shared resources. The situation illustrated in the figure 2.2 corresponds to the situation where the interface IF1 is busy carrying out a transfer on the communication bus and cannot immediately receive the data carried by the relation M 2 .

x NM2S (k) x NM2E (k) x RdM2E (k)
The construction of accurate performance models first requires the establishment of reliable abstractions, quantifying the duration associated with the communication and computation primitives used to describe the studied architecture. The influence of shared resources must then be described at the considered level of abstraction. For this type of model, the simulation duration is essentially linked to the number of calls to the simulation engine, the operations described being of limited complexity. The fact of having to consider ever more components within an architecture (functions, relations, elements of a platform) implies controlling the simulation effort of the created models and this while delivering an acceptable level of precision.

Principles of the proposed system-level approach

The proposed approach aims to limit the number of calls to the simulation engine while preserving the level of accuracy achieved by traditional approaches. To do this, this approach uses the properties expressed within the performance models created and which establish, in particular, the dependencies between components of the application as well as the strategies for arbitrating the resources of the platform. Based on this knowledge, the proposed approach consists in predicting, during the simulation, the future instants of execution of the model without requiring calls to the simulation engine. the execution of a model created according to the proposed approach, for which time y(k) is predicted at time u(k). This prediction corresponds to a calculation symbolized by the action Compute_y(), relating to the set of instants x i (k). This calculation is based on the knowledge of the temporal dependencies expressed

/Compute_y(); u(k) y (k) (b) Instantaneous computation T (k) t s u(k) y (k) (a)
Calls to the simulation kernel within the initial architecture model. At this stage, the expression of these dependencies can be made by a set of state equations expressed in the form:

t s x (k) M1 x (k) M2 x (k) M3 x (k) NM4S x (k) NM4E x (k) NM4S x (k) NM4E M 1 M 1 M 6 M 6 NM 4
X(k) = f (X(k -1), u(k)) y(k) = g(X(k), u(k)) (2.1)
The state vector X designates here the set of instants x i involved in the calculation of y(k). f and g reflect the dependencies between the instants y, the current and previous values of the state vector as well as the instants u. As mentioned above, these equations are established taking into account the dependencies between the elements of the architecture model. The proposed construction for these state equations is discussed in the next section.

An essential point of this approach concerns the fact that, during the simulation, certain situations can impact the prediction made and lead to degrading the accuracy achieved. This phenomenon occurs in particular in the case of the use of shared resources of the execution platform. x (k) Part (a) of the figure 2.4 illustrates the situation where the use of the shared resource occurs before the previously predicted instant x NM 4 S (k). In the situation presented, M 2 uses bus N before M 4 . Consequently, the contention phase on the communication bus N is not correctly established and the model thus constructed delivers degraded precision. The approach proposed to correct such phenomena is illustrated in part (b) of the figure 2.4. It consists in identifying the situation of contention taking into account the value of the state vector. In doing so, it is possible to retroactively correct the prediction made and thus to take account of the effect of the contentions on the predicted instants. On the given example, the identification and the correction are carried out at instant y(k). Instant y c (k) then corresponds to the newly established exit instant taking into account the contention phase that has occurred. This principle was also used in the context of Mr. Singh's Master for the case of multiple applications allocated on the same resource platform [J2 -1].

NM4S x (k) NM4E u(k+1) x (k+1) NM2S x (k+1) NM2E x (k+1) NM2S x (k) NM4E = x (k+1) NM2E x (k) NM4S M 1 M 1 M 6 M 6 c M 6 u(k+1) M 6 y(k+1) y(k+1) M 1 M 1 Contention
In this field of study, many approaches have been proposed in order to limit the number of simulation events while seeking to maintain the accuracy of the models created. A first example concerns the two coding styles proposed in the SystemC TLM2.0 [10] standard: the so-called approximately-timed (TLM-AT) style and the so-called loosely-timed style (TLM-LT). The TLM-AT approach leads to the description of numerous synchronization points between processes, involving numerous interventions of the simulation engine (lock-step simulation). The TLM-LT approach allows processes to run independently of the simulation engine, for a given time interval (temporal decoupling). Such an approach is notably used to speed up the simulation of models used for software verification on virtual prototypes but may involve inaccuracies about the influence of shared resources [START_REF] Stattelmann | Fast and accurate resource conflict simulation for performance analysis of multi-core systems[END_REF], [START_REF] Lu | Analytical timing estimation for temporally decoupled TLMs considering resource conflicts[END_REF]. The principle consisting in predicting the future instants of evolution of a model in order to abstract some of its elements was notably considered in the so-called ROM approach (Result-Oriented Modeling) proposed by Schirner and Dömer in [START_REF] Schirner | Result-oriented modeling -a novel technique for fast and accurate TLM[END_REF], [START_REF]Introducing preemptive scheduling in abstract RTOS models using result oriented modeling[END_REF]. A retroactive adaptation of the predicted instants was also considered in order to be able to correct the possible influence of shared resources. However, the method used to predict the synchronization instants during the simulation was based on a priori knowledge of the durations to be used. Different approaches combining simulable system-level models and calculations have also been proposed in order to offer an optimized compromise between simulation speed and accuracy [START_REF] Bobrek | Stochastic contention level simulation for single-chip heterogeneous multiprocessors[END_REF]- [START_REF] Chen | An activity-sensitive contention delay model for highly efficient deterministic full-system simulations[END_REF]. The proposed approach differs from this work in the way simulation and calculations are associated. The prediction of simulation instants is based on a description that express the dependencies between simulation instants. This approach also makes it possible to retroactively correct the calculated instants in the case of conflicts of access to shared resources. This approach was successively described in international conferences [C2-1]-[C2-3] and in international journals [J2-1], [J2-2]. Hereafter, the two principal aspects of this approach are explained: the establishment of the state equations then the executable model used in simulation.

Creation of state-based models

An essential aspect of the proposed approach supposes to establish the dependencies between simulation instants of the elements of a given architecture, these instants then being calculated during the simulation without using the simulation engine. These equations are established taking into account the knowledge of the physical architecture model. Thus, the application model establishes the dependencies between functions and this taking into account different communication protocols between functions. The platform model establishes the organization of communication and computation resources as well as the arbitration strategies for access to shared resources. We used the formal model of Petri nets in order to rigorously establish the dependencies between simulation instants. More specifically, we used the formalism of timed Petri nets (timed Petri nets) to establish the existing dependencies for each of the primitives used within the architectural models studied. This choice lies in the fact that this formalism has a direct correspondence with the (max, plus) algebra. This algebra represents the appropriate framework for expressing in the form of state equations the dependencies within a discrete event model [START_REF] Baccelli | Synchronization and linearity, an algebra for discrete event systems[END_REF]. Timed Petri nets correspond to an extension of Petri nets for which the time constraints are given by a single value. In our case, these values represent minimum occupation durations of the places by the tokens. Such a network is defined by the tuple T = (P, Q, • (.), (.) • , µ 0 , T, ρ), for which P denotes a nonempty finite set of places, Q denotes a nonempty finite set of transitions, • (.) ∈ (N |P| ) |Q| denotes the upstream incidence function, (.) • ∈ (N | mathcalP| ) |Q| is the downstream incidence function, µ 0 ∈ N |P| is the marking initial of the network, T ∈ R |P| is the set of durations on places. A transition q is active if each upstream place contains at least one token. Basically, triggering a transition results in removing a token from each place upstream and adding a token to each place downstream of the transition. Additional weights can be carried by the arcs, indicating the number of tokens needed to trigger a transition. Occupation duration in a place is the time spent in a place before contributing to the activation of downstream transitions. Part (a) of the figure 2.5 illustrates this formalism for a simple network formed of seven places and six transitions. We note x j (k) j = 1, . . . , |Q|, k ≥ 0, the instant at which the transition q j is activated for the k-th time. Taking into account the construction rules of such a network, the relations between instants of transition can be expressed according to two operators: addition and maximization. The addition expresses a shift in time taking into account the time spent in a place, the maximization reflects the effect of a wait, of synchronization. Part (b) of the figure gives the instants of the transitions of the illustrated network. We adopted this formalism in order to rigorously express the existing dependencies within an architecture model as illustrated on the example of the figure 2.1. For a given architecture model, the expression of the dependencies is established by successively considering the elements of the application model then the constraints introduced by the allocation on the resources of a platform. Such an approach was notably presented in [START_REF] Seidner | Formal methods for systems engineering behavior models[END_REF] for the case of the EFFBD notation (enhanced function flow block diagram). In our case, we tried to remain independent of a specific notation by considering the mechanisms encountered in many modeling approaches. First, a set of elementary patterns must be established taking into account the meaning given to each element of the application model. Each pattern can be described by an elementary Petri net T n . The figure 2.6 illustrates some patterns established to describe the dependencies associated with the calculation mechanisms and the control instructions encountered for the description of the application model.

q 2 p 3 q 3 q 4 p 4 T p5 q 5 p 5 q 1 q 0 p 0 p 1 p 2 T p3 T p1 T p2 T p0 p 6 (a) (b)
The network associated with the complete application model is obtained by connecting each elementary pattern n required taking into account the description of the behavior of each function and the organization between functions. The figure 2.7 illustrates the patterns considered in the case of communications between functions according to the rendezvous and FIFO protocols of infinite capacity. The network associated with the application model is then completed taking into account the considered allocation constraints and the characteristics of the elements of the platform. The execution times of the computation and communication primitives are taken into account in the form of an occupation duration in places. The limited capacities of platform resources are taken into account in the form of additional places and arcs on the network. On the example of the figure 2.8, part (a) shows the dependencies between transition times for the case of the communication of M 2 through the interfaces IF1 and IF2 and the communication bus N. In this example, the places noted p(IF1) and p(IF2) indicate the fact that each interface IF1 and IF2 cannot simultaneously manage the transfer of data on the bus and receive or deliver new data. Part (b) of the figure 2.8 illustrates the construction made in the case of the function F 4 described in the figure 2.1. This construction is obtained by combining the elementary patterns illustrated in the figures 2.6 and 2.7. In [J2-2], a complete example is presented to illustrate the construction process implemented.

The establishment of such a Petri net makes it possible to rigorously establish the dependencies within an architecture model. In order to carry out the computations required during the simulation, these dependencies are formulated in the form of a directed graph, denoted G = (V, E). V designates the set of nodes of G, formed by the transition instants x i (k) of the network. E denotes the set of arcs formed by pairs (x i (k), x j (k )), where q(Op) q(/Op) p(Op) p 0 (Op) T Op (a) Pattern related to the computation statement, q(Op) and q(/Op) denote the start and end transitions. T Op denotes the computation duration.

q(/f) p 0 (f) N q(f) p(f) p(/f) q(le) p(le) N q(f, 0 ) p(f, 0 ) (b)
Pattern related to the finite iteration statement, q( f , 0) and q(/ f ) denote the start and end transitions of one iteration, q(le) denotes the end of all the iterations.

q(i,0) q(/i) p 0 (i) inf q(i) p(i) p(i,0) p(/i) (c)
Pattern related to the infinite iteration statement, q(i, 0) and q(/i) denote the start and end transitions of one iteration. q(a1,0) q(/a) p 0 (a) q(a) p(a) p(/a) q(a2,0)

(p(a)) ρ (d)
Pattern related to the alternative instruction, q(a) and q(/a) denote the start and end transitions of the alternative, ρ is the used to designate the selected transition. x i (k) denotes the source node and x j (k ) the destination node. These arcs are established when a dependency exists between times x i (k) and x j (k ). The weight associated with the arc (x i (k), x j (k )) corresponds to the duration between the instants x i (k) and x j (k ). In the proposed approach, this graph will be used in simulation in order to carry out the calculations previously expressed within the state equations (2.1). The traversal of the graph reflects the execution of the Petri net given the evolution rules used. A detailed example of such a graph is presented in [J2-2].

Generic execution model

The form taken by the executable model created according to the proposed simulation approach is discussed here. This is the simulated model that evolves according to the principles illustrated in the figures 2.3 and 2.4. This model has an equivalent behavior from the point of view of its inputs and outputs to an executable model created using a traditional approach but with a limited number of required processes. By applying this principle to the example in figure 2.1, the executable model created must therefore exhibit equivalent behavior from the point of view of the M1 input and from the point of view of the M6 output. Part (a) of the figure 2.9 illustrates the organization and behavior of the execution model considered. The instants of synchronization between functions are themselves expressed within the executable model according to the TRd ReadToken q(Rd) p(Rd) q(/Rd) p 0 (Rd) data transfer q(N) p(N) q(/N) According to the behaviour thus described, a new input data can be consumed when the instant x u (k) is reached. The action noted Compute_y corresponds to the calculation of the instants X(k) and y(k) taking into account the instant of reception u(k). XS designates the set of instants X calculated and not reached during the simulation. The process noted Emission is activated according to two conditions: each time a new output time is calculated (new_y) or when the simulation time has reached the calculated time (t s = y(k)). The presented model is said generic as it can be applied for different state equations and therefore different architecture models (the case presented here is with one input and one output).

T N WriteToken q(Wr) p(Wr) TWr q(/Wr) p(IF2) p(IF1) p(M) p 0 (Wr) F4 / P2 inf TF4Op1 T RdM5 ReadToken Execute p 0 (i) q(i) p(i) q(i,0) q(RdM5) p(RdM5) q(/RdM5) q(F4Op1) p(F4Op1) q(/F4Op1) p(/i) q(/i) p(M5) p(a) p(/a) q(a) q(a1,0) q(a2,0) q(/a) )) ( ( a p ρ TWrM5 WriteToken p(WrM6) q(/WrM6) q(WrM6) (a) (b)
Part (b) of the figure 2.9 presents the sequence of operations performed by the procedure denoted Update. This sequence of operations and the behavior of the executable model are illustrated in part (b) of the figure 2.4. When a new output time has been computed, the next time (line 3) is set to y(k) and no output is performed. When the simulation time t s has reached the value y(k), XS is analyzed to determine if a contention has occurred (action CorrectionNeeded line 6). In the example of figure 2.4, the action CorrectionNeeded corresponds to the comparison of x NM 1 E (k ) with x NM 4 S (k) and x NM 4 E (k). The operation Correct_y (line 7) designates the action which performs the correction of the instants X(k) from the updated instants. In the example of the figure 2.4, x NM 4 S (k) is updated with the value x NM 1 E (k ) and the times depending on it are also updated. y c (k) corresponds to the corrected value of y(k) taking into account the contention to access resource N. According to the behavior presented, the instants stored within XS can therefore be corrected retroactively at the instant t s = y(k). When the simulation time has reached the value y(k) and no correction is necessary, the instants stored within XS can be deleted (line 11).

Implementation and preliminary results

The approach presented was implemented to quantify the gains obtained in terms of simulation duration. The objective was also to estimate the potential limits of the approach given the complexity of the calculations to be made during the simulation. Two modelling and simulation environments were considered. The first is the Intel CoFluent Studio [27] modeling and simulation environment. This environment allows the capture of physical architecture models by combining functional and executive views. Once the graphical description made, the models are generated in SystemC in order to be simulated and analyzed. The models proposed by this environment are very rich and make it possible to approach numerous mechanisms of the functioning of hardware-software architectures. We have therefore established different patterns required for the construction of state-based models according to the construction approach previously presented. A description of the generic execution model in the formalism specific to this environment has been developed. It was thus possible to compare different models created with or without the proposed approach and thus to estimate the precision obtained and the simulation times. The figure 2.10 presents two sets of results obtained in order to illustrate the potential gains of the proposed approach as well as the influence of the complexity of the approach.

(100) (132) Part (a) of the figure, taken from [J2-2], illustrates the effect of applying the proposed method on a variable number of functions composing a physical architecture model similar to the one illustrated in figure 2.1. The number of functions considered is indicated in parentheses. In doing so, the gains observed in terms of simulation speed change by a factor of 3 to 18, while preserving the accuracy of the models. We observe the significant influence of the complexity of the calculation method on the accelerations obtained. Thus, for a set of 100 abstract functions by applying the proposed method, the gain obtained is a factor of 4 for a graph G composed of more than 700 nodes. Part (b) of the figure, taken from [C2-1], also illustrates this phenomenon by keeping a constant number of abstracted functions but increasing the size of the graph required to establish an equivalent accuracy.

In [J2-1], we quantified the contribution of the correction method mentioned in the section 2.3. To do this, the simultaneous execution of two applications is considered on a platform having a shared communication bus. A first application is described with a variable number of functions depending on the configurations, periodic input data and randomly generated calculation and communication times. The second application is described in order to cause contention on the communication bus and this according to a controllable contention rate. A first come first served (first come first served, FCFS) bus arbitration is considered. These models were created within the Intel CoFluent Studio environment. The table 2.1 presents the results obtained for different configurations studied. The accuracy of the models was evaluated by comparing the instants of synchronization between the functions of the applications with an execution of the models not using the proposed approach. The application of the proposed correction method allows a complete correction of the errors introduced by the second concurrently executed application. The acceleration factors for the simulation of the two concurrent functions and of the single reference application were also estimated. The second implementation of the proposed approach corresponds to a SystemC development of the generic execution model. This development was used in the thesis of Mr. Hai Dang Vu and will be presented in chapter 3. More generally, we have been able to put this approach into practice through various case studies carried out as part of co-supervised theses. The table 2.2 summarizes the case studies discussed as well as the gains obtained in terms of simulation speed. These case studies will be presented in the indicated chapters. In particular, the approach presented was used to improve the efficiency of existing models (study of the HomePlugAV communication interfaces and the LTE mobile radio receiver presented respectively in chapters 3 and ??). It was also used to promote the creation of effective models based on a detailed understanding of the mechanisms observed on a real target (study of the AXI4-Lite multiprocessor bus presented in chapter 3).

Case study

Conclusion

The approach presented in this chapter combines simulation methods and formal models in order to optimize the efficiency of simulable models used for the performance evaluation of hardware and software architectures of embedded systems. The creation of simulable models using the proposed approach turns out to be systematic for the creation of state model and executable model. A first prototype of a software tool was developed using Acceleo technology for the manipulation and transformation of models [START_REF]Acceleo[END_REF]. This prototype tool aimed to validate the principle of automated creation of simulable models using the proposed approach, and this from models captured in the Intel CoFluent Studio environment. In parallel with the continuation of this development, it would be beneficial to approach the reduction of the complexity of the formal model created, this in order to be able to consider systems comprising a high number of components. Finally, it would be interesting of establishing suitable patterns in order to describe the main strategies of arbitration of shared resources existing within multiprocessor architectures.

From an organizational point of view, the approach presented could be developed in particular within the framework of the research stay carried out in 2012-2013. It was also possible to apply this work to various case studies carried out within the framework of co-supervised theses. These applications are illustrated in the following chapters 3 and 4.

Chapter 3

Communication modelling of multiprocessor architectures

Introduction

This chapter presents the work carried out around two case studies considered in the context of two cosupervised theses. These works have in common to address the design of architectures involving several processors interconnected through communication buses of different natures. In both cases, the work focused on the prediction of temporal properties (typically, the execution latency of applications) with the objective to optimize the studied architectures according to parameters such as the number of processors or the memory capacity required. The creation of simulable models was then necessary and the improvement of the efficiency of these models was an essential point in order to favour the dimensioning of the architectures. Thus, in collaboration with the two co-supervised students, we were able to evaluate the application of the simulation approach presented in Chapter 2 and compare its contribution to models created according to other approaches. Moreover, we considered the implementation of this approach according to two development environments: Intel Cofluent Studio and SystemC.

For the two discussed case studies, it was essential to correctly describe the communication mechanisms between processors. As mentioned in Chapter 1, the analysis of the temporal properties of embedded systems can be carried out according to different levels of detail. Figure 3.1 illustrates the different levels of abstraction addressed in the context of these studies given the description of the communication mechanisms. As illustrated, the message level considers the exchange of structured data through atomic primitives (e.g., WriteTokens for writing a set of tokens). The communication time is not zero and, within the framework of our studies, it will be calculated taking into account the simulation approach presented in Chapter 2. The transaction level describes the successive exchanges of refined data by identifying certain instants representative of the communications. The arbitration of exchanges is explicitly described. The transfer level considers elementary data exchanges according to a defined protocol and for which the time scale is the clock cycle (cycle-accurate). A similar classification was adopted by G. Schirner et al. in [START_REF] Schirner | Quantitative analysis of the speed/accuracy trade-off in transaction level modeling[END_REF]. They present a quantitative evaluation of the effect of these different levels of abstraction on the accuracy of performance models and their simulation durations. This evaluation was made by considering different communication protocols: the ARM AHB system-on-chip multiprocessor bus protocol, the CAN fieldbus protocol and the Motorola ColdFire multiprocessor bus protocol.

Case studies

Message

Transaction

Transfert time

Granularity of exchanged data

Structured data

Elementary cycles

Levels of abstraction

Intermediate communication phases

In the first part of this chapter, the case of an architecture envisaged for the automotive field is presented. This architecture was studied as part of the ANR CIFAER project and the thesis of Mr. Takieddine Majdoub [START_REF] Majdoub | Technique de modélisation transactionnelle en vue de l'amélioration de la simulation des modèles de performances des architectures électroniques dans le domaine automobile[END_REF] conducted from 2009 to 2012. This thesis approached the dimensioning of a distributed architecture with several electronic controllers communicating through a protocol adapted to power line carrier transmission. In the scope of this work, we were able to evaluate the contribution of the proposed simulation method on this case study. This study was conducted before we considered the different principles mentioned in Chapter 2.

In the second part of this chapter, we present an architecture integrated on a chip with several processors communicating by shared memory through a multi-master communication bus. This case study was addressed as part of Mr. Hai-Dang Vu's thesis [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF] conducted from 2017 to 2021. This thesis was oriented towards the application of probabilistic models and methods for the study of multiprocessor systems. It also offered the opportunity to optimize the communication bus model used for this study. We were thus able to compare the models created with measurements on a real target, making possible an advanced comparison of the precision of the built models. Only aspects related to the modelling of communication buses with the proposed method are presented in this chapter. The other facets of the work carried out within the framework of Mr. Hai-Dang Vu's thesis will be presented in Chapter 5.

Improvement of simulation efficiency for distributed architecture analysis

The work presented in this section focuses on the study of distributed architectures for the automotive field, work begun in 2008 through the Master of Miss Maria Cheik Wafa [C3-1] and continued as part of the thesis of Mr Takieddine Majdoub [START_REF] Majdoub | Technique de modélisation transactionnelle en vue de l'amélioration de la simulation des modèles de performances des architectures électroniques dans le domaine automobile[END_REF]. It represents a first application of the principles mentioned in Chapter 2 to the case of communication protocols adapted to networks of on-board computers.

Characteristics of the studied systems

This case study was addressed in order to evaluate the benefits of data transmission based on power line carrier (PLC) for high-speed communications within motor vehicles. The studied system, represented in Figure 3.2, corresponds to a distributed architecture of several on-board computers and supporting a video stream application applied to the automotive field.

The application consists of managing a video stream, captured by one of the controllers and then transmitted to other controllers through the HomePlugAV communication protocol. This protocol is adapted to PLC transmissions. It supports the transfer of data with IP and Ethernet formats with throughput of up to 150 Mbit/s. Each controller (Electronic Control Unit, ECU) essentially consists of a microprocessor, performing the application tasks and managing data flows according to the RTP-UDP and IP protocols, and a HomePlugAV communication interface. The purpose of the study carried out was to estimate the capacities required of the memories within each communication interface.

As illustrated in the lower part of Figure 3.2, the HomePlugAV protocol supports two communication media access techniques: TDMA (Time Division Multiple Access) type access and type CSMA/CA (Collision Sense Multiple Access/Collision Avoidance). Considering the needs of the application, only the TDMA access technique was considered in this case study. A detailed presentation of this protocol and the operation of the communication interfaces is given in [START_REF] Majdoub | Technique de modélisation transactionnelle en vue de l'amélioration de la simulation des modèles de performances des architectures électroniques dans le domaine automobile[END_REF]. In this architecture, the role of the HomePlugAV communication interfaces is to classify the IP packets according to their source and their destination, and to ensure the transmissions are correclty performed. The data exchanged between ECUs correspond to sets of bytes of constant size designated by the term Physical Block (PB). These PBs are transmitted in the time intervals allocated for this purpose for each ECU. They are kept within the interfaces until they are positively acknowledged. In order to illustrate the operation of this protocol, Figure 3.3 represents the typical use of the memory of the transmitting HomePlugAV interface for the transmission of PBs to a receiver.

Tx Slot

Rx1 Slot Tx Slot Rx1 Slot

(5) Part (A) represents the various exchanges carried out between the transmitting and receiving interfaces. Part (B) indicates the different time intervals allocated for each element. Part (C) represents the evolution over time of the occupation of the memory within the sender interface. The interval (1) designates the IP packets successively received by the sender interface and intended for the receiver. The interval (2) corresponds to the data successively stored within the interface, inducing the increase in the memory occupation (a). When a PB is formed and the transmitter time slot occurs, the start of a frame is notified (0) then the stored PBs are successively read within the interface (3) and transmitted over the communications medium (4). The reception of the transmitted data corresponds to the interval (5). Acknowledgments are delivered by the receiver when the time interval allocated to it occurs (6). The acknowledged PBs are then deleted from the sender interface, the memory occupation then being reduced (b). The observation given in Figure 3.3 comes from the simulation of the model presented in [START_REF] Majdoub | Technique de modélisation transactionnelle en vue de l'amélioration de la simulation des modèles de performances des architectures électroniques dans le domaine automobile[END_REF]. This model considered the organization presented in Figure 3.2 with three ECUs. This model was used to predict the memory occupation of the different interfaces as well as the end-to-end latency during the transmission of video sequences between on-board computers. The influence of parameters such as the error rate on the PBs transmitted or the size of the IP packets used was also evaluated. The main results obtained being are presented in [J3-1].

(4) (6) (5) (6) (0) (0) (3)

Application of the simulation method

The model initially created exhibits the different phases of transmission of PBs as well as the acknowledgments made in the time intervals allocated for each ECU. This level of detail, considered here as the transaction level, allows an analysis of the memory occupation within the interfaces during the different communication phases. Such observations can be used in order to appropriately size these resources taking into account the constraints and the parameters of the complete system. However, such a representation leads to a high number of communications between model elements, significantly impacting the simulation duration required. The proposed simulation method was applied in order to reduce the number of exchanges between the interfaces while preserving the prediction made of the use of the memory resources. For this case study, the reduction in the number of exchanges required is obtained by applying the following observations:

• each transmitted message corresponds now to a variable set of PBs resulting from the reception of IP frames. The duration between two successive transmissions is thus calculated during the simulation taking into account the number of transmitted PBs.

• The instants of transmission are also calculated taking into account the TDMA intervals previously established.

• The supposed transmission instants of each PB are indicated within each message, in order to allow a detailed observation of the occupation of memory resources for the message level model.

• The acknowledgment instants of PBs are also calculated locally within the elements of the message level model in order to overcome the exchanges previously displayed in the transaction level model.

HPAV_Data (a) (b) (a) & (b) (a) (2)
(1) The message level model therefore considers a grouping of PBs within a single data exchange. The number of PBs is variable and depends on the quantity of data present in memory. Also, we used the possibility of predicting the instants of acknowledgment of the PBs, these instants depending on the organization of the access intervals to the communication medium. According to this observation, the instants of releasing the memory can be established at the instant of the production of the PBs. An important point lies in the fact that the observation of the evolution of memory occupation is no longer carried out solely according to the simulation time t s but taking into account a local variable called observation time t o . This variable is introduced because the observations are no longer linked solely to the flow of simulation time but are made taking into account the calculations carried out locally within the elements of the model. The models developed were presented in an international journal article [J3-1] and in international conferences [C3-2], [C3-3]. This work was also presented in the reports of the CIFAER project [R3-1], [R3-2].

Obtained results

Experiments were conducted using the Intel CoFluent Studio modeling and simulation environment. The previously mentioned transaction and message level models were described within this environment. These models are created first of all through a graphical capture <ith a notation specific to the environment, supplemented with codes in the C++ language. These sets are then automatically translated into SystemC to be simulated and analyzed. The simulations were carried out in order to study the occupation of storage resources during the transmission of several sets of images, from 150 images to 4500 images, between three computers. Table 3.1 gives the simulation durations observed for the simulation of the different models. For the different situations evaluated, the gains obtained in terms of simulation time lead to a reduced analysis time, offering the possibility for architects to be able to explore different design alternatives more quickly.

Improvement of simulation efficiency for multiprocessor systems-on-chip analysis

The case study presented here was cosnidered within the framework of the thesis of Mr. Hai-Dang Vu and within the framework of the collaboration with the German institute OFFIS.

Characteristics of the studied systems

The systems studied here correspond to data flow oriented applications distributed on multiprocessor platforms, as illustrated in Figure 3.5. The applications are described on the basis of the Synchronous Data Flow (SDF) model of computation, introduced by E. Lee in [START_REF] Lee | Synchronous data flow[END_REF]. They are organized into a set of actors exchanging tokens through communication channels. Subsequently, each exchanged token corresponds to a pixel composing the image processed by the studied application. In the example of Figure 3.5, the illustrated application comprises four actors and five communication channels noted from C 0 to C 4 . The communication channels correspond to buffers of FIFO type with limited capacity and for which read and write accesses are blocking. An actor can only begin its computation phase once the reading of the various data from the input channels has been completed. Once the computation phase has been executed, an actor writes the necessary data to its output channels.

The studied systems are based on the use of a platform organized as a tile-based platform where each tile corresponds to a programmable processor with its private instruction and data memories as well as a communication interface. Such a platform has a variable number of tiles, one or more shared memories and a shared communication bus. Shared memories are used to temporarily store the data exchanged between the actors of the application. In the example in Figure 3.5, the five channels are exchanged through the communication bus and shared memory. It should be noted that each tile can execute its program without interfering with the other tiles as long as this program does not explicitly access the shared resources. The interest of such a system lies in the fact that it can be easily extended in number of tiles.

As part of Mr. Hai-Dang Vu's thesis, we were particularly interested in the modelling of communication between tiles in order to describe the influence on the temporal properties of the system (here, the end-to-end latency of the application allocated on different tiles). At the application level, communications between actors are carried out through two functions: WriteTokens leads to writing a set of tokens within the shared memory, ReadTokens leads to reading a set of tokens within the shared memory. The example of writing n tokens is shown in Figure 3 Part (b) of Figure 3.6 represents the sequence of states observed during the writing of n tokens within a shared memory. The states denoted by polling, writing and update buffer usage correspond to situations where processors access shared resources and for which contention may occur. Within the framework of the experiments carried out, the arbitration of the communication bus is done according to the First Come First Served protocol. The states denoted initialization, inter-polling stage, pre-writing, inter-writing stage and post-writing correspond to situations where the execution of the program of each processor does not interfere with any other resource. At the beginning of the writing of n tokens, the polling phase aims to check the availability of the targeted buffer. The inter-polling phase reflects a minimum duration between two successive polling phases. Once the buffer is ready, a copy of the data of a token is written (state writing) and at the end of the writing of the data the state of the buffer is updated in order to notify the possibility to read the written data (corresponding to the elementary state update buffer usage). The procedure for reading n tokens is carried out according to a similar sequence of states. Each state has its own duration expressed in number of clock cycles. These elementary durations will be established experimentally by measurements on a real target via the measurement infrastructure mentioned in Figure 3.5. This infrastructure is also used to allow the computation time of each actor to be measured as well as the execution latency of the application on the platform.

Ultimately, the modelling and simulation of such a system should make it possible to estimate the execution latency of the application for different design alternatives, in particular taking into account the number of tiles used and the distribution of the actors of the application.

Application of the simulation method

The analysis of the temporal properties of the studied systems requires taking into account the effect of communication mechanisms and the penalties induced during simultaneous accesses to shared resources. These mechanisms have been successively described at the transfer, transaction and message levels of abstraction. Figure 3.7 considers the case of two simultaneous communications, a write and a read of n tokens, through the bus and shared memory.

Part (a) of the figure corresponds to a transfer level model built in order to reproduce the operation illustrated in Figure 3.6. At this level of detail, the phase of scanning the state of the buffer as well as the successive exchanges token by token are expressed. Each of the elementary phases is exhibited through a specific duration 1 . The situations noted (1), ( 2) and (3) correspond to the different situations of access to shared resources previously highlighted in Figure 3.6. The situation noted (1) corresponds to conflicts due to two simultaneous scanning phases. The situation noted (2) corresponds to the situation where an elementary write phase is delayed due to an elementary read in progress. Finally, the situation noted (3) corresponds to the situation where the phase of updating the state of the channel C 1 is delayed due to the updating of the channel C 0 .

At this level of detail, two phases involve numerous calls to the simulation engine: the scanning phase and the successive writes or reads for each token. A message-level model using the simulation principles introduced in Chapter 2 has been built in order to limit the number of calls required while preserving precision on the use of resources, and therefore the effect of contentions on access to shared resources2 . Using the proposed approach, the communications are described by considering as atomic the transfer of n tokens, the duration of the communications then being computed during the simulation. For this level of abstraction, bus arbitration is no longer explicitly expressed, it will be taken into account in the computation performed. Part (b) of Figure 3.7 illustrates the application of the proposed simulation method for a message-level model of communications. At this level of abstraction, only three significant instants are exhibited: the instants of the start and end of communication of the tokens (x w ComC and x w ComE ), and the instant when the buffer is available (x w ComS ). The application of the proposed simulation method leads to the calculation of the communications durations, noted T W and T R

Wait event read_C1

T W (k)=x w (k)-x w (k)

Wait event write_C0 T R (k')=x r (k')-x r (k') (a) (b)
...

/ComputeCommTime(T W (k)); /ComputeCommTime(T R (k'))

;

(1) (2)
(2) (2)

(3)

x w (k)

x r (k')

x w (k)

x w (k) x w (k)

x w (k+1)

x w (k) therefore necessary to establish the durations of the communication phases even in the case where situations of conflict of access to shared resources arise. According to the proposed approach, the expression of communication durations is based on the knowledge of the arbitration protocol used as well as on the mechanisms of exchange between actors (FIFO with limited capacity in the studied systems). This knowledge makes it possible to establish the dependencies between instants of communication. shared resources. Based on this model, transition times can be expressed using the addition and maximization operators. The complete state model, extended to several tiles, is presented in [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF] and [C3-4]. This model is used in order to calculate during simulation the durations of writing n tokens and this taking into account the number of communications observed.

The description in the SystemC language of the message level communication model is illustrated in Figure 3.9. Figure 3 two tiles. The communication infrastructure is then described using the generic execution model introduced in Chapter 2. This is transcribed in the form of a hierarchical channel for which the interfaces comprise the methods of access to the communication resources. The behaviour of the methods describes the access conditions for the exchange of finite capacity FIFO type channels as well as the required durations. The ComputeCommTime establish during the simulation the durations of the writes and reads of n successive tokens based on the state model established from the network illustrated in the figure 3.8. In the case of multiple channels exchanged between tiles, the instants in XS are shared among the interfaces related to each channel. The calculated instants can thus be updated depending on the observed communication situations. This description is detailed in [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF].

Obtained results

The evaluation of the developed models was done through two distinct applications studied according to different allocations on a platform based on seven tiles. The considered applications correspond to a Sobel filter and a JPEG decoder. The modeling according to the SDF formalism of these applications is given in part (a) of Figure 3.10. The multiprocessor platform studied is described in part (b) of this figure. Seven tiles are connected to a shared memory through an AMBA AXI4-Lite [START_REF] Limited | Amba® axi™ and ace™ protocol specification[END_REF] type communication bus. Each tile corresponds to a Xilinx MicroBlaze core associated with private instruction and data memories. The measurement infrastructure put in place makes it possible to record the computation times of each actor allocated to a tile as well as the communication times between actors. This set-up was implemented on a Xilinx ZC702 prototyping board based on a Xilinx Zynq-7000 FPGA. Different allocations of the applications studied on the experimentation platform were considered. Each implementation made it possible to record the execution time of each application and could thus be confronted with the model created elsewhere. Also, preliminary measurements on the target made it possible to establish the durations of the elementary communication phases, these quantities then being used within the transfer, transaction and message level models.

In Table 3.2, the average latency values obtained for different allocations of applications on the considered platform are presented. For example, the experiments denoted Sobel2 and Jpeg3 correspond respectively to Sobel filter and JPEG decoder applications allocated on 2 tiles and 3 tiles. The Measurement column presents the average execution times for 1 000 000 of iterations of the applications implemented on the experimentation platform. The next two columns give the mean values predicted by the transfer-level and message-level models previously presented. The results of the transfer level model show an over-estimation of 3.57 % for the configuration Sobel1 and 2 % for the configuration Sobel2 while the configuration Sobel4 presents an underestimation of 7.7 %. In the case of the JPEG decoder, the errors observed turn out to be very low due to the limited influence of the communication on the total execution time of the application. In all the configurations studied, the proposed message level model presents a high level of accuracy. Thus, in the case of the Sobel4 configuration, for which communications represent an important part, the observed error is 1.81 %. In [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF], we also compared the distribution of measured execution times and estimated from the proposed message level model. The shapes of the observed distributions remain identical between measured values and estimated values, regardless of the considered allocations. Table 3.3 presents the durations measured for the execution of 1 000 000 of application iterations on the experiment platform. Simulation times for 1 000 000 iterations are given for transfer and message level models. In the case of the JPEG application, the simulation time varies from 30 s for the configuration Jpeg1 to 1 h 55 min for the Jpeg7 configuration. In the case of the message level model, the simulation time remains less than 10 s for the two applications studied. The acceleration factor of the message level model compared to the transfer level model is 602.25 for the Jpeg3 configuration and 1731.25 for the Jpeg7 configuration . Also, the interest of such performance models is illustrated here by the comparison between the Jpeg3 and Jpeg7 configurations. Thus, the gain obtained in terms of execution time does not turn out to be significant by deploying the JPEG decoder application on 7 tiles, compared to the solution on 3 tiles. Moreover, this estimation turns out to be much faster than considering executions on a real target, fully justifying the usefulness of the message-level models created.

Conclusion

The work presented here allowed the application of the proposed simulation method on realistic case studies. It was thus possible to confirm the potential gains in terms of simulation time as well as to verify the achieved levels of precision. The case study addressed with Mr. Majdoub made it possible to quantify the potential contribution of the imagined simulation approach. This was addressed before proposing a generalization of the approach and its principles. In the case of the work carried out with Mr. Hai-Dang Vu, the model developed was supplemented by annotations from measurements on a real target, resulting in a high-precision model. This approach should be applied to advanced bus and network-on-chip communication mechanisms typical of high data flow architectures. One thinks in particular of the use of DMA for systematic transfers by data packets between memory zones. For the two presented case studies the models were developed manually and progressively. Eventually, it would be appropriate to propose an automation of the creation of such models in order to promote their use in the modeling and analysis process.

From an organizational point of view, Mr. Majdoub's thesis addressed the dimensioning of a distributed architecture for a new type of protocol applied to the automotive field. This case study was therefore used to experiment with the proposed modelling approach. As part of this thesis and the associated CIFAER project, we were unable to compare the results of the models developed with concrete implementations, which was a limit of the work then carried out. The proposed optimization of the simulation of the considered case study was a contribution of this thesis. As part of Mr. Hai-Dang Vu's thesis, the use of the simulation method was an opportunity that emerged during the work carried out. This study was processed in a few weeks as the principle of the model associated with the ARM AXI4-Lite bus quickly emerged from our discussions on the operation of this bus. This study was thus able to enrich Mr. Vu's thesis work as well as the collaboration carried out elsewhere with the OFFIS institute.

Supervision

PhD thesis

• Hai-Dang Vu, Fast and accurate performance models for probabilistic timing analysis of SDFGs on MPSoCs, University of Nantes, March 2021.

• Takieddine Majdoub, Transaction-level modelling methods for simulation efficiency improvement for performance prediction of automotive architectures, University of Nantes, October 2012.

Master thesis

• Maria Cheik Wafa, Transaction level modelling of a FlexRay communication network, Juin 2008.

Publications related to Chapter 3

International journals with program committee Modelling and management of computation resources in multiprocessor systems

Introduction

This chapter presents the contributions made within the framework of two co-supervised theses. These works have in common to address the dimensioning under time and energy constraints of the computing resources of multiprocessor architectures processing large data streams (physical layers of radiocommunication systems, audio and video applications). First, the contributions made aim to favour the modelling, evaluation and performance optimization of the studied multiprocessor architectures. Also, this work addresses the definition of online management strategies for computation resources under functional (quality of service) and non-functional (timing and energy) constraints.

The first part of this chapter presents the work carried out as part of Mr. Anthony Barreteau's thesis on the study and optimization under timing constraints of mobile radiocommunication system architectures. Firstly, this work led to proposals for integration of non-functional properties within hardware-software architecture models. This work was carried out from 2007 to 2010 and the proposals made formed the beginnings of the approach previously presented in chapter 2. Secondly, this work also addressed system-level modelling of the dynamic management of computation resources. This work was preceded by Master theses by Mr. Romain Guignard in 2006 and Anthony Barreteau in 2007 on high-level modeling of SoC architectures.

The second part of this chapter presents the work carried out within the framework of Ms. Simei Yang's thesis from 2016 to 2020, related to the proposal of online management methods for computation resources of multiprocessor systems. The purpose of this thesis was to optimize the energy consumed by the computation resources of such architectures. The contributions focused on the definition of scheduling and allocation strategies for multiprocessor and multicore platforms. As part of this thesis, we were also able to contribute to the definition of a method for simulating the online management of computation resources.

Modelling and sizing of mobile radiocommunication system architectures

The work carried out within the framework of Mr. Barreteau's thesis [START_REF] Barreteau | Techniques de modélisation transactionnelle pour le dimensionnement des futurs systèmes de radiocommunications mobiles[END_REF] aimed to apply the principles of system-level modelling for the study and dimensioning of mobile radiocommunication system architectures.

Considering the characteristics of such architectures, it was a question of identifying possible limits to the existing modelling flows. Two contributions was made: the first concentrates on the description and simulation of performance models and the second considers the online management of architectures under quality of service constraints.

Modelling and simulation method for non-functional properties

Mobile radiocommunication systems require high computing capacities in order to satisfy the timing constraints associated with the communication protocols supported. These computations are notably due by the various functions of the physical layer of the communication systems. These functions operate successively between the analog/digital conversion stage and the preparation of the data for the higher level communciation protocol layers. One of the objectives of Mr. Barreteau's thesis was to promote the evaluation of computing and memory capacity requirements for such architectures.

As mentioned in Chapter 1, the creation of workload models of an application is done by first describing the structure of the application and the behaviour associated with each of its elements. In a second step, the allocation of the elements of the application on the resources of a given platform is described. The application is organized as a set of functions and coupling relationships between functions. The behaviour of each function expresses the sequence of computation and communication actions performed. A communication or computation load can be associated with each action and reflects, for example, the number of arithmetic operations performed or the memory size required. The evolution of the model thus formed can be analyzed with regard to the degree of potential parallelism of the application and the capacity offered by the communication and computation resources of the execution platform. Figure 4.1 illustrates such a model on the case of the example introduced previously in Chapter 2.

Processor 2

F 2 M 3 M 2 M 2 transfert IF2 Process_F2 : while(1) { ReadToken(M2); Execute(token); WriteToken(M3); } M 2 M 3 (a)
Processor 2

F 21 M 21 M 2 M 2 transfert IF2 F 22 M 22 F 23 M 3 (b)
Processor 2 Part (a) of Figure 4.1 illustrates the modelling of a function executed on a processor with a given behaviour. The evolution associated with this model shows here the computation load induced (expressed in Mega operations per second (MOPS)) during the execution of the function F 2 . At this level of detail, this load is described according to a unique value between the instant of reception of data via relation M 2 and the instant of production of data via M 3 . Typically, this value may depend on the content of the data carried by the relation M 2 . Part (b) of the figure illustrates a refined modelling, showing elementary functions composing F 2 . The grain of the operated data is also refined. Each elementary function induces its own computation load, leading to a more precise evaluation of the occupation of the processor. At this level of detail, the number of exchanges generated between functions also turns out to be greater. The proposal made as part of Mr. Barreteau's thesis aimed to limit the number of elements (functions and relationships) simulated within the performance models while trying to preserve the precision of the observations made for finer levels of detail. Part (c) of the figure illustrates this proposition. In the case observed, a level of precision equivalent to case (b) is reached for a limited number of functions and exchanges between functions. The principle then proposed consisted in establishing a decoupling between the simulation time noted t s and the observation time manipulated locally within the simulated function. The observations made locally are then calculated at the times when the function is triggered (reception instant of M 2 in the case of Figure 4.1). This proposal uses the principle of instantaneous calculation presented in Chapter 2. As mentioned previously, this approach makes it possible to reduce the number of calls required to the simulation engine by locally calculating some of the instants when computation or communication resources of the platform are used. As part of M. Barreteau's thesis, we considered this method in order to limit the number of functions used to predict the computing capacity of the studied systems. Originally, this reduction was done by combining within the simulable model the loads induced by all the elementary functions considered [C4-1], [C4-2]. It was then latter that we considered the use of (max, plus) algebra and the formalism of Petri nets in order to systematize the definition of the calculations carried out during the simulation and to establish a generic model of execution used for the simulation of the models. In the context of Mr. Barreteau's thesis, this proposal was notably applied to the following case study inspired by the field of mobile radiocommunications.

F 2 M 3 M 2 M 2 transfert IF2 Computation load (MOPS) Computation load (MOPS) t s t s Computation duration of F2:Execute (c) M 2 Computation load (MOPS) t s M2 M3 M21 M22 M21 M22 M2 M3 M21 M22 M21 M22 M2 M3 M21 M22 M21 M22 Δt 1 Δt 2 M 3 /ComputeObservation() Δt 1 Δt 2

Study of the physical layer of the LTE protocol

This case study addressed the sizing of the computing and memory resources required to support the processing associated with the physical layer of the LTE (Long Term Evolution) [51] communication standard. The radio access technology associated with this standard, called E-UTRA (Evolved Universal Terrestrial Radio Access), has been defined in order to support transmission rates of up to 100 Mbit/s for the downlink. Part (a) of the figure 4.2 illustrates the organization of a reference LTE radio frame. This reference frame is organized in the form of ten sub-frames, themselves divided into two time slots of 0.5 ms. Each elementary interval is made up of six or seven OFDM symbols (Orthogonal Frequency Division Multiplex) spaced by long or short cyclic prefixes. The OFDM modulation technique makes it possible to allocate one or more blocks of resources to each receiver according to the quantity of information to be transmitted and the timing constraints to be respected in order to ensure a given level of quality of service.

Modelling of dynamic functions

One characteristic of the studied radiocommunication systems was their ability to support a wide variety of applications and to use different communication standards and protocols. These various functionalities could be activated during the operation of the system and this taking into account the needs of the user and the available communication infrastructures. The modeling and simulation of dynamically activated functions, i.e. during operation, supposed to extend the capacities of the software environment used within the framework of the thesis M. Barreteau. Classically, any function identified within a performance model is created at the start of the model simulation. Once the simulation has started, this function can be executed as soon as its activation conditions are met (e.g., availability of the data to be processed or the computing resources). We therefore proposed the case of so-called dynamic functions whose creation could be controlled during the simulation and no longer only at the start of the simulation. A dynamic function as we have defined it evolves according to three states:

• the Stopped state designates the initial state of the function when the simulation starts. This state corresponds to the case of a function not created or not allocated on a computation resource.

• The Started state represents the state where the feature is created and activated. The function is then allocated and can thus be executed.

• The Suspended state represents an intermediate state where the function is created but can no longer be executed.

The state control of a dynamic function is carried out from a specific relation indicating the state required for the function. This adaptation of the behaviour of the functions was integrated within the CoFluent Studio environment and could thus be used within the framework of M. Barreteau's thesis. This adaptation corresponded to the addition of a process specific to each function in order to manage their current state during the simulation. The case study presented below used this new modelling and simulation capability.

Study of a multi-standard mobile terminal

This case study focused on the modeling of a mobile radio terminal able to support several communication protocols and to autonomously select the protocol adapted to the operating situation. We considered the case of a mobile terminal implementing the E-UTRA and WiFi access technologies in order to support voice communication, Internet browsing and streaming video playback applications. The system thus imagined had to be capable of autonomously selecting the communication interfaces to be used given a changing network environment, offering variable communication capacities (urban or rural environment). The objective of the study related to the analysis of the evolution of the computation loads induced by the various communication interfaces and this according to various possible operating scenarios.

Figure 4.4 illustrates the adopted modelling of the communication interfaces. The selected level of granularity corresponds to the reception of data frames of duration equal to 10 ms for E-UTRA technology (considering a bit rate of 384kbit/s) and 347 us for WiFi (for a considered speed of 54Mbit/s). The behaviour of the E-UTRA reception and WiFi reception functions is described in such a way as to represent the processing related to the MAC and RLC (Radio Link Control) protocol layers of the E-UTRA and LLC (Logical Link Control ) from WiFi. These protocol layers ensure in reception the demultiplexing of the different data streams contained in a radio frame. Each stream is associated with an application used by the user. They also carry out the reconstitution of the data blocks associated with each application which have been previously segmented to be transmitted over the radio interface.

In the system studied, the communication interfaces were activated according to the needs of the applications used. These functions were modelled as dynamic functions in order to describe the influence of their activations and deactivations during the operation of the system. The relation noted RAT control was then used to activate these functions taking into account the quality of service required by the applications used.

The model of the studied system was described and simulated within the Intel CoFluent Studio environment. Figure 4.5 illustrates a simulated operating scenario and the influence on the latency of the considered applications. The model created is simulated according to a test environment for which the three types of applications are successively activated. The available networks are also evolving by offering different possible speeds (E-UTRA at 384 kbps then 130 kbps, WiFi unavailable then available at 1500 kbps). The scenario represented in Figure 4.5 illustrates the transition of video data transmission from the E-UTRA protocol to the WiFi protocol. The latency associated with streaming video increases given the reduced throughput offered by E-UTRA technology. The selection of the WiFi technology is then carried out autonomously and leads to reducing the latency of this application.

Service request

System management

Service response RAT discovery RAT control Application response Application request

Service management

Web page

WiFi reception

Video frame The proposed method of integrating non-functional properties was also used to complete the description of the behaviour of communication interfaces. The computation loads associated with the different functions of the physical layers of the two communication protocols were thus integrated into the description of the interfaces. As shown in Figure 4.4, the action ComputeObservation is executed upon receipt of the data in order to describe the use of the computing resources associated with the functions of the physical layer of each interface. It was thus possible to take into account the computation load induced by the different functions making up the physical layer of the standards considered. The characteristics of such a system and the details of its modeling are presented in [START_REF] Barreteau | Techniques de modélisation transactionnelle pour le dimensionnement des futurs systèmes de radiocommunications mobiles[END_REF], [J4-1]. Figure 4.6 illustrates two results obtained for the observation of the use of resources according to the operating scenario considered. Part (a) of Figure 4.6 represents the evolution according to the considered operating scenario of the total computation capacity required for the E-UTRA and WiFi interfaces. The instants noted (1) and ( 2) correspond to the start times of the channel decoding function on the received data. The interval noted (3) corresponds to the time interval for which the computing capacity is maximum, corresponding to the moment when the two interfaces are simultaneously active. Part (b) of Figure 4.6 represents the evolution of the computing capacity required for the WiFi interface for the processing of a WiFi data frame. This frame is made up of 27 OFDM symbols, the demodulation and channel decoding functions being applied successively to these symbols. In part (b) of Figure 4.6, instants (1) and (2) designate the times at which these functions start during the processing of the first OFDM symbol, instants (3) and ( 4) designate the instants of end of processing of the last OFDM symbol.

E-UTRA reception

The two aspects addressed in the context of Mr. Barreteau's thesis could thus be put into practice within a professional modeling and simulation environment. The contributions made it possible to approach the dimensioning of the resources of mobile radiocommunication systems for advanced operating scenarios. Subsequently, Ms. Yang's thesis was the opportunity to deepen the study of online management of multiprocessor systems.

Management strategies of multiprocessor architectures

Ms Simei Yang's thesis focused on the optimization under timing and energy constraints of multiprocessor and multicore architectures (MPCSoC, Multi Processor and Core System on Chip). The application framework corresponded to the case of multiple data flow applications that could be executed simultaneously according to different possible operating scenarios. The main objective of the thesis focused on the definition of online management strategies for multiprocessor platforms in order to jointly optimize the allocation and scheduling of tasks on computing resources as well as the operating frequency of the processors.

Related work and contribution of our work

The gradual increase in the number of processor cores is observed in many fields of application of embedded systems. Such multiprocessor platforms deliver significant execution parallelism while allowing to limit the required operating frequencies of the cores. These platforms favour the simultaneous execution of multiple applications, these applications being themselves described according to a set of tasks in order to take advantage of the offered parallelism. The process that establish the allocation and scheduling of tasks and communications between tasks on the platform's available resources1 is conducted considering criteria such as performance and power consumption. The establishment of an optimized mapping can be carried out during design phase (static definition) or during operation (dynamic definition). Many works exist in order to propose static approaches for optimizing the mapping of data flow applications on multiprocessor platforms [START_REF] Singh | Mapping on multi/many-core systems: Survey of current and emerging trends[END_REF], [START_REF] Pimentel | Exploring exploration: A tutorial introduction to embedded systems design space exploration[END_REF]. Within the framework of this study, we were interested in the case of systems for which the workload can evolve during operation according to the applications simultaneously executed. For such systems, the static definition of optimized mappings lead to consider a design space that is far too vast given the possible combinations of applications. Consequently, the dynamic definition approaches and therefore online management of resources represent interesting solutions in order to adapt the use of resources during operation and thus optimize the performance and the overall energy consumption of the system. Among the various dynamic definition approaches [START_REF] Singh | A survey and comparative study of hard and soft real-time dynamic resource allocation strategies for multi-/many-core systems[END_REF], we considered a hybrid approach associating static preparation of certain possible mappings for each application and definition during operation of an optimized solution for all the supported applications.

The studied systems consider a set of applications app i executed according to different possible operating situations u m . Each situation u m is characterized by the set {app 1 , . . . , app I } of executed applications. In the study conducted, the considered applications are inspired by the multimedia field, corresponding to the periodic processing of large data streams. These periods represent constraints on the execution times of the applications. For each situation u m , a hyper-period is defined as the least common multiple among the periods of the applications of u m . The SDF formalism is used to describe each application, even if this choice was not a limitation as to the contributions made. In the developed hybrid approach, different possible mappings are considered for each supported application. Figure 4.7 illustrates the notation used to describe the applications studied and the associated mappings. As shown, these mappings represent distinct solutions in terms of

t 1,1 t 2,1 t 4,1 t 3,1 e 1,1 e 2,1 e 3,1 3 1 1 1
1 3 1 1 (a) (b-1) t 1,1 (1) t 2,1 (1) t 2,1 (2) t 2,1 (3) t 3,1 (1) t 3,1 (2) t 3,1 (3) t 4,1 (1)
x s_t11 (1) x e_t11 (1) x s_t31 (1) x s_t31 (2)

x s_t31 (3) x e_t41 (1) time Coeur 1 ST slot1 ET slot1 slot1 Period app1 (b-2) t 1,1 (1) t 2,1 (1) t 2,1 (2) t 2,1 (3)
x s_t11 (1) x e_t11 (1) latency and platform resource usage. Each considered mapping is characterized by a periodic pattern formed by the instants x i (k) when the resources of the platform are used. This pattern corresponds to an execution trace established for each mapping over a given period. In Figure 4.7, the notion of slot designates a time interval during which a computing resource is used by the same task. The instants ST and ET designate the start and end times of the interval. These sets will be referred to as clusters. This type of organization makes it possible to allocate distinct operating frequencies for each cluster [START_REF] Pagani | Energy efficiency for clustered heterogeneous multicores[END_REF]. The proposed dynamic management strategies aimed to minimize the average power consumed over each hyper-period by optimizing the mapping and the operating frequency of the clusters considered. These strategies were proposed at two levels: at the local level within a cluster made up of several cores, and at the global level on the scale of several clusters.

x s_t31 (1) x s_t31 (2) x s_t31 (3) x e_t41 (1) time Latency app1 Coeur 1 STslot1 ETslot1 slot1 Period app1 t 3,1 (1) t 3,1 (2) t 3,1 (3) t 4,1 (1)
STslot2 ETslot2 slot2 Coeur 2

Proposed online management strategies

Local management of computation resources

This sub-section concerns the intra-cluster optimization of the computation resources usage in order to minimize the average power consumed for different applications executed simultaneously. The position of the online manager is shown in figure 4.8.

Online management (allocation, task scheduling and DVFS)

Ongoing situation

Application constraints

Platform resources t1, The object of the studied manager is to establish the operating frequency of the cluster as well as an optimized combination of the execution traces of each of the active applications. In doing so, the timing constraints specific to each application as well as the number of available computing resources must be respected. The proposed strategy assumes a set of information established statically during design:

• for each application supported by the cluster, a limited number of possible mappings are established for different numbers of cores. The considered mappings reflect different occupations of computation resources and thus distinct latencies for each application.

• A specific operating frequency is associated to each considered mapping, corresponding to the smallest operating frequency of the cluster for which the timing constraint associated with the application is respected.

This information is used at the start of each new operating situation u m in order to establish a scheduling and an optimized allocation for all the active applications. To do this, the iterative process illustrated in part (b) of Figure 4.8 is proposed. The first step consists in selecting among the prepared frequencies the smallest value allowing the active applications to respect their own constraints. This selection leads to selecting a first set of execution traces used in order to establish the occupation of the resources for the active applications.

An original method was proposed to optimize the allocation and scheduling of active applications on the computing resources of the cluster [C4-3]. This method uses the prior knowledge of the time intervals during which the computation resources are used for each mapping. Figure 4.9 illustrates this method in comparison with two methods from the literature in the field.

Part (a) of the figure illustrates the time intervals during which two applications denoted app 1 and app 2 use the computing resources. In the considered example, Period app 1 = 2 × Period app 2 and the intervals slot5 and slot6 correspond to the duplication of the intervals slot1 and slot2. Part (b) represents a possible combination of time intervals considering the so-called FCFS (First Come First Served) approach used in [START_REF] Khdr | Power density-aware resource management for heterogeneous tiled multicores[END_REF]. This approach considers the allocation of a single application per core, avoiding the possible sharing of computing resources. Part (c) represents the combination of time slots according to the LASP approach (Longest Available Slot Packing) presented in [START_REF] Singh | Resource and throughput aware execution trace analysis for efficient run-time mapping on mpsocs[END_REF]. This approach successively allocates the tasks taking into account the availability of the cores. In the case illustrated, this approach results in allocating the interval slot4 on core 1 and delaying the execution for the interval slot5. Thus, it has been observed that the LASP approach can lead to increasing the latency of applications over a hyper-period, ultimately leading to higher operating frequencies. The method proposed by Miss Yang makes it possible to preserve the allocation of periodic executions within a hyper period while seeking to limit the number of resources used. This method called GAPVC (Grouped Applications Packing under Varied Constraints), illustrated in part (d), considers the availability of cores by taking into account the duplicate intervals within a hyper-period. The objective of this method is then to establish the allocation of the slots taking into account the duplicated intervals and seeking to limit the number of cores used. Thus, this approach leads to limiting the number of cores used compared to the FCFS method and to limiting the performance degradation observed for the LASP method. On part (d) of Figure 4.9 the interval slot4 is allocated on core 2 in order to avoid delaying the execution of slot5 and in order not to use any additional core . The detailed algorithm of this method is given in [START_REF] Yang | Evaluation and design of a run-time manager for ultra-low power multiprocessor systems on chip[END_REF] and [C4-3].

In order to evaluate the effectiveness of the proposed method, nine different applications were considered. These applications were described according to the SDF formalism with different numbers of tasks, relations and transfers between tasks within an execution period. For each application, between 1 and 3 distinct mappings relating to the use of 1, 2 or 4 cores were prepared statically. For the 9 applications studied, 511 possible operating situations were considered. For each operating situation, the latency obtained for each application and the average power consumed for each combination of applications were then compared according to the method used. Table 4.1 from [START_REF] Yang | Evaluation and design of a run-time manager for ultra-low power multiprocessor systems on chip[END_REF] compares the performance obtained for the GAPVC allocation and scheduling method with the FCFS and LASP methods. For the three sets of cores considered, the number of situations where the generated combination is not satisfactory is estimated. The gain in terms of average power is estimated according to the methods evaluated. The average power was estimated considering the occupation rate of the processor cores and the obtained operating frequency [START_REF] Yang | Evaluation and design of a run-time manager for ultra-low power multiprocessor systems on chip[END_REF]. Thus, in the case of 10 cores, the GAPVC method leads to a reduction in the average power consumed of the order of 206% compared to the LASP method and between 16.6% and 36% with the FCFS method.

We could not compare these predictions to measurements made on a real target. However, the implementation of the GAPVC algorithm was considered for an Exynos 5422 multiprocessor platform based on an ARM big.LITTLE [START_REF] Yang | Evaluation and design of a run-time manager for ultra-low power multiprocessor systems on chip[END_REF] architecture. The execution time of the algorithm is measured for the 511 possible operating situations considered. The average time obtained is 0.137 ms on the LITTLE part (Cortex-A7 core clocked at 1.4 GHz) and 0.037 ms on the big (core Cortex-A15 clocked at 2.1 GHz). The execution time achieved for this algorithm turn out to be lower than those of the FCFS and LASP algorithms.

Global management of computation resources

We consider here the case of platforms organized in cluster, where each cluster groups together a homogeneous set of processor cores and can operate at a specific frequency. For this type of platform, the cluster used for the execution of an application can vary according to the operating situation u m considered. The contribution made aimed to reduce the average power consumed across multiple clusters by optimizing the allocation of applications running simultaneously. The proposal made, illustrated in Figure 4.10, relates to the definition of a hierarchical management of resources. At the scale of the global platform, the proposed method aims to establish at the beginning of each new operating situation u m the allocation of applications on the clusters as well as the operating frequency required for each cluster. At the scale of the cluster, it is a question of establishing the allocation and the scheduling of the tasks of the various applications allocated on the available cores. The management made is based on a set of statically prepared data: for each supported application, a set of possible mappings and, for each mapping, the minimum operating frequency to meet the timing constraints.

The global management approach aims to establish an allocation of applications and a possible frequency of operation of each cluster that minimizes the average power consumed by the entire platform, while taking into account the number of available computing resources and the timing constraints specific to each application. Two allocation strategies were proposed by Miss Yang and are detailed in [START_REF] Yang | Evaluation and design of a run-time manager for ultra-low power multiprocessor systems on chip[END_REF] and [J4-3]. These strategies apply at the start of each new operating situation. The first strategy, named Neighboring Search Application-to-cluster Assignment (NSACA) consists in successively allocating the applications according to their minimum operating frequencies, taking into account the number of computing resources available within each cluster. This strategy does not take account of the allocations prior to the new operating situation evaluated and can therefore generate numerous re-allocations of applications. The second strategy, named Greedy Search Application-to-Cluster Assignment (GSACA), is proposed in order to control the number of re-allocations authorized from one operating situation to another. This strategy allocates newly active applications on clusters delivering a compatible operating frequency and a sufficient number of computing resources. The re-allocation of already active applications is considered in order to further optimize the overall consumption of the newly formed set. According to this approach, the previously presented scheduling strategy, GAPVC, is used to estimate the number of computing resources employed within a cluster.

The evaluation of these strategies, detailed in [START_REF] Yang | Evaluation and design of a run-time manager for ultra-low power multiprocessor systems on chip[END_REF] and [J4-3], was carried out by considering the dynamic allocation of different applications for multiple possible operating situations. This evaluation was conducted for platforms with different numbers of clusters and different numbers of cores per cluster. Figure 4.11 compares the average consumption obtained for the allocation of ten distinct applications according to 1023 possible operating situations. The comparisons relate to the results obtained for the GSACA strategy relative to different strategies in the domain: an exhaustive strategy considering the evaluation of all possible solutions, the LEF strategy (Low Energy First) presented in [START_REF] Pagani | Energy efficiency for clustered heterogeneous multicores[END_REF], the LPF (Low Power First) strategy presented in [START_REF] Muthukaruppan | Hierarchical power management for asymmetric multi-core in dark silicon era[END_REF].

The GSACA method presents performances close to those obtained according to an exhaustive approach for solution search, and this for the various studied platform configurations. On all the configurations considered, the gains observed compared to the LEF and LPF strategies go up to 21.2% and 80.3% respectively. In [J4-3], the influences of the number of application re-allocations and the application scheduling strategy (GAPVC or FCFS) are also evaluated.

Online management architecture modelling and simulation

The purpose of this part of the work carried out within the framework of Ms. Yang's thesis focused on the consideration of online management strategies in system-level modelling and simulation process of architectures. The objective was to allow the simulation of applications executed on high-level models of the targeted platforms, taking into account the developed online management strategies. While many system-level modelling and simulation environments exist, few of them allow for the consideration of online resource management and modification of allocations. In [START_REF] Quan | A hybrid task mapping algorithm for heterogeneous mpsocs[END_REF], the Sesame modeling and simulation environment is extended to take into account the online resource management of a multiprocessor platform. This extension makes it possible to adapt during the simulation the way in which the loads induced by the functions of the application are allocated to the resources of the platform model. In [START_REF] Lemaitre | Dynamic migration and performance optimization of deterministic applications across platform components using intel cofluent studio[END_REF], an adaptation of the Intel CoFluent Studio environment is proposed. A specific API is proposed in order to be able to adapt the allocation of functions during the simulation, however this API is not currently available in the current version of this environment.

This work aimed to take into account the possible modification during the simulation of the allocation of functions on the computing resources of the platform model. The experimented proposal is based on the fact that the online management methods studied in the context of Ms. Yang's thesis lead to establishing for each new operating situation an optimized mapping as well as a new operating frequency. Thus, at the start of each new operating situation u m , a new execution trace is established prior to the execution of the applications on the resources of the platform. In simulation, knowledge of future execution instants allows the manager to successively activate the tasks at the required instants. These instants of activation take into account the evolution during the simulation of the distribution of the functions on the resources of the considered platform. The simulated manager therefore acts in order to notify the availability of the computing resources during the execution of the functions of the application model. Figure 4.12 illustrates this principle for the case of the simulation of two successive situations u 1 , considering the simultaneous execution of two applications app 1 and app 2 , then u 2 , considering the execution only of app 2 . At the start of each operating situation u 1 and u 2 , the manager establishes an operating frequency and an execution trace, thus establishing the instants of use of the resources of the platform. This knowledge allows the manager to activate the tasks according to the required order and at the newly calculated instants. In Figure 4.12, the instants of start and stop of the functions by the manager are represented. These instants then take account of the resources used. This approach was implemented within the Intel CoFluent Studio modelling and simulation environment. Figure 4.13 illustrates this implementation by positioning the manager model with an application model. In the implementation performed, the manager model is graphically captured as a function activated at the start of each new operating situation. The action noted Compute corresponds to a C++ code establishing the traces associated with each application. During the simulation, the manager controls the state of each function of the applications considered at the calculated instants, controlling thus access to the computing resources of the platform.

t 2,2 t 1,2 t 4,1 t 3,1 t 2,1 t 1,1 x s_t1,1 (1) x s_t1,2 (1)
x s_t2,1 (1) x e_t2,2 (1) x e_t2,1 (3) In order to illustrate this implementation, Figure 4.14 illustrates a possible observation of the evolution over time of the dynamic power consumption caused by an application formed of 4 tasks [C4-4]. During the simulation, the manager establishes different operating frequencies and different possible allocations of the tasks. The task execution instants are established and used to activate accordingly the various tasks. The intervals noted (1), ( 4), ( 5) and ( 6) correspond to the durations of execution of the same task but for distinct operating frequencies and allocations.

x e_t2,2 (2) x s_t1,2 (1) x s_t2,
Init_t1,1 Op_t1,1 t1,1 Init_t2,1 Op_t2,1 t2,1 Init_t3,1 Op_t3,1 t3,1 Init_t4,1 Op_t4,1 t4,1 App1 Init_Input

Conclusion

Originally, Mr. Barreteau's thesis focused on the study of mobile radiocommunication systems integrating adaptation mechanisms as imagined according to the paradigms of software defined radio and cognitive radio. Initially, the work carried out focused on the integration of non-functional properties with a view to evaluating performance for complex operating scenarios. This work led to the proposal of a simulation method limiting the number of calls to the simulation engine while preserving the precision of the models created. This thesis was therefore a first step towards the establishment of a general and systematic approach that was subsequently pursued. In a second step, it was a question of approaching the consideration of dynamic adaptation mechanisms within such systems and this in high-level modelling and design approaches. From an organizational point of view, this thesis corresponded to a study carried out not in connection with the development of a new tool but rather with the idea of using and extending the possibilities of an existing environment (Intel CoFluent Studio). Such positioning can be difficult to value the contributions made. Subsequently, Mr. Barreteau was hired within the company ensuring the development of this environment and still participates in it within the Intel company.

The work carried out within the framework of Ms. Yang's thesis represented an opportunity to address the optimization of the energy consumption of multiprocessor architectures. Ms. Yang made substantial efforts to establish original proposals in this very active field of research. However, this work could not be supplemented by experiments on targets which would have been necessary in order to validate the hypotheses made and the results obtained. This work made it possible to transpose certain principles associated with the modelling and simulation approach developed in our other recent projects. Thus, based on the models developed elsewhere, it would be interesting to continue the work started as part of Miss Yang's thesis in order to optimize the energy consumed, also taking into account the use of communication and memory resources of multiprocessor platforms.

Suepervision

PhD thesis

• Simei Yang, Evaluation and design of a run-time manager for ultra-low power multiprocessor systems on chip, University of Nantes, June 2020. Chapter 5

Probabilistic modelling and simulation of multiprocessor systems

Introduction

In the context of embedded multiprocessor systems, the modeling of temporal properties is essential in order to be able to predict and optimize the temporal behavior of programs. However, the sharing of resources within multiprocessor platforms significantly influences program execution times and complexifies the modelling and analysis of temporal properties. In this context, the approaches of probabilistic analysis of temporal properties, probabilistic timing analysis (PTA), have emerged in recent years in order to favour the analysis of multiprocessor systems [START_REF] Davis | A Survey of Probabilistic Timing Analysis Techniques for Real-Time Systems[END_REF] . These approaches consider the analysis of execution times according to a set of possible executions in order to establish and analyze the distributions of the obtained values. Thus, the statistical method EVT (Extreme Value Theory) is considered in [START_REF] Cazorla | Proxima: Improving measurement-based timing analysis through randomisation and probabilistic analysis[END_REF] in order to establish a probabilistic analysis of the worst case execution time (pWCET, probabilistic Worst Case Execution Time ). In [START_REF] Katoen | Probabilistic model checking for uncertain scenario-aware data flow[END_REF], the probabilistic model-checking method is adopted in order to analyze the temporal properties of dataflow applications presenting different possible operating scenarios. In [START_REF] Santinelli | A Probabilistic Calculus for Probabilistic Real-Time Systems[END_REF], a probabilistic extension to the RTC-MPA [START_REF] Huang | Embedding formal performance analysis into the design cycle of mpsocs for real-time streaming applications[END_REF] approach used for best and worst execution time estimation is presented.

In this context, based on the skills developed in modelling and simulation at the system level, my activity focused on the development of two aspects. The first point concerns the establishment of a measurement-based modelling flow for the creation of probabilistic models used for the analysis of the temporal properties of multiprocessor systems. The second point concerns the use of statistical model-checking methods in order to control the simulation of probabilistic models. This set-up aims to establish a complete modelling and analysis flow that we have evaluated, through various experimental achievements on real targets, the accuracy of the results, the speed of analysis and the ability to address complex architectures. These activities were initially initiated through the Master's internships of Miss Nadia Ghazali and Mr. Jiatong Li [C5-1] then developed within the framework of the thesis of Mr. Hai-Dang Vu [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF]. Also, during the thesis of Mr. Hai-Dang Vu, we were able to collaborate with the team of Mr. Kim Grüttner from the German institute OFFIS. This collaboration aimed at establishing and consolidating a common flow of modeling and analysis in order to evaluate the contribution of methods for the probabilistic analysis of multiprocessor systems. The two teams were thus able to share their activities through common case studies and develop complementary contributions. This collaboration has resulted in numerous study trips, in France and Germany, and regular remote meetings. The results of this work have led to various joint publications in an international journal [J5-1] and in international conferences [C3-4], [C5-2], [C5-3].

5.2 Establishment of a measurement-based characterization flow for the creation of probabilistic models

Proposal

This work aims to favour the creation of probabilistic models used for the analysis of the temporal properties of multiprocessor architectures. Two aspects of the functioning of such architectures have been more particularly taken into account: the variation of execution times induced by the data-dependency of programs as well as the effect of shared resources on the execution of programs. The established flow combines a measurement-based characterization approach of the elements of an architecture and the creation of simulable models. The originality of this work compared to the state of the art lies in the possibility to control the level of compositionality of the architectures in order to adopt probabilistic models appropriate to the operating situations observed. In this first part, the case of a fully compositional platform is discussed for which the characterization effort is limited. This choice implies adopting computation and architecture models guaranteeing a strict separation of communication and calculation mechanisms. The case of a non-compositional platform was considered in a second step. The organization of the flow implemented is illustrated in figure 5.1. As indicated, the presented flow comprises three distinct parts. Part (a) corresponds to the prototyping phase aiming to implement on a real target a given application on the resources of the studied platform. The established flow is based on a set of assumptions justified by the characteristics of the applications and the platform considered. Applications are described using the Synchronous Data Flow (SDF) computation model. This model considers the organization of applications in the form of a set of actors communicating through finite capacity FIFO-type communication channels. The behavior of each actor corresponds to a succession of phases of reading from the input channels, execution of the computation and writing to the output channels. This assumption leads to a strict separation between computation and communication mechanisms.

Analysis results

Latency measurement

Simulation models

Access path characterization

In order to respect the separation of communication and computation mechanisms, the considered platform is organized on the basis of tiles (tile-based platform). Each tile corresponds to a processor core associated with local memory for instructions and data. This organization leads to avoiding any interference between tiles during the execution of computations. Each tile also has a communication interface for access to the shared communication bus. Communications between tiles are made through a shared memory. The allocation of actors on the tiles is established once the programs are compiled and is not modified during execution. The execution of the application is done according to the dependencies established between the actors and taking into account the availability of shared resources. Such an organization is fully compositional: modifying the allocation of the application and using more tiles does not modify the computation times measured for each actor for a given configuration. The characterization made of the computation times is therefore valid for different organizations of the platform and different allocations of the application.

The measurement infrastructure includes the resources needed to record the computation times of the actors on the tiles as well as the communication times between actors. For the computation time measurement, we used the device developed within the OFFIS institute, presented in [START_REF] Schlaak | Power and execution time measurement methodology for sdf applications on fpga-based mpsocs[END_REF], in order to measure the duration required between the start and the end of a phase of calculation of an actor. This device was also used to measure the end-to-end latency of complete applications. For the measurement of the communication times, we used a logic analyzer device allowing the observation of the signals of the communication bus. These observations made it possible to record the start and end times of the various phases of communication between tiles.

Part (b) of the flow corresponds to the modelling phase which aim at obtaining a simulable model. This phase uses as input the description of the application and the platform as well as the measurement results related to the execution of an application on the resources of a platform. The upper part of Figure 5.2 details the process leading to the modelling of computation resources. Once the prototyping phase on a real target has been carried out, the studied application is executed on the implemented platform. This execution makes it possible to record the computation durations associated with each actor of the application and this for multiple iterations of the application. Each iteration corresponds to the processing of distinct data, they can therefore make it possible to identify distinct paths within the executed program. The durations thus recorded for each actor are then analyzed in order to establish a representation in the form of a random variable according to a given law of probability. In this chapter, we will present the application of Gaussian laws to describe these variations. The combination of several Gaussian distributions was also considered in [J5-1] using the inference method Kernel Density Estimation (KDE) [START_REF] Rosenblatt | Remarks on some nonparametric estimates of a density function[END_REF]. The right part of Figure 5.2 illustrates the organization of the SystemC model created. The Tile0 and Tile1 modules describe the execution of the actors allocated on the computation resources. The behaviour of the actors is described taking into account the durations measured. The function noted GetDelay allows to set the computation duration according to the distribution resulting from the measurement data.

The module denoted Interconnect models tile accesses to shared memory. The functions ReadTokens and WriteTokens implement the communication protocol for the transfer of tokens through shared memory. This protocol is the same as the one previously described in Chapter 3, Figure 3.6. The Shared memory module models the effect of read and write accesses to memory during communications. The lower part of • The first approach, presented in [C5-3], corresponds to a static analysis at the assembler level of the code developed to implement the functions ReadTokens and WriteTokens. The instructions associated with each phase of the communications are identified and the durations of each phase are thus estimated. These durations were used within a transfer level model.

• The second approach, presented in [C5-2], uses the measurement infrastructure to record the durations of the different elementary phases of communication. These readings were then used in transfer and transaction level models as presented in Chapter 3.

• Finally, the third approach, presented in [C3-4], [J5-1], also uses the measurement infrastructure to record the durations of the different elementary phases of communication and this in connection with the message-level simulable model proposed in Chapter 3.

Part (c) of Figure 5.1 corresponds to the analysis phase of the flow, consisting in carrying out the simulation of the models created. The property analyzed was essentially the end-to-end latency of applications. The simulation results are then compared to the measurements made on the real target. It was then possible for us to quantify the level of precision achieved by the created models as well as to note the required simulation duration. The assessment of the established flow was carried out for different applications and different allocations of applications on the resources of the platform.

Different approaches exist to calibrate performance models of multiprocessor architectures. In [START_REF] Kreku | Combining uml2 application and systemc platform modelling for performance evaluation of real-time embedded systems[END_REF], three families of approaches are presented. The first consists of establishing an analytical model to quantify the execution time of an algorithm, taking into account parameters such as the number of elementary operations to be performed, the number of memory accesses or the size of the manipulated data. The second approach consists in statically analyzing the code of the algorithm considered in order to extract the possible execution durations. Finally, a third presented approach consists in extracting information directly from executions on a real target. In [START_REF] Pimentel | Calibration of abstract performance models for system-level design space exploration[END_REF], an approach is presented for the calibration of models created within the framework of the Sesame environment [START_REF] Erbas | A framework for system-level modeling and simulation of embedded systems architectures[END_REF]. The elementary computation and communication times come from simulations made using instruction set simulators for the programmable processor part or simulations at the register transfer level for the dedicated hardware resources. The approach presented in [START_REF] Bobrek | Stochastic contention level simulation for single-chip heterogeneous multiprocessors[END_REF] associates a simulation at a high level of abstraction of multiprocessor architectures with a stochastic model making it possible to deduce the effect of contention to shared resources on the execution of the software. This stochastic model is established from preliminary tests of reference programs on detailed descriptions of the resources studied. The creation of probabilistic models of multiprocessor systems from measurements has also been adopted by Nouri et al. [START_REF] Nouri | Astrolabe: A rigorous approach for system-level performance modeling and analysis[END_REF] to extend the BIP modeling environment [START_REF] Nouri | Statistical model checking qos properties of systems with sbip[END_REF]. This approach consists in executing the entire application on the real target in order to establish a representation of the execution times of each actor composing the application. A detailed presentation of these approaches is given in the research report [R1-1].

Results

The purpose of the experiments carried out was to validate the relevance of the established modelling and simulation flow, both for the construction of computation and communication models. First, the accuracy of the created models was analyzed by comparing the estimates obtained for the end-to-end latency of the applications with the measurements made on a real target. The simulation duration of the created models was also analyzed. The applications and the platform considered for these experiments are the same as those presented in Chapter 3, Section 3.3. These systems were realized on a Xilinx ZC702 prototyping board based on Zynq-7000 FPGA. For these experiments, the models of the studied systems were created according to the process indicated in Figure 5.2. Computation times were measured by running 1 000 000 iterations of each application on a single platform processor. These measurements were then analyzed in order to establish the distribution of execution times for each actor. The different communication models created were considered and a complete comparison of the results was presented in [J5-1]. In this part, we will present the main results obtained for the transfer-level communication models annotated from measurements, as mentioned in Chapter 3. Figure 5.3, taken from [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF], presents the distribution of end-to-end latency values of the studied systems obtained by measurement and by simulation. The upper part of the figure corresponds to the results obtained for three distinct allocations of the Sobel filter application. The lower part corresponds to the results obtained for three allocations of the JPEG decoder application. The curves presented illustrate the distribution of the values observed for the iteration latencies. These values were obtained by measurement on a real target or by simulation. Two types of models are considered here according to the representation of the computation times. The curves presented in blue correspond to the values obtained by measuring the iteration latencies on a real target. The curves presented in red correspond to the values obtained by simulation of models using a Gaussian law in order to describe the distribution of the computation times of the actors. Finally, the dotted vertical lines indicate the mean values associated with each set of values. For all the studied configurations, the achieved level of accuracy in predicting mean values is acceptable: a difference between simulation and measurement of 7.7% for the configuration Sobel4 and 1.75% for the configuration Jpeg7. As mentioned in chapter 3, we were able to further improve the level of precision by using the message-level communication model. This precision can also be estimated taking into account the shape of the distributions. In [J5-1] the so-called Bhattacharyya distance criterion [START_REF] Bhattacharyya | On a measure of divergence between two statistical populations defined by their probability distributions[END_REF] is used to quantify the similarity between the distributions obtained. According to this criterion, the KDE approach is more efficient for applications with a large number of possible data paths.

With regard to the analysis duration criterion, we compared the simulation durations of the different models with the time required to execute the applications studied on the real target. Thus, the execution of the Sobel filter application, for 1 000 000 iterations, on four tiles takes just over 7 minutes1 . Running the Jpeg decoder application, for 1 000 000 iterations, on seven tiles takes just over 5 hours. The use of simulable models, at the transfer level, leads to executions of the order of 12 seconds for the Sobel filter on 4 tiles and 2 hours for the Jpeg decoder on 7 tiles [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF]. In Chapter 3, we also observed how the message-level model proposed to describe communications allowed a significant reduction in simulation durations (Table 3.3).

The various experiments carried out have demonstrated the effectiveness of the models created. Given the assumptions made, these models can be used to analyze different allocations of the application on the platform. The variability of the execution times of the applications is essentially found within the computation times, taking into account the data dependencies of the algorithms studied. The influence of shared resources was correctly described through the models of communication resources gradually put in place. The creation of effective probabilistic models therefore opens the way to the use of advanced methods to control their simulation. This work is the subject of the next section.

Adoption of statistical model-checking analysis methods

Proposal

The work mentioned so far dealt with the analysis of the behaviour of systems analyzed through simulation. An intrinsic limit of this analysis approach relates to the limited coverage of operating situations. Our objective here is to allow a more successful simulation analysis, by offering the possibility to the designer to control the simulation effort given a level of confidence in the analysis carried out. To do this, the so-called statistical model-checking approach (statistical model checking, SMC [START_REF] Legay | Statistical model checking: An overview[END_REF]- [START_REF] Benoit | Vérification Classique et Statistique pour les Systèmes Probabilistes[END_REF]) is considered. This approach is based on the simulation of a probabilistic system, subsequently denoted S. A simulation of S generates an execution trace corresponding to a sequence of states from S. Using the probabilities inherent in S, the execution traces are generated randomly. They therefore constitute representative samples making it possible to estimate the probability according to which an execution trace satisfies a given property, noted ϕ. Two types of algorithms make it possible to estimate either the probability with which S satisfies ϕ (quantitative analysis), or whether the probability with which S satisfies ϕ is greater than a given bound θ (qualitative analysis). Such analyzes can be useful in the process of sizing resources and verifying non-functional properties.

The algorithms used to conduct a quantitative analysis come from Monte-Carlo techniques [START_REF] Robert | Monte Carlo Methods[END_REF], [START_REF] Hérault | Approximate probabilistic model checking[END_REF]. Let γ be the probability with which S satisfies ϕ and γ N the estimate obtained for N samples. It is possible to bound the precision of γ N and the probability that an error will occur [START_REF] Hoeffding | Probability inequalities for sums of bounded random variables[END_REF]. We can then calculate the minimum number of samples that guarantee a given precision, noted δ and therefore such that |γ N -γ| ≤ δ . We introduce α, called the confidence parameter, such as Pr(|γ N -γ| ≤ δ ) ≥ 1α. In [START_REF] Hérault | Approximate probabilistic model checking[END_REF], [START_REF] Laplante | Probabilistic abstraction for model checking: An approach based on property testing[END_REF], it is shown that considering N ≥ 4 δ 2 ln( 2 α ) then it is guaranteed that Pr(|γ N -γ| ≤ δ ) ≥ 1α. Therefore, it is possible to estimate the probability that S satisfies ϕ with a precision δ and a confidence level 1α by averaging the number of simulations satisfying ϕ with the number of total simulations. The approach used to conduct a qualitative analysis derives from the so-called hypothesis testing technique (hypothesis testing). In order to establish whether γ is greater than a limit θ , it is necessary to compare the hypothesis H 0 such that γ ≥ δ with the hypothesis H 1 such that γ < δ . The strength of such a test is determined by the parameters α and β respectively bounding the probabilities that H 0 is accepted while H 1 is true (type I error) and that H 1 is accepted while H 0 is true (Type II error). However, it is impossible to ensure a low probability for both types of error. A symmetric indifference region denoted [γ 1 , γ 0 ] is then used, centered on θ and for which p 1 = θδ and p 0 = θ + δ . The SPRT algorithm (sequential probability ratio test) presented in [START_REF] Younes | Verification and planning for stochastic processes with asynchronous events[END_REF] makes it possible to perform this hypothesis test.

These algorithms have been implemented in various probabilistic model analysis tools, including UPPAAL [START_REF] David | UPPAAL SMC tutorial[END_REF] and PRISM [START_REF] Kwiatkowska | Prism 4.0: Verification of probabilistic real-time systems[END_REF]. Also, the SMC approach has been applied to different types of [START_REF] Bulychev | Uppaalsmc: Statistical model checking for priced timed automata[END_REF] systems. Compared to the formal methods applied to probabilistic models, known as probabilistic model-checking (probabilistic model checking, PMC), SMC does not allow exact quantification of the probability that the given property is satisfied. However, SMC methods offer strict guarantees on the accuracy of the γ N estimates. Also, the approximation made is obtained with a lower analysis time compared to full resolution methods, SMC not suffering from the state space explosion problem inherent to model-checking in general. The application of the SMC method to the analysis of the temporal properties of multiprocessor systems is recent, in particular through the work presented by Nouri et al. [START_REF] Nouri | Rigorous system-level modeling and performance evaluation for embedded systems design[END_REF]- [START_REF] Nouri | Statistical model checking qos properties of systems with sbip[END_REF]. In [START_REF] Nouri | Building faithful high-level models and performance evaluation of manycore embedded systems[END_REF], the application of SMC is presented for the qualitative analysis of the temporal properties of an image processing application running on a multicore platform. The SPRT method was then used within the SBIP [START_REF] Nouri | Statistical model checking qos properties of systems with sbip[END_REF] analysis tool. In [START_REF] Chen | Variation-aware evaluation of mpsoc task allocation and scheduling strategies using statistical model checking[END_REF], the UPPAAL-SMC tool is used to jointly evaluate the timing and power properties of allocated applications on multiprocessor platforms. This same tool was used in [START_REF] Stemmer | Probabilistic state-based rt-analysis of sdfgs on mpsocs with shared memory communication[END_REF] to conduct an analysis similar to the one we conducted. This work illustrates the use of the UPPAAL-SMC formalism and the difficulties in modeling the different aspects of the systems studied. In [START_REF] Ngo | Statistical model checking for systemc models[END_REF], the use of SMC for the analysis of SystemC models is considered for a control-command system distributed on three processors. First, our approach differs from these works by the fact to establish a scalable approach, with the objective to favour the analysis of different possible applications and allocations. This objective therefore implies specific hypotheses on the calculation and architecture models used. Secondly, we adopted the SMC approach to the case of SystemC models of multiprocessor systems, in order to have a greater flexibility in comparison with tools like UPPAAL-SMC. Finally, the experiments carried out on different applications, platforms and possible allocations have made it possible to evaluate the effectiveness of the SMC method with regard to the criteria of accuracy and simulation speed. The modeling flow previously presented has been extended to allow the implementation of SMC according to the principle presented in Figure 5 The flow considers a probabilistic model created by following the approach previously described. A monitor is added to observe the variables of interest of the model during the simulation. For each observed variable, the monitor delivers an execution trace of the form: ω = (s 0 ,t 0 ), (s 1 ,t 1 ), ..., (s N-1 ,t N-1 ), N ∈ N, where each couple (s i ,t i ) indicates a particular state s i and an instant t i ∈ R ≥0 . The generated execution traces are analyzed during the simulation by the SMC analysis tool in order to establish whether the analyzed properties are respected or not. The analysis tool successively triggers the simulations of the model, the number of simulations depending on the statistical algorithms used and their specific parameters. Within the framework of our work, we more particularly considered the use of the Plasma-lab analysis environment [START_REF] Boyer | PLASMA-lab: A Flexible, Distributable Statistical Model Checking Library[END_REF], as it allows the analysis of models written in SystemC [START_REF] Ngo | Statistical model checking for systemc models[END_REF]. Figure 5.5 details the creation of the analyzed SystemC model as well as its control by the SMC analysis tool. This flow considers as input a probabilistic model written in SystemC and created by following the the variables to be observed within the probabilistic model. The SystemC description of this monitor is obtained using the Monitor and Aspect-advice Generator (MAG) tool described in [START_REF] Ngo | Statistical model checking for systemc models[END_REF]. The instrumentation of SystemC models aims to allow communication between these models and the generation of execution traces [START_REF] Tabakov | Monitoring temporal systemc properties[END_REF]. This instrumentation is operated automatically using the AspectC++ tool. The obtained description can then be compiled in order to have an executable model that can be interfaced with the Plasma-lab environment.

Analysis results

Latency measurement

Probabilistic

In the considered approach, the properties are expressed in the so-called Bounded Linear Temporal Logic (BLTL) language. This language is an extension of the Linear Temporal Logic (LTL) language considering bounded temporal operators. These properties apply to finite execution traces, taking into account the fact that the simulation itself is of finite duration. These properties will be used to conduct both quantitative and qualitative analyzes on the created models. In the considered case studies, we have expressed properties in this language in order to estimate the average execution latency of applications.

Results

The experiments carried out aimed to evaluate the contribution of SMC techniques to the simulation-based analysis of the temporal properties of multiprocessor architectures. These experiments extend the studies previously described in this chapter. The applications considered correspond to those illustrated in Figure 3.10, that is to say the Sobel filter and the JPEG decoder. Two platform configurations were studied. The first configuration corresponds to the fully compositional configuration considered in the previous section. The objective was to evaluate the contribution of the SMC method and its influence on the precision delivered and on the duration of the analysis. A second platform configuration, non-compositional this time, was considered in order to consider the possible extension of the developed approach. This second configuration considers a global DDR memory, shared by all the tiles of the platform and external to the FPGA used for prototyping. In addition, within each tile, the data and instruction caches are activated, thus ensuring exchanges with the global memory. This configuration corresponds to an organization that is more representative of current multiprocessor architectures and allows larger program sizes than for the first configuration. This configuration however implies having to take into consideration the effects of the caches and of the accesses to the global memory during the calculations carried out within each processor as well as during the execution of the communications between processors. These effects therefore imply possible contention during the communication and calculation phases. Furthermore, for the two configurations mentioned, a shared memory is dedicated to communications between tiles.

The creation of probabilistic models is carried out following the process previously used. The computation times associated with each actor were estimated as following Gaussian laws whose parameters (mean value and standard deviation) were established from the taken measurements. The message-level communication model presented in chapter 3 was used. For the second configuration of the platform, the measured durations of the elementary communication phases illustrated the influence of the new resources used. These durations were described in the form of random variables with value following a uniform law between the minimum and maximum values measured. Details of the quantities resulting from the characterization phase are given in [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF] and [C5-4].

Subsequently, we present the results obtained for a quantitative analysis of the models created. This analysis aimed to estimate the average duration of the iterations of the studied applications, allocated on different resources of the platforms considered. To do this, the properties were established in order to estimate the probability that this duration is included in a given interval, this estimate being repeated for different time intervals.

First configuration of the platform

The first criterion addressed relates to the precision of the estimates obtained by adopting the SMC approach. Figure 5.6 illustrates the distribution of the estimates obtained for different intervals of time in the case of the Sobel filter distributed over 4 tiles. These estimates lead to the establishment of the estimated average value. Table 5.7 presents the average measured values of the execution times of the considered applications for different allocations on the platform and for a total of 1 000 000 iterations. These values are to be compared with the values obtained in simulation for 1 000 000 iterations. The last column presents the average values obtained for controlled simulations according to the SMC approach. The SMC method used corresponds to the Monte-Carlo method with the parameters δ = 0.02 and 1α = 0.98. In this case, only 5757 successive iterations are carried out. The results obtained by using the SMC approach show a satisfactory level of accuracy compared to an intensive simulation involving a higher number of iterations. We were also able to observe the significant influence of the parameter α on the number of iterations required and on the level of precision reached [START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF], [C5-4]. It is thus possible to control the simulation effort with regard to the desired level of confidence.

However, the use of the SMC method involves an additional cost in terms of model analysis time. Thus, the simulation of 5757 iterations of the model for the Sobel4 configuration has a duration of 1 minute and 44 seconds, to be compared to 5 seconds for the simulation of 1 000 000 of iterations without SMC method 2 . For the configuration Jpeg7a the analysis time is 2 minutes and 16 seconds compared to 29 seconds for the simulation of 1 000 000 iterations without SMC method. This observation underlines the influence of the addition of the SMC method to the simulation of probabilistic models. This influence comes from the need for the Plasma-lab tool to note the evolution of the variables observed at each advancement in the SystemC simulation time. However, the analysis times remain satisfactory and such results validate the possible use of the SMC method for the evaluation and comparison of the performances of different possible architectures.

Second configuration of the platform

For this second platform configuration, only the Sobel filter application was considered, given the excessive execution times in the case of the Jpeg decoder. Figure 5.8 illustrates the distribution of the estimates obtained for different time intervals in the case of the Sobel filter distributed over 4 tiles. Table 5.9 presents the average values observed by the measurement on real target and by simulation. The results presented in the second column correspond to the average values measured for 10 000 000 iterations of the applications. The third column corresponds to the estimated value after the simulation of 1 000 000 iterations of the considered probabilistic model. Finally, the fourth column presents the average values resulting from the simulation of this model using the SMC method. The results presented are obtained for the simulation of 5757 iterations of the application. We always observe a very good level of precision for a lower number of simulated iterations. The simulation times noted for these experiments are of the order of 5 seconds for the simulation of 1 000 000 iterations of the probabilistic model created and of the order of 1 minute and 40 seconds for the simulation of 5757 iterations of the same model controlled by the SMC approach.

This second configuration allowed us to tackle a platform with a two-level memory hierarchy. The experiments carried out have shown the validity of the approach with, however, limits due to the noncompositionality of the platform. Thus, it would be appropriate to approach the modelling of the mechanisms of cache or DDR memory in order to limit then the effort of characterization of the resources of calculation 2 Simulations carried out on an Intel core i7 2.5GHz machine, 8GBytes of RAM, under Ubuntu. and communication. Moreover, through this second configuration, we were also able to observe the relevance of the proposed message-level communication model, even in the case of variations in the durations of the elementary communication phases.

Conclusion

The work carried out on this theme has led to the establishment of a complete modelling flow for the analysis of the temporal properties of multiprocessor systems. The effectiveness was illustrated through various case studies implemented on a real target. The contributions made are methodological and experimental. The efficiency of the proposed flow is based on the strict separation between communications and calculations, separation established at the level of the application and the execution platform. The extension of this flow is however necessary to address more advanced platforms that do not guarantee this separation. Moreover, it would be interesting to extend the proposed approach in order to allow the modelling and the analysis of the energy consumed for multiprocessor embedded systems. This would make possible a joint optimization of performance and power consumption. These aspects will be addressed in particular through the thesis of Mr. Quentin Dariol, started in September 2020, about to the modelling and optimization of applications based on neural networks under time and energy constraints.

From an organizational point of view, beyond the supervision of Mr. Hai-Dang Vu's thesis work, this activity has enabled the establishment of fruitful exchanges with a research team from the OFFIS institute in Germany. The quality of this collaboration is based on the understanding and integration of the respective skills and interests of each partner. In addition, this collaboration has led us to pay particular attention to the dissemination and reproducibility of experiments, through specific tools (github, zenodo). Finally, this research project has led to simultaneous modelling and prototyping on a real target, which represents substantial efforts in the context of doctoral theses. In order to effectively pursue this approach, we will therefore need to be able to include it in projects allowing us to provide the technical support necessary for carrying out the experiments in connection with the research work. The work presented in this document falls within the field of the design of hardware-software architectures of embedded systems. This work is motivated by the need to control the design complexity of these systems.

Supervision

The definition of reliable high-level abstraction models thus represents an essential issue in order to support the analysis and the dimensioning of the architectures. The contributions brought within the framework of my works go in the direction of the improvement of the effectiveness of the models used for the simulation-based analysis of the architectures. Various case studies have made it possible to refine and demonstrate the relevance of the contributions made. For certain studies, we could compare with measurements on real targets. Different research directions have been drawn up in order to continue to consolidate and enhance this work.

A first axis of study identified in Chapter 1 of this document concerned the control of the simulation effort. Thus, the hybrid approach presented makes it possible to limit the number of calls to the simulation engine while preserving the precision of the models created. Through various co-supervised theses, the case studies carried out have made it possible to gradually enrich the approach and to quantify the gains obtained in terms of precision and simulation speed. In parallel, a systematic approach for the creation of models was proposed in order to consider an automation of the developed approach. In the medium term, it would be interesting to apply the proposed approach to new case studies addressing other advanced mechanisms of the operation of multiprocessor systems as well as developing the tools required to support such an approach.

A second area of study focused on controlling the modelling effort required in order to establish models that deliver a good compromise between analysis speed and accuracy. In this sense, the proposal of a generic execution model represents a guide for the creation of efficient high-level abstraction models. This model was completed by associating an approach based on measurement. The experiment carried out around the modelling of the ARM AXI4-Lite multiprocessor bus protocol has made it possible to illustrate the interest of this combination. Thus, probabilistic modelling based on measurement represents an approach with great potential in order to be able to understand complex architectures for which shared resources significantly influence the behaviour of applications. The experimental approach put in place could thus be extended to be able to consider such phenomena. This approach could also be extended to take into account the induced power consumption, opening the way to modelling, analysis and optimization at the system level of the energy consumed by such architectures.

Finally, on the axis of online management of multiprocessor architectures, a first set of proposals focused on the definition of methods for the modelling and simulation of such management within an industrial software environment. Subsequently, some allocation and scheduling strategies have been proposed in order to improve the energy efficiency of multiprocessor systems. It would be interesting to consider the application of this work in the case of the experimental platform set up through the PETA-MC project, thus making it possible to refine and validate the proposals made and the models established. Also, taking communication and storage resources into account would be necessary in order to optimize the proposed allocation strategies.

Beyond this scientific and technical assessment, some general observations can also be made.

In this document, the presentation made of the work particularly focuses on describing a modelling and simulation approach by first addressing the principles of this approach and then its application to different case studies. This work has been gradually built up over time in parallel with the co-supervised theses and the collaborative projects carried out. Such a presentation makes it possible to underline the mutual contributions between projects carried out over limited periods and more in-depth work. In the longer term, it seems useful to me to be able to continue with such an approach in addition to research by project.

On another level, the presented research work is particularly consistent with the teaching activities that I carry out. The interaction between these two facets is gradually proving fruitful: setting up student projects or practical work addressing aspects developed in research, enrichment of courses given in Master program, student internships with research partners, support of students trained in the engineering cycle towards research. In addition, the supervision of thesis students, and training in research through research, is a particularly enriching experience from the point of view of the teacher and researcher. I was able to co-supervise students of different backgrounds, nationalities and sensitivities. This supervision requires supporting students on research topics while ensuring the development of their own sensitivity.

Finally, the work carried out presupposes a large part of experimentation on complex targets. This can represent a significant effort in the context of theses that do not fit into an advanced collaborative context. Therefore, the establishment of CIFRE conventions1 seems to me an important objective in order to establish closer collaborations with companies in the field. The achievements put in place will be able to convince of the relevance of the work carried out.

Prospects and directions envisaged

Current environmental issues tend to consider an increasing digitization of our societies. The proliferation of embedded systems should therefore continue in many areas, with strong constraints in terms of computation efficiency, power consumption, security and reliability. Mastering the complexity of future hardware-software architectures will therefore remain a key challenge. Also, it is important to consider solutions to limit the carbon footprint of such a digital transition and this for all phases of a product's life cycle: design optimization of hardware and software resources, operational functioning with the optimization of energy consumption and the lifespan of products, the recycling of these systems. The planned research project fits into this context by relying on the work previously carried out and by opening up new directions.

First, the thesis of Mr. Quentin Dariol, started in September 2020, addresses the prediction of the performance and energy of multiprocessor systems for applications based on neural networks. This thesis work, in collaboration with the OFFIS institute in Germany, is based on the prototyping and modeling environment previously set up as part of the PETA-MC project. Ultimately, this work should address the modeling and analysis of such architectures in order to optimize their performance and energy efficiency. The expected contributions go in the direction of the definition of performance and energy models of multiprocessor architectures for neural networks, with the development of a measurement infrastructure adapted to take into account the consumption of architectures. This thesis therefore represents an opportunity to consolidate and refine our work for new types of applications and constraints. Also, in this field of the implementation of artificial intelligence algorithms for embedded systems, exchanges have been initiated with certain members of the Images department of the IETR in order to study the case of so-called dynamic neural networks. Such algorithms have strong dependencies on the processed data and presents adaptability of the network architectures [START_REF] Han | Dynamic neural networks: A survey[END_REF]. Given the irregularities in their flow of execution, these algorithms prove to be inefficient for executions on graphic processors (GPU). The study and proposal of hardware-software architectures adapted to this type of network are the subject of an exploratory project supported internally by the IETR laboratory. This project will be carried out in 2022 through two supervised Master's level internships within the two teams involved.

The continuation of the collaborations initiated with the OFFIS institute 2 is currently envisaged according to two themes. The first theme deals with the analysis of temporal properties for non-compositional multiprocessor platforms, for which shared resources significantly influence the execution of programs. Typically, platforms based on shared cache memory can be analyzed. The experimental approach set up within the framework of the PETA-MC project offers the possibility to estimate the worst case execution time in a probabilistic way (pWCET, probabilistic worst case execution time). The adoption of methods based on the EVT approach (Extreme Value Theory) would make it possible to establish a distribution of the pWCET from the execution times measured [START_REF] Davis | A Survey of Probabilistic Timing Analysis Techniques for Real-Time Systems[END_REF]. However, the application of this approach raises the question of the representativeness of the processed data and the measurement protocol considered so far in our approach should be adapted. The perspectives of such works would be to allow a reliable prediction of worst case execution times of data flow oriented applications for complex multiprocessor platforms. The second topic envisaged aims to address the study and optimization of neural networks for multiprocessor platforms under time, power consumption and reliability constraints. The aim is to define static and dynamic optimization methods for the allocation and scheduling of neural networks distributed over several computers. Computer overload or failure situations would be considered. On-line management of the resources would allow the adaptation of the distribution of the computations taking into account the constraints imposed on the complete system. For the two themes mentioned, experiments on real prototypes are planned in order to compare the models created.

These themes highlight two basic trends in the field of research:

• the integration of new artificial intelligence algorithms within embedded systems implies new use cases that should be taken into account and modelled;

• the ever-increasing complexity of platforms requires the development of original methods to favour the creation of efficient models for performance estimation.

Thus, in the medium term, it seems appropriate to me to approach these developments according to two complementary axes: the integration under constraints of artificial intelligence algorithms and the use of artificial intelligence for the system-level design of architectures.

On this first line of work, the integration of artificial intelligence algorithms within embedded systems imposes new needs within execution platforms. In order to dimension architectures under constraints, it will be necessary to consider more specifically the influence of the storage resources on the temporal behaviour of the architectures. The models proposed so far will have to be extended in order to allow a dimensioning taking into account the placement in memory of the data of the algorithms (for example, the parameters of neural networks) and the characteristics of the memories considered. The hybrid approach implemented, combining simulable models, calculations and characterization by measurement, can be used to provide reliable models of the influence of storage resources. Using the models then created, it will be possible to explore the design space with the aim of proposing implementations of artificial intelligence algorithms optimized under the constraints of available resources, performance and consumption. This work could be carried out in collaboration with some of the national and international teams addressing different aspects to optimize the hardware-software architectures of embedded systems for artificial intelligence. We are thinking here first of all of the methods of automatic neural architecture search (neural architecture search, NAS) which could be completed using the models developed. Secondly, if the platform developed within the framework of the PETA-MC project can be initially considered, the application of this work to the case of platforms built around RISC-V technology would be interesting. This technology offers many perspectives for optimizing hardware-software architectures under performance and energy constraints. It also receives strong interest from industry. Finally, this study may lead us to take an interest in other forms of calculation, which are gradually emerging. One thinks in particular of the case of neuromorphic computing, some implementations of which are beginning to emerge in the industrial environment (for example, the Loihi 2 architecture presented by Intel in 2021). Thus, the integration of these new forms of calculation in interaction with more traditional architectures and the joint dimensioning of resources opens the way to the proposal of new methods of analysis and dimensioning [START_REF] Staudigl | A survey of neuromorphic computing-in-memory: Architectures, simulators and security[END_REF].

On the second line of work mentioned, we see that artificial intelligence methods benefit many engineering fields. In the field of the design of embedded systems, such methods could in particular promote the creation of reliable high-level abstraction models based on prior observations. One example is the use of learning methods to help predict program performance. Such methods, notably described in [START_REF] Zheng | Lacross: Learning-based analytical cross-platform performance and power prediction[END_REF] and [START_REF] Gamatié | Empirical Model-Based Performance Prediction for Application Mapping on Multicore Architectures[END_REF], consider the prior training of a performance model from a set of programs executed on a given target. The trained model is then used to predict the performance of new programs. An extension of this work has recently been proposed for multiprocessor platforms [START_REF] Saeed | Learning based memory interference prediction for co-running applications on multi-cores[END_REF]. The platform and the tools set up within the framework of the PETA-MC project could be used to study such methods. It would thus be interesting to evaluate the influence of the level of compositionality of the architectures on the learning methods studied. Also, artificial intelligence methods could be considered in order to promote the exploration of the architecture design space and the selection of suitable architectures, given the many constraints to be respected. If these methods are beginning to be considered for the design of hardware resources of integrated circuits [START_REF] Huang | Machine learning for electronic design automation: A survey[END_REF], their adoption in the design flow of hardware-software architectures of embedded systems represents a particularly interesting perspective. The integration of such methods within design flows would then represent an additional step in the evolution of design practices for electronic systems associating hardware and software resources.

Future developments both within the architectures of embedded systems and in the design practices of these architectures will bring out new needs among industrial players. The training of students in these new technologies therefore appears essential in order to meet these needs. As such, it will be important to associate such training with the ethical issues associated with these new technologies (data security, environmental responsibility, technological sovereignty and independence, neutrality of algorithms). All of these developments and the associated questions represent, both for the teacher and the researcher, particularly rich and stimulating perspectives.

3 . 4

 34 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Lessons taught in the field of embedded system design. The titles in bold are modules which I assume the responsibility, the titles in italics are modules which I episodically participated. . 2 Position of research activities in the field of hardware/software architectures design of embedded systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 The Y diagram with detailed at the system level, inspired from [16]. The main activities led at the system level are identified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Illustration of the compromise between accuracy and analysis time for different performance evaluation methods, (a) simulation-based approaches, (b) formal approaches. . . . . . . . . 1.3 Different levels of complexity in shared resources of multiprocessor systems. . . . . . . . . 1.4 Position of the covered research topics, main projects and co-supervised PhD thesis. . . . . 2.1 (a) Example of a system-level model with three architecture viewpoints: functional, executive and physical, physique, (b) description of functions behaviours with elementary communication and computation statements. The execution semantic related to each statement needs to be defined such as illustrated in Figure 2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Discrete event simulation of the architecture model in the figure 2.1. In this example, the instants associated with the communication of M 2 via the interfaces IF1 and IF2 and the communication bus N are detailed. The instants associated with the communications of the other relations are not detailed for the sake of readability. The shaded part corresponds to a situation of contention on the interface IF1. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 (a) Execution of a model with classical simulation approach, (b) execution of a model with instantaneous computation of future simulation instants. . . . . . . . . . . . . . . . . . . . . 2.4 (a) Situation with erroneous prediction of instants when a shared resource is used, (b) principle of the correction method of resource usage instants. . . . . . . . . . . . . . . . . . . . . . 2.5 (a) Notation of timed Petri nets used to describe the dependencies between simulation instants, (b) expression of the transition instants in the illustrated network. . . . . . . . . . . . . . . 2.6 Examples of elementary patterns used to describe the dependencies between start and end instants of computation and communication statements. . . . . . . . . . . . . . . . . . . . . 2.7 Examples of patterns related to communication statements: (a) rendez-vous protocole, (b) infinite capacity FIFO protocol. T W r and T Rd denote the write and read durations. . . . . . . 2.8 Examples of built Petri net models to describe the dependencies between start and end instants of communication and computation statements. . . . . . . . . . . . . . . . . . . . . . . . . 2.9 (a) Structural and behavioral description of the proposed generic execution model, (b) management procedure of the computed instants. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Influence of the complexity of the calculation method on the achieved simulation speed-up. . 3.1 Illustration of levels of abstraction in communication description for the two case studies. . . 3.2 Illustration of the distributed architecture studied in the scope of the CIFAER project [J3-1]. 3.3 Illustration of exchanged between two HomePlugAV interfaces and evolution of the interface memory usage during the transmission [J3-1]. . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Evolution over the simulation time of transaction level and message level models [J3-1]. . .

3. 5

 5 Illustration of the studied multiprocessor systems. They are made of an application described following the SDF model of computation and a platform with multiple tiles connected through a communication bus and a shared memory. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 (a) Coding example of the procedure WriteTokens for writing n tokens, (b) state-transition diagram describing the sequence of writing n tokens into the shared memory. The shaded rectangles highlight the states during which the shared resources (communication bus, memories) are accessed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Execution of models describing the writing of n tokens on channel C 1 and the reading of n tokens from channel C 0 in the example of Figure 3.5. (a) At the transfer level, the basic delays and penalties caused by contentions are highlighted. (b) At the message level, the communication times (denoted T W and T R ) are calculated during the simulation. . . . . . . . 3.8 Timed Petri net for writing n tokens on channel C 1 and reading n tokens from channel C 0 . Communication is considered at transaction level with the FCFS arbitration policy. The shaded rectangles correspond to the situation during which the shared resources (bus, memory) are accessed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Illustration of the organization of the message level communication model described in the SystemC language. This model uses the calculation method presented in Chapter 2. . . . . 3.10 (a) Modeling of the studied applications: Sobel filter and JPEG decoder. (b) Experiment platform formed by seven tiles, a shared memory and a communication bus. . . . . . . . . . 4.1 Modelling and evolution of the computation load according to different approaches. ∆t 1 and ∆t 2 denote the interval of time between two successive data to be processed. Situation (b) corresponds to a pipeline execution of the architecture. . . . . . . . . . . . . . . . . . . . . 4.2 (a) Organisation of an LTE data frame in the time and frequency domains, (b-1) organization of the functions of the physical layer in reception, (b-2) possible allocation of functions on two types of computing resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Observations of the occupation of computation and memory resources for an architecture based on a dedicated hardware resource [50], [J4-1]. . . . . . . . . . . . . . . . . . . . . . 4.4 Description of the behaviour of the communication interfaces according to the dynamic function principle [J4-1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Evolution of the usage of resources according to an operating scenario that modifies the applications executed as well as the network available [J4-2]. . . . . . . . . . . . . . . . . . 4.6 Observation of the computation loads induced by the physical layer functions of the E-UTRA and WiFi protocols [J4-2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 (a) Example of an application described according to the SDF model of computation, (b) Computation resources usage for two distinct mappings associated with the application app 1 . 4.8 (a) Position of the online manager in relation to the applications running within the same cluster, (b) Process for selecting the frequency of the cluster operation and defining task allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Different methods of allocating timeslots based on prepared execution traces: (a) prepared execution traces for two active applications, (b) combining traces according to the FCFS method, (c) combining traces according to the LASP method, (d) combining traces according to the proposed GAPVC method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Hierarchical organization for managing multiple applications running on a platform consisting of multiple clusters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Comparison of average power relative to the platform configuration 8 × 8 [J4-3]. For this comparison, no application re-allocation is necessary. . . . . . . . . . . . . . . . . . . . . 4.12 Simulation principle using the traces established during each new operating situation. . . . . 4.13 A high-level model of an application and associated online manager within the Intel CoFluent Studio environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Simulation of dynamic power consumption for different operating frequencies and different possible allocations of the considered application [C4-4]. The simulation is conducted within the Intel CoFluent Studio environment using the proposed principle. . . . . . . . . . . . . . 5.1 Measurement-based characterisation flow for the establishment of probabilistic models for the temporal properties analysis of MPSoC architectures. . . . . . . . . . . . . . . . . . . . 5.2 Process of characterization and probabilistic modelling of computation and communication resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Distribution of the TL simulation models. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Extended modelling flow to allow application of SMC methods. . . . . . . . . . . . . . . . 5.5 Details about the generation and simulation flow of instrumented and monitored SystemC models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Distribution of measured data and estimates obtained by simulation for the experiment Sobel4a [47]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Average values expressed in cyces, obtained by measurement on a real target, simulation of 1 000 000 iterations of a probabilistic model and simulation controlled by the SMC approach. The values given in parentheses indicate the deviation from the mean value measured for the first configuration of the platform [47]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Distribution of measured data and estimates obtained by simulation for the experiment Sobel4b [47]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Average values expressed in cyces, obtained by measurement on a real target, simulation of 1 000 000 iterations of a probabilistic model and simulation controlled by the SMC approach. The values given in parentheses indicate the deviation from the mean value measured for the second configuration of the platform [47]. . . . . . . . . . . . . . . . . . . . . . . . . . . .List of Tables1 Number of hours and distribution of teachings at the University of Nantes for the 2019-2020 academic year. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Tested configurations and associated simulation results [J2-1]. . . . . . . . . . . . . . . . . 2.2 Summary of the case studies using the proposed modelling and simulation approach. These case studies are presented in the indicated chapters. The indicated speed-up factors are obtained without degrading the accuracy of the predictions. . . . . . . . . . . . . . . . . . 3.1 Observed simulation duration (in seconds) for execution of transaction and message level models. The models were executed on a Intel Core2 Dual (2.66 GHz) running under Windows7 [C3-2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Comparison of average execution durations obtained by measurements on a real taget and by simulation of transfer and message level models. The values are expressed in clock cycles. . 3.3 Execution durations on real target and simulation durations (in HH:MM:SS) for 1 000 000 of application iterations according to different possible allocations. . . . . . . . . . . . . . . . 4.1 Comparison of multi-core platform online management strategies for 511 different operating situations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 1 :

 1 Figure 1: Lessons taught in the field of embedded system design. The titles in bold are modules which I assume the responsibility, the titles in italics are modules which I episodically participated.

  . I was a member from 2005 to 2007 of the commission of specialists 61st joint section University of Nantes / Ecole Centrale de Nantes. I participated in recruitment committees for the University of Nantes (in 2007 for position labelled 1169 and in 2010 for position labelled 1040), the University of South Brittany (in 2014 for position labelled 0939), INSA Rennes (in 2009 for position labelled 0169). I initiated two partnership agreements between Polytech Nantes and the following foreign institutions: the University of Engineering and Architecture of Friborg in Switzerland (33 Polytech Nantes students on internship from 2007 to 2014), the University of Queensland in Australia (15 Polytech Nantes students on internship from 2015 to 2018). I was president of one baccalaureate jury in 2008. 2 https://polytech.univ-nantes.fr/les-formations/cycle-ingenieur/ingenieur-electronique-et-technologies-numeriques-2022795.kjsp?RH=1336143536804

Figure 2 :

 2 Figure 2: Position of research activities in the field of hardware/software architectures design of embedded systems.

C. 3

 3 Contracts and research projects • Coordinator for University of Nantes of the RFI WISE-International pSSim4AI project with OFFIS institute, Germany 2020-2023 Object: This project deals with the evaluation and optimisation of performance of neural networks on multicore platforms. Partner: OFFIS (Oldenburg, Germany) • Coordinator for University of Nantes of Hubert Curien Partnership PETA-MC with OFFIS institute, Germany 2019-2020 Object: This project deals with the development and evaluation of probabilistic models and analysis methods for timing and energy prediction of multicore systems. Partner: OFFIS (Oldenburg, Germany) • Coordinator for University of Nantes of the RFI WISE PETA-MC international project 2019-2020 Object: This project deals with the development and evaluation of probabilistic models and analysis methods for timing and energy prediction of multicore systems. Partner: OFFIS (Oldenburg, Germany) • Coordinator of an industrial grant with Intel company 2016-2017 Object: Development of a C-code generation tool from the environment Intel CoFluent Studio and experimentation with the Intel Galileo2 platform Partner: Intel (Nantes) • Invited researcher at University of Queensland, Australia 2012-2013 Object: Research project about the improvement of simulation efficiency for early performance evaluation of multiprocessor systems. Partners : Adam Postula, Neil Bergmann (School of Information Technology and Electrical Engineering, University of Queensland) • Coordinator for University of Nantes of the ANR CIFAER project 2007-2011 Object: Design of innovative communication infrastructures for the automotive domain. Study and evaluation of communication infrastructures performance. Partners: Atmel, See4sys, IRISA, IETR • Coordinator for University of Nantes of a GDR ISIS Young researcher project 2007 Object: Optimisation of scheduling strategies for image and signal applications. Partners: IETR (Image team, INSA Rennes) More generally, I set up strong exchanges with the team of Dr Kim Grüttner of the OFFIS institute (Oldenburg, Germany), specialized in the design of embedded systems. These exchanges have materialized through various projects by stays for myself in Germany in 2016, 2018 and 2019, stays for doctoral students and researchers in France and Germany in 2019 and 2020, internships for engineering students in Germany (four internships carried out from 2016 to 2019). In 2020, we started a thesis co-funded by OFFIS and RFI WISE.

From

  2008 to 2011, I participated in the council of the IREENA laboratory as an elected member. From 2012 to 2015, I participated in the Polytech Nantes research council as an elected member. C.6 Animation of research Proofreading of articles for international journals: Eurasip Journal on embedded systems, Integration the VLSI journal, Eurasip Journal on advances in signal processing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Elsevier Microprocessors and Microsystems. Proofreading of articles for the Gretsi and DASIP conferences. Participation in the program committee of the SDR-WinnComm conference in 2009 and 2010. Participation in the organizing committee of the DASIP conference in 2007. Member of the ISIS and SOC2 research groups. Organizer of the inter-GDR ISIS SOC2 day 'Modeling and design of mobile radiocommunication systems' in 2010. Invited talk at CEA in 2015, GDR SoC in 2007, GDR ISIS in 2006, in National Microwave days (JNM) in 2005. Participation in the science day organized at the University of Nantes in 2019.Chapter 1

Figure 1 . 1 :

 11 Figure 1.1:The Y diagram with detailed at the system level, inspired from[16]. The main activities led at the system level are identified.

Figure 1 . 2 :

 12 Figure 1.2: Illustration of the compromise between accuracy and analysis time for different performance evaluation methods, (a) simulation-based approaches, (b) formal approaches.

F BFigure 1 . 3 :

 13 Figure 1.3: Different levels of complexity in shared resources of multiprocessor systems.

1. 2 Figure 1 . 4 :

 214 Figure 1.4: Position of the covered research topics, main projects and co-supervised PhD thesis.

Figure 2 . 1 :

 21 Figure 2.1: (a) Example of a system-level model with three architecture viewpoints: functional, executive and physical, physique, (b) description of functions behaviours with elementary communication and computation statements. The execution semantic related to each statement needs to be defined such as illustrated in Figure 2.7.

F2Figure 2 . 2 :

 22 Figure 2.2: Discrete event simulation of the architecture model in the figure 2.1. In this example, the instants associated with the communication of M 2 via the interfaces IF1 and IF2 and the communication bus N are detailed. The instants associated with the communications of the other relations are not detailed for the sake of readability. The shaded part corresponds to a situation of contention on the interface IF1.

Figure 2 .

 2 3 illustrates this simulation principle by comparing it with the approach previously illustrated. Part (a) of the figure 2.3 illustrates the different simulation instants and the different calls to the simulation engine occurring during an execution of the model illustrated in the figure 2.2. The instants u(k) and y(k) correspond respectively to the instants when the data carried by the relations M 1 and M 6 are available at the input and at the output of the model. Each instant x i (k) corresponds to a simulation instant of the model. As an example, the instants denoted x NM 4 S (k) and x NM 4 E (k) correspond to the instants of start and end of the use of communication bus N during transfer of data associated with relation M 4 . Part (b) of the figure illustrates

Figure 2 . 3 :

 23 Figure 2.3: (a) Execution of a model with classical simulation approach, (b) execution of a model with instantaneous computation of future simulation instants.

Figure 2 .

 2 4 extends the example of figure 2.3 and illustrates this phenomenon.

Figure 2 . 4 :

 24 Figure 2.4: (a) Situation with erroneous prediction of instants when a shared resource is used, (b) principle of the correction method of resource usage instants.

Figure 2 . 5 :

 25 Figure 2.5: (a) Notation of timed Petri nets used to describe the dependencies between simulation instants, (b) expression of the transition instants in the illustrated network.

Figure 2 . 6 :

 26 Figure 2.6: Examples of elementary patterns used to describe the dependencies between start and end instants of computation and communication statements.

Figure 2 . 7 :

 27 Figure 2.7: Examples of patterns related to communication statements: (a) rendez-vous protocole, (b) infinite capacity FIFO protocol. T W r and T Rd denote the write and read durations.

Figure 2 . 8 :

 28 Figure 2.8: Examples of built Petri net models to describe the dependencies between start and end instants of communication and computation statements.

Figure 2 . 9 :

 29 Figure 2.9: (a) Structural and behavioral description of the proposed generic execution model, (b) management procedure of the computed instants.

( a )Figure 2 . 10 :

 a210 Figure 2.10: Influence of the complexity of the calculation method on the achieved simulation speed-up.

Figure 3 . 1 :

 31 Figure 3.1: Illustration of levels of abstraction in communication description for the two case studies.

Figure 3 . 2 :

 32 Figure 3.2: Illustration of the distributed architecture studied in the scope of the CIFAER project [J3-1].

Figure 3 . 3 :

 33 Figure 3.3: Illustration of exchanged between two HomePlugAV interfaces and evolution of the interface memory usage during the transmission [J3-1].

Figure 3 .

 3 Figure 3.4 illustrates the application of the simulation method in the case of the scenario previously illustrated in Figure 3.3. Part (A) of Figure 3.3 illustrates successively the formed IP packets. Part (B) presents the

Figure 3 . 4 :

 34 Figure 3.4: Evolution over the simulation time of transaction level and message level models [J3-1].

4 Figure 3 . 5 :

 435 Figure 3.5: Illustration of the studied multiprocessor systems. They are made of an application described following the SDF model of computation and a platform with multiple tiles connected through a communication bus and a shared memory.

Figure 3 . 6 :

 36 Figure 3.6: (a) Coding example of the procedure WriteTokens for writing n tokens, (b) state-transition diagram describing the sequence of writing n tokens into the shared memory. The shaded rectangles highlight the states during which the shared resources (communication bus, memories) are accessed.

Figure 3 . 7 .

 37 The calculations of the durations of the WriteTokens and ReadTokens functions are performed at instants x w ComS (k) and x r ComS (k ) and are denoted ComputeCommTime. It is

Figure 3 . 7 :

 37 Figure 3.7: Execution of models describing the writing of n tokens on channel C 1 and the reading of n tokens from channel C 0 in the example of Figure 3.5. (a) At the transfer level, the basic delays and penalties caused by contentions are highlighted. (b) At the message level, the communication times (denoted T W and T R ) are calculated during the simulation.

Figure 3 . 8 Figure 3 . 8 :

 3838 Figure 3.8: Timed Petri net for writing n tokens on channel C 1 and reading n tokens from channel C 0 . Communication is considered at transaction level with the FCFS arbitration policy. The shaded rectangles correspond to the situation during which the shared resources (bus, memory) are accessed.

Figure 3 . 9 :

 39 Figure 3.9: Illustration of the organization of the message level communication model described in the SystemC language. This model uses the calculation method presented in Chapter 2.

[

  J3-1] T. Majdoub, S. Le Nours, O. Pasquier, and F. Nouvel, "Performance evaluation of an automotive distributed architecture based on a high speed power line communication protocol using a transaction level modeling Chapter 4

Figure 4 . 1 :

 41 Figure 4.1: Modelling and evolution of the computation load according to different approaches. ∆t 1 and ∆t 2 denote the interval of time between two successive data to be processed. Situation (b) corresponds to a pipeline execution of the architecture.

  Structural organization of functions and resources of a LTE receiver

Figure 4 . 2 :

 42 Figure 4.2: (a) Organisation of an LTE data frame in the time and frequency domains, (b-1) organization of the functions of the physical layer in reception, (b-2) possible allocation of functions on two types of computing resources.

Figure 4 . 4 :

 44 Figure 4.4: Description of the behaviour of the communication interfaces according to the dynamic function principle [J4-1].

Figure 4 . 5 :

 45 Figure 4.5: Evolution of the usage of resources according to an operating scenario that modifies the applications executed as well as the network available [J4-2].

  Evolution over time of the computation load (in MOPS) for the E-UTRA and WiFi interfaces (channel decoding function). Usage of computation resources for the WiFi reception process.

Figure 4 . 6 :

 46 Figure 4.6: Observation of the computation loads induced by the physical layer functions of the E-UTRA and WiFi protocols [J4-2].

Figure 4 . 7 :

 47 Figure 4.7: (a) Example of an application described according to the SDF model of computation, (b) Computation resources usage for two distinct mappings associated with the application app 1 .

  Online management of resources.Design-time prepared dataFor each application-Traces d'exécution pour différents mapping possibles -Fréquence minimale possible associée à chaque mapping Combined execution traces & tuned common frequency Ongoing situation Run-time selection Run-time mapping combination Selected common frequency, selected prepared mapping (b) Proposed management strategies.

Figure 4 . 8 :

 48 Figure 4.8: (a) Position of the online manager in relation to the applications running within the same cluster, (b) Process for selecting the frequency of the cluster operation and defining task allocations.

Figure 4 . 9 :

 49 Figure 4.9: Different methods of allocating timeslots based on prepared execution traces: (a) prepared execution traces for two active applications, (b) combining traces according to the FCFS method, (c) combining traces according to the LASP method, (d) combining traces according to the proposed GAPVC method.

Figure 4 . 10 :

 410 Figure 4.10: Hierarchical organization for managing multiple applications running on a platform consisting of multiple clusters.

Figure 4 . 11 :

 411 Figure 4.11: Comparison of average power relative to the platform configuration 8 × 8 [J4-3]. For this comparison, no application re-allocation is necessary.

  For each application App: execution traces XAppi are prepared Online management (Compute()) Comination trategy of execution traces (e.g., GAPVC, LASP…) Control of the state of functions Control of situations

Figure 4 .

 4 Figure 4.13: A high-level model of an application and associated online manager within the Intel CoFluent Studio environment.

Figure 4 . 14 :

 414 Figure 4.14: Simulation of dynamic power consumption for different operating frequencies and different possible allocations of the considered application [C4-4]. The simulation is conducted within the Intel CoFluent Studio environment using the proposed principle.

Figure 5 . 1 :

 51 Figure 5.1: Measurement-based characterisation flow for the establishment of probabilistic models for the temporal properties analysis of MPSoC architectures.

Figure 5 . 2 :

 52 Figure 5.2: Process of characterization and probabilistic modelling of computation and communication resources.

Figure 5 .

 5 Figure 5.2 illustrates three approaches successively considered in our work in order to model communication mechanisms:

Figure 5 . 3 :

 53 Figure 5.3: Distribution of the measured data (blue) compared to the results otained for models differing according to the modelling of the computation times. Computation times are described by injected data (orange) or a Gaussian distribution (blue). (a), (b) and (c) show the results for the Sobel filter application. (d), (e) and (f) show the results for the JPEG decoder application. Dotted horizontal lines indicate average execution times [47].

Figure 5 . 4 :

 54 Figure 5.4: Extended modelling flow to allow application of SMC methods.

Figure 5 . 8 :Figure 5 . 9 :

 5859 Figure 5.8: Distribution of measured data and estimates obtained by simulation for the experiment Sobel4b [47].

  PhD thesis• Hai-Dang VU, Fast and accurate performance models for probabilistic timing analysis of SDFGs on MPSoCs, University of Nantes, March 2021.Master thesis• Jiatong Li, Extraction of stochastic models for computation and communication time on a multicore Zynq platform, University of Nantes, June 2017.

1

 1 Review of the work carried out

3

  Communication modelling of multiprocessor architectures 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Improvement of simulation efficiency for distributed architecture analysis . . . . . . . . . . 3.2.1 Characteristics of the studied systems . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Application of the simulation method . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Obtained results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Improvement of simulation efficiency for multiprocessor systems-on-chip analysis . . . . . 3.3.1 Characteristics of the studied systems . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Application of the simulation method . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Obtained results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 1 :

 1 Number of hours and distribution of teachings at the University of Nantes for the 2019-2020 academic year.

	Semester Level	Title	Lecture Tutorial Practical Project
			Circuit design 1	3,75	17,5	42
	s.7	ETN4	Microprocessor systems 1	2,5	17,5	21
			3rd year internship supervision				1
	s.8	ETN4	Real-time system design Transversal project		13,5		15
			SoC design 1	4,5	15	9
	s.9	ETN5	HW-SW codesign 1 Embedded system architectures Technical projects	9		18 9	25
			4th year internship supervision				11
	s.9	Master2	Circui design methodology 1 Performance evaluation 1		12 7,5	12
	s.10	ETN5	Final year internship supervision				26,5

Functional architecture Physical architecture Executive architecture

				Programmable software
				resources
				RTOS API	Dedicated hardware
				Real time kernel	resources
				Hardware abstraction	Communication IF
				Proc. Mem.	I/O	Bus controller
						Bridge
		F1	F21	F22
						Selection	CPU	HW IP
				Complexity estimation		of ressources Partitioning and allocation	HW/SW interfaces	F1	F21	F22
	A1	A2		Application modelling		niveau Système	Scheduling	RTOS API Real time kernel Hardware abstraction	Communication IF
					niveau Architectural	Proc. Mem.	I/O	Bus controller
				Specifications		niveau Logique	Processors, memories	Bridge
				Register transfer				ALU, MUX,
				Logic equations	niveau Transistor	Gates,	registers	IP libraries
				Physical equations	Transistors flip-flop	Proc., bus
						Rectangles, polygones	RTL
							Basic
							cells
							Modules,	Gates
							macro-cells
								Transistors

  [R1-1] R. Stemmer, H.-D. Vu, M. Fakih, K. Grüttner, S. Le Nours, and S. Pillement, "Feasibility Study of Probabilistic Timing Analysis Methods for SDF Applications on Multi-Core Processors," IETR ; OFFIS, Research Report, Mar. 2019. [Online]. Available: https://hal.archives-ouvertes.fr/hal-02071362.

Table 2 .

 2

2: Summary of the case studies using the proposed modelling and simulation approach. These case studies are presented in the indicated chapters. The indicated speed-up factors are obtained without degrading the accuracy of the predictions.

Table 3 .

 3 Number of transmitted images Transaction level Message level Speed-up factor 1: Observed simulation duration (in seconds) for execution of transaction and message level models. The models were executed on a Intel Core2 Dual (2.66 GHz) running under Windows7 [C3-2].

	150	249.4 s	1.38 s	187.8
	1500	2498.6 s	12 s	208
	4500	7459.3 s	35.9 s	208

  .6.

	void WriteTokens(channel_t *channel, token_t inputtokens[]) { // poll for empty buffer			inter-polling stage					inter-writing stage
	while(*(channel->full));		End of					End of
	// write token into channel buffer for(int i=0;i<channel->prate;i++) {	inter-polling		buffer not available	inter-writing		index += 1 index != n
	Channel->tokens[i]=inputtokens[i];
	} //flag buffer as full *(channel->full)=1;	init.	End of init.	polling (1)	buffer available	pre-writing	End of pre-writing	writing (2)	index==n	post-writing post-writing End of	update buffer usage (3)	End of update
	}

  .9 represents the message-level model organization of a channel communication between

		Message-level model
	Tile0						Tile1
		WriteTokens()			ReadTokens()
	while(1) {	Place available ?	Data available ?	while(1) {
	wait(GP_delay);						pC0->ReadTokens(C0);
	pC0->WriteTokens(C0);	yes		no	yes		no	wait(GX_delay);
	...	SC_PORT					SC_PORT	...
	}	pC0	waiting		waiting	pC0	}
					XS
				rd_C0		wr_C0
		/ComputeCommTime(x w (k)); ComS	/ComputeCommTime(x r (k)); ComS
		s w			wr_C0	s r
		ts=x w	comE(k)		ts=x r	comE(k)
		/notify(wr_C0);	rd_C0	/notify(rd_C0);

Table 3 .

 3 3: Execution durations on real target and simulation durations (in HH:MM:SS) for 1 000 000 of application iterations according to different possible allocations.

Table 4 .

 4 1: Comparison of multi-core platform online management strategies for 511 different operating situations.

			Nb of not satisfactory situations	Comparison with the proposed approach
	Number of cores	Strategie	Total	Due to not enough resources	Due to timing straints con-	Nb of situations with higher average power	Increase in average power
		FCFS	102	102	0	16	12.1% to 34.6%
	6	LASP	90	67	23	31	142.8% to 206.3%
		GAPVC	76	76	0	-	-
		FCFS	9	9	0	32	12.8% to 35.6%
	8	LASP	34	2	32	40	206.3%
		GAPVC	3	3	0	-	-
		FCFS	0	0	0	5	13.6% to 36.0%
	10	LASP	32	0	32	40	206.3%
		GAPVC	0	0	0	-	-

  • Anthony Barreteau, Transaction-level modelling methods for resource definition of future mobile radiocommunication systems, University of Nantes, December 2010.

	Master thesis
	• Anthony Barreteau, Automated generation of test environment from high level models, University of
	Nantes, June 2007.
	• Romain Guignard, Study and modelling of a SoC architecture in CoFluent Studio, University of Nantes,
	June 2006.

  .4.

		End-to-end latency
	GP	C1	GX	C3
	C0	GY	C2	ABS
	P.E. + private memory	P.E. + private memory
	IF Com.	IF Com.
	Bus arbiter	Communication bus
		IF Com.
		Shared memory

  Average values expressed in cyces, obtained by measurement on a real target, simulation of 1 000 000 iterations of a probabilistic model and simulation controlled by the SMC approach. The values given in parentheses indicate the deviation from the mean value measured for the first configuration of the platform[START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF].

		0.6	Measured SMC simulation	Exp.	Measure 1M simulation runs	SMC simulation
		0.5		Sobel1a	3690	3797.5 (2.91 %)	3799.2 (2.96 %)
	Probability	0.3 0.4 0.2		Sobel2a Sobel4a Jpeg1a 2385860 2382722.5 (-0.13 %) 2376010.1 (-0.42 %) 2902.5 2977.5 (2.58 %) 2977.8 (2.58 %) 3097.4 3194.5 (3.13 %) 3189.0 (2.96 %) Jpeg3a 940836 912219.5 (-3.05 %) 911764.7 (-3.1 %) Jpeg7a 941059 896367.7 (-4.75 %) 886538.5 (-5.8 %)
		0.1
		0.0	Iteration delay (cycles) 3050 3075 3100 3125 3150 3175 3200 3225 3250	Figure 5.7:
	Figure 5.6: Distribution of measured data and
	estimates obtained by simulation for the exper-
	iment Sobel4a [47].

Scientific referent of the 'Embedded and secure communicating systems' axis within the new ASIC team of the IETR, from January 2022. Member of the working group 'Scientific Animation' of the IETR laboratory.

In this simplified representation of the Y diagram, only four levels of abstraction are identified. In more detailed versions, five levels are exhibited, highlighting the functional analysis of the systems to be designed.

The terms used to designate these views frequently differ. At this stage, we use the terms used in[17].

The simulation instants noted with an upper index w are associated with the writing process, those noted with an upper index r are associated with the process of reading. Each instant noted x w j (k) (respectively, x r j (k)) corresponds to the k-th instant of transition between two elementary phases of the token writing process (respectively, of reading tokens).

A transaction level model was also considered in order to replace the polling phase by waiting for an event notifying the change of state of the buffer. The different writings and successive readings were always exhibited.

This process and the resulting result will be referred to by the term mapping.

The results mentioned here are detailed in[START_REF] Vu | Fast and accurate performance models for probabilistic timing analysis of sdfgs on mpsocs[END_REF]. They use the simulation infrastructure offered by the intensive computing center of Pays de la Loire[START_REF]Centre de calcul intensif des pays de la loire[END_REF].

In France, CIFRE convention is an industrial agreement for training through research between a company, a laboratory and a thesis student.

On January 1, 2022, the Transport department of the OFFIS institute with which we collaborate was integrated into the DLR, the German center for aeronautics and astronautics. Collaborations will therefore continue with this centre.

Summary of research and teaching activities

A resource block designates the smallest unit used to send data to a mobile terminal, corresponding to the association of twelve consecutive sub-carriers. Thus, in order to be able to adapt the quantity of data required for each receiver, the number of allocated resource blocks, the number of occupied sub-carriers as well as the type of modulation used can change from one subframe to another. For this case study, only a configuration with a single antenna for transmission and reception was considered. Part (b) of Figure 4.2 represents the organization of the main functions of the physical layer executed upon receipt of an LTE subframe in order to form a block of data used by the upper layer of communication. The main time constraint imposed was to process fourteen OFDM symbols in 1 ms. The role and behaviour of each function is detailed in [START_REF] Barreteau | Techniques de modélisation transactionnelle pour le dimensionnement des futurs systèmes de radiocommunications mobiles[END_REF]. Also, different expressions were established in order to formulate the computation load induced by each elementary function taking into account the different possible configurations of the received sub-frames.

Such a receiver was approached according to the two levels of abstraction illustrated in part (b-1) of Figure 4.2:

• a first level displays the six functions operating on each OFDM symbol received,

• a second level corresponds to the only reception function operating on each OFDM symbol received, the global calculation load induced by all the elementary functions being calculated locally. This calculation is carried out according to the dependencies between functions and according to the allocation considered on the platform studied.

The contribution of the proposed approach therefore consisted in the possibility of analyzing the workload induced for different architectures, while keeping a limited number of functions and communications within the model created. These different models were entered into the Intel CoFluent Studio environment in order to verify the validity of the models and the gain in terms of simulation speed. The models created made it possible to estimate the computing and memory capacities required for two possible architectures: a first architecture using dedicated hardware resources for the execution of all the functions and a second architecture associating programmable processor and dedicated accelerator for the single channel decoding function. The figure 4.3 illustrates the observations obtained for the evolution of the computation load induced by the functions of the physical layer as well as the memory required for the first architecture.

Computation load (MOPS)

Sub-frame n°1

Sub-frame n°2

Sub-frame n°3

(a) Usage of computation resources.

Sub-frame n°2

Sub-frame n°1

Sub-frame n°3

Memory size (bits) (b) Usage of memory resources. The presented observations relate to the reception of three distinct sub-frames with varying number of resource blocks and type of demodulation used. Such observations make it possible to estimate the occupation of the calculation resources as data frames are received. These observations were obtained with the same level of precision for the models created according to the two levels of abstraction previously mentioned. The gain obtained in terms of simulation speed was of the order of 4 between the two models created within the Intel CoFluent Studio environment. Subsequently, we used the approach presented in Chapter 2 to describe the load model associated with the different functions of the LTE receiver. The graph then used in simulation comprised 84 nodes corresponding to the different synchronization instants calculated locally at the reception of each OFDM symbol. This case study was therefore initiated as part of Mr. Barreteau's thesis and was then continued in order to illustrate the validity of the extended approach. process previously described in this chapter. The creation of a monitor is operated from the definition of

List of publications

International journals with program committee