E Beigne

A Valentian

B Giraud

O Thomas

T Benoist

Y Thon- Nard

S Bernard

G Moritz

O Billoint

Y Maneglia

P Flatresse

J P Noel

F Abouzeid

B Pelloux-Prayer

A Grover

S Clerc

P Roche

J Le Coz

S Engels

R Wilson

" Ultra-Wide

Voltage Range

C Bernard

J Le Xxiii

CONTEXT, BACKGROUND AND MOTIVATION 1 2 CONTEXT, BACKGROUND AND MOTIVATION

A: Additional studies on pulse-triggered flip-flop architectures W g Gate width [µm

Introduction xix

I.1 The FDSOI technology xx I.2 Purpose of this thesis xxi I. [START_REF] Moore | Cramming more components onto integrated circuits[END_REF]

Thesis outline xxii

Author's publication list xxv Trois ans... En Belgique, tout le monde me disait "C'est beaucoup trop court, on commence seulement à être productif ! Mais au moins tu auras plus rapidement fini avec la thèse et tout ce qui va avec..." Et pourtant... Et pourtant j'ai vécu tant d'expériences pendant ces trois années, appris un nombre incalculable d'informations, vu, entendu et participé à tant d'évènements, que je n'ai pas l'impression que ces trois années soient passées si vite. J'achève maintenant une longue période de rédaction et de préparation de présentation et me jette dans la vie active, avec le sentiment que ces trois ans ne furent ni trop longs, ni trop courts, juste une expérience professionnelle, mais surtout humaine, riche et inoubliable. Tout d'abord, je souhaiterais remercier mes encadrants, le Professeur David Bol et le Docteur Alexandre Valentian, qui ont toujours été disponibles lorsque j'avais des doutes ou des interrogations, ou lors de la relecture d'articles scientifiques. Même si la distance n'aidait pas toujours, ils ont toujours fait le maximum pour m'apporter une aide optimale. Plus particulièrement, je remercie David Bol pour m'avoir donné le goût et l'envie de la microélectronique à très haute efficacité énergétique, de par ses présentations passionnées et ses cours scientifiquement et esthétiquement remarquables, et Alexandre Valentian pour m'avoir accueilli et veillé à ce que je me sente chez moi au LISAN tout au long de ces trois années. Ensuite, j'aimerais remercier mes promoteurs, Marc Belleville et le Professeur Jean-Didier Legat, qui m'ont permis d'entamer cette thèse à Grenoble grâce à leur contact réciproque et leur appui de ma candidature au siège du CEA. Enfin, je remercie les autres membres de mon jury, les Professeurs Wim Dehaene, Andrei Vladimirescu et Lionel Torres pour les discutions riches et intéressantes qui ont suivi mes soutenances.

J'aimerais ensuite remercier mes collègues de bureau pour tout ce temps passé ensemble et pour avoir contribué à la bonne ambiance qui animait chacune de mes journées de travail : A Grenoble, Ogun Turkyilmaz, pour son apprentissage conventionnel du français non-conventionnel, Thiago Raupp Da Rosa, et son histoire après le match Allemagne-Brésil (mythique!), Santhosh Onkaraiah, pour son éternelle bonne humeur et son aide lors de l'organisation du voyage à Berlin, Olivier Billoint, pour avoir partagé tant d'abattements face aux nouveaux DK de ST, Sébastien Thuries, pour ses réponses patientes à mes questions sur les outils, Romain Lemaire pour son effarement quand il a appris ce qu'était le Mudday, Karim Azizi-Mourier, Youcef Fellah et Christian Servière du support informatiques, qui connaissaient tous mon prénom après seulement deux semaines, -et un remerciement tout particulier à Christian pour ces soirées ix x astronomiques en Chartreuse et cette magnifique Saturne!-l'équipe mémoire, et ses réunions presque biquotidiennes, composée entre autres de Adam Makosiej, et ses réponses patientes à mes nombreuses questions pas toujours intelligentes, et de Bastien Giraud, alias le marseillais-avec-ponctuation, et enfin mon équipe du Mudday, Alin Riatu, Matthieu Verdy et Robert Polster, pour cette expérience intense et inoubliable (la boue, la boue, la boue !). De l'autre côté à Louvain-la-Neuve, Guerric de Streel, surnommé l'amibe (n'en profite pas pour coloniser mon bureau !), avec qui je partageai conférence, cookies, recherche d'information dans un nuage de milliard de points, ainsi que joie et peine des simus, Vital Angelo Kuti Lusala, dont la patience face aux étudiants nous a tous impressionnés, Julien De Vos, qui découvrit Grenoble quand je retournais en Belgique, Geoffroy Gosset, pour ces match de tennis dignes des tournois du grand chelem, et enfin François Stas, pour son protocole de communication avec Guerric per muros.

Un immense merci à tous mes amis de l'association AITAP et mon coloc Benjamin Vianne, qui m'ont permis de rapidement m'intégrer et de participer à des activités sensationnelles ! Et pour terminer, je tiens tout specialement à remercier mes collègues grenoblois Bastien, pour l'argent de ses impôts qui a permis, à moi de partir en voyage aux quatre coins du monde et, à AITAP, de financer ses activités, et Robert, pour ce tandem franais-allemand qui restera dans les annales et qui nous a, j'en suis sr, tous les deux enrichis, pas seulement linguistiquement... Je remercie le Centre à l' Énergie Atomique et aux Énergies Alternatives pour avoir financé mes recherches et mes séjours réguliers en Belgique.

Et finalement, je voudrais remercier tous les membres de ma famille qui m'ont soutenu pendant ces trois années de thèse, et tout spécialement mes parents qui ont parfois (souvent ?) stressé plus encore que moi, surtout lors de conférences tropicales durant lesquelles ils ont parfois eu du mal à dormir !

Sébastien

ABSTRACT

The portable applications, such as smartphones, tablets, and mobiles, and the ultra-low power (ULP) circuits, such as RFID tags, wireless sensors network, and biomedical functions, are the applications driving the microelectronics industry today. In these applications, the microprocessor is connected to a battery or an energy harvesting system, meaning, in both cases, a finite amount of available energy and power. Therefore, the power and energy consumptions are of fundamental importance in the design of these circuits.

The FDSOI technology appeared recently in industrial processes to overcome the bulk technology limits and continue the trend of Moore's law. Thanks to the better electrostatic control of the channel, this technology provides a lower junction capacitance and leakage, steeper subthreshold slope, lower variability, and powerful back biasing technique over a wide voltage range. The back bias allows to dynamically modify the threshold voltage of the transistors in a reversible way. Therefore, this technology is extremely suitable for highly energy-efficient and ULP circuits.

In modern synchronous designs, the number of flip-flops (FF) has literally exploded with the raise of new microarchitectural techniques. Consequently, the flip-flop architecture has a decisive impact on the timing and energy consumption of the processor. The explicit pulse-triggered flip-flop (explicit pulsed-FF) topology presents remarkable timing properties which allow to gain a non-negligible part of the clock cycle. At the same time, its energy consumption can be severely reduced by sharing its pulse generator. So far, this structure is almost completely absent from circuits working at ultra-low voltage (ULV), where the master-slave architecture is mainly and widely used. The main reasons are its two following drawbacks:

• Low robustness against local variations in the pulse generation

• Positive hold time leading to additional delay buffers and thereby energy overhead

In order to improve the performances of UWVR and ULP circuits, both in a energy-efficiency and timing point of view, this dissertation studies and analyses architectural innovations to overcome these two disadvantages.

xi xii

ABSTRACT

The study is driven by the two following questions:

• How to provide robust and energy-efficient pulse-triggered flip-flops at ultra-low voltage ?

• How can the FDSOI technology help us to improve the robustness and energy-efficiency ?

First, we present the explicit pulse-triggered flip-flop which is composed of a pulse generator (PG) sending pulse-like signals to a latch. We select the most promising latch architectures in an energy-efficiency point of view. Then, we compare these architectures in the energy-delay (E -D) domain by a sizing methodology at nominal and ultra-low voltages. The TGPL-Clk and C 2 MOS-Data architectures are pointed out, respectively, for high-speed and low power applications. Afterwards, we show how the wide back biasing allowed in FD-SOI technology outperforms the sizing methodology in a delay and energy point of view. These comparisons are then confirmed by silicon measurement of the selected pulsed-FF architectures.

Second, we explain the robustness handicap of pulse-triggered flip-flop at ULV and the fundamental tradeoff between robustness and energy consumption. As a result, we propose a current-starved delay generator (DG) which provides sufficient degrees of freedom to reach the robustness target without impacting the energy consumption. Then, post-layout simulations and silicon measurements show the significant robustness improvement due to our proposed DG. The silicon measurements also show that choosing the proper back bias couple allows to reach the highest possible robustness. Afterwards, it is shown that additional flip-flop functionalities can be implemented in the PG with a very small timing, area, and energy penalties compared to master-slave architecture.

Finally, a conditional capture technique is presented to suppress the useless energy consumption remaining when there is no data activity. It is shown that, combined with the energy-efficient latch and PG previously analysed, this technique provides a lower energy consumption than master-slave architecture. After confirming the advantage of pulse generator sharing, the combination of previous innovations is integrated in a realistic register file. The comparison with masterslave based register files shows that our pulse-triggered flip-flops exhibit higher speed, lower area, and lower energy consumption over a wide range of supply voltage.

ACRONYMS

INTRODUCTION

Over the last two decades, the portable applications have become the keystone of the microelectronics industry. Millions of smartphones, tablets, and mobiles are sold every day and the projections do not see a decrease for a while. However, the energy bugdet is the bottleneck of these applications. Today, the smartphones need to be recharged every day and the battery has become a major concern for industrial people and customers. The most efficient solution found by designers is to reduce the supply voltage of the CMOS circuits. This greatly decreases each component of the energy dissipation, with the inconvenience of decreasing the maximum speed of the circuit. The current targeted tradeoff is to work at nominal voltage when high-performances are needed, for example when a webpage is downloaded, and at ultra-low voltage when performance is not on concern. Consequently, the supply voltage of these circuits covers a wide range of value during the life-time of the circuit. It is why there are called ultra-wide voltage range (UWVR) circuits [1].

At the same time, emerging applications such as biomedical devices, wireless sensors networks, radio-frequency identification (RFID) tags, and the advent of the Internet of Things (IoT) paradigm have led designers to develop ultra-lowpower (ULP) design of integrated circuits [START_REF] Bol | Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era[END_REF]. Most of these circuits will work with systems harvesting only the available energies in the environment. Thus, the energy budget will determine the accomplishment of these circuits. In the IoT, wireless sensors will be placed outdoor and indoor and biomedical measurement tool will be on-and then in-body. Thereby, only a small amount of energy and power will be available in the environment. Therefore, there is a huge demand for reducing the energy consumption of the circuits dedicated to portable and ULP applications.

To continue the trend of Moore's law [START_REF] Moore | Cramming more components onto integrated circuits[END_REF], new technologies have emerged to replace the conventional bulk technology. Two of them are today implemented in industrial process flow: the FinFET technology and the fully-depleted silicon on insulator (FDSOI) technology. The aim of these two transistor technologies is a better electrostatic control of the channel. The FinFET transistor has a 3D shape which allows to encircle the channel, and the FDSOI transistor presents a buried oxide (BOX) below the channel which acts like a second gate and brings many others advantages. In this work, the transistor architectures are designed xvii INTRODUCTION and fabricated in 28nm FDSOI technology, with full benefit of its interesting properties.

The appropriate choice of flip-flop architecture is of fundamental importance in the design of VLSI integrated circuits. In modern synchronous CMOS circuits, the clock tree and its leaves represent between 30% and 70% of the total energy consumption of the microprocessor [START_REF] Paik | Implementation of pulsed-latch and pulsedregister circuits to minimize clocking power[END_REF][START_REF] Magen | Interconnect power dissipation in Microprocessor[END_REF]. The main reason is that the number of flip-flops has literally exploded the last two decades. Pipelining, super-scalar and time-borrowing techniques need always more flip-flops to reach the timing limits of the circuit. Therefore, the flip-flop timing and energy characteristics have a considerable impact on the performances of the whole circuit. As a result, this dissertation starts with an overview of the flip-flop topologies with the aim of selecting the most promising FF structure for improving the energy-efficiency of UWVR and ULP circuits. It turns out that explicit pulse-triggered flip-flops own remarkable properties for the targeted applications, but present several disadvantages to function at ultra-low voltage. The pulse-triggered flip-flop (pulsed-FF) is a well-known topology which is, to the best of our knowledge, only used in high-performances circuits. It is composed of one latch, which is open during a short period determined by a pulse-like signal. This signal is generated by a pulse generator active at the triggering clock edge.

Unfortunately, this flip-flop topology suffers from two big drawbacks compared to master-slave architecture, which are magnified at ultra-low voltage: it presents a lower robustness to local variations ; it exhibits a positive hold time, inducing energy overhead paid for additional delay buffer insertion at Place&Route step. This is the focus of this dissertation: integrating the fast pulse-triggered flipflop topology in energy-efficient circuits working at ultra-low voltage operations, with the help of the FDSOI technology.

I.1 THE FDSOI TECHNOLOGY

The fundamental configuration of the FDSOI transistor is a conventional bulk transistor where a thin oxide layer, or buried oxide (BOX), is inserted between the substrate and the active part such as the channel height is a few nanometre (8nm of silicon for 28nm technology for a BOX of 25nm height). Beneath the BOX, the region is called the back plane and is not necessarily tied to the supplies. This topology presents many advantages. First, the junction capacitance between the source-drain contact and the bulk is reduced, as well as the junction leakage current. Then, the better electrostatic control provides a dramatic reduction of many short channel effects and an enhanced subthreshold slope. Furthermore, FDSOI technology exhibits a much lower variability than bulk technology mainly thanks to the undoped transistor channel. Moreover, it is possible to produce up to three different threshold voltages without doping the channel and adding variability. And as a last advantage, the most important property of the FDSOI technology according to the author, the back biasing technique. The voltage below the buried oxide, called back bias, can vary over a PURPOSE OF THIS THESIS xix wide range of voltage. The variation is equivalent to a strong forward (FBB) or reverse body bias (RBB) in bulk.

I.2 PURPOSE OF THIS THESIS

This dissertation studies and develops pulse-triggered flip-flops with the aim of pushing them in ultra-low voltage operations. In addition to the robustness challenge, ULV operations are focusing on the energy-efficiency of the circuits. In order to explain the targets followed all over this work, let us remind that the energy-delay product (EDP) is the main figure of merit for UWVR circuits, while the energy per operation (E op ) is of primary importance in ULP applications.

Architectural innovations are presented and designed in this thesis to answer the following questions:

• What is the most energy-efficient latch architecture to be inserted in an industrial standard-cell library covering a wide range of supply voltage ?

A lot of studies [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF][START_REF] Tschanz | Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors[END_REF][START_REF] Stojanovic | Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems[END_REF][START_REF] Rebaud | A comparative study of variability impact on static flip-flop timing characteristics[END_REF] compare flip-flop architectures at the same, and often nominal, supply voltage, trying to reach a given figure of merit (delay, energy, or energy-delay product). Moreover, the compared flip-flops hardly present more than three functional pins (input, output, and clock) which is not realistic for applications in advanced technologies. In this work, we elaborated a set a promising scannable and resettable flip-flop topologies and then compared them in the energy-delay (E -D) domain at nominal and ultra-low supply voltage. Afterwards, we studied the back biasing technique applied to the selected architectures and highlighted the benefit in timing and energy performances provided by a wide back bias range.

• How to guarantee the robustness of pulse-triggered flip-flop facing local variations at ultra-low voltage, without overdesign and energy overhead ?

As the width of the pulse window is determined by a delay generator composed of a chain of CMOS stages, the generated delay is highly impacted by local variations at ultra-low voltage. If the pulse width is too narrow, the latch of the pulsed-FF does not have enough time to change its state. The common ways for ensuring the minimum pulse width is wide enough under worst-case conditions, lead to an overdesign and/or an significant energy overhead. In this work, we proposed a current-starved delay generator as architectural innovation to overcome the tradeoff between robustness and energy and studied how to choose the back bias values to maximise the yield under timing constraints.

INTRODUCTION

a pseudo-XOR gate inside to make the hold time negative and limit the energy consumption when no data activity. Then, we assembled several innovations presented in the dissertation to lay out a robust and energy-efficient register file and to show the obtained gains in speed, energy, and area.

I.3 THESIS OUTLINE

In order to answer the previously exposed questions, this thesis is organised as follows:

Chapter 1. After a short reminder about the power and energy consumption of digital CMOS circuits, the FDSOI technology and all its advantages are presented in more details. Next, we assess the state of the art of the four CMOS flip-flop topologies. The master-slave, differential, pulse-triggered and dual-edge configurations are illustrated with FF architectures from the literature and, for each of them, the advantages and disadvantages are exposed and finally summarized. At the end, we point out the explicit pulse-triggered flip-flop topology as a promising candidate to increase the energy-efficiency of the UWVR and ULP circuits. This topology suffers from two main drawbacks, namely the robustness and the positive hold time, which are handled in Chapter 3 and 4 respectively. Chapter 2. After having observed all the architectural ideas in the previous chapter, we perform a design reasoning to select the most efficient flip-flop architectures for the targeted applications. This leads us to compare six pulsetriggered architectures. The comparison consists of determining the set of design points, i.e. transistor gate width, which provides optimal points in the energydelay (E -D) domain, from the high-speed region to the low power region. The pulsed-FFs architectures are compared in the E -D domain both at nominal and ultra-low supply voltages. While the transmission gate pulse latch muxed clock (TGPL-Clk) architecture presents the best energy-efficiency for high-speed operations, the complementary CMOS muxed data (C 2 MOS-Data) architecture is revealed as the most energy-efficient pulsed-FF architecture over a wide range of targeted delays and supply voltages. Afterwards, we show how the back biasing technique allowed by the FDSOI technology, can provide better energy and delay performances than the sizing methodology used before. Finally, silicon measurements confirm the results obtained previously.

Chapter 3. This chapter starts by explaining the inherent tradeoff of pulsetriggered structures at ULV. To ensure a sufficient robustness, one of the two main drawbacks of pulsed-FFs, a large energy overhead is paid in several ways. To overcome this issue, we propose a current-starved delay generator (DG) presenting enough degrees of freedom to reach the desirable robustness without energy penalty. Then, post-layout simulations and silicon measurements show how our proposed DG structure improves dramatically the robustness of pulsed-FFs.

Finally, we present a way of implementing flip-flop additional functionalities, usually added in standard-cells library, in the pulse generator, thus providing a robust and energy-efficient pulse-triggered flip-flop.

Chapter 4. Firstly, the behaviour of pulsed-FFs face to the clock skew appearing at clock tree synthesis, is exposed. Afterwards, a new conditional capture technique is presented and explained. As the pulse generator (PG) is the highest energy consumer in pulsed-FF architectures, this structure efficiently tackles the FF energy dissipation. Furthermore, the E op is reduced up to the point that the pulsed-FF finally exhibits a lower energy consumption than master-slave architecture. Then, after confirming the efficiency of the shared pulse generator, we integrate previous innovations, namely fast and energy-efficient latch, robust and energy-efficient DG and shared PG, in a structured register file. This pulsed-FF based register file presents a higher speed, lower energy consumption and lower area compared to master-slave based register files.

Conclusions and appendixes. We finally summarize this work and draw some perspectives. Additionally, the conclusion is followed by 3 appendixes. In Appendix A, additional studies about pulsed-FF architectures are exposed. The optimal conditional discharge flip-flop (CDFF) structure version is justified, regarding the precharge mechanism and the reordering technique, and the inefficiency of the resettable and scannable conditional precharge flip-flop (CPFF) is exposed. In Appendix B, the testbench used for the flip-flop comparison in Chapter 2 is presented in details. In particular, the delay and energy are rigorously defined. Finally, Appendix C exposes the testbench used for the register file comparison of Chapter 4.

Note.

Let us highlight that the basic edge-triggered sequential element is sometimes called D-latch in the literature, mostly american. It will be called flip-flop in the rest of this work and latch will be used for level-sensitive elements. For decades, the main target of the microelectronics industry has been the increase of the speed of digital circuits while reducing the fabrication cost. This had been reached by two main ways of improvement: the scaling of the transistor dimensions and the architectural optimisation of the processor. Technology scaling has allowed to increase the speed and the integration density of digital circuits while reducing the overall power consumption. Nevertheless, we are today reaching the limits of this trend both from a technological and a design point of view. As the dimensions scale down, the variability of electrical properties becomes more and more predominant, leading finally to an unacceptable margin and energy overhead [START_REF] Bol | Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era[END_REF]. Many disruptive technologies have been proposed to replace the conventional bulk, especially the fully-depleted silicon on insulator (FDSOI) technology. This technology provides speed and energy gains with minimum change in the technological process. The section 1.2 explains how the addition of a buried oxide layer provides a great improvement in the transistor properties and how it can help designer to improve the energy-efficiency.

In the same time, the architecture of the central processing unit (CPU) has drifted from a single instruction by clock cycle to a deeply pipelined and also multi-scalar CPU architecture. Pipeline technique adds several registers along the datapath in order to subdivide instructions into many stages [START_REF] Harris | Digital Design and Computer Architecture[END_REF]. Multi-scalar architecture is a partial replication of the datapath allowing the simultaneous processing of N data for an approximate cost of N in hardware [START_REF] Harris | Digital Design and Computer Architecture[END_REF]. Therefore, while heavily increasing the throughput, these architectures need a largely superior amount of sequential elements leading the entire clock tree to become the biggest power consumption part of a modern digital circuit [START_REF] Paik | Implementation of pulsed-latch and pulsedregister circuits to minimize clocking power[END_REF][START_REF] Magen | Interconnect power dissipation in Microprocessor[END_REF][START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF]. As a result, it is of primary importance to choose the proper flip-flop architecture in order to provide fast and energy-efficient processors.

The chapter is structured as follow: section 1.2 gives an overview of the trend of the microelectronics industry and why it has reached its limits with the classical bulk technology. Then, the Fully-Depleted Silicon On Insulator (FDSOI) technology is presented as well as its capabilities to help designers to overcome the limits of scaling. Afterwards, section 1.3 briefly introduces the modern processor architectures and exhibits the importance of flip-flop (FF) architecture on the speed and energy of sequential digital circuits. An overview of the stateof-the-art flip-flop architectures is performed for the four big categories of FF: master-slave, differential, pulse-triggered and dual edge. The section concludes by pointing out the remarkable properties of explicit pulse-triggered flip-flop (pulsed-FF) topology and motivates the research approach of the following chapters.

TECHNOLOGICAL CONTEXT

From a technological point of view, the reduction of the fabrication cost was achieved by the trend of Moore's law: the transistor density in a microprocessor doubles every 18 to 24 months. The reduction of transistor dimensions has for direct impact to decrease, for the same amount of functionalities, the area of the circuit and thus the cost per chip per wafer. This last point is obviously a determinant parameter for an industrial point of view and that is why this trend is continuing. This section explains why this law is also interesting for two other important figures of merit of a microelectronic circuits -the speed and the energy consumption -and why this trend is reaching its limits with the advanced technology. Finally, the FDSOI technology and its new design facilities will be presented.

Delay and energy equations

Before explaining the impact on the circuit performances, let us remind the fundamental equations giving the speed and the energy consumption of a digital circuit. It allows to understand the evolution of these performances with the technological parameters.

The propagation delay of a CMOS logic gate is proportional to:

T del ∝ C L V dd -V th I on (1.1)
where C L is the typical load capacitance of the transistors, V dd the supply voltage, V th the MOSFET threshold voltage, and I on the average MOSFET drain current in on-state. The instantaneous power of a digital circuit is composed of two components: the dynamic power, only consumed when circuit performs computation, and static power.

P inst = P dyn + P stat (1.2)
The static power can be expressed as

P stat = I leak V dd (1.3)
where the leakage current I leak depends exponentially on the threshold voltage V th [START_REF] Bol | Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era[END_REF]:

I leak ∝ e Vgs+ηV ds S × (1 -e -V ds U th ) (1.4)
where η is the DIBL coefficient, S is the subthreshold swing equal to ln(10)nU th , n the body-effect factor and U th the thermal voltage. The dynamic power also comes from two components: the capacitance switching power and the short circuit current. The capacitance switching is the power needed to charge and discharge the capacitance of the circuit, especially the transistor gate capacitances and interconnection wires.

P sw ∝ C L V 2 dd f clk (1.5)
where f clk is the clock frequency. If the circuit is properly sized, the input slope on the gate is sufficiently abrupt so that the short circuit power P sc can be kept at 5-10% of P sw [11].

The energy per operation can be extracted by integrating the power over the clock cycle:

E tot = E dyn + E stat (1.6) E tot ≈ E sw + E stat (1.7) E tot ∝ C L V 2 dd + I leak V dd T clk (1.8)
where the short circuit energy is neglected in equation 1.7 and

T clk = 1/f clk is the clock period.
Reducing transistor size has led to a reduction of the supply voltage in order to guarantee the same electrical field across the gate dielectric and to avoid an electrical breakdown. The threshold voltage is reduced to keep the same overdrive voltage and thus the current in on-state. The gate delay was thus reduced because both C L and V dd are reduced while I on remained roughly the same. Although a decrease of the threshold voltage increases the leakage current, the overall energy was effectively reduced because the leakage energy stayed quite low compared to dynamic energy. Therefore, reducing dimension and thus supply voltage permitted the microelectronics industry to create digital circuits with lower cost, higher speed, and lower energy consumption. Now, let us have a look on the last statement for ULV and ULP circuits. As the clock period depends on the delays of the gates (T del ) and both I on and I leak depend on supply voltage, equation 1.8 has a non-trivial dependence on V dd . Actually, the shape of this function exhibits a global minimum at a given V dd [START_REF] Bol | Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era[END_REF]. From an energy point of view, two V dd are concerned: the V dd,opt is the supply voltage which gives the lowest energy per operation. If a circuit has a certain amount of computation to do before coming back in stand-by mode, it should operate at this supply voltage to minimize the amount of energy consumed by computation. The V dd,min is the minimum supply voltage which guarantees the correct functionality of the circuit. If a circuit has to permanently compute data and is concerned about power, it should work at this voltage to minimize its power consumption.

Those two voltages are highly impacted by the transistor variability, as explained in the next section.

The end of scaling benefit in bulk technology

The conventional bulk transistor is represented in figure 1.1. The electrical relations between currents and voltages depend on many technological parameters, such as the effective gate width, gate length, the oxide thickness,... and the doping concentration. All of those parameters are slightly modified during the fabrication process, leading to a variability in voltage-current relation between the transistors on a same chip and on the whole wafer.

Scaling down and down the technology, the size of the transistors becomes so small that the discrete number of the implanted ions and the roughness of the layer interfaces have a huge impact on the average threshold voltage. It has been shown that the critical device parameter variability is the threshold voltage variability, mainly caused by the doping statistics in the channel region for bulk technology [START_REF] Veendrick | Nanometer CMOS ICs[END_REF]. Figure 1.2 illustrates the effect of the dopant position on the threshold voltage. To study the evolution of performances with the scaling, the effects of the variability must be taken into account. To do that, we have to introduce an equation which has not been mentioned in the previous section, the Pelgrom's law. It states that the variability of the threshold voltage of transistors among the whole chip follows a Gaussian distribution with standard deviation

σ V th = A V th � W g L g (1.9)
where W g and L g are respectively the transistor gate width and length and A V th a parameter depending on the technology. Last decade, the variability induced by the aggressive sizing of the transistor led designers to take huge margins to ensure the correct functionality of the chip. As shown in figure 1.3 and thoroughly explained in [START_REF] Bol | Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era[END_REF], the minimum energy point is no longer lowered by reducing the size of the technological node. Thus, because of the variability, the energy consumption of the advanced technological nodes is actually bigger, in contrast to the basics laws of scaling. On top of that, the variability has a direct impact on V dd,min [START_REF] Itoh | Low-voltage scaling limitations for nano-scale CMOS LSIs[END_REF].

To overcome this limit in Moore's law, new transistor technologies were suggested in the last decade. Today, the most competitive technologies are the finger field-effect transistor (FinFET) and the fully-depleted silicon on insulator (FD-SOI).

In FinFET technology, also called trigate in certain companies, the transistor channel is surrounded on three sides by the same poly-silicon layer. It was developed and presented to push still away the speed of the high-performance circuits [START_REF] Chang | A 25-nm gate-length FinFET transistor module for 32nm node[END_REF][START_REF] Wu | A 16nm FinFET CMOS technology for mobile SoC and computing applications[END_REF]. On the other hand, the FDSOI technology [START_REF] Grenouillet | UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below[END_REF][START_REF] Liu | High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond[END_REF][START_REF] Fenouillet-Beranger | Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below[END_REF] has been presented as a very promising candidate for low power applications and will be described in the next section.

FDSOI transistor technology

The FDSOI transistor is represented in figure 1.4. A thin oxide layer, or buried oxide (BOX), is inserted between the bulk and the active part such as the channel height is a few nanometer (8nm of silicon for 28nm technology for a BOX of 25nm height). Beneath the BOX, the bulk region is now called the back plane. The back plane might be different to the bulk of the wafer and is not necessarily clamped to the supplies. When the gate-source voltage becomes higher than the threshold voltage, the electrons coming from the drain and source completely fill the channel between the gate and thick oxide insulator. The silicon of the electron channel is thus entirely in deep depletion regime, giving the name of the technology : Fully-Depleted Silicon on Insulator.

As first observation, the junction capacitance between the source and drain and the bulk is now reduced to a little PN junction within the channel. It provides a junction capacitance per length highly lower than in bulk technology [START_REF] Flandre | Dispositifs électroniques avancés[END_REF][START_REF] Vitale | FDSOI Process Technology for Subthreshold-Operation Ultra low-Power Electronics[END_REF].

As the complete electron channel lies in the thin volume between the gate and the BOX, the gate voltage better controls the channel evolution. Thanks to that, the body effect n and many short channel effects, as the DIBL, are dramatically reduced, thus providing an enhanced subthreshold slope [START_REF] Bol | Sub-45nm Fully-Depleted SOI CMOS Subthreshold Logic for Ultra-Low-Power Applications[END_REF][START_REF] Kilchytska | On The UTBB SOI MOSFET Performance Improvement In Quasi-Double-Gate Regime[END_REF].

As there is no more PN junction between the bulk and the source or the drain of the FDSOI transistor, the absolute value between the source voltage and the back plane voltage, or back bias, can be superior to 0.3V. Moreover, it has been proved that the buried oxide can support a voltage difference of up to 2 volts without electrical breakdown [START_REF] Wilson | A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking[END_REF]. However, the back interface of FDSOI transistor is thin enough in such a way that a variation of the back bias influences the electrical characteristics and performances of the transistor. As with conventional bulk transistor, the gate voltage needed to form the electron channel depends on the voltage difference with the bulk voltage. In other words, the back bias modifies the threshold voltage of transistor. All of that means that, during the life time of the circuit, the threshold voltage of the transistor, one of its main parameter for the current-voltage dependency, can dynamically vary over a relative wide range. As the buried oxide is approximately ten times thicker than the main gate, the back biasing can be considered as a gate voltage having an influence roughly ten times lower on the current.

On the contrary of bulk transistor, the FDSOI transistor channel is undoped. It provides a lower variability -up to two times smaller A V th [START_REF] Weber | High immunity to threshold voltage variability in undoped ultrathin FDSOI MOSFETs and its physical understanding[END_REF] -because the threshold voltage does not depend any more on the dopant number (see section 1.2.2). As thoroughly explained in [START_REF] Noel | Multi-VT UTBB FDSOI Device Architecture for Low Power CMOS Circuit[END_REF], a multi-V th technology is provided by changing the type of doping of the back plane and its polarization. Therefore, it is possible to produce up to three different threshold voltages without doping the channel and adding variability, unlike the bulk transistors. As a example, in the LVT feature of the 28nm FDSOI technology, the NMOS transistor is lying above a N doped well and the PMOS is above a P doped well. This feature will be used in every simulation and measurement results of this book.

Let us sum up the advantages of FDSOI technology owing to the addition of the BOX and the better channel electrostatic control:

• The parasitic junction capacitances are radically reduced.

• The subthreshold slope is higher, so is the I on /I of f ratio.

• There is no channel doping leading to a dramatically lowered variability.

• The threshold voltage can be modified by the back plane doping type and also dynamically by the back plane voltage (back bias) over a wide voltage range.

In [1], authors show that this technology offers several advantages and degrees of freedom to reach a pareto-like optimum in the energy-delay domain. These conclusions on the CMOS standard cells obviously apply for the most critical one in term of impact on the overall circuit performances: the flip-flop. In this respect, the next section will present the state of the art flip-flop architectures and will select the architectures which seem to be the most interesting ones for high-speed and low-power applications.

FLIP-FLOPS IN MICROPROCESSOR ARCHITECTURE

Flip-flop is the fundamental element of the synchronous logic. In a synchronous microprocessor, the clock signal is spread among a big number of paths all around the chip, forming the clock tree. The clock signal essentially brings in its edge the information that the data is valid and ready, and synchronises the whole circuit.

This section first explains why the number of flip-flops has literally exploded in the modern synchronous digital circuits and why their characteristics have a direct and huge impact on the overall circuits performances. Afterwards, the FF main figures of merits will be defined and then compared between the different flip-flop architectures of the state of the art. Thanks to that, the choice of explicit pulse-triggered flip-flop is motivated for high speed and low power applications.

Flip-flop contribution in modern ICs

The technique of pipeline has been widely and efficiently used to increase both the clock frequency and the operations per second of a processing unit, thus the instruction level parallelism (ILP). In contrast to the single instruction per cycle architecture, pipeline technique adds register along the datapath in order to separate the instruction treatment into several stages: fetch, evaluate, memory write-back,... It allows to reduce the length of the datapath between flip-flops and to treat different instructions at the same time. The clock frequency and the average throughput are thus intensively increased. Nevertheless, each pipeline stage needs a register to store all the data and the instruction control bits.

In addition to pipelined CPUs, the super-scalar technique has also been developed to increase the ILP. It consists of replicating combinational elements, the arithmetic/logical unit for example, to process several data in parallel. As the intermediate results of the ALU must be stored, the register file is also expanded in relation with the hardware replication. The choice in architecture has a direct and immediate impact on the number of flip-flops in the core: if the number of stages and/or of hardware replication is N times bigger, the number of flip-flops is roughly N times bigger.

Over the last years, systems proposing the time-borrowing technique to push away the speed limit of digital circuits have appeared in the literature. The idea of the time-borrowing technique is to work with a lower clock period than the critical path delay while sensing the end of critical paths thanks to custom flipflops. If the circuit senses that a data changes during the sensing time after the triggering clock edge, a recovery mechanism is activated to guarantee the proper functionality of the circuit.

Therefore while increasing the speed, these three techniques induce a much higher complexity of the clock tree. Combined with the increase of the length of the datapath, tens of thousands of flip-flops were added to digital circuits to meet the speed target. Consequently, the energy consumption of the clock tree including its leafs (FF) exploded to become the most important part of the overall energy consumption of a modern digital circuit, up to 50% or even 70% [START_REF] Paik | Implementation of pulsed-latch and pulsedregister circuits to minimize clocking power[END_REF][START_REF] Magen | Interconnect power dissipation in Microprocessor[END_REF]. On top of that, around 80% of the switching energy of a clock tree is located at the leaf level: the flip-flops [27]. The flip-flop architecture is thus an important element that designers must take into account to provide an energyefficient circuit.

Flip-flop figures of merit

For standard high speed and low power applications, the FF figures of merit are the following (illustrated in figure 1.5):

• The clock-to-output (Clk-to-Q) delay. It is the propagation delay between the triggering clock edge and the time when the output data of the flip-flop is valid. It should obviously be as short as possible.

• The setup time. The setup time is the minimum time when the data must be valid before the triggering clock edge. It is defined positive when the data edge is before the clock edge and should be as low as possible. Designers use metrics based on the three signals of the figure 1.5, to provide quantitative criteria to compute the setup time. We propose a new metric dedicated to pulse-triggered flip-flops in [START_REF] Bernard | An efficient metric of setup time for pulsed flip-flops based on output transition time[END_REF].

• The input-to-output (D-to-Q) delay. For flip-flops, it is the time between the input data edge when it arrives at the setup time, and the output data edge. Therefore, the D-to-Q delay can be written as equal to the Clk-to-Q delay plus the setup time (D-to-Q = Clk-to-Q + setup).

• The hold time. The hold time is the minimum time until when the valid data must stay valid and stable after the triggering clock edge. It is defined positive when the data edge is after the clock edge.

• Finally, the energy consumption and the area of the flip-flop should obviously be as low as possible.

Flip-flop architectures

There is an extremely large amount of flip-flops topologies in the literature. Edge-triggered cells have been the subject of many studies and continue to feed the imagination of researchers.

In [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF], a comparison of nineteen state-of-the-art flip-flops is performed. The authors first classified them into four main categories:

• master-slave flip-flops

• differential flip-flops
• pulse-triggered flips-flops: implicit and explicit

• dual-edge triggered flip-flops

This section shows, for each topology, the different architectures proposed in the literature and concludes by a summary of their advantages and drawbacks. Then, the next section explains more precisely why we selected the explicit pulsetriggered flip-flop architecture category as the best candidate for our high-speed and low-power applications.

Master-Slave

The master-slave flip-flops are composed of two latches connected in series. The input data is connected to the master latch and the output of the FF is the output of the slave latch. The master latch is enabled during the clock period preceding the triggering clock edge, so that the data information can pass through the latch during this period. The slave latch is enabled during the other period of the clock. Consequently, the information passes from the master latch to the slave latch only at the triggering clock edge. During the non-triggering clock edge, the slave latch becomes closed and keeps the previous data value while the master latch becomes open and can switch to a new data value.

As soon as the master latch samples the correct data, the slave latch will automatically follow. Therefore, the setup time is highly subject to the switching speed of the master latch. Then, the clock to output (Clk-to-Q) delay depends mainly on the propagation delay in the slave latch. The input-to-output (D-to-Q) delay, here the sum of the setup time and the Clk-to-Q delay, is not only the propagation delay across the two latches but has also to take into account the margin (included in the setup time) needed to guarantee the correct latching of the data. Among a large panel of master-slave FF in the literature, let us remind the conventional static architecture shown in figure 1.6a. This architecture is called the transmission gate master-slave (TGMS) and is the basic structure of masterslave flip-flop.

The great advantage of the complementary square MOS (C 2 MOS) architecture, compared to the TGFF one, is its immunity to the clock overlapping phenomena. Indeed, if the complementary clocked signals (clk and clk on figure 1.6) are temporarily both at the same level, there is a short circuit path between the inverter supplies and the input data of TGMS whereas it is impossible for the C 2 MOS structure. This effect creates a short circuit current during a short period of time which can nevertheless represent a significant energy overhead.

In order to combine the speed of the TGMS -thanks to pass-gate utilizationand the robustness of the mC 2 MOS, the transmission gate flip-flop (TGFF) has been proposed and is today the reference for master-slave architecture comparison (figure 1.6c).

More complicated master-slave architectures have been proposed in the literature. We can cite the comparisons of [START_REF] Rebaud | A comparative study of variability impact on static flip-flop timing characteristics[END_REF], [START_REF] Ko | High-Performance Energy-Efficient D-Flip-Flop Circuits[END_REF], and [START_REF] Markovic | Analysis and design of low-energy flipflops[END_REF] and the proposition of [START_REF] Fuketa | 12.7-times Energy Efficiency Increase of 16-bit Integer Unit by Power Supply Voltage Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF) and Separated V DD between Flip-Flops and Combinational Logics[END_REF], both illustrated in figure 1.7. The last two propose NAND-gates based master-slave flip-flops. Those architectures do not have any transparency time thus avoiding metastable state [START_REF] Rebaud | A comparative study of variability impact on static flip-flop timing characteristics[END_REF][START_REF] Fuketa | 12.7-times Energy Efficiency Increase of 16-bit Integer Unit by Power Supply Voltage Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF) and Separated V DD between Flip-Flops and Combinational Logics[END_REF][START_REF] Piguet | Low Power Electronics Design[END_REF]. Nevertheless, the propagation delay is highly increased by the series of NAND gates and thereby these structures are not used in applications needing performances.

Seeing the principle of master-slave flip-flop, we can say that the setup time is in nominal conditions strictly positive, meaning that the correct data value must change before the clock edge in order to permit the master latch to sample the data before its closing. On the other hand, the hold time is, in nominal conditions, negative because once the master latch is closed after the triggering clock edge, a change of the input data will not influence the flip-flop output. (f ) The write-port master slave FF (WPMS) [START_REF] Markovic | Transmission-gate based flipflop[END_REF].

Differential

The differential flip-flops, also called dual-ended, have also the complementary input data as input and generate simultaneously the output signal and its complement. The primary concept of the design is the symmetry of the structures, ensuring a identical behaviour between the data-to-output path and the complementary path. This concept is illustrated in figure 1.8 by the adaptation of the conventional master-slave structure.

In non differential architectures, an extra inverter might be used at the synthesis step if the complementary output is needed in a following path. This causes a speed penalty and a shift between the two complementary signals, possibly causing disturbing glitches later in the circuit [START_REF] Myjak | An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems[END_REF]. That is why the main application of this kind of flip-flop is the deeply pipelined systems where the delay from flip-flop is a heavier penalty for the computational time [START_REF] Myjak | An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems[END_REF]. Moreover, the improved alignment in the output signals is especially suitable for combinational elements such as decoders and multiplexers, where the complementary signal is used in every computation. Despite some exceptions (figure 1.9), most of the differential flip-flop found in the literature are based on the sense amplifier principle (figures 1.10): one differential pair is connected to a symmetrical bistable element and senses the complementary inputs. The nodes of the amplifier part are pre-charged to the supply voltage value (V dd ) during the clock level preceding the triggering-clock edge. After that, the high input value pulls one dynamic node to ground which switches the following bistable to its new state. During the following clock level, the flip-flop is always open and can evaluate a new data coming to the input. It means that this kind of flip-flops are actually latches and designers must take care of the hold time constraint and the glitch effects. After the non-triggered clock edge, the dynamic nodes are pre-loaded again.

D Q CLK CLK D Q CLK CLK
Q Q D D CLK CLK CLK
(a) SAFF basic structure [START_REF] Yuan | New single-clock CMOS latches and flipflops with improved speed and power savings[END_REF]. To avoid the level-triggered behaviour of the previous architecture, [START_REF] Yuan | New single-clock CMOS latches and flipflops with improved speed and power savings[END_REF] proposed differential master-slave architectures (figure 1.11). Nevertheless, those structures suffer from a highly penalizing voltage drop at one of the slave latch input, thus reducing the driving capability of its outputs [START_REF] Stojanovic | Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems[END_REF].

Q Q D D CLK CLK CLK S R S R R S S S R R (b) Improved SAFF topology [36]. Q Q D D CLK K CLK S R S R R S (
Thanks to the NMOS differential pair, differential flip-flop architectures have shown lower D-to-Q delays than master-slave ones. Nevertheless, because of the pre-load, the additional complementary data-to-output path and the delay buffers needed to fix the hold time constraint, this topology leads to a huge energy overhead compared to master-slave. Furthermore, in many differential architectures, there is no feedback transistors in the bistable element. It means that a stack of NMOS must fight and beat a PMOS in the bistable element in order to change its state. Consequently, those structures are extremely susceptible to process variation at ultra-low voltage where an unbalanced strength may cause serious issues and design problems. For these reasons, differential flip-flops are not suitable for low-power applications and have essentially been used in high-speed processors.

Pulse-Triggered

The pulse-triggered flip-flops, or simply pulsed-flip-flops (pulsed-FFs), are composed of only one latch which is open during a short period of time after the triggering clock edge, defined by a pulse-like signal. During this short period, the data value passes through and changes the state of the latch, as illustrated in 1.12. Afterwards, the latch is closed and its output value remains constant. The pulsed behaviour is achieved thanks to a delayed clock signal generated in the flip-flop. During the period defined by this delay, both the clock and the delayed clock signals have the same voltage value. A comparative stack allows to get open the latch during this period.

Due to the architecture, a data value changing slightly after the clock edge can be sampled by the latch. Therefore, the setup time is essentially negative while the hold time becomes positive in contrast to the master-slave topology. As only one latch is laying in the D-to-Q path and no timing barrier is involved, the speed of pulse-triggered FF is largely superior to MS.

There are two main types of pulsed-flip-flops: implicit and explicit. In implicit pulsed-FFs, there is no node which exhibits a pulse signal at any time during the clock cycle (see figure 1.13). The pulse behaviour is thus called implicit. As the charge and discharge into the flip-flop also depend on the data, the architectures often need a stack of minimum three transistors: two performing the pulse property and one containing the data information. A lot of proposed implicit pulse-triggered flip-flops have been called semi-dynamic, as reference to the dynamic NMOS logic. Those structures are composed of a static part, meaning a bistable element, and a dynamic part with a NMOS stack and a pre-charge mechanism (figures 1.13b, 1.13c, and 1.13d).

For the explicit pulsed-FFs, the latch is connected to the output(s) of a pulse generator (PG). The element provides at least one signal which has effectively the shape of a pulse. It often contains the delay generator and has the advantage to be shared by several latches. As the latches need only the pulse signal to perform their flip-flop functionality, like the clock signal for master-slave flip-flop, this signal can be propagated as well as the clock tree in a conventional digital circuit. Moreover, a stack of two transistors in the latch is sufficient to contain

CLK CLK D Pulse Pulse (a)
The conventional pulse generator.

CLK D CLK

(b) Low area delay generator [START_REF] Teh | Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems[END_REF]. In 1.14c and 1.14d, transistors in diode mode lead to a lower swing, thus energy consumption, in the delay generator [START_REF] Su | A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder[END_REF].

the clock and input data informations. The overview starts by the different pulse generators found in the literature and then the latches. These latches can be used with every presented PG and conversely.

The conventional pulse generator for pulse-triggered flip-flops is shown in figure 1.14a. The inputs of the NAND gate are the clock signal CLK and its delayed complementary signal CLK d . It provides the complementary pulse signal P ulse which is connected to the latch and to the input of an inverter providing the P ulse signal. The delay generator is located between the two inputs of the NAND and is composed of three inverters giving the complementary and delayed signal needed. In [START_REF] Teh | Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems[END_REF], authors propose to add stacking in the delay path in order to use only one inverter to perform the delay. It has also the advantage not to increase the clock input capacitance (clock load) on the contrary of increasing the gate length. The pulse generators of figures 1.14c and 1.14d have been implemented in an implicit pulsed-FF [START_REF] Su | A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder[END_REF] but this low swing technique can be easily transposed in the delay generator of the conventional PG. The extremely basic explicit pulse-triggered structure is shown in figure 1.15a. A great improvement in its robustness is shown in figure 1.15b where the feedback of the bistable element is idle during the pulse. Those structures are also called in the literature transmission gate pulsed latch (TGPL) to make the differentiation with the master-slave structure TGFF (figure 1.6). As with implicit pulsed-FFs, sense-amplifier-like versions have appeared in the literature. As designers always inspire from previous topology, a semi-dynamic explicit pulsed-FF has also been proposed ( [START_REF] Tschanz | Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors[END_REF] figure 1.16c).

Conditional techniques

In many architectures seen before, especially in the semidynamic topologies, nodes are charged or discharged even when the data does not change. As the data switching activity factor (α sw ) is on average between 0.1 and 0.4 depending on the application, this leads to a useless energy consumption. Therefore, the interesting idea of conditional latching technique appeared in the literature. The key point is to use the information of the output of the flip-flop, combine it with the input data and enable or not the switching, to save the

CLK D Q D CLK CLK D CLK D (a)
The singled-ended version of conditional capture flip-flop (CCFF) [START_REF] Kong | Conditional-capture flip-flop for statistical power reduction[END_REF].

CLK Q D CLK Q D S R R S S R R S Q Q (b)
Dual-ended or differential version [START_REF] Kong | Conditional-capture flip-flop for statistical power reduction[END_REF]. energy consumption. As said, the main characteristic is the use of the output signal in feedback in the writing system. In semi-dynamic structures, we can cite the conditional capture technique represented in figures 1.17a and 1.17b and the conditional precharge and its complementary discharge techniques in figures 1.17c and 1.17d. Each of them was implemented in pulse-triggered topology.

Dual-edge

A dual-edge flip-flop latches the data on both edges of the clock. With the same datapath, the clock cycle can be divided by two, keeping the same throughput. As the switching activity of the clock tree is divided by two, so is its switching energy.

Every architecture discussed in the preceding section can be adapted in dualedge-triggered topology [START_REF] Tschanz | Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors[END_REF][START_REF] Chung | The Usage of Dual Edge Triggered Flip-flops in Low Power Low Voltage Applications[END_REF]. For most of them, the writing part is doubled to perform the triggering on both edges, meaning that the internal energy con- sumption of the flip-flop is increased. At some point, the data and clock loads are so increased and even doubled that the saving energy in the clock tree does not cancel out the energy overhead due to making the dual-edge feature (see [START_REF] Tschanz | Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors[END_REF] and figure 1.18a). For all the reasons cited above, the literature trend is the adaptation of explicit pulsed-FF into dual-edge version. The main change in the architecture of dualedge flip-flops is the pulse generator, working on both edges. The direct solution is to put a XOR gate instead of an AND (NAND+inverter, figure 1.19a). Other implementations are shown in figure 1. [START_REF] Fenouillet-Beranger | Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below[END_REF].

Finally, let us notice that a duel-edge triggering system must ensure a perfect balanced clock cycle. Indeed, it is the shorter level of the clock which determines the operational clock frequency. Therefore, buffers and inverters must have perfectly balanced rising and falling propagation delay, as well as the clock generator. This assumption is extremely hard to guarantee because of process, voltage and temperature (PVT) variations, especially at ultra-low voltage.

Summary and state of the art in ultra-low power domain

The master-slave architecture is the most used topology, especially in low power circuits. Its behaviour is robust and straightforward to understand for microarchitecture designers and that is why it is today the most used FF architecture, especially in ultra-low voltage circuits. Nevertheless, it suffers from a large D-to-Q delay because of the use of two latches virtually separated by a clock barrier.

The differential flip-flops are composed of two symmetric rails of data and are based on the sense-amplifier principle. They are more susceptible to process variation and often need a precharge at each clock cycle exhibiting a high energy consumption. They are so highly not recommended for ULP and ULV circuits.

The pulse-triggered flip-flops are made of only one latch which is open during short period after the triggering clock edge. The propagation delay is thus dramatically reduced and the setup time becomes negative while the hold time is positive.

A dual-edge architecture samples the data at each edge of the clock signal. Some architectures allow to reach this property without duplicating the datapath and thus doubling the clock and data load. But the most energy-efficient way is to modify the pulse generator of the explicit pulsed-FFs. However, the clock cycle must be perfectly balanced in order to have the same timing constraints both in high and low levels of the clock. This statement is hardly achieved at ultra-low voltage.

Table 1.1 gives a summarized comparison of the four flip-flops topologies. First, we can cite the numerous conditional techniques presented before [START_REF] Kong | Conditional-capture flip-flop for statistical power reduction[END_REF][START_REF] Nedovic | Conditional techniques for low power consumption flip-flops[END_REF][START_REF] Zhao | High-Performance and Low-Power Conditional Discharge Flip-Flop[END_REF][START_REF] Hamada | A Conditional Clocking Flip-Flop for Low Power H.264/MPEG-4 Audio/Visual Codec LSI[END_REF], helping to decrease the energy consumption. Then, in the wide comparison performed in [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF], the basic and conventional transmission-gate structures (see the TGFF in figures 1.6c) are pointed out to be the most energyefficient ones. Later, the adaptive coupling flip-flop (ACFF) was proposed by [START_REF] Teh | A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS[END_REF] to tackle the susceptibility of differential structures to process variation. As we can see in figure 1.20, the basic differential structure is enhanced by the addition of two pairs composed of one NMOS and one PMOS in parallel. This helps to alleviate the drawbacks of the conventional topology, due to a short circuit path formed between supplies and an overdesign of the pull-down NMOS for worst case conditions. As the conventional structure, it needs only one phase of the clock which means the saving of clock buffer and two times less clocked transistors, meaning reduced clock load. This architecture has been fabricated in 40nm CMOS bulk process and has shown an energy per cycle of 2fJ per cycle for a data activity of 10% at 1.1V which is the lowest measured energy consumption reported in the literature at nominal voltage. The main drawback of this structure is its high setup time leading to a relatively large D-to-Q delay (see table 1.2). Finally, silicon measurements showed a tolerable yield down to 0.6V.

Later on, [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF] proposed the conditional push-pull pulsed latch (CP 3 L) architectures and studied it at nominal voltage operations (1V). It can be categorized as an explicit conditional pulse-triggered flip-flop with the output feedback in the pulse generator (see figure 1.21). It exhibits the best energy-delay product (EDP) among the literature, mainly thanks to the small delay of pulse-triggered flip-flop (table 1.2). As the D-to-Q path is composed of two stages, it exhibits better performances for a high output capacitance [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF].

[50] proposed a differential flip-flop (IMD-FF) and studied its reliability until 0.4V. Unfortunately, it is only compared to other differential flip-flops and exhibits a NMOS stack having to counter a PMOS.

Finally, [START_REF] Lin | A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS[END_REF] proposed an adaptive pulse-triggered flip-flop (APFF) with a replica delay generator with the aim of performing operation over a wide voltage

CLK1 CLK CLK2 CLK3 CLK4 CLK CLK CLK1 CLK1 CLK3 CLK3 CLK4 CLK4 CP f CP f CP r CP r D D R S n R S n Q Q Q D Q D Q D Pseudo-NOR Pseudo-NAND Shareable Figure 1
.21: Conditional push-pull pulsed latch (CP 3 L) [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF]. The lowest EDP of the literature.

range, from 1V down to 0.2V. Comparison to conventional master-slave has shown that, over the wide range, the delay is more than two times lower, the energy consumption about 30% higher, and thus the energy-delay product of the pulsed-FF represents approximately 65% of the master-slave EDP. Keeping in mind all of the descriptions above, this section points out the remarkable properties of the explicit pulse-triggered flip-flops and motivates this choice for the research strategy of the following chapters.

As every pulsed-FF, there is only one latch in the input-to-output path. The propagation delay is thus extremely low compared to architectures with two complementary latches.

In opposition to differential flip-flops, only one data rail and output inverter are charged and discharged. Moreover, contrary to dynamic or NMOS-like flipflops, there is no pre-charging. The energy consumption is so largely lower than the second category of FF.

Compared to implicit pulse-triggered flip-flops, the explicit version should provide a lower delay for the same sizing because of the additional stack needed by implicit topology. This stack is also a drawback for ULV operations as it decreases the robustness of the CMOS logic. On the other hand, the pulse generator needed by explicit structure should provide a higher energy consumption with the same transistor size. Nevertheless, the output(s) of the pulse generator could be sent to the neighbouring identical latches, i.e. flip-flops. This technique provides a reduction of both the energy per flip-flop and the area per FF because the consumption and area of the pulse generator is normalized by the number of shared latches.

The dual-edge version of explicit pulse-triggered flip-flop only needs a dualedge version of the pulse generator, as the latch only needs a pulse signal at each clock edge to properly work.

Finally, explicit pulsing easily allows to perform time borrowing technique. In this text, time-borrowing has no concern with the latch-based pipeline architectures. It means that the valid data might arrive during a time-borrowing window after the triggering clock edge. If a data transition is detected during this time-borrowing window, an error signal is sent to the controller of the microprocessor architecture. Then, an error detection method with or without an error correction mechanism, is used to handle the late data arrival. The figure 1.22 shows a direct implementation of the time-borrowing and clock stretching techniques developed at system level in [START_REF] Ernst | Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation[END_REF] [53] and [START_REF] Lee | Timing error prevention using elastic clocking[END_REF]. Here we use one pulse generator, one latch and one transition detector which needs less hardware than one master-slave flip-flop (2 latches), one latch and one XOR gate as proposed in [START_REF] Ernst | Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation[END_REF] and [START_REF] Lee | Timing error prevention using elastic clocking[END_REF]. Furthermore, the latch connected to the pulse generator has a flip-flop behaviour. So, the delay error detection window is the pulse width and not nearly the half of the whole clock cycle as in [START_REF] Blaauw | Razor II : In Situ Error Detection and Correction for PVT and SER Tolerance[END_REF]. This property avoids a massive additional buffering insertion as mentioned in [START_REF] Blaauw | Razor II : In Situ Error Detection and Correction for PVT and SER Tolerance[END_REF]. Change needed in the pulse generator simply consists in the addition of two minimum sized transistors to perform the NAND gate behaviour. A control signal maintains the pulse active during the desirable time such as the next latch in the datapath stays open. This control signal is generated in the transition detector or somewhere else in the circuits, and provides a clock stretching property without the need of synchronous signals as in [START_REF] Lee | Timing error prevention using elastic clocking[END_REF]. Nevertheless, let us not forget that the pulse-triggered topology exhibits several disadvantages.

As the pulse signal makes the latch open after the triggering clock edge, the hold time is essentially positive, contrary to master-slave FF. Indeed if the data value quickly changes after the clock edge, a wrong data will be latched. Then, during the synthesis placement, the tools will automatically add buffer in short path to fix the hold constraints. This drawback can be mitigated by the simultaneous negative setup time thanks to the useful skew technique [START_REF] Chou | Useful-skew clock optimization for multipower mode designs[END_REF][START_REF] Shena | Useful Clock Skew Optimization under A Multi-corner Multi-mode Design Framework[END_REF] and delay buffers designed with the current-starved technique (Chapter 3).

Then, it directly follows from the architecture principle that, if the pulse width is not wide enough, the latch will not have enough time to switch with the new data. The issue is especially critical in the ultra-low voltage domain where the local variations lead to a wide range in the pulse width. This problem will be fully discussed and treated in Chapter 3.

CONCLUSION

In the aim of ULP and UWVR circuits, the need of efficient clock tree is of primary importance. This chapter has presented the FDSOI technology and the state of the art of flip-flop topologies and motivated the choice of explicit pulsetriggered flip-flops in FDSOI technology for the targeted ULP and UWVR applications.

In order to maintain the trend of the microelectronics industry, the new FDSOI technology has been proposed to overcome the bulk limitations. This technology allows designers better electrical performances, lower variability and a powerful degree of freedom -the back bias voltage -which allows to change dynamically the threshold voltage of transistors. Several previous studies have demonstrated the benefit of this technology compared to the conventional bulk one, especially to provide energy-efficient circuits.

In a modern complex digital circuit, the number of flip-flop and the complexity has literally exploded due to the increasing number of bits in the datapath and the intensive use of pipeline and super-scalar techniques. The proper flipflop architecture is thus a challenge for designers who want to reach a good energy consumption under throughput constraints. Among a wide overview of the flip-flop topologies, the explicit pulse-triggered architecture was pointed out as an extremely interesting candidates for high-speed and low-power applications, thanks to:

• a very small input-to-output delay -defined when the input arrives at the setup time,

• a negative setup time allowing much more reduction of clock cycle,

• the sharing of the energy-consuming pulse generator, reducing both energy and area,

• a lower delay than implicit pulsed-FF thanks to lower stacking,

• dual-edge and time-borrowing facilities that can be more easily implemented with explicit than implicit pulsed-FFs.

In the following chapters, the design of energy-efficient explicit pulsed-FFs in FDSOI is studied. As seen, the study can be separated between the latch and the pulse generator which will therefore be the topics of the next two chapters.

Abstract

This chapter gives a complete comparison of explicit pulse-triggered flip-flops architectures in order to select the most energy-efficient ones, according to the specifications of UWVR and ULP applications: fast and energy-efficient at nominal voltage and extremely energy-efficient at low voltage. First of all, a list of design constraints is elaborated to take into account the particularities of the targeted applications. From that, the choice of the compared architectures is motivated thanks to a theoretical analysis of the writing network in a latch. The sizing methodology used for the comparison is introduced and discussed.

After all that, the results of the comparison are exposed in the energy-delay domain. At nominal voltage, the TGPL-Data and C 2 MOS-Data architectures are shown to be the most energy-efficient in the low-power region while the TGPL-Clk structure exhibits the best energy-delay product in the high-speed region. At ultra-low voltage, C 2 MOS-Data presents the lowest energy consumption in every region excepted for very high speed applications. In order to deal with the fact that the results are not the same at nominal voltage and at ultra-low voltage, it is shown that the back biasing technique allows to dynamically reach both high-speed and low-power properties with the same architecture sizing. It means that the FDSOI technology allows a higher energy-efficiency than obtained by the sizing methodology thanks to the back biasing technique.

Next, we mention that none additional problem appears during the implementation in conventional flow, compared to hard-edge triggered flip-flops. Finally, silicon measurements of previously selected architectures in 28nm FDSOI highlight and confirm the previous conclusions. In particular, an average clock-to-output delay of 31ps has been measured for the TGPL-Clk architecture in nominal conditions.

INTRODUCTION

As seen in the previous chapter, among all the flip-flop topologies found in the literature, the explicit pulse-triggered architecture is the most promising candidate for the high-speed and low-power applications. As fundamental principle, the clock signal is connected to a pulse generator (PG) providing a pulse signal to a level-sensitive latch. The latch architecture is of fundamental importance in the flip-flop performances. Indeed, it directly gives the speed of the FF and directly impacts the sizing of the pulse generator, thus the overall energy consumption.

In order to reach an energy-efficient FF, we have to find a latch providing the required speed for a minimum amount of energy.

In this chapter, a large set of pulse-sensitive latches is compared. First, Section 2.2 exposes the design constraints of the latches for this work focusing on ULV and UWVR circuits. These constraints come from the targeted ultra-low voltage applications, the characterization method used in ASIC design, and from the use of an aggressive technology. Based on the design constraints, Section 2.2 develops and presents the choices of latches that will be compared. It is motivated by a theoretical analysis on the writing system of pulse-triggered flip-flops (pulsed-FFs). In Section 2.3, the sizing methodology of the latches is firstly presented. It is shown that the optimum ratio between the width of the NMOS and PMOS transistors (β P N ) is not the same if we target identical timing or maximized robustness, while the CMOS stage stack slightly varies the conclusion. Secondly, the complete comparison is performed at nominal and ultra-low voltages and over the whole energy-delay domain. The results of this comparison are then discussed for each supply voltage. As the results are not exactly the same at nominal and ultra-low voltages, we provide a discussion about the choice and the desired tradeoff depending on the application. Consequently, the use of a wide back biasing range possible in FDSOI technology is added to the discussion. It is shown that it allows a better tradeoff in speed and energy than by sizing methodology. The final Section 2.4 shows silicon measurements of these selected architectures which confirms the previous finding.

SELECTION OF ULTRA-LOW VOLTAGE LATCHES

As we saw in Section 1.3, flip-flop architectures are extremely varied and can be optimal for a specific application. Therefore, we have to determine some choices and design constraints in order to select relevant latches for the targeted applications of this work. After describing and motivating these constraints, the elaboration of the writing system is analysed in Section 2.2. As we will see, the conclusions lead to pulse-triggered flip-flops already presented in the previous chapter. Slight improvements in some architectures are finally proposed.

Design constraints

First of all, the target of energy-efficiency leads us to choose the static complementary MOS logic (CMOS). This logic style has been present for three decades in the industry because it provides a strong immunity to crosstalk and a lower total energy consumption thanks to the absence of short circuit path [START_REF] Veendrick | Nanometer CMOS ICs[END_REF].

Ultra-low voltage operation

The pulse-triggered flip-flops of this work have to function at ultra-low voltage (ULV) in order to provide a high energy-efficiency. At this operational mode, the on-state current is small, meaning low operational clock frequency, and varies dramatically with the environmental variations. Moreover, the leakage current becomes predominant and is even more strongly proned to environmental variations. All this leads to several design consequences.

A short circuit path during the writing time is forbidden. The process variations may lead to a strength difference between PMOS and NMOS extremely high compared to the nominal case. Therefore, designers have to increase the transistor dimensions to ensure an acceptable signal to noise margin in writing mode (SNMW), leading to an unacceptable energy overhead.

A pass-gate with only one transistor is forbidden. In some architectures working at nominal voltage, a NMOS (or a PMOS) performs both the charge and the discharge of the next node. Because of the configuration, the charge (discharge) is not complete and the node value reaches quickly V dd -V th,n (gnd+V th,p ) but the rest of the transition becomes extremely slow. For sufficiently high voltage, this value is high (low) enough compared to the threshold voltage of the next CMOS branch. But, at ultra-low voltage, the transistors would pass quickly in cut-off mode and the time needed to reach the switching threshold voltage of the next branch might be several orders of magnitude higher than standard operations.

A stack of four transistors is also forbidden. Stacking transistors decreases the speed and the robustness of the gates if the size of the transistors is not increased. Therefore, designers have to make a tradeoff between the speed-robustness and the area of the standard cells. We chose in this work a maximum stack of three as it has already been the case in other works in ULP operations [START_REF] Bol | SleepWalker: A 25-MHz 0.4-V Sub-mm 2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes[END_REF].

Finally, the flip-flops of this work will not be dual-edge-triggered. In dual-edge systems, the clock tree must be perfectly balanced, providing an equal time in the low level and the high level of the clock. Nevertheless, if the constraint of 50%-50% is relaxed, it will always be possible with explicit pulsed-FFs to adapt the latch in dual-edge mode.

Logic synthesis aspects

Even if our flip-flop comparison is a study at gate level, the objective of every digital cell is to be implemented in a complete circuit. Consequently, we have to keep in mind that the flip-flops will be characterized and then used for synthesis by CAD tools. These points lead us to set out two constraints which are not always found in the literature.

The output of the flip-flop must be the output of an inverter. Indeed, if the FF output is a node of the bistable element, the time needed to (dis)charge it, i.e. the minimum pulse time, depends on the output load. As the output load of a standard cell is only known after the synthesis placement, it might lead to two situations: (i) if the load is too large, the pulsed-FF could not be able to switch the state of its bistable element during the pulse period; (ii) if the load is too weak, the flip-flop will be overdesigned, meaning useless energy overhead. The size of this inverter will give the driving strength (or drive) of the cell and is an input of the sizing algorithm.

All of the external inputs arrive on a transistor gate. In a lot of latches proposed in the literature, the data input of the analysed flip-flops is the source/drain contact of a transistor. This directly means that there is a stack of two, at least, between the other source-drain contact of the transistor and the supplies; this might lead to several problems. First of all, is the input slope chosen when the transistor is on or off ? If it is on, it will not be the case in most of the characterization tool. If the clocked transistor is off during the input transition, the drive of the stack -when it will be on -will directly impact the time of charge or discharge and thus the timing performances of the flip-flop. But, for two identical input slopes, the stack may be very different as well as the corresponding rise and fall time. The idea is illustrated in figure 2.1 and the delay difference is quantified in Table 2.1. Moreover, the strength of the previous driving stage, or gate drive, is only known after the synthesis step and the modern synthesis tools are not able to take into account the voltage drop during the data latching to properly size the previous gate. Therefore, we forbid inputs arriving on a transmission gate but only on capacitive transistor gates which do not add stack.

Table 2.1: Computed delay difference between an ideal slope and the driving strength of the previous stage. Depending on the supply voltage, there can be a substantial different of up to 23% on the computed delay.

Configuration: 1V X1 1V X8 0.35V X1 0.35V X8 rise time 19% 1.2% 22.3% 2% fall time 18% 1.4% 23% 1.8%

Scan, reset and inverted output functionalities

Testing determines the yield of a given circuit and gives indications on how to improve it. With the complexity of modern ICs, it is impossible to have pins with direct access to all the desirable parts of the circuit. Therefore, designers use one or several scan chains as an artificial mean to access the circuit inside and show the correct behaviour of the circuit, and it is today compulsory in advanced designs [START_REF] Zyuban | Optimization of scannable latches for low energy[END_REF]. The principle of this technique is the following: scannable flip-flops are used in the functional datapath with two inputs -data in (D) and data test in (TI) -selectable by a test enable signal (TE). During the automatic Placement&Route (P&R), the outputs (Q) and the test inputs (TI) are connected to each other to form a chain of flip-flops called scan chain. If the length of the chain is N, known values of data are fetched in the circuit during N clock cycle. At the end, the state of the circuit is perfectly known, so is the expected output of the combinational logic. Thanks to that, the outputs of the chip are detected and compared to the expected outputs.

As the test represents a lot of time in the industrial process, the trend is to reach similar functional and scan frequencies. Thereby, the scan path and the D-to-Q path will be similarly sized in this work.

Processor designers intensively use the reset function in order to know precisely the initial state of the circuit. Synthesises of industrial state of the art processors, namely TI MSP430 and ARM Cortex M0, were performed and have been shown that the majority of the flip-flops is resettable and with minimum drive. Consequently, the reset function will be also added to our architecture in order to compare realistic flip-flops.

As we could see in Section 1.3, flip-flops may have a different number of stages between the input and output. It means that the direct and shorter output might also be the complementary incoming data. To compare the best performances of the different flip-flops, an inverted output is chosen if it minimizes the D-to-Q delay with the previous constraints and it is considered that the synthesis tool will handle it in the following combinational datapath. The choice is the same for negative triggering edge. Finally, let us sum up the design constraints chosen in this work before developing the latch architectures:

• Static CMOS logic,
• No short circuit path, especially during writing,

• A single transistor pass-gate is forbidden,

• A stack of four transistors is also forbidden,

• The flip-flops are single-edge-triggered,

• The output of the flip-flop must be the output of an inverter,

• The external inputs all arrive on a transistor gate,

• The flip-flops are scannable and resettable,

• An inverted output and negative triggering edge are allowed. Keeping these constraints in mind, we will develop in the next section the kind of latch that would be interesting for the targeted energy-efficient applications.

Architectures of static R-S pulsed-FFs

In this section, the architectures of the static resettable and scannable pulsetriggered flip-flops are elaborated. After motivating the choice of the bistable element structure, different possibilities of writing systems are discussed and the most promising energy-efficient ones will be kept for the comparison.

Bistable element

A static latch needs at least one bistable element. Three radically different architectures are proposed in the literature :

• The conventional cross-coupled inverters,

• The ULP latch [START_REF] Levacq | Low leakage SOI CMOS static memory cell with ultra-low power diode[END_REF][START_REF] Haine | Optimization of the area / robustness / speed trade-off in a 28 nm FDSOI latch based on ULP diodes[END_REF]

(figure 2.2) ,
• The Schmitt trigger, either original or simplified [START_REF] Kulkarni | A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM[END_REF] (figure 2.3).

The ULP latch consists in two ULP diode in series and interestingly exhibits only one logic node. As the current-voltage characteristics in the combination of two ULP diodes [START_REF] Levacq | Low leakage SOI CMOS static memory cell with ultra-low power diode[END_REF], this configuration provides two stable points (see figure 2.2c). The maximum current of an ULP diode is the drain current of a transistor with V GS = 0, as shown in figure 2.2a. Consequently at nominal voltage operation, every capacitive coupling will change the voltage value and the recovery time to reach a supply value is several orders of magnitude lower than the two cross-coupled inverters. Therefore, it would impact the driving strength of the inverted output and is thus not suitable for nominal V dd operations [START_REF] Bernard | Etude et comparaison de cellules SRAM dual-port sans assist dynamique[END_REF]. At ultra-low voltage, the leakage current of the writing system has a huge impact on the static voltage value. Indeed, if the writing system is not in ULP logic, the off-current will be in the same order of magnitude than the on-current of the ULP bistable. A careful and complex sizing study must so be performed to ensure functional operations in every environmental cases [START_REF] Haine | Optimization of the area / robustness / speed trade-off in a 28 nm FDSOI latch based on ULP diodes[END_REF].

The simplified Schmitt trigger was proposed in [START_REF] Kulkarni | A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM[END_REF] to increase the yield of the SRAM cells to the detriment of the area. As the read operation is the first cause of failure of 6-transistor SRAM cell, [START_REF] Kulkarni | A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM[END_REF] modifies the bistable and increases the read signal to noise margin (RSNM) thanks to a half-Schmitt trigger in the push-down system of the bitcell.

Nevertheless, the topology of static CMOS flip-flop is not subject to any RSNM because the reading is performed without any perturbation in the bistable

Pulse Pulse Q Q Q Pulse Q towards D (a) Breaking feedback mechanism in a latch. CLK CLK D Q Adaptive coupling (b)
The adaptive coupling pulsed latch (ACPL) with input data as breaking signal (inspired by [START_REF] Teh | A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS[END_REF]). element. This technique is so not relevant in our case. In conclusion, the conventional cross-coupled inverters will be used as bistable element of our latch.

Breaking feedback mechanism

As the conventional bistable element is selected, the conventional technique of breaking bistable feedback (figure 2.4a) can be used to fulfil the constraint of none short circuit path. Let us note the signal breaking the feedback may not only be the clock or pulse signal. Generally speaking, it is any signal which enables the pull-up or pull-down system. A feedback mechanism using the input data instead of the clock signal was proposed in [START_REF] Teh | A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS[END_REF]. The advantage of increasing the data load instead of the clock load is that the data activity is usually much lower than the clock activity (namely 100%), leading thus to a reduced energy consumption. Nevertheless, the evolution of the data input during the whole clock cycle is basically random. Thus, if the data value changes slightly after the triggering clock edge, a node of the bistable element becomes floating and we get every drawback of dynamic logic. That is why only the master latch uses this technique in [START_REF] Teh | A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS[END_REF] and why the hypothetical adaptive coupling pulsed latch (see figure 2.4b) will be discarded from the comparison of this work.

Consequently, the writing system will be connected to only one node of the bistable element and, by constraints, at least two transistors will be used to perform both the pull-up and pull-down systems.

Writing system

Generally speaking, the writing system has to pull down the output value of the flip-flop Q when

P ulse = 1 & D = 0 & Q prev = 1 (2.1)
and has to pull up when

P ulse = 1 & D = 1 & Q prev = 0 (2.2)
This logic equation can be implemented with a stack of three transistors having respectively P ulse, D, and Q prev on their gate. But, the use of the third transistor is useless because the information of Q prev is already contained in the node of the bistable. Thus, a stack of two transistors with P ulse and D on their gate is sufficient (figure 2.5a). If the D gated transistor is directly connected to the bistable node and not to the supply nodes, a glitch of the input during the clock cycle will charge or discharge an intermediate node of the stack. As it will result in an useless energy consumption, the P ulse gated transistors must be directly connected to the bistable and the D gated to the supply voltage. The drain of the P ulse gated PMOS and NMOS can be connected to form a pass-gate (TGPL configuration) or let separated (C 2 MOS configuration).

Let us analyse the case where only one PMOS and/or one NMOS achieve(s) the pull-down or pull-up system(s).

In both cases, the transistor has to be off when P ulse = 0 and becomes in on-state only if a new value must be written, meaning that the signal on the gate brings the information. For example, a stack of two PMOS, with P ulse and D, can be connected to a NMOS, as drawn in black in figure 2.5b. When P ulse = 1 & D = 1, the PMOS stack charges the intermediate node, the NMOS becomes on and discharges to ground the internal node of the bistable element containing the output information (Q bistable ). To avoid a discharge of the intermediate node when Q bistable is already at 0, and thus to increase the energy-efficiency, the preceding stack may contain the Q prev information thanks to a third transistor as illustrated in 2.5b. Let us notice that this configuration is the complementary of the CDFF architecture presented in [START_REF] Zhao | High-Performance and Low-Power Conditional Discharge Flip-Flop[END_REF]. On the other hand, the pull down system is a stack of two NMOS directly connected to the bistable element. It needs the complement input D but avoids stacking three PMOS known as the slowest transistor configuration in this technology (for identical threshold voltages).

Following these ideas, another possibility to avoid a stack of three transistors, is a stack of two transistors commanding the last stage connected to the bistable and containing the entire information P ulse, D, and Q prev , as shown in figure 2.5c. The question is: in which order should they be ? If the gate signals of this stack are Q prev and a signal commanded by P ulse and D, it will increase the D-to-Q delay and produce switching energy overhead in the first stage when D = Q prev . If the gate signals of this stack are P ulse and a signal commanded by Q prev and D, it will increase the D-to-Q delay and produce switching energy overhead in the first stage if D changes during the clock signal. If the gate signals of this stack are D and a signal commanded by Q prev and P ulse, the D-to-Q path is not augmented and there is no switching energy overhead in any stage. That is why it is the choice of [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF]. As a XOR gate does not bring the information of one or zero but only compared D and Q prev signals, [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF] uses pseudo-NAND and pseudo-NOR gates. The pseudo-NOR gate needs a stack of three PMOS but the timing performances are not under concern in the pulse generation.

A four stages configuration is basically the CP 3 L configuration without the Q prev signal in the pulse generator, which would lead to an useless energy consumption.

After the triggering edge, the bistable element must see the writing system as a high impedance. If there is only one transistor in the pull-up or pull-down system, its gate voltage must come back to its initial value after writing. This precharge mechanism can be implemented in different ways. An extended and applied discussion will be performed in Annex A with the CDFF architecture.

Scan and reset functionalities

As a result from the previous sections, the architectures adopted for the comparison are the transmission gate pulsed latch (TGPL), the complementary CMOS (C 2 MOS), the conditional discharge flip-flop (CDFF) and the conditional pushpull pulsed latch (CP 3 L).

For pulse-triggered flip-flops, the reset function is easily implemented by adding two transistors in the bistable element, one to pull a node to gnd or V dd and one to break the feedback. At least one other transistor must be added in the writing system to ensure no short current path at triggering clock edge.

The scan functionality is implemented with minimum additional transistors, the size of which is the same as the functional data path to ensure a scan test in every operating condition of the circuit (see section 2.3.1).

For TGPL and C 2 MOS pulsed-FFs, there are two ways to elaborate the scan function (figures 2.6 and 2.7): either the data stack is enlarged then duplicated, having so a basic CMOS multiplexer with the test enable signal (TE) as command signal and D and TI as multiplexed inputs, or both data and clock stack are duplicated, presenting two AND gates in the pulse generator but a lower stack in the latch. Let us notice that the TI-to-Q path of the -Clk architectures can be connected by the other node of the bistable element (Q int ). It would reduce the junction capacitance at the intermediate node and thus decrease the D-to-Q delay. Nevertheless, in this configuration, the TI-to-Q path presents one additional stage compared to the D-to-Q path. If we want to perform scan test at ultra-low voltage, the delay generated in the pulse generator has to be ensured large enough for this worst case and we will see in the next chapter that guaranteeing a sufficient delay at ULV is a key bottleneck for pulsed-FFs. As we consider that scan test must be available at ULV, this option is discarded in this work.

For CDFF architecture (figure 2.8), the data stack may not be enlarged because a stack of four is forbidden. Thus, the stack must be duplicated as well as the precharge part.

The CP 3 L architecture on figure 2.9 is the -Data version obtained in the same way of TGPL and C 2 MOS architectures. The CP 3 L-Clk architecture was discarded because presenting a too important amount of transistors.

The pulse generators of each latch have the same sizing strategy, i.e. achieving an FO3 slope on the clocked transistors. It allows us to take into account the real cost of an increase in speed for the energy consumption.

Finally, the schematic of each selected static resettable and scannable pulsetriggered flip-flop architectures are shown in figures 2.6 to 2.9. Let us notice that one of the differences between these architectures is the number of stages in the D-to-Q path. Without considering the output inverter, we can differentiate the one-stage (TGPL and C 2 MOS) and two-stages (CDFF and CP 3 L) topologies.

R W PG W PG W 1 W 1 W 2 W 2 W 2 W 2 β PN W 2 β PN W 2 β PN W 2 β PN W 2
For TGPL W drive

W PG W PG W PG W PG W 1 W 1 W 1 W 1 W 2 W 2 β PN W 2 β PN W 2
For TGPL W drive

Q int Q int Q int Q int W PG W PG W PG W PG W 1 W 1 W 1 W 1 W 1 W 1 W 2 W 2 W 2 W 2 W 2
F CP F CP R S N R N R N S N R N S N R R Q D W 1 β PN W 2 β PN W 2 β PN W 2 W 2 W 2 W 2 β PN W 1 W PG W PG W drive

COMPARISON AND RESULTS

This section starts by explaining the sizing methodology used in this work, focusing on the β P N ratio of transistors and the concept of energy-efficient curves (EECs). Then, the results of the comparison of all FFs are shown at nominal (1V) and optimal energy (0.35V) voltage. The conclusion of the comparison is then discussed and the C 2 MOS-data and TGPL-Clk topologies are pointed out.

Sizing methodology

The proper ratio β P N between the gate width of the PMOS (W g,p ) and the gate width of the NMOS (W g,n ) in a CMOS stage, depends on the design target. Generally speaking, the optimum β P N is not the same if equal rise and fall delays or transition times are on purpose or if the energy or robustness is under consideration [11,[START_REF] Sproull | Logical Effort: Designing Fast CMOS Circuits[END_REF][START_REF] Alioto | Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Standard Cells[END_REF][START_REF] Keane | Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing[END_REF]. Moreover, the stack is another parameter for the sizing.

For circuits working at nominal voltage, the timing properties are of primary importance and equal rise and fall times are targeted. For circuits working at ultra-low voltage, the ratio between the on-and off-current in a CMOS stage is the main consideration as it will be shown in Section 3.4. But the choice is more difficult in UWVR circuits where the logic works both at nominal voltage and ULV. Spice simulation have been performed at 1V and 0.35V for a stack of one and two transistors and the optimum β P N ratio for timing consideration and robustness are shown in Table 2

I of f,sat ) 1 1.6 0.38 2 2 0.37
In FDSOI 28nm technology with LVT feature and nominal back biasing (vdds=gnds=0V), the optimal β P N ratio for a timing match is about 1.6 for a stack of 1 and 2 for a stack of 2, both at 1V and 0.35V. The fact that results are identical for 1V and 0.35V, is particular to the 28nm FDSOI technology. The subthreshold current per unit width is actually higher for the PMOS transistor than for the NMOS in this technology. It is explained by the fact that PMOS have a lower threshold voltage to compensate the loss of mobility at nominal voltage. And indeed, despite their higher leakage current, PMOSs need a larger W g to provide an identical timing at nominal voltage.

Those observations may lead to a lot of discussions about the proper sizing to use in a circuit working both at nominal and near-or subthreshold voltage. In this work, we chose to target identical timing performances at nominal voltage and assume that the robustness problem at ultra-low voltage can be handled in FDSOI thanks to the proper choice of back bias values (see Section 3.4).

Energy-efficient curves

FF architectures can be thoroughly and fairly compared by extracting the energy-efficient curve (EEC) in the energy-delay (E -D) space [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF]. This curve is the set of design points showing minimum energy (delay) for a given delay (energy) [START_REF] Zyuban | A Unified methodology for resolving powerperformance tradeoffs at the microarchitectural and circuit levels[END_REF]. From the theory, EEC has a hyperbolic shape and allows the understanding of the E -D tradeoff of FF in both high-speed and low-energy designs. Our sizing optimization methodology is largely inspired from [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF] and the details of the testbench can be found in Annex B. Therefore only the outlines are presented in this section.

Only the gate width of the transistors in the D-to-Q path can modify the speed and thus the energy-delay tradeoff. Thereby, those gate widths -called W k (k = 1, 2, ...) in figures 2.6, 2.7, 2.8, and 2.9 -are the main variables for the transistor sizing algorithm. Once the sizing variable w k are chosen, it is possible to apply an optimization algorithm to extract the optimum w k for each point of the EEC. As already mentioned, the EEC is made up of the design points minimizing the E i D j figures of merit (FOMs). The exponents i and j are predetermined integers balancing the contributions and a particular E i D j FOM is a choice of the designer on the energy and timing characteristics of the circuit. In the neighbourhood of the design minimizing a given E i D j FOM, a j% performance increase is traded for a i% energy increment and vice versa [START_REF] Consoli | General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space[END_REF]. Thus, the designers have to choose which figure of merit is targeted for their application.

E 2 D 1 1W g,min 6 1.5 E 1 D 1 2W g,min 4 2 E 1 D 2 3W g,min 3
3 †: Logically for realistic designs, the higher the gate width is, the lower the delay and the higher the energy are.

For a given set of W k which minimizes a particular E i D j FOM, it is associated a propagation delay and an energy consumption of the flip-flop. Hence, each design point can be plotted in the energy-delay space (E -D) as represented in Figure 2.10: Extraction of energy-efficient curve (EEC) [START_REF] Consoli | General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space[END_REF]: from the corresponding energy consumptions (E) and propagation delays (D) of the design points given by the W k , we plot them in the E -D space and interpolate those points by a hyperbole. figure 2.10. As the theory also tells us that the EEC has an hyperbolic shape, it is possible to select a discrete set of the E i D j FOMs and interpolating them to extract the intermediate points. This allows to get the energy-efficient curve without applying an optimization algorithm for all the EEC points, which would take a infinite amount of time.

In this work, we chose to consider the FOMs ED j and E i D, for i, j = 1...5, because they cover a very wide range of applications. After having determined the nine sets of W k which provide an optimal design point for each FOM, we got nine couples of energy consumption and delay propagation which correspond to the nine design points. Then, we plot those couples in the energy-delay space, as in figure 2.10, and we interpolate this set of nine points by a hyperbole. The obtained hyperbolic curve is the EEC of a given flip-flop and represents the corresponding E and D of the design points minimizing all the E i D j FOMs. In other words, this curve shows us what the cost in energy for a given propagation delay is. Thanks to the EECs, we are able to fairly compare the FF architectures over a wide range of FOMs, thus applications.

In order to provide technology independent results, delay and energy are normalized respectively by :

• D 0 the propagation delay of a Fan-out 4 (FO4) inverters chain,

• E 0 the energy dissipated during a complete switching cycle of a minimum sized symmetrical inverter without output load. Let us notice that the most significant difference with the testbench of [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF] is the use of a novel setup time metric dedicated to pulse-triggered flip-flop [START_REF] Bernard | An efficient metric of setup time for pulsed flip-flops based on output transition time[END_REF]. This metric is focused on the output transition of the flip-flop during a sweep of the input, instead of the Clk-to-Q or D-to-Q delay as it is the case in the literature and the industrial characterization tools. We showed that, for pulsed-FFs, it provides the most timing-efficient setup time considering the whole pipelined CPU. Finally, let us remind that the propagation delay of FF is defined at the D-to-Q time when the input data D arrives at the setup time, defined as a variation of 10% of the output transition time (see [START_REF] Bernard | An efficient metric of setup time for pulsed flip-flops based on output transition time[END_REF] for more details).

Nominal voltage operation

The energy-efficient curve of all the scannable and resettable pulsed-FFs are reported in figure 2.11, for a nominal supply voltage and a minimum driving strength (X1). The temperature is 70 • C, the data switching activity factor (α sw ) is 15% and the clock period (T clk ) is 40 times the propagation delay of FO4 inverters in the same environmental conditions. All those values are typical for the targeted applications and do not heavily impact the outcomes of the comparison [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF].

We see that the *-Data architectures provide the lowest minimum energy consumption, with C 2 MOS slightly better than TGPL. During a C 2 MOS transition, the intermediate nodes of tristate input inverters are not completely charged or discharged, because the gate to source voltage of the first transistor in the stack decreases gradually below the threshold voltage. Therefore, C 2 MOS architecture saves the dynamic energy of fully charging and discharging the junction capacitances proportional to W 2 (see figure 2.6). This lower dynamic consumption allows C 2 MOS architectures to get higher W k , so higher speed, for the same energy. Nevertheless, C 2 MOS are finally outperformed by TGPL topologies in high-speed region, since the two transistors of the transmission gate help to improve the transition speed. *-Clk architectures provide a better E -D tradeoff in the high-speed region, due to their smaller stack in the input stage. Let us notice that two-stages structures (CP 3 L and CDFF) presents a poorer tradeoff on the overall E -D space.

Ultra-low voltage operation

The EECs of all the pulsed-FFs, for a supply voltage of 0.35V (minimum energy per operation in 28nm FDSOI technology) and a minimum driving strength, are reported in figure 2.12. Here the operating temperature is 25 • C because the selfheating of ultra-low power circuits is almost negligible and those circuits normaly work in ambient temperature.

We see that the C 2 MOS-Data architecture is the most energy-efficient in almost the whole E -D domain, excepted in very high-speed region. Thanks to the stack, this architecture exhibits a very low leakage current which becomes extremely significant in ULV operation and so dramatically impacts the energy consumption.

At ULV, TGPL architectures are less energy-efficient over the whole E -D space. While they are keeping a higher leakage current as C 2 MOS, their benefit in timing is jeopardized by the sub-threshold regime. Indeed, during a transition, the V GS of one of the two transistors of the transmission gate progressively decreases. As it exponentially depends on the V GS in sub-threshold domain, the drain current of one of the two transistors of the transmission gate is negligible a short time after the beginning of the transition. It leads to a C 2 MOS-like topology, with higher diffusion capacitances in the D-to-Q path.

Again, the two-stages architectures are less energy-efficient than the one-stage ones in every region of the E -D domain. The fact that CDFF and especially CP 3 L structures present the worst energy-delay products (EDP), in opposition to the results in [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF], shows that the reset and particularly the scan functionalities may change the conclusion of comparisons. Therefore, it proves that the facility of implementing the scan function must be taken into account in the choice of FF architectures.

Back-biasing technique

In the previous section, we saw that C 2 MOS-Data architecture is the most energy-efficient topology for energy-efficient and low-power applications at ultralow voltage and nominal voltage. On the other hand, TGPL-Clk exhibits the lowest ED n products for n � 2 and is thus dedicated to high-speed applications.

These conclusions apply to the 28nm FDSOI technology but, generally speaking, there might be more than two optimal architectures for a large set of E i D j FOM. If an application needs both a high performance on critical path and a low power consumption for the circuit, the selected architecture needs to be designed with all possible sizing to reach a pareto optimum-like energy-delay tradeoff on the whole circuit. Nevertheless, it means that the architectures must be properly sized for each figure of merit targeted and all characterized in each PVT conditions for all the drives provided in the library. All this may significantly increase the design and computation time.

This tradeoff between design time and energy-efficiency can be almost fully alleviated thanks to the FDSOI technology. Figures 2. [START_REF] Pelgrom | Different faces of variability[END_REF] performances in the E -D space of the C 2 MOS-Data architecture (minimum ED sizing) on which a wide symmetrical back biasing is applied. Figure 2.13 also shows the TGPL-Clk architecture with minimum ED 2 sizing, as it is the most energy-efficient in high-speed region. As we can see, the delay in the high-speed region is lower for the same energy than the delay obtained by the sizing methodology. Similarly in the low-power region, the energy consumption is lower for the same delay than the energy consumed by the minimum sizing of transistor. At ultra-low supply voltage (figure 2.14), the impact of the threshold voltage on the on-current is almost as strong as on the off-current. Therefore, an increase (decrease) in delay implies a decrease (increase) for the leakage current. The leakage energy is this leakage current integrated over the clock period that is related to the gates delay. As the transistor dimensions and the supply voltage remain the same, the dynamic energy variation is only due to short-circuit current. Consequently, the energy per operation does not vary that much in the low-power region, i.e. for reverse body bias, and remains quite the same as the energy of the minimum ED sizing architecture. On the other hand, the relative delay gain is higher at ULV than at nominal voltage because the delay, essentially depending on the on-current, varies much more with the threshold voltage shift. All that clearly shows that we can modulate the energy-delay performances of flip-flops more efficiently than the sizing methodology and also more flexibly because it is not built in hardware and can be dynamically modified during the circuit operation.

IMPLEMENTATION IN DIGITAL FLOW AND SILICON MEASUREMENTS

As we saw in figures 2. our first results were that the TGPL-Data architecture was more energy-efficient than the C 2 MOS-Data, i.e. with a lower E 1 D 1 product.

That is why we selected the TGPL-Data architecture to be implemented on silicon in the high-speed DSP FRISBEE [START_REF] Wilson | A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking[END_REF]. The TGPL-Data post-layout netlist was characterized by the same automatic tools used for master-slave topologies. To obtain a proper hold time value, we have to set some simulation variables to ensure that the tool does not allow a glitch during the pulse window. Indeed, due to the soft-edge property of the pulsed-FF, it is possible to trigger a right final output value after having seen a glitch at the output. But if this glitch propagates in the paths after the flip-flop, it will lead to an additional energy consumption in the combinational logic.

The setup time of soft-edge FF is obtained by the same way as hard-edge triggered flip-flop, excepted that we showed in [START_REF] Bernard | An efficient metric of setup time for pulsed flip-flops based on output transition time[END_REF] that the setup time metric is not optimal. For FRISBEE, the criteria to determine the setup time was an increase of the Clk-to-Q delay of 10% compared to the nominal case. In [START_REF] Bernard | An efficient metric of setup time for pulsed flip-flops based on output transition time[END_REF], we showed that this metric, as well as the minimum D-to-Q delay, does not give the limit beyond which the performance of the flip-flop is degraded and the reliability is endangered [START_REF] Stojanovic | A Unified Approach in the Analysis of Latches and Flip-Flops for Low-Power Systems[END_REF]. A setup time metric based on the output transition time would provide all the timing performances of the TGPL-Data architecture. Measured delays from 0.3V to 1V in nominal case (VDDS=GNDS=0V). Clk-to-Q delay is lower for TGPL-Data than for TGPL-Clk, contrary to the D-to-Q delay (T • = 80 • C).

After having obtained the timing characteristics of our pulsed-FF, synthesis and Place&Route were performed without any serious problem for the timing closure. After the signoff verification, the chip was sent in fabrication and the measured performances have expectantly outperformed the state of the art [START_REF] Wilson | A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking[END_REF].

In parallel, a test circuit was laid out and fabricated to study more precisely the performances of the pulsed-FFs alone. Hence, the following of this section presents post-layout simulations and silicon measurements of TGPL-Data and TGPL-Clk architectures and compares them to the conventional master-slave flip-flop.

Silicon measurements

This section presents delays measured on silicon, exhibited by different flipflops architectures: TGPL-Data with minimum EDP, TGPL-Clk with minimum ED 2 P, and a conventional master-slave (MS) coming from an industrial standardcell library. The mean and standard deviation of the delay are extracted from the measurements of 63 chips uniformly distributed on the wafer.

Figure 2.15 represents the ±3σ dispersion, assuming a Gaussian distribution above 0.5V and a lognormal distribution below, for one architecture at each supply voltage V dd . This figure shows that the model used for the simulation is very accurate because the delay computed in the five process corners at each V dd effectively lays in the range of delay coming from measurement. Similarly, it also proved that our measurements are consistent.

We clearly see in figure 2.15 the exponential behaviour of the delay when we go towards the subthreshold regime, i.e. an linear evolution in logarithm scale. On the other side, for the highest V dd values, we see a larger delay dispersion (σ) relatively to the average (µ). This is explained by the accuracy of our measuring equipment. Indeed, as the speed increases with V dd , the FFs delay reaches the precision limit of our tester. In other words, the delay dispersion due to the test accuracy becomes identical to the real FF delay dispersion. Consequently, the measured σ /µ ratio increases at nominal voltage.

Figure 2.16 compares the measured Clk-to-Q delays of the three selected architectures for a wide range of supply voltage. To remind, the dots represent the average delay computed over 63 chips. As predicted in simulations, the Clk-to-Q delay of the TGPL-Data is faster than the Clk-to-Q delay of the TGPL-Clk. Nevertheless, simulations also showed that the D-to-Q delay, which is the principal timing parameter, is lower for TGPL-Clk than for TGPL-Data. Measurement results showed that this trend is effectively observed but, unfortunately, the measures of the minimum D-to-Q delay are not consistent because of the inaccuracy of the setup time measurement. As quantitative results, TGPL-Clk shows an average Clk-to-Q delay of 31ps at 1V and 80 • C, without FBB. The above results are for flip-flops in nominal back biasing conditions, namely VDDS = GNDS = 0V. Figure 2.17 represents the evolution of the delay with the back bias for the TGPL-Clk architecture at super-threshold supply. As the flipflops use LVT transistors, only a strong forward back bias is available. Playing with the back voltages allows to cover a wide range of performance since the maximum delay is 2.5 times higher than the minimum delay. This trend is also visible for the two other architectures. As a reminder, changing the back bias does not affect the dynamic energy.

The back biasing technique has an even deeper impact on the performances when the supply voltage is near the threshold voltage. We can see in figure see that, for a reverse body bias (gnds = -0.5V), the spread of the distribution is subthreshold-like, while for a forward body bias (gnds = 1V), the range of variation becomes closer than the variations at 0.5V. Finally, let us notice that gnds, the NMOS back bias, impacts more on the variation of the delay than the vdds, the PMOS back bias (figures 2.18a and 2.18d).

Finally, Table 2.4 compares the energy performances and efficiency of the three architectures by post-layout simulations. As we can see, the TGPL's architectures, composed of one latch and one pulse generator, consume a bit more than the master-slave architecture. It might surprise since pulse-triggered architectures have only one latch instead of two for master-slave. However, as it will be explained more precisely in Chapter 4, the pulse generator is actually the largest part of energy consumption. Nevertheless, TGPL's architectures are more energy-efficient as soon as we take the delay into consideration. More precisely, pulsed-FFs outperform MS topology for each E i D j figures of merit with j � 1 and i � 3, for all supply voltages between 0.3V and 1V and all activity factors (figure 2.19). Let us notice from figure 2.19, that the minimum energy point is effectively at 0.35V and the minimum EDP around 0.7V.

CONCLUSION

This chapter presented our approach to choose the most energy-efficient pulsetriggered flip-flop architecture for our UWVR and ULP applications. First, the corresponding design constraints were exposed and motivated. Then, a theoretical analysis was performed to select the most suitable architectures based on It turned out that the C 2 MOS architecture is the most energy-efficient topology in the low power region at ultra-low voltage and at nominal voltage while the TGPL-Clk exhibits the lowest ED n�2 products in the high-speed region in both voltages. These conclusions showed that adding reset and scan functionalities may effectively change the result of the comparison. In particular, the scannable and resettable CP 3 L architecture exhibits a higher energy-delay product than the corresponding TGPL and C 2 MOS topologies. As different architectures might provide the optimum sizing point for different figures of merit, we highlighted that the wide back biasing range offered by the FDSOI technology allows to almost totally overcome this tradeoff. It has been shown that the flip-flop energy-delay characteristics get better performances with the back biasing technique than with the sizing methodology. In other words, a forward back bias provides a lower delay for the same energy than the architecture sized to reach the very high speed (ED 5 ) figures of merit ; a reverse back bias provides a lower energy dissipation for the same delay than the architecture sized to reach the low power (E 5 D) figures of merit. Furthermore, the back biasing technique allows to change dynamically the energy-delay performances of flip-flop, on the contrary of a sizing methodology which provides fixed hardware configurations. We are thus allowed to contend that the FDSOI technology is khtêma es aeí.

The last section of this chapter presents silicon measurements performed on the most efficient TGPL architectures. First, it is mentioned that the implementation in the chip FRISBEE [START_REF] Wilson | A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking[END_REF] demonstrated that the pulsed-FFs and their soft-edge property do not raise any additional problem at characterization and timing closure steps. Next, measures confirmed the expected low delay of pulsed-FFs compared to master-slave for a wide range of supply voltage (0.3V -→ 1V ) and a relatively high number of chips [START_REF] Sproull | Logical Effort: Designing Fast CMOS Circuits[END_REF]. Results of back biasing technique also showed the great modulation of performances that is achievable with the same hardware sized architecture. The number of tested chips allowed us to exhibit the physical distribution of the delay, showing the sub-or super-threshold regime.

Post-layout simulations showed the energy-efficiency of the TGPL architectures, the EDP of which is unconditionally lower than that of a master-slave topology.

Thanks to these performances, our TGPL architectures are already dedicated to cover a wide range of application, especially where the energy-efficiency and the speed are both of primary importance, like in UWVR circuits. Nevertheless, as shown in Table 2.4, the average energy consumption per cycle and the area are lower for the conventional master-slave flip-flop. Consequently, the masterslave architecture is still commonly used in very ultra-low power applications where the power dissipation is the main target to reduce and the robustness is of primary importance. The next chapter explains how to guarantee the robustness of pulse-triggered flip-flops at ultra-low voltage thanks to the use of the currentstarved technique in the delay generator. Later in Chapter 4, the study about the pulse generator will show how the pulsed-FF architectures can finally provide a lower energy consumption and area than master-slave flip-flops.

Abstract

After the study of scannable and resettable latches in the energy-delay domain, this chapter analyses the pulse generator with other figures of merit. Firstly, the problems of the pulsed-FFs occurring at ultra-low voltage are exposed and illustrated. It is shown that, so far, designers have to make a tradeoff between the robustness of the pulsed-FF and its energy budget.

Then, the second section presents and analyses the current-starved (CS) delay generator (DG) which allows to largely avoid the robustness/energy tradeoff. It is shown that the pulse width guaranteeing the correct functionality of the FF, can be modulated without significant increase in the energy dissipation.

Afterwards, a comparison with other delay generators of the literature shows that the current-starved and the conventional DG are the most energy-efficient. Then, post-layout simulations in extreme environmental conditions prove the higher robustness achieved by our delay generator compared to the conventional DG. Therefore, it demonstrates that the current-starved delay generator is the best architecture, regarding the three figures of merit of the delay generators.

The fourth section analyses the results of silicon measurements. First, we analyse the effects of the back biasing technique on the robustness and show an optimum couple (vdds,gnds) for the yield. Then, the computation of the average yield exhibits the robustness improvement due to the current-starved architecture. Thanks to our proposed DG, an identical yield is achieved at a supply voltage 45mV lower -at ULV -than without the CS technique.

The last section shows how to efficiently add reset and enable functionalities in the pulse generator. As a result, these additional functionalities lead to an increase of 9.7% in the energy-delay product (EDP), while the EDP of the master-slave topology increases by 64%.

INTRODUCTION

As a reminder, pulse-triggered flip-flops (pulsed-FFs) are made of one latch open during a short period following the triggering clock edge. This period is physically determined by a pulse signal, activating the latch and generated by a pulse generator (PG). The width of this pulse signal is fixed by the delay between the clock and the output of the delay generator (DG) included in the pulse generator (figure 3.1a).

At ultra-low voltage where the impact of local variations is predominant, both the generated delay and the data-to-output (D-to-Q) delay vary significantly from one pulsed-FF to another on the overall circuit. But, with a slow D-to-Q path in the pulsed-FF, the pulse signal can be too narrow to permit the pulsed-FF to latch the data. A basic solution given to designers is to add stages in the delay chain of the pulse generator (figure 3.1a). Nevertheless, it dramatically increases the hold time and thus decreases the internal race immunity (IRI) [START_REF] Oklobdzija | Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment[END_REF] of the pulsed-FF. The IRI can be evaluated regarding the maximum pulse width achieved by the PG submitted to local variation. If it leads to a hold time much larger than the mean D-to-Q delay, many delay buffers will be inserted in the short paths. Therefore, an energy overhead is paid twice for inserting additional inverters in the PG, and also delay buffers in short paths in order to fix the hold time violations.

In summary, the pulse window must be large enough to guarantee the correct functionality of the pulsed-FF, and as small as possible to avoid hold time penalties. Consequently, the figures of merit (FOMs) for the pulse generation are

• Minimum delay regarding local variations (µ -3σ in this work)

• Maximum delay (µ + 3σ) or delay dispersion

• Energy consumption

As shown in figure 3.1b, there is a clear tradeoff between the robustness of pulsed-FFs and the energy consumption. To overcome this drawback, we propose a new pulse generator architecture for ultra-low-voltage applications [START_REF] Bernard | A Robust and Energy Efficient Pulse Generator for Ultra-Wide Voltage Range Operations[END_REF]. It is shown that, for an area penalty of three fingers, the robustness is greatly improved compared to the conventional DG used in literature, while the delay spread remains relatively close and the energy consumption is even lower [START_REF] Bernard | A Robust and Energy Efficient Pulse Generator for Ultra-Wide Voltage Range Operations[END_REF].

This chapter is structured as follows. Section 3.2 presents the proposed pulse generator architecture and studies the sizing compared to the three figures of merit. Section 3.3 compares the energetic performances and robustness of a selected sizing of our DG with other architectures. From this comparison, it is shown that the conventional DG and the proposed one are the best candidates for energy-efficient circuits. Then, Section 3.3.1 compares these two pulse generators in post-layout simulations, and exhibits the gain of robustness due to our DG. Afterwards, Section 3.4 studies the minimum operating supply voltage of our FF thanks to silicon measurements. Finally, Section 3.5 shows how adding reset and enable functionalities can be efficiently performed by modifying the pulse generator.

FOM definition

To evaluate the three figures of merit of the delay generators, we use the same testbench as mentionned in the previous chapter, where the slope is adapted to PVT conditions (the temperature range for our ultra-low-voltage design is from -40 • to 85 • ) and the output load is the clocked transistors of the TGPL-Data architecture with minimum EDP.

The generated delay, the key parameter for the width of the pulse, is defined by the delay between the rising edge of the clock and the falling edge of the delayed clock signal (CLK), at 50% of the supply voltage V dd . The energy is measured by integrating the supply current over the overall clock period, which is set to the typical logic depth of energy-efficient circuit (40 FO4 delays [67]). For both energy and delay, the mean (µ) and the standard deviation (σ) of the distribution are extracted from 10000 Monte-Carlo runs. As the delay follows a lognormal distribution in the subthreshold regime [START_REF] Hanson | Analysis and mitigation of variability in subthreshold design[END_REF], the statistical parameters are calculated as

µ = ln(M ean(T del )) - 1 2 ln(1 + StdDev(T del ) 2 M ean(T del ) 2 ) σ = � ln(1 + StdDev(T del ) 2 M ean(T del ) 2 )
and finally T del,3σ = e µ+3σ

Simulations showed that the energy (dynamic and static together) gets a distribution significantly closer to the normal form than to the lognormal. Thereby, µ and σ are extracted directly from simulations.

As in chapter 2, in order to provide technology independent results, delay and energy are normalized respectively by [START_REF] Consoli | General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space[END_REF] :

• D 0 , the delay of a FO4 inverters chain,

• E 0 , the energy dissipation during a complete switching cycling of a minimum sized symetrical inverter without output load.

CURRENT-STARVED DELAY GENERATOR

Our proposed delay generator architecture is represented in figure 3.2.

The delay generator is a chain of three inverters composed of minimum sized transistors with their source contact connected to two always-on transistors -one PMOS for the pull-up system and one NMOS for the pull-down system. This DG architecture is thus similar to the current-starved ring oscillator architecture in [START_REF] Zhang | A low variation GHz ring oscillator with additionbased current source[END_REF]. The size of these current-starving (CS) transistors are called W CS and L CS .

The idea contained in this architecture is illustrated in figure 3.3. As we have seen, additional stages are placed in the delay path to increase the minimum generated delay but lead to a wider delay window because of the spread of the generated delay. To alleviate this drawback, our current-starved delay generator architecture exhibits only three stages in the delay path, i.e. where CMOS stages are switching during the pulse window, but increases the average generated delay thanks to the CS transistors. As these always-on transistors are not in the delay path, they do not impact (in first approximation) the spread of the generated delay. Hence, this CS architecture can be seen as a translation without expansion of the delay window in the time line. This translation without expansion is the key point to guarantee a sufficient robustness without energy overhead. Figures 3.4a and 3.4b show the evolution of minimum and maximum delays, as well as energy consumption, with W CS and L CS identical for NMOS and PMOS. As expected, a larger gate length provides a lower drain current and thus higher minimum delay. The gate width can be simultaneously increased, in order to reach the same minimum delay with a lower delay dispersion (figure 3 on the dynamic energy, the size of current-starving transistors only impacts the leakage energy. As the inverters chain switches at each clock cycle, the switching activity is predominant, and thus the overall energy does not vary as much as delays with gate dimensions. (figure 3.4b).

Gnd

.4b). As the gate capacitance of the always-on transistors has no repercussion

Let us insist on the fact that the sizes of the current-starving transistors are really powerful and straightforward degrees of freedom. Designers can modulate easily the dimensions of these transistors and reach the desired delay dispersion without impacting the energy consumption.

From this architecture, it directly follows two variants, with only one currentstarving transistor (NMOS or PMOS). Figure 3.5 shows that only-NMOS architecture provides a lower delay spread than the only-PMOS one, while both transistors version always provides the lowest dispersion at the same sizes, at the expense of an additional transistor. The energy is not shown because it stays quite the same for the three architectures.

Finally, let us notice that this technique can easily be transposed to dual-edge pulse generators which use a chain of inverters ( [START_REF] Zhao | Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop[END_REF][START_REF] Ghadiri | Dual-Edge Triggered Static Pulsed Flip-Flops[END_REF]).

DELAY GENERATORS COMPARISON

Several techniques and architectures of delay generators (figure 3.6) are proposed to designers to increase the minimum delay :

• 3 (the conventional DG), 5 or 7 minimum sized inverters connected in series,

• 1, 2 or 3 inverters with a gate length increase, also called poly bias (PB),

• 1, 2 or 3 half Schmitt triggers (hST) in the delay path for positive triggering clock edge, • the insertion of a pass-gate after the second inverter, as proposed in [START_REF] Lin | A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS[END_REF].

0
Delay generator proposed in [START_REF] Su | A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder[END_REF] was discarded because the driving current of the transistors, which are connected to supplies, is, at low voltage, several orders of magnitude lower than the nominal current, leading thus to a generated delay extremely higher than the typical D-to-Q time at the same supply voltage. We have chosen a particular sizing of the current-starved DG, namely W CS = 150nm and L CS = 38nm (surrounded in figure 3.4a and 3.4b), to perform the comparison. 3.7 compares the current-starved DG with the conventional DG and its variants: one, two or three stages have a PB of 10nm or 16nm. We see that increasing the gate length provides the lowest energy consumption, but it is achieved to the detriment of a huge spread dispersion. Indeed, as the switching energy is predominant in a pulse generator activated at each clock cycle, the saving in energy is quite small compared to the delay dispersion due to the PB. For example, the energy consumption of 3PB16 (the three stages of the conventional PG have a gate length increased by 16nm) is 13% lower than the CS delay generator, but its maximum delay is 84% higher, resulting in an global energy overhead due to buffers insertion for fixing the hold time constraint.

N inverters

One can be surprised by the fact that a higher gate length leads to a higher delay dispersion. However, these results are not in contradiction to the design theory. What it is well known is that the ratio σ/µ decreases with the number of gates or the increase of transistor dimensions. But, we have to keep in mind that while µ increases, σ increases as well, as illustrated on figures 3.3 and 3.7.

Figure 3.8 compares the CS delay generator and the conventional one with different architectures: the replica DG proposed in [START_REF] Lin | A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS[END_REF], one, two or three half Schmitt triggers, and five or seven stages. As explained in section 3.1, adding inverters leads to a tradeoff between energy and robustness. Half Schmitt triggers present a lower robustness than the chain of seven inverters, with a higher energy dissipation due to the hold time penalty. The replica DG decreases both the energy and hold time penalty compared to half Schmitt triggers and inverters chain. However, the current-starved DG exhibits, for the same robustness, a lower energy consumption and delay spread. Finally, compared to the conventional three inverters chain, the hold time penalty of the CS is 50% higher and its energy consumption is 6% inferior.

In summary, the CS pulse generator and the conventional are the best candidates for energy-efficient circuits. The conventional pulse generator provides the lowest global energy consumption but its minimum delay is lower than the CS delay generator, leading to a weaker robustness. Therefore, in order to quantify the robustness face to environmental variations, the next section studies the rate of failure of complete pulsed-FF architectures, one with the conventional DG and the other with our proposed current-starved DG, in post-layout simulations.

Layout comparison

To show the performance of our proposed delay generator, layouts of complete TGPL-Data flip-flops have been made (figure 3.9). The flip-flop has a minimum driving strength in the technology library, and is designed for reaching a minimum energy-delay product. The first layout contains a conventional delay Figure 3.9: Layout of TGPL-Data (mininmum EDP and driving strength) with the conventional DG (above) and the current-starved-like DG (below). An overhead of three fingers is paid for an impressive increase of robustness.

generator, and the second contains the current-starved delay generator with the selected sizing (W CS = 150nm and L CS = 38nm).

Let us notice that every transistor, in the PG and the D-to-Q path of the pulsed-FF, has the same threshold voltage V th . One could argue that if the transistor of the DG had a higher V th than the transistors in D-to-Q path, the drawback of minimum delay of the conventional DG would be resolved. However, at the same subthreshold supply voltage, the delay dispersion between two V th is highly significant [START_REF] Bol | Technology Flavor Selection and Adaptive Techniques for Timing-Constrained 45nm Subthreshold Circuits[END_REF]. Thus, guaranteeing the minimum delay will again result in high energy overhead, even for the conventional DG.

Figure 3.9 shows that three additional fingers are needed to make to complete layout with our proposed pulse generator. To give a comparison, the TGPL architecture of minimum drive is composed of 29 fingers and this number obviously increases for higher drives, while the size of the DG does not. The robustness of these flip-flops is tested by writing logical 1 and 0 in worst environmental conditions. Table 3.1 shows the results of a 1000 runs Monte-Carlo simulation for several PVT conditions. As we see, the number of latching failure is dramatically reduced.

The next section presents silicon measurements which were performed to definitely show the gain of robustness provided by our current-starved architecture.

MEASUREMENTS

A test chip has been fabricated in 28nm FDSOI technology to test the functionality of a single FF for the four following architectures: • a conventional C 2 MOS master-slave topology from a industrial standardcell library

• the TGPL-Data architecture with conventional delay generator

• the TGPL-Data architecture with our proposed current-starved delay generator

• the TGPL-Clk architecture with our proposed current-starved delay generator All these flip-flops shared the same clock, input data, PMOS back bias (vdds), and NMOS back bias (gnds) signals and have been designed in LVT feature. This section presents firstly the yield of the FFs in the (vdds,gnds) space. Because of the LVT feature, only a forward back biasing (FBB) is shown. Afterwards, the shape of the yield in the (vdds,gnds) space is explained by theory in simulation. Finally, the average yield is compared for each V dd between the four different FFs. The robustness gain of our current-starved architecture is thus highlighted.

Yield in the (vdds,gnds) space

The functionality of a single FF, for a large set of (V dd ,vdds,gnds), has been tested at room temperature on 64 chips. This computed yield is showed in figure 3.10 (The darker is the square, the higher is the yield) for each point of the set (vdds,gnds) and some V dd values.

We clearly see that at each V dd , there is(are) one or several couple(s) (vdds,gnds) providing a maximum yield. The number of optimal couple(s) and the average yield extremely rapidly increase relatively to the small increase of V dd between each figure (10mV). From that/those optimal couple(s), the yield gradually decreases until 0%. However, we see that the yield gradient is not the same in every direction. The yield is actually maximum along a 45 • line passing through the optimal points and this line is bounded on the four corners direction. Thus, the yield has approximately the shape represented in figure 3.11 which will be explained in the following section.

Analysis of the trend

In nanometer CMOS technologies, the functional yield, taking into account the output logic levels at ULV, was shown in [START_REF] Bol | Analysis and Minimization of Practical Energy in 45nm Suthreshold Logic Circuits[END_REF] to be directly related to the ratio between I on in linear mode (low V ds ) and I of f in saturation mode (V ds ≈ V dd ), 0. which is strongly affected by three parameters: the subthreshold slope, the DIBL effect, and the local variability (mismatch) [START_REF] Bol | Analysis and Minimization of Practical Energy in 45nm Suthreshold Logic Circuits[END_REF]. Moreover, NMOS/PMOS imbalance also significantly affects the output logic levels [START_REF] Alioto | Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Stdandard Cells[END_REF]. To capture this trend, we define a new figure of merit (FOM) for functional yield with respect to output logic levels as:

F OM logic0 = I on,lin,N I of f,sat,P (3.1)
F OM logic1 = I on,lin,P I of f,sat,N (3.2)
F OM = min(F OM logic0 , F OM logic1 ) (3.3)
where

I on,lin -→ |V GS | = V dd ; |V DS | = 0.2V dd (3.4) I of f,sat -→ |V GS | = 0 ; |V DS | = 0.8V dd (3.5)
The yield dependence with V dd is a well known behaviour which can easily be explained considering the evolution of the FOM with Monte-Carlo simulations (see figure 3.12). The two gray sides in figure 3.11 are explained by the imbalance between the PMOS and NMOS strengths, also called imbalance factor in [START_REF] Alioto | Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Stdandard Cells[END_REF]. Along diagonal 2 and its parallels, the threshold voltages evolve in opposite direction and so do the two components of the FOM, as illustrated in figure 3.13. Notice that the optimal point slightly varies with V dd .

The dark gray boundary in figure 3.11 is also explained by the decrease of the FOM but for another reason. Along diagonal 1, vdds and gnds are symmetrical and thus the currents evolve in the same direction. Nevertheless, continuing to decrease the threshold voltage might eventually lead to a zero-V th transistor. That is why the current ratio progressively decreases when we go to strong FBB as depicted in figure 3.14. As a result, FBB substantially increases the speed of the circuit at ULV (see Chapter 2) but this performance gain is at the expense of lower robustness. Medèn ágan.

Finally, the light gray boundary in figure 3.11 is due to setup time violation. The clock period of our test pattern was 2000ns and, at ULV with nominal threshold voltages, FFs are too slow to switch before the triggering clock edge.

Let us notice that, theoretically, symmetrical RBB does decrease the speed but does not decrease the robustness. Indeed, in sub-threshold regime, the onand off-currents of the PMOS and NMOS follow the same slope and thus evolve in the same way. However, in the 28nm FDSOI technology, the sub-threshold slopes are not the same for PMOS and NMOS. If their V th is increased by the same amount, the on-and off-currents of the PMOS decrease more slowly than I of f,sat,N progressively decreases in our 28nm FDSOI technology, which explains the change of behaviour in the RBB region in figure 3.14. Therefore, the light gray boundary is explained by both timing violation and logic level failure in our case.

Yield comparison

The figure 3.15 compares the average of the yield in the (vdds,gnds) space in terms of the supply voltage.

If the average yield at a certain V dd is higher for an architecture than another one, it means that this architecture is more robust to a back biasing variation, thus a V th shift. Similarly, if the same average yield is reached at a lower V dd , one architecture is more robust to a variation of supply voltage than the other one. We can see in figure 3.15 that the lack of robustness of the explicit pulsed-FF topology, compared to Master-Slave topology, is now completely filled thanks to the current-starved technique.

Below 0.3V, the TGPL-Clk presents a robustness slightly higher than the other pulse-triggered architectures. In addition to its current-starved delay gene- rator, its D-to-Q is much faster at ULV thanks to its lower stack in the input inverter. Thereby even if the generated delay is short, the FF has a higher probability to latch the input data.

The last two architectures help us to compare the yield with and without the current-starved delay generator discussed previously. As we see in figure 3.16, the current-starved DG provides the same yield value at a supply voltage up to 45mV inferior and a yield 7.5% superior at the same V dd . It means that, for the same yield, FFs can work in ULV operations at a V dd 45mV lower than without the current-starved technique.

Moreover, we see that the robustness gap between TGPL-Data without CS technique and the master-slave FF is eliminated thanks to the current-starved DG. As a reminder, the lower robustness was the main disadvantage of pulsetriggered FF at ultra-low voltage. From our results coming from the measurement of 63 FFs, we can affirm that our technique has a significant impact on the pulsed-FF robustness.

After the current-starved technique in the delay generator, the next and final section shows a second way to increase the energy-efficiency of pulsed-FFs: the implementation of the additional functionalities in the pulse generator.

ADDITIONAL FUNCTIONALITIES

As already mentioned, flip-flops present hardly nothing but the three basic connections (D, CLK, Q) in an industrial standard-cell library. In addition to the scan and reset functionalities discussed in the previous chapter, the set and enable functions are also familiar in a common library. The set function is exactly the same as the reset excepted that the output presents a high value. Thus, the transistors used to perform the set function are simply the complementary of the transistors in the reset version. The enable function forbids the writing of the flip-flops without modifying the output. In every case, the writing system must be disabled to avoid writing two different data.

In master-slave flip-flops, these functionalities are implemented inside the two latches, by modifying the (tristate) inverters composing them. Disabling the writing system cannot be implemented in the clocked inverters providing the CLK and CLK signals because if the signal becomes inactive during the high level of the clock, a triggering edge will occur despite the global triggering edge is passed. Therefore, the flip-flop will not be functional any more. As the latch of a pulsed-FF does not work on the levels of the clock but on a edge, the clock system can be easily modified without disturbing the correct functionality of the FF. As we can see in figure 3.17, the pulse generation can be disabled with a NAND and/or NOR gate in the delay generator. It means that only two additional transistors are needed to perform each additional functionality, plus two transistors in the latch for the set and reset functions.

Obviously, the functionalities can be performed with the signal or its complementary, depending on layout or design considerations. After the preceding sections, we are tempted to use the stacking of NAND and NOR as native current-starved technique. Unfortunately, the stack may not be on the delay path. Indeed, when the functionality signal is active, the CLK d signal must be pulled to ground whatever the value of the clock is. Thus, the active signal is on the PMOS of NAND gates and NMOS of NOR gates. But, during normal operations, the CLK d signal is also pulled to zero, therefore using the same pulling system in NAND and NOR gates. Hence, the use of the current-starved technique should be modified as represented in figure 3. [START_REF] Liu | High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond[END_REF].

In master-slave topology, the additional transistors laying in the latches directly impact the timing and/or the energy performances. Indeed, as adding transistors will increase the stack, either the current is lowered or the gate width increases and so does the energy consumption. In pulsed-FFs, as the additional transistors lay in the pulse generator but are not directly on the delay path, the impact on the delay and energy performances is significantly lowered. Layouts of scannable, resettable and/or enabling TGPL-Data flip-flops have been made for the comparison. Table 3.2 compares the area of master-slave FFs from industrial library and pulsed-FFs with the same amount of functionalities. We see that, despite the efficient implementation of reset and enable functions in the pulse generator, the master-slave architectures exhibit a lower area than the pulse-triggered flip-flops for the same functionalities. Nevertheless, Table 3.3 compares the performances of these same FFs. As we can see, the impact of the additional functionalities is significantly much lower for pulsed-FFs than master-slave which shows that they can be efficiently integrated in a complete standard-cells library. Moreover, a simple calculation shows that the complete scannable, resettable and enabling master-slave has a area-energy-delay product (AEDP) almost 3.5 times superior to the AEDP of the corresponding pulsed-FF. The gain in energy-efficiency is now clearly highlighted for UWVR and ULP circuits.

CONCLUSION

In this chapter, a new pulse generator for ultra-wide voltage range pulse-triggered flip-flops is presented. First of all, the key issues of pulse-triggered flip-flops at ultra-low voltage (ULV) were presented. It was explained that the minimum generated delay must be large enough in order to ensure the correct functionality of the pulsed-FF and, on the other hand, the maximum generated delay should be as small as possible to minimize energy overhead. The proposed DG consists of using current-starved-like inverters in the delay chain, with a PMOS and a NMOS always in on-state. This architecture allows a great flexibility in design, by sizing the current-starving transistors without impacting the dynamic energy. Several architectures of delay generators have been compared with one chosen sizing of our delay generator. All of them present at least one drawback in the figures of merit characterizing delay generators: minimum delay, delay dispersion and energy consumption. Post-layout simulations have been performed to compare the robustness of our pulse generator with the conventional one. It is shown that, for an area penalty of only three fingers, the number of latching failures at ultra-low-voltage is dramatically reduced. Afterwards, silicon measurements were presented to study the robustness improvement of the current-starved DG. Moreover, we showed that, based on our results, the robustness gap between pulsed-FFs and master-slave structures is compensated thanks to the current-starved technique.

Finally, the implementation of additional functionalities in pulse-triggered flip-flops was studied. In master-slave (MS) topology, the additional transistors needed to carry out these functionalities, lead to a large increase in area and energy-delay product (EDP). On the other hand, it has been shown that, for our pulsed-FFs, the reset and enable functions can easily be performed and implemented in the pulse generator. The EDP overhead is only 9% for pulsed-FFs and 64% for master-slave, while the AEDP of the biggest pulsed-FF is 3.5 times smaller than the biggest MS.

INTRODUCTION

So far, we have clearly seen that explicit pulse-triggered flip-flops (pulsed-FFs) are much faster than master-slave flip-flops whereas they suffer from energy and area penalties. After guaranteeing the robustness of pulsed-FFs at gate level in Chapter 3, this chapter studies several techniques to decrease their energy, area or both at block level and finally reaches better performances than master-slave (MS) flip-flops.

In Section 4.2, the impact on the clock skew on the explicit pulse-triggered flipflop architecture is discussed. We show that soft-edge property allows a certain immunity and facilitates the timing closure during clock tree synthesis.

In Section 4.3, a conditional capture technique is applied and studied with the aim of saving energy. Then, several architectures are compared in the energydelay domain, as in Chapter 2. It is shown that this architecture exhibits a lower energy consumption but also lower speed than the MS, C 2 MOS and TGPL architectures developed in Chapter 2. Thereby, it provides another design point in the energy-delay (E -D) tradeoff of flip-flop design and, with the help of master-slave topology, may help the tools to produce a Pareto-optimum-like netlist in an energy point of view.

As mentioned in Section 1.4, one of the advantages of the explicit pulsetriggered flip-flop is the shareability of its pulse generator. This is one of the ideas proposed in the literature to reduce the FF energy budget. In Section 4.4, the energy consumption per flip-flop is studied for shared pulse generators and compared to the energy consumption of the master-slave flip-flop. Following this idea, a complete register file with the energy-efficient scannable C 2 MOS-Data latch and a shared current-starved pulse generator with the enable and reset functionalities, is developed in Section 4.5. By comparing to register files based on master-slave flip-flops, it is shown that the explicit pulsed-FF finally presents a lower energy consumption, even without the conditional capture, and a lower area than master-slave thanks to pulse generator sharing. Finally, Section 4.6 concludes this chapter.

CLOCK SKEW ABSORPTION

After the clock tree synthesis, it appears that the clock signal do not exactly arrive at the same time at the leaf level. Even in neglecting the local variations, a static timing analysis of the clock tree shows a certain difference between the clock signal arrivals. If a flip-flop receives its clock signal a time ΔT before the preceding flip-flop in a path, the data has ΔT time less to pass through the combinational logic and reach this flip-flop. This difference is called the clock skew and it directly penalises the speed of the circuit. On the other hand, if designers set a too small clock skew, the clock tree synthesis may become very difficult and the use of more and/or larger clock buffers might become necessary, leading to additional energy consumption. More precisely, clock skew is modelled as a window around the nominal arrival time where the actual clock transition may occur [START_REF] Nedovic | A Clock Skew Absorbing Flip-Flop[END_REF]. A change in the D-to-Clk delay might cause a fluctuation in the effective input-to-output delay. Nevertheless, the soft-edge property of the pulse-triggered flip-flops leads to a D-to-Q behaviours as shown in figure 4.1. As we can see, over a large window, the D-to-Q delay does not vary that much with the D-to-Clk delay, thus the clock arrival time. That allows to tolerate a larger clock skew in the clock tree without modifying the timing performances. Thus, the constraints on the clock tree synthesis are lower and lead to a save in energy.

In conclusion, the pulse-triggered flip-flops present a large clock skew absorption, which tends to facilitate the timing closure and improve the timing and energy performances of the circuit.

CONDITIONAL CAPTURE ARCHITECTURE

We have seen that, in our 28nm FDSOI technology, the most energy-efficient pulsed-FF architecture, over a wide range of supply voltage and driving strength, is the C 2 MOS-Data architecture, with the current-starved delay generator (DG). It is an explicit pulse-triggered topology, where the distribution of energy is represented in figure 4.2 for minimum driving strength. We clearly see that the main source of energy consumption is the pulse generator (PG), made of the delay generator and the gates controlling the clocked transistor of the latch (included in clock load). The part of the delay generator is less predominant with a higher driving strength, because the energy consumption of the latch is higher. However, as mentioned in Section 2.3, the lowest driving strength is the most used in the synthesis of industrial low-power microprocessors. Therefore, as we focus the energy-efficiency, only the energy consumption of the lowest driving strength is of primary importance. This section studies one of the ways to tackle the high energy consumption of the pulse generator based on the "xored" inputoutput technique. This idea is to compare the current input with the current output and disable the FF latching mechanism if they are identical [START_REF] Xiang | Design of a low-power pulsetriggered flip-flop with conditional clock technique[END_REF]. Firstly, we show how to implement the XOR technique in our efficient pulse generator with a brief discussion about the position of the pseudo-XOR gate. Secondly, we present various implementations in the latch and compare them in the energydelay (E -D) domain with the same methodology of Chapter 2.

Pseudo-XOR gate in explicit pulsed-FFs

The five stages of the PG (3 minimum-sized current-starved inverters, a NAND gate and an inverter) are activated at each clock cycle, even without data activity. In addition, the clocked transistors of the latch are also charged and discharged even when the input has not changed. To tackle this useless energy consumption, the XOR-architecture represented in figure 4.3 is proposed with a slightly different approach from [START_REF] Xiang | Design of a low-power pulsetriggered flip-flop with conditional clock technique[END_REF]. Using the explicit pulse property, a pseudo-XOR gate is added in order to disable the pulse generation when both the input (D) and the output (Q) are the same, i.e. when latching is not needed.

Let us notice that this technique cannot be applied with edge-triggered flipflops, like the master-slave topology. Indeed, in order to disable the latching,

CLK Pulse Pulse RN W PG W PG disable D Q Qd D D Q D Qd β PN W 3 W 3 E (a)
The conditional pulse generator (current-starved circuitry not shown for clarity). the conditional capture technique must maintain a closed master latch and open slave latch during the triggering edge of the clock. But if the incoming data changes between the triggering and the non-triggering clock edge, the conditional capture is being disabled and the FF will see a new clock level. This will create a triggering edge on the FF after the global triggering edge of the circuit, thus leading to functional failure. To sum up, it is impossible for the edge-triggered flip-flop to make the difference, excepted by exhibiting a hold time of half T clk which is obviously non-acceptable in energy-efficient circuits.

The position of the pseudo-XOR output in the delay generator will impact the setup time and the hold time of the flip-flop, and the number of stages which flip at each clock cycle. If the XOR gate is close to the NAND gate of the PG, the input data edge has more time to reach the FF input before the end of the propagation of the triggering clock edge. Therefore, the setup time and the hold time evolve in the same direction. Since T setup -T hold is the key parameter for the useful-skew technique ( [START_REF] Chou | Useful-skew clock optimization for multipower mode designs[END_REF][START_REF] Shena | Useful Clock Skew Optimization under A Multi-corner Multi-mode Design Framework[END_REF] Section 1.4), the only criteria for the position of the NAND is the energy dissipation of the inverter chain. Obviously, there is less energy overhead if the first inverter is disabled when D is identical to Q (figure 4.3). Finally, the position of the enable (E) and reset (R) signals (see Section 3.5) is a design choice depending on the use rate of those signals in the application.

Afterwards, let us point out that the setup and hold times are now positive and negative, respectively. Indeed, the incoming data must now be valid sufficiently before the triggering clock edge so that the disable signal enables the pulse generator, i.e. the CLK signal has a high logic level. Similarly, the hold time becomes negative because if an input data comes after the triggering clock edge, the NAND gate output in the pulse generator is already pulled to one.

Architectures comparison

A two-inputs CMOS XOR gate needs the two inputs plus their complementary signals. D and Q signals can be easily taken from the input signal and the bistable element node not laying on the D-to-Q path, without degrading the timing performances (assuming identical input slope for D). The D and Q d (for Q delayed) signals can be taken directly in the D-to-Q path, or by adding inverters connected to the pseudo-XOR gate. Notice that providing D signal in the D-to-Q path means to switch to a TGPL architecture. Figure 4.4 shows a comparison performed on the different XOR configurations in the E -D space, where the sizes of the transistors in the XOR gate are additional sizing variables.

The lowest energy consumption is still provided by C 2 MOS architectures, because of the lowest junction capacitance (dis)charged in the input tri-state inverter (see Chapter 2). Again, the gap is small because the junction capacitance of FDSOI technology is highly lowered compared to bulk. The minimum energydelay product (EDP) is reached by the C 2 MOS topology with an additional inverter for Q (C 2 MOS-invQ), as represented in figure 4.3, for a D-to-Q delay of approximately 6D 0 . Nevertheless, we can see that directly after this small window where C 2 MOS-invQ is the most energy-efficient, the TGPL-invQ-D architecture (with an additional inverter for Q but with D taken directly from the input inverter) becomes the most energy-efficient for the high-speed figures of merit. However, as explained in Section 2.3.4, the back biasing technique allows designers to cover the E -D domain with the same architecture and even more efficiently than with the sizing methodology. Therefore, to save design time, designers can choose to use only the TGPL topology, with a reverse body bias when performances are not under consideration. First of all, we see that our conditional capture technique, disabling the pulse generator when D and Q are identical, provides a lower energy consumption than the master-slave architecture. Consequently, ULP circuits, targeting a very low energy consumption without hard speed constraints, might use this explicit pulsed-FF architecture. Moreover, let us remind that the problem of positive hold time is alleviated because the conditional XOR-technique induces a positive setup time and negative hold time. Secondly, we can imagine a Pareto-optimum-like curve is provided in the E-D space by mixing different FF architectures, at the cost of area overhead (see Table 4.1). It means that the synthesis tools have the opportunity to choose the most energy-efficient FF for a path, depending of the timing constraints of this path, in order to provide a minimum energy consumption. This pareto optimum point in synthesis is extremely interesting for UWVR circuits where both speed and power are under consideration.

PULSE GENERATOR SHARING

Sharing the pulse generator has been studied many times from an energyefficiency point of view [START_REF] Ashna | Design of low power clocking system using merged flip-flop technique[END_REF][START_REF] Lin | Pulsed-Latch Utilization for Clock-Tree Power Optimization[END_REF][START_REF] Chang | Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating[END_REF][START_REF] Paik | Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power[END_REF]. The objective of sharing one pulse generator with N latches is to get a lower energy consumption than using 2N latches with master-slave topology. Most of the papers in the literature work in the superthreshold regime where the random variations can be more easily handled to ensure a correct and sufficient slope of the pulse signal after the Place&Route steps. In near-and subthreshold regime, we consider that the variability of the pulse signal is too high (see Chapter 3) to deal with a variable PG output capacitance. Therefore, we recommend a single block of many latches and one pulse generator which can be characterized independently. Let us notice that a block of FFs can be useful in many applications: synthesised register files or any other standard-cells based memory [START_REF] Meinerzhagen | Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology[END_REF], or pipeline registers in low-power datapaths like the 16bits or 32bits ultra-low power CPU ( [START_REF] Bol | SleepWalker: A 25-MHz 0.4-V Sub-mm 2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes[END_REF][START_REF] Botman | Bellevue: a 50MHz Variable-Width SIMD 32bit Microcontroller at 0.37V for Processing-Intensive Wireless Sensor Nodes[END_REF] respectively). Figure 4.6 shows the energy consumption of a block of N latches sharing a PG compared to the energy consumption of one master-slave FF from an industrial standard-cells library (dotted line). The size of the transistor of the NAND and INV gates are adapted to reach the same slope for the P ulse and P ulse signals.

As we see, one PG shared with 4 latches dissipates almost the same energy per FF than the master-slave architecture. Then from 8 or more latches, shared pulsetriggered FF architecture is more energy-efficient than master-slave FF. Figure 4.6 also shows the relative proportion of the three contributions of the total energy of the bloc: the delay generator, the pulse generation and the external clock signal load (both included in the Clk load component) and the latch itself. When the pulse generator, meaning the delay generator plus the Clk load, is connected to only one latch, we can see that it represents more than 70% of the total energy consumption. This percentage clearly shows that it is the key point to be optimized in order to reach an energy-efficiency as the latch mainly deals with the timing performances (and also robustness) of the FF. Proportionally to the total energy per FF, the Clk load component remains at the value (≈ 40%) because the constant slope constraint is maintained. While the energy per FF due to the latch remains obviously roughly the same, the energy gain comes from the sharing of the delay generator. After 16 latches, the energy of the delay generator normalized by the number of FF becomes negligible and thus we see a stagnation of the benefit of sharing the pulse generator.

-32% -32% FF0 FF0 FF7 FF7 Latch0 Latch0 Latch7 Latch7 Shared PG Shared PG
The area of a block of 8 latches sharing one PG is 32% lower than 8 times the area of a master-slave FF, considering the layout from an industrial library (figure 4.7). Therefore, after a certain number of latches, the area per FF is smaller for pulse-triggered topology with the drawback of using the first vertical layer (M3 in this technology) to spread the P ulse and P ulse signals over the latches.

In the next section, we study a 16x32bits register file using the PG sharing developed in this section, in order to compare its timing, energy and area performances to master-slave topology based register file. It will be shown that the conclusion of this section remains the same when shared PG are used in a higher level application.

REGISTER FILE

In this section, we compare two register files: one with our pulsed-FFs and the other with conventional master-slave flip-flop. A register file is a small embedded [START_REF] Zhao | Structure configuration of low power register file usingenergy model[END_REF]. A typical size for energy-efficient circuits is around 16 or 32 registers, each of them with the same number of bits as the datapath. For this small memory capacity, register files are more area-and power-efficient than SRAM and are faster in any case. Moreover, it is more robust (scalable in supply voltage) and can be easily integrated into the logic. Indeed, the fundamental bit cell of a register file is the flip-flop.

Design of register files

From all the studies performed in the previous chapters, we laid out a structured register file based on our energy-efficient explicit pulse-triggered flip-flop: a C 2 MOS-Data architecture with minimum E 1 D 1 product for the latch, a currentstarved delay generator with enable and reset options, and one shared pulse generator for each register. In order to provide realistic conditions, we chose the same characteristics as the register file of the low-power dedicated Cortex-M0 microprocessor: 16 registers of 32 bits, one synchronous write port, and two asynchronous read ports. Each 32-bits register is composed of one pulse generator placed above and below 16 latches sharing the P ulse and P ulse signals.

The write port is implemented by a conventional 4-to-16 decoder, composed of NAND, NOR and inverter gates. Each read port is composed of two stages of 4-to-1 multiplexer for every bit. The clock network is an unbuffered H-tree 0 level since [START_REF] Bol | SleepWalker: A 25-MHz 0.4-V Sub-mm 2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes[END_REF][START_REF] Seok | Clock Network Design for Ultra-Low Power Applications[END_REF] showed that this configuration provides lower slew and skew variations at ultra-low voltage than buffered clock-tree. A global reset and scan-enable pins are available, as well as 32 scan-inputs.

The pulse generator contains an enable signal E connected to a decoder output. It allows to select the right register in the bank and, at the same time, it acts as a clock gating system. On the other hand, the MS-based register file contains latches at the decoder outputs performing clock gating. and α rate = 15%). Explicit pulsed-FFs based register file presents a lower energy consumption for super-threshold V dd and an optimal one at 0.35V.

In the following section, the timing, area, and energy performances of the structured pulsed-FF-based and MS-based register files are compared.

Comparison of energy-delay-area performances

First of all, figure 4.8 shows the layouts of the pulsed-FF-based and master-slavebased register files. The area of the structured pulsed-FF-based register file is 40.8µm × 72.8µm = 2970.4µm 2 while the area of the MS-based register file is 40.8µm × 83µm = 3386.2µm 2 , both including the multiplexers used for reading, the clock buffer, the write decoder and the clock gating system. Consequently, our pulsed-FF-based register file presents an area 14% lower than the MS-based one.

Figure 4.9 compares the average energy consumption per operation between the pulsed-FF-based and master-slave-based register files. These numbers are computed from SPICE simulations with the testbench presented in Annex C, where the clock period T clk = 40F O4 is adapted for every supply voltage. For supply voltage higher than 0.5V, the average energy consumption per operation E op is lower for the pulsed-FF-based register file. Then, the higher leakage current presented by the pulsed-FF leads to a lower E op for MS-based register file. Indeed, at low voltage, the leakage energy is more and more predominant and thus the leakage current penalizes the pulsed-based structure.

In parallel to this, a RTL code representing our register file operations has been synthesized, placed and routed by commercial tools. The RTL code performs register file operations with the same number of pins and ports. An industrial 28nm FDSOI LVT standard-cells library has been characterised at nominal voltage (1V) and ultra-low voltage (0.35V). Then, two synthesises have been performed with these two libraries. In both synthesises and Place&Route (P&R) in the two points of characterisation, the clock period has been set to reach the energy-efficient limit of the register file. Table 4.2 compares the area of the structured and automatic placed layouts, as well as the energy-delay performances for two supply voltage values. We can notice that an automatic implementation may lead to an increase of 25% in area, more than 20% in delay and up to 50% in energy at ultralow voltage. Custom implementation is thus highly pertinent for register file application.

Back biasing

Thanks to the FDSOI technology, we can apply a wide back biasing (symmetrical in this section) range on the register file transistors and observe the behaviour of the figures of merit.

For the same supply voltage, a forward body bias (FBB) decreases the threshold voltage, thus increases the speed and the leakage current. Figure 4.10 shows the energy per operation (E op ) effectively increasing for FBB at each supply voltage. As the leakage current is integrated over the entire clock period, the static energy at ultra-low voltage becomes higher than the dynamic energy and the energy-efficiency decreases dramatically. The supply voltage providing minimum E op varies between 0.3V and 0.5V, depending on the back bias. The figure 4.11 presents the evolution of the delay with the back bias. As with the silicon measurements in Chapter 2, the delay decreases with FBB and the relative variation is higher for low supply voltage. For strong FBB, the delay difference between two supply voltages reduces while this voltage reduction induces a lower dynamic energy consumption. For example, the delay at V dd = 0.7V is 73% higher than at V dd = 1V for Gnds = -Vdds = 1V, but the energy consumption is 2.5 times lower (figure 4.10).

This trend is even clearer in the figure 4.12, which represents the evolution of the energy-delay product (EDP), i.e. the combination of the two previous observations, with the supply voltage (V dd ) and back bias. For highest supply voltages, the energy consumption, impacted by the short-circuit current, mainly determines the shape. For the lower supply voltages, the delay is the most important part of variation. All combined, we can see that the minimum EDP is not reached at the same V dd for each back bias and that the lowest EDP is reached for strong FBB. Therefore, we see that the energy-efficiency needs to combine adaptive dynamic supply voltage and back bias, as done in [START_REF] Wilson | A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking[END_REF].

CONCLUSION

This chapter studied the integration of our energy-efficient pulse-triggered flipflops at block level applications. First, we explained how our pulse-triggered flip-flops absorb the clock skew and allow to reduce this constraint during clock tree synthesis. After that, we presented a new conditional capture technique based on a pseudo-XOR gate which compares the data input and the current output. This pseudo-XOR gate is inserted at the beginning of the pulse generator which allows to save a lot of energy when data remains unchanged. A comparison in the energy-delay space has allowed the most energy-efficient variant to be selected depending on the targeted application. Then, we compared the architecture exhibiting the lowest ED product with the pulsed-FFs of Chapter 2 and the conventional master-slave. We have shown that, thanks to our conditional capture technique, this new explicit pulse-triggered flip-flop architecture presents a lower delay but also a lower energy consumption than the master-slave architecture. As the problem of hold time is handled with the pseudo-XOR gate and the robustness is ensured by the current-starved technique (Chapter 3), we have designed an explicit pulsed-FF more energy-efficient than master-slave topology. Another advantage of this architecture is to provide another energy-delay tradeoff for the CAD tools. Combined with the two pulsed-FFs architectures pointed out in Chapter 2 and the master-slave topology, the automatic synthesis tools are able to choose the lowest FF energy consumption while meeting the timing constraints of each path.

Afterwards, we studied the promising property of explicit pulsed-FFs: the pulse generator sharing. It has been shown that after a given number of latches sharing a PG, the energy consumption and area per FF are actually lower for explicit pulsed-FFs than for master-slave, even without pseudo-XOR gate. To highlight this idea, we implemented a structured register file with the energyefficient explicit pulse-triggered flip-flop architecture developed in this work. It has been shown that the pulsed-FF-based register file effectively exhibits a lower energy per operation and lower area than the master-slave based register file.

In this dissertation, robust and energy-efficient explicit pulse-triggered flipflop architectures targeting ultra-wide voltage range and ultra-low power circuits, have been developed and designed in FDSOI technology.

First of all, the explicit pulse-triggered flip-flop topology was pointed out of the literature in Chapter 1. This architecture presents interesting and remarkable timing properties, e.g. small input-to-output delay, negative setup time, timeborrowing technique, and dual-edge operation facilities, as well as shareable pulse generator. Nevertheless, this topology is hardly used in circuits working at ultralow voltage because of two main drawbacks:

• the poor robustness to environmental variations compared to master-slave topology -handled in Chapter 3,

• the positive hold time which induces an energy overhead for inserting delay buffers -handled in Chapter 4.

In Chapter 2, an analysis of the latch operations led us to select six promising pulsed-FFs architectures for the targeted applications. Then, a fair comparison was performed in the energy-delay (E -D) domain to highlight the most energyefficient architecture depending on the targeted application. If the TGPL-Clk architecture presents the best energy-efficiency for high-speed operations, the C 2 MOS-Data architecture is revealed as the most energy-efficient pulsed-FF architecture over a wide range of targeted delays and supply voltage. Integration in a chip showed none additional difficulty to perform the timing closure. Then, silicon measurements showed the timing performances of flip-flops composed of the most energy-efficient latches and exhibited an average input-to-output delay down to 31ps at nominal voltage (1V), high temperature (80 • C), and nominal back biasing conditions. Moreover, reverse and forward back bias allowed us to increase either the timing or the energy performances.

In Chapter 3, the fundamental tradeoff between robustness and energy consumption in a pulse-triggered flip-flop was explained and a current-starved delay generator (DG) was proposed to overcome this issue. It has been shown that our proposed current-starved DG significantly improves the robustness of the pulsed-FF, which was one of the two big drawbacks. Moreover, the structure is very flexible and offers many degrees of freedom to designers. Silicon measure-ments compared the yield and minimum operating voltage of different flip-flops and showed that our proposed current-starved DG provides an average yield increase of 7.5% at the same V dd and an identical average yield reached at a supply voltage up to 45mV lower than without the current-starved DG. Moreover, it is explained how the proper choice of back bias can help designers to reach the lower operating voltage, or the higher yield. Then, an efficient approach of implementing the reset and enable functionalities in the pulse generator was presented.

In Chapter 4, it is shown that soft-edge pulse triggered flip-flops tolerate a large clock skew without modifying the delay performance. This absorption of the clock signal non-ideality facilitates the precision/energy tradeoff of clock tree synthesis. Afterwards, a conditional capture technique was presented and implemented in the most energy-efficient latch of Chapter 2. Then, a comparison in the E -D domain showed that this pulse-triggered flip-flop architecture exhibits a lower energy dissipation than the master-slave topology and a negative hold time. The second drawback of pulsed-FF is thus partially alleviated thanks to this architecture. Finally, a 16x32bits register file, based on robust and energyefficient pulsed-FFs coming from the development of the previous chapters and the pulse generator sharing property, is compared to MS-based register files. This comparison showed that our pulse-triggered flip-flop provides higher speed, lower area occupation and lower energy consumption, while guaranteeing a sufficient robustness in subthreshold regime.

In conclusion, we have designed energy-efficient pulsed-FF architectures, namely TGPL-Clk, C 2 MOS-Data, and C 2 MOS-Xor, respectively dedicated to high-speed, energy-efficient and ultra-low power operations. The FDSOI technology, through the back biasing technique, allows the energy-delay performances of these flip-flops to be dynamically modified, depending on the actual constraints of the circuit. The energy-efficiency is preserved at synthesis step thanks to the clock skew absorption, the conditional capture technique and during the addition of flip-flop functionalities thanks to the pulse generator structure. Finally, the robustness at ultra-low voltage is ensured by the low variability of FDSOI, the proper choice of the back bias value thanks to the yield study, and our proposed current-starved delay generator.

Perspectives and future work

Three main pulsed-FFs architectures are pointed out from this work. The TGPL-Clk architecture is dedicated for high-speed operations, the C 2 MOS-Data architecture is extremely energy-efficient over a wide range of supply voltage and timing performances, and the C 2 MOS-Xor architecture presents a still lower energy consumption than MS and a negative hold time, which means no delay buffer insertion. By characterizing these architectures, we could synthesize a low-power microprocessor (the Cortex M0 for example) with our fast and energy-efficient flip-flops. Therefore, the expected energy saving comes from two ways. Firstly, the clock period is reduced, so is the static energy per operation (the integration of the static current over the clock period) and finally the total energy per operation. Secondly, as the C 2 MOS-Xor topology exhibits a lower energy consumption than master-slave flip-flops, it would provide more energy-efficient non-critical paths.

Lógo mén the C 2 MOS-Xor will be used for the short paths, C 2 MOS-Data in most of the cases and TGPL-Clk for the very critical paths ; érgo dé microprocessor architecture is so complex that the behaviour of synthesis is highly unpredictable, and the TGPL-Clk and C 2 MOS-Data architectures could be used at the end of short paths. Thereby, their positive hold time would induce additional delay buffers for fixing the hold time constraint. Moreover, the clock load of the pulse-triggered structures is higher than the clock load of masterslave FFs of around 11% without shared PG. But, the relation between the total clock load and the clock tree consumption is not simple at all, and certainly not linear. For example, an industrial standard-cell library provides a finite amount of driving strength for the clock tree buffers. After a clock tree synthesis for a master-slave-based circuit, the sizes of the clock tree buffers are maybe already strong enough to drive the pulsed-FF clock load. Furthermore, the size of the buffers of the last branch of the tree might increase so much that they become as big as the previous branch, and an entire clock branch could be saved. Moreover, as already mentioned, the pulse generation sharing is an efficient way to reduce the energy consumption and the clock load by FF seen by the clock tree [START_REF] Ashna | Design of low power clocking system using merged flip-flop technique[END_REF][START_REF] Lin | Pulsed-Latch Utilization for Clock-Tree Power Optimization[END_REF][START_REF] Chang | Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating[END_REF][START_REF] Paik | Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power[END_REF]. Synthesis and Place&Route should be performed to study if the energy saving is higher or lower than the energy loss.

The structured datapath feature is a promising way for placing and routing a regular register file. While keeping the speed, energy and area performances of Chapter 4, it would add reconfigurable and reprogrammable properties to pulsed-FF-based register file.

As mentioned in Section 1.4, the time-borrowing technique is a very complicated microarchitectural system appeared in the literature these last few years.

Here, it has the meaning of presenting a time-borrowing window after the triggering clock edge, sensing a valid data transition. If this transition is detected during the time-borrowing window, an error signal is generated and an error detection and/or correction mechanism(s) handle(s) this late data arrival. Yet, all the publications [START_REF] Ernst | Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation[END_REF][START_REF] Blaauw | Razor II : In Situ Error Detection and Correction for PVT and SER Tolerance[END_REF][START_REF] Lee | Timing error prevention using elastic clocking[END_REF][START_REF] Chang | Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating[END_REF] use master-slave and latch-based topology to perform the operations. As presented in Section 1.4, the implementation of the time-borrowing property needs less resources with pulse-triggered flip-flop than for master-slave-based topology.

Finally, the dual-edge property was discarded in Chapter 1 because we considered that the balance constraints on the clock tree seemed too difficult to reach at ultra-low voltage. A solution to overcome this problem might come from the interesting well properties of FDSOI technology. Thanks to the buried oxide (see Section 1.2.3), this technology allows PMOS and NMOS transistors to share an identical well. Indeed, the P-doped and N-doped channels can be over a buried oxide which is over a single P-well encircled by N-well. In [START_REF] Giraud | Robust Clock Tree using Single-Well Cells for Multi-VT 28nm UTBB FD-SOI Digital Circuits[END_REF], authors show that this cell can be inserted into the logic with acceptable area penalty and leads to remarkable performances in fall/rise and propagation delays balancing and clock-tree skew. Moreover, an adaptive body biasing mechanism could be designed to sense and compensate the P-N imbalance and, contrary to [START_REF] Ragheb | Design of thermally robust clock trees using dynamically adaptive clock buffers[END_REF], only one back bias generator would be needed for both PMOS and NMOS.

Q int Q int Q int Q int W PG W PG W PG W PG W 1 W 1 W 1 W 1 W 1 W 1 W 2 W 2 W 2 W 2 W 2 NX Figure A.1: Two-stages single-edge CDFF.
at ULV. Nevertheless, it creates a short circuit path when writing a logical 1 and two gates plus one drain junctions are added to NX.

As keeper should be active when either D or Q or both equal zero, we propose a keeper composed of only two minimum-sized PMOS transistors connected to the intermediate node N X (encircled in figure A.1). Thanks to that, no short circuit path is created during write time and the parasitic capacitance on N X is reduced. The drawback is the increase of the data load but it is fully compensated by the removal of the short circuit path. It means that only a high number of glitches could get rid of the energy gain due to the absence of short circuit current.

Let us notice that, depending on the specifications and/or the technology, a keeper might be unnecessary. As a reminder, this structure needs a keeper mechanism to avoid the node NX to be discharged by leakage current when it should functionally stay at high level. This discharge causes additional energy overhead because NX will be in any case precharged after the triggering pulse signal. But, if the minimum level achieved, for the worst case of PVT and local variations, is sufficiently high, the keeper can be removed.Sufficient high means that the energy loss is lower than the energy gain due to the removal of the keeper and its parasitic capacitances, while improving the delay too.

Reordering Transistor reordering is a well-known technique that can be used to optimize circuit delay and power dissipation [START_REF] Lanuzza | Comparative analysis of yield optimized pulsed flip-flops[END_REF]. In the two NMOS stacks of the CDFF architecture (see figure A.1), the order of the input D and P ulse can be switched without changing the FF functionality.

The four configurations were previously compared and the results clearly showed that the configuration with the input data and its complementary D the closest to the stage output provides the best energy-efficiency for the whole energy-delay domain. That is because the intermediate junction capacitance has

CLK CLK D Q Adaptive coupling Figure A.2:
As a reminder, the pulse-triggered version of the ACFF, the adaptive coupling pulse latch (ACPL). Even the basic architecture without additional functionalities is not functional at ultra-low-voltage.

been previously discharged and so the total amount of charge having to go to the ground, for the same transistor sizes, is reduced.

ACPL

The ACPL topology (figure A.2) keeps the adaptive coupling technique proposed in [START_REF] Teh | A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS[END_REF], allowing a very small clock load. Nevertheless, this structure leads to floating nodes under certain conditions. Indeed, if the incoming data changes slightly after the end of the pulse signal, the inputs of the two cross-coupled inverters, providing the bistable element, are floating. Therefore, if the leakage current of the transistors gate-connected to the pulse signal is higher than the leakage current of the transistors gate-connected to the input data signal, the floating nodes might change their value, leading to a non correct functionality of the flip-flop.

Figure A.3 shows the results of 100 Monte-Carlo (MC) simulation made on the ACPL architecture. It shows that, at already 0.4V, the bistable element does not maintain the valid data value properly for 10% of the MC runs. On the other hand, if the gate width of the two pulsed transistors is not big enough, the writing system cannot switch the state of the bistable element during the pulse time. Therefore, the gate widths of both the pulsed transistors and the transistor performing the adaptive coupling technique (gate-connected to D) have to be large enough to guarantee sufficient writing and leakage currents, respectively. As large gate widths, meaning high energy consumption, are needed for ensuring a correct functionality, this architecture has not been selected for the comparison.

Resettable and scannable CPFF

From the large study and comparison of [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF], the conditional precharge flip-flop (CPFF) architecture presents the best energy-efficiency in low power domain for small data activity among all studied pulse-triggered flip-flops. However, all the studied structures in [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF] only perform the basic flip-flop functionality, i.e. with only three (D, CLK, Q) ports. In this section, the reset and scan property is added to the CPFF architecture (figure A.4), as the other pulsed-FFs.

Figure A.5 shows the comparison in the E -D space of the pulsed-FFs architectures. We see that the resettable and scannable CPFF architecture is overwhelmingly the worst energy-efficient without presenting good timing performances. Because of its implicit pulse property, as well as its feedback system, a quite large amount of additional inverters is needed to perform both reset and scan functionalities. Therefore, CPFF is not more energy-efficient than TGPL topology in low-power region, in contradiction with the results in [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF]. As already said, this shows that adding FF functionalities may change the comparison result and should be included in every comparison of FF in advanced technology.

APPENDIX B TESTBENCH FOR FLIP-FLOP AND ENERGY-DELAY ESTIMATION

In this section, we present in detail the testbench used for every flip-flop comparison in this work, the definition of the delay and energy, and the sizing methodology which allowed us to get/compute the energy-efficient curves (EECs) described in Section 2.3.

Testbench

Our testbench, represented in figure B.1, is largely inspired from [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF]. The data and clock input signals have a FO3 inverter slope which is tuned for every environmental conditions. The reset and scan signals are held in disable mode, i.e. T E = 0V and RN = V dd or R = 0V . The scan input data is the inverse value of the input data D in order to take the worst case, thus maximum delay, into account. The output load is composed of three identical inverters of same driving strength as the FF under test and each of those three inverters is connected to another inverter to avoid unrealistic Miller effect. This emulates a FO3 output, quite common after synthesis, and takes into account the dependency of the transistor gate capacitance with the gate voltage. The current going from the FF to the load is integrated and then removed from the total energy computation. The energy result is thus load independent. Since [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF] showed that they largely influence the FF architectures comparison, layout parasitics are evaluated and taken into account in the design methodology. Their evaluation is performed thanks to the geometrical approach proposed in [START_REF] Consoli | General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space[END_REF].

Definition of timing parameter and energy consumption

In this dissertation, the delay of the flip-flops are defined by the data-to-output (D-to-Q) delay computed at setup time. The metric used to compute the setup time is a new metric we proposed, based on the output signal transition time [START_REF] Bernard | An efficient metric of setup time for pulsed flip-flops based on output transition time[END_REF]. Compared to the state of the art, it really gives the limit beyond which the performance of the flip-flop is degraded and the reliability is endangered for pulsed-FFs. As it takes into account the soft-edge property of pulsed-FFs, this metric provides the most timing efficient value for the setup time of pulsed-FF and allows the maximal clock frequency obtained by synthesis to be reduced.

Here, the setup time is by definition the time between the data edge and the triggered clock edge such as the transition time of the output increases of 10% compared to the transition time of the output when input data arrives far before the clock edge.

The average FF energy consumption by clock cycle depends on many parameters, including the data input switching activity (α sw ), the clock period (T clk ) and the temperature. As proposed in [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF] in order to be technologically independent, T clk is normalized by the FO4 inverter delay, giving the logic depth of the circuit, and delay and energy are normalized respectively by: • D 0 , the F O4 inverter chain delay in the same environmental conditions,

• E 0 , the energy dissipated by an unloaded symmetrical minimum sized inverter during a complete 0 → 1 → 0 transition cycle.

The total energy dissipation is computed as described in the appendices of [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF], where the output current is removed from the total FF consumption and the effect of every input transitions is taken into account, as well as input data and clock loads.

Design methodology

Our sizing methodology is also largely inspired from [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF]. Only the gate widths of the transistors in the D-to-Q path (W k ) can modify the speed, and thus the E -D tradeoff. Thereby, they are the main variables for the transistor sizing algorithm. This algorithm consists in determining the set of W k which provides a minimum point for a given figure of merit (FOM). Since modern applications of digital electronic range from high-speed to low-power designs, a large class of FOMs E i D j have been adopted to cover all the possible tradeoffs. From a discrete set of design points minimizing several E i D j FOMs, the energy-efficient curve (EEC) of the FF, i.e. the set of design points showing minimum energy (delay) for a given delay (energy) [START_REF] Zyuban | A Unified methodology for resolving powerperformance tradeoffs at the microarchitectural and circuit levels[END_REF], can be extracted. We chose to consider ED j and E i D, for i, j = 1...5, because they cover a very wide range of applications. To reduce the total number of variables in the sizing algorithm, some simplifications are introduced:

• series-connected transistors are equally sized for litho-friendly layout [START_REF] Veendrick | Nanometer CMOS ICs[END_REF],

• pull-up and pull-down network in the D-to-Q path are symmetrically sized (see Section 2.3.1),

• transistors of the pulse generator (W P G ) are sized in order to achieve a FO3 fall and rise time for the pulse signal,

• on the contrary to [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF], the gate width of the output inverter (W drive ) is an input of the sizing algorithm in order to be more realistic compared to an industrial standard-cell library,

• the rest of the transistors are minimally sized.

APPENDIX C TESTBENCH FOR REGISTER FILE

The testbench used to compute the delay and energy performances of the register files was developed with a commercial electrical simulator, using the RCc extractions of the register file layouts. As a reminder, the input-output ports for each 16 × 32b register file are:

• [1 bit] clock, write-enable, reset, scan-enable,

• [4 bits] read-addr1, read-addr2, write-addr,

• [32 bits] write-data, write-data-scan,

• [output 32 bits] read-data1, read-data2

Similarly to the testbench in Annex B, each of the input presents a FO3 input slope and each of the output is connected to three identical inverters of the same drive as the FFs inside the register file (see figure C.1).

The clock signal is generated thanks to a FO3 input slope on the gate of the first inverter (or buffer) of the clock tree. Notice that the input clock signal is not connected directly to the FFs. The write-enable signal rises to V dd during a writing cycle and then goes back to gnd. It allows us to take into account the dynamic energy induced by the write-enable signal during writing operations. After a global reset at the beginning of the simulation, the reset signal is tied to inactive value, as well as the scan-enable signal.

The write-addr signal changes from 0110 to 1001 during the writing cycle, thus performing a maximum activity, and is then maintained during the rest of the operations. During the first reading cycle, read-addr1 passes from 0110 to 1001 and the read-data1 output is sensed. In addition to performing a maximum data activity for the energy computation, we compute the read-access-time1 which is by definition the worst propagation time between the read-address change and the output signal switching. In the second reading cycle, read-addr2 goes from 0110 to 1001 and both the read energy and access-time is computed.

The write-data signal is a random chain of 32bits with equal number of 0 and 1. None of the 32 input bits changes in the first writing cycle and all of them vary Data Clk Write_addr

Read-addr1

Read-addr2

Scan-Data

Read-data1

Read-data2 in the second cycle. This emulates a 0% and 100% data input rate activity factor (α rate ), the probability of the inputs to flip their state during a clock cycle. The 32 bits of write-data-scan signal are kept at constant values.

Finally, the delay is defined as the worst read-access-time between read-access-time1 and read-access-time2. where i = 0, ..., 31. The writing-access is not computed because it would have needed a bisection method with several iterations to defined the setup time.

Because of the huge netlist provided after layout extraction, the needed computation time would have been too high. Nevertheless, the inputs are directly connected to the FF inputs and we know from previous chapters that the Dto-Q performance of pulsed-FFs is highly superior of the timing performance of master-slave flip-flops.

The energy per operation is the combination of several computed energies coming from several clock cycles. In the first clock cycle, a global reset is performed followed by a writing operation with known data values. No energy is computed. In the second clock cycle, the write-enable signal is activated but a zero data activity is seen on the inputs. The energy is the integration of the supply plus input currents: E w0 . In the third clock cycle, a writing with 100% data rate activity is performed, giving E w100 . In the fourth clock cycle, we read a new set of 32 bits from the output signal 1 E r1 . Because of the 100% activity imposed in the previous cycle, all the read output values switch after the read-address change. And in the last clock cycle, we read a complete new set of 32 bits from the output signal 2 E r2 where, again, every output switches.

As a read operation is asynchronous, we only computed the read-energy until the end of the output switch. Indeed, the supply current I dd is not integrated over the whole read clock cycle since the leakage energy has already been taken into account in the write-energy computation. More precisely, the end of the integration is the time when:

dI dd dt < 1000 & (I dd < 0.1I dd,max || I dd < 2I dd,end )
where I dd,max is the maximum supply current reached during the read clock cycle and I dd,end the supply current computed at the end of the read clock cycle.

Finally, the energy per operation is defined as:

E op = α rate E w100 + (1 -α rate )E w0 + α rate ( E r1 + E r2 2 ) (C.2)
Avec l'explosion du marché des applications portables et le paradigme de l'Internet des objets, la demande pour les circuits à très haute efficacité énergétique ne cesse de croître. Afin de repousser les limites de la loi de Moore, une nouvelle technologie est apparue très récemment dans les procédés industriels afin de remplacer la technologie en substrat massif ; elle est nommée fully-depleted silicon on insulator ou FDSOI. Dans les circuits numériques synchrones modernes, une grande portion de la consommation totale du circuit provient de l'arbre d'horloge, et en particulier son extrémité : les bascules. Dès lors, l'architecture adéquate de bascules est un choix crucial pour atteindre les contraintes de vitesse et d'énergie des applications basse-consommation. Après un large aperu de l'état de l'art, les bascules à impulsion explicite sont reconnues les plus prometteuses pour les systèmes demandant une haute performance et une basse consommation. Cependant, cette architecture est pour l'instant fortement utilisée dans les circuits à haute performance et pratiquement absente des circuits à basse tension d'alimentation, principalement à cause de sa faible robustesse face aux variations.

Dans ce travail, la conception d'architecture de bascule à impulsion explicite est étudiée dans le but d'améliorer la robustesse et l'efficacité énergétique. Un large panel d'architectures de bascule, avec les fonctions reset et scan, a été comparé dans le domaine énergie-délais, à haute et basse tension d'alimentation, grce à une méthodologie de dimensionnement des transistors. Il a été montré que la technique dite de polarisation face arrière, l'un des principaux avantages de la technologie FDSOI, permettait des meilleures performances en énergie et délais que la méthodologie de dimensionnement. Ensuite, comme le générateur d'impulsion est la principale raison de dysfonctionnement, nous avons proposé une nouvelle architecture qui permet un très bon compromis entre robustesse à faible tension et consommation énergétique. Une topologie de bascule à impulsion explicite a été choisie pour être implémentée dans un banc de registres et, comparé aux bascules maître-esclave, elle présente une plus grande vitesse, une plus faible consommation énergétique et une plus petite surface.

D.1 INTRODUCTION

Les applications portables, telles que les smartphones, les tablettes et les téléphones portables, ainsi que les circuits à très basse consommation, tels que les puces RFID, les réseaux de capteurs sans fils et les applications biomédicales, portent vritablement l'industrie de la micro électronique aujourd'hui. Dans ces applications, le microprocesseur est connecté à une batterie ou un système de récupération d'énergie, ce qui signifie, dans les deux cas, une énergie limitée d'énergie et de puissance disponible. Par conséquent, l'efficacité énergétique est d'une importance capitale pour la conception de ce type de circuits.

La technologie appelée FDSOI est apparue récemment dans les procédés industriels, afin de surmonter les limites de la technologie en substrat massif. Grâce à son meilleur contrôle électrostatique du canal des porteurs, cette technologie apporte une plus faible capacité de jonction, une pente sous-seuil plus raide, une plus faible variabilité et une très performante technique : la polarisation face arrière sur une très large gamme de tensions. Cette polarisation face arrière permet de modifier dynamiquement la tension de seuil des transistors de manière réversible. En conséquent, cette technologie convient parfaitement aux circuits à haute efficacité énergétique et très basse consommation.

Dans les circuits numériques synchrones modernes, le nombre de bascule a littéralement explosé avec la montée en puissance de nouvelles techniques micro-architecturales. Ainsi, l'architecture de bascule a un rôle et un impact décisif sur les performances temporelles ainsi que la consommation énergétique du processeur. Les bascules à impulsion explicite présentent de remarquables caractéristiques temporelles, permettant de gagner une part non-négligeable du cycle d'horloge. En même temps, sa consommation énergétique peut être drastiquement réduite par le partage du générateur d'impulsion. Jusqu'alors, cette structure est presque complètement absente des circuits travaillant à très basse tension d'alimentation, pour lesquelles les architectures de type maitre-esclave sont principalement utilisées. Les deux principales raisons en sont :

• Une plus faible robustesse face aux variation local dans la génération de l'impulsion,

• Un temps de maintien (hold time en anglais) positif, provoquant des tampons en délais additionnels et donc une surconsommation énergétique.

Dans le but d'améliorer les performances des circuits à haute efficacité énergétique, d'un point de vue à la fois en vitesse et en consommation, ce travail étudie et analyse des innovations architecturales pour surmonter et résoudre ces deux désavantages.

L'étude est menée par les deux questions suivantes :

• Comment obtenir des bascules robustes et efficaces en énergie à très basse tension d'alimentation ?

• Comment la technologie FDSOI peut-elle nous aider à améliorer la robustesse et l'efficacité énergétique ?

Le manuscrit est articulé autour de quatre chapitres principaux qui sont repris de manière succincte dans ce résumé étendu :

Dans le chapitre 1, la technologie FDSOI et tous ses avantages sont présentés en détails. Ensuite, nous dressons un état de l'art des quatre topologie de bascule CMOS. Les configurations maitre-esclave, différentielle, à impulsion et à doublefront sont illustrées avec des architectures de bascule de la littérature scientifique. Pour chacune d'entre elles, les avantages et désavantages sont expliqués et ensuite résumés. A la fin du chapitre, nous pointons la structure de bascule à impulsion explicite comme candidate prometteuse pour augmenter les performances des circuits à haute efficacité énergétique. Cette topologie souffre néanmoins de deux principaux inconvénients, à savoir la robustesse et le temps de maintien positif, qui sont traités dans le chapitre 3 et 4, respectivement.

Dans le chapitre 2 sont comparées six architectures prometteuses pour nos applications, dans le plan énergie-délais. L'architecture appelée C 2 MOS-Data se révèle comme la plus efficace énergétiquement sur une large gamme de tension d'alimentation. Après cela, nous montrons comme la polarisation face arrière, permise par la technologie FDSOI, peut apporter de meilleures performances en énergie et délais que la méthodologie de dimensionnement utilisées précédemment. Enfin, des mesures sur silicium viennent confirmer les résultats précédemment obtenus.

Le chapitre 3 commence par expliquer le compromis inhérent des structures à impulsion à très basse tension d'alimentation. Pour assurer une robustesse suffisante, une surconsommation énergétique est payée sous plusieurs formes. Pour contourner ce problème, nous proposons une nouvelle architecture de générateur de délais (GD), basée sur la technique du current-starved, présentant assez de degrés de liberté pour atteindre la robustesse désirée sans pénalité de consommation. Ensuite, des simulations post-layout et des mesures sur silicium montrent comment notre structure de GD améliore significativement la robustesse des bascules à impulsion.

Dans le chapitre 4 est premièrement présentée et expliquée une technique de capture conditionnelle. Sachant le générateur d'impulsion (GI) est le plus grand consommateur d'énergie au sein des bascules à impulsion, cette technique attaque très efficacement la consommation énergétique de la bascule. Par ailleurs, les courbes d'efficacité énergétique montrent que l'énergie par opération obtenue grâce à cette technique est plus petite que celle des architectures maitre-esclaves. Ensuite, après avoir confirmé l'efficacité du partage de la génération d'impulsion, nous intégrons des innovations précédemment exposées, à savoir le rapide et énergie-efficace latch, le robuste et énergie-efficace générateur de délais et le GI partagé, afin d'implémenter un banc de registre. Ce banc de registre basé sur des structures de bascules à impulsion présente une plus grande vitesse, une plus faible consommation énergétique et une plus petite surface qu'un banc de registre basé sur des bascules maitre-esclave.

Finalement, nous terminons par une conclusion résumant ce travail. • Une capacité de jonction fortement réduite [START_REF] Bol | Sub-45nm Fully-Depleted SOI CMOS Subthreshold Logic for Ultra-Low-Power Applications[END_REF][START_REF] Kilchytska | On The UTBB SOI MOSFET Performance Improvement In Quasi-Double-Gate Regime[END_REF].

• Un meilleur contrôle électrostatique de la grille et de la face arrière sur le canal. Cela a pour conséquence une meilleure pente sous-seuil et un meilleur effet de substrat, ainsi que la réduction des effets canaux courts, comme le DIBL.

• Une disparition de la jonction PN entre les sources et drain et le substrat.

Cela signifie que nous ne sommes plus limité aux 0,3V de différence de tension comme en technologie en substrat massif. Il a été montré sur silicium qu'il est possible d'appliquer une tension de substrat jusqu'à 2 volts sans claquage électrique [START_REF] Wilson | A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking[END_REF]. De plus, cela signifie que l'on peut, durant la vie du circuit, dynamiquement varier cette tension de substrat et donc la tension de seuil et les propriétés électriques des transistors. • Contrairement à la technologie en substrat massif, il n'y a plus d'atome dopant dans le canal du transistor FDSOI. Grâce à cela, la variabilité intrinsèque du transistor est fortement réduite [START_REF] Weber | High immunity to threshold voltage variability in undoped ultrathin FDSOI MOSFETs and its physical understanding[END_REF]. De plus dans [START_REF] Noel | Multi-VT UTBB FDSOI Device Architecture for Low Power CMOS Circuit[END_REF], les auteurs expliquent comment obtenir trois tensions de seuil différentes (pour NMOS et PMOS) en jouant sur le dopage de la face arrière. Il est donc possible d'obtenir la même diversité qu'en substrat massif, tout en conservant une faible variabilité.

D.1.2 État de l'art des bascules

La bascule est l'élément fondamental des circuits numériques synchrones. Ces dernières années, leur nombre au sein des circuits a littéralement explosé du fait de nouvelles techniques microarchitecturales, comme le pipelining, les architectures super-scalaires et les techniques de time-borrowing. De ce fait, les bascules ont un rôle déterminant sur la vitesse, l'énergie, la surface et la robustesse des circuits. On estime que 50% à 70% de la consommation totale provient de l'arbre d'horloge [START_REF] Paik | Implementation of pulsed-latch and pulsedregister circuits to minimize clocking power[END_REF][START_REF] Magen | Interconnect power dissipation in Microprocessor[END_REF], et 80% de l'énergie dynamique de l'arbre est située au niveau des bascules [27]. Ainsi donc, l'architecture des bascules est un élément primordial que les concepteurs de circuits doivent prendre en compte pour concevoir un circuit à haute efficacité énergétique.

Nous allons maintenant présenté l'état de l'art des architectures de bascule présentes dans la littérature scientifique. Les bascules peuvent être cataloguées en quatre grandes catégories : maitre-esclave, différentielle, à impulsion, doublefront.

D.1.2.1 Maitre-esclave

Les bascules maitre-esclave sont composées de deux latch, non nécessairement identiques, placés en série (voir figure D.2. La donnée d'entrée (D) est connecté au latch maitre qui est actif sur niveau bas de l'horloge. Lors du front montant,

Q Q D D CLK CLK CLK
(a) Structure basique de bascule SAFF [START_REF] Yuan | New single-clock CMOS latches and flipflops with improved speed and power savings[END_REF].

Q Q D D CLK CLK CLK S R S R R S S S R R (b
) Topologie améliorée de SAFF [START_REF] Nikolic | Sense amplifier-based flip-flop[END_REF]. le latch maitre devient bloqué et transmet l'information de la donnée au latch esclave devenant passant. Ce dernier transmet l'information à la sortie (Q) de la bascule pour l'étage suivant du circuit et la maintiendra jusqu'au prochain front montant de l'horloge. Le temps de setup dépend donc principalement de la vitesse de commutation du maitre, tandis que le temps de propagation entre les fronts d'horloge et de sortie (Clk-Q) dépend de l'esclave. Le temps de maintien est, pour des conditions d'utilisation normales, toujours positif car comme le maitre est fermé après le front de l'horloge, une variation de l'entrée n'influe en rien la sortie.

Q Q D D CLK K CLK S R S R R S (
Le temps de propagation entre l'entrée et la sortie (D-Q) est la somme du temps de setup plus le Clk-Q. La donnée devant passer deux latch, ce type de bascule est relativement lent par rapport aux autres catégories. De plus, le temps D-Q explose lorsque l'on diminue la tension d'alimentation. Les bascules de type maitre-esclave ne semblent donc pas appropriées pour la haute performance à très faible tension. Ces bascules sont extrêmement rapides, surtout comparées aux maitre-esclave. Néanmoins, elles nécessitent une pré-charge à chaque cycle d'horloge, quelque soit la valeur de la donnée. Cela augmente sensiblement la consommation énergétique et n'est pas adapté à la haute efficacité énergétique. De plus, elles sont très peu robustes lorsque l'on diminue la tension d'alimentation. En effet, il y a toujours un noeud auquel une pile de transistor NMOS est connectée et, lors de l'écriture, tente de décharger ce noeud pendant que un ou plusieurs transistors PMOS tentent de le maintenir à la tension d'alimentation. La réduction de la tension d'alimentation, combinée aux variations de procédé de fabrication, rend cette catégorie de bascule caduque pour notre application.

D.1.2.3 A impulsion

Les bascules à impulsion sont composées d'un seul latch ouvert pendant une courte période après le front montant de l'horloge. Elles ne fonctionnent pas à proprement parlé sur un front d'horloge, mais pendant une impulsion suivant le front. Ce comportement est obtenu grâce à l'utilisation d'un signal d'horloge retardé, dont le retard définit la largeur de l'impulsion. De part l'architecture, si la donnée change légèrement après le front d'horloge, elle peut être échantillonnée par la bascule. Cela signifie que le temps de setup est négatif, mais en contrepartie, le temps de maintien est positif.

Au sein de cette catégorie, il existe deux grandes familles : les implicites et les explicites.

Les bascules à impulsion implicite ont leur génération d'impulsion intégrée directement dans le latch (voir figure D.4). Cette génération intégrée permet de consommer légèrement moins que leurs pendants explicites, mais néanmoins, les architectures implicites nécessitent un minimum de trois transistors empilés pour transmettre l'information de l'entrée à la sortie.

Les architectures explicites ont un générateur d'impulsion qui peut être facilement discerné de l'architecture du latch plus que leurs pendants implicites. Néanmoins, elles ne nécessitent que de deux transistors minimum pour transmettre l'information de l'entrée à la sortie.

D.1.2.4 Double-front

Les bascules double-front, ou dual-edge en anglais, échantillonnent la donnée en entrée non pas sur un front -montant ou descendant -de l'horloge, mais sur les deux fronts. Comme conséquence directe, cela permet de diviser l'énergie dynamique de l'arbre d'horloge par deux, pour un même débit dans la logique combinatoire.

Chaque architecture des sections précédentes pourraient être adaptée en double-front. Néanmoins, [START_REF] Tschanz | Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors[END_REF] a montré que pour certaines topologies, la charge d'horloge est multipliée par deux ou plus, et donc le bénéfice d'une fréquence de commutation divisée par deux est annihilé. La littérature montre également que le moyen le plus efficace d'implémenter la fonction double-front est de modifier le générateur d'impulsion des bascules à impulsion explicite (voir figure D.6).

Par ailleurs, ce système de fonctionnement demande un rapport cyclique identique entre le niveau haut et le niveau bas de l'horloge, afin de ne pas dé-balancer la contrainte en temps du circuit. Or, cette contrainte est très difficilement atteignable à très basse tension d'alimentation, où la variabilité locale devient prépondérante. Cette fonctionnalité sera donc difficilement implémentable pour les applications visées.

Impulsion explicite

Les architectures de bascule à impulsion explicite présentent plusieurs avantages que nous résumons ici :

• Elles sont rapides car ne présentant qu'un seul latch dans le chemin de propagation entrée-sortie,

• Elles ont néanmoins une consommation énergétique raisonnable car ne nécessitent pas de pré-charge à chaque cycle d'horloge,

• Par rapport aux impulsion implicites, elles sont plus rapides car demandant un empilement moins grand mais consomment un peu plus. Néanmoins, nous pouvons remarquer que le signal d'impulsion (P ulse sur la figure D.5) peut être partagé sur plusieurs latch en parallèle, afin de diminuer la consommation par bascule.

Néanmoins, cette topologie présente deux grands désavantages : Le temps de maintien est positif. Cela signifie que, lors de la synthèse et du placement et routage du circuit, les outils automatiques vont devoir insérer des tampons en délais sur les chemins courts afin de garantir la contrainte de maintien. Cela amènera une surconsommation en énergie et en surface.

Le deuxième problème, directement lié à l'architecture, est la variabilité du signal d'impulsion. En effet, le délais généré étant soumis à la variabilité locale comme tout signal, il est possible que le signal d'impulsion n'atteigne pas une tension suffisante pour permettre l'ouverture du latch. Cela signifie que, quelque soit la fréquence de fonctionnement du circuit, la bascule ne sera jamais fonctionnelle.

Ces deux problèmes seront traités dans la section D.3 grâce à la technique du current-starved.

Dans la suite, la conception de bascules à impulsion explicite et haute efficacité énergétique en technologie FDSOI est étudiée. Comme il a été vu, l'étude peut être séparée entre le latch et le générateur d'impulsion, qui seront par conséquent le sujet des deux prochaines sections.

D.2 COMPARAISON D'ARCHITECTURES

Après avoir parcouru l'état de l'art de la littérature, nous avons sélectionné six architectures qui répondent à nos contraintes. Ces dernières sont :

Pulse R W PG W PG W 1 W 1 W 2 W 2 W 2 W 2 β PN W 2 β PN W 2 β PN W 2 β PN W 2
For TGPL W drive

W PG W PG W PG W PG W 1 W 1 W 1 W 1 W 2 W 2 β PN W 2 β PN W 2
For TGPL W drive L'architecture de la figure D.9 est une modification de l'architecture CDFF proposée dans [START_REF] Zhao | High-Performance and Low-Power Conditional Discharge Flip-Flop[END_REF], afin qu'elle répondent à nos critères précédemment cités. Nous pouvons noter que cette architecture n'a besoin que du signal d'impulsion P ulse, et non de son complémentaire logique. De la même manière, la figure D.10 représente une autre version de l'architecture CP 3 L proposée dans [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF].

int Q int Q int Q int W PG W PG W PG W PG W 1 W 1 W 1 W 1 W 1 W 1 W 2 W 2 W 2 W 2 W 2
F CP F CP R S N R N R N S N R N S N R R Q D W 1 β PN W 2 β PN W 2 β PN W 2 W 2 W 2 W 2 β PN W 1 W PG W PG W drive
Dans la suite, nous allons comparer ces architectures dans l'espace énergiedélais, grâce à leur courbe d'efficacité énergétique (CEE).

D.2.1 Comparaison dans le plan énergie-délais

Ces six architectures ont été comparées dans le domaine énergie-délais (E -D) grce à un algorithme de dimensionnement, selon la méthode présentée dans [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF]. Cette méthode consiste à déterminer les points de dimensionnement qui donnent une valeur optimale à une figure de mérite donnée. A partir de ces points, nous pouvons inter-et extrapoler la courbe d'efficacité énergétique (CEE), présentant une forme d'hyperbole [START_REF] Zyuban | A Unified methodology for resolving powerperformance tradeoffs at the microarchitectural and circuit levels[END_REF]. Il est à noter que la principale différence entre notre banc de test et celui utilisé dans [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF], est l'utilisation d'une métrique différente pour le temps de setup. Cette dernière est basée sur le temps de transition de la sortie et convient parfaitement pour les bascules à impulsion [START_REF] Bernard | An efficient metric of setup time for pulsed flip-flops based on output transition time[END_REF].

Comme nous visons la large gamme de tension, les architectures de bascules à impulsion ont été comparées à tension d'alimentation nominale et à très faible tension, pour des tensions de substrat nominales, soit Gnds= Vdds = 0V. Nous voyons que les architectures *-Data produisent la plus faible consommation d'énergie, avec la C 2 MOS légèrement meilleure que la TGPL. Durant une transition de la C 2 MOS, les noeuds intermédiaires de l'inverseur trois-états d'entrée ne sont pas complètement chargés ou déchargés, parce que la tension grille-source du premier transistor de l'empilement diminue graduellement en dessous de la tension de seuil. Par conséquent, l'architecture C 2 MOS sauvegarde de l'énergie dynamique dans la charge et décharge des capacités de jonction proportionnelles à W 2 (voir figure D.7). Cette consommation dynamique plus faible permet aux architectures C 2 MOS d'atteindre un plus grand W k , donc une plus grande vitesse, pour la même énergie. Néanmoins, les C 2 MOS sont finalement dépassées par les topologies TGPL dans la région haute performance, car les deux transistors de la porte de transmission aident à l'augmentation de la vitesse. Les architectures *-Clk produisent un meilleur compromis E -D dans la région haute performances, grce à leur empilement d'entrée plus faible. Enfin, notons que les deux dernières structures présentent un compromis beaucoup moins intéressant sur tout l'espace E -D.

D.2.1.1 Tensions de bias nominales

Les courbes d'efficacité énergétique extraites à très faible tension d'alimentation -0.35V, fournissant l'énergie par opération minimum pour la technologie 28nm FDSOI -sont représentées à la figure D.12. Ici la température est de 25 • C car l'auto-échauffement des circuits à très basse consommation est pratiquement négligeable, et ces circuits fonctionnent normalement à température ambiante.

Nous voyons que la courbe C 2 MOS-Data est la plus efficace en énergie sur presque tout le plan E -D, excepté dans la région de très haute performance. Grce à son empilement, cette architecture exhibe un très faible courant de fuite, qui devient extrêmement significatif à très basse tension et donc impacte fortement la consommation.

À très faible tension d'alimentation, les architectures de type TGPL sont moins efficaces en énergie sur tout le plan E -D. En plus de présenter un courant de fuite plus de grand que les architectures de type C 2 MOS, leur bénéfice en vitesse est mis en péril par le régime sous seuil. En effet, durant une transition, la tension grille-source V GS de l'un des transistors de la porte de transmission diminue progressivement. Comme il dépend exponentiellement de V GS dans le régime sous-seuil, le courant de drain de l'un des transistors est très vite déjà négligeable après le début de la transition. Cela mène à une architecture de type C 2 MOS, avec de plus capacités de jonction dans le chemin entrée-sortie.

A nouveau, les deux dernières structures présentent un compromis beaucoup moins intéressant sur tout l'espace E -D. Le fait que la structure CP 3 L présente un moins bon produit énergie-délais (PED), en opposition aux résultats de [START_REF] Consoli | Conditional Push-Pull Pulsed Latches With 726fJ.ps Energy-Delay Product in 65nm CMOS[END_REF], montre que les fonctionnalités de reset et surtout de scan peuvent changer les conclusions de la comparaison. Ainsi, cela prouve que la facilité d'implémenter la fonction scan doit être prise en compte dans le choix de l'architecture de la bascule.

D.2.1.2 Modification de la tension de bias

Dans la section précédente, nous avons vu que pour être le plus efficace en énergie sur tout le plan E -D, nous avons besoin de plusieurs architectures et surtout de plusieurs points de dimensionnement. Toutes ces architectures dimensionnées devront être caractérisées pour plusieurs conditions PVT, et cela pourrait significativement augmenter le temps de conception.

Cependant, ce compromis entre temps de développement et efficacité énergétique peut être presque complètement éviter grce à la technologie FD-SOI. Les figures D. [START_REF] Pelgrom | Different faces of variability[END_REF] consommation énergétique, que le délais obtenu par la méthode de dimensionnement. De la même façon dans la région basse-puissance, la consommation est plus petite pour le même délais que l'énergie consommée par le dimensionnement minimum des transistors. À très faible tension, l'impacte de la tension de seuil sur le courant en mode passant, est presque aussi important que sur le courant de fuite en mode bloqué. Par conséquent, une augmentation (diminution) du délais entraine une diminution (augmentation) du courant de fuite. L'énergie de fuite étant le courant de fuite intégré sur une période d'horloge, l'énergie par opération ne varie pas de manière importante dans la région basse-puissance, i.e. pour une polarisation arrière en inverse, et donc reste relativement la même que celle à tension de face arrière nominale. D'un autre côté, le gain en délais est relativement bien plus grand à très faible tension qu'à tension d'alimentation nominale. Tout cela montrent clairement que nous pouvons moduler les performances en énergie et délais plus efficacement que par la méthodologie de dimensionnement, et de plus, de manière dynamique durant la vie du circuit.

D.2.2 Intégration dans le flot et résultats de mesure

Une architecture de bascule à impulsion explicite a été dessinée, caractérisée et incorporée dans le flot de conception du circuit FRISBEE [START_REF] Wilson | A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking[END_REF]. Il faut tout d'abord noté, qu'aucun problème additionnel majeur ne fut rencontré durant ces étapes. Les outils automatiques ont correctement interprété nos bascules à impulsion, pourtant fort différentes des bascules maitre-esclave classiques. Ensuite, il est à souligner que les mesures de FRISBEE ont montré des performances en vitesse et en consommation qui surpassaient, comme attendu, celles de l'état de l'art.

En parallèle de ça, des architectures de bascule isolées ont été fondues sur silicium afin d'étudier plus précisément les caractéristiques des bascules elles-mêmes. Pour chaque architecture, nous avons pu mesuré le délais de propagation de 63 Voilà pourquoi, j'ai proposé un générateur de délais (GD) basé sur la technique du current-starved [START_REF] Zhang | A low variation GHz ring oscillator with additionbased current source[END_REF]. L'architecture est présentée à la figure D.19. Notre GD présent seulement trois étages dans le chemin de délais, mais augmente le délais moyen grce aux transistors current-starved placé entre les inverseurs et la leur tension d'alimentation. Comme ces transistors toujours ouverts ne sont pas dans le chemin de délais, ils n'impactent pratiquement pas la dispersion du délais. Ainsi, cette architecture current-starved peut être vue comme une translation sans expansion de la fenêtre de délais sur la ligne du temps. Cette translation sans expansion est le point clé permettant de garantir une robustesse suffisante sans surconsommation énergétique.

Insistons encore une fois sur le fait que les tailles des transistors currentstarved sont des degrés de liberté réellement puissants et faciles à manier.

D.3.1 Comparaison de générateur de délais

Les figures D.21 et D.22 comparent le compromis énergie-robustesse entre plusieurs architecture de GD de l'état de l'art et notre architecture currentstarved avec un dimensionnement donné. Chaque architecture présente un plus grand délais minimum, càd robustesse, que l'architecture conventionnelle. Néanmoins, c'est notre architecture de GD qui exhibe le plus petit délais maximum, càd consommation, après l'architecture basique.

Ensuite alors, nous avons comparé la robustesse de notre GD current-starved et le GD classique grâce à des simulations post-layout. Comme montré au tableau D.3, nous obtenons une amélioration substantielle de la robustesse de la bascule grâce à notre architecture de générateur de délais.

Afin de démontrer encore plus cette amélioration, la section suivante présente des résultats silicium qui corroborent ces dires.

D.3.2 Robustesse : mesures silicium

Une puce de test a été fabriquée en technologie 28nm FDSOI pour tester la fonctionnalité d'une bascule pour des paramètres vdd, vdds et gnds donnés. À nouveau, 64 bascules réparties uniformément sur la galette de silicium ont pu être mesurées afin d'étudier statistiquement les tensions extrêmes de fonctionnement. Comme montré à la figure D.24, la décroissance le long de la diagonale 2 s'explique par le débalancement entre les transistors NMOS et PMOS [START_REF] Alioto | Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Stdandard Cells[END_REF]. En effet, les tensions de seuil de ces deux transistors évoluent dans des directions opposées le long de cette diagonal. Il en va donc de même pour le rapport des courants en état passant et bloqué. La décroissance du rendement vers le coin supérieur gauche s'explique également par la diminution du rapport des courants, mais pour une raison différente. Le long de la diagonal 1, les tension de substrat sont symétriques et donc les courants évoluent dans la même direction. Néanmoins, diminuer la tension de seuil des transistors peut mener à un transistor avec une tension de [START_REF] Xiang | Design of a low-power pulsetriggered flip-flop with conditional clock technique[END_REF]. En utilisant la propriété d'impulsion explicite, une porte XOR est ajoutée à l'entrée du GI afin de désactiver la génération de l'impulsion quand à la fois l'entrée (D) et la sortie courante (Q) sont identiques, càd quand la capture n'est pas nécessaire.

Notons que, maintenant, le temps de setup et de maintien sont, respectivement, positif et négatif. En effet, la donnée doit maintenant être valide suffisamment tt avant le front déclencheur de l'horloge tel que le signal disable rende le GI actif. Cela signifie que cette architecture résout le problème de temps de maintien positif des bascules à impulsion.

D.4.2 Partage du générateur d'impulsion

Le partage du générateur d'impulsion (GI) a été étudié un certain nombre de fois d'un point de vue de l'efficacité énergétique [START_REF] Ashna | Design of low power clocking system using merged flip-flop technique[END_REF][START_REF] Lin | Pulsed-Latch Utilization for Clock-Tree Power Optimization[END_REF][START_REF] Chang | Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating[END_REF][START_REF] Paik | Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power[END_REF]. L'objectif de partager un GI avec N latches est d'obtenir une plus faible consommation énergétique que utiliser 2N latches avec une topologie maitre-esclave. La plupart des papiers dans la littérature travaillent dans le régime bien au-dessus du seuil, où les variations aléatoires peuvent être plus facilement traitées pour garantir une pente suffisante du signal d'impulsion après l'étape du placement et routage. Dans les régimes opération moyenne E op est plus petite pour le BR contenant les bascules à impulsion. Ensuite, leur plus grand courant de fuite mène à une plus petite E op pour le BR contenant les MEs. En effet, à faible tension, la puissance statique de fuite représente une part de plus en plus important de l'énergie totale, et donc le courant de fuite pénalise notre structure de BR basé sur les bascules à impulsion.

D.5 CONCLUSIONS

Dans ce travail, des architectures de bascules à impulsion robuste et efficace en énergie, visant la très large gamme de tension d'alimentation et les circuits très basse consommation, ont été développées et conçues en technologie FDSOI.

En premier lieu, la topologie de bascule à impulsion explicite a été mise en évidence parmi la littérature scientifique au chapitre 1. Cette architecture présente de remarquables propriétés temporelles, càd petit délais entrée-sortie, temps de setup négatif, facilités d'implémentation des techniques de time-borrowing et de double-front, ainsi qu'un générateur d'impulsion partageable. Néanmoins, cette topologie est rarement utilisée dans les circuits fonctionnant à très basse tension à cause de deux principaux désavantages :

• La faible robustesse aux variations environnementale comparé aux structures maitre-esclave -problème traité au chapitre 3,

• le temps de maintien positif qui induit une surconsommation énergétique de par l'insertion de tampons en délais -problèmes traités au chapitre 4.

Au chapitre 2, une comparaison juste et rigoureux de six architectures, semblant les plus prometteuses de l'état de l'art, a été effectuée dans le domaine énergie-délais pour mettre en évidence l'architecture la plus efficace en énergie. Si l'architecture TGPL-Clk présente la meilleure efficacité énergétique pour les opérations haute vitesse, c'est l'architecture C 2 MOS-Data qui s'est révélée l'architecture de bascule à impulsion la plus efficace en énergie sur une large gamme de délais et tension d'alimentation.

Dans le chapitre 3, le compromis fondamental entre la robustesse et la consommation énergétique d'une bascule à impulsion est expliqué et un générateur de délais (GD) utilisant la technique du current-starved a été proposé pour surmonter ce problème. Il a été montré que notre GD proposé améliore sensiblement la robustesse des bascules à impulsion, ce qui était l'un des deux désavantages majeurs. De plus, cette structure est très flexible et offre plusieurs degrés de liberté aux concepteurs de circuit. Des mesures sur silicium ont permis de comparer le rendement fonctionnel et la tension d'alimentation (V dd ) minimum de différentes bascules, et ont montré que notre architecture de GD permet d'atteindre une augmentation du rendement moyen de 7.5% pour une mme V dd et un rendement moyen identique obtenu à une tension d'alimentation jusqu'à 45mV plus petite que sans la technique du current-starved.

Dans le chapitre 4, une technique de capture conditionnelle a été présentée et implémentée dans la bascule efficace en énergie du chapitre 2. Ensuite, une comparaison dans le domaine énergie-délais a montré que cette architecture de bascule à impulsion présente une dissipation d'énergie plus petite que les topologies maitre-esclaves, et un temps de maintien positif. Le second inconvénient des bascules à impulsion est donc partiellement résolu grce à cette architecture. Finalement, un banc de registre, basé sur les bascules robustes et efficaces en énergie provenant des innovations des chapitres précédents, est comparé à un banc de registre contenant des bascules maitre-esclaves. Cette comparaison a montré que nos bascules à impulsion explicite fournissait une surface et une consommation d'énergie inférieures, tout en garantissant une robustesse suffisante dans le régime sous-seuil.

En conclusion, nous avons conçu des architectures de bascules à impulsion explicites très efficace en énergie, à savoir la TGPL-Clk, C 2 MOS-Data et C 2 MOS-Xor, dédiées respectivement à la très haute performance, l'efficacité énergétique et la très faible puissance. La technologie FDSOI, à travers la technique de polarisation face arrière, permet de modifier dynamiquement les performances en énergie et en délais des bascules, en fonction des contraintes courantes du circuit. L'efficacité énergétique est préservée durant la synthèse grce à la technique de capture conditionnelle présentée. Finalement, la robustesse à très basse tension est assurée par la faible variabilité du FDSOI, le choix adéquat de la polarisation face arrière -grce à notre étude du rendement fonctionnel -et notre architecture innovante de générateur de délais.

Figure 1 . 1 :

 11 Figure 1.1: Conventional Bulk transistor (NMOS).

Figure 1 . 2 :

 12 Figure 1.2: Discrete threshold voltage distribution in the transistor channel [13].

Figure 1 . 3 :

 13 Figure 1.3: Minimum energy point increases with further technological node because of the higher variability [2].

Figure 1 . 4 :

 14 Figure 1.4: FDSOI transistor (NMOS version).

Figure 1 . 5 :

 15 Figure 1.5: The flip-flop principle and its figures of merit.

Figure 1 . 6 :

 16 Figure 1.6: Conventional master-slave architectures. TGFF gives the best tradeoff between speed performances and pass-through phenomena.

  The push-pull D-flip-flop[START_REF] Ko | High-Performance Energy-Efficient D-Flip-Flop Circuits[END_REF]. The push-pull Isolation D-flip-flop[START_REF] Ko | High-Performance Energy-Efficient D-Flip-Flop Circuits[END_REF]. The gated master slave FF (GMSL)[START_REF] Markovic | Analysis and design of low-energy flipflops[END_REF].(d) Contention-less flip-flops (CLFF) dedicated to specific applications[START_REF] Fuketa | 12.7-times Energy Efficiency Increase of 16-bit Integer Unit by Power Supply Voltage Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF) and Separated V DD between Flip-Flops and Combinational Logics[END_REF]. Race-Free NANDbased D flip-flop[START_REF] Piguet | Low Power Electronics Design[END_REF].

Figure 1 . 7 :

 17 Figure 1.7: Novel master-slave architectures proposed in the literature.

Figure 1 . 8 :Figure 1 . 9 :

 1819 Figure 1.8: The differential flip-flop principle (master-slave-based).

  c) With modified output part.

Figure 1 . 10 :

 110 Figure 1.10: Differential sense-amplifier based flip-flops.

Figure 1 . 11 :

 111 Figure 1.11: Differential master-slave flip-flops [35].

Figure 1 . 12 :

 112 Figure 1.12: The pulse-triggered flip-flop principle. During the pulse period, the flip-flop behaves essentially like a level-sensitive latch.

  Sense-amplifier based implicit pulsetriggering structures[START_REF] Xia | Differential CMOS edge-triggered flip-flop with clockgating[END_REF]. Hybrid-latch flip-flop (HLFF)[START_REF] Stojanovic | Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems[END_REF].

  Semi dynamic flip-flop (SDFF)[START_REF] Stojanovic | Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems[END_REF]. Implicit-pulsed data-close-to-output (ipDCO) semi-dynamic hybrid flip-flop[START_REF] Tschanz | Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors[END_REF].

Figure 1 . 13 :

 113 Figure 1.13: Differential and semi-dynamic implicit pulse-triggered flip-flops.

  Low swing PMOS version. CLK D CLK (d) Low swing PMOS version.

Figure 1 . 14 :

 114 Figure 1.14: Pulse generators dedicated for pulsed-FFs in the state of the art.In 1.14c and 1.14d, transistors in diode mode lead to a lower swing, thus energy consumption, in the delay generator[START_REF] Su | A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder[END_REF].

  The simplest expression of a explicit pulse-triggered flip-flop[START_REF] Tschanz | Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors[END_REF]. The conventional explicit pulsetriggered flip-flop (ep-FF)[START_REF] Kim | Differential pass transistor pulsed latch[END_REF].

Figure 1 . 15 :

 115 Figure 1.15: The basic structures of explicit pulse-triggered flip-flop.

Figure 1 . 16 :

 116 Figure 1.16: Differential and semi-dynamic architectures of explicit pulsed-FF.

Figure 1 . 17 :

 117 Figure 1.17: Other conditional techniques.

  With this implementation, dual-edge version leads to a higher overall energy consumption. The conventional latch duplicated.

Figure 1 . 18 :

 118 Figure 1.18: A basic implementation of the dual-edge property [7].

Figure 1 . 19 :

 119 Figure 1.19: Dual-edge pulse generators.

Figure 1 . 20 :

 120 Figure 1.20: Adaptive-coupling flip-flop [48]. Thanks to the elementary clock load, this architecture exhibits the lowest energy consumption among the flip-flop literature.

Figure 1 . 22 :

 122 Figure 1.22: Example of implementation of the time-borrowing technique in explicit pulse-triggered flip-flop.

Figure 2 . 1 :

 21 Figure 2.1: Three different configurations providing identical input slopes when the transmission gate is closed.

  The transistor schematic of the ultra-low power diode.X (b)The bistable element composed of two ultra-low power diodes.(c) Principle of the currentvoltage characteristics of the bistable.

Figure 2 . 2 :

 22 Figure 2.2: Ultra-low power static bistable element [59].

Figure 2 . 3 :

 23 Figure 2.3: The half Schmitt trigger bistable [61].

Figure 2 . 4 :

 24 Figure 2.4: Breaking feedback mechanism in a cross-coupled inverters bistable.

  Writing system with three stages.

Figure 2 . 5 :

 25 Figure 2.5: Schematic principle of the writing system with many stages. Only the pull-down part is shown.

Figure 2 . 6 :

 26 Figure 2.6: One-stage TGPL-Data and C 2 MOS-Data (with and without the doted wire, respectively) FFs, two variants of the TGPL architecture from figure 1.15.

Figure 2 . 7 :

 27 Figure 2.7: One-stage TGPL-Clk and C 2 MOS-Clk (respectively with and without the doted wire) FF.s, two variants of the TGPL architecture from figure 1.15.

Figure 2 . 8 :

 28 Figure 2.8: Scannable and resettable version of the two-stages single-edge CDFF from figure 1.17d

Figure 2 . 9 :

 29 Figure 2.9: CP 3 L-Data, scannable and resettable version of the two-stages negativeedge triggered CP 3 L from figure 1.21.

Figure 2 . 11 :

 211 Figure 2.11: EEC: V dd = 1.0V, vdds=gnds=0V, α sw = 0.15, T clk = 40F O4, corner TT, temperature 70 • C.

Figure 2 . 12 :

 212 Figure 2.12: EEC: V dd = 0.35V, vdds=gnds=0V, α sw = 0.15, T clk = 40F O4, corner TT, temperature 25 • C.

Figure 2 . 13 :

 213 Figure 2.13: EECs of the C 2 MOS-Data and TGPL-Clk architectures extracted from the sizing methodology and from a applied back biasing (V dd = 1V, vdds/gnds range = ± 1V , α sw = 0.15, T clk = 40F O4, temperature 70 • C). Back biasing technique provides better performances than sizing methodology.

Figure 2 . 14 :

 214 Figure 2.14: EECs of the C 2 MOS-Data architecture extracted from the sizing methodology and from a applied back biasing (V dd = 0.35V, driving strength X1 , α sw = 0.15, T clk = 40F O4, temperature 25 • C).

6 and 2 . 7 ,Figure 2 . 15 :

 27215 Figure 2.15: Measured delays of TGPL-Data from 0.3V to 1V with the expected 3σ range computed from 63 chips (VDDS=GNDS=0V). Gray dots are the results of post-layout simulations in the five process corners (T • = 80 • C).

  Figure 2.16:Measured delays from 0.3V to 1V in nominal case (VDDS=GNDS=0V). Clk-to-Q delay is lower for TGPL-Data than for TGPL-Clk, contrary to the D-to-Q delay (T • = 80 • C).

Figure 2 . 17 :

 217 Figure 2.17: Vdds variation and GNDS at intermediate supply voltage. A variation of 250% is achieved with the back biasing.

  Gnds variation at near-threshold supply voltage. Gnds variation at super-threshold supply voltage. Vdds variation at subthreshold supply voltage.

Figure 2 . 18 :

 218 Figure 2.18: Evolution of measured delays with VDDS and GNDS.

2 .

 2 [START_REF] Liu | High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond[END_REF] the delay distribution either typical of subthreshold operation (0.3V) or of super-threshold operation (0.5V), depending on the back bias values. In figure 2.18b, the supply voltage is 0.4V, a bit above the threshold voltage. We can Evolution of the average energy per cycle (αsw = 15%) and the EDP with the supply voltage. Evolution of the average energy per cycle with the data switching activity factor.

Figure 2 . 19 :

 219 Figure 2.19: The TGPL architectures outperform MS topology for all supply voltage between 0.3V and 1V and all activity factors (post-layout simulation).

Figure 3 . 1 :

 31 Figure 3.1: Increasing the robustness of the pulsed-FF leads to a great cost in energy.

Figure 3 . 2 :Figure 3 . 3 :

 3233 Figure 3.2: Proposed current starved (CS) delay generator architecture [70].

  Minimum delay (T del,-3σ ) function of the size of the current-starving transistors. Maximum delay (T del,3σ ) and energy function of the size of the CS transistors.

Figure 3 . 4 :

 34 Figure 3.4: Impact of sizing on the delay generators figures of merit.

Figure 3 . 5 :

 35 Figure 3.5: Minimum and maximum delays (T del,±3σ ) and energy consumption function of the size of the current-starving transistor(s). NMOS-only exhibits a lower timing variability than PMOS-only.

( a )

 a Inverters chain: varying stage number and gate length for each stage. (b) Two half Schmitt triggers (hST) placed in the pulling-systems of the delay path.(c) replica delay generator[START_REF] Lin | A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS[END_REF].

Figure 3 . 6 :

 36 Figure 3.6: Delay generator architectures used for the comparison.

Figure 3 . 7 :

 37 Figure 3.7: Comparison of energy and delay performances in subthreshold regime (V dd = 0.3V ). The name indicates the poly bias and the number of stages getting this PB.

Figures 3 .

 3 Figures 3.7 and 3.8 show the performances of the delay generators for the three figures of merit. Figure3.7 compares the current-starved DG with the conventional DG and its variants: one, two or three stages have a PB of 10nm or 16nm. We see that increasing the gate length provides the lowest energy consumption, but it is achieved to the detriment of a huge spread dispersion. Indeed, as the switching energy is predominant in a pulse generator activated at each clock cycle, the saving in energy is quite small compared to the delay dispersion due to the PB. For example, the energy consumption of 3PB16 (the three stages of the conventional PG have a gate length increased by 16nm) is 13% lower than the CS delay generator, but its maximum delay is 84% higher, resulting in an global energy overhead due to buffers insertion for fixing the hold time constraint.One can be surprised by the fact that a higher gate length leads to a higher delay dispersion. However, these results are not in contradiction to the design theory. What it is well known is that the ratio σ/µ decreases with the number of gates or the increase of transistor dimensions. But, we have to keep in mind that while µ increases, σ increases as well, as illustrated on figures 3.3 and 3.7.Figure3.8 compares the CS delay generator and the conventional one with different architectures: the replica DG proposed in[START_REF] Lin | A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS[END_REF], one, two or three half Schmitt triggers, and five or seven stages. As explained in section 3.1, adding inverters leads to a tradeoff between energy and robustness. Half Schmitt triggers

Figure

  Figures 3.7 and 3.8 show the performances of the delay generators for the three figures of merit. Figure3.7 compares the current-starved DG with the conventional DG and its variants: one, two or three stages have a PB of 10nm or 16nm. We see that increasing the gate length provides the lowest energy consumption, but it is achieved to the detriment of a huge spread dispersion. Indeed, as the switching energy is predominant in a pulse generator activated at each clock cycle, the saving in energy is quite small compared to the delay dispersion due to the PB. For example, the energy consumption of 3PB16 (the three stages of the conventional PG have a gate length increased by 16nm) is 13% lower than the CS delay generator, but its maximum delay is 84% higher, resulting in an global energy overhead due to buffers insertion for fixing the hold time constraint.One can be surprised by the fact that a higher gate length leads to a higher delay dispersion. However, these results are not in contradiction to the design theory. What it is well known is that the ratio σ/µ decreases with the number of gates or the increase of transistor dimensions. But, we have to keep in mind that while µ increases, σ increases as well, as illustrated on figures 3.3 and 3.7.Figure3.8 compares the CS delay generator and the conventional one with different architectures: the replica DG proposed in[START_REF] Lin | A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS[END_REF], one, two or three half Schmitt triggers, and five or seven stages. As explained in section 3.1, adding inverters leads to a tradeoff between energy and robustness. Half Schmitt triggers

Figure 3 . 8 :

 38 Figure 3.8: Comparison of energy and delay performances in subthreshold regime (V dd = 0.3V ) for difference DG architectures.

Figure 3 . 10 :Figure 3 . 11 :

 310311 Figure 3.10: Computed yield of TGPL-Data in the (vdds,gnds) space (25• C). The darker is the square, the higher is the yield.

Figure 3 . 12 :

 312 Figure 3.12: At ULV, the degradation of the FOM ( Ion I of f ratio) leads to a degraded output logic level.

Figure 3 . 13 :

 313 Figure 3.13: For Vdds and Gnds values evolving in the same way, an optimal point is found near the middle of the diagonal 2 (Fig. 3.11).

Figure 3 . 14 :

 314 Figure 3.14: Strong FBB increases the speed but decreases the robustness. In 28nm FDSOI technology, the non-identical subthreshold slopes cause a robustness decrease also for RBB.

Figure 3 . 15 :

 315 Figure 3.15: Yield average over the whole (vdds,gnds) space. The explicit pulsed-FFs presents, now, the same robustness as Master-Slave topology.

Figure 3 . 16 :

 316 Figure 3.16: The current-starved (CS) delay generator provides a notable gain for the yield.

Figure 3 . 17 :Figure 3 . 18 :

 317318 Figure 3.17: (Re)Set and Enable functionalities are easily implemented in the pulse generator.

D. 1

 1 Introduction D.2 Comparaison d'architectures D.3 Générateur d'impulsion robuste D.4 Réduction de la consommation d'énergie D.5 Conclusions

Figure 4 . 1 :

 41 Figure 4.1: Timing regions and characteristics for TGPL flip-flop (nominal voltage.

Figure 4 . 2 :

 42 Figure 4.2: Repartition of the energy dissipation in C 2 MOS architecture (minimum EDP sizing). Corner TT, nominal voltage (1V), temperature = 70 • C.

  The C 2 MOS-XOR latch with additional inverters for D and Q d signals.

Figure 4 . 3 :

 43 Figure 4.3: Schematic of the TGPL/C 2 MOS-invQ/invD architectures.

Finally, the C 2

 2 MOS-XOR architecture with TGPL-Clk, C 2 MOS-Data and the master-slave C 2 MOS FF are compared in the E -D domain (figure 4.5).

Figure 4 . 4 :

 44 Figure 4.4: Energy-Delay with several different XOR (V dd = 1V, driving strength X1 , α sw = 0.15, T clk = 40F O4, temperature 70 • C).

Figure 4 . 5 :

 45 Figure 4.5: EECs for the four interesting architectures at V dd = 1V (driving strength X1 , α sw = 0.15, T clk = 40F O4, temperature 70 • C). The dashed curve is only there to illustrate the Pareto optimum idea.

Figure 4 . 6 :

 46 Figure 4.6: The energy per FF with the number of latches sharing a PG. Bars represent the proportions of the energy consumed in the delay generator, the clocked part (CLK and P ulse signals), and the latch alone. V dd =1V, minimum driving strength (X1), T clk = 40FO4, α sw = 15%.

Figure 4 . 7 :

 47 Figure 4.7: Pulse-triggered FF architecture shows a lower area per FF than masterslave. The block of 8 pulsed-FF (right) has 32% less area than 8 MS FFs, at the expense of the M3 layer utilization.

( a )

 a Structured explicit pulsed-FFs based register file layout. (b) Structured master-slave FFs based register file layout.

Figure 4 . 8 :

 48 Figure 4.8: Layout comparison led to a 14% saving in area.

Figure 4 . 9 :

 49 Figure 4.9: Energy per operation over a wide voltage range (Gnds = Vdds = 0Vand α rate = 15%). Explicit pulsed-FFs based register file presents a lower energy consumption for super-threshold V dd and an optimal one at 0.35V.

Figure 4 . 10 :

 410 Figure 4.10: Energy per operation function of the supply voltage and the back biasing (α rate = 15%, T clk = 40F O4, corner TT, temp. = 25 • C).

Figure 4 . 11 :

 411 Figure 4.11: Evolution of the register file delay with back biasing.

Figure 4 . 12 :

 412 Figure 4.12: Evolution energy-delay product (EDP) with V dd and back bias.

Figure A. 3 :

 3 Figure A.3: Monte-Carlo simulations exhibit the weak robustness of ACPL architecture to transistor variability (corner FS, temp. = 25 • C, V dd = 0.4V).

Figure A. 5 :

 5 Figure A.4: R-S CPFF architecture.

Figure B. 1 :

 1 Figure B.1: Testbench used to characterize FFs with layout parasitics included.

Figure C. 1 :

 1 Figure C.1: Testbench used to characterize the register files (post-layout extraction).

D

  read = max(D read,A,i , D read,B,i ) (C.1)

Figure D. 1 :

 1 Figure D.1: Le transistor FDSOI (version NMOS).

2

 2 MOS). Le phénomène de pass-through est évité.

Figure D. 2 :

 2 Figure D.2: Architectures maitre-esclave conventionnelles. TGFF donne un meilleur compromis entre la vitesse et le phénomène pass-through.

  c) Avec l'étage de sortie modifié.

Figure D. 3 :

 3 Figure D.3: Bascules différentielles basées sur le sense-amplifier.

D.1. 2 . 2 Différentiels

 22 Les architectures typiques de bascules différentielles sont représentées à la figure D.3. Ces bascules présentent à la fois la sortie logique (Q) et son complémentaire (Q) en sortie et nous pouvons remarquer une très forte symétrie axial dans la structure. Bascule à latch hybride (HLFF)[START_REF] Stojanovic | Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems[END_REF]. Bascule semi-dynamique (SDFF)[START_REF] Stojanovic | Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems[END_REF].

Figure D. 4 :

 4 Figure D.4: Bascule semi-dynamiques à impulsion implicite.

  (voir figure D.5). Recevant le signal d'horloge, le générateur envoie un ou plusieurs signaux en forme d'impulsion sur le latch afin de le rendre passant. Ces architectures consomment un petit La bascule à impulsion explicite conventionnelle[START_REF] Kim | Differential pass transistor pulsed latch[END_REF].

Figure D. 5 :

 5 Figure D.5: Les structures basiques de bascules à impulsion explicite.

Figure D. 6 :

 6 Figure D.6: Générateurs d'impulsion (GIs) double-front.

D.1. 2 . 5

 25 Synthèse et impulsion expliciteLe tableau D.1 résume la comparaison des quatre catégories de bascule.

•

  Logique CMOS statique, • Pas de chemin de court-circuit, • Une porte de transmission à transistor unique est interdite, • Un empilement de quatre transistors ou plus est aussi interdit, • Les bascules sont sensibles sur un seul front d'horloge, • La sortie des bascules doit être la sortie d'un inverseur, • Toutes les entrées arrivent sur une grille de transistor, • Une sortie inversée logiquement ou un front descendant actif sont autorisés, • Les bascules possèdent les fonctions scan et reset.La dernière contrainte provient du fait qu'aujourd'hui en industrie, et tout spécialement avec des noeuds technologiques avancés, il est nécessaire de tester le circuit quand il sort de fabrication. De plus, la fonction reset permet au concepteur de l'architecture du processeur de connaitre l'état du circuit à un moment donné.Les six architectures sont représentées aux figures D.7 à D.10. Les figures D.7 et D.8 représentent deux fois deux variantes de l'architecture conventionnelle.Les versions TGPL et C 2 MOS consistent en l'utilisation ou non d'une porte de transmission sur l'étage d'entrée. Une porte de transmission sera plus rapide qu'un inverseur trois-états. Néanmoins, les capacités de jonction des autres transistors de l'étage d'entrée seront toutes et complètement chargées et déchargées lors de chaque variation de la donnée en entrée. Il y a donc un compromis à faire entre la vitesse et la consommation.Les versions -Data ou -Clk consistent en deux multiplexage différents des signaux de données (D et la donnée de test T I). Soit l'étage d'entrée est un multiplexeur commandé par le signal de test T E, soit la génération d'impulsion est dédoublée. Dans le premier cas, nous voyons un empilement de trois transistors et dans le second cas, une augmentation de la capacité interne du générateur d'impulsion. C'est donc un deuxième compromis vitesse/consommation.

Figure D. 7 :

 7 Figure D.7: Les bascules TGPL-Data and C 2 MOS-Data (respectivement avec et sans les pointillés), deux variantes de l'architecture TGPL de la figure D.5.

Figure D. 8 :

 8 Figure D.8: Les bascules TGPL-Clk and C 2 MOS-Clk (respectivement avec et sans les pointillés), deux variantes de l'architecture TGPL de la figure D.5.

Figure D. 9 :

 9 Figure D.9: La version avec scan et reset de l'architecture CDFF de la figure 1.17d

Figure D. 10 :

 10 Figure D.10: CP 3 L-Data, version avec scan et reset de l'architecture CP 3 L de la figure 1.21.

Figure D. 11 :

 11 Figure D.11: CEE: V dd = 1.0V, Vdds=Gnds=0V, α sw = 0.15, T clk = 40F O4, corner TT, température 70 • C.

Figure D. 12 :

 12 Figure D.12: CEE: V dd = 0.35V, Vdds=Gnds=0V, α sw = 0.15, T clk = 40F O4, corner TT, température 25 • C.

Figure D. 13 :

 13 Figure D.13: CEEs des architectures C 2 MOS-Data et TGPL-Clk extraites partir de l'algorithme de dimensionnement et partir d'une polarisation face arrire (V dd = 1V, Vdds/Gnds range = ± 1V , α sw = 0.15, T clk = 40F O4, température 70 • C). La technique de polarisation face arrire applique sur une large gamme fournie de meilleures performances en dlais et nergie que la mthodologie de dimensionnement.

Figure D. 14 :

 14 Figure D.14: CEEs de l'architecture C 2 MOS-Data extraites partir de l'algorithme de dimensionnement et partir d'une polarisation face arrire (V dd = 0.35V , α sw = 0.15, T clk = 40F O4, température 25 • C).

Figure D. 15 :

 15 Figure D.15: Délais mesurés de 0.3V à 1V dans le cas nominal (Vdds=Gnds=0V). Le délais Clk-Q est plus faible pour la TGPL-Data que pour la TGPL-Clk, contrairement au délais entrée-sortie (T • = 80 • C).

Figure D. 17 :Figure D. 18 :

 1718 Figure D.17: L'architecture TGPL surpasse la topologie maitre-esclave pour toute tension d'alimentation entre 0.3V et 1V et tous les facteurs d'activité (simulation post-layout).

Figure D. 19 :Figure D. 20 :Figure D. 21 :

 192021 Figure D.19: Architecture du générateur de délais (GD) proposé [70].

Figure D. 22 :

 22 Figure D.22: Comparaison des performances nergtiques et en dlais dans le rgime sous-seuil (V dd = 0.3V ). pour diffrentes architectures de GD.

Figure D. 23 :Figure D. 24 :

 2324 Figure D.23: Rendement mesuré de l'architecture TGPL-Data dans l'espace (Vdds,Gnds) à 25 • C. Plus le carré est sombre, plus le rendement est élevé.

Figure D. 25 :

 25 Figure D.25: The current-starved (CS) delay generator provides a notable gain for the yield.

  Le générateur d'impulsion conditionnelle. Le latch C 2 MOS-Xor avec des inverseurs pour les signaux D et Q d .

Figure D. 26 :

 26 Figure D.26: Schématique des architectures TGPL/C 2 MOS-invQ/invD.

Figure D. 28 :

 28 Figure D.27: L'énergie par bascule fonction du nombre de latches partageant un GI. Les barres représentent les proportions de l'énergie consummée dans le générateur de délais, la partie "horlogée" (les signaux CLK et P ulse) et le latch pris isolément. V dd =1V, T clk = 40FO4, α sw = 15%.

( a )

 a Layout du banc de registre structuré basé sur des bascule à impulsion. (b) Layout du banc de registre structuré basé sur des bascule à maitre-esclave.

Figure D. 29 :Figure D. 30 :

 2930 Figure D.29: La comparaison des layouts mène à un gain en surface de 14%.

Table 1 . 1 :

 11 Comparison of the flip-flop topologies for different figures of merit.

	Topology	Speed	Power Area V dd Scalability
	Master-slave	-	+	+	++
	Differential	++	--	-	--
	Implicit pulsed-FF	+	-	-	-
	Explicit pulsed-FF † ++/++ -/++ -/++	-/-
	Dual-edge	+	++	+	-
	† without/with shared pulse generator
	Let us now highlight the state of the art about the architectures reaching good
	performances in low-power operations.

Table 1

 1

	.2: A sample of the quantitative results of the state of the art flip-flop
	performances
	Archi-	Supply Techno-D-to-Q	Energy [fJ]	EDP Transistor
	tecture	[V]	logy	[ns]	[data activity] [fJ.ps]	count
	ACFF*	1.1	40nm	0.264	2 [10%]	528	22
	CP 3 L*	1	65nm	0.017	26.1 [10%]	451.5	34
	IMD-FF	0.4	90nm	1.7	[n.a.]	[n.a.]	22
	APFF	0.4→1V	65nm	14.2	4.2 [n.a.]	59700	30
	* silicon measurements

Table 2 . 2 :

 22 .2. Optimal β P N =

	Wp Wn ratio for identical rise and fall time at nominal I of f ratio at ULV. voltage and for maximal Ion
	CMOS stage β P N at nominal voltage	β P N at ULV
	stack	(identical rise/fall times) (maximal	I on,lin

Table 2 . 3 :

 23 Imaginary example of sizing algorithm results.

	FOM to minimize (Designer choice) (Algo. result) W k †	corresponding D corresponding E (Algo. result) (Algo. result)

  and 2.14 compare the

	0.8 10	1	1.2	1.4	1.6	1.8	2	2.2	2.4	2.6

Table 2 . 4 :

 24 Comparison of the EDP and ED 2 P figures of merit for the three architectures (post-layout simulation at 1V and 80 • C).

	Architecture	E op [f J] (α sw = 15%)	EDP [fJ • ps] ED 2 P [fJ • ps 2 ] Area [µm 2 ]
	MS	6.72 (ref.)	1136 (ref.)	1877	4.4 (ref.)
	TGPL-Data	10.08 (+50%)	288 (-74%)	82	5.4 (+23%)
	TGPL-Clk	14.88 (+121%)	334 (-70%)	74	6.7 (+52%)

the previous constraints. Afterwards, a comparison of the performances in the energy-delay (E -D) domain was performed at the nominal and the energyoptimum supply voltages.

Table 3

 3

	.1: Robustness comparison with 1000 Monte-Carlo runs of post-layout sim-
	ulations in subthreshold regime (0.3 V)
	PVT conditions	# Failed Conventional	Proposed
	FS -40 • FS 85 • SF -40 • SF 85 •	14 3 60 29	0 0 1 0

Table 3 . 2 :

 32 Area [µm 2 ] comparison between a conventional master-slave and the TGPL-Data architecture

	Topology Original Resettable Resettable and Enable
	MS	3.75	4.4 (+17%)	5.38 (+43%)
	pulsed-FF	5.38	5.71 (+6%)	5.87 (+9%)

Table 3 . 3 :

 33 EDP [ps.fJ] comparison between a conventional master-slave and the TGPL-Data architecture (post-layout simulations)

	Topology Original	Resettable	Resettable and Enable
	MS	580	721 (+24%)	953 (+64%)
	pulsed-FF	236	249 (+5.5%)	259 (+9.7%)

Table 4 . 1 :

 41 Area [µm 2 ] comparison between the four most energy-efficient FF architectures.mC 2 MOS MS † C 2 MOS-Data TGPL-Clk C 2 MOS-Xor

	4.4	5.4	6.7	6.7
	† Highly optimised layout from industrial library

Table 4 . 2 :

 42 Energy-delay-area comparison of our explicit pulse-triggered flip-flop based and the master-slave (MS) based register files at V dd = 1V and V dd = 0.35V .

		Pulsed-FF	Master-slave structured	Master-slave Master-slave 1V library 0.35V library
	Area [µm 2 ]	2970.4	3386.2 (+14%)	4123.5(+39%)
	D read|1V [ps]	87	87	119 (+37%)	151 (+73%)
	D read|0.35V [ns]	6.36	6.36	7.69 (+21%) 9.73 (+51%)
	E op|1V [pJ]	0.8	0.88 (+10%)	0.86 (+7.5%) 0.89 (+11%)
	E op|0.35V [pJ]	0.18	0.15 (-17%)	0.23 (+30%) 0.25 (+39%)

Table D .

 D 1: Comparaison de topologies de bascules pour différentes figures de mérite.

	Topologie	Vitesse Puissance Surface robustesse
	Maitre-esclave	-	+	+	++
	Différentielle	++	--	-	--
	A impulsion implicite	+	-	-	-
	A impulsion explicite † ++/++	-/++	-/++	-/-
	Double-front	+	++	+	-
	† sans/avec générateur d'impulsion partagé

  et D.14 comparent les performances dans l'espace E -D de l'architecture C 2 MOS-Data (dimensionnement minimum PED) sur laquelle est appliquée une large et symétrique polarisation arrière. Comme nous pouvons voir, le délais dans la région haut-performance est plus petit, pour la même

	0.8 10	1	1.2	1.4	1.6	1.8	2	2.2	2.4	2.6

Abstract

This chapter focuses on the integration of our energy-efficient explicit pulsetriggered flip-flops in large digital circuits, i.e. at block level.

First, the phenomena of clock skew encountered in the design at block level is briefly discussed and its impact on our explicit pulse-triggered flip-flop architectures is exposed.

Then, the design of a conditional capture pulsed-FF is established with the same methodology as in Chapter 2. Several variants are compared in the energydelay (E -D) domain in order to select the most energy-efficient. This conditional capture technique disables the pulse generator when there is no data activity and thanks to that, this explicit pulse-triggered architecture exhibits a lower energy consumption than the master-slave architecture available in an industrial standard-cells library. Then, it is shown that this new architecture gives another degree of freedom in the energy-delay-area tradeoff faced by the automatic synthesis tools. Using the lowest FF energy consumption while meeting the timing constraint for each path, provides a Pareto-optimum-like energy-efficient circuit synthesis [1].

Afterwards, the sharing of the pulse generator (PG) of explicit pulse-triggered flip-flops is studied. The pulse generator represents the largest part of the energy consumption of pulsed-FFs, but this part can be divided by the number of latch when it is shared. We show that, after a given number of latches sharing the same PG, the energy and area per FF are actually lower than the energy dissipation and area of a master-slave FF. To conclude, a complete 16x32bits register file was laid out using the energy-efficient scannable C 2 MOS-Data latch of Chapter 2, the enable and resettable current-starved PG of Chapter 3 and the PG sharing property. It is shown that, compared to a master-slaved based register file, our energy-efficient explicit pulse-triggered flip-flops provide lower energy consumption (-10%) above a supply voltage of 0.6V and a lower area (-14%).

ARCHITECTURES

The studies presented here do not give a fundamental message for the comprehension of the plain text. Nevertheless, some architectural choices in Chapter 2 may become clearer after this section.

First, we present the reasoning to reach the CDFF architecture compared in Chapter 2, which is slightly different from the original structure proposed in [START_REF] Zhao | High-Performance and Low-Power Conditional Discharge Flip-Flop[END_REF]. Second, simulations performed on the pulse-triggered version of the adaptive coupling flip-flop (ACFF [START_REF] Teh | A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS[END_REF]), the adaptive coupling pulse latch (ACPL), are shown to prove that it is not suitable for very-low voltage operations, as assessed in Section 2.2.2. Finally, in [START_REF] Alioto | Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops : Part I-II[END_REF], the result of the comparison of pulsed-FFs showed that the CPFF architecture presents a lower energy consumption than TGPL in the low-power region of the energy-delay (E -D) domain. Here, we show that the resettable and scannable version of CPFF exhibits by far the worst energy-efficiency over all the pulsed-FFs.

CDFF : keeper and reordering

From the original architecture proposed in [START_REF] Zhao | High-Performance and Low-Power Conditional Discharge Flip-Flop[END_REF], two points are analysed here: the keeper architecture and the order of the gate inputs in the two NMOS stack.

Keeper The aim of the feedback keeper of the original CDFF structure in [START_REF] Zhao | High-Performance and Low-Power Conditional Discharge Flip-Flop[END_REF], crossed in figure A.1, is to maintain the voltage value of the node when it has to stay high during the pulse signal. Keeper is needed since the leakage current and the period of the pulse signal are strongly affected by global and local variations