David Cordeau

Maître De

Jean-Marie Paillot

18 GHz 13.4 -14 GHz 15.4 -17.7 GHz K 18 -27 GHz 24.05 -24.25 GHz 24.05 -24.25 GHz 24.05 -24.25 GHz 24.65 -24.75 GHz

Moreover, they always encouraged me to keep exploring and trying. I still remember one time when David told me not to worry that my operations would kill Cadence software.

All these were like sparks that helped me to cross one obstacle after another. In addition, I would like to thank them for their precious and valuable feedback and comments that I have greatly benefited from during the process of writing my articles and dissertation. Special thanks are given to my dear colleagues from the IDDO-IC, Mr. Sébastien Charpentier, Mr. Matthieu Lecuyer, Mr. Sébastien Vauclair, Mr. Lewis Macdonald and others. Starting from the initial installation and configuration of the PDK to the various details of the circuit design and layout, their constant guidance meant a lot to me. In addition, their selfless care and assistance in my work and life made me feel at home. Of course, I also enjoyed the jokes they occasionally shared, even though some of them were not so funny. My sincere thanks also go to Ms. Emmanuelle Baldinger for helping me with many administrative tasks and keeping me worry-free. Time flies, but the memories II of my time at IDDO-IC will stay with me forever. I would like to sincerely thank the members of the ReSYST research group, including Mr. Claude Duvanaud, Mr. Smail Bachir, former and current Ph.D. students (Tayeb, Younès, Nuraddeen, Abdulrazaq, Manuel, Bhanu, etc.). I would also like to thank other colleagues and friends, Maxime, Mohamed, Sergueï, Dounia, Baptiste, Georgian, etc. I have to say that they have consistently provided me with invaluable assistance and have supported, encouraged, and accompanied me throughout my academic journey.

Lastly, I would like to thank all my sisters and brothers (Yan Li, Yu Li, Wei Li, Liang Li, Kongliang Liu, Sanqiang Cen, Meng Liu) for their enduring love and encouragement.

Especially, I would like to express my deepest appreciation to my lovely parents Zhanguo Li and Xinju Zhang. I will forever be grateful for their unconditional love, their endless sacrifices, and their unwavering faith in me.

Zhigang Li

March 2023 Table I.

III

Table of Contents

List of Figures

General Introduction

As one of the core sensors for advanced driver assistance systems (ADAS), the automotive radar is becoming mainstream for applications such as obstacle detection and automatic cruise control. Meanwhile, the millimeter-wave (mm-W) band, 76 -81 GHz, is promised to be a long-term solution for automotive radar development as it allows for a smaller antenna size, uncrowded spectrum, larger bandwidth, etc. In particular, the frequency-modulated continuous-wave (FMCW) automotive radar greatly benefits from the high carrier frequency and the large bandwidth to improve its angular and radial resolution, which is also inseparable from the linear triangular or sawtooth chirp generated by the phase-locked loop (PLL).

However, some bottlenecks of the analog PLL are revealed at deep nanoscale CMOS nodes. For instance, the chip area of PLL does not decrease significantly with process scaling, and it is difficult to migrate it from one process to another, leading to long design cycles and high costs. Based on these facts, implementing PLLs like digital circuits has recently been a hot research topic, i.e., all-digital phase-locked loop (ADPLL). Compared to the analog PLL, the ADPLL shows excellent prospects in terms of low cost, small area, low power consumption, easy integration, and high compatibility with other digital baseband circuits. As one of the essential building blocks of ADPLLs, Digitally Controlled Oscillators (DCO) are employed to generate a periodic waveform with a frequency that can be digitally controlled, making them a versatile and flexible alternative to traditional analog Voltage-Controlled Oscillators (VCO). While numerous DCOs operating at frequencies below 10 GHz have been published so far, reports of those operating above 10 GHz are scarce. There is even less material on the design challenges of K-band DCOs and the solutions to address them.

In such a context, the objective of this thesis is not only to investigate the feasibility of designing a K-band DCO in an advanced 22 nm FD-SOI process, but also the proposed DCOs need to meet stringent specifications to be suitable for 76 -81 GHz FMCW automotive radars, such as achieving low phase noise, wide tuning range, and high frequency resolution simultaneously, which is quite challenging.

Chapter I aims to comprehensively review the research background related to automotive radars, frequency synthesis techniques, and oscillators. We will begin by -2 -presenting an overview of the principles, structures, categories, operating bands, and processes relevant to automotive radars, followed by a brief review of the research conducted on 76 -81 GHz automotive radars. This will highlight the significant commercial value of this research topic. Next, we will review some common frequency synthesis techniques and emphasize the basic theory and main modules of PLLs and ADPLLs, while also comparing them to show the potential of ADPLLs for future applications. Finally, we will introduce the theory and types of oscillators and conduct a brief analysis of their phase noise performances. These are crucial factors in DCO design and serve as the theoretical foundation for the discussion in later chapters.

In Chapter II, we will begin by briefly introducing GlobalFoundries' 22 nm FD-SOI process, including the flipped well structure, the back-gate biasing technique, and the available components in the library. We will then compare different DCO topologies, focusing on LC-based DCOs, as well as classical frequency tuning techniques. We will also briefly introduce the fundamental theory of FMCW radars and DCO gain calibration for chirp linearity. Our main focus will be on the design and implementation of a K-band low-phase-noise triple-bank DCO (T-DCO) for 76 -81 GHz automotive radars. We will not only discuss the design difficulties and important considerations, but also provide a theoretical analysis and a detailed presentation of the switched-capacitor structure used, along with a novel back-gate-based fine-tuning structure. Finally, we will compare the post-layout simulation results of the T-DCO with the specifications and other state-ofthe-art DCOs to demonstrate the feasibility of designing a K-band DCO in a 22 nm FD-SOI process. This will further solidify the potential of using this process for highfrequency applications such as automotive radars.

In Chapter III, we will first briefly elucidate the frequency overlap problem that arises in a multi-bank DCO, as well as the complex frequency calibration and linearization problems. In order to address these issues at the design level rather than only at the algorithmic level, we will present a new dual-bank DCO (D-DCO) prototype that has seldom been disclosed before. We will describe the circuit implementation in detail, along with the key considerations and design challenges. Finally, we will compare the postlayout simulation results of the D-DCO with the specifications to verify its compliance with the 76 -81 GHz automotive radar requirements.

CHAPTER I

Introduction to Research Work

This research work aims to design a high-performance digitally controlled oscillator (DCO). It is a core module of an all-digital phase-locked loop (ADPLL) that will be used in 76 -81 GHz automotive radars. Therefore, this chapter focuses on presenting and reviewing the background in the existing literature related to the research purpose. In Section I.1, we will briefly introduce the development footprint, main architectures and principles of automotive radars. In Section I.2, the fundamentals of frequency synthesizers will be elaborated, followed by an introduction and comparison of PLLs and ADPLLs. In Section I.3, we will mainly present the theory and types of oscillators, and finally their phase noise is analyzed.

I.1. Automotive Radar

I.1.1. Radar Fundamentals

Radar is an acronym standing for Radio Detection and Ranging. As the name implies, it uses radio/electromagnetic (EM) waves to detect the targets. The first practical radar was invented by the British physicist Robert Watson-Watt and his team in 1935, and a flying bomber was clearly detected in their experiment. During the World War Ⅱ, radar was developed explosively in the military field. Today, radar plays an important role in our daily life owing to its wide variety of applications in many fields:

• Military: airborne early warning radar, airborne ground surveillance radar, antiaircraft artillery radar, missile guidance radar, fire control radar;

• Air traffic control and navigation: airport surveillance radar, precision approach;

• Meteorology and geography: weather (rain, fog, snow, hail, etc.) surveillance radar, wind profiling radar, millimeter cloud radar, imaging radar, 3D radar;

• Traffic and road safety: radar speed gun, anti-collision radar, blind-spot detection radar, car parking/reversing radar, automatic cruise control system.

Such diverse applications are inseparable from the inherent properties of the EM waves used in radar. For example, EM waves propagate at the speed of light (c = 3×10 8 m/s) and are highly immune to the environment and weather conditions, making radar capable of rapidly determining the location, speed, orientation, etc., of aircraft, ships or other invisible objects at long distances. In addition, radar often works together with different types of sensors to provide better and more comprehensive performances, among which ultrasonic and optical sensors are commonly used, especially in the automotive industry, which is the theoretical basis for autonomous driving technology. L-band, so the radars require a much higher emitted power to achieve long-range detection. Moreover, some special airport surveillance radars also use this band to detect aircraft within 120 km. Most mobile military battlefield and weather radars are based on C-band, allowing for quick installation, good angular accuracy and reasonable resolution.

The radar in Ku and K bands are commonly used as airborne radars, maritime navigation radars and imaging radars (spaceborne or airborne), which have appropriately small antennas and adequate angular accuracy. The high-frequency K and Ka bands are heavily influenced by weather and atmospheric attenuation. Therefore, radars in these bands are suitable for some short-range scenarios such as traffic radars, terrain avoidance and terrain tracking radars. The mm-Wave radars in V, W and mm bands offer a series of advantages in terms of the large spectrum space, low latency time, compact antenna size and high resolution. However, they also suffer from severe atmospheric attenuation, and three attenuation peaks occur at about 60 GHz, 120 GHz and 180 GHz, coinciding with the resonant frequencies of the oxygen and water molecules (Figure I.1.2).

Correspondingly, there are some frequency windows between these peaks where the atmospheric attenuation is relatively lower, and most mm-Wave applications are within these windows, such as 76 -81 GHz automotive radars.

I.1.1.2. Mono-static and Multi-static Radars

The physical configurations of the antennas can classify the radars into monostatic -8 -In a monostatic radar system, the time and phase synchronization between transmission and reception can be performed by the same frequency source and clock, resulting in a relatively simple structure. Moreover, for most short-range civil scenarios, the radar size can be petite because of the low emitted power required, such as automotive radars. In military applications, the monostatic radar can also be equipped inside the rocket head to track and attack aircrafts, tanks, etc.

Multi-static radar offers some advantages over monostatic radar in cases where the reflected energy from the target is deficient, such as long-range and weather radars.

Furthermore, it allows more comprehensive observations of targets from different transmit-receive pairs, thereby adding potentially valuable information. Hence, it is more likely to detect stealthy objects and less susceptible to interference. However, in such a separated system, a precise standard time reference and complex algorithms are required for synchronization and data processing.

I.1.1.3. Radar Equation

The radar equation quantitatively describes the relationship between the radar parameters, the detection distance, and target characteristics [I-6]. Assuming that a target is located at a range of R from the radar, Pt is the radar transmitted power, and Gt is the transmit antenna gain, the directional power density S1 at this target is given by

𝑆 1 = 𝑃 𝑡 𝐺 𝑡 4𝜋𝑅 2 (I. 1. 1)
The reflected power P1 by the target is

𝑃 1 = 𝑆 1 • 𝜎 = 𝑃 𝑡 𝐺 𝑡 𝜎 4𝜋𝑅 2 (I. 1. 2)
where σ is the radar cross section (RCS). A target with a larger RCS means that it is more easily detected. The returned power density S2 at the radar is given by

𝑆 2 = 𝑃 1 4𝜋𝑅 2 = 𝑃 𝑡 𝐺 𝑡 𝜎 (4𝜋𝑅 2 ) 2 (I. 1. 3)
Thus, the total received power Pr by the radar is

𝑃 𝑟 = 𝑆 2 • 𝐴 𝑒 (I. 1. 4)
where Ae is the effective antenna aperture. The relationship between the receive antenna gain Gr, the wavelength λ, and Ae can be expressed as

𝐺 𝑟 = 4𝜋𝐴 𝑒 𝜆 2 (I. 1. 5)
Substituting (Ⅰ.1.5) into (Ⅰ.1.4), the total received power Pr is therefore written as

𝑃 𝑟 = 𝑃 𝑡 𝐺 𝑡 𝐺 𝑟 𝜆 2 𝜎 (4𝜋) 3 𝑅 4 (I. 1. 6)
If the minimum received power that can be detected by the radar is Pr,min, then the maximum achievable range Rmax can be derived as Typically, the transmitter emits a train of rectangular pulses, each pulse has a width τ of about 0.1 to 1 microsecond (μs). During this pulse emission, the receiver is isolated from the antenna to protect its sensitive components from the high-power transmit pulse. Once the pulse emission is completed, the receiver is connected to the antenna, enabling it to pick up the reflected echo signals from the target. The distance R between the radar and the target can then be measured by simply calculating the round-trip time ∆t from the -10 -pulse emission to the reception of its return, which is given by

𝑅 𝑚𝑎𝑥 = √ 𝑃 𝑡 𝐺 𝑡 𝐺 𝑟 𝜆 2 𝜎 (4𝜋) 3 𝑃 𝑟,𝑚𝑖𝑛
𝑅 = 𝑐 • ∆𝑡 2 (I. 1. 8)
Note that the pulse is emitted periodically with a pulse repetition interval PRI, so the pulse repetition frequency PRF can be written as

𝑃𝑅𝐹 = 1 𝑃𝑅𝐼 (I. 1. 9)
The transmitted duty cycle D represents the ratio between τ and PRI and is given by

𝐷 = 𝜏 𝑃𝑅𝐼 = 𝜏 • 𝑃𝑅𝐹 (I. 1. 10)
If the transmitted pulse is a square wave, its average power Pav is equal to its peak power Pt multiplied by its duty cycle D, which can be expressed as:

𝑃 𝑎𝑣 = 𝑃 𝑡 • 𝐷 = 𝑃 𝑡 • 𝜏 • 𝑃𝑅𝐹 (I. 1. 11)
Pav is crucial because it determines the potential detectable range of the pulsed radar. To maximize the detection range, Pav can be increased by three means: improving the PRF, enlarging τ, and increasing Pt.

In addition, to avoid the range ambiguity, the echo pulse must be received before the next pulse is emitted, which means that the round-trip time ∆t of the radar pulse must be less than its PRI, and this relation can be defined as

∆𝑡 = 2𝑅 𝑐 ≤ 𝑃𝑅𝐼 (I. 1. 12)
Therefore, the maximum unambiguous range Rmax is

𝑅 𝑚𝑎𝑥 = 𝑐 • 𝑃𝑅𝐼 2 = 𝑐 2𝑃𝑅𝐹 (I. 1. 13)
The minimum detectable range Rmin (or blind distance) depends on the radar pulse width τ. When the front of the echo pulse reaches the antenna while the radar is still in transmission mode, the round-trip time ∆t cannot be determined. Considering the recovery time tr of the duplexer, Rmin is approximately given by

𝑅 𝑚𝑖𝑛 ≈ 𝑐 • (𝜏 + 𝑡 𝑟 ) 2 (I. 1. 14)
In the above range measurements, only the amplitude of the echo pulse is employed. In order to further acquire the velocity of the target vt, the frequency of the echo pulse has to be extracted and compared with that of the transmitted pulse, and the resulting frequency difference fd is known as a Doppler shift. This coherent radar is also referred to as pulsed Doppler radar, and the relationship between the Doppler frequency shift and the velocity of the target can be expressed as

𝑓 𝑑 = 2𝑣 𝑡 𝜆 (I. 1. 15)
where λ is the wavelength of the transmitted pulse.

Another important parameter is the resolution, which represents the capability of the radar to distinguish between two or more adjacent targets, whether in range, angle, or frequency. Let's take the range resolution as an example, if two targets are close enough, their reflected echo pulses will be merged or overlapped, and they will be considered as the same target in the receiver. The minimum resolvable range is defined as the range resolution ∆R, which is proportional to the pulse width τ. The relationship is

∆𝑅 = 𝑐 • 𝜏 2 (I. 1. 16)
Therefore, the fine range resolution can be achieved by shortening the pulse. Recall that in this case, the average power (or pulse energy) will be correspondingly decreased, which makes the detection more difficult. To solve this contradiction, pulse compression techniques are used to maintain the pulse energy while providing better range resolution by modulating the amplitude, phase, or frequency of the pulse signal.

Pulsed radars have shown excellent performances in some long-range scenarios such as weather radars, over-the-horizon (OTH) radars, and satellite-based remote sensing radars. However, they are rarely used in short-range scenarios due to their minimum detectable range which is limited by the pulse width and the switching time of the duplexer. Meanwhile, the accurate target localization also requires additional information about the antenna directionality, which further increases the complexity of the system.

I.1.1.4.2. Continuous-Wave Radar

Unlike pulsed radar, CW radar continuously transmits EM wave, and its waveform may be considered as a sine wave with constant frequency. The velocity of the target can be measured by Doppler shift, but not the range. Therefore, the EM wave must be modulated so as to obtain the round-trip time for the range determination. There are several ways to modulate a frequency in time, such as linear frequency modulation (LFM), frequency shift-keying (FSK), and frequency-stepped continuous-wave (FSCW) modulation [I-11]. Among them, the LFM method consists in varying the signal frequency linearly with time, and it is the most commonly used method in automotive radars.

I.1.1.5. Transceiver Architectures

As the core of wireless communications and radar systems, the transceiver acts as the link between the digital signal processor (DSP) and the RF antenna usually consisting of two or more independent transmitter and receiver chains. The transmitter is used to upconvert a modulated signal to a higher RF signal, which is then amplified to a specific power level to drive the antenna. The receiver is used to filter, amplify and down-convert the received weak signals while suppressing external interferences (e.g., noise, jamming,

t f(t) (a) t (b) t (c) f(t) f(t)
-13 -and clutter). The choice of transceiver architectures is mainly determined by complexity, performance, cost, and power consumption. In the following, we will take a representative PLL-based transmitter and a superheterodyne receiver as examples to briefly elaborate their principles. Another commonly used homodyne architecture will not be presented here, but some details can be found in of the PLL is appropriately selected, so the output RF filter can be omitted and the output noise of the transmitter at large frequency offsets is mainly determined by the VCO employed [I-14]. Therefore, this architecture permits some advantages such as low phase noise, low power consumption, and high linearity. However, a major challenge is to reduce the lock-in time of the PLL to further lower the power consumption.

Another critical issue is that this architecture is limited to the systems using constant amplitude modulation (AM) because the modulated PLL does not reproduce AM information. The polar modulation architecture can be used to address this issue. For example, the output signal of the modulator is divided into the amplitude and phase components. Phase modulation (PM) is still performed by the PLL, and an additional mixer prior to the PA is added to apply the AM. More details can be found in [I-15]. Nevertheless, in superheterodyne receivers, high-performance image-reject filters are still required. Passive filters, such as surface acoustic wave (SAW) or high-order LC filters, are frequently employed. They typically have a large physical size and are difficult to integrate, leading to an increase in design complexity, power consumption, and cost.

However, the use of IF and multiple filters in the superheterodyne architecture enables a wide dynamic range of reception and excellent suppression of interference, thus improving its selectivity and sensitivity.

I.1.2. Automotive Radar for Autonomous Driving

Autonomous driving usually refers to self-driving vehicles that relies on cutting-edge technologies such as powerful processors, multi-purpose sensors and artificial intelligence to travel without any driver manipulation. Such intelligent vehicles can not only improve the travel efficiency by planning routes and times in advance, but also accurately perceive the road conditions and timely react. In addition, they are capable of avoiding road traffic accidents caused by risky behaviors such as drunk, fatigue or distracted driving. According to the World Health Organization (WHO), about 90% of road traffic accidents are caused by human errors, and more than 1.3 million people die and up to 50 million get injured worldwide each year, making them the leading cause of Most vehicles on the road today are still stuck at level 0, which means they are always under control of the driver. Part of them may be equipped with some electronic or mechanical systems for driving safety, such as automatic emergency braking (AEB) systems and the electronic stability control (ESC) systems, but since these systems do not directly drive the vehicle, they cannot be counted as driving automation.

f RF f L02 f IF f IM f L02 f RF f IM f IM = f L02 + f IF f IF = f L02 -f RF f IF f IF f IF Image Useful Signal -16 -
Some new cars of the latest years can be qualified as level 1, which means that the vehicle can assist the driver to perform simple driving tasks, such as steering, acceleration or braking, but not simultaneously. A driver must control the vehicle and respond to unexpected situations. An example is the collision mitigation braking system (CMBS), which only permits the vehicle to automatically brake when a collision is imminent.

Currently, the majority of automakers have reached the level 2, such as Tesla Autopilot, Volvo Pilot Assist, and Cadillac Super Cruise System. The often-mentioned adaptive cruise control (ACC) allows the vehicle to follow its predecessor at a safe distance, and to maintain cruising speed and lanes on the highway. However, the driver needs to constantly monitor the changes in the surrounding environment and be prepared

Human Transfer of responsibility Machine

Source: Evercore ISI, SAE International -17 -to take over the vehicle in case of danger.

At the level 3, the driver no longer needs to take over the vehicle and can close the eyes in ideal road conditions, but still requires vigilance. The vehicle can handle almost all driving tasks independently, and it is highly capable of detecting and processing more details in its surrounding environment. Certain automakers have introduced their commercially available level 3 vehicles, such as the Audi A8L with Traffic Jam Pilot and the Mercedes S-Class with Drive Pilot.

The level 4 and level 5 both reach the fully autonomous driving, and the vehicle can perform all driving tasks without driver intervention. The difference is that the level 4 is applicable to some scenarios, usually in cities or on highways. The level 5 has none of these restrictions, the vehicle does not even need a steering wheel, and the driver becomes a passenger. However, these two levels of vehicles are still in the development and testing phase, and significant investments by some automakers and technology companies are expected to accelerate this process. Note that previously described systems such as AEB, ESC, and ACC all belong to the advanced driver-assistance systems (ADAS). In addition, ADAS also includes the pedestrian protection system (PPS), automatic parking system (APS), night vision system The most common sensors in state-of-the-art ADAS are radars, ultrasonic sensors, cameras, and lidars. The primary role is to sense the surrounding environment in real time and provide the vehicle's central processor with accurate and complete data about the road condition, such as obstacles, traffic signals, and road markings.

I.1.2.2. Advanced Driver-Assistance System

As the previous sections explain, radar detects a target by emitting EM waves and receiving echoes. Depending on the frequency and bandwidth, radar is widely applied in ADAS scenarios such as ACC and BSD. In addition, it is less affected by weather conditions such as fog, rain, and snow and can operate at night. Similar to the principle of the radar, ultrasonic sensors use the round-trip time of ultrasound to detect obstacles. Due to the low propagation speed and weak environmental robustness of ultrasound, both the response time and the detection accuracy of ultrasonic sensors are poor. However, because of their low price, they are often adopted in parking systems, and the effective detection range is generally no more than 10 m.

Lidar refers to light detection and ranging, which scans the environment with laser beams. Because the wavelength of the laser signal can reach the nanometer level, lidar offers higher detection accuracy than radar, and it also allows to detect smaller obstacles and construct their high-resolution three-dimensional (3D) images. However, the attenuation of the laser signal in the air is more aggressive (see Figure I.1.2), especially in harsh weather conditions, so its detection range and stability are lower than those of radar.

Camera sensors are passive sensors that perceive the surrounding environment mainly by capturing real-time image information. Camera sensors permit the acquisition of rich color, contour and brightness information that is impossible with radar and lidar, such as lane monitoring and traffic light recognition. In addition, they also feature mature technology and low price, making them indispensable in autonomous vehicles. The main disadvantages are their sensitivity to light changes and the complexity of image processing algorithms. Table I.1.2 shows a comparison of the sensors as mentioned earlier in ADAS. It can be noted that each kind of sensor has its unique advantages and limitations. Therefore, autonomous vehicles usually use several types of sensors in combination to achieve more stable and comprehensive performances. At the same time, as autonomous driving transitions to higher levels, the demand for high-performance sensors becomes more pressing. In particular, automotive radar is growing rapidly and is replacing other sensors as the dominant sensor in autonomous vehicles thanks to its advantages, such as allweather and all-day capability, easy integration, and cost-effectiveness. A typical example is the 4D imaging mm-Wave radar [I-21]. In contrast to the conventional 3D mm-Wave radar, it can detect not only an object's distance, velocity, and azimuth, but also the vertical height, thus outlining the object. Later, 24 GHz, 60 GHz, and 77 GHz frequency bands were introduced into Subsequently, these bands dominated the global automotive radar market.

I.1.2.3. Automotive Radar Frequency Bands

In fact, 24 GHz UWB was only a temporary option. In 2013, the European Telecommunications Standards Institute (ETSI) and the FCC decided to phase out this 24 GHz UWB. One reason is that the spectrum is crowded as it covers the industrial, scientific, and medical (ISM) band of 24 -24.25 GHz. Moreover, 77 GHz automotive radars outperform 24 GHz automotive radars in many aspects, such as antenna size, resolution, and accuracy. Thus, 24 GHz UWB is no longer applied to new autonomous vehicles from 1 January 2022, which is also known as the "sunset date".

I.1.2.4. Automotive Radar Classification

It is worth mentioning that there are various classifications of automotive radar, which -21 -can generally be separated in three categories according to the effective detection distance: long-range radar (LRR), medium-range radar (MRR) and short-range radar (SRR).

Current autonomous vehicles are equipped with about seven automotive radars (e.g., one LRR, two MRRs and four SRRs). Table I.1.3 summarizes the technical characteristics of these three automotive radar systems operating in the frequency band of 76 -81 GHz. The LRR operating at 76 -77 GHz features a maximum equivalent isotropically radiated power (EIRP) of 55 dBm and a large detection range of up to 250 m, which is primarily deployed at the front of automotive vehicles for ACC. A narrow bandwidth of 600 MHz is sufficient to obtain a moderate distance resolution of 0.5 m and a velocity resolution of 0.6 m/s. Moreover, a precise angular accuracy of 0.1° and a 3 dB beamwidth azimuth of ±15° are necessary to achieve a narrow field of view (FOV).

The MRR operating at 77 -81 GHz provides a maximum detection range of 100 m with an allowable EIRP of 33 dBm. Compared to the LRR, the MRR has comparable bandwidth, distance resolution, and velocity resolution, but requires a 3 dB beamwidth azimuth of ±40° to cover a wider area. The main applications include, but are not limited to, lane-change assistance, cross-traffic alerts and rear collision warnings.

The SRR also operating at 77 -81 GHz offers a maximum detection range of 30 m with an allowable EIRP of 33 dBm, which often adopt the FMCW method to achieve a fine distance resolution of 0.1 m thanks to the UWB of 4 GHz. Moreover, the 3 dB beamwidth azimuth of ±80° provides a large coverage area surrounding the vehicle, allowing for features such as pedestrian and cyclist detection, parking assistance. Empirically, the operating frequency in the RF circuit design should be about one-third of fT. Thus, SiGe BiCMOS process can allow an operating frequency of about 80 GHz, while the CMOS process can only reach about 20 GHz. In order to achieve similar operating frequencies as the SiGe BiCMOS process, CMOS-based circuits must use smaller process nodes.

More recently, those CMOS processes with fT and fmax greater than 200 GHz have started to gradually penetrate the 76 -81 GHz automotive radar field, such as the advanced 65 nm, 45 nm, 28 nm and 22 nm process nodes. Obviously, some of their key characteristics have been disclosed and need to be carefully considered when designing. • Because of the smaller nodes, mature processes, and more available metal layers, these nanoscale CMOS processes can achieve extremely high levels of integration at a very low cost. For example, GlobalFoundries' 22 nm fully depleted silicon-oninsulator (FD-SOI) technology provides up to 10 layers of metal.

• Nanoscale planar CMOS processes permit the supply voltage as low as about 1 V, thus making them very suitable for low-power designs. However, their relatively high threshold voltage of about 0.5 V results in very low headroom voltages, which greatly increases the difficulty of the design.

• Note that the noise performances of nanoscale CMOS processes is still not as good as that of SiGe and GaAs processes.

• FD-SOI technology fits very well into the nanoscale CMOS process. For example, with fT and fmax of about 350 GHz, the 22 nm FD-SOI technology provides the best mm-Wave performances in the most advanced submicron nodes (above 14 nm). This process isolates the entire channel from the substrate via a buried oxide layer, featuring low parasitic capacitance and high speed. Meanwhile, the back-gate bias technique permits more design flexibility and is well suited for low-voltage, lowpower applications. More details will be presented in Chapter II.

• The fin field-effect transistor (FinFET) technology is much more complicated than only reduces the design complexity of the frequency synthesizer (primarily VCO) but also enlarges the maximum chirp bandwidth to 1.93 GHz. In addition, the frequency doubler adopts an injection-locked structure, which is placed between the frequency synthesizer and the PA, providing a favorable isolation. Consequently, the frequency synthesizer no longer needs to drive the PA, which relaxes the requirement for its output power. Two LNAs and a PA are integrated on the chip to provide sufficient bandwidth and gain, and the LNAs can be digitally controlled to further improve frequency calibration capabilities. This automotive radar transceiver is fabricated in a 65 nm CMOS process with a total area of 4.64 mm 2 including pads, and it consumes 343 mW from a 1.2 V supply voltage. The FMCW signal at 76 -77 GHz is generated by the differential Colpitts-based VCO.

The buffer amplifier is dedicated to guarantee high output power and temperature stability. This radar system-on-chip (SoC) utilizes an industry-leading 22 nm FD-SOI process, with a 14 mm 2 chip area and a total power consumption of about 0.7 W, and is expected to be the next generation of low-cost and small-size automotive radar.

I.2. Frequency Synthesizer

As mentioned earlier in Section I.1.1.5, the local oscillator (LO) is one of the key modules of the radar transceiver. It can be employed in the transmitter to synthesize frequency modulated chirp signals for transmitting, and in the receiver to demodulate the received RF signal to extract useful informations. The frequency synthesizer is usually used to provide a stable LO with high spectral purity, which largely determines the overall performances of the transceiver system. Therefore, its design is always a challenge and needs to take into account many constraints and process influences.

I.2.1. Frequency Synthesis Techniques

The choice of the frequency synthesis technique depends on many factors, such as operating frequency, frequency range, phase noise, frequency resolution, design complexity and cost. There are three main types of frequency synthesis techniques: direct analog, direct digital, and indirect or PLL.

The direct analog frequency synthesizer generally produces the desired frequency directly by multiplying, dividing or mixing a reference frequency source. Its main advantages are short time of frequency synthesis and low phase noise. However, due to the requirement of a great number of frequency dividers, mixers and filters, direct analog frequency synthesizers have the disadvantages of large size, complex structure, high spurious and high-power consumption. This method is mainly used in the instrumentation, and is generally not applicable to communication systems. In addition to the DAC and filter, the DDFS is implemented mainly through digital technology, thus offering a high level of integration and low cost. Meanwhile, the short frequency switching time and low phase noise make it suitable for advanced digital Moreover, by modifying the phase-to-amplitude conversion table, flexible output waveforms such as sine, triangle or sawtooth can be obtained. Unfortunately, the DAC process inevitably introduces digital quantization errors, which in turn lead to phase and amplitude distortions. In addition, there are other problems such as large spurs, truncation errors in the phase accumulator, limited word length of the conversion table and leakage of the clock signal. All these factors also limit the achievable frequencies to a few gigahertz.

For operating frequencies up to tens of gigahertz, an indirect frequency synthesizer is generally required. Currently, the implementation of indirect frequency synthesizers is mainly based on PLL, which combines phase feedback and phase-locking techniques to synthesize frequencies. This synthesis technique has the advantages of high output frequency, low phase noise, strong spurious suppression, low cost, and easy integration.

It will be highlighted in the following subsections.

I.2.2. Phase-Locked Loop Fundamentals

In general, PLLs are used to lock the phase and frequency of an oscillator to provide a stable output signal. This output signal frequency is usually a multiple of a highprecision reference frequency, such as that of a crystal oscillator, which also makes it possible to use the same PLL to generate different output frequencies. In addition, since the change in phase with respect to time can be used to calculate the corresponding frequency, the frequency can also be locked as long as the phase of the oscillator is locked.

I.2.2.1. PLL Building Blocks

The PLL is a closed-loop feedback control system. In case of a phase difference between the output frequency of the PLL and the input reference frequency, the error is fed back to the VCO input for frequency correction so that the phase difference is gradually reduced to zero, i.e., the PLL reaches a locked state. As a result, the PLL is able

I.2.2.2. PLL Transfer Functions

We all know that the PLL, as a feedback system, is essentially a nonlinear circuit.

However, when the PLL is in the locked state, its loop behavior is well suited to be characterized by a linear model, which is essential for analyzing the loop stability as well as the noise contribution, etc.

Since the parameter of interest in a PLL is the phase rather than the frequency, the phase relationship between the input and output of each module in the PLL needs to be considered and used to construct the transfer function of the PLL. Therefore, the open-loop transfer function G(s) of the PLL can be written as

𝐺(𝑠) = 𝜙 𝑜 (𝑠) 𝑁 ⁄ 𝜙 𝑒 (𝑠) = 𝐾 𝑃𝐹𝐷 𝐹(𝑠)𝐾 𝑉𝐶𝑂 𝑁𝑠 (I. 2. 1)
Open-loop gain typically decreases monotonically with the frequency, with at least one pole at zero frequency. Moreover, the order of the PLL is defined by the number of the poles of the open-loop transfer function and equals the order of the loop filter plus one.

The type of the PLL is defined by the number of the integrators (poles at the origin or at zero frequency) within the loop. Many critical characteristics of the loop are determined by the type of the PLL, such as the commonly used type-II PLL.

Figure I.2.3 Linear s-domain model of a typical analog PLL.

The closed-loop transfer function H(s) of the PLL is given by

𝐻(𝑠) = 𝜙 𝑜 (𝑠) 𝜙 𝑖 (𝑠) = 𝐺(𝑠)𝑁 1 + 𝐺(𝑠) = 𝐾 𝑃𝐹𝐷 𝐹(𝑠)𝐾 𝑉𝐶𝑂 𝑁 𝑁𝑠 + 𝐾 𝑃𝐹𝐷 𝐹(𝑠)𝐾 𝑉𝐶𝑂 (I. 2. 2)
It can be seen that the closed-loop transfer function is a low-pass function with a DC gain equal to N. Its cutoff frequency is the bandwidth of the PLL. In addition, in order to simplify the analysis, we assume that a simple first-order RC low-pass filter is used as the passive loop filter whose transfer function F(s) can be written as

𝐹(𝑠) = 1 1 + 𝑅𝐶𝑠 = 1 1 + 𝑠 𝜔 𝐿𝑃𝐹 (I. 2. 3)
where 𝜔 𝐿𝑃𝐹 represents the cutoff frequency or -3 dB bandwidth of the LPF. The closedloop transfer function H(s) of this second-order PLL can then be rewritten as

+ F(s) K VCO /s ϕ i ϕ o 1/N ϕ d ϕ e + K PFD - PFD Loop Filter VCO Frequency Divider -36 - 𝐻(𝑠) = 𝐾 𝑃𝐹𝐷 𝐾 𝑉𝐶𝑂 𝑁𝜔 𝐿𝑃𝐹 𝑁𝑠 2 + 𝑁𝜔 𝐿𝑃𝐹 𝑠 + 𝐾 𝑃𝐹𝐷 𝐾 𝑉𝐶𝑂 𝜔 𝐿𝑃𝐹 (I. 2. 4)
According to the classical feedback control theory, H(s) can be reformulated into the standard form as

𝐻(𝑠) = 𝑁𝜔 𝑛 2 𝑠 2 + 2𝜉𝜔 𝑛 𝑠 + 𝜔 𝑛 2 (I. 2. 5)
The natural frequency 𝜔 𝑛 and the damping factor 𝜉 are given by

𝜔 𝑛 = √ 𝜔 𝐿𝑃𝐹 𝐾 𝑃𝐹𝐷 𝐾 𝑉𝐶𝑂 𝑁 (I. 2. 6) 𝜉 = 1 2 √ 𝜔 𝐿𝑃𝐹 𝑁 𝐾 𝑃𝐹𝐷 𝐾 𝑉𝐶𝑂 (I. 2. 7)
The two poles of the closed-loop transfer function can be expressed as

𝑠 1,2 = -𝜉𝜔 𝑛 ± √(𝜉 2 -1)𝜔 𝑛 2 = (-𝜉 ± √𝜉 2 -1) 𝜔 𝑛 (I. 2. 8)
When 𝜉 = 1, the closed-loop transfer function has two coincident real poles and the system is in a critically damped state. When 𝜉 > 1, there are two symmetric real poles and the system is overdamped. When 𝜉 < 1, these two poles become complex and the system is underdamped, and the step response to the input frequency 𝜔 𝑖𝑛 = ∆𝜔 • 𝑢(𝑡) can be obtained by the inverse Laplace transform as

𝜔 𝑜𝑢𝑡 = [1 - 𝑒 -𝜉𝜔 𝑛 𝑡 √1 -𝜉 2 𝑠𝑖𝑛 (𝜔 𝑛 √1 -𝜉 2 𝑡 + 𝜃)] ∆𝜔 • 𝑢(𝑡) (I. 2. 9)
where 𝜃 = sin -1 √1 -𝜉 2 . Note that this step response includes a sinusoidal component The output frequency resolution of the integer-N PLL is equal to the reference frequency FREF and is usually chosen to be the same as the channel spacing of the RF transceiver. The PLL in-band (loop filter bandwidth) phase noise is directly affected by the N value, and the phase noise accumulates to the output in a ratio of 20log(N).

Therefore, the integer-N PLL is not suitable for narrow loop bandwidth applications with very high N values because of its severe phase noise degradation, long settling times, and sensitivity to power supply and substrate noise. In addition, the frequency divider often fractional division is typically accomplished by performing frequency dithering via a sigma-delta modulator (SDM). Unfortunately, due to the large perturbations generated by this continuous frequency division operation, the PFD and charge pump will constantly attempt to correct for transient phase errors, which in turn produces a large number of spurs at the output, while the modulator is also burdened with heavy computational tasks.

In addition, the PLL bandwidth is usually set to less than 10% of the reference frequency to avoid any significant feed-through of the reference source and to maintain loop stability.

I.2.2.4. Limitations of the Analog CPPLL

Remarkably, the analog fractional-N CPPLL is still the dominant architecture for frequency synthesizers in today's RF communications. However, the large area of its analog modules (such as the charge pump, loop filter, and VCO) makes the CPPLL occupy most of the chip area in a frequency synthesizer. In recent years, the performances of the analog CPPLL have been further improved as CMOS processes have entered the deep nanometer node. However, limited by the non-ideal and mismatch properties of analog circuit modules, the chip area of the CPPLL has not been consistently reduced, leading to relatively high chip costs. Furthermore, such an analog-intensive PLL also lacks portability from one process to another, and thus still requires a long design cycle.

Meanwhile, the ongoing reduction of CMOS supply voltage further complicates the design of analog modules of the CPPLL, especially voltage-controlled oscillators. For example, the 22 nm FD-SOI process can have supply voltages as low as 0.8 V, but the threshold voltage is about 0.35 V and the tunable voltage range is extremely narrow.

I.2.3. An Overview of All-Digital Phase-Locked Loop

In order to alleviate these bottlenecks encountered by the conventional analog CPPLL, -39 -TI developed the first generation of all-digital phase-locked loop (ADPLL) that could replace the CPPLL in 2003 [I-64], [I-65]. However, restricted by the CMOS process at that time, the main application scenario was around 2.4 GHz wireless communication system. In recent years, mm-Wave ADPLLs have come into the limelight with the popularity of more advanced 45 nm, 28 nm and 22 nm process nodes. A typical example is the previously mentioned 76 -81 GHz automotive radar. One can be seen that analog PLLs will inevitably be replaced by ADPLLs in certain scenarios in order to maximize the integration benefits of advanced processes.

I.2.3.1. ADPLL Basic Principles

The block diagram of a conventional divider-based ADPLL is depicted in Figure I.2.6.

Its loop mainly consists of a time-to-digital converter (TDC), a digital loop filter, a digitally controlled oscillator (DCO) and a digital frequency divider. Compared with the CPPLL in Figure I.2.2, it can be seen that this ADPLL has a very similar topology.

However, the analog CPPLL uses mainly analog control signals like current and voltage between the modules, while the ADPLL uses mainly digital signals.

Figure I.2.6 Simplified block diagram of an ADPLL based on frequency divider.

The TDC takes the place of the charge pump and converts the time error (or phase error) between the reference frequency FREF and the divider output frequency FDIV into a digital control signal, which is then fed into the digital loop filter to eliminate high frequency noise. Subsequently, the DCO output frequency FOUT can be changed by this pure digital control signal or the oscillator tuning word (OTW). Furthermore, the SDM dynamically modulates a programmable divider to perform a fractional frequency division. Another SDM is introduced into the DCO to obtain ultra-fine frequency resolution by dithering the least significant bit (LSB) of the DCO control signal. Note that not only the TDC structure is deployed to detect phase errors between FREF and FDIV, but Compared to the previous one, this counter-based ADPLL avoids the use of the divider and the wide-range of TDC. Instead, two high-speed counters are used and the resolution can be improved by increasing the number of counter bits. Theoretically, these two architectures are quite similar, except that some modules have different specification requirements. Hereafter we will briefly introduce several core blocks of ADPLL.

I.2.3.2. ADPLL Key Building Blocks

I.2.3.2.1. System Clock Retiming

The clock is very important in digital circuit systems. As shown in

I.2.3.2.2. Time-to-Digital Converter

The CKR frequency generated by the D flip-flop is the same as the FREF frequency, but there is an initial time deviation ∆𝑡 𝑑 between the rising edge of the FOUT and FREF, and this deviation is part of the phase error. Since we expect the ADPLL to be locked on a stable reference frequency FREF, this deviation must be corrected to meet the requirements of some high-precision systems. The TDC is the one used to measure this deviation. Figure I.2.8 shows that this deviation is less than the clock period of FOUT, so the deviation measured by TDC is also called the fractional phase error, i.e., the fractional part of the variable phase.

F REF F OUT Q D clk CKR F REF CKR F OUT ∆𝑡 𝑑 Q D τ F REF F OUT Q 0 Q n-1 Q n Q D Q 1 Q D Q D τ τ τ τ D 0 D 1 D n-1 D n F OUT F REF D 0 D 1 D n-1 D n … 0 1 1 1 0 ∆𝑡 𝑑
-42 -of delay units. In addition, it is also possible to make the delay chain end-to-end in a loop, so as to obtain a large dynamic range with fewer delay units. Note that the implementation of a high-precision TDC is one of the major difficulties in ADPLL design because the TDC is sensitive to power supply noise [I-67].

I.2.3.2.3. Digital Loop Filter

The primary function of a digital loop filter is to suppress digital high-frequency noise and spurs generated by other blocks in the loop such as TDC, DCO, and SDM, thereby There is no doubt that this ADPLL offers excellent mm-Wave performances.

However, from the author's point of view, there are still some minor drawbacks. Firstly, the design and optimization of customized distributed switched-metal capacitors are complicated and susceptible to the process, which goes against the high portability of ADPLLs. Secondly, the algorithm complexity of the gain linearization scheme to calibrate three capacitor banks with different gains is relatively high, particularly at 60 -45 -GHz. Finally, considering the PVT variations, for FMCW radars, especially SRRs, the DCO frequency tuning range needs to be around 15 %. This can be simply interpreted as 8 % for the PVT compensation and 7 % for the chirp generation.

I.2.3.4. Advantages of the ADPLL

With more than a decade of development, the ADPLL is competitive or superior to the conventional analog CPPLL in many aspects, such as integration, portability, configurability, stability, and system noise.

• Integration: many of the analog modules in the CPPLL are implemented based on passive devices, such as capacitors and resistors in the analog loop filter, resulting in a large area. In the ADPLL, except for the inductors and capacitors of the DCO, which occupy a similar area to the VCO, the other modules have a smaller area, especially the digital loop filter. Thus, the ADPLL allows a very high level of integration.

• Portability: most of the modules in the ADPLL are digital circuits, except for customized high-speed circuits such as DCO, TDC and high-speed counters.

Therefore, it is easier to migrate the ADPLL from one process to another, and the design cycle is relatively short.

• Configurability: the signals in the ADPLL are mainly digital, so it is easy to evaluate them to obtain the loop performance and status, and thus to dynamically configure -47 -some loop parameters. A typical example is the loop filter. Once the analog loop filter based on capacitors and resistors in the CPPLL is determined, it is difficult to change its order and loop bandwidth. However, the digital loop filter in the ADPLL has the flexibility to configure its gain KP and KI to further optimize the overall dynamic performance of the loop. In addition, dynamic configuration of the closed-loop response of the CPPLL is extremely challenging, requiring not only monitoring of the VCO transfer function, but also a high-precision DAC to generate the compensation signal, which is why the CPPPL is suitable for narrowband applications. Thanks to the digital signal in the ADPLL, it is much easier to compensate its closed-loop response, such as the commonly used two-point modulation, which not only enables a wideband modulated signal, e.g., more than the loop bandwidth, but also keeps the carrier frequency unshifted.

• Stability: the digital signal in the ADPLL is insensitive to coupling noise from other modules in the transceiver, so the system is more stable.

• System noise: the ADPLL usually includes five noise sources. They are phase noise of the reference signal, quantization noise of the TDC, phase noise and quantization noise of the DCO and quantization noise of the SDM. The CPPLL generally includes six noise sources. They are the phase noise of the reference signal, the thermal noise and flicker noise of the charge pump, the phase noise of the VCO, the quantization noise of the SDM, the thermal noise of the loop filter and the phase noise of the loop divider. The quantization noise of TDC is similar to that of charge pump and is mainly distributed within the loop bandwidth. The phase noise performances of DCO and VCO is basically the same, and the quantization noise of DCO can be reduced to negligible by SDM dithering. The quantization noise of SDM is mainly located at high frequencies outside the loop bandwidth. Moreover, the noise level of the loop filter and divider in the CPPLL is relatively low. Therefore, it can be considered that the noise performances of ADPLL and CPPLL is pretty similar.

Nevertheless, ADPLL will not completely replace CPPLL in the foreseeable future, mainly because of the large fractional spurs in ADPLL, which are caused by the limited accuracy of TDC, making it difficult to meet the requirements of some high-precision systems. In fact, fractional spurs also exist in CPPLL, mainly due to the mismatch, coupling and other mechanisms in the system, but their level is rather low and may be further suppressed by some calibration methods.

I.3. Oscillators

As one of the core modules in a PLL, the performance of the oscillator is critical. This section will briefly review the oscillator fundamentals, especially the LC oscillator. We first analyze the theoretical basis of oscillation through linear feedback systems and negative resistance compensation systems. Then we analyze and compare three different types of oscillators, including ring oscillators, Colpitts oscillators, and differential crosscoupled oscillators. Finally, we present some theories and models of phase noise. All these will contribute to the analysis of DCO performances in the next chapter.

I.3.1. Principles of an Oscillator

The core of an oscillator is a loop with positive feedback at the oscillation frequency and a certain gain to compensate for the energy loss in the feedback path in order to maintain stable oscillations. There are two methods usually used to analyze the oscillator behavior, one is based on a two-terminal linear feedback system, and the other is based on a negative resistance compensation system [I-73]. In the following, we will introduce these two methods.

I.3.1.1. Linear Feedback System

To explain the physical mechanism of oscillations, we can consider the oscillator as a simple linear positive feedback system. As shown in

𝐻(𝑗𝜔) = 𝑌(𝑗𝜔) 𝑋(𝑗𝜔) = 𝐺(𝑗𝜔) 1 -𝐺(𝑗𝜔)𝐹(𝑗𝜔) (I. 3. 1)
When 𝐺(𝑗𝜔 0 )𝐹(𝑗𝜔 0 ) = 1 , the closed-loop gain at angular frequency 𝜔 0 is infinite, which means that any weak noise at 𝜔 0 in the system will be continuously amplified and eventually reach stability and make the system oscillate. Thus, the well-known Barkhausen stability criterion for oscillations is given by

|𝐺(𝑗𝜔 0 )𝐹(𝑗𝜔 0 )| = 1 (I. 3. 2) ∠[𝐺(𝑗𝜔 0 )𝐹(𝑗𝜔 0 )] = 2𝜋𝑛, 𝑛 ∈ {0, 1, 2, … } (I. 3. 3)
That is, in the steady state, the open-loop gain is unity and the total phase shift of the open-loop must be 0° (or a multiple of 360°). In practice, considering the PVT variation -49 -as well as the nonlinearity, the open-loop gain has to be greater than one in the beginning to start up the oscillation.

C P L P C R P L R C R L C L (a) (b) (c) 𝐿 𝑃 = 𝐿 (1 + 1 𝑄 𝐿 2 ) (I. 3. 5) 𝐶 𝑃 = 𝐶 (1 + 1 𝑄 𝐶 2 ) ⁄ (I. 3. 6) 𝑅 𝑃 = 𝑅 𝐿 (1 + 𝑄 𝐿 2 )||𝑅 𝐶 (1 + 𝑄 𝐶 2 ) = 1 + 𝑄 𝐿 2 + 𝑄 𝐶 2 + 𝑄 𝐿 2 𝑄 𝐶 2 2 + 𝑄 𝐿 2 + 𝑄 𝐶 2 (I. 3. 7)
Moreover, at the resonant frequency 𝜔 𝑟 , the Q-factor of this parallel RLC resonant circuit can be written as

𝑄 𝑅𝐿𝐶 = 𝑅 𝑃 𝜔 𝑟 𝐿 𝑃 = 𝜔 𝑟 𝐶 𝑃 𝑅 𝑃 (I. 3. 8)
Due to the presence of the lossy RP, the energy in the resonant circuit drops as it oscillates, and the amplitude decreases until the oscillation stops. In order to maintain stable oscillation, it is necessary to compensate for these losses in the circuit.

I.3.2. Different Types of Oscillators

I.3.2.1. Ring Oscillators

The basic architecture of a ring oscillator is depicted in the output of the last inverter is fed back to the input of the first inverter, so that the total phase shift of the loop is an integer multiple of 2π radians. The oscillation frequency of this single ended ring oscillator can thus be expressed as

𝑓 𝑟𝑜 = 1 𝑁𝑇 𝑑 (I. 3. 9)
where N represents the number of inverters in the inverter chain, Td represents the time delay for a single inverter. Therefore, the oscillation frequency of the ring oscillator is highly dependent on the number of inverters and the process.

Figure I.3.4 Ring oscillator based on an inverter chain.

The ring oscillator can be implemented entirely based on transistors, avoiding the use of large inductors and leading to a very compact structure and small size. It can also provide multi-phase outputs and a wide tuning range. However, its shortcomings are fatal.

When the inverter is charged and discharged, for example, noise from the power supply or the transistor itself is injected into the signal path. Thus, the phase noise performances of ring oscillators are much worse than those of oscillators using LC resonators, which greatly limits their use in low-noise applications. Therefore, we do not describe it in detail here.

I.3.2.2. Colpitts Oscillator

The LC oscillator can be implemented with an LC resonant tank and a single MOS The commonly used approaches are to insert an inductive divider or capacitive divider in the feedback path, the so-called Hartley oscillator and Colpitts oscillator.

𝑓 𝑐𝑜 = 1 2𝜋√𝐿 𝑃 𝐶 1 𝐶 2 𝐶 1 + 𝐶 2 (I. 3. 10)
The oscillator voltage gain gmRP to maintain stable oscillation can be derived as

𝑔 𝑚 𝑅 𝑃 = 𝐶 2 𝐶 1 (1 + 𝐶 1 𝐶 2 ) 2 ≥ 4 (I. 3. 11)
where gm is the transconductance of M1 and RP is the equivalent parallel resistance of the resonator. It can be derived that when 𝐶 1 = 𝐶 2 , the voltage gain is minimized to 4.

Therefore, a critical drawback of the Colpitts oscillator is that it requires a voltage gain of at least 4. Considering the difficulty of implementing a high Q-factor inductor in CMOS processes, the RP is generally small, so the Colpitts oscillator requires a high transconductance, leading to an increase in power consumption.

VDD

C 1 R P L P V B V OUT R P L P g m V 1 V 1 + - C 1 C 2 V OUT (a) (c) VDD C 1 C 2 R P L P V B V OUT (b) M1 M1
-53 -In addition, as the major noise source of the Colpitts oscillator, the MOS transistor M1 needs to be optimized in terms of its size and bias. For example, the thermal noise of M1 can be reduced by usually increasing the size of M1 and reducing the bias current, however, the former introduces a large parasitic capacitance and the latter reduces the voltage swing. cross-connected gates and drains, which can be analyzed using the concept of negative The input current IIN is given by

I.3.2.3. Differential Cross-Coupled Oscillator

+ - V GS2 g m V GS1 g m V GS2 + - V GS1 Y IN V IN I IN VDD ( a
𝐼 𝐼𝑁 = 𝑔 𝑚 𝑉 𝐺𝑆2 = -𝑔 𝑚 𝑉 𝐺𝑆1 (I. 3. 13)
The negative resistance can be derived by

𝑉 𝐼𝑁 𝐼 𝐼𝑁 = 𝑉 𝐺𝑆1 𝐼 𝐼𝑁 - 𝑉 𝐺𝑆2 𝐼 𝐼𝑁 = - 1 𝑔 𝑚 - 1 𝑔 𝑚 = - 2 𝑔 𝑚 (I. 3. 14)
In addition, the equivalent parallel impedance of the combined LC resonant circuit is 2RP, the absolute value of the negative resistance generated by the cross-coupled pair needs to be no greater than 2RP, which can be expressed as

2 𝑔 𝑚 ≤ 2𝑅 𝑃 (I. 3. 15)
Thus, we have

𝑔 𝑚 𝑅 𝑃 ≥ 1 (I. 3. 16)
That is, when 𝑔 𝑚 ≥ 1 𝑅 𝑃 ⁄ , the energy dissipated by RP can be continuously compensated by the active cross-coupled pair and the oscillator starts to oscillate.

The cross-coupled oscillator offers a number of advantages. Firstly, compared to the Colpitts oscillator it can be seen that the cross-coupled oscillator no longer requires a very high MOS transistor transconductance. Secondly, this simple differential structure facilitates the elimination of common-mode noise. Moreover, the cross-coupled oscillator is capable of operating at low supply voltages, such as 0.8 V, which makes it very suitable for some low-power scenarios. Finally, the cross-coupled oscillator allows for large voltage swings, resulting in excellent phase noise.

Reviewing the literature, one can learn that there are many different topologies of the cross-coupled oscillator, and new structures are emerging all the time. To simplify the analysis, three commonly used structures will be highlighted and discussed, which are NMOS-only structure, PMOS-only structure, and complementary structure.

-55 -

I.3.2.3.1. NMOS-Only Structure with Tail Current Source

As illustrated in Figure I.3.7 (a), the NMOS-only structure with a tail current source is the most classic and commonly adopted LC oscillator structure. Since the electron mobility is much higher than that of holes, under the same size, the transconductance that the NMOS transistor can provide is about twice larger than that of the PMOS transistor, but the price is that the flicker noise of the NMOS transistor is higher. Therefore, compared to the PMOS-only structure, for the same transconductance and the same bias current, the NMOS-only cross-coupled pair has a smaller size, i.e., less parasitic capacitance. Alternatively, for the same transconductance and the same crosscoupled pair size, the NMOS-only cross-coupled oscillator features a lower power consumption.

Note that the tail current source plays a very critical role in controlling power dissipation and phase noise. By providing a stable bias current for the cross-coupled pair, the tail current source can speed up the switching of the differential pair, as well as reduce the oscillator's sensitivity to changes in supply voltage and optimize phase noise by manipulating the output voltage swing. This is why many cross-coupled oscillators incorporate a tail current source, even though the tail current itself can introduce noise.

The NMOS-only cross-coupled oscillator can also provide an output voltage swing in excess of the supply voltage, making it suitable for low supply voltage scenarios.

VDD VDD VDD V B V B V B (a) (b) (c)
-56 -However, considering the hot-carrier injection (HCI) effect, excessive voltage swing can reduce the lifetime of the cross-coupled pair, which needs to be taken into account in the design.

Moreover, the cross-coupled oscillator can also be biased by a top current source. The high output impedance of the top current source suppresses the effect of supply voltage variations on the resonant LC tank. However, the top current source itself will continuously inject noise, which in turn leads to a poor phase noise performance.

I.3.2.3.2. PMOS-Only Structure with Top Current Source

Compared to the former, the PMOS-only cross-coupled oscillator leads to higher power consumption and larger parasitic capacitances. However, it has better phase noise performances due to the lower flicker noise and thermal noise (larger size) of the PMOS transistors than that of the NMOS ones. In addition, the high output impedance of the top current source isolates the supply voltage from the resonant LC tank, further enhancing the phase noise performances.

I.3.2.3.3. Complementary Structure with Tail Current Source

This complementary structure combines NMOS transistors and PMOS transistors to provide the negative resistance required for the resonant LC tank. One of its distinct advantages is low power consumption. For the same bias current, it has twice the output voltage swing of the NMOS-only or PMOS-only structure. Furthermore, the rising and falling times of its output waveform are more symmetrical, which contributes to the reduction of flicker noise and thus improves phase noise performances. Therefore, the complementary structure is well suited for low-power, low-phase noise applications.

However, it also suffers from some significant drawbacks. Firstly, the introduction of an extra transistor between power and ground makes the implementation of this structure difficult considering the low supply voltage of 0.8 V and the threshold voltage of about 0.35 V for advanced processes. Although this issue can be addressed by removing the tail current source, this would require a high-performance low-dropout regulator (LDO) to stabilize the supply voltage and would also lead to an increase in power consumption.

Secondly, the maximum voltage swing allowed by the complementary cross-coupled oscillator is small, which is not favorable for further phase noise improvement. Therefore, without considering the power consumption, the optimal phase noise achievable by this complementary structure is significantly worse than the previous two structures. Finally, -57 -this structure introduces a large parasitic capacitance, which ultimately leads to a reduction in the output frequency and frequency tuning range of the oscillator.

I.3.3. Phase Noise Analysis of the Oscillators

Phase noise is one of the most important indicators of how good an oscillator is and how it affects the sensitivity of an RF transceiver. The noise sources of the LC oscillator can be classified into two main categories: internal noise and external interference noise.

The former includes thermal noise, flicker noise, etc. The latter includes supply voltage noise as well as substrate coupling noise, etc. This section will therefore focus on the main sources of phase noise, its definition and the classical phase noise model. where k is the Boltzmann constant ( = 1.38 × 10 -23 J/K), T is the absolute temperature, R is the resistance, ∆f is the bandwidth around the frequency f. In addition, the channel resistance of MOS transistors also produces thermal noise, which can be modeled by a noise current source 𝐼 𝑛 2 connected between the drain and source terminals whose spectral density can be expressed as

𝑆 𝑖 (𝑓) = 𝐼 𝑛 2 ∆𝑓 ̅̅̅̅ = 2 3 • 4 𝑇𝑔 𝑚 (I. 3. 18)
where 𝑔 𝑚 is the transconductance of the MOS transistor and the factor 2/3 is only applicable to long-channel devices. For short-channel devices, the thermal noise becomes much greater as the strong electric field makes the charge heated.

I.3.3.1.2. Shot Noise

The shot noise is mainly found in active non-linear devices with DC currents. The carriers need to have sufficient energy and speed to cross the potential barrier, and each carrier crossing the barrier can be seen as a random event, i.e., an independent small current pulse. The fluctuations in the current caused by these current pulses can be described in terms of shot noise. The spectral density is given by

𝑆 𝑖 (𝑓) = 𝐼 𝑛 2 ̅̅̅̅ ∆𝑓 = 2𝑞𝐼 (I. 3. 19)
where q is the amount of charge, I is the DC current. Since the carriers cross the potential barrier at random times, the shot noise is frequency independent and is also a white noise.

I.3.3.1.3. Flicker Noise

The flicker noise is mainly caused by lattice defects at the interface between singlecrystal silicon and its oxide during the fabrication of MOS transistors. Flicker noise is also known as 1/f noise, and its spectral density can be expressed as

𝑆 𝑖 (𝑓) = 𝐼 𝑛 2 ̅̅̅̅ ∆𝑓 = 𝛾ℎ 𝑓 𝛼 𝑁 𝐼 2 (I. 3. 20)
where 𝛾ℎ is the global Hooge coefficient, 𝛼 is an empirical coefficient, N is the number of carriers, and I is the DC current.

I.3.3.2. Definition of the Phase Noise

In the ideal case, i.e., without noise, the output of the oscillator is a single frequency sine wave, which can be expressed as

𝑉 𝑂𝑈𝑇 (𝑡) = 𝐴 𝑐𝑜𝑠(𝜔 0 𝑡 + 𝜙) (I. 3. 21)
where A is the amplitude, 𝜔 0 is the angular frequency, and ϕ is the phase. It can be seen that the amplitude and phase of the oscillator are fixed. As shown in Figure I.3.8 (a), its power spectral density is a pulse (blue arrow) at the angular frequency 𝜔 0 .

However, the active and passive devices that make up the oscillator inevitably introduce some noise, such as the previously mentioned thermal noise, shot noise and flicker noise. In practice, these noises constantly disturb the phase and amplitude of the oscillator output signal, causing its power spectral density to extend from 𝜔 0 to both sides, and thus two sidebands appear as shown in the gray area in where both amplitude A(t) and phase ϕ(t) are functions of time t. Therefore, the noise of the oscillator is mainly manifested as amplitude noise and phase noise. Normally, the amplitude noise is attenuated by the amplitude limiting circuit or nonlinear circuit and does not have a significant impact on the circuit performances. However, the phase noise cannot be eliminated and needs to be carefully considered in the oscillator design. The phase noise of the oscillator is usually expressed as the ratio of the single sideband noise power per unit bandwidth (1Hz) at a certain offset angular frequency ∆𝜔 deviating from the carrier 𝜔 0 to the carrier power, which can be denoted as

𝐿{∆𝜔} = 10 𝑙𝑜𝑔 [ 𝑃 𝑠𝑖𝑑𝑒𝑏𝑎𝑛𝑑 (𝜔 0 + ∆𝜔, 1𝐻𝑧) 𝑃 𝑐𝑎𝑟𝑟𝑖𝑒𝑟 ] (I. 3. 23)
where Δω is the offset angular frequency, 𝑃 𝑠𝑖𝑑𝑒𝑏𝑎𝑛𝑑 (𝜔 0 + ∆𝜔, 1𝐻𝑧) is the single sideband power per unit bandwidth at the offset angular frequency Δω, and 𝑃 𝑐𝑎𝑟𝑟𝑖𝑒𝑟 is the total carrier power. The unit of phase noise is dBc/Hz, where dBc refers to the ratio of the two powers (dB).

I.3.3.3. Phase Noise Models

For decades, a lot of research works have been carried out to understand the physical

𝐿{∆𝜔} = 10 𝑙𝑜𝑔 { 2𝐹 𝑇 𝑃 𝑠 • [1 + ( 𝜔 0 2𝑄 𝐿 ∆𝜔 ) 2 ] • (1 + ∆𝜔 1 𝑓 3 ⁄ |∆𝜔| )} (I. 3. 24)
where F is the noise factor, k is the Boltzmann constant, T is the absolute temperature, Ps is the average power dissipated in the resistive part of the resonator, ω0 is the carrier angular frequency, QL is the loaded quality factor of the resonator, ∆𝜔 is the offset angular frequency from the carrier, and ∆𝜔 1 𝑓 3 ⁄ is the corner frequency between the 1 𝑓 3 ⁄ region and the 1 𝑓 2 ⁄ region.

It can be concluded that a low phase noise can be achieved by increasing the power dissipated in the resistive part of the resonator or by improving the quality factor of the LC resonator. Furthermore, the phase noise of the oscillator can be partitioned into three different regions, as shown in Figure I.3.9.

Figure I.3.9 Typical characteristic curve of oscillators' phase noise

• When the frequency offset is less than ∆𝜔 1 𝑓 3 ⁄ , the phase noise rolls off at a rate of 1 𝑓 3 ⁄ , i.e., the slope of the phase noise curve is 30 dB/decade, so this region is called the 1 𝑓 3 ⁄ region. In this region, the flicker noise plays a dominant role.

• When the frequency offset is between ∆𝜔 1 𝑓 3 ⁄ and ∆𝜔 1 𝑓 2 ⁄ , the slope of the phase noise curve becomes 20 dB/decade, which corresponds to the 1 𝑓 2 ⁄ region. In this region, the thermal noise plays a dominant role. ), which is independent of frequency. Moreover, the frequency offset

∆𝜔 1 𝑓 2 ⁄ is close to 𝜔 0 2 ⁄ 𝑄 𝐿 .
However, because the oscillator itself is a nonlinear circuit, there are some shortcomings in the analysis with a linear time-invariant model. For example, experimental data are required to obtain the noise factor F, and corner frequency ∆𝜔 1 𝑓 3 ⁄ cannot be directly determined, thereby leading to inaccurate prediction of the phase noise performances of the oscillators. In addition, ∆𝜔 1 𝑓 3 ⁄ is considered to be the same as the corner frequency of the MOS transistor' flicker noise, which does not match well with the actual measurement results.

In response to these shortcomings of the where 𝛾 is the MOS transistor channel current noise factor, A is the amplitude of the output signal, Ibias is the bias current, gm,bias is the transconductance of the tail MOS transistor. The first term represents the thermal noise contribution of the LC resonator tank, the second term represents the noise contribution of the differential cross-coupled pair, and the third term represents the noise from the tail current source.

As we know, in the case of small voltage swing, the output amplitude A can be expressed as 𝐴 = (2𝐼 𝑏𝑖𝑎𝑠 𝑅 𝑃 )/𝜋 , where the second term is approximately equal to a constant 𝛾. As the bias current 𝐼 𝑏𝑖𝑎𝑠 increase, both the power consumption Ps and the output voltage swing increase, so that the on-time of the cross-coupled pair decreases, i.e., the time of noise injection also decreases, which eventually manifests as a phase noise improvement. This region where the phase noise is boosted as the bias current increases -62 -is known as the current-limited region. Beyond the current-limited region, the voltage swing does not change as the bias current continue to increase, and the phase noise enters a relatively stable state, although the power consumption continues to increase, and this region is known as the voltage-limited region. It can be concluded that the best phase noise performances can be obtained in the transition region from the current-limited region to the voltage-limited region.

To better understand the noise contribution of the tail current source, we can consider the differential cross-coupled pair as a mixer, and then the noise signal of the tail current source is mixed with the carrier signal into the resonant tank. Since the mixer exhibits the maximum conversion gain at the fundamental frequency ω0, the low-frequency flicker noise from the tail current source can be up-converted around ω0. Similarly, the highfrequency thermal noise near 2ω0 can be down-converted near ω0. The latter can be attenuated by adding an LC resonator with a frequency around 2ω0.

I.3.3.3.2. Linear Time-Variant Model

The time-invariant model assumes that the noise has the same effect on the result of the oscillator output at any moment, which is apparently not rigorous enough. Based on this fact, a linear time-variant model has been proposed by Hajimiri et al.,.

For each noise source, the system can be considered as a single-input, single-output system, so the time-domain impulse response of the amplitude A(t) and phase ϕ(t) of the oscillator can be characterized as shown in For the oscillator, it is known from the above analysis that the ISF reaches its maximum value at the zero-crossing point of the oscillation signal, while the ISF is 0 at the peak of the oscillation signal. The mathematical model of the phase noise given by Hajimiri is

𝐿{∆𝜔} = 10 𝑙𝑜𝑔 ( 𝑖 𝑛 2 ̅ ∆𝑓 ∑ 𝑐 𝑛 2 ∞ 𝑛=0 4𝑞 𝑚𝑎𝑥 2 ∆𝜔 2 ) (I. 3. 27)
where 𝑖 𝑛 2 ̅ ∆𝑓 ⁄ represents the power spectral density of the white noise considered, 𝑐 𝑛 is the Fourier coefficient of the ISF function, 𝑞 𝑚𝑎𝑥 is the maximum charge swing across the capacitor on the node, and ∆𝜔 is the offset angular frequency. This formula indicates that

i(t) τ i(t) ϕ(t) ℎ 𝑡, 𝜏 ϕ(t) i(t) τ i(t) A(t) ℎ 𝑡, 𝜏 A(t) τ τ t t t t C L i(t) (a) (b) ∆V t t t t ∆V i(t) V OUT i(t) V OUT -64 -
the noise located near an integer multiple of the oscillator frequency is shifted to the vicinity of the carrier frequency through the up-conversion or down-conversion process.

As shown in Figure I.3.12, the noise in the 1 𝑓 3 ⁄ region is mainly the low-frequency flicker noise of the MOS transistor weighted by the coefficient 𝑐 0 . The noise in the 1 𝑓 2 ⁄ region is the sum of the white noise on higher harmonics weighted by coefficients 𝑐 𝑛 , and the white noise region is the white noise of the oscillator itself. It can be concluded that Hajimiri's time-variant model not only elaborates the contribution of each noise sources in the oscillator to the overall phase noise, but also provides a relatively accurate method for calculating the phase noise, although solving the ISF function for each noise source is complex. In general, benefiting from this model, we can reduce the effect of some specific noise sources at the beginning of the design.

I.4. Conclusion

The purpose of our research project is to design a high-performance K-band DCO, which is one of the core modules of an ADPLL used in a 76 -81 GHz FMCW automotive radar. Therefore, in this chapter, we introduced the research background in three main aspects: the automotive radars, the frequency synthesizer and the oscillator.

ω 0 2ω 0 3ω 0 Δω Δω Δω 𝑖 𝑛 2 ̅ 𝑆 𝜔 𝑆 𝑉 𝜔 Δω 𝐶 0 𝐶 1 𝐶 2 𝐶 3 PM ω 0 -65 -
In Section I.1, we began with the introduction of radar fundamentals, i.e., radarfrequency bands, radar types, radar equations, and commonly used transceiver architectures. Then, we reviewed the autonomous driving technology, including the level of autonomy, the ADAS system, the development and classification of automotive radars.

Moreover, typical processes applied to automotive radars and related academic and commercial works were also discussed.

In Section I.2, we first reviewed several common frequency synthesis techniques.

Next, we introduced two basic structures of the analog PLL (integer-N type and fractional-N type), and then analyzed some key loop characteristics through its transfer functions. Finally, we presented some core modules and two widely used structures of the ADPLL (loop divider-based structure and loop counter-based structure) and summarized its advantages and disadvantages. It can be concluded that the ADPLL features great advantages in terms of integration, power consumption, and low supply voltage, which certainly cannot be achieved without a high-performance DCO.

In Section I.3, we first reviewed the basic principles of oscillators, including the linear feedback system and the negative resistance compensation system applied to the determination of start-up conditions. Secondly, we compared three popular structures of oscillators, which are ring oscillators, Colpitts oscillators and differential LC crosscoupled oscillators. The latter is also the structure that will be used in our highperformance DCOs. Finally, we presented some critical noise sources in electronic devices and exposed the phase noise performances of oscillators by the classical Leeson's model and Hajimiri's model, and these theories are also applicable to the phase noise analysis of DCOs.

I.5. Résumé du Chapitre I

CHAPTER II

K-Band Triple-Bank DCO (T-DCO) Design

As the core frequency generation module, the DCO mainly determines the overall performances of the ADPLL. Like the conventional VCO, the DCO design suffers from three trade-offs: frequency tuning range, frequency resolution, and phase noise. Moreover, when a DCO is used to generate frequency-modulated chirp, the linearity of frequency tuning also becomes very important. This chapter will focus on some key issues in the design of high-performances K-band DCOs. In Section II.1, we will briefly introduce the GlobalFoundries' 22 nm FD-SOI process (also known as 22 FDX technology) and its main highlights. In Section II.2, the principles and types of DCOs will be summarized. In Section II.3, we will review the development and current research status of DCOs and highlight some typical frequency tuning techniques found in the literature. In Section II.4, we will present the principle of FMCW radars and DCO gain calibration, which is the theoretical basis for the DCO proposal. In Section II.5, we will detail the circuit implementation and simulation results of the proposed K-band low-phase-noise triplebank DCO (T-DCO) for 76 -81 GHz FMCW automotive radars, involving a novel backgate-based fine-tuning structure.

II.1. Overview of 22FDX Technology

II.1.1. Supported EDA Tools

Before introducing the DCO, we first give the EDA (Electronics Design Automation) tools we are currently using and their corresponding versions in Table II.1.1. Virtuoso integrates powerful mixed-signal chip design capabilities that support full-flow design from front-end to back-end. ICADV is Virtuoso's version for advanced node processes.

-76 -Spectre is a multi-mode (Spectre, Spectre APS, Spectre X, Spectre XPS MS, etc.) simulation tool for custom chip simulations. Actually, the Spectre APS is used in our simulations. Moreover, with the exponential growth in design rule check (DRC) complexity in advanced nodes, first-and second-generation DRC solutions can no longer support the turnaround requirements needed to ensure that design schedules are met. As

II.1.2. Preferred Choice for Automotive Radar: FD-SOI

It is well known that the performances of early MOS transistors continued to improve as their size shrank. However, as its gate length approaches 20 nm, its ability to control the current drops dramatically, and the leakage current rises significantly, which makes the conventional planar bulk CMOS technology no longer applicable. Based on this fact, the three-dimensional FinFET technology and the FD-SOI technology, which allows Moore's Law to continue today. Moreover, it is worth mentioning that only FinFET technology is feasible in smaller nodes (< 20 nm), however, its cost is too high and it is only suitable for applications with large volumes (mainly for digital circuits) and ultrahigh performances. Therefore, planar FD-SOI technologies (28 nm, 22 nm) remain the mainstream for commercial applications due to its cost-effectiveness and FinFET-like performance with energy-efficiency. • The thin silicon layer in FD-SOI improves the ability of the gate to fully turn off and on the transistor, thus enabling higher circuit speeds and allowing it to operate in the millimeter-wave band.

• The buried oxide layer reduces the parasitic junction (source, drain) capacitance as well as various types of noise, and also effectively suppresses electron flow from source to drain, thus significantly reducing the leakage current that causes performances degradations and improving the threshold voltage stability.

• FD-SOI provides a robust back-gate bias function. By controlling the back-gate bias voltage, the threshold voltage can be flexibly changed to optimize the power consumption and performances of the circuit. mV/V, which is much higher than the variation rate in the bulk CMOS process (25 mV/V).

Figure Moreover, it should be noted that the 22FDX technology offers several different libraries, with three being primarily used for our design: the core library (cmos22fdsoi), the RF library (cmos22fdsoi_rf), and the mm-W library (cmos22fdsoi_mmw). As the names implies, the RF and mm-W libraries are mainly suitable for RF and mm-W circuit designs. Of course, in actual design, it is necessary to flexibly select the device type, backgate voltage, and process library for optimal performances.

II.2. Introduction to DCO

Vbg = 0 V Vbg = 1 V Vbg = 2 V V D = 0.8 V, V S = 0 V lvtnfet: W = 100 nm, L = 20 nm
-82 -the y-axis. Moreover, in practice, the value of KVCO is not constant, which leads to nonlinearity in the frequency tuning of the VCO. • The supply voltage gradually decreases as the CMOS process scales, and the nominal voltage for the advanced 22 nm FD-SOI process can be as low as 0.8 V. Such a low voltage makes it difficult for VCOs in advanced nodes to achieve wide frequency tuning range, high resolution and low phase noise simultaneously.

• The nanoscale transistor features a relatively high threshold voltage, such as 0.35 V, further reducing the available voltage margin.

•

V ctrl f 0 f 1 f 2 V 1 V 2 V ctrl f out MOS Varactor -83 -

2(c). The control voltage

Vctrl is applied to the common pin 2, the DC voltage of the two differential gates (pin 1) is 1.2 V. The employed egncap_rf has a single polysilicon finger with a length and width of 250 nm and 1 μm, respectively.

II.2.2. Different Types of DCO

II.2.2.1. RO-Based DCO

In Chapter I, the basic principle of a single-ended ring oscillator based on a chain of inverters has been described, whose oscillation frequency can be regulated by changing the number or the delay time of the inverters. Therefore, an RO-based DCO can be implemented by digitally controlling these two parameters.

II.2.2.1.1. Changing the number of inverters

A typical structure of this type of RO-based DCO is shown in The advantage is that this structure allows the use of an existing VCO in a digital PLL.

However, the performances of the DAC-based DCO are strongly dependent on the DAC itself. Since DAC introduces additional power consumption and noise, and the matching design between DAC and VCO is quite complex, thus, this approach is not widely used.

II.2.2.3. LC-Based DCO

The achievable frequency tuning range of early VCOs relying on MOS varactors is often narrow. Therefore, a straightforward approach to enlarge the frequency tuning range

∆𝐶 𝑘 = 𝐶 1,𝑘 -𝐶 0,𝑘 (II. 3. 2)
where 𝐶 1,𝑘 and 𝐶 0,𝑘 represent the high and low capacitance, respectively. Considering the digital control bit 𝑘 ̅̅̅ , the capacitance of kth PMOS varactor can be expressed as

𝐶 𝑘 = 𝐶 0,𝑘 + 𝑘 ̅̅̅ • ∆𝐶 𝑘 (II. 3. 3)
Hence, the Equation (II. respectively. Thus, the capacitance of kth switched capacitor is

𝐶 𝑘 = 𝐶 0 • 2 𝑘 + 𝑘 ̅̅̅ • ∆𝐶 0 • 2 𝑘 (II. 3. 5)
Therefore, as shown in Figure II.3.2, the total capacitance of the binary-weighted switched-capacitor bank of size N can be expressed as

𝐶 𝐵 = ∑(𝐶 0 • 2 𝑘 + 𝑘 ̅̅̅ • ∆𝐶 0 • 2 𝑘 ) 𝑁-1 𝑘=0 -88 - = ∑ 𝐶 0 • 2 𝑘 𝑁-1 𝑘=0 + ∑ 𝑘 ̅̅̅ • ∆𝐶 0 • 2 𝑘 𝑁-1 𝑘=0 (II. 3. 6) = 𝐶 0,𝑆𝑈𝑀 + ∑ 𝑘 ̅̅̅ • ∆𝐶 0 • 2 𝑘 𝑁-1 𝑘=0
where the first term 𝐶 0,𝑆𝑈𝑀 represents all non-adjustable capacitance, and the second term represents the effective capacitance for frequency regulation of the DCO. Once the ADPLL is powered on, the PVT and acquisition banks coarsely set the desired frequency in sequence for channel selection. Since these two banks need to achieve a wide frequency range at the cost of a relatively poor frequency resolution, the

𝑁-1 1 0 ∆C 0 C 0 2 N-1 2 1
Basic Unit -89 -binary-weighted structure is employed to arrange a large number of PMOS varactors.

Therefore, based on the Equation (II. 3.6) the total capacitance of these two banks can be given by

𝐶 𝑃 = 𝐶 0 𝑃 + ∑ 𝑘 ̅̅̅ 𝑃 𝑁 𝑃 -1 𝑘=0

II.3.2. Overview of Frequency Tuning Techniques

In recent years, one of the research hotspots of DCOs is their frequency tuning techniques. In addition, according to different application scenarios, some DCOs also aim to achieve low power consumption or low phase noise, which is mainly related to the choice of the DCO structure, but also cannot be separated from the frequency tuning techniques. Therefore, in this subsection, we will highlight several typical frequency tuning techniques found in the literature.

II.3.2.1. Mismatched MOS Varactors

In order to achieve a finer frequency resolution than the traditional single MOS Apparently, this type of mismatched structure allows for a tiny capacitance difference;

however, the stability of this structure is highly dependent on the process. Moreover, as shown in Figure II.3.5(c), an optimized differential structure using only one NMOS switch was proposed in [II-19] and adopted in where the inverter does not consume any static power and the main role of the large resistors is to bias the voltage -92 -at the drain/source of M0 to VDD in the OFF state, thereby reducing and getting a better control of the capacitance due to the reverse biased drain-to-bulk junction. In addition, there is only one ON parasitic resistor in this structure, so its Q-factor is about twice that of the previous structure for the same size MOS switch; however, its parasitic capacitance in the OFF state is higher.

II.3.2.2. Switched Capacitors

C 2C 3C 4C M 0 M 1 M 0 (b) (c) V BIAS EN EN EN EN EN EN VDD EN VBB M 0 M 0 M 0 M 2 M 1 M 4 M 3 M 1 M 2 M 3 M 4 M 1 M 2 M 0 M 1 M 2 M 3 M 4 EN EN M 0 M 1 M 2 (d) (e) (f) (g) (h) A B A B A B A B A B A B V S -93 -
The gates of two pull-up PMOS transistors are directly connected to the enable signal EN, avoiding the use of the bias circuit and the inverter. Therefore, the same functionality as the previous structure can be achieved by using only five transistors. However, it is still a more complex structure compared to To the author's knowledge, the K-band DCO in achieves the best PN of -106.6 dBc/Hz. However, it is a dual-band design with a minimum frequency resolution of ~187

II.3.3. Performances Summary of LC-Based DCOs

MHz. Moreover, the mm-W DCO in [II-28] has only one frequency-tuning bank and its frequency resolution is up to ~1.39 GHz. It can be seen that none of them can meet the requirements of FMCW automotive radar.

Note that the DCO in [II-37] using a multi-stage C-2C exponentially scaling switched-capacitor ladder achieves very fine frequency resolution (several Hz), similar to the DCO in . However, the implementation of this type of DCO is more complicated and is susceptible to various constraints, such as the scaling factor and the matching problem, thereby limiting its application.

II.4. DCOs for FMCW Radars

Most of the DCOs mentioned in the previous section are not applicable to FMCW radars, which have more stringent requirements for DCOs, requiring not only excellent phase noise performances, but also a large frequency tuning range to generate chirp signals. Therefore, before presenting the proposed DCO, we will first analyze the principle of FMCW radars for detecting stationary and moving targets, and then briefly introduce the DCO gain calibration and linearization in chirp signal generation. These details are essential to the design of the DCO and to understand its specifications.

II.4.1. Principle of FMCW Radars

As we know, unmodulated continuous-wave (CW) radar emits a constant frequency signal, which can only detect the relative velocity of a target through a Doppler shift. In order to determine the distance to the target simultaneously, frequency-modulated continuous-wave (FMCW) radar is commonly employed. In the following, we will briefly introduce the principle of FMCW radars for stationary target and moving target detections, -99 -respectively. Taking into account ∆𝑡 ≪ 𝑇 𝑚 , the baseband beat frequency fb generated by the down-

II.4.1.1. Stationary Target Detection

t f(t) Transmitted signal t B f b f b f(t) f L f H T m
Received signal ∆t -100 -conversion represents the frequency difference between the transmitted signal and the received signal and is given by

𝑓 𝑏 = |𝑓 𝑇 (𝑡) -𝑓 𝑅 (𝑡)| = 2𝐵 𝑇 𝑚 • ∆𝑡 = 4𝐵 𝑐 • 𝑇 𝑚 • 𝑅 (II. 4. 3)
This beat frequency is proportional to the distance and is usually at the megahertz level for automotive radars. To further determine the range resolution, the limiting case of a beat signal with a duration of Tm/2 (chirp duration) is considered as shown in Figure The Fourier transform or spectrum of this rectangular pulse is given by

|𝑋(𝑓)| = 𝐴𝜏 • 𝑠𝑖𝑛𝑐 (𝜋 𝑇 𝑚 2 𝑓) (II. 4. 5)
The spectrum is plotted in Figure II.4.2(c). Note that the first zero point occurs at the frequency of 2/Tm (and -2/Tm), which is the inverse of the pulse width Tm/2. Typically, the value 2/Tm can also be used as a rough estimation of the frequency resolution. It can be seen that the chirp bandwidth limits the range resolution, and a large bandwidth provides a higher range resolution. For example, for a typical mm-W SRR with a 4 GHz bandwidth (77 -81 GHz), a range resolution of ~3.75 cm can be achieved. However, in practice, the range resolution is further deteriorated due to the use of digital Fourier transform (DFT) for spectrum estimation, even though windowing techniques are applied to enhance the spectrum estimation results. For example, the range resolution is worsened by a factor of 1.8 when using the Blackman-Harris window . Once beat frequencies fb1 and fb2 are determined in the baseband, the velocity vt and the distance R can be approximated by

II.4.1.2. Moving Target Detection

t f(t) Transmitted signal t B f b1 f(t) f L f H T m ∆t Received signal f b2 f d -102 - 𝑣 𝑡 ≈ 𝜆 • (𝑓 𝑏2 -𝑓 𝑏1 ) 4 (II. 4. 10) 𝑅 = 𝑐 • 𝑇 𝑚 • (𝑓 𝑏1 + 𝑓 𝑏2 ) 8𝐵 (II. 4. 11)
where λ is the wavelength of the transmitted signal. Note that any variation in the chirp waveform will affect the accuracy and resolution of the range and velocity measurements.

Consequently, a purely linear chirp is required to obtain high-performance beat frequencies in both stationary and moving target measurements. Therefore, the size of the look-up table is determined by the number of bank-switchover points, and the mid-point of the overlap region is chosen for a robust switchover.

II.4.2. DCO Gain Calibration for Chirp Linearity

Meanwhile, to ensure the monotonic tuning against PVT, the whole fine-tuning range is set to 1.5 times the frequency step size of the medium-tuning bank. It is worth noting that the gains of the fine-and medium-tuning banks vary with different coarse-tuning codes due to the wide coarse-tuning range, which also leads to non-linearity. Therefore, the gains of DCOs need to be continuously calibrated in the background to make the estimation error less than 1% . Moreover, depending on the design requirements, other digital calibration techniques for mitigating DCO non-linearity can be found in [II-44]-[II-48]. Overall, the DCO gain calibration is another complex task that we do not describe in detail here.

II.5. Design and Implementation of a K-Band Low-Phase-Noise T-DCO for 76 -81 GHz FMCW Automotive Radars

II.5.1. Introduction

As the core frequency generation module, the DCO mainly determines the overall performances of the ADPLL. To integrate multi-range detection in a single radar, a DCO with an FTR of ~10 % is required to cover the entire band of 76 -81 GHz. Moreover, considering process, voltage, and temperature (PVT) variations (e.g., harsh operating temperatures from -25° to 125°), the FTR should be extended to ~20 %. In addition, a DCO with low PN and high frequency resolution is necessary to produce a high-purity linear chirp. However, in practice, the Q-factor of the mm-W passive devices is relatively low, which restricts the PN of the DCO, and the large parasitic capacitances associated with the LC tank and active devices limit the FTR. Therefore, achieving low PN and wide FTR simultaneously at mm-W frequencies has always been a great challenge.

A straightforward approach to make the DCO operate at mm-W frequencies is to -104 -design a mm-W LC tank (e.g., at 80 GHz) as mentioned in Section II.3.2.3. Metal strips placed beneath the resonator (i.e., transmission line, inductor, or transformer) are configurated by MOS switches to load the tank with more (or less) capacitance, thereby varying the DCO frequency . However, it is hard to achieve a wide FTR of more than 10 % in this case due to the large parasitic capacitance. Another approach is to design a sub-mm-W LC tank (e.g., at 20 GHz), where mm-W frequencies can be obtained by using multipliers or higher-order harmonics [II-26], . Thus, classical switchedcapacitor structures can still be utilized to reach a wide FTR of ~20 %. However, to our knowledge, the best PN achieved using this approach at 23.7 GHz is -106.6 dBc/Hz at 1

MHz frequency offset, as presented in .

Therefore, our main objective is to explore the feasibility of implementing a K-band high-performance DCO for 76 -81 GHz automotive radars in the advanced 22 nm FD-SOI process. Meanwhile, this DCO needs to achieve both best-in-class phase noise performances, excellent FTR, and high frequency resolution to ensure accuracy and robustness of the automotive radar.

II.5.2. K-Band DCO Design Considerations

II.5.2.1. DCO Specifications

Since the proposed DCO is intended for the FMCW automotive radar, its design needs to meet some specifications as outlined in Table II.5.1. Prior to the design process, it is imperative to highlight several essential constraints that are listed as follows:

• The K-band DCO output frequency needs to completely cover the frequency band of 19 -20.25 GHz, which is a quarter of the 76 -81 GHz, and is mainly used to generate linear frequency-modulated (chirp) signals;

• The coarse-tuning step is about 200 MHz, and the coarse-tuning bank is dedicated to compensate for PVT variations;

• The fine-tuning step is approximately 2.5 MHz, which allows the output frequency of a FMCW radar to be swept linearly over time at this step while ensuring a low level of quantization noise;

• The chirp range is about 2.5 GHz. Compared to the actual useful chirp range of 1.25

GHz (19 -20.25 GHz), we left a sufficient margin;

• The phase noise at 1 MHz frequency offset is about -115 dBc/Hz, which is far lower than the phase noise of other K-band DCOs.

It is noteworthy that, to more easily cover the wide chirp range of about 2.5 GHz, we have incorporated a medium-tuning step into this design, with a value between the coarsetuning step and the fine-tuning step. The medium-tuning bank will be used in conjunction with the fine-tuning bank to generate the chirp signal. Along with the coarse-tuning bank, they form the prototype of the triple-bank DCO (T-DCO). The most significant advantage of this prototype is that a wide FTR and ultra-fine frequency resolution can be achieved simultaneously by using fewer capacitor tuning units.

Table II.5.1 DCO Specifications.

II.5.2.2. Selection of DCO Structures

Among the different structures of DCOs reported in recent years, LC resonator-based cross-coupled DCOs are preferable due to their low PN, low power consumption, simplicity, and robustness. As mentioned in Section I.3.2.3, since the electron mobility is much higher than that of holes, the NMOS-only structure can provide a higher transconductance compared to the PMOS-only structure, which implies a smaller size cross-coupled pair and less parasitic capacitance. The complementary structure offers low PN and low power consumption. However, introducing an extra transistor between the Figure II.5.1(c) shows the structure of a class-D cross-coupled oscillator, which eliminates the tail current source, thus avoiding its noise from entering the resonant tank through the cross-coupled pair. Moreover, this structure allows a much higher oscillation amplitude (~2•VDD) than the previous two structures, resulting in better phase noise performances. In addition, the differential transistors are used as switches, since the product of the drain voltage and the channel current of the switches is very close to zero during the whole oscillation period, all the power dissipation occurs in the LC tank, leading to excellent power efficiency. Based on these characteristics, this type of oscillator is known as the class-D oscillator. However, the current consumption of a class-D oscillator depends on the VDD and the losses of the LC tank, thus this approach generally features higher power consumption. Furthermore, it is highly sensitive to the supply voltage and therefore requires a high-performance regulator .

Consequently, we chose the class-B cross-coupled oscillator architecture shown in

II.5.2.3. K-Band LC Tank Design Considerations

As we know that the resonant frequency of the parallel LC tank is approximately 𝑓 = 1 (2𝜋√𝐿𝐶) ⁄ , where L and C are the total inductance and total capacitance, respectively.

Therefore, the relationship between the frequency-tuning step ∆𝑓 and the capacitancetuning step ∆𝐶 can be estimated as

∆𝑓 = -2𝜋 2 𝑓 3 𝐿∆𝐶 (II. 5. 1)
Therefore, for an oscillation frequency of 20 GHz and a typical inductance of 140 pH, a ∆𝐶 of only ~100 aF is required to achieve a fine frequency resolution of ~2.5 MHz, which is the first challenge of the K-band LC tank design, i.e., achieving a tiny capacitancetuning step. In addition, the FTR of a DCO can be expressed as

𝐹𝑇𝑅 = 2 (𝑓 𝑚𝑎𝑥 -𝑓 𝑚𝑖𝑛 ) (𝑓 𝑚𝑎𝑥 + 𝑓 𝑚𝑖𝑛 ) ⁄ = 2 √ 𝐶 𝑚𝑎𝑥 + 𝐶 𝑝 -√ 𝐶 𝑚𝑖𝑛 + 𝐶 𝑝 √ 𝐶 𝑚𝑎𝑥 + 𝐶 𝑝 + √ 𝐶 𝑚𝑖𝑛 + 𝐶 𝑝 (II. 5. 2)
where 𝑓 𝑚𝑎𝑥 and 𝑓 𝑚𝑖𝑛 are the maximum and minimum oscillation frequencies of the DCO, 𝐶 𝑚𝑎𝑥 and 𝐶 𝑚𝑖𝑛 are the maximum and minimum capacitances of LC tank, 𝐶 𝑝 represents the whole parasitic capacitance. For instance, to achieve an FTR of ~20 %, assuming an oscillation frequency of 18 -22 GHz (4 GHz bandwidth) and with a constant inductance of 140 pH, 𝐶 𝑚𝑎𝑥 and 𝐶 𝑚𝑖𝑛 can be estimated to be 560 fF and 375 fF, respectively, which means a capacitance ratio 𝐶 𝑚𝑎𝑥 𝐶 𝑚𝑖𝑛 ⁄ of ~1.5. Considering the contribution of 𝐶 𝑃 to the total capacitance, this ratio needs to be larger, which is the second challenge in the Kband LC tank design.

Note that inductance values for wide-FTR DCO designs generally do not exceed 200 pH since sufficient margin needs to be reserved for the total capacitance (>300 fF).

Meanwhile, according to the Equation (II. 5.1), if the inductance L increases, ∆𝐶 must be further reduced for the same ∆𝑓. which is often used in sub-10 GHz DCO designs, offers a much higher Q-factor (>100) than the inductor. Therefore, according to the Equation (I.3.4), the Q-factor of the final LC tank depends mainly on that of the inductor. -109 -However, for K-band DCO designs, this is no longer applicable because the Q-factor of the MOS varactor tends to be close to or slightly higher than that of the inductor.

Furthermore, the Q-factor of the MOS varactor is even lower in the FD-SOI process due to the presence of the buried oxide layer. For example, the simulated minimum capacitance step of the smallest size NMOS varactor is ~1.4 fF with a worst Q-factor (inversion mode) of ~20 at 20 GHz in the 22 nm FD-SOI process. Although the switchedcapacitor structure with a better Q-factor in Figure II.5.3(b) is proposed, it endures the trade-off between Q-factor and parasitic capacitances, which is the third challenge in the K-band LC tank design.

II.5.2.4. Low Phase Noise Considerations

Let us remind the well-known Leeson's formula in the Equation (I.3.24), which can also be applied to the PN analysis of LC-DCOs and is given in . One can conclude that the PN of DCOs can be boosted by increasing the dissipated power and improving the Q-factor of the LC tank.

More dissipated power implies a higher tail current, since, in the current-limited region, the output voltage swing is proportional to the tail current. Consequently, the conduction time of the transistors of the cross-coupled pair can be reduced accordingly, resulting in a minimization of cyclostationnary noise sources contribution to the overall PN. Furthermore, as the tail current still increases, the oscillator eventually enters the voltage-limited region, i.e., the amplitude no longer increases . Therefore, the best PN performances of the DCO can be obtained at the edge of the current-limited and voltage-limited regions.

As mentioned above, the inductor of the K-band DCO has a relatively constant Qfactor at 20 GHz, so the Q-factor of the LC tank is highly dependent on that of the capacitors. Since the Q-factor of the LC tank directly affects the PN and power consumption of the DCO, the switched-capacitor structure needs to be optimized in order to achieve the best Q-factor with acceptable parasitic capacitances. Meanwhile, the backgate bias provided by the 22nm FD-SOI process will be used in the design of the MOS switch to further improve its Q-factor, and this point will be discussed in detail in the following Section.

In addition, unlike the conventional VCOs, the DCOs exhibit a quantization noise introduced by its finite frequency resolution ∆𝑓 𝑟𝑒𝑠 , whose contribution to phase noise is given by

𝐿{∆𝑓} = 1 12𝑓 𝑅 • ( ∆𝑓 𝑟𝑒𝑠 ∆𝑓 ) 2 • 𝑠𝑖𝑛𝑐 ( ∆𝑓 𝑓 𝑅 ) 2 (II. 5. 3)
where 𝑓 𝑅 and ∆𝑓 are the reference frequency and the offset frequency, respectively.

Therefore, in order to reach an ultra-fine frequency resolution (several kHz) or a fractional input, two additional fine-tuning units are connected to a digital high-speed ΣΔ modulator The current mirror (N3,4) is well biased in the saturation region to provide a stable tail current and drive the output voltage swing. Moreover, two additional large tail capacitors (CT1 and CT2) connected in parallel with the tail current source act as a filter, providing a path for the high-order harmonics at the common source node T and filtering out the thermal noise from the tail current mirror. Moreover, the analysis of MOS switches needs to consider the operation region of MOS transistors, whose parasitic capacitances are different under different operation regions. The 22FDX technical paper does not disclose some relevant theoretical basis.

N 1 N 2 T Decoder N 4 N 3 C T2 C T1 (b) EN C C 1 C 1 N 5 N 6 N 7 EN M N 8 N 9 EN F VDD N 10 N 11 (c) (d) (a)
However, considering that the parasitic capacitance distribution in a planar FD-SOI process is similar to that of a conventional bulk CMOS process, we will use the latter for our analysis. Taking Figure II.5.6(a) as an example, we will mainly analyze the relationship between Cgs, Cgd, and Cgb. Cds is regarded as a process-related independent capacitance, which is less affected by the gate voltage and will not be discussed.

The parasitic capacitances of MOS transistors for different operation regions are given in Table II.5.3. When the MOS transistor is in the cutoff region, i.e., Vgs < Vth, Cgs is the same as Cgd and is about CoxLDW, where Cox is the oxide's dielectric constant, LD is the gate-drain/source overlap length, W is the width of the channel. In addition, Cgb is approximately CoxLW, which can be seen as proportional to the effective length L and width of the channel. When the MOS transistor is in the linear triode region (Vgs > Vth,

(a) (b) Component Rgate Cwiregd, Cwiregs Cwireds Ractive Rsti Rwire Rsub Dwsub Label Rg A, B, C, F G Y P T, U, V, W Z, S K, L (c)
Vds < Vgs -Vth), the capacitance value Cgb is assigned symmetrically to the source and drain. When the MOS transistor is in the saturation region (Vgs > Vth, Vds ≥ Vgs -Vth), most of Cgb is added to Cgs, and Cgd becomes CoxLDW again [II-57].

Table II.5.3 Parasitic capacitances of MOS transistors.

II.5.3.3. 5-Bit Coarse-Tuning Bank

The 5-bit (CB[4:0]) coarse-tuning bank employs a 5-31 binary-to-thermometer decoder to control 31 coarse-tuning units to compensate for PVT variations. As shown in Figure II.5.8, we take a more concise 3-7 binary-to-thermometer decoder as an example to explain its decoding and control mechanism. This decoder consists of 3 inputs (B0 -B2) and 7 outputs (T0 -T6), where the input value and the corresponding output value are identical in decimal representation, so that a large number of outputs can be represented with a small number of inputs. In addition, the thermometer code provides a more efficient representation of numbers, as can be seen from the truth table, where the number of '1' is incremented, meaning that it allows to monotonically turn the coarsetuning units on or off. Since the switches operate in the cutoff region, hence, Cgd = Cgs. Therefore, the total differential parasitic capacitance of these switches, Cpar, highlighted by the red dashed box, can be expressed as:

𝐶 𝑝𝑎𝑟 = 3 2 • 𝐶 𝑑𝑠 + 𝐶 𝑔𝑑 (II. 5. 4)
The total differential capacitance in the OFF-state, COFF_CB, which consists of two capacitances C1 in series with Cpar, can be estimated as follows:

𝐶 𝑂𝐹𝐹_𝐶𝐵 ≈ 𝐶 1 × 𝐶 𝑝𝑎𝑟 𝐶 1 + 2𝐶 𝑝𝑎𝑟 = 1 2 • 𝐶 1 × (3𝐶 𝑑𝑠 + 2𝐶 𝑔𝑑 ) 𝐶 1 + (3𝐶 𝑑𝑠 + 2𝐶 𝑔𝑑 ) (II. 5. 5)
Moreover, the equivalent schematic in the ON-state is shown in Figure II.5.9(b). Since the switches operate in the triode region, they can be equated as resistors. More

C gd C 1 C 1 C ds C gd C gs C gd C ds C ds C 1 C 1 EN C = 0V (a) EN C = 0.8V C gd C ds C gd C gs C ds C gd R on R on R on C ds (b) VP VN VP VN
specifically, RON can be used to represent the ON-state resistance between the drain and source of each switch. Considering that RON ≈ 0 Ω, then the parasitic capacitances are shorted, and the expression for the ON-state capacitance, CON_CB, can be formulated as follow:

𝐶 𝑂𝑁_𝐶𝐵 ≈ 1 2 • 𝐶 1 (II. 5. 6)
Therefore, the coarse capacitance step ΔCCB representing the difference between the ONstate capacitance CON_CB and the OFF-state capacitance COFF_CB is given by:

∆𝐶 𝐶𝐵 = 𝐶 1 2 - 𝐶 1 × 𝐶 𝑝𝑎𝑟 𝐶 1 + 2𝐶 𝑝𝑎𝑟 = 𝐶 1 2 2(𝐶 1 + 2𝐶 𝑝𝑎𝑟 ) = 1 2 • 𝐶 1 2 𝐶 1 + 3𝐶 𝑑𝑠 + 2𝐶 𝑔𝑑 (II. 5. 7)
Since C1 ≫ Cpar, a large capacitance step ΔCCB can be obtained. In addition, the ON-state parasitic resistance (RON) significantly degrades the Q-factor of the coarse-tuning unit

(𝑄 = 1 2𝜋𝑓𝑅 𝑠 𝐶 𝑠 ⁄
, CS is the equivalent series capacitance, RS is the equivalent series resistance, and RS ∝ RON). Thus, to reduce RON, a higher W/L ratio of MOS switches is required at the cost of larger OFF-state capacitance. -117 -voltage of 0.8 V is finally chosen as the forward back-gate voltage. In addition, the prelayout simulation results show that the coarse-tuning unit achieves a capacitance ratio CON_CB/COFF_CB of 7.97 fF/2.97 fF and a Q-factor ratio QON_CB/QOFF_CB of 54.2/84.7. Thus, the 5-bit coarse-tuning bank allows to cover a frequency range of 18.45 -21.12 GHz (post-layout simulations), leading to an average coarse frequency resolution of 86 MHz. Here, it is used for the first time in a frequency-tuning unit of a DCO. Meanwhile, we note that the back-gate structure was also applied to the frequency regulation of a VCO, and its role is equivalent to that of a varactor . To be precise, the functions of the back-gate structure are similar in both the VCO and the DCO.

II

The cross-section view is illustrated in Figure II.5.12. The substrate ring of N10,11

isolates the back-gate deep-N well to make this structure more stable. Another advantage is that the back gate allows a higher breakdown voltage (i.e., up to 2 V in a 22 nm FD-SOI process) compared to the front gate. As shown in Figure II.5.13,varying the ENF from 0 V to 1.2 V allows a small capacitance step of about 63 aF. Meanwhile, since the total capacitance of the fine-tuning bank is much smaller than that of the coarse-and the voltage-limited region mentioned in Section II.5.2.4. Note that 20 mA is not the maximum current value that this current mirror structure can offer, and a current margin of ~5 mA is reserved for flexible compensation of PVT variations.

II.5.4.2. FMCW Chirp with Frequency Overlap

It is worth noting that the T-DCO combines both the medium-tuning bank and the fine-tuning bank to produce a wide FTR and high-resolution FMCW chirp, which requires the medium frequency resolution (∆fMB) to be smaller than the fine-tuning range (BWFB) to avoid frequency modulation gaps.

II.5.5. Post-Layout Simulation Results

The

II.5.6. Comparative Study

Table II.5.5 T-DCO performances vs DCO specifications.

Table II.5.5 compares the performances of the T-DCO with the specifications. It can be seen that the current consumption of the T-DCO is much less than the 60 mA in the specifications, while T-DCO also has a very wide frequency-tuning range. The chirp range, which relies on the medium and fine-tuning banks, does not reach 2.5 GHz, but is still well above the theoretical 1.25 GHz, and the coarse-and fine-tuning steps are both better than the specifications. Unfortunately, we have taken various measures to improve the phase noise performances, but there is still about 2 dB difference from the requirement of -115 dBc/Hz at 1 MHz frequency offset. In general, the proposed T-DCO basically meets the required specifications.

Moreover, to quantify the overall performances of oscillators, the widely used figure- where PDC is the dissipated power, f is the carrier frequency and ∆f is the offset frequency.

Moreover, the performances of the proposed T-DCO compared with the state-of-the-art are presented in Table II.5.6. It can be noted that the proposed T-DCO achieve the bestin-class PN with a competitive power consumption while also featuring a comparable FTR, FoM, and FoMT.

II.6. Conclusion

In Section II.1, we focused on introducing the 22FDX technology, including its advantages and the supported libraries and components.

In Section II.2, we first introduced the challenges faced by conventional VCO designs in nanoscale CMOS processes, which is also the reason for the emergence of DCOs. We

C C 1 C 1 N 5 N 6 N 7 EN F N 8 N 9 C 2 C 2
However, when the back-gate voltage is increased from 0 V to 2 V, the Q-factor ratio can be boosted significantly from 34.7/92.2 to 42.6/101.8 due to the reduction of the equivalent series resistance.

III.2.1.3. 10-Bit Fine-Tuning Bank

As shown in Figure III.2.1(d), the structure of the fine-tuning unit is similar to that of the medium-tuning unit of the T-DCO; however, there are two differences between them.

The first difference is that the common source terminal of N8 and N9 is connected to the control terminal ENF through an inverter, and the other is that the capacitance value C2 of 1.33 fF is achieved by connecting in series the two smallest tri-metallic APMOM capacitors (1 μm/1 μm, 2.66 fF) provided by the design kit. These are three main reasons for choosing such a small capacitance value: (1) it allows a higher frequency resolution;

(2) there are 961 such fine-tuning units in the fine-tuning bank, and too large a capacitance The truth table of this digital control block is given in Table III

C 2 C 2 Y R(j)
1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0

0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 Column Codes Row Codes (a) (b) (c) R(j) 0 0 0 0 1 1 1 1 C(i) 0 0 1 1 0 0 1 1 C(i+1) 0 1 0 1 0 1 0 1 Y 0 1 0 1 0 1 1 1
-144 -start-up condition, i.e., 𝑔 𝑚 𝑅 𝑃 ≥ 2, the cross-coupled pair's transconductance value gm needs to be higher than 15 mS.

Figure III.2.6

Real part of the impedance versus the resonant frequency of the LC tank. The output voltage ranges from 0.68 V to 1.72 V. In addition, VT is the waveform of the signal at the common mode point T, and the frequency of this signal is 2f0. Furthermore, this signal can be mixed to the oscillator output frequency by the cross-coupled pair, thereby degrading its phase noise. Therefore, in order to filter out this second-order harmonic, a large capacitor CT2 is inserted at node T, resulting in a small voltage swing (almost a constant voltage) of VT.

III.2.2. Pre-Layout Simulation Results

III.2.2.1. Frequency-Code Characteristic Curves

III.2.2.2. PN Performances

Considering the trade-off between the power consumption and the phase noise, the tail current is set to 12 mA, so the D-DCO.1 consumes 14. -147 -reduction of the Q-factor as the tuning units are turned on. Meanwhile, we notice a significant PN degradation close to the carrier frequency (at 10 kHz frequency offset).

Fortunately, this kind of noise close to the carrier will be filtered by the ADPLL loop.

Moreover, the worst PN occurs at the maximum frequency (CB = 0, FB = 0) of 22.37

GHz, where the PN decreases by 8.6 dB and 1.6 dB at 10 kHz and 1 MHz frequency offsets, respectively, compared to the PN at medium frequency. The main reason is the significant increase in carrier frequency.

Figure III.2.10

III.2.2.3. PVT Variations

When CB = 8, FB = 481, the supply voltage is 1.2 V and the temperature is 27°, the effects of different process corners on the oscillation frequency and the phase noise are given in Figure III.2.13. The selected process corners are fast-fast (ff), typical-typical (tt), and slow-slow (ss). Compared to the tt corner, the ff and ss corners result in a frequency deviation of about 2 GHz. Fortunately, the different process corners have no significant effect on the phase noise except for the low frequency offset. Meanwhile, the phase noise performances degrade severely at high temperatures, which needs to be compensated from the system design level and is not the focus of our studies.

III.2.3. Problems in Post-Layout Simulations

The pre-layout simulation results of the D-DCO.1 are encouraging; however, it can be inferred that the 10-bit fine-tuning bank inevitably occupies a large area and introduces large interconnect parasitic capacitances. The question remains, how large are the parasitic capacitances and do the post-layout simulation results of the D-DCO.1 still meet the design requirements ? These are the key points that will be discussed in this subsection. this inductor is about one-300th of that of the fine-tuning bank. There is no doubt that this layout is unacceptable.

Therefore, the first thing that should be done is to reduce the layout area. Since the digital control blocks occupy a large portion of the total area, there are two intuitive ways to reduce the total area. One is to fuse the transistors in the digital control block, i.e., to remove the substrate ring of the transistors or even to change the finger structure, but this way of using non-standard components requires various technical support. In contrast, the other way is more attractive, which is to move all digital control blocks out of the oscillator so that they can be implemented through digital circuits. In order to evaluate the parasitic capacitances, the post-layout simulation results of the fine-tuning unit and the fine-tuning bank are given in Table III In addition, based on these data, the interconnect parasitic capacitance Cwire in the fine-tuning bank can be calculated. Since the capacitance of a single fine-tuning unit in the ON-state is 762 aF, if Cwire is ignored, the total capacitance of 961 such fine-tuning units would be 732.3 fF (762 aF × 961). Nevertheless, the simulated total capacitance of the fine-tuning bank with 961 fine-tuning units in the ON-state is 1.37 pF, meaning that Cwire is 1.37 pF -732.3 fF = 637.7 fF. Indeed, an approximate Cwire value can be obtained by using the capacitance in the OFF-state. Therefore, it can be concluded that the Cwire value in this fine-tuning bank is about half of the total capacitance value. Moreover, one can be vaguely aware that the interconnect parasitic capacitance Cwire is proportional to the layout area, which is also in line with common sense since a larger layout area often implies more complex internal connections.

III.2.4. Summary

In this Section, we described in detail the circuit implementation and the problems faced by designing the D-DCO.1. The pre-layout simulation results of D-DCO.1 are fully compliant with the design specifications; however, the post-layout simulation results are not satisfactory, mainly due to the large layout area of the fine-tuning bank, which leads to large interconnect parasitic capacitances. Although some measures were taken to optimize the layout, they were still insufficient. Therefore, some other unique methods are still required to further reduce the layout area of the 10-bit fine-tuning bank. In addition, other modules in D-DCO.1, such as the coarse-tuning bank and the crosscoupled pair, also need to be further optimized in order to reduce their own parasitic capacitances and to compensate for the performance degradations that may be caused by these parasitic capacitances. Based on these points, we propose a second version of D-DCO, named D-DCO.2, in the following Section.

III.3. Second Version of D-DCO (D-DCO.2)

In this section, we will highlight some of the crucial parameters and performances of output voltage swing of the DCO is typically required to be 1.8 V or higher. Thus, the transistors with a channel length of 100 nm can better compensate for the lifetime degradation caused by the HCI (hot-carrier injection) effect.

• The width-to-length ratio (W/L) of the current mirror (N12 and N13) is doubled.

Although this leads to a larger layout area, the flatness of the drain-source current in its saturation region is further improved as the channel length modulation effect is suppressed, thereby providing a more stable tail current.

• The channel length of the MOS switches (N14-16, N17,18) in the coarse-and fine-tuning units is reduced from 70 nm to 20 nm. This initiative can further reduce the layout area, especially for the fine-tuning bank. Moreover, the performances of the switches can be improved because the parasitic resistance of the switches is inversely proportional to their channel lengths. However, this requires a digital control voltage of 0.8 V as the thin-oxide devices have a nominal voltage of 0.8 V.

Moreover, the coarse-tuning unit is shown in

III.3.2. Pre-Layout Simulation Results

Table III.3.2 gives the DC operating points of the cross-coupled pair (N10,11) and the current mirror (N12,13) in the D-DCO.2. The transconductance provided by the single-side transistors of the cross-coupled pair has increased to 38.34 mS. Moreover, the tail current is around 19.93 mA, which is quite close to the ideal current of 20 mA, meaning that the current mirror operates well in the saturation region. Table III.3.3 indicates that in the worst case and the best case, the medium frequency variation of the D-DCO.2 does not exceed 1.1 GHz due to its large total capacitance, which is significantly smaller than that of the T-DCO. The coarse-tuning range of 1.99

GHz available from the D-DCO.2 can fully accommodate PVT variations. In addition, the FTR also remains similarly around 20%. In the worst case, the PN varies by no more than 4 dB and still reaches -109.13 dBc/Hz at 1 MHz frequency offset.

III.4. Conclusion

In Section III.1, we briefly described the main objectives of designing a K-band D-DCO to address the frequency overlap and calibration issues in multi-bank DCOs, and also introduced the main challenges of D-DCO design. In Section III.2, we presented the initial version of the D-DCO using standard components from the process library.

General Conclusion

The 76 -81 GHz FMCW automotive radar has gained significant attention due to its importance in the development of ADAS and autonomous driving technologies. The 76 -81 GHz frequency band provides a good balance between range, resolution, and sensitivity, making it highly desirable for automotive applications. Meanwhile, FMCW technology enables accurate and reliable real-time object detection and distance measurement. Furthermore, the automotive industry's demand for advanced safety features, as well as the increasing popularity of electric and hybrid vehicles, further promote the widespread adoption of automotive radars.

As a critical component of FMCW radar systems, the PLL is used to generate a stable oscillation frequency, which is then used to generate the modulation frequency of the radar. Compared with traditional analog PLLs, ADPLLs offer several advantages, including the ability to be integrated with digital systems, lower power consumption, and ease scalability to advanced CMOS technologies. In addition, ADPLLs can be easily programmed and reconfigured to adapt to variations in operating conditions. This makes ADPLLs more robust and reliable, particularly in harsh environments, which is critical for safety-critical applications such as automobiles. Therefore, ADPLLs have become an increasingly popular choice in modern frequency synthesis systems.

The implementation of a DCO is a necessary step in the design of ADPLLs. Some critical issues in DCO design have been largely solved in the field of wireless communications below 10 GHz. However, the possibility of obtaining a K-band DCO with a high spectral purity applicable to FMCW automotive radar remains to be proven.

Therefore, the main goal of this thesis was to implement a wideband low-phase-noise Kband DCO in an advanced 22 nm FD-SOI process. To achieve this goal, we first studied some classical oscillator theories to understand the strengths and weaknesses of each Mots clés : Oscillateurs à commande numérique, OCN, bande K, faible bruit de phase,

I

  would also like to acknowledge Mr. Yann Deval, Professor at the University of Bordeaux; Mr. Philippe Ferrari, Professor at the University of Grenoble Alpes; Mr. Philippe Descamps, Professor at the Ecole Nationale Supérieure d'Ingénieurs de Caen (ENSICAEN); Mr. Bruno Barelaud, Professor at the University of Limoges; Mr. Florin Hutu, Maître de Conférences at the Institut National des Sciences Appliquées de Lyon (INSA Lyon); Mr. Francis Huin, Engineer at the IDDO-IC; whom I am very honored to have as the committee members for my oral defense. I am equally grateful to them for their examinations of my dissertation and for all their valuable comments and suggestions.

Figure I. 1 . 1 Figure II. 4 . 1 Figure II. 4 . 4

 114144 Figure I.1.1 Simplified block diagram of a radar system. ........................................... --Figure I.1.2 Atmospheric absorption at altitudes of sea level and 4 km. .................... --Figure I.1.3 Radar configurations. (a) Monostatic. (b) Bistatic. ................................. --Figure I.1.4 Range measurement principle of the pulsed radar. .................................. --Figure I.1.5 LFM methods. (a) Linear triangular frequency modulation. (b) Linear sawtooth frequency modulation. (c) Segmented linear frequency modulation. ......... --Figure I.1.6 Block diagram of a PLL-based transmitter. ........................................... --Figure I.1.7 Block diagram of a typical superheterodyne receiver. .......................... --Figure I.1.8 Impact of the image frequency on the spectrum of the useful signal. ... --Figure I.1.9 Five levels of autonomy......................................................................... --Figure I.1.10 Typical types of sensors used in ADAS. ............................................. --Figure I.1.11 Early automotive radar systems. (a) 10 GHz radar in the early 1970s. (b) 16 GHz radar in 1975. (c) 35 GHz radar in 1974. ...................................................... --Figure I.1.12 Frequency bands for automotive radars. .............................................. --Figure I.1.13 Comparison of fT / fmax collected from published papers. (a) SiGe BiCMOS. (b) CMOS-Bulk/SOI/FinFET. .................................................................................... --Figure I.1.14 Schematic of the fully integrated 77 GHz FMCW radar transceiver in 65 nm CMOS technology. ............................................................................................... --Figure I.1.15 Schematic of the 77 GHz frequency doubling two-path phased-array FMCW transceiver for automotive radar.................................................................... --Figure I.1.16 Schematic of the CMOS 76 -81 GHz 2-TX 3-RX FMCW radar transceiver based on mixed-mode PLL chirp generator. .............................................................. --Figure I.1.17 Schematic of the Bosch's LRR3 system. ............................................. --Figure I.1.18 Schematic of the Denso's LRR system. .............................................. --Figure I.1.19 Schematic of the Bosch's 76 -81 GHz automotive radar. .................. --Figure I.2.1 Simplified block diagram of a DDFS. ................................................... --Figure I.2.2 Simplified block diagram of a typical CPPLL. ..................................... --Figure I.2.3 Linear s-domain model of a typical analog PLL. .................................. --Figure I.2.4 Step response of the underdamped system. (a) Input step signal. (b) Step response with different damping factors. ................................................................... --Figure I.2.5 Block diagrams of (a) integer-N PLL with a pulse swallow frequency divider

1. 1

 1 Standard radar-frequency letter band nomenclature. ................................ --Table I.1.2 Comparison of sensors in ADAS. ........................................................... --Table I.1.3 Automotive radar characteristics in 76 -81 GHz frequency band. ........ --Table I.1.4 Cutoff frequencies for various semiconductor technologies. .................. --Table I.1.5 Performance summary of 76 -81 GHz automotive radars ..................... --Table II.1.1 Supported EDA Tool Versions. ............................................................. --Table II.1.2 Summary of different devices in the PDK. ............................................ --Table II.3.1 Performances summary of LC-based DCOs. ........................................ --Table II.5.1 DCO Specifications. ............................................................................ --Table II.5.2 Main parameters of the proposed T-DCO. .......................................... --Table II.5.3 Parasitic capacitances of MOS transistors. .......................................... --Table II.5.4 Post-layout simulated T-DCO performances for the three most representative PVT configurations ........................................................................... --Table II.5.5 T-DCO performances vs DCO specifications. .................................... --Table II.5.6 Comparison with state-of-the-art K-band DCOs ................................. --Table III.2.1 Main parameters of the proposed D-DCO.1 ...................................... --Table III.2.2 Truth table of the digital control block. ............................................. --Table III.2.3 DC operating points of the transistors N1-4. ....................................... --Table III.2.4 D-DCO.1 performances vs DCO specifications ................................ --Table III.2.5 Post-layout simulation results with RC extraction of the new fine-tuning unit and the new 10-bit fine-tuning bank with 31 × 31 fine-tuning units. ................ --Table III.2.6 Post-layout simulation results of the new resized fine-tuning bank. . --Table III.3.1 Main parameters of the proposed D-DCO.2 ...................................... --Table III.3.2 DC operating points of the transistors N10-13. .................................... --Table III.3.3 Post-layout simulated D-DCO.2 performances for the three most representative PVT configurations. .......................................................................... --Table III.3.4 D-DCO.2 performances vs DCO specifications. ............................... --Table III.3.5 Comparison with the state-of-the-art K-band DCOs. ........................

Figure I. 1 . 1

 11 Figure I.1.1 Simplified block diagram of a radar system.

Figure I. 1 . 2

 12 Figure I.1.2 Atmospheric absorption at altitudes of sea level and 4 km.

  and multi-static (including bistatic) as shown in Figure I.1.3. A traditional radar in which the transmitting and receiving antennas are located in the same place is referred to as a monostatic radar, regardless of whether single or two antennas are used. A multi-static radar system contains two or more transmitting or receiving antennas, which are all far apart compared to the size of the antennas [I-5].

Figure I. 1 . 3

 13 Figure I.1.3 Radar configurations. (a) Monostatic. (b) Bistatic.

4 ( 4 . 4

 444 Figure I.1.4 Range measurement principle of the pulsed radar.

Figure I. 1 . 5

 15 Figure I.1.5 LFM methods. (a) Linear triangular frequency modulation. (b) Linear sawtooth frequency modulation. (c) Segmented linear frequency modulation.

  Figure I.1.6 Block diagram of a PLL-based transmitter.

7

 7 Figure I.1.7 Block diagram of a typical superheterodyne receiver.

Figure I. 1 . 8

 18 Figure I.1.8 Impact of the image frequency on the spectrum of the useful signal.

  death among people aged 15 -29 years[I-18],[I-19]. These numbers are expected to decrease significantly in the near future with the widespread deployment of autonomous driving technology, which will also bring tremendous social and economic benefits. the Society of Automotive Engineers (SAE) J3016 TM standard laid out six levels of autonomy for on-road motor vehicles as shown in Figure I.1.9 [I-20]. These levels span from no automation, partially automation to fully automation. As the level of autonomy increases, the vehicle will take over more of the operations of the driver.

Figure I. 1 . 9

 19 Figure I.1.9 Five levels of autonomy.

Figure I. 1 . 10

 110 Figure I.1.10 Typical types of sensors used in ADAS.

  , lane keep assistance (LKA), traffic sign recognition (TSR), blind spot detection (BSD), adaptive light control (ALC), etc. The realization of these functions is highly dependent on the sensors employed. Figure I.1.10 illustrates an ADAS platform with multiple sensors and functions integrated [I-9].

  Automotive radar was first proposed around the 1960s [I-22]-[I-27]. Some early automotive radar systems are shown in Figure I.1.11, their implementations are mainly based on existing two-terminal diode devices, such as GUNN and Schottky diodes, which suffered from low operating frequencies and large volumes.

Figure

  Figure I.1.11 Early automotive radar systems. (a) 10 GHz radar in the early 1970s. (b) 16 GHz radar in 1975. (c) 35 GHz radar in 1974.

Figure I. 1 . 12

 112 Figure I.1.12 Frequency bands for automotive radars.

Figure I. 1 .

 1 Figure I.1.13 Comparison of fT / fmax collected from published papers. (a) SiGe BiCMOS. (b) CMOS-Bulk/SOI/FinFET.

Figure I. 1 .

 1 Figure I.1.15 Schematic of the 77 GHz frequency doubling two-path phased-array FMCW transceiver for automotive radar.

Figure I. 1 .

 1 Figure I.1.16 Schematic of the CMOS 76 -81 GHz 2-TX 3-RX FMCW radar transceiver based on mixed-mode PLL chirp generator.

The 19

 19 GHz dielectric resonant oscillator (DRO) is used as a reference oscillator, mixed with the divided-by-4 RF frequency (77 GHz) to generate an IF signal, which serves as an input to the PLL of the Radar-ASIC. The modulation control and the signal preprocessing (pre-amplification, A/D conversion, filtering) are integrated in the Radar-ASIC. The SiGe-MMIC is mounted on a multi-layer PCB and bonded to the RF substrate on the top of the PCB, and the patch antenna is also placed on the RF substrate. In addition, the radar has four receiver channels, two of which are used as transmit/receive channels simultaneously. The total power consumption of this radar transceiver is about 4 W from a 5.5 V supply voltage and allows operating temperature from -40 °C to +125 °C.

Figure

  Figure I.1.17 Schematic of the Bosch's LRR3 system.

Figure I. 1 .

 1 Figure I.1.18 Schematic of the Denso's LRR system.

Figure I. 1 .

 1 Figure I.1.19 Schematic of the Bosch's 76 -81 GHz automotive radar.

Figure I. 2 . 1

 21 Figure I.2.1 Simplified block diagram of a DDFS.

  as frequency shift keying (FSK) and frequency hopping.

  to generate one or more output signals synchronized to the input reference signal [I-62]. The current mainstream RF synthesizers are still based on the analog charge-pump PLL (CPPLL) structure. As depicted in Figure I.2.2, a typical CPPLL consists of the following modules: phase-frequency detector (PFD), charge pump, loop filter, voltagecontrolled oscillator (VCO) and frequency divider.

Figure I. 2 . 2

 22 Figure I.2.2 Simplified block diagram of a typical CPPLL.

  Figure I.2.3 gives a linear s-domain (Laplace transform) model of a typical analog PLL. The PFD can be represented by (𝜙 𝑖 -𝜙 𝑑 ) • 𝐾 𝑃𝐹𝐷 , where (ϕi -ϕd) is the input-output phase difference, and KPFD is the gain of the PFD and the charge pump. F(s) is the transfer function of the loop filter. The VCO can be characterized by an integrator with a gain of KVCO (since frequency of phase with respect to time) and its transfer function can be expressed as KVCO/s. The input-output phase relationship of the frequency divider is ϕd = ϕo / N.

  decaying with a time constant (𝜉𝜔 𝑛 ) -1 . As shown in Figure I.2.4, the exponential decay term determines the settling speed of the PLL, and the damping factor should generally be set to about 0.7. Meanwhile, considering the relationship 𝜉𝜔 𝑛 = 𝜔 𝐿𝑃𝐹 2 ⁄ , there is a critical trade-off between the settling speed and the VCO input interference. The lower the 𝜔 𝐿𝑃𝐹 , the better the suppression of the high-frequency disturbance generated by the PFD, but the smaller damping factor and the slower the settling speed.

Figure I. 2 . 4

 24 Figure I.2.4 Step response of the underdamped system. (a) Input step signal. (b) Step response with different damping factors.

Figure I. 2 . 5

 25 Figure I.2.5 Block diagrams of (a) integer-N PLL with a pulse swallow frequency divider and (b) fractional-N PLL with an SDM.

  adopts a pulse swallow structure as shown in FigureI.2.5(a), which provides a very large programmable frequency division ratio in a simpler structure with low power consumption and is therefore well suited for the RF integer-N PLL.As shown in Figure I.2.5(b), the fractional-N PLL permits an output frequency resolution ∆FOUT equal to a fraction of the reference frequency, allowing a higher reference frequency far greater than the desired channel spacing. Therefore, a very low N value and fine frequency resolution can be effectively achieved, resulting in a significant reduction in both in-band phase noise and settling time, and an important improvement in loop dynamics. For example, a fractional-N division ratio of 10.1 can be obtained by dividing the output frequency FOUT by 10 in 9 cycles and by 11 in 1 cycle. Moreover, this

  structure or the Bang-Bang PFD structure. The latter two allow the detection of the phase along with the frequency in order to avoid the system locking on the second harmonic of the output signal.As illustrated inFigure I.2.7, another common structure of the ADPLL is based on the loop counter [I-66]. The frequency control word (FCW) is actually the dividing ratio of the ADPLL, and the reference phase can be obtained by accumulating FCW. The variable phase is partitioned into an integer part and a fractional part. The integer part is captured by counting the rising edge of the DCO output frequency FOUT. The fractional part is estimated by TDC measuring the time difference between the adjacent rising edges of FREF and FOUT. The difference between the reference phase and the variable phase represents the actual quantization error ε(k) between FREF and FOUT. This error is then filtered by the digital LPF and converted into the digital control signal that varies the DCO frequency. When the ADPLL is locked, the output frequency FOUT is identical to the reference frequency FREF times FCW.

Figure I. 2 . 7

 27 Figure I.2.7 Simplified block diagram of an ADPLL based on loop counter.

  Figure I.2.8, the reference frequency FREF and the output frequency FOUT in ADPLL are unsynchronized F if these two clocks are compared directly to extract the phase difference, it will inevitably cause sub-stability problems. Therefore, a D flip-flop can be introduced to retime the clocks. The principle is to use the FREF as the input to the D flip-flop, the FOUT as the control clock, and then the output clock CKR can serve as the system clock.

Figure

  Figure I.2.8 D flip-flop used for system clock retiming.

Figure

  Figure I.2.9 Classical diagram of the TDC based on an inverter chain.

Figure

  Figure I.2.9 illustrates a classical diagram of the TDC. This TDC is implemented by an inverter chain consisting of basic delay units with a time delay τ, and the D flip-flops sample the output state of each delay unit at the rising edge of the FREF clock to determine the mentioned time deviation ∆𝑡 𝑑 . The accuracy of such a TDC is the time delay τ of a single delay unit, and a larger dynamic range can be obtained by increasing the number

  preserving the low-frequency digital control signal. As illustrated Figure I.2.10, a typical digital loop filter generally adopts a proportional-integral (PI) structure, which consists in a proportional circuit with a gain of KP and an integral circuit with a gain of KI. The choice of KP and KI is crucial for the phase margin and stability of the ADPLL loop [I-68]. Its z-domain transfer function is given by 𝐻(𝑧) = 𝐾 𝑃 + 𝐾 𝐼 1 1 -𝑧 -1 (I. 2. 10) Compared with analog RC filters with large capacitors and resistors, digital loop filters can dramatically reduce chip area and power consumption. Moreover, digital loop filters allow dynamic configuration of their type, loop bandwidth (adaptive filtering), etc., which facilitates fast locking and improved loop dynamic performances.

Figure I. 2 .

 2 Figure I.2.10 Discrete z-domain transfer function of the PI loop filter.

Figure I. 2 .

 2 Figure I.2.11 Schematic of the TI's ADPLL-based transmitter system.

Figure I. 2 .

 2 Figure I.2.12 Schematic of the 60 GHz ADPLL-based FMCW transmitter system.

Figure I. 2 .

 2 Figure I.2.13 Schematic of the divider-based ADPLL.

  Figure I.3.1, the input and output of this system are X(jω) and Y(jω), respectively, and the open-loop transfer function is G(jω)F(jω), then its closed-loop transfer function H(jω) can be expressed as

Figure I. 3 . 1

 31 Figure I.3.1 Linear positive feedback system for oscillators.

Figure I. 3 . 3

 33 Figure I.3.3 Negative resistance compensation system for oscillators.

  Figure I.3.4. To satisfy the Barkhausen criterion, it consists of an odd number of inverters connected in series, where

  transistor. The LC resonant tank features a purely resistive characteristic at the resonant frequency, i.e., the phase difference is 0. The signals at the source and drain of the MOS transistor also have the same phase. According to the Barkhausen criterion, if the drain signal is fed directly back to the source, then the positive feedback required by the oscillator is obtained.As shown in FigureI.3.5 (a), the MOS transistor M1 as an active device is used to amplify the output signal of the feedback, and the LC resonant tank (LP and C1) performs frequency selection. Another role of the employed capacitor (C1) is to avoid coupling that affects the bias point of M1. Remarkably, this circuit introduces the source impedance -52 -1/gm of M1 into the resonant circuit, resulting in its inability to oscillate due to insufficient loop gain. An effective solution is to transform the source impedance to a very high level.

Figure I. 3

 3 Figure I.3.5 (a) Single MOS transistor with feedback applied from drain to source. (b) Colpitts oscillator. (c) Equivalent small-signal model of the Colpitts oscillator.

Figure I. 3

 3 Figure I.3.6 (a) Simplified schematic of a differential cross-coupled oscillator. (b) Small-signal model of the cross-coupled pair.

  substrate effects and channel modulation effects, the small-signal model of the cross-coupled pair can be simplified as shown in FigureI.3.6 (b). Therefore, the input voltage VIN can be expressed as 𝑉 𝐼𝑁 = 𝑉 𝐺𝑆1 -𝑉 𝐺𝑆2(I. 3. 12)

Figure I. 3 . 7

 37 Figure I.3.7 Cross-coupled oscillators with a tail/top current source. (a) NMOS-only structure. (b) PMOS-only structure. (c) Complementary structure.

̅̅̅̅

  Due to thermal excitation, random displacement of the charge carriers forms a varying current, thereby causing a random voltage across the resistive element, which is the origin of thermal noise. Thus, thermal noise exists in the vast majority of electronic devices at temperatures above absolute zero, for example, non-ideal capacitors and inductors can also generate thermal noise due to the presence of series resistance. The thermal noise of a resistor can be modeled by a series noise voltage source 𝑉 𝑛 2

  Figure I.3.8 (b). The actual output waveform can thus be represented as -59 -𝑉 𝑂𝑈𝑇 (𝑡) = 𝐴(𝑡) 𝑐𝑜𝑠(𝜔 0 𝑡 + 𝜙(𝑡))(I. 3. 22)

Figure I. 3

 3 Figure I.3.8 (a) Ideal power spectral density of oscillators. (b) Actual power spectral density of oscillators.

  mechanisms of phase noise and to develop mathematical models to predict the phase noise performances of oscillators [I-74]-[I-79]. Here, we will focus on the following two typical phase noise models: linear time-invariant model and linear time-variant model. Ideal 𝜔 [rad/sec] well-known phase noise model based on the linear time-invariant assumption for oscillators in 1966, which was the first model widely used for phase noise analysis, partly due to its simplicity. The corresponding empirical formula derived from Leeson's model is given by [I-75]

  Figure I.3.10. Thus, the effect on the oscillation waveform when the current impulse i(t) is injected into the LC resonant tank can be represented in Figure I.3.11, and the instantaneous voltage change ∆V is given by ∆𝑉 = ∆𝑞 𝐶 𝑡𝑜𝑡 ⁄ , where ∆q is the total injected charge by the current impulse and Ctot is the total capacitance at the node considered. Obviously, the current impulse will change only the instantaneous voltage across the capacitor and will not affect the instantaneous current through the inductor. As shown in Figure I.3.11 (a), when the current impulse is injected at the peak of the capacitor voltage, it will only change the amplitude of the oscillator. Because of the nonlinear limiting mechanism in the oscillator, the oscillation amplitude is able to return to a steady state after a period of time.Figure I.3.11 (b) shows that when the current impulse is injected at the zero-crossing point, the current impulse will only change the phase of the oscillator. When the current impulse is added at any other time, it will change both the amplitude and the phase of the oscillator. Since the phase change cannot be eliminated, the effect of noise source on phase shift is usually of interest.

Figure I. 3 . 10

 310 Figure I.3.10 Phase and amplitude impulse response model

Figure I. 3 . 12

 312 Figure I.3.12 Conversion of noise to phase fluctuations and phase noise sidebands.

  shown in Figure II.1.1, the third-generation Pegasus Verification System is a massively parallel, cloud-ready, physical verification signoff solution that improves the performance of DRC runs by up to 10 times, enabling engineers to deliver advanced node integrated circuits to market faster [II-1].

Figure II. 1 . 1

 11 Figure II.1.1 Third-generation Pegasus Verification System.

Figure

  Figure II.1.2 (a) Bulk CMOS versus (b) FD-SOI. (Source: STMicroelectronics).

Figure II. 1 . 4

 14 Figure II.1.4 Cross-section view of (a) conventional well and (b) flipped well.

  Figure II.1.6 Threshold voltage for different back-gate voltages.

Figure

  Figure II.2.1 (a) Simplified structure of a typical LC-based VCO using the MOS varactor. (b) Frequency-voltage characteristic curve.

  The nonlinearity of the capacitance-voltage (C-V) curve becomes more and more severe at low supply voltages. As shown in FigureII.2.2(a), the linear tuning range is strongly compressed and the gain KVCO is undesirably high in deep sub-micrometer CMOS processes, so the oscillator is very sensitive to noise and interference, leading to severe degradation of its overall performances.To verify these findings, a differential MOS varactor is designed and simulated. The cross-section diagram of a MOS varactor (NFET in N-well) in the GF 22 nm FD-SOI process is illustrated in FigureII.2.2(b). It is a 3-terminal device, where pin 1 (Gate)

  represents the polysilicon finger, pin 2 (N-well) represents N + over N-well, and pin 3 (PSUB) is the substrate contact and should always be connected to the ground [II-5]. The differential MOS varactor using the device egncap_rf (extended gate NFET over N-well capacitor from the RF library) is configurated as in Figure II.2.

Figure

  Figure II.2.2 (a) Idealized C-V curves of a MOS varactor for both a traditional and deep sub-micrometer CMOS process. (b) Cross-section view of the MOS varactor model. (c) Differential MOS varactor using the device egncap_rf and its main parameters. (d) Simulated capacitance and Q-factor versus voltage curves of (c).

  Figure II.2.3 [II-6], which is composed of a coarse-tuning block to extend the frequency range and a finetuning block to improve the resolution. The number of inverters in the loop can be changed by controlling the multiplexer through digital coarse-tuning words. Fine frequency resolution is achieved by changing the driver strength on the fixed loading or adjusting the load capacitance.

Figure

  Figure II.2.3 A conventional RO-based DCO.

Figure II. 2 . 4

 24 Figure II.2.4 RO-based DCO using parallel tri-state inverters.

Figure

  Figure II.2.5 (a) MOS varactor controlled by the DAC. (b) Binary-weighted switchedcapacitor bank controlled by the digital signal.

  is to use switched capacitors in parallel with the MOS varactor. As shown in FigureII.2.5(b), the switched capacitors can be arranged in a binary weighted bank, which can be controlled by digital control words. Essentially, this type of wideband VCO is no analog circuit, but a mixed-signal circuit. If the voltage-controlled varactor is also removed and replaced by digitally controlled capacitor banks with different frequency resolutions, a classical multi-bank LC-based DCO can be formed.Consequently, the LC-based DCO inherits the advantages of the LC-based VCO, such as high operating frequency and excellent phase noise performances, making it the most popular DCO. Moreover, the LC-based DCO can also be implemented by changing the inductance value using digital control signals. However, this approach is rarely employed due to its complexity.II.3. Development and Research StatusII.3.1. First Multi-Gigahertz DCO for RF ApplicationsIn 2003, the first multi-gigahertz LC-based DCO for RF applications was proposed in, contributing significantly to the in-depth development of DCOs.

Figure

  Figure II.3.1 (a) DCO with discrete tuning controls. (b) Differential PMOS varactor driven by an inverter. (c) Modeling a binary-weighted switched capacitor.

  where L and C are the total inductance and capacitance, respectively. Moreover, the total capacitance is quantized into an N number of smaller digitally controlled MOS varactors.As shown inFigure II.3.1(b), they are configured differentially and each of them consists of two PMOS transistors M1 and M2, whose drain, source, and back gate are shorted together and tied to the inverter output. Depending on the oscillator tuning word (OTW), the inverter output has only two discrete voltage values (Vtune_high and Vtune_low), which in turn make the PMOS varactor operate either in the off-state or in the on-state. The capacitance difference between these two states of the kth PMOS varactor is

Figure

  Figure II.3.1(c) shows a model of a binary-weighted switched capacitor with the digital control bit 𝑘 ̅̅̅ , the kth such switched capacitor has a weight of 2 k , which is composed of 2 k basic PMOS varactors in parallel for better matching. The low capacitance and capacitance difference of one basic PMOS varactor are 𝐶 0 and ∆𝐶 0 ,

Figure II. 3 . 2

 32 Figure II.3.2 Binary-weighted switched-capacitor bank of size N.

Figure II. 3 . 3

 33 Figure II.3.3 LC tank with three-stage switched-capacitor banks.

  varactor in FigureII.3.1(b), a common approach is to use two parallel mismatched MOS varactors.

Figure

  Figure II.3.4 (a) Mismatch between two PMOS varactors with different sizes. (b) Mismatch between two PMOS varactors with different connections. (c) Mismatch between a PMOS varactor and a NMOS varactor.

  Switched-capacitor structures were first widely used to extend the frequency tuning range of VCOs, and a commonly used single-ended structure is shown in FigureII.3.5(a).The NMOS transistor switches one plate of a fixed capacitor to the ground (ON state) or leaves it floating (OFF state), while the other plate is connected to the resonant tank of the oscillator [II-14],. Furthermore, as shown in FigureII.3.5(b), its differential structure has also been widely employed,. Compared with the single-ended structure, the two NMOS switches will contribute two series drain-to-source parasitic resistors in the ON state (EN = 1) and a smaller parasitic capacitance in the OFF state (EN = 0). It is worth noting that the voltage at the two floating points A and B is slightly higher than the supply voltage VDD in the OFF state, which does not significantly reduce the lifetime of the NMOS switches M0 and M1 since their channel do not conduct any current in the OFF state.

Figure II. 3 . 5

 35 Figure II.3.5 Common structures of switched capacitors.

  Figure II.3.5(b) and Figure II.3.5(c).

Figure

  FigureII.3.5(f) illustrates a more straightforward structure that contains only three transistors, the series switch M0 with two pull-down transistors, M1 and M2, are used to effectively turn the cell between its high and low capacitance states [II-24]-[II-26]. In the ON state, the source and drain of the M0 are biased to the ground. In addition, a comparable size of these three transistors results in a smaller ON resistance, hence a better Q-factor, although M1 and M2 contribute part of the parasitic capacitance in the OFF state.

Figure

  FigureII.3.5(h) shows a new switched-capacitor structure. The sizes of M0-2 are the same, and VS is biased to a voltage slightly higher than the gate voltage of M1 and M2, making them (M1 and M2) completely switched off. As a result, only the gate-tosource and gate-to-drain overlap capacitances are employed in this structure, thereby allowing an excellent capacitance resolution. In addition, this structure is very compact, although suffering from a trade-off between stability and parasitic.

Figure II. 3 . 6

 36 Figure II.3.6 General DiCAD differential transmission line configuration. (b) Crosssectional view of DiCAD differential transmission line strip.

Figure II.3. 7

 7 Figure II.3.7 Schematic of the DiCAD DCO

Figure

  Figure II.3.8 (a) Schematic of the 60 GHz inductor-based DCO. (b) Inductor-based fine-tuning bank. (c) Reconfigurable TL for coarse-tuning and medium-tuning.

Figure

  Figure II.3.9 (a) Schematic of the 60 GHz transformer-based DCO. (b) Transformerbased fine-tuning bank.

  TableII.3.1 gives the performances of some typical LC-based DCOs. It can be seen that the DCOs are mainly evolving towards low power consumption, high frequency, and low phase noise. Meanwhile, depending on the application scenarios, they differ in frequency-tuning range (FTR) and frequency resolution. A low-power DCO typically employs a complementary cross-coupled structure driven by a low supply voltage, as in [II-16], [II-31], and [II-26]. Moreover, most DCOs operate at frequencies below 10 GHz and typically use a multi-stage switched-capacitor structure to achieve both wide FTR and high resolution, as in [II-11], [II-12], [II-32], and [II-33].

Figure II. 4 . 1

 41 Figure II.4.1 The principle of FMCW radars with triangular modulation for detecting a stationary target and the resulting beat signal.

II. 4

 4 .2(a). Since the frequency of this beat signal is fixed, this signal can be further represented as a solitary rectangular pulse x(t) with a pulse width Tm/2 and amplitude A, as shown in FigureII.4.2(b), which can be expressed as 𝑥(𝑡) = { 𝐴 -

Figure II. 4 .

 4 Figure II.4.2 (a) A solitary rectangular pulse and (b) its spectrum.

Figure II. 4 . 3

 43 Figure II.4.3 The principle of FMCW radar with triangular modulation for detecting a moving target and the resulting beat signal.

  For an ADPLL-based FMCW generator, the DCO tuning words (OTW) are stepped up/down on each rising edge of the modulation clock, following the triangular chirp trajectory. The accuracy of such FMCW radar depends not only on the ADPLL's phase noise and robustness to PVT variations, but also on the chirp's linearity that determines the beat frequency's quality. As we know, most DCOs are based on multi-bank structures to achieve both high frequency resolution and wide tuning range. Therefore, the wideband triangular modulation requires traversing multiple capacitor banks with different gain KDCO. Consequently, in multi-bank DCOs, gain calibration and linearization techniques are critical for generating a linear chirp.

Figure II. 4 . 4

 44 Figure II.4.4 Gain calibration and linearization technique of multi-bank DCOs.

  to 95 % of the final vdd_dco) supply voltage and ground makes it unsuitable for low supply voltage applications in advanced process nodes. Therefore, only NMOS-only structures will be considered in this design. Three of these representative structures are shown in FigureII.5.1.

Figure

  FigureII.5.1(a) shows the structure of a class-B cross-coupled oscillator, which is one of the most famous and widely used topologies. When the oscillation amplitude is small, the oscillator operates in the current-limited region, where the oscillation amplitude is proportional to the tail current. As the tail current keeps increasing, the oscillation amplitude continues to increase gradually until it remains constant, i.e., entering the voltage-limited region. Since the single-side transistor of the cross-coupled pair conducts in about half a cycle, which means that its conduction angle is 180°, this type of oscillator is called the class-B oscillator.

Figure II. 5 . 1

 51 Figure II.5.1 Commonly used NMOS-only structures of cross-coupled LC DCO. (a) Class-B structure. (b) Class-C structure. (c) Class-D structure.

Figure

  FigureII.5.1(b) shows the structure of a class-C cross-coupled oscillator. Compared with the class-B oscillator, the gates of its cross-coupled pair are no longer biased to VDD, but at a lower bias voltage VB, and the output signal is coupled through capacitor CB.Therefore, the class-C structure prevents the cross-coupled pair from entering the deep triode region by controlling the VB (reducing the overdrive voltage), thus improving the PN performances. Since the conduction time of a single-side transistor is less than half a cycle, i.e., the conduction angle is less than 180°, this type of oscillation is referred to as

Figure

  Figure II.5.1(a) as the K-band DCO architecture.

  Figure II.5.2 shows some simulation results for several typical inductance values of center-tap inductors and their Q-factors at 20 GHz in GlobalFoundries' (GF) 22 nm FD-SOI process. Inductors between 100 -150 pH exhibit a good Q-factor of ~22. In general, the MOS varactor structure shown in Figure II.5.3(a),

Figure II. 5 . 2

 52 Figure II.5.2 Typical inductance and Q-factor of a center-tapped inductor at 20 GHz implemented in the GF' 22 nm FD-SOI process.

Figure

  Figure II.5.3 (a) MOS varactor structure commonly used for sub-10 GHz DCOs. (b) Simplified switched-capacitor structure adapted to K-band DCOs.

  Figure II.5.4 (a) Block diagram of the proposed T-DCO. (b)Center-tapped inductor and its main parameters. (c) Schematic of the coarse-tuning unit. (d) Schematic of the medium-tuning unit. (e) Schematic of the fine-tuning unit.

  pH is implemented using the tenth layer of thick metal with a width of 6 μm, as shown in FigureII.5.4(b). It achieves a Q-factor of about 22 at 20 GHz. The oscillation frequency adjustment is carried out by three parallel capacitor banks: the coarse-tuning bank, the medium-tuning bank, and the fine-tuning bank.Table II.5.2 Main parameters of the proposed T-DCO.Two NMOS transistors (N1,2) form a differential cross-coupled pair with a negative transconductance -gm/2 to compensate for the losses caused by the parallel resistance RP of the LC tank. As shown in Figure II.5.5, a minimum 𝑅 𝑃 ≈ 240 Ω arises at the lowest resonant frequency of 20.1 GHz. In addition, N1 and N2 are thick oxide devices with a channel length of 100 nm, targeting to compensate for the lifetime degradation caused mainly by the hot carrier injection (HCI) effect, particularly for large voltage swing cases.Furthermore, two diodes placed underneath the gates of N1 and N2 are employed to protect their thin gate dielectrics from the antenna effect during chip manufacturing and to avoid mismatch problems.

Figure II. 5 . 5

 55 Figure II.5.5 Real part of the impedance versus the resonant frequency of the LC tank.

and

  Cwiregs include PC-CA, M1-PC, M1-CA, and CA-CA capacitances between the gate and the source/drain regions. M1-M1 parasitic capacitances will be extracted by PEX (Parasitic Extraction). Cwireds include CA-CA, M1-M1 capacitances, and fringing capacitances between M1-M1 in multi-finger devices [II-56].

Figure II. 5 . 7

 57 Figure II.5.7 NMOS in N-well (flipped well) with M1 reference plane: (a) cross-section view, (b) RF sub-circuit, (c) corresponding labels of the components.

Figure

  Figure II.5.8 (a) Typical schematic and (b) truth table of a 3-input 7-output binary-tothermometer decoder.

Figure II. 5 . 9

 59 Figure II.5.9 Equivalent schematic of the coarse-tuning unit: (a) in the OFF-state, (b) in the ON-state.

Figure

  Figure II.5.10 (a) Threshold voltage VTH of N5-7 versus back-gate voltage. (b) QON and RON of the coarse-tuning unit versus back-gate voltage.

  .5.3.4. 6-Bit Medium-Tuning Bank To ensure the monotonicity of the frequency chirp, the whole frequency range of 19 -20.25 GHz, equaling a quarter of 76 -81 GHz, should mainly rely on the mediumtuning bank as the fine-tuning bank has a very narrow FTR. Considering the trade-off between the frequency range and the frequency resolution, a 6-bit (MB[5:0]) mediumtuning bank is thermometer decoded to sweep the 63 medium-tuning units. Moreover, to avoid the large interconnect parasitic capacitances caused by the large area of the medium-tuning bank, a more compact structure with only two NMOS switches (N8,9) is employed, as shown in Figure II.5.4(d).

Figure

  Figure II.5.11 Equivalent schematic of the medium-tuning unit: (a) in the OFF-state, (b) in the ON-state

  Section II.5.2.3, a high capacitance resolution of tens of attofarads is required to achieve a fine frequency resolution of ~2 MHz for the purpose of low quantization noise. Therefore, we propose a novel back-gate-based fine-tuning bank, as shown in Figure II.5.4(e). The drain and source nodes of the two MOS switches (N10,11)are connected to the supply voltage (VDD) to make them operate in the depletion region, providing lower capacitance and better Q-factor. The control signal ENF is applied to their back-gates. Note that the back-gate technique is often used to flexibly control the threshold voltage and thus improve the performances and energy efficiency of the circuit.

Figure II. 5 . 14

 514 Figure II.5.14 Output waveforms for tail currents (IT1) of 5 mA and 20 mA, respectively.

Figure

  FigureII.5.15 illustrates the drain-source current waveforms on one side of the crosscoupled pair after the T-DCO reaches the steady state. It can be seen that there is a large spike in the waveform when the tail current is 20 mA, which means that the transistor on the other side is completely off, and almost no noise is introduced. In contrast, when the tail current is 5 mA, the cross-coupled pair is conducting most of the time, thus continuously injecting noise into the resonant tank.

FigureFigure

  Figure II.5.16 illustrates the PN performances of this T-DCO. At a carrier frequency of about 21.5 GHz, the PN at 1 MHz frequency offset can be boosted from -107.4 dBc/Hz to -111.4 dBc/Hz (i.e., an improvement of 4 dB) when the tail current is increased from 5 mA to 20 mA. Meanwhile, simulation results also show that the PN performances (at 1 MHz frequency offset) at the maximum frequency of 26.4 GHz and the minimum frequency of 19 GHz are also improved by 2.5 dB and 4.6 dB, respectively.

Figure II. 5 .

 5 Figure II.5.16 PN performances of the T-DCO for tail currents (IT1) of 5 mA and 20 mA, respectively.

Figure

  FigureII.5.17 shows the partial frequency-code characteristic curves of the mediumtuning bank and the fine-tuning bank when the coarse-tuning code is 16 (CB = 16). When

Figure

  Figure II.5.17 Frequency-code characteristics of the medium-tuning bank and the finetuning bank when CB = 16.

  Figure II.5.18 Top layout view of the proposed T-DCO

II. 7 .

 7 then reviewed three common types of DCOs. The RO-based DCO features poor phase noise performances and low oscillation frequency. The DAC-based DCO is highly dependent on a high-performance DAC and it is still essentially a VCO. The LC-based DCO not only exhibits excellent phase noise, but also can achieve both wide FTR and fine frequency resolution through a multi-stage capacitor bank structure, which is undoubtedly the most favored DCO structure at present. In Section II.3, we started with a brief introduction of the first LC-based DCO for RF applications and its principle of digital-to-frequency conversion, where digitally controlled MOS varactors are used as frequency tuning units. We then reviewed and compared some of the commonly used frequency tuning techniques in DCOs, including mismatched MOS varactor structures, various switched-capacitor structures, and mm-W DiCAD structures. Finally, we summarized the performances of some typical LC-based DCOs in the literature at different frequencies.In Section II.4, we mainly analyzed the principle of FMCW radar for detecting stationary and moving targets, and also briefly introduced the DCO gain calibration and linearization in chirp signal generation.In Section II.5, we first outlined the background of DCO design for 76 -81 GHz FMCW automotive radars. Next, we discussed some critical considerations for K-band DCO designs. Then, we detailed the proposed K-band T-DCO using the 22 nm FD-SOI process. We further analyzed the employed three different switched-capacitor structures, which allow to a wide FTR of more than 20 % and a frequency resolution of about 1.38MHz. Moreover, the post-layout simulation results show that the T-DCO achieves best--129 -in-class phase noise in a compact area. Résumé du Chapitre II Le Chapitre II est consacré à la conception et la réalisation d'OCN à triple banques de capacités commutées (T-OCN) en bande K. Dans la Section II.1, nous avons brièvement présenté les outils d'automatisation de la conception électronique (EDA en anglais) et la technologie 22 nm FD-SOI de GlobalFoundries utilisée dans le cadre de ces travaux de thèse. Par rapport aux process CMOS traditionnels, les dispositifs FD-SOI permettent de mieux contrôler le canal et de concevoir des circuits aux fréquences millimétriques. Grâce à la couche d'oxyde enterrée, les capacités parasites des jonctions (source, drain), le courant de fuite et les différentes sources de bruits sont considérablement réduits. En outre, la technologie de polarisation de la grille arrière et la structure à puit inversé (flipped well en anglais) sont les deux autres avantages du process FD-SOI, qui offre davantage de choix pour la conception des circuits qu'un process CMOS conventionnel. Dans la Section II.2, nous avons d'abord indiqué les limites des Oscillateurs Contrôlés en Tension (OCT) traditionnels à résonateur LC utilisant un varactor MOS et implémentés en utilisant des process CMOS avancés, telles que la faible tension d'alimentation, la tension de seuil relativement élevée et la non-linéarité de la courbe capacité-tension. Nous avons ensuite comparé trois types courants d'OCN. Les OCNs à oscillateur en anneau qui ont un faible bruit de phase et une fréquence d'oscillation relativement basse. Les OCNs basés sur un Convertisseur Numérique-Analogique (CNA) qui dépendent fortement des performances du CNA et restent essentiellement des OCTs. Les OCNs à résonateur LC qui présentent non seulement un excellent bruit de phase, mais qui permettent également d'obtenir une large plage de réglage de la fréquence et une très bonne résolution en fréquence grâce aux multiples banques de capacités commutées qui peuvent être utilisées. Dans la Section II.3, nous avons d'abord présenté le premier OCN à résonateur LC réalisé et fonctionnant à 2.4 GHz, dans lequel un varactor MOS contrôlé numériquement est utilisé comme unité de réglage de la fréquence. En outre, nous avons comparé certaines techniques de réglage de la fréquence couramment utilisées dans les OCNs, -130 -telles que les varactors MOS non appariés, différentes structures de capacités commutées et les structures diélectriques artificielles contrôlées numériquement (DiCAD en anglais). Parmi ces techniques, la structure à capacité commutée est le premier choix pour la conception d'un OCN en bande K en raison de sa flexibilité, de sa stabilité et de sa simplicité. Nous avons également résumé les performances des OCNs typiques à résonateur LC oscillant à différentes fréquences et présents dans la littérature. Nous avons pu constater que peu d'OCN en bande K ou à ondes millimétriques ont été publiés, et que la plupart d'entre eux ne peuvent répondre aux contraintes imposées par les radars automobiles FMCW en raison de la limitation de la plage de réglage de la fréquence et de la résolution en fréquence. Afin de mieux comprendre les particularités des OCNs appliqués aux radars FMCW, nous avons analysé en détail, dans la Section II.4, le principe du radar FMCW pour la détection de cibles stationnaires et mobiles, dont la précision dépend non seulement du bruit de phase et de la robustesse du système aux variations de process, de la température et de la tension d'alimentation (PVT en anglais), mais aussi de la linéarité des signaux modulés en fréquence. À notre connaissance, la plupart des OCNs sont basés sur des structures à multiples banques de capacités commutées permettant d'obtenir simultanément une haute résolution en fréquence et une large bande, ce qui signifie que la génération du signal modulé à large bande requiert l'utilisation de plusieurs banques de capacités commutées avec différents gains. Par conséquent, nous avons ensuite discuté brièvement des techniques d'étalonnage et de linéarisation du gain dans les OCNs à multiples banques de capacités commutées, lesquelles sont essentielles à la génération du chirp. À la suite de ces discussions, dans la section II.5, nous avons d'abord décrit le contexte et les défis à relever afin de concevoir un OCN pour les radars automobiles FMCW fonctionnant entre 76 et 81 GHz. Nous avons ensuite présenté quelques considérations importantes pour la conception d'un OCN en bande K, notamment les spécifications de l'OCN souhaité, sa topologie, la conception du résonateur LC en bande K et le faible bruit de phase. Afin d'atteindre une largeur de bande de fréquence d'environ 2.5 GHz et une résolution d'environ 2.5 MHz, nous avons d'abord proposé d'utiliser trois banques de capacités commutées. Parmi ces banques, la banque de réglage grossier est principalement utilisée pour compenser les variations de PVT, tandis que les banques de réglage moyen et fin permettent de couvrir la largeur de bande du chirp. Afin de satisfaire aux exigences de faible bruit de phase et de stabilité, la structure classique d'oscillateur à simple paire croisé fonctionnant en classe B a été adoptée. Par ailleurs, nous avons étudié en détail les capacités parasites des commutateurs MOS pour différentes régions de fonctionnement, ce qui est utile pour l'analyse qualitative de la structure à capacité commutée. Dans ces conditions, les résultats de simulations post-layout montrent que le T-OCN proposé oscille à une fréquence moyenne de 19.61 GHz et permet d'obtenir une large plage de réglage de la fréquence de 23.4 % et un faible bruit de phase de -112.6 dBc/Hz à 1 MHz de la porteuse. Une nouvelle structure de réglage fin basée sur la grille arrière permet d'obtenir une résolution de fréquence fine d'environ 1.38 MHz. En outre, le chevauchement de fréquence de plus de 15 % entre les banques de réglage moyen et fin permet la génération d'un chirp linéaire avec une plage de fréquence d'environ 1.84 GHz. Le T-OCN consomme environ 24 mW sous une tension d'alimentation de 1.2 V, ce qui conduit à une FoM de -184.65 dBc/Hz et une FoMT de -192.03 dBc/Hz. Il est implémenté en technologie 22 nm FD-SOI et occupe une surface de 201×302 μm 2 . En conclusion, bien que le bruit de phase obtenu par le T-OCN proposé n'atteint pas les spécifications de -115 dBc/Hz à 1 MHz de la porteuse, les résultats de simulation postlayout montrent qu'il permet d'obtenir un bruit de phase à l'état de l'art. En outre, le T-OCN proposé est relativement robuste aux variations de PVT. Dans un cas typique (27º, tt corner, 1.2V), le T-OCN atteint un bruit de phase inférieur à -110 dBc/Hz à 1 MHz de la porteuse sur l'ensemble de la plage de fréquences, tout en permettant une large plage de réglage de la fréquence d'environ 20 %. Enfin, ce travail de recherche confirme la faisabilité de la conception d'un OCN à faible bruit de phase en bande K pour un radar automobile FMCW fonctionnant entre 76 et 81 GHz en technologie 22 nm FD-SOI. En outre, la nouvelle structure de capacité commutée basée sur la grille arrière proposée dans le T-OCN s'avère essentielle à l'obtention d'une résolution de fréquence fine.II.8. References[II-1] L. Cadence Design System, "Cadence Launches the Pegasus Verification System, a Massively Parallel Physical Signoff Solution," 2017. [II-2] GLOBALFOUNDRIES, "22FDX-EXT Process Design Kit (PDK) Release Notes," 2019. The simplified block diagram and main parameters of the proposed D-DCO.1 are depicted in Figure III.2.1 and Table III.2.1, respectively. The D-DCO.1 also adopts the cross-coupled LC structure with a tail current mirror as the T-DCO, but it contains only two parallel switched-capacitor banks: a 4-bit coarse-tuning bank and a 9-bit fine-tuning bank. As we mentioned before, the coarse-tuning bank is mainly used to compensate for PVT variations, and the fine-tuning bank needs to cover the entire chirp band. As shown in Figure III.2.1(b), the center-tapped inductor has an inductance value of 78.6 pH, its inner diameter is 44.5 μm. Moreover, this inductor is implemented in the tenth metal layer (QB) with a width of 6 μm and a thickness of 3.5 μm, and it achieves a Q-factor of about 20 at 20 GHz. The ratio of the current mirror is 12, and its thermal noise is filtered out by the large tail capacitors (CT1 and CT2). Meanwhile, since the ideal current source IR1 provides a reference current of 1 mA, the tail current IT1 is about 12 mA.

Figure

  Figure III.2.1 (a) Block diagram of the proposed D-DCO.1. (b) Center-tapped inductor and its main parameters. (c) Schematic of the coarse-tuning unit. (d) Schematic of the fine-tuning unit.

  value would cause the DCO to fail to oscillate around 20 GHz; (c) the fine-tuning unit with a small capacitance value allows the use of small-size MOS switches (N8,9, 5 μm/70 nm) while not degrading its Q-factor significantly. Moreover, the pre-layout simulation results of the fine-tuning unit are illustrated in Figure III.2.3. It can be seen that the Qfactor can also be further improved by increasing the back-gate voltage. When the backgate voltage is 2 V, the proposed fine-tuning unit achieves a capacitance ratio of 747 aF/513 aF and an excellent Q-factor ratio of 80.4/278.9.

Figure III. 2 . 3

 23 Figure III.2.3 Pre-layout simulation results of the fine-tuning unit. (a) Capacitance values and (b) Q-factor versus control voltage ENF when the back-gate voltage is 0 V, 1V, 2V, respectively.

Figure

  FigureIII.2.4 shows the schematic of the 10-bit fine-tuning bank, which is array-

Figure III. 2 . 4

 24 Figure III.2.4 Schematic of the 10-bit fine-tuning bank.

Figure

  Figure III.2.5(c) depicts an example of logical values in the array control architecture.It can be seen that there are three possibilities: (1) one column is completely on; (2) one column is completely off; (3) one column is partially on. More specifically, if C(i) = 1 and its next bit C(i+1) = 1, the output logical value Y = 1, meaning that the corresponding ith and (i+1)th columns are fully on. If C(i) = 1, C(i+1) = 0, the ith column is still fully on, but the (i+1)th column is partially on, and R(j) is used to control the number of turned-on

Figure

  Figure III.2.5 (a) Simplified array control architecture of the fine-tuning bank, (b) digital control block implementation, and (c) example of output logical values.

  can conclude that the column code C(i+1) is assigned to turn 31 fine-tuning units (one column) on or off simultaneously, i.e., if C(i+1) = 1, Y = 1. The column code C(i), together with the raw code R(j), is assigned to control an individual fine-tuning unit, which means that if C(i) = 0 and R(j) = 1, then Y = 1, otherwise Y = 0.

Figure III. 2 . 7

 27 Figure III.2.7 Output oscillation waveforms of the D-DCO.1.

Figure III. 2 . 9

 29 Figure III.2.9Frequency-code characteristic of the fine-tuning bank when the coarsetuning code is 8.

  4 mW from a 1.2 V supply voltage. Its pre-layout simulated PN performances at minimum, medium, and maximum frequencies are shown in Figure III.2.10. At the medium frequency (CB = 8, FB = 481) of 19.68 GHz, the PN is -70.3 dBc/Hz and -116.1 dBc/Hz at 10 kHz and 1 MHz frequency offsets, respectively. Compared to the PN at medium frequency, the PN has no significant improvement at the minimum frequency (CB = 15, FB = 961) of 17.73 GHz due to the

  code: FB[9:0] Fine-tuning code: FB[9:0]

Figure III. 2 . 13

 213 Figure III.2.13Frequency and PN variations versus different processes.

Figure

  Figure III.2.14 Frequency and PN variations versus different supply voltages.

Figure III. 2 . 15

 215 Figure III.2.15 Frequency and PN variations versus different temperatures.

Figure

  FigureIII.2.16 gives the layout view of a single fine-tuning unit. It can be seen that the digital control block occupies twice the area of the fine-tuning unit since it contains more transistors. Note that all the used transistors and capacitors are from the standard library of the 22 nm FD-SOI process. Then, taking into account the DRC rules, such as the minimum distance between two adjacent transistors, a non-compact layout is obtained.

Figure

  Figure III.2.16Layout of a single fine-tuning unit with a digital control block.

Figure III. 2 .

 2 Figure III.2.17 Internal connection of partial fine-tuning bank.

Figure

  Figure III.2.17 shows the internal connection of the upper left part of the 10-bit finetuning bank. As explained in Figure III.2.5, this fine-tuning bank adopts an array control architecture, where all 961 fine-tuning units can be precisely controlled by row codes (Row<0>, Row<1>, …) and column codes (Col<0>, Col<1>, …).

  Figure III.2.19 New fine-tuning unit without the digital control block.

Figure

  Figure III.2.20 New 10-bit fine-tuning bank without the digital control block.

Figure

  Figure III.2.21 New resized fine-tuning bank with 20 × 20 fine-tuning units.

D

  -DCO.2, as well as some essential modifications relative to the D-DCO.1. The transition from D-DCO.1 to D-DCO.2 shows in detail the whole design process and difficulties of D-DCO. III.3.1. Circuit Implementation of the Proposed D-DCO.2 III.3.1.1. Block Diagram of the K-Band D-DCO.2 As shown in Figure III.3.1, the structure of D-DCO.2 is basically the same as that of D-DCO.1. However, as the final version of D-DCO, intuitively, two high-speed Σ∆ dithering units are inserted in D-DCO.2, while two diodes are placed under the gates of the cross-coupled pair (N10 and N11) to protect their thin gate dielectric from the antenna effect. The main parameters of D-DCO.2 are given in TableIII.3.1. Several other notable differences can be noted:• The tail current (IT2) and width-to-length ratio (W/L) of the cross-coupled pair are significantly increased. In D-DCO.1, we separately simulate different process corners, different voltages, and different temperatures without considering the worst case (ss -158 -corner, low voltage, high temperature), and the gain of D-DCO.1 has reached its limit value. Therefore, for D-DCO.2, it is necessary to further increase its gain to compensate for the PVT variations in the worst case.

Figure•

  Figure III.3.1 (a) Block diagram of the proposed D-DCO.2. (b)Center-tapped inductor and its main parameters. (c) Schematic of the coarse-tuning unit. (d) Schematic of the fine-tuning unit.

  Figure III.3.1(c), which achieves a capacitance ratio of 17.25 fF/7.04 fF and a Q-factor ratio of 82/25 using a large series MOM capacitor of 34.2 fF. The 4-bit coarse-tuning bank (CB[3:0]) incorporates 15 such coarse-tuning units to cover the frequency range of 19.18 -21.17 GHz for PVT compensation, resulting in an average coarse frequency resolution of 133 MHz. As shown in Figure III.3.1(d), the 10-bit fine-tuning bank (FB[9:0]) incorporates 961 fine-tuning units. Ideally, they allow to cover the entire 19 -20.25 GHz FMCW chirpwith a constant fine frequency resolution, thus avoiding the complex gain calibration required in the T-DCO. In addition, a small single-turn center-tapped inductor of 78.6 pH is selected to leave enough margin for the large fine-tuning bank. This inductor features a Q-factor of about 20 at 20 GHz.III.3.1.2. Fine-Tuning Bank Using a Novel Customized MOM CapacitorImplementing a fairly large fine-tuning bank faces several significant trade-offs: Qfactor, frequency resolution, FTR, and parasitic capacitances. The same structure of two NMOS switches as the fine-tuning unit of the D-DCO.1 is used to attain a high Q-factor, thereby ensuring excellent PN performances. The frequency resolution can be flexibly configured by changing the size of the NMOS switches (parasitic capacitance in the OFFstate). The resonant frequency of about 20 GHz requires that the total capacitance of the fine-tuning unit must not exceed 1 fF. However, the capacitance value of the smallest capacitor that the standard library can provide is 2.63 fF. Therefore, in the fine-tuning -160 -unit of the D-DCO.1, four such smallest capacitors are connected in series to achieve capacitance values below 1 fF. However, the layout area of the fine-tuning unit increases accordingly, resulting in large interconnect parasitic capacitances in the fine-tuning bank with 961 such fine-tuning units. To further reduce the layout area of this new fine-tuning bank, a new customized capacitor is developed.

Figure

  Figure III.3.2 (a) Structure of the novel customized MOM capacitor. (b) Its equivalent π model.

Figure

  Figure III.3.3 (a) New fine-tuning unit with the customized capacitor. (b) New 10-bit fine-tuning bank.

  fifth layer) is deployed to reduce the substrate coupling capacitance. A shield is placed at its bottom and serves to maintain a stable capacitance value. Furthermore, this customized capacitor is characterized by the 2-port S-parameters, and its simplified equivalent π model is illustrated in Figure III.3.2(b). The parasitic parameters extracted by Momentum show a main capacitance Cs of 819.7 aF, a series resistance Rs of 33 mΩ, and coupling capacitances Cp1 and Cp2 are 152.7 aF and 107.7 aF, respectively. The total capacitance is ~973 aF. The layout of the fine-tuning unit with the customized capacitors is shown in Figure III.3.3(a), the layout area is 2.8 µm × 5.56 µm, which is only 29 % of the layout area of the fine-tuning unit used in D-DCO.1 (Figure III.2.19). In addition, the layout of the 10bit fine-tuning bank is shown in Figure III.3.3(b), the layout area is 98 µm × 234 µm, which is about 40 % of the layout area of the fine-tuning bank in D-DCO.1 (Figure III.2.20). Meanwhile, simulation results show that this new fine-tuning unit achieves a capacitance ratio of 380 aF/536 aF (i.e., a capacitance difference of 156 aF) and a Qfactor ratio of 140/88. In addition, the electrostatic discharge (ESD) effect caused by long digital control lines, especially high-frequency ΣΔ dithering control lines, is avoided by placing diodes under the common gate of NMOS switches.

Figure III. 3 . 4

 34 Figure III.3.4 Frequency-code curve of the coarse-tuning bank when FB = 481.

Figure III. 3 . 5

 35 Figure III.3.5 Frequency-code curve of the fine-tuning bank when CB = 8.

Figure III. 3 . 6 7

 367 Figure III.3.6 Top layout view of the proposed D-DCO.2.

Figure III. 3 . 8

 38 Figure III.3.8 Frequency-code curve of the fine-tuning bank when CB = 8.

Figure III. 3 . 9

 39 Figure III.3.9 Simulated phase noise plot at the minimum frequency of 18.37 GHz, the medium frequency of 20.06 GHz, and the maximum frequency of 22.44 GHz.

  The performances of the proposed D-DCO.2 compared with the state-of-the-art and the T-DCO are presented in TableIII.3.5. To the best of our knowledge, only few K-band DCOs have been published so far. The DCO presented in [III-1] is a dual-band design with a minimum frequency resolution of ~187 MHz, which does not meet the specifications of FMCW automotive radar. No less than three switched-capacitor banks are employed in [III-2]-[III-4], which is similar to the proposed T-DCO and requires complex frequency calibration algorithms to generate FMCW chirps. Moreover, it should be noted that the more switched-capacitor banks in the DCO, the higher the complexity of the algorithm. Therefore, unlike the above published DCOs, the proposed D-DCO.2 solely relies on the fine-tuning bank to completely cover the frequency range of the

  SummaryThe proposed D-DCO.2 features a wide FTR of 20 % and a low PN of -113.04 dBc/Hz at the medium frequency of 20.06 GHz. Post-layout simulation results indicate that it is capable of operating in the harshest environment, i.e., the worst case (125º, ss corner, 1.14 V). The construction of the FMCW chirp solely relies on the fine-tuning bank, and the frequency overlap problem in conventional muti-bank DCOs is no longer present.Meanwhile, the 961 fine-tuning units employ the novel customized interdigitated MOM capacitor of about 973 aF, thereby enabling a fine frequency resolution of ~2.1 MHz and a fine-tuning range of ~2 GHz. Moreover, the D-DCO.2 consumes about 24 mW from a 1.2 V supply voltage, leading to a FoM of -185.64 dBc/Hz and a FoMT of -191.67 dBc/Hz.It is implemented in a 22 nm FD-SOI technology, and the occupied area is 196 × 469 μm 2 .

  Unfortunately, this design suffered from large interconnect parasitic capacitances introduced by the large size of the fine-tuning bank. Despite a series of layout optimization efforts, its performances were still far from meeting the specification requirements. Therefore, in Section III.3, we proposed an alternative version of the D-DCO. The issues such as large parasitic capacitances were well addressed by using customized tiny MOM capacitors. Post-layout simulation results show that this version of the D-DCO almost meets the design specifications. III.5. Résumé du Chapitre III Dans le Chapitre III, nous avons étudié une architecture alternative d'OCN dédié aux radars automobiles FMCW. En effet, l'intégration d'un OCN conventionnel basé sur une structure à multiples banques de capacités commutées (plus de trois banques, similaire au T-OCN) dans une ADPLL s'avère complexe à mettre en oeuvre car la génération d'un chirp linéaire avec une bande supérieure à 1 GHz nécessite un processus complexe et long d'étalonnage et de linéarisation du gain de l'OCN. Dans le cas d'un étalonnage, les résultats doivent être stockés en mémoire et l'étalonnage doit être répété périodiquement pour compenser les variations du PVT. Par conséquent, nous avons proposé un prototype d'OCN à seulement deux banques de capacités commutées (D-OCN) qui peut résoudre les problèmes susmentionnés au niveau « hard » plutôt qu'au niveau « soft », et, à notre connaissance, pratiquement aucun OCN de ce type n'a été publié jusqu'à présent. Ainsi, dans la Section III.1, nous avons d'abord décrit brièvement le D-OCN en bande K proposé pour répondre aux spécifications requises. Alors que la banque de réglage grossier n'est encore utilisée que pour compenser les variations de PVT, la génération d'un chirp linéaire repose entièrement sur une seule banque de réglage fin du D-OCN, ce qui signifie que le problème de chevauchement de fréquence n'existe plus, réduisant ainsi significativement la complexité de l'algorithme d'étalonnage.

  design. Meanwhile, compromises must be made in DCO design, such as phase noise, power consumption, and frequency tuning range. According to the specifications, the phase noise of the DCO should be extremely low, reaching about -115 dBc/Hz at 1MHz frequency offset from a carrier frequency of about 20 GHz, the frequency-tuning range should be about 20 % with a frequency resolution as low as 2.5 MHz, and the requirement to operate under high-temperature conditions should also be met, which are the mostRésuméLes radars à ondes millimétriques sont indispensables dans la réalisation de fonctions de sécurité des véhicules et pour la conduite autonome, ce qui en fait l'un des domaines de recherche les plus en vogue actuellement. L'objectif principal de cette thèse est de mettre en oeuvre un oscillateur à commande numérique (OCN) en bande K à faible bruit de phase avec une large bande d'accord en fréquence de plus de 20 % pour une boucle à verrouillage de phase entièrement numérique (ADPLL en anglais), qui sera ensuite appliquée aux radars automobiles à ondes continues modulées en fréquence (FMCW en anglais) de 76 à 81 GHz. Deux solutions différentes sont proposées. La première est un OCN à triple banques de capacités commutées (T-OCN), dont la banque de réglage grossier est principalement utilisée pour compenser les variations de PVT, tandis que les banques de réglage moyen et fin permettent de couvrir la largeur de bande de fréquence désirée, nécessitant ainsi un chevauchement des fréquences de plus de 15 % comme dans les OCN conventionnels. En outre, grâce à la nouvelle architecture de réglage fin proposée et basée sur la polarisation de la grille arrière, le T-OCN permet d'obtenir une résolution de fréquence fine de 1.38 MHz à une fréquence porteuse d'environ 20 GHz. Le second est un OCN à double banque (D-OCN), qui s'appuie uniquement sur une banque de réglage fin à grand nombre d'éléments contrôlée sur 10-bit afin de générer des signaux modulés en fréquence. Cette approche originale nous permet de nous affranchir du problème de chevauchement et de calibration de la fréquence indispensable dans le cas des OCNs à plusieurs banques (plus de trois banques de réglage de fréquence, similaire au T-OCN), le rendant ainsi plus adapté à une utilisation dans le domaine des radars automobiles FMCW. Parallèlement, le D-OCN permet d'obtenir une résolution de fréquence fine de 2.1 MHz et une plage de réglage fin de 2 GHz en utilisant une nouvelle capacité MOM personnalisée de 973 aF. De plus, le T-OCN et le D-OCN sont tous les deux implémentés en technologie 22 nm FD-SOI, ce qui permet d'atteindre des performances en bruit de phase à l'état de l'art et inférieures à -110 dBc/Hz à 1 MHz de la porteuse sur l'ensemble de la plage de fréquences.

Table I .1.2 Comparison of sensors in ADAS.

 I

Table I .1.3

 I Automotive radar characteristics in 76 -81 GHz frequency band.

dB beamwidth azimuth ±15°±40°±80°3 dB beamwidth elevation ±5°±5°±10° I.1.3. Technologies Trends in Automotive Radar

	This section provides an overview of semiconductor technologies applicable to mm-
	Wave automotive radars operating in the frequency band of 76 -81 GHz [I-28]-[I-30].
	Historically, semiconductors have evolved for three generations. The first generation of
	semiconductors was mainly based on silicon and germanium, such as the conventional
	CMOS process. Their early development followed Moore's law, and the technology was
	Type relatively mature and widely used in large-scale integrated circuits. However, at deep LRR MRR SRR
	Frequency band nanometer nodes, silicon processes are becoming increasingly crucial in RF and mm-76 -77 GHz 77 -81 GHz 77 -81 GHz
	Maximum transmit power (EIRP) Bandwidth Wave circuits. Second-and third-generation semiconductors are mainly based on III-V 55 dBm 33 dBm 33 dBm 600 MHz 600 MHz 4 GHz
	Distance range compounds. Compared to first-generation semiconductors, they feature superior high-10 -250 m 1 -100 m 0.15 -30 m
	Distance resolution temperature and high-frequency performances. Second-generation semiconductors, such 0.5 m 0.5 m 0.1 m
	Distance accuracy as gallium arsenide (GaAs) and indium phosphide (InP), are widely used in optoelectronic 0.1 m 0.1 m 0.02 m
	Velocity resolution Velocity accuracy and wireless communication devices. The prominent representatives of the third-0.6 m/s 0.6 m/s 0.6 m/s 0.1 m/s 0.1 m/s 0.1 m/s
	Angular accurary generation semiconductors are gallium nitride (GaN) and silicon-carbide (SiC), which 0.1°0.5°1°3
	offer tremendous advantages in high-frequency and high-power scenarios such as 5G and
	electric vehicles. However, they are still in their infancy.
	A comparison of the approximate unit gain cut-off frequencies (fT) achieved by these
	semiconductor technologies is given in Table I.1.4. In general, the maximum frequency
	of oscillation (fmax) is much higher than fT. Considering that the maximum operating
	frequency in RF circuit design should be one-half to one-third of fT, it can be concluded
	that all these

advanced processes can support 76 -81 GHz automotive radars due to the high fT of over 250 GHz. Table I.1.4 Cutoff frequencies for various semiconductor technologies.

	making them suitable for high-performance mm-Wave applications such as PAs and
	LNAs, as well as enabling oscillators with excellent phase noise properties. However, the
	GaAs process has some inherent disadvantages, such as the high difficulty of wafer
	fabrication and few available metal layers, resulting in high cost and low integration for
	early mm-Wave radars. Since the chip is the product of a trade-off between performance,
	cost and benefit, this determines that GaAs will not replace silicon as the dominant
	semiconductor material.
	The emergence of silicon-germanium (SiGe) process can be dated back to 1980, IBM
	doped germanium into silicon material in order to increase the flow rate of electrons and
	reduce power consumption. Starting in 1998, IBM officially announced that the SiGe
	process was in mass production. A significant advantage of the SiGe process is that it is
	highly compatible with the mature silicon process. It not only has the integration and cost
	advantages of the silicon process, but also has the advantages of the GaAs process in
	terms of speed. Since about 2007, mm-Wave radars have officially entered the SiGe era,
	and its cost has dropped about 50% compared to that of the GaAs process. In addition,
	the SiGe BiCMOS process, which combines the high-speed and high-gain characteristics
	of bipolar transistors, can integrate RF, analog and digital circuits on a single chip,
	significantly reducing the number of external components while optimizing power
	consumption. Currently, 0.13 μm SiGe transistors with fT and fmax in excess of 250 GHz
	occupy a pivotal position in the automotive radar market.
	Figure I.1.13 compares the fT and fmax of SiGe BiCMOS [I-31]-[I-37] and CMOS
	processes [I-38]-[I-46] at different nodes. It can be seen that under 0.18 µm process, the
	fT of SiGe BiCMOS process is about 250 GHz, the fT of CMOS process is about 60 GHz.
	Process GaAs mHEMT	GaN HEMT	InP HBT	SiGe HBT	RF CMOS 45 nm
	f T	1000 GHz	300 GHz	500 GHz	250 GHz	400 GHz
	However, like other mm-Wave integrated circuits (ICs), the mm-Wave radars were
	previously dominated by III-V compound semiconductors (primarily GaAs). For example,
	Mercedes-Benz's first commercially available 77 GHz automotive radar utilized GaAs
	Gunn diodes embedded in a waveguide cavity as the mm-Wave signal source. Compared
	to silicon semiconductors, III-V compound semiconductors have shown some superior
	electrical characteristics, such as high electron mobility and low resistive parasitic, thus
				-23 -

1.4. Examples of 76 -81 GHz FMCW Automotive Radars In

  the bibliography, there are a number of researches on automotive radar systems. In this section, several representative papers from academic and commercial fields are cited to introduce the current progress in this field.

	600 planar FD-SOI technology. Its 3D gate resembles a fish fin surrounding the channel
	0.25 μm 0.18 μm 0.13 μm 90 nm 0.18 μm 0.13 μm 90 nm 65 nm and thus provides better control. This structure can significantly reduce the leakage 55 nm 45 nm
	500 current and also significantly shorten the gate length of the transistor, such as the 28 nm 22 nm 14 nm SiGe BiCMOS
	400 14/16 nm nodes commonly used today. However, the fT and fmax of FinFET is lower
	300 than those of FD-SOI, so the FinFET process currently lacks sufficient attractiveness (GHz) in mm-Wave radars.
	f Max
	200
				CMOS: Bulk / SOI / FinFET
	100
	0
	0	50	100	150	200	250	300	350	400
					f T (GHz)
					-25 -

I.

I.

1.4.1. Academic Works I.1.4.1.1. J. Lee et al., 2010 [I-47] Figure I.1.14 Schematic of the fully integrated 77 GHz FMCW radar transceiver in 65 nm CMOS technology.

	extracted. Moreover, the 77 GHz VCO utilizes a standard LC resonant structure with a
	thick-oxide (5.6 nm) varactor to suppress the leakage, and the frequency tuning range is
	about 1 GHz. The mm-Wave PA and LNA are integrated on the chip to improve the
	emitting power and the receiving sensitivity. The implementation of this radar transceiver
	is based on TSMC's 65 nm CMOS process with a chip area of 0.95 × 1.1 mm 2 , and it
	consumes 243 mW from a 1.2 V supply voltage.
	I.1
	This research work from National Taiwan University was published in 2010. A 77
	GHz fully integrated FMCW automotive radar system is proposed, and it is also one of
	the first monolithic microwave integrated circuit (MMIC) to integrate the entire radar
	transceiver. As illustrated in Figure I.1.14, the transmitter utilizes an analog fractional-N
	frequency synthesizer to generate the triangularly FMCW signal, while the reference of
	this frequency synthesizer is set to 700 MHz, which is provided by an external 50 MHz
	crystal oscillator-based PLL. The received signal is processed by an external FPGA-based
	signal processor and the corresponding speed and distance information can then be

.4.1.2. H. Jia et al., 2016

	[I-48]
	This research work from Tsinghua University was published in 2016. The simplified
	schematic of this 77 GHz fully integrated frequency doubling two-path phased-array
	FMCW transceiver is given in Figure I.1.15. Compared with the previous one, the output
	frequency (triangular wave) of this analog fractional-N frequency synthesizer is reduced
	to about 38.5 GHz, and 77 GHz is achieved by a frequency doubling circuit, which not

Table I .1.5

 I Performance summary of 76 -81 GHz automotive radars

						TX		RX
	Reference Technology	FMCW Generator	Frequency (GHz)	P OUT (dBm)	PN @1MHz (dBc/Hz)	Gain (dB)	NF (dB)	Area (mm 2 )	Power Consumption (W)
	[I-47] JSSC 2010	65 nm CMOS	Fractional-N PLL	77	5.1	-85.53	38.7	7.4 @1MHz	1.04	0.243
	[I-53] JSSC 2010	90 nm CMOS	Fractional-N PLL	77	-2.8	-85	23.1	15.6	6.83	0.416
	[I-54] TCAS-I 2013	65 nm CMOS	Fractional-N PLL	77	6.4	-85	23	14.8 @1MHz	0.97	0.275
	[I-55] TMTT 2015	65 nm CMOS	External PLL	77	8.9	-97.6	13	7.95 @1MHz	2.56	0.468
	[I-56] TMTT 2015	65 nm CMOS	Fractional-N PLL	76 -81	3	-83.43	-	-	2.74	0.32
	[I-48] JSSC 2016	65 nm CMOS	Fractional-N PLL	77	13	-81	47.8 -100.7	5.04 @3.3MHz	4.64	0.343
	[I-57] JSSC 2017	0.13 μm SiGe	External PLL	76 -81	17	-99	15	10 @1MHz	12.7	1.8
	[I-58] ASSCC 2017	28 nm CMOS	Integer-N PLL	79	8.5	-85	45	12 @100MHz	7.9	1
	[I-59] ISSCC 2018	45 nm CMOS	Fractional-N PLL	76 -81	10.8	-94	-	18 @1MHz	22	3.4
	[I-49] JSSC 2020	65 nm CMOS	Mixed-mode PLL	76 -81	13.4	-87.4	26.2 -78.8	15.3 @600kHz	7.29	0.921
	[I-51] RFIC 2020	40 nm CMOS	Fractional-N PLL	76 -77	11 -14.1	-91	-	8.7 -14 @10MHz	46.2	-
	[I-60] TCAS-I 2021	65 nm CMOS	Fractional-N PLL	76 -81	0	-	18 -66	11 -26	14.5	0.52
	[I-61] EuRAD 2021	22 nm FD-SOI	ADPLL	78	7 -11	-	16	14.5	14	0.7

  Meanwhile, power supply noise and substrate noise as common-mode noise can further deteriorate the phase noise performances, because this single MOS structure does not provide a way to eliminate common mode noise. Furthermore, the Colpitts oscillator cannot generate the differential signals required for high-performance transceivers, which greatly limits its application.As an alternative, two Colpitts oscillators can be interconnected to form a differential Colpitts oscillator, reducing the requirement for high transconductance of a single transistor, but also losing simplicity, which is the most important advantage of a single MOS structure. More details can be found in[I-17].

  Leeson's model, several more refined models have been proposed, among which the Rael's model takes into account the contributions of the LC resonant tank, cross-coupled pair and bias current source to the phase noise, which is more instructive for our design. The formula is given by

	𝐿{∆𝜔} = 10 𝑙𝑜𝑔 [ 2𝐹(∆𝑓) 𝑇 𝑃 𝑠	( 2𝑄 𝐿 ∆𝜔 𝜔 0	2 )	]	(I. 3. 25)
	It can be observed that this phase noise model is identical to the Leeson's model in the
	1 𝑓 2 ⁄ region, but the factor 𝐹(∆𝑓) is determined by [I-80]
	𝐹(∆𝑓) = 1 +	2𝛾𝐼 𝑏𝑖𝑎𝑠 𝑅 𝑃 𝜋𝐴	+	4 9	𝛾𝑔 𝑚,𝑏𝑖𝑎𝑠 𝑅 𝑃	(I. 3. 26)

  Le Chapitre I présente le contexte des travaux de recherche et traite des radars automobiles, des techniques de synthèse de fréquence et des oscillateurs, qui constituent la base théorique des Oscillateurs à Commande Numérique (OCN) dont l'analyse et la conception sont proposés dans ce mémoire. celle-ci et en recevant le signal de l'écho. Par conséquent, les caractéristiques des ondes électromagnétiques utilisées, principalement la bande de fréquence, déterminent les performances et les applications du radar. La relation entre les principaux paramètres du radar (puissance d'émission, gain d'antenne, etc.), la portée notamment la synthèse de fréquence analogique directe, la synthèse de fréquence numérique directe et la boucle à verrouillage de phase. Elles peuvent toutes être utilisées afin de délivrer un signal stable avec une pureté spectrale élevée. Cependant, pour les applications supérieures à 10 GHz, la PLL est préférée en raison de fréquence élevée du signal de sortie et de son faible bruit de phase, etc.

	détectée et les caractéristiques de la cible peuvent être décrites quantitativement par
	l'équation du radar. En outre, il existe différents types de radars, mais, quelle que soit la Actuellement, les PLLs analogiques sont encore les plus courantes dans les applications
	catégorie de radar étudié, celui-ci est inévitablement constitué d'un système émetteur-industrielles, bien que les boucles à verrouillage de phase entièrement numérique
	récepteur, servant de lien entre le processeur de traitement de signal numérique et (ADPLL en anglais) les remplacent progressivement dans certains domaines en raison de
	l'antenne. Les émetteurs basés sur la boucle à verrouillage de phase (PLL en anglais) sont leurs avantages en matière d'intégration, de reconfigurabilité et de stabilité. Les modules
	souvent utilisés dans les radars à ondes continues modulées en fréquence (FMCW en de base d'une ADPLL sont presque tous implémentés en utilisant des circuits numériques,
	germanium (SiGe) sont ensuite devenus populaires car ils sont hautement compatibles
	avec les process silicium matures et présentent non seulement les avantages des process
	silicium en termes d'intégration et de coût, mais aussi les avantages du GaAs en termes
	de réponse en fréquence. Ces dernières années, grâce à la maturation progressive des
	process CMOS à l'échelle nanométrique, en particulier le process FD-SOI (Fully
	Depleted Silicon-On-Insulator en anglais), il est ainsi devenu possible de mettre en oeuvre
	un radar automobile à ondes millimétriques entièrement intégré en technologie CMOS,

Dans la Section I.1, nous avons d'abord étudié les principes de base du radar, lequel permet la détection d'une cible

(distance, vitesse, caractéristiques, etc.)

en émettant des ondes électromagnétiques vers anglais) pour obtenir un chirp linéaire. Les structures hétérodynes et superhétérodynes classiques sont également couramment utilisées dans les systèmes émetteurs-récepteurs et il est utile de préciser que l'Oscillateur Contrôlé en Tension (OCT) joue un rôle primordial dans ces dispositifs. Par ailleurs, le développement de technologies de conduite autonome dépend fortement des capteurs, en particulier dans les véhicules autonomes de niveau trois et supérieur, dont le plus représentatif est le radar automobile. Les bandes de fréquences actuellement les plus utilisées pour les radars automobiles sont la bande étroite de 76 à 77 GHz et la bande ultra-large de 77 à 81 GHz, lesquelles conviennent respectivement aux radars à longue portée avec une distance de détection d'environ 250 mètres et aux radars à courte portée avec une distance de détection inférieure à 30 mètres. Le développement de technologies de radars pour des applications automobiles à ondes millimétriques a traversé trois phases principales. Initialement, il était dominé par les semi-conducteurs composés III-V, surtout l'arséniure de gallium (GaAs), mais avec une faible intégration et un coût élevé. Les alliages siliciumce qui a suscité une grande attention de la part du milieu universitaire et de l'industrie. Dans la Section I.2, nous avons présenté trois techniques de synthèse de fréquence -67 -couramment utilisées, tels que le TDC (Time-to-Digital Converter en anglais), le filtre numérique de boucle, le diviseur de fréquence. L'OCN est, quant à lui, un circuit à signaux mixtes. Néanmoins, comme son entrée et sa sortie peuvent être représentées sous forme de signaux numériques, il peut aussi être considéré comme "entièrement numérique". Finalement, dans la Section I.3, nous avons présenté les principes de base des oscillateurs. Nous avons notamment exposé trois topologies d'oscillateurs typiques. Par rapport aux oscillateurs en anneau et aux oscillateurs Colpitts, les oscillateurs à résonateur LC et à simple paire croisée différentiels sont la structure la plus utilisée dans les circuits radiofréquences en raison de leur simplicité et de leurs performances en termes de bruit de phase. Nous avons également présenté les principales sources de bruit dans les oscillateurs, notamment le bruit thermique, le bruit de scintillement et le bruit de grenaille. Enfin, nous avons présenté le modèle linéaire invariant dans le temps de Leeson et le modèle linéaire variant dans le temps de Hajimiri pour analyser et comprendre les performances en bruit de phase des oscillateurs.

Table II .

 II

1.1 Supported EDA Tool Versions.

II.2.1. From VCO to DCO

		1.2E-04
	[A]	1.0E-04
	I D	8.0E-05
	Current	6.0E-05
	Drain	2.0E-05 4.0E-05
		0.0E+00
		0	0.1	0.2	0.3	0.4	0.5	0.6	0.7	0.8
					Gate Voltage [V]
	Most oscillators, such as VCOs, require tunable oscillation frequencies within a
	certain range in order to achieve channel selection, frequency modulation, or frequency
	compensation. Figure II.2.1 illustrates a simplified structure of a typical cross-coupled
	LC-based VCO using a MOS varactor and its frequency-voltage (F-V) characteristic
	curve. When the control voltage Vctrl applied to the analog MOS varactor is gradually
	increased from V1 to V2, the oscillation frequency gradually changes from f1 to f2. The
	slope of the curve KVCO represents the gain of the VCO, and the output frequency fVCO
	can then be expressed as
			𝑓 𝑉𝐶𝑂 = 𝑓 0 + 𝐾 𝑉𝐶𝑂 𝑉 𝑐𝑡𝑟𝑙			(II. 2. 1)

where f0 represents the frequency at the intersection point of the F-V extension line and

  𝑃 and 𝐶 0 represent the total non-adjustable capacitance of the PVT bank and the acquisition bank, 𝑁 𝑃 and 𝑁 are the number of binary-weighted switched capacitors, 𝑘 ̅̅̅ 𝑇 is the inverted tracking bits, and ∆𝐶 𝑇 represents the capacitance difference of one switched capacitor in the tracking bank. Considering the fixed capacitance 𝐶 0,𝑡𝑜𝑡 in Figure II.3.3, the total capacitance of the LC tank is given by In addition, it should be noted that at any given time, only switched capacitors belonging to the same capacitor bank are allowed to switch, while the digital control words of the other two banks are in the locked state. Moreover, the high-speed dithering technique is used for the fractional operation, the capacitance of the smallest switched capacitor (tracking bank) alternates between the low capacitance and high capacitance several times during the one reference cycle, thus leading to a fractional multiple of its capacitance difference ∆𝐶 𝑇 . Meanwhile, the issue of spurs generated by the periodic dithering is addressed by the Σ∆ modulation. The implementation of this 2.4 GHz DCO is based on a 0.13 μm CMOS process, and it achieves a large frequency tuning range of 500 MHz and consumes 2.3 mW from a 1.5 V supply voltage. The phase noise is -112 dBc/Hz at 500 kHz frequency offset.

		• ∆𝐶 𝑃 • 2 𝑘	(II. 3. 7)
	𝑁 𝐴 -1
	𝐶 = 𝐶 0 + ∑ 𝑘 ̅̅̅	• ∆𝐶 • 2 𝑘	(II. 3. 8)
	𝑘=0
	where 𝐶 0
	𝑁 𝑇 -1
	𝐶 𝑇 = 𝐶 0 𝑇 + ∑ 𝑘 ̅̅̅ 𝑇	• ∆𝐶 𝑇	(II. 3. 9)
	𝑘=0
	where 𝐶 0
	𝐶 = 𝐶 0,𝑡𝑜𝑡 + 𝐶 𝑃 + 𝐶 + 𝐶 𝑇	(II. 3. 10)

𝑘

̅̅̅

𝑃

and 𝑘 ̅̅̅ are the inverted PVT and acquisition bits, and ∆𝐶 𝑃 and ∆𝐶 represent the capacitance difference of the basic unit.

Furthermore, during the actual transmission and reception, the tracking bank is used to precisely regulate the oscillation frequency with a fairly high frequency resolution, thereby employing the unit-weighted structure controlled by thermometer codes, which means all switched capacitors in this bank are identical. Thus, the total capacitance is 𝑇 represents the total non-adjustable capacitance, 𝑁 𝑇 is the number of unitweighted switched capacitors,

Table II .3.1

 II Performances summary of LC-based DCOs. Not many K-band and mm-W DCOs have been disclosed. The multi-stage (more than 3) switched-capacitor structure can still be used in K-band DCOs, as in [II-26], [II-38].However, it is necessary to carefully set the inductance and capacitance values of the LC tank. The aforementioned DiCAD technique is usually employed in mm-W DCOs, e.g., a multi-stage frequency-tuning structure using the DiCAD technique is applied in.

	Reference	Technology	Frequency (GHz)	FTR	∆C fine	∆F fine	Phase Noise (dBc/Hz)	P DC (mW)	Voltage (V)
	[II-4] TMTT 2003	0.13 μm	2.4	23%	38 aF	23 kHz	-112 @500kHz	3.45	1.5
	[II-34] JSSC 2005	90 nm	3.6	25%	50 aF	12 kHz	-165 @20MHz	25.2	1.4
	[II-35] ISSCC 2006	65 nm	10	10%	55 aF	1.03 MHz	-102 @1MHz	3.3	1.1
	[II-11] ISCAS 2007	0.18 μm	3.8	26%	21 aF	20 kHz	-123 @1.2MHz	5.04	1.8
	[II-36] ASSCC 2007	90 nm	3.3	18%	10 aF	5 kHz	-118 @1MHz	2.4	1.2
	[II-13] EL 2008	65 nm	5	20%	0.8 aF	1.4 kHz	-102 @1MHz	2.16	1.2
	[II-12] RFIT 2009	0.18 μm	5.9	10%	28 aF	14 kHz	-117 @1MHz	9.2	1.8
	[II-28] MWSYM 2009	90 nm	58 -64	9.27%	-	1.39 GHz	-90.1 @1MHz	10.6	1.2
	[II-30] JSSC 2013	90 nm	60	9.75%	50 aF	2.5 MHz	-94 @1MHz	14	1.2
	[II-32] ESSCIRC 2014	65 nm	3 -4.3	36%	60 aF	3 kHz	-149.5 @10MHz	6.5	0.5
	[II-27] RWS 2017	22 nm	4	35%	20 aF	12 kHz	-122 @1MHz	2.5	1
	[II-37] TCSI 2017	65 nm	54.8 -63.2 14.2%	-	4 Hz	-94.1 @1MHz	15	1.2
	[II-16] EuMIC 2018	28 nm	3.9 -4.7	17%	-	400 kHz	-109.5 @1MHz	0.35	0.8
	[II-23] CICC 2019	28 nm	2.02 -2.87 35%	12 aF	-	-118 @1MHz	0.75	0.3
	[II-38] TVLSI 2019	65 nm	24	29%	-	1.1 MHz	-106 @1MHz	12.8	1.2
	[II-31] TMTT 2019	65 nm	23.7	24.4%	-	187 MHz -106.6 @1MHz	4.8	0.45
	[II-33] TSP 2020	28 nm	2.4	-	4.23 aF	8 kHz	-113 @1MHz	1.5	1
	[II-39] ISCAS 2021	14 nm	14	18%	-	7 kHz	-110 @1MHz	6.3	0.8
	[II-26] LMWC 2021	28 nm	24.4	27.3%	4 aF	150 kHz	-97 @1MHz	1.2	0.65
					-98 -

  Thus, the correspondingly instantaneous frequency is given by

		𝑓 𝑇 (𝑡) =	{ 𝑓 𝐿 + 𝑓 𝐿 +	2𝐵 𝑇 𝑚 2𝐵 𝑇 𝑚	(𝑡 -𝑛𝑇 𝑚 ) (𝑡 -2𝑛𝑇 𝑚 )	(𝑛 + 1)𝑇 𝑚 2 ≤ 𝑡 ≤ 2𝑛𝑇 𝑚 𝑛𝑇 𝑚 ≤ 𝑡 ≤ 2 (𝑛 + 1)𝑇 𝑚	(II. 4. 1)
	where n is a positive integer. The ratio 2B/Tm represents the slope of the chirp and is
	known as the ramp rate or the sweep rate. Assuming that the received signal from a target
	at a distance R has a round-trip time ∆t so that ∆𝑡 = 2𝑅 𝑐 ⁄ , the instantaneous frequency
	of this received signal fR(t) (red line) can be expressed as
	𝑓 𝑅 (𝑡) =	{ 𝑓 𝐿 + 𝑓 𝐿 +	2𝐵 𝑇 𝑚 2𝐵 𝑇 𝑚	(𝑡 -𝑛𝑇 𝑚 -∆𝑡) (𝑡 -2𝑛𝑇 𝑚 -∆𝑡)	𝑛𝑇 𝑚 + ∆𝑡 ≤ 𝑡 ≤ 2 + ∆𝑡 ≤ 𝑡 ≤ 2𝑛𝑇 𝑚 + ∆𝑡 (𝑛 + 1)𝑇 𝑚 + ∆𝑡 2 (𝑛 + 1)𝑇 𝑚	(II. 4. 2)

  Hz over the entire frequency range (i.e., for all codes). Simulated phase noise plot at the minimum frequency of 17.72 GHz, the medium frequency of 19.61 GHz, and the maximum frequency of 22.41 GHz.PN has dropped to -104.4 dBc/Hz at 1 MHz frequency offset. However, this PN degradation can be further compensated by increasing the tail current.

	18 18.5 19 19.5 20 20.5 21 21.5 -170 Frequency [GHz] -150 -130 -110 -50 1.0E+04 0 dBc/Figure II.5.20 Table II.5.4 Post-layout simulated T-DCO performances for the three most 4 8 12 16 20 24 28 32 Coarse-tuning code: CB[4:0] 19.5 19.8 20.1 12 13 14 15 16 (a) 19.55 19.65 19.75 28 29 30 31 32 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Phase Noise Relative Frequency [Hz] 17.72 GHz -90 -70 19.61 GHz [dBc/Hz] 22.41 GHz
	(b) representative PVT configurations
	19.58 19.59 19.6 19.61 19.62 19.63 19.64 T-DCO Configuration Minimum Frequency (CB = 31, MB = 63, FB = 31) [GHz] Medium Frequency (CB = 16, MB = 32, FB = 16) Maximum Frequency (CB = 0, MB = 0, FB = 0) Frequency FTR	19.612 19.616 Typical case 125º, ss, 1.14 V Worst case 27º, tt, 1.2 V 19.608 16.03 GHz 17.72 GHz 17.97 GHz 19.61 GHz 21.06 GHz 22.41 GHz 27.1 % 23.4 %	Best case -25º, ff, 1.26 V 19.77 GHz 21.49 GHz 23.86 GHz 18.7 %
	0 PN@1MHz (CB = 16, MB = 32, FB = 16) 4 8	12	16 -104.4 dBc/Hz 20	24 -112.6 dBc/Hz 28	32 -112 dBc/Hz
	Fine-tuning code: FB[4:0]
	(c) Table II.5.4 summarizes the post-layout simulated T-DCO performances for the three
	most representative PVT configurations: the worst case (125º, ss corner, 1.14 V), the
	typical case (27º, tt corner, 1.2 V), and the best case (-25º, ff corner, 1.26 V). Compared
	with the typical case, the medium frequency deviations are 1.64 GHz and 1.88 GHz for
	the worst and best cases, respectively. Fortunately, the coarse-tuning bank with a
	frequency tuning range of 2.67 GHz can fully compensate for these deviations. Moreover,
	the FTR is reduced to 18.7 % for the best case, but it is still sufficient to cover the FMCW
	chirp. In the worst case, the T-DCO suffers from severe voltage swing compression,
	leading to substantial degradation of the PN. At the medium frequency of 17.97 GHz, the
		-125 --126 -

Table II .5.6

 II Comparison with state-of-the-art K-band DCOs MHz frequency offset, allowing a wide FTR of more than 20 % simultaneously. Furthermore, the T-DCO consumes about 24 mW from a 1.2 V supply voltage, leading to a FoM of -184.65 dBc/Hz and a FoMT of -192.03 dBc/Hz. It is implemented in a 22 nm FD-SOI technology, and the occupied area is 201×302 µm 2 .

	Reference	Technology	Frequency [GHz]	FTR [%]	P DC [mW]	PN [dBc/Hz] c	FoM [dBc/Hz] c	c [dBc/Hz] FoM T
	a LMWC 2021 [II-26]	28 nm	24.4	27.2	1.2	-97	-184	-193
	a JSSC 2018 [II-49]	28 nm	27.3		14	12	-106	-184	-187
	a TMTT 2019 [II-31]	65 nm	23.7	24.4	4.8	-106.6	-187.2	-194.9
	b TVLSI 2019 [II-38]	65 nm	24		29	16.9	-104	-179	-188
	a JSSC 2018 [II-59]	65 nm	24.6		17	10	-102	-180	-184
	This Work	b	22 nm	19.61	23.4	24	-112.6	-184.65	-192.03
	a : measured results;	b : post-layout simulation results;	c : @ ∆f = 1MHz
	II.5.7. Summary
	The proposed T-DCO achieves a wide FTR of 23.4 % and a low PN of -112.6 dBc/Hz
	at the medium frequency of 19.61 GHz. The novel back-gate-based fine-tuning bank
	allows a fine frequency resolution of ~1.38 MHz. Moreover, a frequency overlap of more
	than 15 % between the medium-tuning and fine-tuning banks allows for constructing a
	linear FMCW chirp with a frequency range of approximately 1.84 GHz. In the typical
	case, the T-DCO achieves a best-in-class PN lower than -110 dBc/Hz over the entire
	frequency range at 1

Table III .2.2

 III Truth table of the digital control block.

		Digital control block
	Thermometer Decoder		C(i) C(i+1)
	Decoder
	Thermometer	N 8	EN M	N 9
	III.2.1.4. LC Resonant Tank
	The minimum, medium, and maximum resonant frequencies of the LC tank and the
	corresponding equivalent parallel resistance RP are plotted in Figure III.2.6. It can be seen

that the RP increases with the resonant frequency. Thus, the minimum RP occurs at the lowest resonant frequency of 17.9 GHz (CB = 15, FB = 961, meaning that all 15 coarsetuning units and 961 fine-tuning units are on), which is about 133.5 Ω. According to the

  The differential output oscillation waveforms (VP and VN, transient simulation) of the D-DCO.1 at medium frequency f0 (CB = 8, FB = 481) are shown in Figure III.2.7.

	the ideal value of 12 mA.
		250
					Minimum Frequency
		200			Medium Frequency
	Resistance [Ω]	100 150			Maximum Frequency
		50
		0
		15 16.5 18 19.5 21 22.5 24 25.5 27 28.5 30
				Resonant Frequency [GHz]
			Table III.2.3 DC operating points of the transistors N1-4.
	Parameters	id	vth	vds	vgs	gm
	N 1-2	5.964 mA	485.3 mV	909.3 mV	913.4 mV	23.35 mS
	N 3	1 mA	518.2 mV	694.1 mV	694.1 mV	10.26 mS
	N 4	11.93 mA	518.6 mV	283 mV	694.1 mV	122.4 mS
	Before determining the frequency-code characteristic curves of the D-DCO.1, the DC
	analysis is required to determine the cross-coupled pair's transconductance value and the
	operating state of transistor N4 in the current mirror. The transistor N4 has to be biased in
	the flat saturation region to provide a stable tail current. When CB = 8 and FB = 481, the
	main parameters of the DC operating points of transistors N1-4 are shown in Table III.2.3.
	It can be seen that the single-side transistors of the cross-coupled pair provides a
	transconductance of 23.35 mS and its threshold voltage is 485.3 mV. In addition, since
	the drain-source voltage of transistor N4 is larger than its overdrive voltage, it is well
	biased in the saturation region, and its drain current is 11.93 mA, which is very close to
				-145 -

  Pre-layout simulated PN at the minimum frequency of 17.73 GHz, the medium frequency of 19.68 GHz, and the maximum frequency of 22.37 GHz. Moreover, when the fine-tuning code is set to 481, the PN variations versus the coarse-tuning codes are shown in Figure III.2.11. It can be seen that the PN variations at 10 kHz frequency offset are lower than 1.5 dB, while the PN is almost unchanged (less than 0.3 dB variations) at 100 kHz, 1 MHz, and 10 MHz frequency offsets. When the coarse-tuning code is set to 8, the PN variations versus the fine-tuning codes are shown in Figure III.2.12. It can be noted that the PN variations for all the fine-tuning codes are less than 1 dB, which is very useful for achieving wide modulation bands.

			PN @10kHz				PN @100kHz
	-69.5						-94.7
	-70						-94.8
	-70.5						-94.9
	-71						-95
	-71.5						-95.1
		0	4	8	12	16	0	4	8	12
		-60	-61.7294 PN @1MHz				PN @10MHz
	-116.05 -116 [dBc/Hz] -115.95	-70.3258 -100 -80	-94.9994 -89.8895	-136.2 -136.15 -136.1	19.68 GHz 22.37 GHz 17.73 GHz
	-116.1 Noise -116.15 Phase	-160 -140 -120 0	4	8	12	16	-116.092 -114.508 -136.25 -136.3 0	-136.241 -135.699 4 8	-156.123 -156.094 12
		-180
		1.0E+04	1.0E+05		1.0E+06	1.0E+07		1.0E+08
					Relative Frequency [Hz]
						-148 -

Figure III.2.11 PN variations versus the coarse-tuning codes.

Figure III.2.12 PN variations versus the fine-tuning codes.

Table III .

 III 2.4 D-DCO.1 performances vs DCO specifications

  The total size of such a fine-tuning unit is 29.148 µm × 23.01 µm.

			DCO Specifications		D-DCO.1 Performances
	Parameters							Units
		Minimum Typical Maximum Minimum Typical Maximum
	temperature	-25°125°-40°140°d
	vdd		0.8			1.2		V
	avdd_reg	0.85	0.9	0.95	1.14	1.2	1.26	V
	ibias_prog		4					bits
	icc_on			60		12		mA
	icc_off			1				mA
	frequency	19	20.25	17.73	19.68	22.37	GHz
	supply voltage		1			1.2		V
	coarse step		200			126		MHz
	fine step		2.5			2.72		MHz
	chirp range		2.5			2.61		GHz
			-115			-116.1		dBc/Hz
	phase noise		-135			-136.2		dBc/Hz
			-155			-156.1		dBc/Hz
	Ton		50					ns
				-152 -

  .2.5. One can see that such a fine-tuning unit achieves a capacitance ratio of 762 aF/602 aF and a Q-factor ratio of 72/88. The 10-bit fine-tuning bank achieves a capacitance ratio of 1.37 pF/1.2 pF, and its Q-factor ratio deteriorates to 14.5/17.8 due to the large interconnect parasitic

resistances. Apparently, the total capacitance value of the fine-tuning bank still remains too high, making it difficult for the D.DCO.1 to oscillate near 20 GHz. Furthermore, it is impossible to achieve low phase noise performances by such poor Q-factors of the finetuning bank.

Table III.2.5 Post-layout simulation results with RC extraction of the new fine-tuning

unit and the new 10-bit fine-tuning bank with 31 × 31 fine-tuning units.

  To verify this point, another resized fine-tuning bank containing 20 × 20 fine-tuning units is simulated and analyzed, as shown in Figure III.2.21, its total area is 179 µm × 134 µm. The post-layout simulation results are given in TableIII.2.6. The Cwire of this resized fine-tuning bank is calculated to be approximately 196.2 fF, which indicates that the interconnect parasitic capacitance Cwire can be reduced by minimizing the layout area. Therefore, a more compact finetuning bank is required for a K-band D-DCO design, which means that the layout area of the fine-tuning unit in Figure III.2.19 needs to be further reduced. This will be one of the critical points in the next Section.

	μm
	134
			179 μm
	Table III.2.6 Post-layout simulation results of the new resized fine-tuning bank.
	Parameters	C ON	C OFF	∆C	Q ON	Q OFF
	Fine-tuning bank (20 × 20) 501 fF	432 fF	69 fF	50	63
			-157 -

Table III .

 III 3.2 DC operating points of the transistors N10-13.When the fine-tuning code is 481, the frequency-code characteristic of the coarsetuning bank is plotted in FigureIII.3.4. The D-DCO.2 oscillates from 24.27 GHz to 21.04 GHz when the coarse-tuning code changes from 0 to 15, resulting in a coarse-tuning range GHz and an average coarse-tuning step of about 215 MHz. Meanwhile, the frequency-tuning step decreases as the oscillation frequency drops, and the maximum frequency step for the lowest code value CB = 0 is about 268 MHz, the minimum frequency step for the highest code value CB = 15 is about 151 MHz.

	of 3.23
	Parameters	id	vth	vds	vgs	gm
	N 10,11	9.964 mA	409.2 mV	831 mV	834.6 mV	38.34 mS
	N 12	2 mA	375.7 mV	553 mV	553.1 mV	20.34 mS
	N 13	19.93 mA	375.8 mV	361.6 mV	553.1 mV	202.6 mS
			-162 -

Table III .3.3

 III Post-layout simulated D-DCO.2 performances for the three most representative PVT configurations. Table III.3.4 compares the post-layout simulated performances of the D-DCO.2 with the specifications. In general, the proposed D-DCO.2 almost meets the design specifications.

	III.3.4. Comparative Study
		-50
					18.37 GHz
	[dBc/Hz]	-90 -70 Table III.3.4 D-DCO.2 performances vs DCO specifications. 20.06 GHz 22.44 GHz
	Noise	-110
	Phase	-150 -130
		-170
		1.0E+04	1.0E+05	1.0E+06	1.0E+07	1.0E+08
			Relative Frequency [Hz]
		D-DCO.2		Worst case	Typical case	Best case
		Configuration		125º, ss, 1.14 V	27º, tt, 1.2 V	-25º, ff, 1.26 V
	Minimum Frequency (CB = 15, FB = 961)	17.29 GHz	18.37 GHz	19.51 GHz
	Medium Frequency (CB = 8, FB = 481)	19.13 GHz	20.04 GHz	21.12 GHz
	Maximum Frequency (CB = 0, FB = 0)	21.5 GHz	22.44 GHz	23.34 GHz
		FTR		21.7 %	20 %	18.3 %
	PN@1MHz (CB = 8, FB = 481)	-109.13 dBc/Hz	-113.04 dBc/Hz	-112.92 dBc/Hz
				-166 -

  FMCW chirp. The trade-off between frequency resolution and FTR, as well as the issue of interconnect parasitic capacitances caused by the large size of the fine-tuning bank, are also well addressed. Subsequently, the D-DCO.2 no longer needs to constantly switch between different switched-capacitor banks to generate linear FMCW chirps. Comparison with the state-of-the-art K-band DCOs.

	DCO Specifications Table III.3.5 Reference Technology Frequency [GHz]	FTR [%]	D-DCO.2 Performances P DC PN c FoM [mW] [dBc/Hz] [dBc/Hz] c	c [dBc/Hz] FoM T
	Parameters a [III-2] LMWC 2021	Minimum Typical Maximum Minimum Typical Maximum 28 nm 24.4 27.2 1.2 -97 -184	Units -193
	temperature vdd a [III-5] JSSC 2018	-25°125°-25°125°d 0.8 28 nm	27.3		14	12	0.8 -106	-184	V -187
	avdd_reg a [III-1] TMTT 2019	0.85 65 nm	0.9	23.7	0.95 24.4	1.14 4.8	1.2 -106.6	1.26 -187.2	V -194.9
	ibias_prog icc_on b [III-3] TVLSI 2019 icc_off a [III-4] JSSC 2018	65 nm 65 nm	4		24 24.6	60 1	29 17	16.9 10	20 -104 -102	-179 -180	bits -188 mA mA -184
	frequency T-DCO b	19 22 nm		19.61	20.25 23.4	18.37 24	20.04 -112.6	22.44 -184.65	GHz -192.03
	supply voltage D-DCO.2 b	22 nm	1	20.06		20	24	1.2 -113.04	-185.64	V -191.67
	coarse step		200				133		MHz
	fine step		2.5					2.1		MHz
	chirp range		2.5					2		GHz
			-115			-113.9	-113	-111.5	dBc/Hz
	phase noise		-135			-134.8	-134.3	-133.4	dBc/Hz
			-155			-155.2	-154.9	-154.3	dBc/Hz
	Ton		50							ns
						-167 -

Acknowledgements

Acknowledgements ........................................................................................................... I List of Figures ................................................................................................................ VII

This research work was carried out within the framework of a collaboration between the research institute of XLIM (UMR 7252, IUT of Angoulême, University of Poitiers)

• FD-SOI devices are more reliable under high-temperature conditions due to less power leakage, which makes them ideal for automotive radar applications. 10M means that the total number of metal layers in this option is 10. The M1 and M2

II.1.3. Device Options in 22FDX Library

II.5.3.2. Parasitic Analysis of MOS Switches

In RF circuits, the parasitic capacitances of MOS transistors play an important role in circuit performances. Before analyzing the switched-capacitor structure, we first need to introduce the parasitic capacitance distribution of MOS transistors.

Figure II.5.6(a) shows the pre-simulation parasitic model of the MOS transistor in 22FDX technology . Because of the overlap between the gate and drain/source regions, when the gate voltage Vgs is applied, the charge accumulates in this overlap region, forming the gate-drain capacitance Cgd and the gate-source capacitance Cgs, which are the main parasitic capacitances of FD-SOI devices. In addition, parasitic capacitances are formed between the gate/drain/source and the substrate of the transistor, which are

Q-factor Capacitance [fF] Control Voltage ENF [V]

CHAPTER III

K-Band Dual-Bank DCO (D-DCO) Design

In the previous chapter, we described the principle of DCOs and introduced the circuit implementation of a K-band T-DCO for 76 -81 GHz FMCW automotive radars. To the best of our knowledge, almost all published DCOs employ a multi-bank (more than three) structure similar to that of the T-DCO, which inevitably leads to a frequency overlap problem and therefore requires complex frequency calibration algorithms to achieve linear FMCW chirps. Therefore, in Section III.1, we will first briefly introduce the proposed K-band dual-bank DCO (D-DCO) to address this issue and meet the required specifications. The implementation of a linear FMCW chirp relies entirely on a single fine-tuning bank in the D-DCO, which means that the problem of frequency overlap no longer exists, leading to a significant reduction in the complexity of the algorithms. In Section III.2 and Section III.3, we will describe in detail the implementation process, the difficulties, and the post-layout simulation results of the proposed D-DCO.

III.1. Introduction to D-DCO

According to the principle of FMCW radar and DCO gain calibration introduced in Section II.4, one can be sure that covering the entire chirp range with a single capacitor bank is the most desirable case since the KDCO of a single bank is approximately constant, which is the mentioned dual-bank DCO (D-DCO) prototype that we will discuss in the following sections, whose circuit implementation is the main objective of this chapter.

Intuitively, this approach avoids frequent switching between multiple switched capacitor banks, leading to a short chirp setup time. Moreover, this approach allows us to address the issue of frequency linearization and calibration in multi-bank DCOs (similar to T-DCO) from the design level rather than only from the algorithm level, thereby making it more suitable for FMCW automotive radars.

Note that the coarse-tuning bank of a D-DCO is not involved in frequency modulation and is only used to compensate for PVT variations. The implementation of the linear chirp depends entirely on the fine-tuning bank, i.e., the fine-tuning bank needs to achieve a large bandwidth of about 2.5 GHz according to the DCO specifications presented in Chapter II (Table II.5.1). Meanwhile, the D-DCO needs to achieve a relatively satisfactory frequency resolution of about 2.5 MHz to reduce quantization noise, meaning that the fine-tuning bank must integrate a large number of fine-tuning units (2.5 GHz 2.5MHz = 1000) to meet the requirements of both large bandwidth and fine frequency resolution, which is the first challenge faced by this design. Meanwhile, the large number of fine-tuning units inevitably introduces enormous parasitic capacitances, making it difficult for the DCO to reach the K-band frequency. As a consequence, a proper design must be done in order to minimize these parasitic capacitances, which is the second challenge faced by this circuit.

III.2. First Version of D-DCO (D-DCO.1)

In this section, we present a D-DCO prototype based on standard components in the process library, called the first version of the D-DCO, named D-DCO.1. tuning unit is similar to that of the coarse-tuning unit of the T-DCO, except that the common source terminal of N6 and N7 is connected to the control terminal ENC through an inverter (Note that this structure was the initial one we proposed, which was later completely abandoned due to the increase in layout area and parasitic capacitance caused by the introduced inverter). Therefore, when the control voltage is 0 V, the common source terminal is biased to a high voltage VDD for better switching off. Moreover, two large tri-metallic APMOM capacitors (3.5 μm/3.5 μm, C1 = 36 fF) are connected in series to achieve a large frequency step. Accordingly, to achieve a favorable Q-factor, three large-size MOS switches (N5- (a) (b)

Control voltage EN C [V] Control voltage EN C [V] Capacitance [F]

Q-factor challenging aspects of the DCO design.

In Chapter I, we introduced the research background from three topics. We first briefly reviewed automotive radars, including the radar fundamentals, autonomous driving technologies, and the selection of frequency bands and processes of automotive radars. Several representative examples of 76 -81 GHz FMCW automotive radars and their performance summaries were also presented. Secondly, we reviewed several different frequency synthesis technologies, focusing on explaining the principles, structures, and advantages and disadvantages of PLL and ADPLL. Finally, we described the operating principles and structure of different types of oscillators, different electronic noise sources, and the effects of these noise sources on oscillators' phase noise performances. These literature reviews are necessary because they not only help us to understand the current status and trends in the field of automotive radar and the necessity of ADPLL research, but also the introduction of oscillator theory greatly contributes to the analysis of DCOs.

In Chapter II, we focused on the circuit design and implementation of the K-band T-DCO. We first provided a brief introduction of the GlobalFoundries' 22 nm FD-SOI process and common types of DCOs. To achieve low phase noise, we ultimately selected an LC-based DCO architecture. We also compared various types of frequency tuning techniques to determine which structures were more suitable for our designs. In addition, considering the DCO specifications, we adopted a conventional multi-stage switchedcapacitor structure, which allows to achieve both a wide frequency-tuning range and a fine frequency resolution with a small number of switched-capacitor units. We also introduced the principle of FMCW radars and existing DCO gain calibration techniques for generating linear chirp signals. Moreover, in the proposed T-DCO prototype, the coarse-tuning tank is mainly used to compensate for PVT variations, while the mediumand fine-tuning banks work together to cover the chirp range. We also proposed a novel back-gate-based fine-tuning structure that allows for a small capacitance step of approximately 63 aF and a fine frequency resolution of about 1.38 MHz around 20 GHz. In Chapter III, we investigated another DCO prototype dedicated to FMCW automotive radars. Indeed, when the modulation bandwidth is wide, it is challenging to integrate a conventional DCO based on a multi-stage (more than three banks, similar to the T-DCO) switched-capacitor structure into an ADPLL, and complex and lengthy DCO gain calibration and linearization are required to obtain a linear frequency-modulated band beyond 1 GHz. In the case of offline calibration, the results must be stored in memory and the calibration must be repeated periodically to compensate for the variations.

Based on these facts, we proposed a D-DCO prototype that allows to address the above issues at the design level rather than only at the algorithm level, and to our knowledge, this prototype has barely been disclosed before. In the proposed D-DCO, the coarsetuning bank is still used only to compensate for PVT variations, while the wide chirp signal relies entirely on the 10-bit fine-tuning bank to be generated. The fine-tuning bank contains 961 fine-tuning units and a novel customized interdigitated MOM capacitor of about 973 aF is used to reduce interconnect parasitic capacitances. Finally, the fine-tuning bank allows to achieve a linear chirp band of about 2 GHz with a fine frequency resolution

Abstract

The millimeter-wave radar is indispensable for realizing vehicle safety and autonomous driving functions, making it one of the current research hotspots. The main objective of this thesis is to implement a K-band low-phase-noise digitally controlled oscillator (DCO) with a frequency tuning range of more than 20 % for an all-digital phaselocked loop (ADPLL), which will be further applied to 76 -81 GHz frequency-modulated