Stéphane Thuries

Éric Tournier

Andreia Cathelin

Sylvain Godet

Member, IEEE Jacques Graffeuil

A 6-GHz Low-Power BiCMOS SiGe:C 0.25 µm Direct Digital Synthesizer

A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This paper discusses the BiCMOS design improvements used for the phase accumulator and the phase-toamplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 µm technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm 2 .

I. INTRODUCTION

A Direct Digital Synthesizer (DDS) [START_REF] Tierney | A digital frequency synthesizer[END_REF] is a very versatile signal generation block, known to have many attractive characteristics among which are fast settling time, possible high frequency resolution, phase and frequency modulation capabilities and large bandwidth. All these features make DDS very attractive for modern microwave telecommunication systems. Although the principle of DDS has been known for many years, it did not get a dominant role in microwave communication systems due to its frequency limitation and/or high power consumption.

The block diagram of the traditional DDS architecture is shown in Fig. 1. It consists of a phase accumulator, a phaseto-amplitude converter (ROM) and a digital-to-analog (D/A) converter. In this paper, we present a fully integrated 6-GHz DDS. This DDS does not only operate at the highest clock frequency on a silicon technology that has been reported to our knowledge, but also demonstrates a considerably reduced power consumption. Two techniques are used in order to achieve theses goals :

• the phase-to-amplitude conversion is performed from an analog triangle-to-sine conversion based on the non-linear transfer function of a bipolar differential pair.

• the digital blocks and particularly the phase accumulator are implemented in a 3-levels merged CMOS/bipolar-ECL logic.

II. DDS ARCHITECTURE

A. Bipolar Differential Pair Phase-to-Amplitude Converter

The proposed DDS 9-bits architecture is based on the idea that the non-linear transfer function of a bipolar differential Manuscript received september, 2006; revised august, 2007. This work was supported by ST Microelectronics.

Stéphane Thuries, Éric Tournier, Sylvain Godet and Jacques Graffeuil are with the LAAS/CNRS research laboratory and with the Paul Sabatier university, Toulouse, 31077, France (email: sthuries@laas.fr; tournier@laas.fr; graffeui@laas.fr). Andreia Cathelin is with ST Microelectronics, Crolles, 38926, France (email: Andreia.Cathelin@st.com) pair can be pertinently used in order to convert a triangle wave into a sine wave [START_REF] Meyer | The differential pair as a trianglesine wave converter[END_REF], [START_REF] Thuries | A DDS-oriented phase-to-amplitude converter using a SiGe:C bipolar transistors differential pair[END_REF]. The DDS resultant architecture is shown in Fig. 2. It consists of a phase accumulator, a complementer, a D/A converter and a bipolar differential pair. The frequency control word (FCW) is repeatedly added to the accumulator contents, generating a digital ramp which represents the instantaneous phase of the output signal. The most significant bit (MSB) is used to decode the half wave symmetry property of the sine wave: the MSB controls a n -1 bits complementer which transforms the phase ramp into a digital triangle. The D/A converter translates this digital triangle into two differential analog ones. Finally, the bipolar differential pair transforms the differential analog triangle into an analog sine wave as shown in Fig. 3. The resistor between the two transistor emitters used in [START_REF] Meyer | The differential pair as a trianglesine wave converter[END_REF] has been safely removed because we use here one collector as a single output.

V dd V in (V) V in V out (V) V out
A i A i B i B i B i B i C i C i R sum R sum A i A i B i B i C i C i C i C i R sum R sum Level 1 Level 2
Level 3

I bias Q 1 M 1 Q 2 M 2

B. BiCMOS Phase Accumulator

Typically the conventional phase accumulator designs that provide the highest speed capability are based on ECL adder [START_REF] Mathew | 2-bit adder: carry and sum logic circuits at 19 GHz clock frequency in InAlAs/InGaAs HBT technology[END_REF], [START_REF] Turner | 4-bit adderaccumulator at 41-GHz clock frequency in InP DHBT technology[END_REF]. These designs are not suitable for wireless telecommunications systems due to their high power consumption and the use of high cost technologies. SiGe BiCMOS technologies are now considered as mid-cost while they provide both high-speed Heterojuntion Bipolar Transistors (HBT) and CMOS transistors. Merged CMOS/Bipolar current switch logic (MCSL) has been suggested [START_REF] Heimsch | Merged CMOS/bipolar current switch logic (MCSL)[END_REF] in order to reduce the adder power consumption. The 3-levels series BiCMOS phase accumulator proposed in this paper consists of a ninebits ripple adder followed by a 9-bits register. In a phase accumulator (Fig. 2) the adder inputs are not used identically: one (A) is used to control the phase increment and the other (B) is connected to the register output. The A input is constant most of the time as long as the output frequency is kept fixed. Then, in order to reduce the supply voltage and the power consumption, the lower level switches (Q 1 , Q 2 ) and the current source (I bias ) from the bipolar adder (Fig. 4 (a)) have been merged into two NMOS (M 1 , M 2 ) controlled current sources (Fig. 4 (b)). These sources are complementary driven according to the adder input. The power consumption for this 3-level, BiNMOS (Bipolar + NMOS) adder versus three-levels bipolar ECL is about 30% less because the V ds voltage needed for the NMOS current source is very low compared to the voltage needed by the bipolar level (V ce min = 0.8 V ) and the current source. This modification does not affect the maximum operating frequency, nor the rejection of supply and process variations. The adder speed is limited by the carry propagation time, so by the level 3 bipolar transistor characteristics.

III. MEASUREMENTS AND RESULTS

The proposed 9-bits DDS with an on chip 8-bits current steering D/A converter has been implemented in ST Microelectronics 0.25 µm BiCMOS SiGe:C process that provide HBT with a F t about 70 GHz. The die microphotograph is shown in Fig. 5. The chip size is 1 × 1 mm 2 with an active circuit size of 600 × 700 µm 2 . It consumes 308 mW and operates from a 2.8 V supply. The DDS chip operates up to a 6 GHz clock frequency and has been probing on wafer. Shown in Fig. 6 is the measured output waveforms at 11.71 MHz corresponding to a frequency clock of 6 GHz with a FCW of 1. Fig. 7 shows the corresponding measured spectrum. The spurious free dynamic range (SFDR) versus FCW for three clock frequency is shown Fig. 8. At clock frequencies of 1 and 3 GHz, the SFDR is better than 31 dBc, and at a clock frequency of 6 GHz, the SFDR is better than 25 dBc for half of the FCW values. The Fig. 9 shows the harmonics level at the bipolar differential pair output versus the input triangle amplitude. This triangle-to-sine conversion provides a good harmonic rejection : -48 dBc, -74 dBc, -60 dBc and -43 dBc for the first, the second, the third and the fourth harmonics respectively.

IV. SUMMARY

In order to push the DDS beyond its traditional limits regarding the maximum operating frequency and power consumption, we have revisited the design of two of its main blocks. Firstly we have substituted an analog differential pair to any ROM-RAM or digital computation block used to convert the phase into amplitude. This drastically saves chip area and power consumption. Moreover, the maximum operating frequency is now only limited by the phase-accumulator speed. Secondly, the traditional four-levels phase accumulators switches and bipolar current sources have been successfully merged into two NMOS current sources: this provides a 3levels design featuring a 30% additional power consumption reduction. The proposed 9-bits DDS has been processed using a 0.25 µm SiGe:C BiCMOS technology and is fully functional with a 308 mW power consumption. To our knowledge this is the first on-silicon DDS supporting a 6 GHz clock frequency. Further improvements should be done on the SFDR which remains a bit high at the full speed.

Fig. 2 .

 2 Fig. 1. Traditional DDS architecture

Fig. 3 .

 3 Fig.3. Triangle-to-sine conversion scheme using a bipolar differential pair

Fig. 4 .

 4 Fig. 4. Bipolar half adder (a) and merged bipolar/NMOS half adder (b)

Fig. 5 .Fig. 6 .

 56 Fig. 5. Microphotograph of the DDS (BDP: Bipolar Differential Pair)

Fig. 7 .F Clk = 1 GHzF Clk = 3 GHzF Clk = 6 GHzFig. 8 .Fig. 9 .

 713689 Fig. 7. DDS output spectrum for F Clk = 6 GHz and F out =11.71 MHz (FCW=1)

ACKNOWLEDGMENT

The authors would like to thank ST Microelectronics for providing the technology.