Leon Strous

Roger Johnson

David Alan Grier

Eds. Doron Swade

Kai Rannenberg

Luís Soares Barbosa

Michael Goedicke

Erich J Neuhold

Ricardo Reis

Steven Furnell

Eunika Mercier-Laurent

Marco Winckler

• David

Alan Grier

Unimagined Futures -ICT Opportunities and Challenges

de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Foreword

IFIPthe International Federation for Information Processingwas founded in 1960 following the first World Computer Congress, and under the auspices of UNESCO. Its aim was to support and advance the work of the then fledging societies dealing with information processing (which we now refer to as information and communication technology, or ICT) and the nascent computing industry.

Today, IFIP is the global federation of ICT societies and associations committed to advancing the professional and socially-responsible application of technology. IFIP's members are national, regional, and international ICT societies. In turn, their members are ICT professionals, practitioners, researchers, academics, educators, and policy-makers, who are focused on: developing and advancing ICT knowledge and expertise; promoting digital equity; educating and enhancing public understanding of technology and its potential (both for good and, occasionally, ill); and increasing professionalism and professional standards.

IFIP is a strong advocate for digital equity ("all of the Internet, for all of the people, all of the time", access to technology for minorities, particularly those in remote areas, and gender equality). Along with its member societies, it works closely with the United Nations and its agencies (UNESCO, ITU, and UNCTAD being the most prominent ones), and many other international bodies, to promote understanding of issues related to technology. It aims to collaborate on solutions to help in the achievement of the United Nations Sustainable Development Goals (SDGs).

IFIP organizes more than 100 events every year to bring together international experts on various ICT-related topics, to share the latest developments, explore possibilities, and to discuss the latest issues of relevance to the ICT profession.

Events, such as the World Computer Congress (WCC)which spawned the creation of IFIP in the first instancebring together thought leaders from across the globe to share their knowledge and expertise and to share information about emerging technology issues and policies. The World IT Forum (WITFOR) is specifically focused on means of enhancing access to technology for developing nations to enable them, and their citizens, to play an active role in the global digital economy.

IFIP's International Professional Practice Partnership (IP3) is the leading group driving professional practice for technologists around the world. It has been responsible for having the importance of professionalism as a key enabler of the SDGs being recognized and discussed at the United Nations General Assembly.

IFIP also seeks to raise awareness and understanding among the wider community about where technology is headed, how it can enhance the quality of all our lives, and how to ensure that all people have equal access and equal opportunity. We must also, of course, be aware that as in the natural sciences, many new technologies that have much potential for good also have potential for harm.

IFIP is uniquely placed to achieve these outcomes through its global network of 13 Technical Committees and more than 130 Working Groups, that bring together experts in different fields in order to share and enhance their knowledge, and to focus attention on key areas related to technology.

IFIP member societies, and their individual members, have access to the largest network of technical expertise in the world. This enables them to make valuable connections, grow their knowledge and skills, and contribute to the development of global insights and standards for ICT and ICT professionals.

This collection is a celebration of IFIP on the occasion of its diamond jubilee. The authors have almost allat some point or othermade significant contributions to IFIP and IFIP member societies, as well as to their own respective technical areas. As a result, they understand both the organization and the issues well. The contributions in this book highlight those developments and challenges that society, in general, and IFIP and other ICT-related societies around the world (including IFIP's own members), in particular, are facing. They consider contributions and developments in a number of key and emerging technical areas and address IFIP's and other ICT societies' important role in policy, professionalism, and professional ethics. These are all significant issues for the ICT industry as it evolves to consider new technologies, new areas of application, and the increasing influence of technology on almost every aspect of our lives. Indeed, as that influence grows, it becomes more of an issue for all of us.

Unimagined Futures: ICT opportunities and challenges reminds us briefly of IFIP's past; it addresses its present context, and its future challenges in a variety of areas. Many of these, of course, are challenges for all of us, and are not unique to IFIP. This excellent collection is written and edited by some of those who know IFIP best. It stands as a record of what the ICT industry-and ICT community as a whole-should be, and can become.

September 2020

Mike Hinchey IFIP President (2016-2022)

Preface

The International Federation for Information Processing (IFIP) was formally established in 1960. Like many organizations it has celebrated its "significant birthdays" with a publication. Looking at a number of examples from different organizations on our bookshelves, most contain two elements in varying proportions -firstly reviewing the progress made since the last birthday volume and secondly looking to the future.

For this volume, the first of two planned 60th anniversary books, IFIP invited experts in different aspects of the contemporary ICT scene to contribute essays from their specialist areas. While addressing the contemporary challenges facing the ICT community today, the book provides the opportunity to look back to help understand the contemporary scene and identify appropriate future responses to them. As such, the book aims to contribute to the ICT community worldwide, as well as IFIP and its member societies, on setting their policy priorities and agendas for the coming decade. We hope to provoke discussion about appropriate responses to the challenges by individuals as well as by national and international bodies including IFIP.

The title Unimagined Futures: ICT opportunities and challenges reflects the fact there were many futures in the past that happened without our having envisaged them, and there are multiple futures that we now speculate about. Often the way things turned out exceeded our wildest imaginings and we can be sure that this will be no different for things to come.

In a conversation with Eunika Mercier-Laurent for the chapter "The future of AI or AI for the future," the term Imaginative and Creative Technology1 was used as the meaning of ICT instead of Information and Communication Technology. Maybe by becoming more imaginative and creative, we can create even better unimagined futures.

ICT's capabilities have been transformed beyond recognition since 1960 and ICT practitioners have had a substantial role in transforming the world in which we all live. The ICT workforce since 1960 has changed from programmers, analysts, and operators numbering a few tens of thousands worldwide into the highly diverse multi-million strong body we see today. For the end user, there are no longer levels of intermediaries between them and the computer-programmers to create software and operators to run the programs. Users have direct access to their PC or mobile device providing access to applications undreamt of in 1960.

While there are still software developers and operations staffnow concerned with networking as much as processingthe workforce has diversified to include new activities such as the graphic design, building, and maintenance of myriad web sites.

In 1995, at the opening ceremony of the IFIP Secretariat office in Laxenburg just outside Vienna, Austria, Prof. Heinz Zemanek, then the IFIP Historian, reminded the audience of the story of the early days of the telephone service when it started to dawn on telephone company executives in the USA that eventually half the population would be making telephone calls while the other half would be employed as telephone operators connecting their calls. He went on to observe that telephone technology rapidly set about automating the connection process so that every telephone user was transformed into an operator by giving us all initially a dial and latterly a keypad. Zemanek was an important computer pioneer but, as an indicator of the speed of change, he had no idea that 25 years later it would be normal for people to carry a "mobile" which would be a portable computer, one of whose many functions would be a telephone, and that people would often use texts and social media to communicate with other people rather than making telephone calls to one individual.

While the contributions were invited and not peer-reviewed like in conference proceedings, all chapters were reviewed by two editors to assure its quality by providing feedback to authors. This volume is the first Festschrift in the IFIP Advances in Information and Communication Technology (AICT) series. Festschrifts honor individual researchers and their scientific work, or they honor institutions or fields like IFIP Technical Committees, Working Groups, or other initiatives. Historical and even personal aspects may show up. They present internationally relevant technical contributions with a reasonable topical focus. As such, the Festschrifts also contribute to the principal aim of the IFIP AICT series to encourage education and the dissemination and exchange of information about all aspects of computing.

The editors accept full responsibility for the choice of topics, realizing that many more topics would have deserved a chapter in the book. We are especially grateful to the authors willing to give freely of their expertise and time to contribute to this book during the very difficult period of the first half of 2020.

We are very pleased with the rich content of the contributions and by making the volume open access, we trust that it will be read and enjoyed by many.

Regina Bernhaupt

Regina Bernhaupt's main research passion is to make people's lives better. Her research focus is on understanding how, when, and why interactive systems fail and how to evaluate the impact of new technologies on people's everyday lives. Her main contributions have been in areas like interactive television, games, and entertainment-oriented applications. Her special topic is how to allow people to stay in control of a system, but as well as to stay in control over their data (privacy) and their lives. Regina was introduced to IFIP during the Interact conference 2003, and became a member of the Working Group 13.2 Methodologies for User-Centred System Design of IFIP in 2005. Today she is the president of this Working Group. She also serves as the Dutch representative of IFIP TC-13. She has been actively involved in the TC-13 Interact conference since 2005 in various roles and was Papers Chair for Interact in 2017.

Vinton G. Cerf Vinton G. Cerf co-designed the TCP/IP protocols and the architecture of the Internet and is Chief Internet Evangelist for Google. He is a former member of the National Science Board and current member of the US National Academies of Engineering and Science and is a Foreign Member of the British Royal Society and Swedish Royal Academy of Engineering. He is a Fellow of ACM, IEEE, AAAS, and BCS. Cerf received the US Presidential Medal of Freedom, US National Medal of Technology, Queen Elizabeth Prize for Engineering, Prince of Asturias Award, Japan Prize, ACM Turing Award, Legion d'Honneur, the Franklin Medal, the Catalunya International Prize, and 29 honorary degrees.

Robert Davison

Robert Davison is a Professor of Information Systems at the City University of Hong Kong and Fellow of the Association for Information Systems. His research focuses on the use and misuse of information systems, especially with respect to problem solving, guanxi formation, and knowledge management in Chinese organizations. He has published over 200 articles in a variety of the premier IS journals and conferences. He is particularly known for his scholarship in the domain of action research. Robert chairs IFIP's Working Group 9.4 (Social Implications of Computing in Developing Countries), is a member of Working Group 8.2 (Information Systems and Organizations), and is also a member of the IFIP Digital Equity Committee. He serves as the Editor-in-Chief of the Information Systems Journal and the Electronic Journal of Information Systems in Developing Countries. Robert seeks to enhance the inclusion of scholars from the global south within our community and frequently visits developing countries where he offers research seminars and workshops, engaging with PhD students and scholars. As a researcher and as an editor, he champions local and indigenous perspectives. Home Page: http://www.is.cityu.edu.hk/staff/isrobert.

Moira de Roche

Moira de Roche is an independent consultant. She is the Chair of IFIP IP3, and a member of the IFIP board. She is also a Director on the Global Industry Council, an IFIP think-tank comprised of senior people from all parts of the globe who are involved with ICT. Moira was awarded the IFIP Silver Core in 2016.

Moira is an accomplished speaker and has presented at conferences around the world, including South Africa, on diverse subjects such as Technology and Learning, IT Leadership, Future Skills, and more. Her speaking engagements on behalf of IP3 have seen her speaking on Professionalism, Trust, and the Duty of Care in Digital, as well as people-related issues with Industry 4.0. She has attended and presented at the World Summit for Information Society since 2012.

A Past President of IITPSA (Institute of IT Professionals South Africa) Moira is a Professional Member and Fellow, and currently serves as a Non-Executive Director. She received the IITPSA Distinguished Service in ICT Award in 2009. Moira is also a member of ACM and the South African Institute of Directors. She serves as a Councilor on the board of the South African National Museum and is a member of the Board Committees on HR, Governance, and Legal as well as Core Business and IT.

Erik DeBenedictis

Erik has a background in Computer Science and Engineering, starting with BSc and PhD degrees in Electrical Engineering and Computer Engineering from Caltech in 1978 and 1983, and an MA degree in Computer Engineering from Carnegie Mellon University in 1979. He worked at Bell Laboratories on hypercube parallel computers, Ansoft Corporation (now Ansys) developing the sparse matrix solver for the High Frequency Structure Simulator (HFSS, mentioned in the article), and in a project management role. He then worked at nCUBE corporation on hypercube parallel supercomputer before founding NetAlive, Inc., a startup with a wireless internet software application framework. He later joined Sandia National Laboratories performing research on supercomputers, cryogenic computers, quantum computing, and spacecraft computing. He is now the principal of Zettaflops, LLC.

He is a Senior Member of the IEEE and has had volunteer leadership roles as a co-lead of the Rebooting Computing initiative, the Quantum initiative, and is Editor-in-Chief of IEEE Transactions on Quantum Engineering.

Per Fors

Per Fors is a postdoctoral scholar at the Department of Civil and Industrial Engineering at Uppsala University. His main research interests are topics related to technology, sustainability, and ethics, and he is teaching ethics, and sustainability to engineering students. Per is a member of the IFIP WG 9.9 (ICT and Sustainable Development).

David Alan Grier

David Alan Grier is the Technology Principal at Djaghe LLC and is the author of When Computers Were Human. He is an IEEE Fellow and has served as president of the IEEE Computer Society, Editor-in-Chief of Computer, Editor-in-Chief of the Annals of the History of Computing, editorial columnist for Consumer Electronics Magazine and the Communications of the Chinese Computing Federation.

Roger Johnson

Dr. Roger Johnson is a Fellow of the British Computer Society and a Chartered Engineer. He worked for 30 years in the School of Computer Science at Birkbeck University of London following a period as a software engineer developing software mainly in the financial services industry. He published extensively on database management and later the history of computing. He is a leading authority on the work of Andrew Booth, who invented the Booth multiplier, and was the first person to successfully connect a magnetic storage device to a computer. Before his retirement in 2015 he was a Director of Charteris plc for 18 years and before that a Partner in Deloitte Consulting for 12. At Deloitte he led the Knowledge Based Systems Centre, a unit developing knowledge-based systems, including the first working fraud detection system for Barclaycard and systems to detect fraudulent share applications in government privatization issues. He practised as a management consultant and as an expert witness in large scale IT disputes. His earlier career was with IBM UK, National CSS (later Dun & Bradstreet) in the USA, and Logica. He has an MA from the University of St Andrews.

He is co-author of From Principles to Profit -The Art of Moral Management (Duckworth, London, 2006).

Liesbeth Ruoff-van Welzen

Liesbeth Ruoff-van Welzen acquired expertise in various fields. After starting as a marketeer in education at the predecessor of the Rotterdam School of Management and IT firms in the hardware and services sector, she became CEO of IDC Benelux. She played an important role in the development and growth of the company and its market research in different sectors like services, channels, and networks. Her last role was Group Vice President IDC EMEA. In 2002 she decided to leave IDC and to start her own company LRWA. In the beginning she worked closely with Paul Strassmann and Tom Pisello. Topics LRWA addressed lay in the area of the added value of IT, how to achieve that within organizations, and how to deliver as an IT company added value. It became more and more clear that skills, attitude, and competences of human capital within organizations were the differentiator between a positive or negative result. That topic is LRWA's main focus.

She currently spends most of her time ensuring that professionalism of the ICT world and digital skills of professional users and citizens are taken seriously, and adequate actions are taken. She does that in her role as chairman of the Interest Group (IG) Digital Skills of the KNVI, the Dutch organization for the information professional, member of CEN TC-428, the European Standardization Committee for ICT Professionalism and Digital Competences and board member of IP3, a part of IFIP.

Adrian Schofield

Adrian began his career in the UK petroleum industry, followed by some years in casino administration. He spent 25 years in various executive and consulting roles in the South African ICT sector prior to joining the Joburg Centre for Software Engineering at the University of the Witwatersrand in 2008 as Manager: Applied Research Unit. In 2018, he was appointed Production/Program Consultant at IITPSA (Institute of Information Technology Professionals South Africa).

He has lectured about the Management of Technology and Systems Thinking and is a regular commentator in the trade media. Adrian has spent more than 30 years promoting standards and growth in the ICT sector. Adrian has served as President of the Information Technology Association in South Africa and as Vice Chairman of the Africa ICT Alliance. He received the 2012 Distinguished Service in ICT Award from Computer Society South Africa (now IITPSA). In 2015, he was appointed as a Councillor for the Broad-Based Black Economic Empowerment (B-BBEE) ICT Sector Council, until March 2020.

He currently serves as Vice Chairman (Standards and Accreditation) of IP3 (the International Professional Practice Partnership at the International Federation for Information Processing).

Adrian is a Fellow and Professional Member of IITPSA, having served terms as its Vice President and President.

Leon Strous

Leon has a background in business economics, business informatics, and a postgraduate degree in IT-Audit. He worked eight years for Philips Electronics in The Netherlands with a focus on internal control and information security. Since 1993, Leon is with De Nederlandsche Bank (DNB), the reserve bank of The Netherlands. Previous positions in the internal audit department, in the oversight department, and in a policy department of the cash and payments division. Currently his main job is advancing business continuity and crisis management arrangements with the key players in the payments and securities processes in the financial sector in The Netherlands. He is also liaising between the financial sector and the government concerning critical infrastructure protection programs.

His more than 25 years of involvement with IFIP include being Chair of Technical Committee 11 on Information Security and Privacy Protection (2001Protection ( -2007) ) and President of the Federation (2010Federation ( -2016)). He was the representative for The Netherlands in TC-11 from 1995-2007and in the General Assembly from 2001-2017. He has co-authored and co-edited publications in the area of information security and has been involved in various roles in the organization of many conferences, including IFIP World Computer Congresses and the IFIP World IT Forum (WITFOR).

Leon was awarded Knight of the Order of Orange-Nassau in 2015. He is an Honorary Member of IFIP.

Doron Swade

Doron Swade is an engineer, historian, and museum professional. He was Curator of Computing for many years at the Science Museum, London, and later Assistant Director and Head of Collections. He has studied physics, mathematics, electrical engineering, control engineering, philosophy of science, and man-machine studies at various universities including University of Cape Town, University of Cambridge, University of Essex, and University College London. He designed digital hardware for 10 years and consulted for the microcomputer industry in the UK and USA. He lectures widely and has published four books (one co-authored) and many scholarly and popular articles on history of computing, curatorship, and museology. He is a leading authority of the life and work of Charles Babbage and is responsible for the construction of Charles Babbage's Difference Engine No. 2 built to original nineteenth-century designs. He founded the Computer Conservation Society in 1989, which is dedicated to the preservation and restoration to working order of historic computing machines. He is an Honorary Fellow of the British Computer Society (2019) and of Royal Holloway University of London (2018). He was awarded an MBE in 2009 for services to the history of computing.

Ruth Wandhöfer

Dr. Ruth Wandhöfer operates at the nexus of finance, technology, and regulation, and is passionate about creating the digital financial ecosystem of the future. She is an expert in the field of banking and one of the foremost authorities on transaction banking regulatory and innovation in financial technology matters. After a distinguished career of over a decade with Citi, Ruth is now an independent Non-Executive Director on the boards of Permanent TSB and Digital Identity Net as well as a Partner at Gauss Ventures. Ulrika H. Westergren Ulrika H. Westergren is an Associate Professor of Informatics at Umeå University, Sweden, and a faculty member of the Swedish Center for Digital Innovation. She specializes in the digitalization of society with a focus on organizational change, new business models, value creation, and issues of trust, in relation to the introduction of new technology. She has led numerous collaborative projects with companies within the manufacturing and processing industries and is currently focusing on exploring viable business models for firms that are operating within an Internet of Things ecosystem and on IoT for societal benefit. Ulrika is the Swedish representative in IFIP Technical Committee 9: ICT and Society and serves as a member of the Domain Committee IFIP IoT. She has published her work at numerous conferences and in journals, such as the European Journal of Information Systems, Information Systems Journal, Information and Organization, Business Horizons, and Information Systems and E-business Management Journal, and is co-author of The IoT Guide (www. iotguiden.se). Ulrika is also an appointed member of the advisory council to Sweden's national accreditation body, Swedac. She is passionate about creating knowledge about new technology and the opportunities and challenges that digitalization offers, both in terms of the emergence of new business logic and in the social implications that follow. Ulrika holds an A.B. in International Relations from Bryn Mawr College, USA, and a PhD in Information Systems from Umeå University.

Anthony Wong

Anthony has double degrees in Computer Science and Law from Monash University, Master of Laws in Media, Communications and IT from University of New South Wales (UNSW), and a Master of Intellectual Property from University Technology Sydney (UTS), Australia.

He has also held senior management positions in multinational corporations and government. His multidisciplinary career traversed legal practice, multinationals in both IT vendor and customer capacities, including with Philips, The Netherlands, as CIO of the Australian Tourist Commission during the Sydney 2000 Olympics, and led the digital transformation of Thomson in the Asia Pacific.

Anthony is the Managing Director of AGW Lawyers & Consultants, a multidisciplinary legal and advisory practice in many areas of law and technology across financial services, media and publishing, education, tourism, insurance, start-ups, business services and consulting, and the data and digitization industries.

He is Vice President of the International Federation for Information Processing (IFIP) and Vice Chair of IFIP IP3. He is Past President of the Australian Computer Society (ACS) and Past President of SEARCC.

Anthony is an industry thought leader and has served on the IT Industry Innovation Council for the Australian Government. He chaired the New South Wales (NSW) Government ICT Advisory Panel and served on the NSW Digital Transformation Taskforce.

He is a Fellow and Honorary Life Member of the ACS and a member of the International Technology Law Association (ITechLaw), Australian Society for Computers and Law, Australian Institute of Company Directors (AICD), International Association of Privacy Professionals (IAPP), and the Law Society of New South Wales.

He is a regular commentator and presenter on topical issues on various print and online media, radio, and TV, as well as a speaker at various national and international forums.

(

  including at the IFIP World Computer Congress in Poznan in 2018), Sri Lanka, Mauritius, and Australia. He is a Liveryman of the Worshipful Company of Information Technologists and Chaired its Ethical and Spiritual Development Panel. He advises charities which benefit from the WCIT Charity on the ethical development of AI systems.

  Dr. ir. Wil van der Aalst is a Full Professor at RWTH Aachen University leading the Process and Data Science (PADS) group. He is also part-time affiliated with the Fraunhofer-Institut für Angewandte Informationstechnik (FIT) where he leads FIT's Process Mining group. His research interests include process mining, Petri nets, business process management, workflow management, process modeling, and process analysis. Wil van der Aalst has published over 800 articles and books and is typically considered to be in the top 15 of most cited computer scientists with an H-index of over 150 and more than 100,000 citations. Next to serving on the editorial boards of over 10 scientific journals, he is also playing an advisory role for several companies, including Fluxicon, Celonis, Processgold, and Bright Cape. Van der Aalst received honorary degrees from the Moscow Higher School of Economics (Prof. h.c.), Tsinghua University, and Hasselt University (Dr. h.c.). He is also an elected member of the Royal Netherlands Academy of Arts and Sciences, the Royal Holland Society of Sciences and Humanities, the Academy of Europe, and the North Rhine-Westphalian Academy of Sciences, Humanities and the Arts. In 2018, he was awarded an Alexander-von-Humboldt Professorship.Wil is proud to be an IFIP Fellow. Ron Berndsen is an independent director of LCH and chairs the LCH Risk Committees. He is also attached to the Tilburg School of Economics and Management at Tilburg University as Full Professor of Financial Market Infrastructures and Systemic Risk. Ron is Editor-in-Chief of the Journal of Financial Market Infrastructures and a member of the Advisory Council of the SWIFT Institute.The author has been active in the field of payments and market infrastructures for over 17 years. He was Head of the Oversight Department and Head of the Market Infrastructures Policy Department at De Nederlandsche Bank. Ron also served as a member on the Market Infrastructure Board at the European Central Bank and as member of the Committee on Payments and Market Infrastructures at the Bank of International Settlements. He also co-chaired the FSB Group on Cross-Border Crisis Management for Financial Market Infrastructures and was a member of the Oversight Committees of CLS, EuroCCP, Euroclear, LCH, SWIFT, and TARGET2.He was awarded a doctorate of Tilburg University in 1992 for his PhD thesis in Economics and Artificial Intelligence.

	viii	Preface
		Authors
	Wil van der Aalst
	Prof. Ron Berndsen
	Prof.
	September 2020	Leon Strous
			Roger Johnson
			David Alan Grier
			Doron Swade

  She is a Strategic Adviser of the European Third Party Provider Association (ETPPA) and Adviser at Coinfirm. Until recently, she has served as independent Non-Executive Director on the Board of the London Stock Exchange Group and Pendo Systems Inc. Ruth was named as one of 2010s 'Rising Stars' by Financial News; named in Management Today's 2011 '35 Women under 35' list of women to watch, and identified as one of the 100 Most Influential People in Finance 2012 by the Treasury Risk Magazine. She received the 'Women in Banking and Finance Award for Achievement' in 2015 and in 2016, 2017, and 2018 she was named on the global 'Women in Fintech Powerlist' of Innovate Finance. She is a 2018, 2019, and 2020 Top 10 Global Fintech Influencer (Fintech Power 50). She speaks five languages, has completed studies in Financial Economics (MA, UK), International Politics (MA, FR), and an LLM in International Economic Law (UK). She was awarded a doctorate by CASS Business School, London, and Tilburg University in 2019 for her PhD thesis in Finance on the topic of "Technology Innovation in Financial Markets." She published two books: "EU Payments Integration" (2010) and "Transaction Banking and the Impact of Regulatory Change" (2014), is a Fellow of CASS Business School City University London, a Visiting Professor at the London Institute of Banking and Finance, and also lectures at Queen Mary London School of Law.

While difficult to find who coined the term, a Google search resulted in a few hits.

x Authors

xvi Authors

Universidad de Costa Rica (UCR) since 1980. She was Dean of Graduate Studies and Director of the Research Center for Communication and Information Technologies (CITIC), both at UCR. Currently, she is the UCR Graduate Program in Computer Science and Informatics Chairperson. She has organized several international and national conferences, and has been, and still is, Chair of several Program and Editorial Committees. From 2012 to 2016, she was President of the Latin American Center for Computer Studies (CLEI), becoming the first woman to occupy such a distinguished position. Since September 2016, she is Vice President of the International Federation for Information Processing (IFIP), in charge of the Digital Equity Committee. Her research interests include Smart Cities, Human Computer Interaction, Decision Support Systems, Gender in IT, and Digital Equity. Eunika Mercier-Laurent Eunika Mercier-Laurent is an electronic engineer, holds a PhD in Computer Science, is an expert in Artificial Intelligence (AI), and is an Associate Researcher at the University of Reims Champagne Ardennes as well as Professor at EPITA International Masters and SKEMA. Her teaching and MOOC includes Knowledge Management and Innovation powered by AI, Ethical Development of AI Systems, Innovation Ecosystems, and Innovation Week Challenges.

After working as researcher in INRIA and a computer designer and manager of innovative AI applications with Groupe Bull, she founded Global Innovation Strategies devoted to all aspects of Knowledge Innovation. Among her research topics are: Knowledge and Eco-innovation Management Systems, methods and techniques for innovation, knowledge modeling and processing, complex problem solving, AI for sustainability, and eco-design and impacts of AI.

She has over 15 years of involvement with IFIP including the Chair position of Technical Committee 12 on AI since 2019 and Chair of WG 12.6 (AI for Knowledge Management). She is representative of TC-12 in France since 2018.

Eunika is President of Innovation3D, International Association for Global Innovation, expert for EU programs, and author of over hundred scientific publications and books.

Bertrand Meyer

Bertrand Meyer is Provost and Professor of Software Engineering at the Schaffhausen Institute of Technology in Switzerland and holds associated positions at Innopolis University and Politecnico di Milano. He is also Chief Technology Officer at Eiffel Software (Santa Barbara, California). He was previously Professor of Software Engineering and Department Chair at ETH Zurich. His works spans several areas of software engineering including software verification, programming languages, object technology, requirements engineering, and concurrent programming. His contributions include the concept of "Design by Contract," the Eiffel development method and programming language, and a number of widely used books.

Chris Rees

Chris Rees was President of the British Computer Society, The Chartered Institute for IT, in 2018-2019. During his presidential year he chose the Ethics of AI as his theme, and lectured on the topic to professional and lay audiences in the UK, Europe


Ming Xiao

Boyan Wang

Student Member, IEEE Jingcun Liu

Student Member, IEEE Ruizhe Zhang

Zichen Zhang

Chao Ding

Shengchang Lu

Kohei Sasaki
email: sasaki@novelcrystal.co.jp

Fellow, IEEE Guo-Quan Lu

Senior Member, IEEE Cyril Buttay
email: cyril.buttay@insa-lyon.fr

Member, IEEE Yuhao Zhang

Packaged Ga 2 O 3 Schottky Rectifiers with Over 60 A Surge Current Capability

Keywords: ultra-wide bandgap, gallium oxide, surge current, ruggedness, package, thermal management, simulation

Ultra-wide-bandgap gallium oxide (Ga2O3) devices have recently emerged as promising candidates for power electronics; however, the low thermal conductivity (kT) of Ga2O3 causes serious concerns about their electrothermal ruggedness. This work presents the first experimental demonstrations of largearea Ga2O3 Schottky barrier diodes (SBDs) packaged in the bottom-side-cooling and double-side-cooling configurations, and for the first time, characterizes the surge current capabilities of these packaged Ga2O3 SBDs. Contrary to popular belief, Ga2O3 SBDs with proper packaging show high surge current capabilities. The double-side-cooled Ga2O3 SBDs with a 3×3 mm 2 Schottky contact area can sustain a peak surge current over 60 A, with a ratio between the peak surge current and the rated current superior to that of similarly-rated commercial SiC SBDs. The key enabling mechanisms for this high surge current are the small temperature dependence of on-resistance, which strongly reduces the thermal runaway, and the double-side-cooled packaging, in which the heat is extracted directly from the Schottky junction and does need to go through the low-kT bulk Ga2O3 chip. These results remove some crucial concerns regarding the electrothermal ruggedness of Ga2O3 power devices and manifest the significance of their die-level thermal management.

I. INTRODUCTION

Ultra-wide-bandgap (UWBG) semiconductor gallium oxide (Ga2O3) is a promising material for next-generation power electronics due to its high critical electrical field (EC), controllable doping, excellent thermal stability, and the availability of large-diameter wafers by the melt growth [START_REF] Pearton | A review of Ga2O3 materials, processing, and devices[END_REF], [START_REF] Higashiwaki | Guest Editorial: The dawn of gallium oxide microelectronics[END_REF]. Recently, kilovolt-class Ga2O3 Schottky barrier diodes (SBDs) [START_REF] Allen | Vertical Ga2O3 Schottky Barrier Diodes With Small-Angle Beveled Field Plates: A Baliga's Figure-of-Merit of 0.6 GW/cm 2[END_REF], [START_REF] Li | Field-Plated Ga2O3 Trench Schottky Barrier Diodes With a BV 2 / Ron of up to 0.95 GW/cm2[END_REF] and power FinFETs [START_REF] Zhang | Ultra)Wide-Bandgap Vertical Power FinFETs[END_REF], [START_REF] Li | Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV[END_REF] were demonstrated with a peak electric field (E-field) in Ga2O3, exceeding the EC of GaN and SiC. However, most of the reported Ga2O3 devices have a small current, and only a few large-area Ga2O3 devices have been demonstrated with a current over 1 Amp [START_REF] Ji | Demonstration of Large-Size Ga2O3 Schottky Barrier Diodes[END_REF], [START_REF] Yang | Vertical geometry 33.2 A, 4.8 MW cm 2 Ga2O3 field-plated Schottky rectifier arrays[END_REF].

A fundamental challenge for the current scaling in Ga2O3 devices is the low thermal conductivity (kT) of Ga2O3 (0.1-0.3 Ming Xiao, Boyan Wang, and Jingcun Liu contributed equally to this work. (Corresponding authors: Yuhao Zhang, Cyril Buttay, Guo-Quan Lu).

Ming Xiao, Boyan Wang, Jingcun Liu, Ruizhe Zhang, Zichen Zhang, Chao Ding, Shengchang Lu, Guo-Quan Lu, and Yuhao Zhang are with the Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061 USA (e-mail: mxiao@vt.edu; wangboyan@vt.edu; jcliu@vt.edu; rzzhang@vt.edu; zichen2013@vt.edu; dingchao@vt.edu; lsheng1@vt.edu; gqlu@vt.edu; yhzhang@vt.edu).

Wcm -1 K -1 [START_REF] Pearton | A review of Ga2O3 materials, processing, and devices[END_REF]), which is about 1/6 of the kT of Si, 1/10 of GaN, and 1/20 of SiC. The high thermal resistance of the Ga2O3 die makes its thermal management very challenging. While some modeling and simulation works have investigated the thermal management of Ga2O3 devices [START_REF] Paret | Thermal and Thermomechanical Modeling to Design a Gallium Oxide Power Electronics Package[END_REF]- [START_REF] Buttay | Surge Current Capability of Ultra-Wide-Bandgap Ga2O3 Schottky Diodes[END_REF], no experimental demonstrations of the packaging and thermal management of large-area Ga2O3 devices have been reported to date.

Due to the low kT of Ga2O3, Ga2O3 devices are often perceived to have very limited electrothermal ruggedness. Surge current ruggedness is essential for power applications, when the device needs to temporarily sustain a current higher than the rated one. The surge current value is listed in a diode's datasheet and is usually measured in a half-sinusoidal currentpulse according to JEDEC standards [START_REF]SILICON RECTIFIER DIODES[END_REF]. While the surge current ruggedness has been extensively studied for SiC diodes [START_REF] Heinze | Surge Current Ruggedness of Silicon Carbide Schottky-and Merged-PiN-Schottky Diodes[END_REF], [START_REF] Wu | 1.2-kV 4H-SiC Merged PiN Schottky Diode With Improved Surge Current Capability[END_REF], no such tests have been reported for Ga2O3 devices.

This work presents the first experimental study on the surge current capability of large-area, packaged Ga2O3 devices. Vertical Ga2O3 SBDs were fabricated with a current over 10 A. Two packaging structures were designed and prototyped, one based on the bottom-side-cooling scheme where the heat must diffuse through the entire Ga2O3 chip before reaching the baseplate (Fig. 1(a)), and the other based on the double-sidecooling scheme (Fig. 1(b)), which allows the heat dissipation through the Ga2O3 chip and directly from the Schottky junction simultaneously. Despite the low kT of Ga2O3, the double-sidecooled Ga2O3 chip showed a high surge current capability over 60 A. The electrothermal dynamics in the packaged Ga2O3 SBDs were also studied using mixed-mode simulations.

II. DEVICE FABRICATION, PACKAGING, AND TEST SETUP

The Ga2O3 wafer consists of a 10-µm Si-doped n-Ga2O3 layer (net donor concentration ~2×10 16 cm -3 ) grown on a 2-inch n + -Ga2O3 (001) substrate (Sn: 1.3×10 19 cm -3 ). The substrate was thinned down to a thickness of 500 µm. The device fabrication is similar to those reported in [START_REF] Allen | Vertical Ga2O3 Schottky Barrier Diodes With Small-Angle Beveled Field Plates: A Baliga's Figure-of-Merit of 0.6 GW/cm 2[END_REF], [START_REF] Wang | High-voltage vertical Ga2O3 power rectifiers operational at high temperatures up to 600 K[END_REF]. A Ti/Au (30/150 nm) Ohmic contact was formed as the cathode. 1-µm-thick SiO2 was deposited as the field-plate (FP) dielectrics, followed by a wet etch to produce a ~15 o FP bevel angle. An Ni/Au stack was deposited as the Schottky and FP metals. 100-nm Ti and 200nm Ag were deposited on both sides as the contact layer for the device packaging that followed. The Schottky contact area is 3×3 mm 2 , and the total sample size is about 4.5×4.5 mm 2 .

A nanosilver paste from NBE Technologies was used for the die attach by a pressureless sintering process in air [START_REF] Wang | Low-Temperature Sintering with Nano-Silver Paste in Die-Attached Interconnection[END_REF], [START_REF] Calata | Sintered nanosilver paste for hightemperature power semiconductor device attachment[END_REF]. The sintered-silver joint has a high melting temperature of 960 o C and a high thermal conductivity over 1 Wcm -1 K -1 . A laser-cut mask was used to stencil-print a 50-µm thick nanosilver paste on bonding pads with minimal lateral seepage. The sintering profile was: from room temperature to 250 o C at a ramp rate of 6 o C/min and held at 250 o C for 30 minutes, followed by air cool to room temperature. For the single-sidecooled package, the cathode of the Ga2O3 chip was sintered on a 1-mm thick Ag plate, and wire-bonds were attached on the top anode. For the double-side-cooled package, each terminal of the Ga2O3 chip was sintered on a 1-mm thick Ag plate. The packaged chips were then soldered on an alumina direct-bondcopper (DBC) substrate and electrically connected through two leads to a curve tracer and a surge current test board. Fig. 1(c) shows a double-side-cooled Ga2O3 package ready for test.

It should be noted that the cooling structure in this work is discussed in the context of a 10-ms transient instead of the steady state. The thickness of Ag plate (1 mm) is designed to ensure that the heat diffusion is confined in the plate during the 10-ms transient (validated in the simulation in Section III, see Fig. 3). The bottom solder and DBC in both packages as well as the top wire bond in the double-side package do not contribute to the heat dissipation during the 10-ms transient.

Fig. 1(d) and (e) show surge-current test circuit and the prototype, respectively. The test circuit is similar to the one reported in [START_REF] Wu | 1.2-kV 4H-SiC Merged PiN Schottky Diode With Improved Surge Current Capability[END_REF]. A 10-ms-wide half-sinusoidal current waveform was produced by a resonance circuit (a 2.2-mH inductor and a 4.7-mF capacitor). SiC MOSFETs were used as the control switches. The peak surge current (Ipeak) was stepped up by increasing the power supply voltage. The device voltage was monitored by a differential probe, and the current was sensed by a 0.1-Ω coaxial current shunt (SSDN series). After each single-pulse surge-current test, the device was measured on the curve tracer to identify any possible degradation.

III. EXPERIMENTAL RESULTS AND PHYSICAL ANALYSIS

Fig. 1(f) and (g) show the temperature-dependent I-V curves of the packaged large-area Ga2O3 SBDs in the linear region and the subthreshold region, respectively. The I-V characteristics of the SBDs in both packages are almost identical. The current on/off ratio is ~10 9 at 33 o C and maintains ~10 7 at 153 o C, suggesting the good thermal stability of the Schottky contact. The turn-on voltage is ~0.85 V at 33 o C and decreases to ~0.65 V at 153 o C. The current reaches 13 A (144 A/cm 2 ) at a forward voltage of 2 V. The temperature dependence of on-resistance (Ron) can be fitted by a power law with a temperature coefficient (α) of 0.73. This α is much smaller than the one reported for SiC SBDs (2.95 [START_REF] Buttay | Thermal Stability of Silicon Carbide Power Diodes[END_REF]), suggesting the superior thermal stability of Ga2O3 SBDs. This could be attributed to the small temperature dependence of mobility in Ga2O3 [START_REF] Buttay | Surge Current Capability of Ultra-Wide-Bandgap Ga2O3 Schottky Diodes[END_REF] and the increased donor ionization at high temperatures [START_REF] Wang | High-voltage vertical Ga2O3 power rectifiers operational at high temperatures up to 600 K[END_REF].

The breakdown voltage (BV) of the fabricated Ga2O3 SBDs was measured to be ~700 V, similar to the one reported in [START_REF] Wang | High-voltage vertical Ga2O3 power rectifiers operational at high temperatures up to 600 K[END_REF] using a similar edge termination, regardless of the packaging structures. Note that this BV is limited by the edge termination and has not reached the material limit. If suitable termination were used, e.g., the one reported in [START_REF] Allen | Vertical Ga2O3 Schottky Barrier Diodes With Small-Angle Beveled Field Plates: A Baliga's Figure-of-Merit of 0.6 GW/cm 2[END_REF] that produces an average junction field of 3.4 MV/cm, the BV of the chip used in this work could reach 1600 V.

Fig. 2(a) and (b) show the current/voltage waveforms in a set of surge current tests with increased Ipeak for the Ga2O3 SBDs with both package structures. The Ga2O3 SBD with the bottomside-cooling package was found to fail in the surge test with an Ipeak of 39 A. The failure Ipeak is much higher (70 A) in the double-side-cooled SBD. Fig. 2(c) and (d) show the surge I-V loops of the SBDs with both types of packages. Both I-V loops are clockwise, due to the increased Ron at higher Tj, and the loop area is correlated to the Ron (and Tj) increase in the surge test. With a similar Ipeak (e.g., 30 A), the loop area of the double-sidecooled SBD is smaller than that of the bottom-side-cooled SBD, suggesting a smaller Tj increase. In addition, the last safewithstand I-V loop of the double-side-cooled Ga2O3 SBD (Ipeak ~ 68 A) shows a larger area than that of the bottom-side-cooled SBD (Ipeak ~ 37.5 A), implying that the double-side-cooled SBD can sustain a higher Tj. Fig. 2(e) shows the transfer characteristics of the double-side-cooled SBD after each surge test with increased Ipeak. Almost no device degradation is shown with Ipeak up to 60 A. At 68 A Ipeak, higher leakage current is present, suggesting the degradation in the Schottky contact.

To understand the electrothermal dynamics within the device structure, mixed-mode electrothermal TCAD simulations were performed in Silvaco Atlas, which solves the self-consistent electrothermal device models [START_REF] Zhang | Electrothermal Simulation and Thermal Performance Study of GaN Vertical and Lateral Power Transistors[END_REF] in a circuit arrangement consistent with that shown in Fig. 1(d). Temperature-dependent kT, heat capacity, and electron mobility models were employed for Ga2O3 and nanosilver (Table I). A good agreement between the simulation and experiment was achieved in static I-V curves and the surge I-V loops (Fig. 2(f)-(g)).

Fig. 2(h) shows the simulated Tj evolution at the Schottky contact region of the two types of SBDs in the surge current tests. In the test with a similar Ipeak, the simulation validates a lower peak Tj in the double-side-cooled SBD. The simulated Tj reaches the peak value at the transient t ≈ 6 ms, agreeing with the failure transients shown in Fig. 2 Klaassen's Unified Low-Field Mobility Model mumaxn.kla = 120 (drift region) /30 (substrate) Ga2O3 kT (Wcm -1 K -1 ) k(TL) = 0.1× (TL/300) -0.95 (TL: lattice temp.) Ga2O3 heat capacity (JK -1 ) C(TL) = 0.2038 + 0.00174×TL -1.459×10 -6 ×TL 2

Nano-Ag kT (Wcm -1 K -1 ) k(TL) = 1× (TL/300) -0. show the simulated heat flux and temperature contours in the bottom-side-cooled SBD at the peak Tj transient in the surge current test with Ipeak ~ 37.5 A. The heat flux distribution in the double-side-cooled SBD reveals that most heat is dissipated directly from the Schottky junction instead of through the Ga2O3 die. This explains the lower Tj in the double-side-cooled SBD as compared to that in the bottom-side-cooled SBD at a similar Ipeak. As shown in Figs. 3(c) and (d), the simulated peak temperature is located within the Ga2O3 drift layer in the double-side-cooled SBD. In contrast, as shown in Fig. 3(f), the peak temperature is located at the Schottky junction in the bottom-side-cooled SBD. The double-side-cooling package moves the peak temperature from the Schottky contact region into the robust bulk Ga2O3, which allows the device to sustain a higher Tj before degradation of the Schottky contact. Additionally, as shown in Figs. 3(d) and (f), the temperature distribution at the Schottky junction region is much less uniform in the bottom-side-cooled SBD compared to that in the double-side-cooled SBD. This temperature non-uniformity could be exacerbated by the wire bonding on the top of the anode in the bottom-side-cooled SBD, which often induces local current crowding and thermal runaway. This explains the lower Tj that bottom-side-cooled SBDs can sustain as compared to the one that double-side-cooled SBDs can. This mechanism is supported by the observation of burning traces near the wire bonds in the failed bottom-side-cooled SBDs.

IV. BENCHMARK, DISCUSSION AND CONCLUSION An important device ruggedness metric for practical power applications is the ratio between the maximum Ipeak in 10-ms surge current tests and the rated current. The rated currents of the bottom-side-cooled and double-side-cooled Ga2O3 SBDs were determined by the calibrated static electrothermal simulations when the Tj reaches 150 o C, being 6.2 A bottom-side-cooled device and 9.2 A for the double-side-colled device. For comparison, several commercial SiC SBDs with similar ratings (600-V voltage rating and 4~11 A current ratings) were tested in the same surge current test setup to identify their maximum surge currents. As shown in Table II, despite the low kT of Ga2O3 (1/20 of SiC), the fabricated Ga2O3 SBDs, particularly the ones with double-side-cooling package, show comparable, or even superior surge current capabilities as compared to the similarly-rated commercial SiC SBDs.

Commercial SiC SBDs usually have bipolar p-n junctions that enhance the device ruggedness. Without p-type doping in Ga2O3, the superior surge current capabilities of Ga2O3 SBDs can be attributed to two mechanisms: first, the inherently smaller α in Ga2O3 devices allows for a small conduction loss increase with increased Tj and less risks for thermal runaway; second, the double-side-cooling package obviates the heat extraction via the low-kT Ga2O3 chip and moves the peak temperature from the Schottky contact into the bulk Ga2O3.

To further understand the design space of the surge current capabilities of Ga2O3 devices, two additional die-level thermal management approaches were considered: thinning of the Ga2O3 substrate, and bonding Ga2O3 device layers to a SiC wafer [START_REF] Xu | First Demonstration of Waferscale Heterogeneous Integration of Ga2O3 MOSFETs on SiC and Si Substrates by Ion-Cutting Process[END_REF]. Using the calibrated simulation models, Fig. 4 shows the simulated peak Tj as a function of surge Ipeak for the different Ga2O3 device structures. A similarly-rated SiC SBD with identical substrate thickness was also simulated as a reference. In Ga2O3 devices, the substrate thinning provides little improvement in the surge current capabilities when compared to the use of junction cooling, since most of the heat is directly extracted from the junction. Whereas, if low-kT SiC substrate is used in Ga2O3 devices, the heat extraction through the bulk chip can be improved significantly. Hence, the surge current capabilities can be further improved in the double-sidecooled device as compared to the bottom-side-cooled one.

In summary, this work presents the first experimental demonstration of large-area vertical Ga2O3 SBDs with different die-level cooling packages, and for the first time, reports the surge current capabilities of these packaged Ga2O3 devices. Despite the low kT of Ga2O3, Ga2O3 SBDs packaged in a double-side-cooling scheme show comparable or even superior surge current capabilities when compared to SiC SBDs. These results remove the key concerns regarding the electrothermal ruggedness of Ga2O3 devices and demonstrate the significance of die-level thermal management for Ga2O3 electronics.

Fig. 1 .

 1 Fig. 1. Schematic of the Ga2O3 SBDs with (a) bottom-side-cooling package and (b) double-side-cooling package. (c) Photo of a double-side-packaged SBD. (d) Circuit diagram and (e) photo of the surge current test board. Forward I-V characteristics of the packaged Ga2O3 SBDs at 33-153 o C in the (f) linear region and (g) subthreshold region. [inset of (f)] temperaturedependence of the differential Ron and the power law fitting.

Fig. 2 .

 2 Fig. 2. Current/voltage waveforms of the (a) bottom-side-cooled and (b) double-side-cooled Ga2O3 SBDs in the surge current tests. I-V loops of the (c) double-side-cooled and (d) bottom-side-cooled devices. (e) Transfer characteristics in the subthreshold region after each surge current test. Simulation model calibration for the (f) surge I-V loops and (g) static I-V characteristics. (h) Simulated junction temperature in the surge current tests for bottom-side-cooled and double-side-cooled Ga2O3 SBDs.

  (a) and (b). The simulation also verifies a smaller Tj in the bottom-side-cooled SBD at its critical Ipeak (~ 37.5 A) as compared to the one in the doubleside-cooled SBD (critical Ipeak ~ 68 A). Figs. 3(a)-(d) show the simulated distributions of heat flux and temperatures in the double-side-cooled SBD at the peak Tj transient in the surge current test with Ipeak ~ 68 A. Fig. 3(e)-(f)

Fig. 3 .

 3 Fig. 3. Simulated heat flux contour in the (a) entire packaged device and (b) device junction region, and simulated temperature distributions in the (c) entire device and (d) junction region, in a double-side-cooled Ga2O3 SBD at the peak Tj transient in the surge current test with 68 A Tpeak. Simulated (e) heat flux contour and (f) temperature contour in the junction region of the bottom-side-cooled Ga2O3 SBD at the peak Tj transient in the surge current test with 37.5 A Tpeak.

Fig. 4 .

 4 Fig. 4. Simulated max junction temperature as a function of peak surge current in 10-ms surge tests for the double-side-cooled and bottom-sidecooled Ga2O3 SBDs on the 0.5-mm-thick Ga2O3 substrate, 0.1-mm-thick Ga2O3 substrate, and 0.5-mm-thick SiC substrate. A thermal boundary resistance of 0.01 K/(W•cm 2 ) was set at the Ga2O3/SiC bonding interface. Identical electrical conductivity was set for Ga2O3 and SiC substrates. The simulated SiC SBD has a 0.5-mm-thick substrate and a bottom-side-cooled package. Caughey-Thomas model was used for the SiC electron mobility.

TABLE I

 I

		.
	KEY MODELS IN THE ELECTROTHERMAL SIMULATION
	Parameter	Models and key parameters
	Ga2O3 electron mobility
	(cm 2 V -1 s -1 )

TABLE II COMPARISON

 II OF THE SURGE CURRENT CAPABILITY OF SIC AND GA2O3 SCHOTTKY BARRIER DIODES

	Device	Rated Current (A)	Max Surge Current (A)	Max surge current over rated current
	SiC SBD (CSD01060A)	4	20.3	5.1
	SiC SBD (CSD02060A)	8	26.9	3.36
	SiC SBD (CSD03060A)	11	31.8	2.89
	Bottom-side-cooled Ga2O3 SBD	6.2	37.5	6.05
	Double-side-cooled Ga2O3 SBD	9.2	68	7.4


Kaoutar Chargui
email: chargui.kaoutar@gmail.com

Abdellah El Fallahi
email: aelfallahi@gmail.com

Tarik Zouadi
email: tarik.zouadi@uir.ac.ma

Mohamed Reghioui
email: m.reghioui@gmail.com

-Morocco "New advances and challenges for sustainable and smart industries" STUDY OF THE IMPACT OF QUAY CRANE PRODUCTIVITY RATE ON BERTH AND QUAY CRANE ASSIGNMENT AND SCHEDULING

Keywords: Berth allocation, quay crane assignment, quay crane scheduling, quay crane capacity

The integrated berth allocation and quay crane assignment and allocation is among the most addressed problems in the maritime related literature. The accuracy of this problem solutions depends on the precision of the resource's capacity estimation. Accordingly, in this paper, we investigate how the estimation error impacts the problem solutions. We focus on the quay cranes as being the main resources involved in serving the port customers vessels. We modelled the problem and tested different estimation errors scenarios for a dataset of instances. Computational results illustrated clearly the variation pattern of the problem solutions error over the capacity estimation error.

INTRODUCTION

Maritime logistics topic is set to become a widely investigated area in the literature due its very noticeable impact on the international trade (UNCTAD, 2018). Improving the port performance brings about various problems to be investigated especially the berth allocation, quay crane assignment and scheduling problems. The quality of this problem solutions depends mainly on how accurate the estimated resources capacities are. In this paper, we focus on the quay crane resources and we propose a model for this integrated problem inspired from a similar one in the literature. Then, we investigate how the quay cranes capacity estimation error influences the quality of the problem solutions. We conduct an experimental study to illustrate the impact of several estimation error values on the model objective value over a set of real based instances.

The remainder of this paper is as follows. Section 2 reports the most related past works regarding the topic addressed in this paper. A mathematical formulation of the studied problem is presented in Section 3. In Section 4, we report the results of the conducted experiments, then the paper ends with a conclusion and some potential lines for future work.

LITERATURE REVIEW

The berth allocation and quay crane assignment and scheduling problems were widely addressed in the literature and different formulation and algorithms were proposed to solve them [START_REF] Bierwirth | A follow-up survey of berth allocation and quay crane scheduling problems in container terminals[END_REF]Li et al., 2015, Fu and[START_REF] Fu | A Lagrangian relaxation approach for solving the integrated quay crane assignment and scheduling problem[END_REF][START_REF] He | Quay crane scheduling for multiple hatches vessel considering double-cycling strategy[END_REF]. Recently, many contributions tended to integrate those problems in one single formulation due to the cost savings induced by that [START_REF] Agra | MIP approaches for the integrated berth allocation and quay crane assignment and scheduling problem[END_REF][START_REF] Chen | Integrated scheduling of crane handling and truck transportation in a maritime container terminal[END_REF][START_REF] Correcher | A biased random-key genetic algorithm for the time-invariant berth allocation and quay crane assignment problem[END_REF][START_REF] Meisel | A Framework for Integrated Berth Allocation and Crane Operations Planning in Seaport Container Terminals[END_REF][START_REF] Unsal | Constraint programming approach to quay crane scheduling problem[END_REF]Oguz, 2013, Chargui et al., 2019). In most of past work, the performance rate of quay cranes was considered fix even though its estimation is subject to potential error. In fact, the capacity of a quay crane, which is expressed in terms of the number of containers moved per time period, is variant and dependent on many factors such as the characteristics of containers to be handled [START_REF] Linn | Predicting the Performance of Container Terminal Operations using Artificial Neural Networks[END_REF].

In the light of that, we investigate empirically the impact of the quay crane estimation error on the solution of the berth allocation and the quay crane assignment and scheduling integrated problem. For this, we modelled the problem based on the formulation proposed by [START_REF] Chargui | A reactive multi-agent approach for online (re)scheduling of resources in port container terminals[END_REF] and conducted a set of experiments to highlight the variation. Total time needed to serve the vessel v.

MATHEMATICAL MODEL

Decision variables

Objective function

The objective of the model consists in minimizing the sum of vessels serving times. It's expressed as in equation ( 1).

Minimize ∑ 𝐼 𝑣 𝑉 𝑣=1

(1)

Constraints

∑ ∑ 𝑄 𝑣𝑡 𝑝𝑐 𝑉 𝑣=1 𝑃 𝑝=1 ≤ 1 (∀𝑡 = 1. . 𝑇, 𝑐 = 1. . 𝐶)
Constraints (2) ensure that at each time period a quay crane is at most assigned to one bay and one vessel.

(2)

13 the International Conference on Modeling, Optimization and Simulation -MOSIM'20 -November 12-14, 2020-Agadir -Morocco "New advances and challenges for sustainable and smart industries"

∑ ∑ 𝑄 𝑣𝑡 𝑝𝑐 𝑉 𝑣=1 𝐶 𝑐=1 ≤ 1 (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃)
Constraints (3) guarantee that at each time period a bay is allocated at most one quay crane and one vessel.

(3)

𝑚 𝑡𝑝 ≤ ∑ ∑ 𝑄 𝑣𝑡 𝑝𝑐 𝑟 𝑉 𝑣=1 𝐶 𝑐=1 (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃)
Constraints (4) determine the performance rate of the quay crane assigned to each bay at every time period. It's null if no quay crane is assigned to that bay at that time period.

(4)

∑ 𝑄 𝑣𝑡 𝑝𝑐 𝐶 𝑐=1
≤ 𝐻 𝑣𝑡𝑝 𝑀 (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉) Constraints (5) ensure that, at each time period, if the remaining workload on each bay and every vessel is null, no quay crane will be assigned that bay.

(5)

𝐻 𝑣𝑡𝑝 = 0 (∀𝑡 = 1. . 𝑇: 𝑡 ≤ 𝐽 𝑣 , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)
Constraints ( 6) ensure that the remaining workload at every bay of a vessel is null before the arrival of that vessel.

(

) 6
𝐻 𝑣𝑡𝑝 ≤ 𝐷 𝑣𝑝 (𝑡 = 𝑦 𝑣 ) + 𝑍 𝑣𝑡𝑝 -𝑋 𝑣𝑡𝑝 (∀𝑡 = 1. . 𝑇: 𝑡 ≤ 𝐽 𝑣 , , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)

Constraints ( 7) is used the calculate the handled amount at each time period.

(7)

∑ 𝑋 𝑣𝑡𝑝 𝑇 𝑡=1
≥ 𝐷 𝑣𝑝 (∀𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)

Constraints ( 8) ensure that the workload on each bay of a given vessel must be handled during the planning horizon.

(

) 8
𝑋 𝑣𝑡𝑝 ≤ 𝑀 (∀𝑡 = 1. . 𝑇: 𝑡 ≤ 𝐽 𝑣 , , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉) Constraints (9) guarantee that the number of containers handled on bay of a vessel at a given time period is null in case no crane was assigned that bay before.

𝑋 𝑣𝑡𝑝 ≥ 𝑚 𝑡-1,𝑝 -𝑀 (∀𝑡 = 1. . 𝑇: 𝑡 ≤ 𝐽 𝑣 , , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉) Constraints ( 10) and ( 11) are used to calculate the number of containers handled during a time period that must be after the starting time to serve the vessel. Constraints ( 12), ( 13) and ( 14) are used to calculate the remaining workload from each time period. ( 14)

∑ ∑ 𝑄 𝑣𝑡 𝑝1𝑐1 𝑟 𝑃 𝑝1=1,𝑝1>𝑝 𝐶 𝑐1=1,𝑐1<𝑐 ≤ 𝑀(1 -𝑄 𝑣𝑡 𝑝𝑐 𝑟) (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉, 𝑐 = 1. . 𝐶)
Constraints ( 15) are added to avoid the interference between quay cranes. Constraints ( 16) define the port stay of a vessel as the time interval between its arrival time and the last time period it was being served.

(

) ∑ 𝐻 𝑣𝑡𝑝 𝑃 𝑝=1 ≤ 𝑠 𝑣𝑡 𝑀 (∀𝑡 = 1. . 𝑇, 𝑣 = 1. . 𝑉) ( 16
) 17
𝑠 𝑣𝑡 ≤ ∑ 𝐻 𝑣𝑡𝑝 𝑃 𝑝=1 (∀𝑡 = 1. . 𝑇, 𝑣 = 1. . 𝑉)
Constraints ( 17) and ( 18) ensure that the remaining workload of a vessel bay is null if it hasn't started being served yet.

(

) 18
𝑠 𝑣1𝑡 ≤ 𝑀 (∀𝑣1 = 1. . 𝑉, 𝑣2 = 1. . 𝑉: 𝑣1 ≠ 𝑣2, 𝑡 = 1. . 𝑇: 𝑡 ≥ 𝐽 𝑣 )

Constraints ( 18) are added to prevent physical contact of vessels. Constraints (20) ensure that the workload remaining at the first time period is null.

𝑋 𝑣1𝑝 = 0 (∀𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)
Constraints ( 21) ensure that the workload handled before the first time period is null.

(21)

𝑍 𝑣𝑡𝑝 ≥ 0 (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)

Constraints ( 22) ensure that the variable Z is positive.

(

) 22
𝐻 𝑣𝑡𝑝 ≥ 0 (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)

Constraints ( 23) ensure that the variable H is positive.

(

) 23
𝑋 𝑣𝑡𝑝 ≥ 0 (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)

Constraints ( 24) ensure that the variable X is positive.

(

) 24
𝑚 𝑡𝑝 ≥ 0 (∀𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃)

Constraints ( 25) ensure that the variable m is positive.

(

) 25
𝑦 𝑣 ≥ 0 (∀𝑣 = 1. . 𝑉)

Constraints ( 26) ensure that the variable y is positive.

(

) 26
𝐼 𝑣 ≥ 0 (∀𝑣 = 1. . 𝑉)

Constraints ( 27) ensure that the variable I is positive.

(

) 27
𝑄 𝑣𝑡 𝑝𝑐 𝜖{0,1}

(∀𝑣 = 1. . 𝑉, 𝑡 = 1. . 𝑇, 𝑝 = 1. . 𝑃, 𝑐 = 1. . 𝐶)

Constraints ( 28) ensure that the variable Q is binary.

(28)

𝑠 𝑣𝑡 𝜖{0,1} (∀𝑣 = 1. . 𝑉, 𝑡 = 1. . 𝑇)

Constraints ( 29) ensure that the variable s is binary.

(29)

RESULTS

Table 1 reports the results of the study. In this study, we considered 50 instances generated based on real case data. For every instance, we solved the model 19 times. At each run, we modified the performance rate of quay cranes that we calculate as in equation ( 30) with A representing the estimated quay crane capacity and the reference capacity is given as 30.

The two equations are used to calculate the gaps between the values. The objective function error is calculated as in equation ( 31) with B being the optimal objective value obtained using the estimated capacity and C is the optimal value found using the reference capacity 30. The averages of the objective functions values errors show that they increase as the estimation error increases and vice versa. Additionally, the objective values errors increase more significantly for the negative estimation errors compared to the positive ones.

CONCLUSION

As the accuracy of the integrated berth allocation and quay crane assignment and scheduling problem solutions depends on the capacity estimation quality, we modeled the problem and conducted an experimental study to highlight the influence of the estimation error on the objective function values obtained using different scenarios of errors. The results showed that there is a significant impact of the error value on the optimal solution found for every instance. This work could be extended by proposing some methods to control the estimation error in order to reduce its impact on the planning solutions.

𝑟

  Processing rate of quay cranes.

  𝐷 𝑣𝑝 Number of containers to handle on the bay p of vessel v.𝐽 𝑣Arrival time of vessel v.𝐸 𝑣 Right berth position of vessel v.𝐹 𝑣Left berth position of vessel v.

  𝑋 𝑣𝑡𝑝 ≤ 𝑚 𝑡-1,𝑝 (∀𝑡 = 2. . 𝑇: 𝑡 ≥ 𝐽 𝑣 , , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)

  𝑀(𝑡 ≥ 𝑦 𝑣 + 1) (∀𝑡 = 2. . 𝑇: 𝑡 ≥ 𝐽 𝑣 , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉) (12) 𝑍 𝑣𝑡𝑝 ≤ 𝐻 𝑣,𝑡-1,𝑝 (∀𝑡 = 2. . 𝑇: 𝑡 ≥ 𝐽 𝑣 , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉) (13) 𝑍 𝑣𝑡𝑝 ≤ 𝐻 𝑣,𝑡-1,𝑝 -𝑀(1 -(𝑡 ≥ 𝑦 𝑣 + 1)) (∀𝑡 = 2. . 𝑇: 𝑡 ≥ 𝐽 𝑣 , 𝑝 = 1. . 𝑃, 𝑣 = 1. . 𝑉)

  1. . 𝑃, 𝑣 = 1. . 𝑉) (20) 13 the International Conference on Modeling, Optimization and Simulation -MOSIM'20 -November 12-14, 2020-Agadir -Morocco "New advances and challenges for sustainable and smart industries"

  crane c is handling the bay p of vessel v at time period t. 0: otherwise.

	𝑄 𝑣𝑡 𝑝𝑐 1: if 𝑦 𝑣 Service starting time of vessel v.

𝑚 𝑡𝑝 Performance rate of the quay crane on bay p at time period t. 𝐻 𝑣𝑡𝑝 Number of containers remained to handle from bay p of vessel v at the beginning of time period t. 𝑍 𝑣𝑡𝑝 Number of containers remained on vessel v at bay p from time period t-1. 𝑋 𝑣𝑡𝑝 Number of containers handled on vessel v at bay p at time period t-1. 𝑠 𝑣𝑡 1: if vessel v is being served at time period t. 0: otherwise 𝐼 𝑣

Table 1 :

 1 The objective function errors over the estimation errors 13 the International Conference onModeling, Optimization and Simulation -MOSIM'20 -November 12-14, 2020- Agadir -Morocco "New advances and challenges for sustainable and smart industries"

	Estimation error percentage