Ole Christian
email: olechris-tian.spro@ntnu.no

Pierre Lefranc

Student Member, IEEE Sanghyeon Park

Senior Member, IEEE, Dimosthenis Peftitsis, Senior Member, IEEE Juan M Rivas-Davila

Member, IEEE Ole-Morten Midtgård

Fellow, IEEE Tore Undeland

O C Spro

D Peftitsis

O.-M Midtgård

V Dc+

V Dc- V Ac

Optimized Design of Multi-MHz Frequency Isolated Auxiliary Power Supply for Gate Drivers in Medium Voltage Converters

Keywords: Resonant power conversion, Inductive power transmission, Virtual prototyping, Medium voltage, Gate drivers

This paper presents the design and optimisation of a suitable topology for an isolated DC-DC auxiliary power supply with high isolation voltage and low coupling capacitance. The converter consists of a GaN HEMT inverter operating at 6.78 MHz, an LCC resonance tank and a class E low dv/dt rectifier. Furthermore, the galvanic isolation is implemented using a coreless planar transformer that enables higher insulation voltage with similar or better converter efficiency compared to designs using magnetic material. An analytical design methodology is developed, however, SPICE investigations show that optimal designs might lie outside the validity of the design equations. Consequently, a virtual prototyping tool is developed based on a genetic algorithm with numerical simulations and, in turn, is used to optimise the converter. The optimisation algorithm maximises the converter efficiency while minimising the transformer size. Prototypes are constructed based on the resulting Pareto front. Experimental results show the validity of the simulated results. Prototypes transferring power up to 15 W with a peak efficiency of 81% are shown. The selected topology enables insulating voltages exceeding 40 kV and coupling capacitances below 10 pF.

I. INTRODUCTION

With the continuous development of high voltage power semiconductors, medium voltage converters can obtain lower power losses and increased efficiency. Main applications for medium voltage (up to 36 kV RMS ) converters include industrial drives (e.g. fans, mills, pumps), wind turbines with fullyrated converters, medium voltage dc distribution grids for marine vessels, urban transportation or other applications, and flexible ac transmission systems (FACTS) used in medium voltage grids [START_REF] Abu-Rub | Medium-voltage converters -state of the art, challenges, and requirements in industrial applications[END_REF]- [START_REF] Giannakis | MVDC distribution grids and potential applications: Future trends and protection challenges[END_REF]. Such converters operate with dc-links of up to a few tens of kilovolts, which necessitates the use of either modular multilevel converter (MMC) topologies, or 2-level or 3-level voltage source converters (VSC) using valves with series-connected power semiconductor switches (Figs. 1a and1b). The characteristics and current development of high voltage SiC devices make them especially attractive for medium voltage applications.

Regardless of the specific medium voltage converter topology, an auxiliary power supply is always required for energising control and gate circuitry. In particular, the auxiliary power supply provides power to a switching unit that consists either of a submodule in a MMC converter or several seriesconnected switches in 2-level VSCs (see Fig. 1). The typical output power requirement of the auxiliary power supply is approximately 10 W [8, pp. 121-132].

One way to supply this power is through the local medium voltage dc-link by using a DC-DC step-down converter, such as the tapped inductor Buck converter [START_REF] Sharifabadi | Design, Control, and Application of Modular Multilevel Converters for HVDC Transmission Systems[END_REF], [START_REF] Modeer | High-Voltage Tapped-Inductor Buck Converter Utilizing an Autonomous High-Side Switch[END_REF]. However, to improve system safety and provide better diagnostics, it is more beneficial to supply auxiliary circuits via an external power source [START_REF] Wunsch | Externally-fed auxiliary power supply of MMC converter cells[END_REF]. The latter requires the design of sophisticated isolated power supplies with high-voltage insulation and low coupling capacitance. The insulation requirement is related to the operating voltage of the medium voltage converter, requiring an isolation voltage of at least the full dc-link voltage. A crucial challenge is to simultaneously minimise the coupling capacitance of the auxiliary power supply, as this capacitor constitutes a path for the noise current generated during dv/dt events and possibly affecting control circuitry [START_REF] Nguyen | Gate driver supply architectures for common mode conducted EMI reduction in series connection of multiple power devices[END_REF]. Moreover, the fast switching capabilities of SiC MOSFETs increase the importance of this requirement.

A. Isolated power supplies Isolated power supplies feeding gate drivers in medium voltage converters is targeted in several publications. In general, these works can be categorised along two dimensions; a single converter feeding a single load or multiple loads, and transformer design with or without magnetic material. For most of the concepts, a resonant or quasi-resonant converter structure is used. Within resonant converter topologies, the seriesseries compensated (SS) resonant converter structure is usually preferred due to its simple design. An established architecture consists of a single converter feeding multiple loads using a single primary winding that goes through several toroidal magnetic cores on which the secondary turns are winded and supplies the loads separately [START_REF] Peftitsis | Auxiliary power supply for medium-voltage modular multilevel converters[END_REF]- [START_REF] Hu | Current-Transformer Based Gate-Drive Power Supply with Reinforced Isolation[END_REF]. The reported coupling capacitance is in the range of 1-2 pF [START_REF] Gottschlich | A galvanically isolated gate driver with low coupling capacitance for medium voltage SiC MOSFETs[END_REF], which is very low. The disadvantage with a single to multiple load system is that the medium voltage converter system is dependent on the reliability of the single feeding converter. Furthermore, the previously mentioned feature of better diagnostics is lost.

An alternative architecture consists of separate feeding converters, each with its own transformer and supplying each load separately [START_REF] Wunsch | Externally-fed auxiliary power supply of MMC converter cells[END_REF], [START_REF] Am | Design methodology for very high insulation voltage capabilities power transmission function for IGBT gate drivers based on a virtual prototyping tool[END_REF]- [START_REF] Mainali | Design and evaluation of isolated gate driver power supply for medium voltage converter applications[END_REF]. A compact transformer concept designed for up to 36 kV RMS application have been shown using magnetic material and a dielectric design using potting gel and conductive paint [START_REF] Wunsch | Externally-fed auxiliary power supply of MMC converter cells[END_REF]. Although the withstand voltage and small system size are impressive, the transformer concept is complex to manufacture. In comparison, a transformer concept that is easier to fabricate with a breakdown voltage higher than 40 kV is demonstrated in [START_REF] Am | Design methodology for very high insulation voltage capabilities power transmission function for IGBT gate drivers based on a virtual prototyping tool[END_REF], [START_REF] Sarrazin | Insulated power supply for gate drivers up to 40 kV for medium-voltage direct current applications[END_REF]. Here, the transformer with a magnetic core has an airgap of 1 mm in which a nonmagnetic insulating material is placed. However, it is reported that any increase in the gap distance, and hence the insulation voltage, drastically decreases the converter efficiency [START_REF] Am | Design methodology for very high insulation voltage capabilities power transmission function for IGBT gate drivers based on a virtual prototyping tool[END_REF].

A more traditional transformer design consisting of insulated wires with different magnetic core materials and shapes has been proposed in [START_REF] Mainali | Design and evaluation of isolated gate driver power supply for medium voltage converter applications[END_REF], [START_REF] Batra | Isolation design considerations for power supply of medium voltage silicon carbide gate drivers[END_REF]. Additionally, an insulating material is wrapped around the core to increase the insulation voltage. Such schemes have been shown to provide an insulation voltage above 20 kV with low coupling capacitances of less than 5 pF. Yet, such layering of dielectric material must be designed carefully to avoid partial discharges in air pockets between layers. Furthermore, such systems have to comply with several criteria in the standards of the International Electrotechnical Commission (IEC) governing insulation schemes which may result in de-rating of the insulation voltage [START_REF] Batra | Isolation design considerations for power supply of medium voltage silicon carbide gate drivers[END_REF].

The auxiliary power supply with galvanic isolation can also be established by using power-over-fibre technology [START_REF] Fujita | A Resonant Gate-Drive Circuit With Optically Isolated Control Signal and Power Supply for Fast-Switching and High-Voltage Power Semiconductor Devices[END_REF]- [START_REF] Rouger | CMOS gate drivers with integrated optical interfaces for extremely fast power transistors[END_REF]. Although a very low coupling capacitance can be achieved, this technology faces power transmission limitations and low efficiency.

Several publications have also investigated the use of inductive power transfer (IPT) systems as a method of fulfilling the insulation requirements [START_REF] Kusaka | Isolation system with wireless power transfer for multiple gate driver supplies of a medium voltage inverter[END_REF]- [START_REF] Wunsch | Inductive power transfer for auxiliary power of medium voltage converters[END_REF]. Both single converter to single load [START_REF] Kusaka | Isolation system with wireless power transfer for multiple gate driver supplies of a medium voltage inverter[END_REF], [START_REF] Wunsch | Inductive power transfer for auxiliary power of medium voltage converters[END_REF] and single converter to multiple loads [START_REF] Takasaki | Wireless power transfer system for gate power supplies of modular multilevel converters[END_REF], [START_REF] Lim | Isolated power supply for multiple gate drivers using wireless power transfer system with single-antenna receiver[END_REF] have been demonstrated. IPT systems uses resonant converters to transfer power by coreless transformers that have poor coupling coefficients. The gap between the primary and secondary sides of the transformer is used to establish an insulation barrier by using either air or another non-magnetic material as the insulation material. Intrinsically, large gap distances result in low coupling capacitance. IPT systems should operate at high frequency to limit the physical size of the transformer and passive components.

B. Contribution of this paper

This paper presents an isolated auxiliary power supply which is based on the insulation scheme reported by Am et al. [START_REF] Am | Design methodology for very high insulation voltage capabilities power transmission function for IGBT gate drivers based on a virtual prototyping tool[END_REF]. By using GaN devices and together with a coreless planar transformer, the presented converter can improve the efficiency while simultaneously increasing the achievable insulation voltage compared to the published work. The proposed topology in this paper is shown in Fig. 2. It consists of a half bridge inverter, a LCC resonant tank, a coreless transformer and a class E rectifier designed for an operating frequency of 6.78 MHz. The proposed topology results in a simple system that can operate in open loop with large variations in load.

Furthermore, an analytical design method is proposed for the topology. In addition, further investigations reveal that the rectifier performance improves when designed for frequencies beyond that of the resonance converter using SPICE simulations. Above-resonance operation is found to be beneficial for the efficiency, however, this necessitates simulation-based design. Thus, the paper demonstrates the feasibility of using a virtual prototyping tool for the converter design which is used to optimise the converter efficiency while minimising the transformer coupling capacitance. The optimisation results are coherent with the presented design theory and investigations. Three potential candidates for the non-magnetic insulation material are explored in the paper and the insulation performance is evaluated in terms of insulation voltage and coupling capacitance.

The paper is organised as follows. Section II describes the converter topology and implementation choices. In addition, arguments for the use of a computer assisted design method are given. In Section III, the converter modelling is analysed and then verified experimentally. The optimisation tool and results are presented in Section IV. Section V presents experimental results of four prototypes taken from the optimised designs obtained in Section IV. Finally, the conclusions are drawn in Section VI.

II. CONVERTER STRUCTURE FOR THE AUXILIARY POWER SUPPLY

A. Proposed Converter Structure

In the literature, a SS resonant converter structure is usually preferred due to the simple design procedure and that the phase angle for the converter does not change with load resistance [START_REF] Wang | Power transfer capability and bifurcation phenomena of loosely coupled inductive power transfer systems[END_REF]. The output voltage of the resonant system is rectified using a full bridge diode rectifier consisting of four diodes. In comparison, the class E low dv/dt rectifier consists of a single diode. While the rectifier topology is known in the literature for several decades [START_REF] Kazimierczuk | Resonant Power Converters[END_REF]Chapter 4] [28], it has gained interest in recent years for use in IPT systems [START_REF] Kkelis | Class-E half-wave zero dv/dt rectifiers for inductive power transfer[END_REF], [START_REF] Liu | A compact class E rectifier for megahertz wireless power transfer[END_REF]. For this topology, the transformer secondary side coil, L sec , and the parasitic capacitance of the diode are used as part of the passive elements needed to form a resonant soft switching circuit. This results in a very compact and efficient rectifier for multi-MHz systems. The diode losses are lower than for full bridge diode rectifier solutions that are reported as a significant contribution to total losses [START_REF] Wunsch | Inductive power transfer for auxiliary power of medium voltage converters[END_REF], especially for low output-power designs.

There are several inverter topologies available for multi-MHz (i.e. 6.78 MHz and beyond) frequency applications. Due to the high switching frequency, the inverter must operate with soft switching in order to eliminate the excessive switching losses. The class E inverter [START_REF] Kazimierczuk | Resonant Power Converters[END_REF]Chapter 13] [31], [START_REF] Nagashima | Analysis and design of loosely inductive coupled wireless power transfer system based on class-E 2 dc-dc converter for efficiency enhancement[END_REF] and the class Φ 2 [START_REF] Rivas | A very high frequency dc-dc converter based on a class Φ 2 resonant inverter[END_REF] are often used, both consisting of a single switch. Main drawbacks of these converters are low switch utilisation and sensitivity to load variation and tuning issues. In this work, a half-bridge structure is used in combination with a LCC resonant tank [START_REF] Pantic | ZCS LCC-compensated resonant inverter for inductive-power-transfer application[END_REF], which results in a total component count that is similar to the SS topology (summarised in Table I). The main difference is the need for a discrete inductor, while only a single diode is needed. In a half bridge, the switch voltage is equal to the dc-link voltage, leading to high switch utilisation. This allows for using an integrated half bridge module with GaN high electron mobility transistors (HEMT) that is available for low power applications [START_REF]LMG5200 80V, 10A GaN Half-Bridge Power Stage[END_REF]. Using GaN HEMT devices operating at high frequency keeps the converter size small while ensuring low driving losses. The characteristic capacitances of GaN HEMTs are lower than for Si and SiC counterparts with similar rating [START_REF] Li | SiC/GaN power semiconductor devices: A theoretical comparison and experimental evaluation under different switching conditions[END_REF]. In this regard, GaN HEMT is an enabling technology as using Si or SiC devices at MHz frequency would result in driver losses comparable to the output power of the auxiliary power supply. This is critical for low power applications. However, a concern regarding GaN devices is the effect of dynamic on-resistance [START_REF] Spro | Modelling and quantification of power losses due to dynamic on-state resistance of GaN E-mode HEMT[END_REF], [START_REF] Cai | Impact of GaN HEMT dynamic onstate resistance on converter performance[END_REF] and losses related to the charging and discharging of the output capacitance [START_REF] Zulauf | Coss losses in 600 V GaN power semiconductors in soft-switched, high-and very-high-frequency power converters[END_REF].

B. Analytical Design Method

The design method for the converter is developed based on the fundamental harmonic approximation [START_REF] Kazimierczuk | Resonant Power Converters[END_REF]. The rectifier is modelled as shown in Fig. 3a. The load resistance is set as

R load,min = V 2 out P nom (1)
where V out is the output voltage at the nominal power, P nom . Next, the required inductance and capacitance of the rectifier, L sec and C rect are found by

L sec = R load,min ω sec Q r (2)
C rect = 1 ω 2 sec L sec (3)
where Q r is the loaded quality factor [START_REF] Kazimierczuk | Resonant Power Converters[END_REF]. ω sec is often set equal to the operating frequency, ω 0 . Furthermore, the voltage transfer function between the rectifier input voltage and the dc output voltage of the rectifier is defined as

M V = V out V m (4)
where V m is the amplitude of the voltage source at the rectifier input [START_REF] Kazimierczuk | Resonant Power Converters[END_REF]. Furthermore, the coupled inductors of the primary and secondary side are modelled as (Fig. 3c).

V prim = -jω 0 M I sec (5) V sec = -jω 0 M I prim [START_REF] Mura | Design aspects of a medium-voltage direct current (MVDC) grid for a university campus[END_REF] where the mutual inductance, M, is defined as

M = k L prim L sec ( 7
)
where k is the transformer coupling factor. The transformer efficiency depends on the coupling coefficient and the quality factor of the coils. For two spiral coils, the coupling coefficient is at its highest when the coils are of the same size with identical winding number [START_REF] Waters | Optimal coil size ratios for wireless power transfer applications[END_REF]. Consequentially, the coil inductance is chosen as Starting from Eq. ( 6), the current in the primary side of the transformer is dimensioned to satisfy the required input voltage of the rectifier, V m , as defined in Eq. [START_REF] Baran | DC distribution for industrial systems: Opportunities and challenges[END_REF].

L prim = L sec = L. C par L R cpar R ser R par Series- switch V DC+ V AC C p C s V in L R
I prim = V m ω 0 M = V m ω 0 kL (8)
Next, the equations for the primary side circuit are developed by using Kirchhoff's voltage law for the fundamental frequency.

√ 2 π V in = (jωL s -j 1 ωC p )I inv + j 1 ωC p I prim (9) 0 = j 1 ωC p I inv + I prim (jωL prim -j 1 ωC p + Z load ) (10)
where Z load = R load + jX load is the rectifier impedance reflected to the primary side, V in is the dc input voltage, C p is the parallel capacitor, L s is the series inductance, L prim is the transformer primary side inductance, and I inv and I prim are the currents as indicated in Fig. 2. Next, we set the resonance of L s and C p according to the following criteria:

ω 2 0 = 1 L s C p = (2πf sw ) 2 (11)
where ω 0 is the series resonance of L s and C p , and f sw is the switching frequency of the inverter. With Eq. ( 11) fulfilled, the part containing I inv in Eq. ( 9) equals zero and the expression for current I prim becomes

I prim = -jω 0 C p √ 2 π V in (12)
Hence, the current in the primary side of the transformer can be dimensioned by C p for a given dc-link voltage and is approximately constant over the converter operating range. Combining Eqs. ( 8) and ( 12), the value of C p is found

C p = πV m 2ω 2 0 kLV in (13)
In the next step, the series capacitor, C s , is used to tune the switching current. The switching current, I inv,sw , is defined as the current amplitude of I inv at the moment of switching in the half bridge. This current is the sum of the fundamental and higher order harmonics of current resulting from the square wave voltage output of the inverter [START_REF] Pantic | ZCS LCC-compensated resonant inverter for inductive-power-transfer application[END_REF]. At the moment of switching, the switching current equals

I inv,sw = √ 2V in πZ c L prim L s - C p C s + X load Z c - π 2 8 ( 14
)
where I inv,sw is the output current of the inverter at the moment of switching, Z c is the characteristic impedance of the primary resonance circuit (Z c = L s /C p ) and X load is the reactance of the rectifier reflected to the primary side. As described in [START_REF] Pantic | ZCS LCC-compensated resonant inverter for inductive-power-transfer application[END_REF], ZCS can be achieved by setting this expression equal to zero. However, ZCS entails loss of the C OSS energy for every switching transition, which is substantial at multi-MHz frequencies. If I inv,sw is set to a negative value, then ZVS can be obtained. Thus, for a given transformer design, C s governs the size of current at the switching instant. C s is chosen so that the impedance seen from the inverter stays inductive, and with a small switching current that allows for soft switching within the set dead time of the half bridge. Since R load does not appear in Eq. ( 14), this switching current is not dependent on the active power transfer to the secondary side. However, Eq. ( 14) contains the term X load . The equivalent impedance of the class E rectifier used in this paper has shown to change with duty cycle, and hence with the operating point [START_REF] Ivascu | Class E resonant low dv/dt rectifier[END_REF]. This is countered by setting a margin for the switching current.

From Eq. ( 5) and using Fig. 3b, the rectifier impedance reflected to the primary side is found as

Z load = - w 2 0 M 2 R i - w 0 M 2 L i (15)
where R i and L i are the equivalent input resistance and inductance as defined in [START_REF] Kazimierczuk | Resonant Power Converters[END_REF]. The switching current is set according to the output capacitance of the inverter and the target dead time.

I inv,sw = - C OSS V in t commutation ( 16
)
where C OSS is the output capacitance of the inverter switches and t commutation is the time required to complete a switching transient which is equal or smaller than the deadtime. Finally, the value of C s is found by combining Eq. ( 14), Eq. ( 15) and Eq. ( 16)

C s = C p πZcIinv,sw √ 2Vin + Lprim Ls + X load Zc -π 2 8 ( 17
)
An example of dimensioning the converter is given in the Appendix. The SPICE simulation of the converter shows that the output voltage is within 2.6% of the ideal case.

C. Design of an above-resonance rectifier

The converter is further investigated by changing the resonance frequency of the rectifier, ω sec . In [START_REF] Kkelis | Class-E half-wave zero dv/dt rectifiers for inductive power transfer[END_REF], many class E rectifiers are compared according to their design parameters. It is shown that designing the rectifier off-resonance might give advantageous characteristics for the system. An example of a benefit is a smaller output voltage variation with varying load current if the rectifier resonance frequency is higher than operating frequency, ω 0 [START_REF] Kkelis | Class-E half-wave zero dv/dt rectifiers for inductive power transfer[END_REF]. The rectifier circuit shown in Fig. 3a is evaluated through SPICE simulations using ideal components. The relation between the resonance frequency of the rectifier and the voltage source frequency is defined as

A r = ω sec ω 0 ( 18
)
The rectifier is dimensioned using Eq. ( 1), Eq. ( 2) and Eq. ( 3), for which Q r is set so that the diode duty cycle is 50% [START_REF] Kazimierczuk | Resonant Power Converters[END_REF], [START_REF] Kkelis | Class-E half-wave zero dv/dt rectifiers for inductive power transfer[END_REF]. A r is varied in this work from 1.5 to 2.0 since this has been found to be the most promising design space in terms of high efficiency and lowest output voltage variation [START_REF] Kkelis | Class-E half-wave zero dv/dt rectifiers for inductive power transfer[END_REF]. With the component values set, the load resistor is varied from R L,min and towards open circuit (a decreasing load). M V is shown in Fig. 4a. The trend in M V for nominal output power is consistent with the findings in [START_REF] Kkelis | Class-E half-wave zero dv/dt rectifiers for inductive power transfer[END_REF]. For A r equal to 1.5 (and below), the rectifier output is closer to a current source behaviour. For higher A r , the output behaves like a voltage source until approximately 10% load. In Fig. 4b the M V is used to investigate the expected variation in output voltage with changing load. Low voltage variation is observed for higher A r . On the other hand, this lower variation comes at a price of lower efficiency since M V decreases. Additionally, the second harmonic of the rectifier circuit increases drastically as shown in Fig. 4c. Nevertheless, an added benefit of increasing A r is that the required inductor value decreases. Fig. 4d shows the passive component values for varying A r . The inductance value decreases from 2.41 to 0.164 µH, which makes the converter size smaller. The increase in capacitance value has a softer impact on the practical implementation.

However, for the optimisation problem, it is paramount that the model used in the optimisation method is coherent with the final experimental results. Fig. 4c shows that there is substantial content of harmonics and, in consequence, the fundamental harmonic approximation can no longer be assumed accurate. In this paper, it is rather argued for choosing a computer assisted design process due to the complexity and interactions between design parameters. A high fidelity simulation model serves as the basis for the optimisation algorithm. Although this approach requires more time due to the development time of exact models and long simulation times, the benefit is that the inverter, transformer and rectifier are optimised holistically. The converter topology contains many components resulting in many degrees of freedom. Moreover, even the resonance frequency could be chosen different from the switching frequency, adding to the design problem complexity. To globally answer the design problem, a virtual prototyping tool is used that is based on a genetic algorithm that is suitable for a mixed integer programming problem. However, since the output of the optimisation process is dependent on the fidelity of the simulation results, accurate simulation models must be first established.

III. MODELLING, SIMULATION PROCEDURE AND VERIFICATION OF CONVERTER OPERATION

A simulation model of the converter structure was established in a SPICE simulation software (LTSpice TM ), as such simulators are suitable for detailed component behaviour of the semiconductor devices. The electrical simulation model is used to investigate the converter behaviour in time domain when steady state operation has been established. Appropriate semiconductor components for the application are selected among commercially available components, and their SPICE models are included in the simulation. Furthermore, all passive components are added as shown in Fig. 2. For all capacitors, the equivalent series resistance is set according to the manufacturer data for the chosen operating frequency. For the inductances, the calculated or measured value for the series resistance was used.

The coreless transformer was modelled using finite element software as a magneto-static problem. From this model, lumped parameter model of the transformer can be extracted to be used in the electrical simulation in time domain. A free software for solving electromagnetic problems using finite element method, FEMM, was used [START_REF] Meeker | Finite Element Magnetic Modelling (FEMM)[END_REF]. The transformer is designed as spiral inductors, thus simplifying the electromagnetic problem to a 2D geometry with axisymmetrical properties. Additionally, the transformer can be accurately reproduced by printing windings on a PCB. Figure 5a shows the geometry of the transformer windings and the magneto-static problem. An example simulation result showing the lines of the magnetic field distribution using FEMM is shown in Fig. 5b. An initial prototype is constructed to verify the results obtained in simulation. Both the converter prototype and the measurement setup are seen in Fig. 6. The prototype is designed to be able to handle the resulting currents when operating with an input voltage of 48 V, resulting in the prototype component values that are given in Table II. The inverter is realised using a GaN HEMT half bridge module (TI LMG5200). As source for the logic input signals for the lower and upper switch, a signal generator is used (Tektronix AFG3052C). C p is chosen to obtain a circulating current of approximately 2 A at 48 V input voltage. The transformer was designed with a 5:2 turn ratio, which results in an output voltage of approximately 20 V. On the rectifier side, a SiC Schottky diode is used in the rectifier (STPSC406B, 600 V/4 A).

I Vm, h = 2 / I Vm, h = 1 [p.u.] A r =1.5 A r =1.6 A r =1.7 A r =1.8 A r =1.9 A r =2.0 (c)
To be able to evaluate the accuracy of the simulation model of the inverter, a loss estimation for the inverter is obtained thermally using a thermal camera (Fluke Ti25). The loss estimate takes into account the ambient temperature and is compensated for the driving losses. All prototype component values are measured with an impedance analyser (Agilent E4990). The estimated lumped parameters of the prototype PCB transformer are extracted and presented in Table III where they are compared to the transformer parameters from the FEMM simulation. As can be seen, the transformer inductance values are close to the values obtained from the simulation study. The additional inductance in the developed transformer design is hypothesised to originate from the connecting wires that are not accounted for in FEMM (see Fig. 5a). Hence, the measurements verify that simulated inductance values in FEMM can be realised in an experimental setup with high accuracy.

The converter is simulated and tested in the lab for several input voltages and load resistances. Fig. 7a shows the total system efficiency, the output power and inverter losses for an input voltage of 48 V while the load resistance varies from 15 to 1000 Ω. The peak measured efficiency is 67% and the converter obtains a peak output power of approximately 8 W. The difference in the maximum efficiency between simulation and experimental values is approximately 5%. Part of this error is due to the thermal and electrical model of the inverter used in the simulation. The comparison of the simulated and measured inverter losses in Fig. 7a shows that the inverter losses are underestimated in simulation. It is the hypothesis of the authors that these losses are related to two phenomena in the GaN HEMTs. One is the losses related to charging and discharging of the output capacitance, C OSS . The second loss factor is dynamic on-state resistance, resulting in a higher effective on-resistance than stated in the device datasheet. Experimental data on hysteresis losses has been published recently [START_REF] Zulauf | Coss losses in 600 V GaN power semiconductors in soft-switched, high-and very-high-frequency power converters[END_REF], [START_REF] Zhuang | Substrate bias effect on E-mode GaN-on-Si HEMT Coss losses[END_REF]. Depending on which manufacturer data from [START_REF] Zulauf | Coss losses in 600 V GaN power semiconductors in soft-switched, high-and very-high-frequency power converters[END_REF] is used for estimating the losses, a range in losses of 0.4 to 1 W is obtained per device. However, this is for 650 V devices. In [START_REF] Zhuang | Substrate bias effect on E-mode GaN-on-Si HEMT Coss losses[END_REF], measurements of the output capacitance losses are performed for a 100 V device, indicating a loss factor of approximately 5-10% of the C OSS energy per cycle [START_REF] Zhuang | Substrate bias effect on E-mode GaN-on-Si HEMT Coss losses[END_REF]. Using this relationship, the output capacitor loss for the two devices in the half bridge then evaluates to

P C OSS , = 2 • % percycle • E oss • f = % percycle • C OSS • V 2 DS • f (19)
Using a conservative % percycle = 10 %, C OSS = 266 pF from the datasheet and V dc = 48 V, P C OSS evaluates to approximately 0.42 W. This power loss is added to the simulated inverter loss as a shaded area in Fig. 7a. Consequently, the gap between simulated and experimentally measured losses in the inverter is partly explained by the C OSS loss mechanism. Moreover, part of the additional losses are hypothesised to be due to dynamic on-resistance. This effect has been shown to affect GaN HEMTs. The magnitude of the increased effective resistance depends on the operating parameters. At works have investigated the effect on the average on-resistance in the megahertz range and with soft switching condition [START_REF] Li | Dynamic on-state resistance test and evaluation of GaN power devices under hard-and soft-switching conditions by double and multiple pulses[END_REF], [START_REF] Galapon | Measuring dynamic on resistance in GaN transistors at MHz frequencies[END_REF]. The results from these works indicate that the effective resistance can be increased up to a factor of 7. In conclusion, the experimental results are expected to show higher losses, and hence, lower efficiency than the simulated results.

The simulated versus experimental performance of the converter is also investigated in time domain by four measurements. Three voltages are measured (shown in Fig. 2 by probe symbols) using passive probes (TPP0200) -the output voltage of the half bridge, the voltage over C p and the voltage at the anode of the diode. The probe tip capacitance is added in the simulation model to account for probe loading. In addition, the current in L s is measured with a Rogowski coil (PEM CWT015). An example of the waveform comparison is shown in Fig. 7b. A good accordance is observed between the simulation and the measured signals. A difference is seen at the edges related to the reverse conduction of the half bridge. In addition to the measured overshoot, a slight difference in the reverse conduction voltage drop of the simulation model and the GaN chip can be observed. For the three other waveforms, the voltages and the current deviate slightly during transients containing harmonics. Yet, the simulation is deemed well within the needed accuracy, knowing that some increased losses should be expected. The goal is to identify the potential of the selected topology. Using the simulation model as input, an optimisation method can be utilised to obtain designs with maximised efficiency. The resulting converter design could then be tested experimentally to establish an expectation of the final converter performance.

IV. CONVERTER OPTIMISATION This section describes the optimisation procedure and the experimental results. The goal of the optimisation algorithm is defined through the objective functions. For the present paper, two such functions are defined. The first function maximises the converter efficiency, while the second one minimises the size of the transformer. The transformer size is defined as the radius of the outer circumference of the transformer windings. The largest value of either the primary or secondary side is selected. Minimising the transformer size is an indirect method of minimising the transformer coupling capacitance without adding additional simulation steps to quantify the capacitance value. Furthermore, a constraint for the output voltage is added. The optimisation problem is thus formulated as follows:

maximize x Obj 1 (x) = η dc-dc minimize x Obj 2 (x) = max(r prim , r sec ) subject to x ≥ x lowerbound x ≤ x upperbound V out,min ≤ V out (x) ≤ V out,max (20)
where x is a vector of variables of the optimisation with minimum and maximum values as defined by x lowerbound and x upperbound , η dc-dc is the converter efficiency, r prim and r sec are the outer radius of the transformer primary and secondary sides respectively, and V out is the converter output voltage.

The optimisation algorithm can vary the geometry of the transformer and the remaining passive elements of the con- verter. Changes to the transformer geometry results in variation in the lumped parameters, which in turn are used in the circuit simulation. In total, the multi-objective optimisation has 10 variables. The variable vector, x, is hence defined as

x = (N prim , N sec , w cu , r prim , r sec , L s , C p , C s , C rect , R load )
where N prim and N sec are the number of turns on the primary and secondary side respectively, w cu is the width of the copper track, r prim and r sec is the inner diameter of the primary and secondary respectively, and L s , C p , C s , C rect and R load are the component values of the circuit as indicated in Fig. 2. The load resistance is defined as an optimisation variable to ensure that an optimal efficiency point is found for any given combination of values for the other passive elements.

A genetic algorithm is chosen to identify the Pareto front of the converter. The algorithm, NSGA-II, is suitable for the multi-objective, mixed integer programming problem [START_REF] Deb | A fast and elitist multiobjective genetic algorithm: NSGA-II[END_REF]. Figure 8 shows the algorithm flow chart. Initialisation of the population is done using random sampling of all variables. During the evaluation step, each individual is evaluated in terms of efficiency and transformer size. First, the lumped parameters of the transformer are found by FEM simulation as described in the previous section. Following the FEM simulation, an LTSpice simulation is run with the circuit parameters of the individual to find the converter efficiency. The timedomain simulation runs for a sufficiently long time period so that steady-state conditions are reached. Since convergence cannot be guaranteed for all SPICE simulations, a time-out is set for each simulation. If the simulation does not finish in time, the individual is rejected by the algorithm. When both of the simulations are finished, the individuals are evaluated based on the objective functions. In addition, violation of the given constraints influences the evaluation of the individuals. The best individuals are chosen among the parents and the children to form the new generation. The algorithm continues to run until the generation number exceeds the maximum number set by the user.

For the optimisation procedure, a suitable use case is constructed that is based on the schematic diagram shown in Fig. 1 and which is summarised in Table IV. An auxiliary power supply provides power to a switching unit that consists either of a module in a MMC converter or several seriesconnected switches. Regardless of the switching unit, the power required would be similar at approximately 10 W [8, pp. 121-132]. The input voltage is set to a common dc bus voltage of 48 V while the output voltage constraint is set according to the driving voltage needed for the switches. For SiC MOSFETs, typical driving voltages are in the range of -5-0 V negative driving voltage to +15-20 V positive driving voltage. Hence, the output voltage constraint is set between 20-25 V. As insulation material, FR4 material is used with a thickness of 1.5 mm. This criterion is set to facilitate the production of the simulated transformers for prototyping. Future optimisations could include further details regarding the insulation scheme. The algorithm is launched with 100 individuals that are developed over 125 generations. Using a single processor, the simulation is carried out and the simulation time is approximately 3.5 days. The development of the optimisation with increasing generation number and the final generation are shown in Figs 9a and9b.

The 100 individuals forming the Pareto front achieves a peak system efficiency ranging from 78 % to above 87 % with a transformer radius of approximately 10 to 17 mm. It is observed that the efficiency obtained by the optimisation algorithm give substantially higher values than that for the initial prototype reported in Section III. The individuals are investigated in terms of average values of key parameters to identify the design trends that result in high efficiency. These values are presented in Table V. Common for all individuals is a transformer turns-ratio of 4:4 which maximises transformer coupling as discussed in Section II. Hence, the voltage conversion from 48 V input to 20-25 V output is achieved by different characteristics. It can be seen that the average resonance frequency of the rectifier, ω sec , is approximately 1.5 times higher than the operating frequency, thus increasing the voltage transfer function towards the peak value. Again, this is in line with the investigations in Section II. Since the turns ratio is the same for all individuals, the increased transformer size is mainly due to wider windings that result in lowered track resistance. In turn, the transformer and system efficiency increases. Moreover, the average resonance frequency of the primary side series resonance, ω 0 , is slightly higher than operating frequency. This is contrary to the circuit design derived from the analytic approach, where the resonance frequency is set to the operating frequency. An important finding that effects the converter implementation is that the inductance of the transformer can be decreased compared to the existing design method in literature [START_REF] Kazimierczuk | Resonant Power Converters[END_REF].

V. EXPERIMENTAL VALIDATION

From the final generation, several individuals are chosen to verify the simulation results. A multitude of prototypes serves to show that the simulation model is in fact a good representation for the actual circuit behaviour. Four individuals are chosen based on their total distance from all other individuals, excluding the outliers on each side. Similarly to the initial prototype, the air transformers are made on PCBs which are seen, together with the series inductors, L s , in Fig. 10a. Each series inductor was manually tuned to obtain the targeted inductance value. This method is time consuming, however, a more industrial product could use PCB printed or 3D printed toroids [START_REF] Sullivan | Design and fabrication of low-loss toroidal air-core inductors[END_REF], [START_REF] Liang | 3D printed air core inductors for high frequency power converters[END_REF]. An added benefit of the toroid structure will be the containment of the field inside the structure.

The measured component values and the error compared to the simulated values are shown for all four prototypes in Table VI. The inductance values are within 6% deviation from the simulated value, while the coupling coefficient is within ±1%. The capacitance values of the prototypes have little deviation compared to simulation as the capacitors are selected based on their measured capacitance value using the impedance analyser.

The efficiency and output voltage of the four prototypes are shown in Fig. 11. Figure 11a shows the change in output voltage as a function of the output power and the characteristic nose curve is observed. The minimum output power or current is limited thermally during testing as the inverter case temperature comes close to its maximum allowable value when operating without a heatsink. Figure 11b shows the efficiency as a function of output power. However, this way of presenting the efficiency leads to double points per output power. To present the data without double points, the efficiency is plotted as a function of output current in Fig. 11c, where zero current equals an open circuit condition and the maximum value equals a short circuit condition.

The maximum efficiency is measured to be 71.0%, 79.3%, 80.3%, 81.0%, ordered according to the prototype number and, hence, with increasing transformer size. All prototypes are able to supply over 10 W, with prototype #3 being able to supply more than 15 W. This fits well with the previously discussed application of the auxiliary power supply. Compared to [START_REF] Am | Design methodology for very high insulation voltage capabilities power transmission function for IGBT gate drivers based on a virtual prototyping tool[END_REF], [START_REF] Sarrazin | Insulated power supply for gate drivers up to 40 kV for medium-voltage direct current applications[END_REF], the proposed designs have the same or better efficiency while increasing both the output power and the air gap height.

The latter results in an increased insulating voltage of the isolated auxiliary power supply. The measured efficiency of the prototypes are lower than the values found in simulation (79.0%, 85.4%, 86.8%, 87.3%). The difference in efficiency between simulation and measured for prototypes #2-4 is approximately 6-7%. As shown with the initial prototype, increased losses should be expected for the experimental setup due to the modelling of the inverter. As discussed in Section III, the simulation model consistently underestimated the losses in the inverter due to the phenomena of dynamic on-resistance of GaN HEMTs. The additional inverter losses measured for all prototypes accounts for the missing percentage points in the measured efficiency compared to the simulated efficiency. The larger efficiency gap of prototype #1 is likely related to the thin track width of prototype #1. The track width of this individual is only 0.2 mm, making the performance sensitive to small variations in track width due to the manufacturing resolution of the in-house etching technique. This is verified as the measured resistance values of the PCB transformer are found to be 15% higher than simulated. The converters appear to loose their soft switching operation when the load goes towards an open circuit. Other practical converter constraints like nose curve shape, inverter temperature and soft switching operation should be included in future optimisations either as separate simulations or by simplified analytic expressions.

The main difference between prototypes #1-3 is the track width, which only slightly decreases the transformer inductance and winding resistance while the coupling slightly increases. Prototype #1 differs from the other prototypes by having a resonance of the primary side higher than the operating frequency (8.65 MHz) whereas prototypes #2-4 are close to the operating frequency (6.99, 6.85, and 6.79 MHz, respectively). For the secondary side, prototypes #1-3 are similar (8.18, 8.57, 8.58 MHz, respectively) whereas prototype #4 has a larger resonance frequency of 11.54 MHz. The maximum output power and variations in the output voltage with load resistance are observed to change for different design configurations. Desired converter characteristics could be added to the optimisation algorithm to further develop the design space in the desired direction. It is hypothesised that the shapes of the nose curves of prototypes #1-3 are similar due to similar impedance values on the rectifier side. Their differences in resistance and coupling gives the premise for the maximum power output and efficiency.

The coupling capacitance of the transformer is indirectly included in the optimisation algorithm since the transformer area is minimised. The coupling capacitance was modelled using FEMM and measured experimentally for the four prototypes. Simulated and measured values are given in Table VII. From measurements, it is found that the coupling capacitances are in the range of 8 to 14 pF, which is higher than compared to the literature [START_REF] Am | Design methodology for very high insulation voltage capabilities power transmission function for IGBT gate drivers based on a virtual prototyping tool[END_REF], [START_REF] Sarrazin | Insulated power supply for gate drivers up to 40 kV for medium-voltage direct current applications[END_REF]. Part of this capacitance is related to the higher value of r of FR4 that is used as the dielectric material in this work. All measured values are 3 to 5 pF higher than the simulated values due to the simplified geometry of the simulation model and possibly the exact value of r for the prototypes. In view of these aspects, the measured values correspond well to the simulation. The coupling capacitance appears to be proportional to the area of the transformer windings, as can be expected. The optimisation algorithm could be modified by adding a simulation of the coupling capacitance to calculation this value directly. Although, minimisation of the transformer size, in particular the surface area, also minimises the coupling capacitance. Similarly, increasing the distance between the primary and secondary side also decreases the coupling capacitance.

Prototype 4 is tested in a setup that is similar to the target application. The setup is shown in Fig. 10b, where the prototype power supply provides power to four Cree SiC MOSFET drivers (CRD-001). Each driver is loaded with a 220 nF capacitor, which is equivalent to the gate capacitance of modern 3.3 kV SiC MOSFET high power module. The switching frequency of the driver load is varied from 1 to 20 kHz to vary the loading of the prototype converter. The resulting load line of the prototype converter is shown in Fig. 11d. A drop in the output voltage from 26 to 21.2 V is observed over the whole power range. However, the output voltage at 9 W is only 23.8 V, a voltage drop of less than 10 %.

Based on the transformer geometry of the experimental prototypes, a comparison is made with similar works regarding the insulation voltage. The comparison is summarised in Table VII. For this work, the breakdown voltage of the insulation barrier is estimated using published experimental data for different materials and material thicknesses combined with the gap distances between the primary and secondary side [START_REF] Sarrazin | Insulated power supply for gate drivers up to 40 kV for medium-voltage direct current applications[END_REF]. For the prototypes, the insulating material is FR4, which results in a breakdown voltage of 32 kV peak . If polyesterimide or Teflon material of 1.5 mm thickness is used instead, breakdown voltages of approximately 48 and 80 kV are obtained. Furthermore, the dielectric constant of these materials, 3.5 [START_REF] Fetouhi | Electric conductivity, aging and chemical degradation of polyesterimide resins used in the impregnation of rotating machines[END_REF] and 2.0 [START_REF] Ehrlich | Dielectric properties of teflon from room temperature to 314 • C and from frequencies of 10 2 to 10 5 c/s[END_REF] respectively, would result in a decreased coupling capacitance down to a half with respect to the case of FR4. This results in coupling capacitances in the range of 4-9 pF for the prototypes in this work.

VI. CONCLUSION

This paper presents the design and optimisation of a suitable topology for an isolated DC-DC auxiliary power supply with high isolation voltage and low coupling capacitance. The converter consists of a GaN HEMT inverter operating at 6.78 MHz, an LCC resonance tank, a coreless transformer and a class E low dv/dt rectifier. In regard to the application, the converter is suitable for supplying gate drivers in medium voltage converters. A design methodology is developed, however, SPICE investigations show that optimal designs might lie outside the validity of the design equations. In particular, the rectifier shows preferential characteristics when designed with a resonance frequency higher than the operating frequency (ω res ≥ 1.6); the output voltage regulation improves and the inductor size is reduced. A virtual prototyping tool is developed based on a genetic algorithm that is used in an holistic optimisation of the converter. The optimisation algorithm maximises the converter efficiency while minimising the coupling capacitance. Using the developed Pareto front, the best performing prototype exhibits a peak efficiency of 81% when supplying 15 W of power. The prototypes all have smaller transformer sizes, and hence, lower coupling capacitance compared to the existing design method in literature [START_REF] Kazimierczuk | Resonant Power Converters[END_REF]. Moreover, the coupling capacitances of the prototypes are found through measurement in the range of 7 to 18 pF. However, if a more suitable dielectric material like Teflon is used, the coupling capacitance is halved and coupling capacitances below 10 pF can be obtained. At the same time, using Teflon as insulation material could increase the isolation voltage up to 80 kV. * Peak insulation voltage is estimated using the experimental data on breakdown voltages for different materials and material thicknesses found in [START_REF] Sarrazin | Insulated power supply for gate drivers up to 40 kV for medium-voltage direct current applications[END_REF].

APPENDIX

This section shows a numerical example using the analytical design method given in Section II. For the example, the input voltage is set to 48 V while the desired output voltage is chosen to 20 V for the maximum load requirement of 10 W. Firstly, the rectifier passive components are found according to (1), ( 2) and (3). where ω 0 equals 2π • 6.78 MHz and the values of Q r and M V are given as 0.3884 and 0.3684 in [START_REF] Kazimierczuk | Resonant Power Converters[END_REF] for the maximum output-power capability of the rectifier. Then, the input voltage is found using (4):

V m = 20 V 0.3684 = 54.29 V

In the following step, C p is found. However, this requires that the coupling factor of the transformer is known. For the example, it is assumed that the factor is 0.6. Furthermore, L prim is assumed equal to L sec . From (13), C p becomes:

C p = π • 54.29 V √ 2 • ω 2 0 • 0.6 • 2.418 µH • 48 V = 0.9545 nF
The corresponding I prim is found to be 0.88 A. Using [START_REF] Nguyen | Gate driver supply architectures for common mode conducted EMI reduction in series connection of multiple power devices[END_REF], L s evaluates to: • The input source, V in , is a trapezoidal voltage that changes between 0 and 48 V with rise and fall times of 10 ns.

• The diode has no junction capacitance, and is modelled with R on and R of f of 50 mΩ and 10 MΩ, respectively. • All passive components have zero resistance. For the design case, the output voltage of the full circuit evaluates to 21.11 V compared to 20.57 V for the reference circuit, an error of 2.6%. The error for changing transformer coupling is shown in Fig. 12. The error in output voltage is small for a coupling factors up to approximately 0.7. Above this value, the second harmonic generated by the rectifier influences the converter behaviour and the calculations become less accurate. Nevertheless, the coupling factor of coreless transformers are usually lower than 0.7. Additionally, it is seen that the switching current also has a slight offset meaning that tweaking of the C s value is likely needed for the final converter design. Moreover, the error between the positive and negative current is asymmetric due to the second harmonic content in the inverter current.

Figure 13 shows the behaviour of the rectifier output with changing load condition. The increasing voltage and power with increasing load resistance are characteristics of a current source. In many cases, a voltage source behaviour is preferred over the current source behaviour.

Fig. 1 .

 1 Fig. 1. Conceptual diagrams of the application -supplying power to the gate drivers in a medium voltage converter arm. The arms of the medium voltage converter consist of either a) submodules (SM) in a multilevel converter or b) series-connected switches. The auxiliary power supply targeted in the paper is shown in bold.

1 Fig. 2 .Fig. 3 .

 123 Fig. 2. Schematic diagram of the converter topology consisting of a half bridge inverter, an LCC resonance tank, coreless transformer and a class E rectifier. The probe signals indicate the voltage measurement points in the experimental setup for time domain comparison.

Fig. 4 .

 4 Fig. 4. Results from SPICE simulations of the rectifier circuit assuming ideal components. The a) voltage transfer function, b) output voltage variation and c) relative 2nd harmonic in the current are plotted as a function of output power. d) shows the values for the resonance components.

Fig. 5 .Fig. 6 .

 56 Fig. 5. Modelling of a coreless transformer printed on PCB. a) Axisymmetric geometry and FEM modelling of the PCB transformer cross section. b) Example view of magnetic density calculation for the transformer in FEMM.

Fig. 7 .

 7 Fig. 7. Comparison of simulated and experimental results of the initial prototype operating with 48 V input voltage. The solid lines are the measured signals and the dashed lines are the simulated signals. a) DC-DC efficiency, output power and inverter losses with varying load resistance. Additionally, variation in output voltage with output power is also shown. b) Waveforms in time domain from the prototype operating with a 35 Ω load.

Fig. 8 .

 8 Fig. 8. Flow chart for the genetic algorithm used for the design optimisation.

Fig. 9 .

 9 Fig. 9. Developed and identified Pareto front using the genetic algorithm. a) Development over several generations. The later generations move down right and form a Pareto front. b) The last generation showing the Pareto front and the realised prototypes.

Fig. 10

 10 Fig. 10. a) Transformers and series inductors for the four prototypes used in the experimental validation. b) Photo of prototype 4 and the load on the output consisting of four Cree SiC MOSFET drivers (CRD-001).

Fig. 11 .

 11 Fig. 11. Experimental results from the four prototypes. a) Efficiency as a function of output power for varying load resistance. b) Output voltage variation as a function of output. c) Efficiency as a function of output current. d) The load line of prototype #4 while powering four Cree SiC MOSFET drivers with capacitive loads, where the output power varies with the driver switching frequency.

  The values of L i is set as 0.814 • L[START_REF] Kazimierczuk | Resonant Power Converters[END_REF]. With a target switching current of -1.25 A, the series capacitor is calculated according to[START_REF] Mainali | Design and evaluation of isolated gate driver power supply for medium voltage converter applications[END_REF]:C s = 0.9545 nF π • 24.59 Ω • (-1.25 A) √ 2 • 48 V + 2.418 µH 0.577 µH + -46.27 Ω 24.59 Ω -π 2 8 = 0.471 nFThe component values are evaluated using SPICE simulations for modelling the reference circuit[START_REF] Kazimierczuk | Resonant Power Converters[END_REF]. Moreover:

Fig. 12 .

 12 Fig.[START_REF] Peftitsis | Auxiliary power supply for medium-voltage modular multilevel converters[END_REF]. Absolute error between the proposed topology and the reference circuit for the output voltage and the inverter current at the switching instant, I inv,sw , for either falling (pos) or rising (neg) edge of the inverter output voltage.

Fig. 13 .

 13 Fig. 13. The inverter output voltage and power as a function of load resistance.

TABLE II PARAMETERS

 II OF THE PROTOTYPE CONVERTER USED FOR VALIDATION OF THE SIMULATION MODEL.

		Component Inverter	Ls	Cp	Cs L prim Lsec coupling Crect Cout	Diode
			-	nH	pF	pF	nH	nH	-	pF	nF	-
		Value	LMG5200 473 981 330	1379	240	0.48	330	100	STPSC406B
		TABLE III
	COMPARISON OF TRANSFORMER CHARACTERISTICS BETWEEN FEMM
	SIMULATION AND THE ESTIMATED VALUES FOUND THROUGH IMPEDANCE
		MEASUREMENT.
	Parameter	Value	Value		Error
		FEM design experimental
	L prim	1369 nH	1379 nH	1%
	Lsec	210 nH	240 nH		15%
	coupling	0.48	0.48		-

TABLE IV USE

 IV CASE FOR THE OPTIMISATION ALGORITHM.

TABLE V AVERAGE

 V VALUES OF KEY PARAMETERS OF THE PARETO FRONT THAT IS PLOTTED IN FIG. 9B.

	N prim : Nsec	w 0	wsec	Ls	L prim	Lsec	Cp	Cs	Crect	coupling
		MHz	MHz	nH	nH	nH	pF	pF	pF
	4 : 4	7.28	10.64 460	419	431	1049 1310	540	0.62
		D =32 4		D 3 =27 mm
		D 2 =27 mm		D 1 =27 mm

TABLE VI COMPARISON

 VI OF COMPONENT VALUES BETWEEN SIMULATION AND THE EXPERIMENTAL SETUP.

			Experimental value (error %)
	Prototype	#1	#2	#3	#4
	Ls [nH]	468 (1%)	501 (1%)	502 (2%)	469 (2%)
	L prim [nH]	395 (3%)	392 (5%)	388 (6%)	561 (4%)
	Lsec [nH]	395 (4%)	380 (6%)	377 (6%)	573 (5%)
	coupling	0.57 (1%)	0.64 (-1%)	0.68 (<1%)	0.71 (-1%)
	Cp [pF]	724 (<1%)	1036 (<1%)	1075 (4%)	1170 (3%)
	Cs [pF]	1347 (<1%)	1379 (-1%)	1376 (-1%)	1199 (-1%)
	Crect [pF]	859 (2%)	808 (<1%)	813 (1%)	232 (-1%)
	C coupling (sim / exp) [pF]	4.5 / 7.6	8.1 / 11.8	10.7 / 14.8	13.8 / 18.3

TABLE VII EVALUATION

 VII OF THE ISOLATION VOLTAGE AND TRANSFORMER GEOMETRY COMPARED TO OTHER PUBLISHED WORK.

	Publication	Gap	Radius -	Radius -	Peak	Isolation	Insulation
		distance ferrite or winding dielectric efficiency	voltage	material
		[mm]	[mm]	[mm]		[kV peak ]
	[16]	1.0	7	50	70 %	40	Teflon
	[10]	13	40	86	90 %	95	Polyurethane
						*32	FR4
	This work	1.5	10-17	-	71-81 %	*48 Polyesterimide
						*80	Teflon

ACKNOWLEDGMENTS

This work is the result of research stays at both G2Elab, Grenoble, France and Stanford University, Stanford, USA, for which both institutions are thanked.

The authors acknowledges the funds received through the Norwegian Research Council grant 243711 and the travel scholarship from The Fund of the Norwegian Institute of Technology. Multilevel module SM SM V DC+ V DC-


Bo Yang
email: boyang@sutd.edu.sg

Xuelin Cao
email: xuelincao@sutd.edu.sg

Chongwen Huang
email: chongwenhuang@zju.edu.cn

Fellow, IEEE Chau Yuen
email: yuenchau@sutd.edu.sg

Senior Member, IEEE Lijun Qian
email: liqian@pvamu.edu

Fellow, IEEE Marco Di Renzo
email: marco.di-renzo@universite-paris-saclay.fr

Intelligent Spectrum Learning for Wireless Networks with Reconfigurable Intelligent Surfaces

Keywords: Reconfigurable intelligent surface, intelligent spectrum learning, convolutional neural network

Reconfigurable intelligent surface (RIS) has become a promising technology for enhancing the reliability of wireless communications, which is capable of reflecting the desired signals through appropriate phase shifts. However, the intended signals that impinge upon an RIS are often mixed with interfering signals, which are usually dynamic and unknown. In particular, the received signal-to-interference-plusnoise ratio (SINR) may be degraded by the signals reflected from the RISs that originate from nonintended users. To tackle this issue, we introduce the concept of intelligent spectrum learning (ISL), which uses an appropriately trained convolutional neural network (CNN) at the RIS controller to help the RISs infer the interfering signals directly from the incident signals. By capitalizing on the ISL, a distributed control algorithm is proposed to maximize the received SINR by dynamically configuring the active/inactive binary status of the RIS elements. Simulation results validate the performance improvement offered by deep learning and demonstrate the superiority of the proposed ISL-aided approach.

I. INTRODUCTION

Due to the dynamic nature of the wireless environment that results in severe signal fluctuations caused by multipath fading and the presence of large obstacles, the wireless link between a desired cellular user and a base station (BS) may not be reliable enough or may even undergo a complete outage. To tackle this issue, reconfigurable intelligent surfaces (RISs) have been proposed to improve the received signal-to-interference-plus-noise ratio (SINR) at the users by appropriately reflecting the incident signals and generating directional beams [START_REF] Renzo | Smart radio environments empowered by reconfigurable AI meta-surfaces: An idea whose time has come[END_REF].

In the literature, some preliminary works investigated the optimization of RIS-assisted wireless communications. In [START_REF] Huang | Reconfigurable intelligent surfaces for energy efficiency in wireless communication[END_REF], a joint transmit power allocation and phase shift design was developed to maximize the energy efficiency. In [START_REF] Wu | Intelligent reflecting surface enhanced wireless network via joint active and passive beamforming[END_REF], the authors considered a downlink RIS-assisted multiuser communication system and studied a joint transmission and reflection beamforming problem to minimize the total transmit power. In [START_REF] Kang | Intelligent reflecting surface: joint optimal training sequence and refection pattern[END_REF], the channel estimation problem was investigated for an RIS-aided wireless communication system by jointly optimizing the training sequence of the transmitter and the reflection pattern of the RIS.

Furthermore, an RIS-assisted anti-jamming solution was proposed for securing wireless communications via reinforcement learning [START_REF] Yang | Intelligent reflecting surface assisted anti-jamming communications based on reinforcement learning[END_REF]. In [START_REF] Bai | Latency minimization for intelligent reflecting surface aided mobile edge computing[END_REF], the authors introduced RISs in mobile edge computing systems, where a joint design of computing and communications was developed to minimize the computational latency.

However, most of the existing works assume either that no interference exists, which rarely occurs in practice, or that the interference is known and can be taken into account, which is not trivial to estimate since the interference is usually dynamically changing. These issues are exacerbated in RISaided systems, since they are nearly-passive surfaces with no active sensing capabilities for channel and interference estimation [START_REF] Di Renzo | Smart radio environments empowered by reconfigurable intelligent surfaces: how it works, state of research, and the road ahead[END_REF]. In order to elucidate the problem at hand, let us consider the case study depicted in Fig. 1(a), in which we consider a practical scenario where all the RISs serve one desired user (e.g., U 1 ). In the analyzed case study, the other users (e.g., U l , l ∈ [2, L]) are considered as interfering users for U 1 at each RIS. As a result, the signal reflected by each RIS is a mixture of the desired signal from U 1 and the interfering signals from the other users. In this context, the received SINR at the BS via an RIS that does not account for the interfering signals could be even worse than the SINR of the direct link. This impact of the interference is, in particular, more severe if the interfering devices are close to the desired user, e.g., in Fig. 1(a) U 2 may cause severe interference to U 1 at RIS 1 when the angle between them (i.e., λ) is small.

To overcome these challenges, in this paper, we empower a conventional RIS-assisted wireless system with 'intelligent spectrum learning (ISL) capabilities', by leveraging appropriately trained convolutional

II. SYSTEM MODEL AND PROBLEM FORMULATION

We consider an RIS-assisted uplink wireless system that consists of one BS, a set K of K RISs, and a set L of L users, where K ≥ 1 and L > K usually hold. We assume that the BS allocates all the 1 In this paper, the ON-OFF status is referred to having the entire RIS ON or OFF, i.e., either all the elements of the RIS are turned ON or all the elements of the RIS are turned OFF.

RISs to serve one user at a time in order to improve the quality of the wireless link. Also, the direct links between the users and the BS are available. Under these assumptions, all the other users act as interferers for the intended user either through the direct links or through the links reflected by the RISs.

Each RIS operates as a nearly-passive surface, i.e., the RIS elements are passive but the RIS controller may consume power [START_REF] Huang | Holographic MIMO surfaces for 6G wireless networks: opportunities, challenges, and trends[END_REF]. In particular, the RIS controller is equipped with a CNN, as shown in Fig. 1(b).

The CNN is discussed in the next sections.

A. RIS-Assisted Communication Model

Each RIS, denoted as R k , k ∈ K, is equipped with N k reflecting elements, which can be appropriately configured by the RIS controller to reflect the signals of the users towards the BS. In general, the RISs can be appropriately deployed so that line-of-sight (LoS) links can be established with the BS and, possibly, the users. We assume that the channel state information (CSI) of all channels involved is perfectly known at the BS2 , which, in turn, can feed back the CSI to the RIS controller via a dedicated control channel [START_REF] Wu | Intelligent reflecting surface enhanced wireless network via joint active and passive beamforming[END_REF], [START_REF] Bai | Latency minimization for intelligent reflecting surface aided mobile edge computing[END_REF].

Each RIS can be in two possible states: ON and OFF. We introduce a binary variable

β k ∈ {0, 1}
to indicate the ON-OFF state of R k . β k = 1 indicates that R k is ON, which means that it reflects the incident signals, while β k = 0 indicates R k is OFF, which means that it does not reflect any signals.

As for the kth RIS that is ON, the amplitude reflection coefficient is assumed to be equal to one for all the N k reflecting elements and the phase reflection matrix is

Φ k = diag e jθ k 1 , e jθ k 2 , ..., e jθ k N k , (1)
where

Θ k = θ k 1 , θ k 2 , .
.., θ k Nk denotes the vector of phase shifts that can be optimized by R k .

B. Wireless Channel Model

We consider an RIS-aided uplink wireless system, where the channels from the desired user (denoted as U l ) to R k , from R k to the BS, and from the mth interfering user (denoted as

U m , m ∈ L, m = l) to R k , are h l,k ∈ C Nk×1 , g k ∈ C 1×Nk ,
and h m,k ∈ C Nk×1 , respectively. The channel gains of the direct links from U l to BS and from U m to BS are denoted by h d,l and h d,m , respectively. These channels are assumed to be perfectly estimated and quasi-static, hence remaining nearly-constant during the transmission time [START_REF] Wu | Intelligent reflecting surface enhanced wireless network via joint active and passive beamforming[END_REF].

Without loss of generality, we assume that the users are randomly distributed and have time-varying traffic demands. This implies that the users may not be all active during the considered transmission time 3 . In particular, the total number of interfering users for U l is given by ω l = m∈L,m =l α m , where α m ∈ {0, 1} is a binary variable that indicates that U m is active (α m = 1) or inactive (α m = 0) and therefore can cause or not interference to U l , respectively. Accordingly, the set of active interfering users is W = {U m |α m = 1}, where ∀m = l and ∀m ∈ L.

Since the number of active interferers is dynamic, it is not easy to estimate the interference distribution over time. The received signal at the BS depends on the desired signal sent from U l (including the direct link and the link reflected by the RIS), the interference from the interfering users in W, and the white Gaussian noise:

y l = h d,l + K k=1 β k g k Φ k h l,k √ p l s l Desired signal from Ul + m∈W h d,m + K k=1 ξ k m,l β k g k Φ k h m,k √ p m s m Interference from other users +n l , (2)
where p l and p m denote the transmit power of U l and U m , respectively, s l and s m are the unit-power information signals sent from U l and U m , respectively, and n l ∼ CN (0, σ 2 ) is the white Gaussian noise.

In addition, ξ k m,l ∈ [0, 1] accounts for the impact of the interference caused by U m to U l and that is associated to the kth RIS, as clarified in Assumption 1.

Assumption 1. We assume that the impact of the strength of the interference reflected by an RIS is inversely proportional to the difference of the angles of incidence between the desired user and the interfering users at the RIS (see λ in Fig. 1(b) for an example).

C. Problem Formulation and Analysis

Let B = {β 1 , β 2 , ..., β K } denote the RIS binary decision vector that collects the binary variables that identify the ON-OFF status of the RISs. The set of RISs that are active is

R = {R k |β k = 1} , ∀k ∈ K.
Accordingly, the SINR at the BS for the intended user U l is

γ l = p l h d,l + K k=1 β k g k Φ k h l,k 2 ωl m=1 p m h d,m + K k=1 ξ k m,l β k g k Φ k h m,k 2 +σ 2 . ( 3
)
Our objective is to maximize the SINR in (3), by optimizing the RIS binary activation vector (B), and the phase shifts matrix of the active RISs which is denoted as Θ = {Θ 1 , Θ 2 , ..., Θ K } . To this end, we need to solve the following optimization problem: Constraint (4b) indicates that the kth RIS can only be ON (i.e., β k = 1) or OFF (i.e., β k = 0) at one time. Constraint (4c) indicates that each RIS reflecting element can only provide a phase shift θ i n ∈ [0, 2π) without amplifying the signals.

P 1 : max B,Θ γ l (4a) s.t. β k ∈ {0, 1} , ∀k ∈ K, (4b)
e jθ i n = 1, ∀n ∈ [1, N i ], ∀i ∈ R. ( 4c
) USRP2 User-1 USRP2 BS USRP2 ...
Our Proposal: We observe that P 1 is an MINLP, which is NP-hard and whose global optimal solution is, in general, difficult to obtain. In addition, traditional optimization methods may be computationally intensive. An emerging approach to tackle this issue is to apply deep learning methods to solve P 1 at a reduced computational complexity [START_REF] Yang | Computation offloading in multi-access edge computing: a multi-task learning approach[END_REF], [START_REF] Huang | Reconfigurable intelligent surface assisted multiuser miso systems exploiting deep reinforcement learning[END_REF]. P 1 , however, may not be easy to solve even using deep learning methods, since the number of interfering users is a random variable that is unknown. In addition, during the channel estimation phase, the RISs cannot estimate on their own the active interferers because they only reflect the incident signals in a passive manner. This makes the solution of P 1 even more difficult. To address this challenge, we propose a distributed control mechanism that solves P 1 with the aid of the ISL algorithm.

III. DISTRIBUTED RIS CONTROL VIA INTELLIGENT SPECTRUM LEARNING

In this section, the ISL-aided distributed RIS control mechanism is introduced. The proposed approach leverages appropriately trained CNNs at the controller of the RISs, which can identify the active interfering users in a distributed way.

A. Intelligent Spectrum Learning

ISL is a multi-class classification algorithm that, based on a CNN, returns the set of interfering users for each intended user U l . To design the ISL algorithm, three main aspects need to be discussed: 1) RF traces collection, 2) offline CNN training, and 3) online CNN inference.

1) RF Traces Collection: As far as the RF data collection phase is concerned, historical RF traces are collected using a universal software radio peripheral (USRP2) testbed, which is wired connected (e.g., Gigabit Ethernet) to a host PC with an implementation of the GNU Radio, as illustrated in Fig. 2 By performing feed-forward calculation via the CNN model (i.e., online inference), the intefering users set for the desired user U l is obtained as

I l =      {U m | α m = 1}, ∀m ∈ L, ∀m = l, If ω l ≥ 1, ∅, If ω l = 0, (5)
where α m denotes the inferred state flag of U m , and ω l indicates the inferred total number of intefering users in the incident signal.

4) An Illustrative

B. Distributed RIS Binary Control

By feeding the inferred set of interfering users into the distributed RIS binary control algorithm, the corresponding phase shifts and the binary ON-OFF status of the RISs can be obtained, as illustrated in Fig. 2.

1) Optimal Phase Shifts Calculation:

To calculate the phase shifts at the RIS, we denote the obtained CSI associated to the kth RIS as

C k = {h l,k , h m,k , g k , h d,l , h d,m }.
Based on the inferred interfering users (including I l and ω l ) obtained via the trained CNN, the received SINR of the signal sent from U l is given by

γ l = p l h d,l + K k=1 β k g k Φ k h l,k 2 ωl m=1 p m h d,m + K k=1 ξ k m,l β k g k Φ k h m,k 2 +σ 2 . ( 6
)
Based on (6), we first obtain the phase shifts of each RIS under the assumption β k = 1, ∀k ∈ K, and then optimize the optimum binary ON-OFF vector B based on the obtained phase shifts. The first step, in particular, can be formulated as

P 2 : max Θ γ l (7a) s.t. β k = 1, ∀k ∈ K, (7b)
e jθ k n = 1, ∀n ∈ [1, N k ], ∀k ∈ K. (7c)
We observe that P 2 is a non-convex problem, which can be tackled by using several methods, such as the semidefinite relaxation (SDR) method [START_REF] Wu | Intelligent reflecting surface enhanced wireless network via joint active and passive beamforming[END_REF] and the successive convex approximation (SCA) method [START_REF] Yang | Energy-efficient wireless communications with distributed reconfigurable intelligent surfaces[END_REF].

The optimal solution for the kth RIS is denoted by Θ * k , and the corresponding reflection-coefficient matrix is Φ * k . With the obtained reflection-coefficient matrix, each RIS ON-OFF status is optimized via the following RIS binary control algorithm.

2) Distributed RIS Binary Control Algorithm: Assuming that only the kth RIS is ON, i.e., β k = 1, the received SINR of the signal sent from U l to the BS via the kth RIS is

γ k l = p l |h d,l + g k Φ k h l,k | 2 ωl m=1 p m h d,m + ξ k m,l g k Φ k h m,k 2 + σ 2 . ( 8
)
If, on the other hand, all the K RISs are OFF, i.e., β k = 0 for k ∈ K, the received SINR of the signal sent from U l to the BS via the direct link is

γ D l = p l |h d,l | 2 ωl m=1 p m |h d,m | 2 + σ 2 . (9)
Based on ( 8) and ( 9), the kth RIS decides whether to be ON or OFF as detailed in Remark 1.

Remark 1. The kth RIS should be ON if γ k l ≥ γ D l holds. This indicates, in fact, that the desired signal from U l can be enhanced via the kth RIS. Otherwise, the kth RIS should be OFF to avoid the degradation of the desired signal. In this case, the incident angle between the signals of the desired user and the interfering signals at the RIS is in general small.

The approach for solving P 2 is summarized in Algorithm 1, which is executed at each RIS controller when the incident signal is received. Specifically, upon receiving the incident signal, each RIS controller identifies the set of interfering devices by extracting the I/Q samples from a copy of the incident signal and feeding them into the trained CNN. Based on the classification outcome of the CNN, the RIS controller can set the RIS ON-OFF state in a distributed manner.

3) Computational Complexity: The total computational complexity includes the online inference via the CNN and the iterative algorithm to solve the phase shift optimization problem P 2 and the RIS ON-OFF optimization problem.

• Complexity for CNN online inference: The CNN is trained offline in a supervised fashion, therefore the complexity of training can be ignored. The trained CNN model has a quadratic time complexity Calculate γ k l and γ D l via ( 8) and ( 9), respectively;

6:

if γ k l ≥ γ D l then 7:
Keep the kth RIS ON, i.e., β k = 1;

8: else if γ k l < γ D l then 9:
Turn the kth RIS OFF, i.e., β k = 0; Add the kth RIS binary decision β k to B.

12: end while during the inference process, i.e., O(M 2 CK), where C denotes the number of layers, M denotes the number of neurons, and K denotes the total number of RISs.

• Complexity for solving the phase shift optimization problem P 2 : To solve the problem P 2 , the complexity lies in computing the optimal phase shift at each iteration of the optimization method, e.g., the SCA method [START_REF] Yang | Energy-efficient wireless communications with distributed reconfigurable intelligent surfaces[END_REF] whose complexity is O(Qz), where Q = K k=1 N k denotes the total number of elements of all the RISs, and z is the total number of the iterations required.

• Complexity for solving the RIS ON-OFF optimization problem: Since γ k l and γ D l need to be calculated via [START_REF] Huang | Holographic MIMO surfaces for 6G wireless networks: opportunities, challenges, and trends[END_REF] and [START_REF] Zappone | Overhead-aware design of reconfigurable intelligent surfaces in smart radio environments[END_REF], respectively, the computational complexity of solving the RIS ON-OFF optimization problem required at each RIS controller is O(K).

As a result, the total complexity is O(M 2 CK + Qz + K), which grows linearly with the total number of RISs.

IV. SIMULATION RESULTS

In this section, we first evaluate the inference accuracy of the trained CNN model and the computational complexity of the proposed ISL-based DRBC algorithm. Then we validate the benefits of deploying the ISL-based DRBC algorithm.

B. Computation Time

The proposed ISL-based DRBC algorithm allows us to obtain the optimal ON-OFF status of each RIS.

As detailed in previous text, the optimal ON-OFF status of the RISs can be formulated as the solution of a non-convex MINLP, which is usually challenging to solve [START_REF] Yang | Energy-efficient wireless communications with distributed reconfigurable intelligent surfaces[END_REF]. In this section, we compare the proposed ISL-based DRBC algorithm against the spatial branch and bound (sBB) method, which is often employed to solve non-convex MINLP [START_REF] Belotti | Branching and bounds tightening techniques for non-convex MINLP[END_REF], in terms of computation time.

The comparison of the average computation time (defined as t =

Total time consumption

Total number of computations ) between the proposed ISL-based DRBC algorithm and the traditional sBB method is conducted on the same hardware platform that consists of an Intel Xeon(R) CPU E5-2650@2.0 GHz x 16. The obtained results are illustrated in Table III. Compared to the traditional sBB method, the ISL-based DRBC algorithm results in much lower computation time while still yielding the optimal ON-OFF status for each RIS.

The computation time of the proposed algorithm is less than one-thousandth of the computation time of the sBB method when the number of RISs varies from 2 to 5. The incident angle between the BS and U 1 at the RIS is 150 o , and the incident angle between U 2 and

U 1 is λ ∈ [0, 150 o ].
We assume that ξ k m,l is linearly inversely proportional to λ. The channel parameters are selected according to the 3GPP Urban Micro standard [START_REF]Further advancements for E-UTRA physical layer aspects (Release 9)[END_REF], which describes the path loss for both line-of-sight and non-line-of-sight components [START_REF] Zhang | Reconfigurable intelligent surfaces assisted communications with limited phase shifts: How many phase shifts are enough?[END_REF]. The transmission power of U 1 is 20 dBm, the noise power σ 2 is -94 dBm, the carrier frequency is 3 GHz, and the reflection amplitude is equal to one.

2) Simulation Results: We evaluate the performance of the proposed ISL-aided algorithm by comparing it with two benchmarks: 'RIS always ON' and 'RIS always OFF'. Figs. 3(a)-(b) depict the achievable SINR versus the angle of incidence (λ) for K = 1 and p m = 10, 15, 20 dBm. We observe that the SINR first gradually decreases as λ increases due to the reduction of the distance between U 2 and BS, and then increases due to the perfect interference elimination at the RIS. When λ is small in particular, the RIS is prone to be OFF since the interference reflected via the RIS is more pronounced. If λ is large, on the other hand, the impact of the interference is reduced and it is more probable that the RIS is ON. In general terms, however, the impact of λ on the system performance is still an open issue, whose analysis is postponed to a future research work.

Fig. 1 :

 1 Fig. 1: In (a), a traditional multiple-user uplink RIS-assisted wireless communication system with K RISs is shown, where we assume that L users transmit to the BS at same time and frequency, and all RISs serve one user at a time. So, the other users are considered as interferers. In (b), the proposed ISL-enabled RIS-assisted wireless communication system is shown. Each RIS controller is deployed with a trained CNN model to identify the interfering users from the incident RF signals, so as to optimize the operation of the RISs in a distributed way.

Fig. 2 :

 2 Fig. 2: RF trace collection scenario is shown in (a), where L transceivers (users) are scheduled for transmission towards a receiver (BS). The proposed ISL-aided RIS control structure is shown in (b), where the input to the CNN is the incident RF signals and the output is the set of interfering users.

  (a). In particular, the users are emulated through a laptop that is mainly responsible for baseband processing while a USRP2 platform is used for the up-conversion, the digital-to-analog (D/A) conversion, and wireless transmission of the signals. As far as the BS is concerned, another USRP2 module first receives the signals from the radio interface and then performs A/D and down-conversion. Subsequently, the laptop receives the signals from the USRP2 via the Ethernet and executes the baseband processing. Finally, the Inphase (I) and Quadrature (Q) sequences are stored as a file. In particular, the experimental setup for RF data collection using the USPR2 is performed by using signals at 2.4 GHz carrier frequency with 1 MHz bandwidth. In order to collect realistic RF signals in the presence of interference, we let multiple USRP2 units transmit RF signals to an USRP2 receiver. The RF traces have been collected as I/Q sequences, by including the wireless channel, for a wide range of SNR (e.g., from 0 to 20 dB with interval of 5 dB) in order to account for different interfering cases[START_REF] Yang | A machine learning enabled MAC framework for heterogeneous Internet-of-Things networks[END_REF]. 2) CNN Offline Training: The acquired RF traces have been used for training the CNN architecture illustrated in Fig. 2(b), where each convolutional layer is followed by a rectified linear units activation function for feature extraction. Fully-connected (FC) layers are used to classify the signals by using the softmax activation function for the output layer [13]. The training algorithms is based on the Adam algorithm that uses the cross entropy as the loss function. The CNN model is trained offline using TensorFlow on a GPU cluster (NVIDIA Tesla P100-PCIE-16GB). Even though the training of the CNN does not account for all possible channel conditions, the generalization property of deep learning enables the trained CNN to infer channel conditions not included in the training dataset [14]. It is also noteworthy that several methods have been proposed to scale up the training process of deep neural networks across GPU clusters, which helps to further reduce the runtime of the offline training. Once the CNN model is appropriately trained, it can directly infer incident signals in near real-time. In other words, the proposed ISL-based framework moves the complexity from online computation to offline training. 3) CNN Online Inference: The CNN is, in particular, trained in order to return the set of active interfering users based on different input signals at each RIS. Specifically, the received RF signals first undergo A/D conversion and frequency down-conversion. Then the baseband I/Q sequences are fed into the trained CNN model to perform online inference at the RIS controller.

Algorithm 1 : 4 :

 14 Distributed RIS Binary Control Input: I l , ω l , and C k ; Output: B; 1: Initialize k = 0, all the RISs are ON; 2: while k < K do 3:k ← k + 1;Calculate Θ * k and Φ * k by solving problem P 2 ;5:

Fig. 3 :

 3 Fig. 3: Achievable SINR vs. λ for K = 1. The distance between the interfering user (U2) and the RIS is 10 m in (a), and 5 m in (b), respectively.

Fig. 4 :

 4 Fig. 4: SINR vs. K for pm = 10 dBm. λ = 0 is shown in (a), λ = 150 o is shown in (b), and λ randomly selected in [30 o , 120 o ] is shown in (c).

  ISL Example: To better understand the proposed ISL algorithm, we illustrate an example with only two users (denoted as U 1 and U 2 ), and each user has a binary state, i.e., 'active'/'ON' and 'inactive'/'OFF'. In this case, there exist four combinations of signals from the perspective of each RIS: (1) 'Idle' (indicating that both U 1 and U 2 are inactive), (2) 'Only U 1 ' (indicating that only U 1 is active), (3) 'Only U 2 ' (indicating that only U 2 is active), and (4) 'U 1 +U 2 ' (indicating that both U 1 and U 2 are active). Based on the superimposed incident signal(s), the RIS needs to identify the composition of the signal(s), i.e., to identify the correct class out of the four possible classes of signals. Therefore, this signal identification boils down to a four-class classification problem, as illustrated in TableI.

TABLE I :

 I An illustrative ISL example with two users

	Inferred Class	Description
	Class-1: Idle	The collected RF traces include only the noise

Class-2: Only U1 The collected RF traces include only U1 Class-3: Only U2 The collected RF traces include only U2 Class-4: U1 +U2

The collected RF traces include both U1 and U2

TABLE II :

 II Inference accuracy of the trained CNN model. We trained the CNN with the 80% of collected RF data set which contains about 800 million I and Q samples (training set), validated it by using 10% of the dataset (validation set), and tested it by using 10% of the dataset (testing set) each corresponding to about 100 million of the I and Q samples. The trained CNN model consists of two convolutional (Conv) layers with ReLU activation functions, followed by two dense fully connected (FC) layers. In particular, the trained CNN model contain 256 filters (1×3) in the first Conv layer, 128 filters (1×3) in the second Conv layer, 256 neurons in the first FC layer, and 9 neurons in the second FC layer (output).The classification accuracy of the trained CNN is analyzed in TableII, by considering a two-user scenario. The window size (i.e., the number of time steps of the collected RF data) is 32, 128, and 512, respectively. We observe from Table II that the online inference accuracy is, in general, greater than 95% in the considered scenario. Compared to other classes, the 'Idle' class has the main characteristic that no user transmits and only background noise exists. Due to the distinguishable pattern compared to the other three classes, the CNN model predicts the 'Idle' class perfectly.

	Scenarios w = 32	w = 128 w = 512
	Idle	100.00% 100.00% 100.00%
	Only U1	98.35%	98.04%	96.21%
	Only U2	96.09%	96.12%	95.64%
	U1 +U2	99.66%	99.76%	99.93%
	A. CNN Testing Results

TABLE III :

 III Computation time (ms) of the proposed ISL-based DRBC algorithm and the traditional sBB method The simulation model consists of K RISs, one desired user (U 1 ), and one interfering user (U 2 ). Each RIS consists of 256 elements and all the K RISs are equally spaced by 5 m in vertical direction. The distances from BS and U 1 to the RIS center are 80 m and 60 m, respectively.

	t
		Traditional sBB method Proposed DRBC algorithm
	K
	2	14.1	2.60 × 10 -3
	3	14.2	2.55 × 10 -3
	4	14.5	2.40 × 10 -3
	5	15.2	5.15 × 10 -3
	C. Performance Evaluation
	1) Simulation Setting:

Many papers in the literature have tackled the issue of estimating and reporting the CSI, e.g.,[START_REF] Di Renzo | Smart radio environments empowered by reconfigurable intelligent surfaces: how it works, state of research, and the road ahead[END_REF],[START_REF] Zappone | Overhead-aware design of reconfigurable intelligent surfaces in smart radio environments[END_REF]. Therefore, this problem is not addressed in this paper and it is left to a future research work.

We assume that the active interfering users remain unchanged during the transmission time of the desired user.

ISL-aided RIS approach. Offline training is only a candidate way to train a CNN, which may need to be retrained when RF data distribution changes significantly. This issue may be avoided by using online training methods, such as federated learning, which is a promising method for application in dynamical wireless environments.