Dr Nathalie Grandjean
email: nathalie.grandjean@unamur.be

Dr Alain Loute
email: alain.loute@univ-catholille.fr

Peter Lang

The Materiality of Virtuality: Towards an Intensification of Invisibilities

The Materiality of Virtuality: Towards an Intensification of Invisibilities

Nathalie Grandjean, Alain Loute "Forget about fingerprints or iris recognition; the way you walk or move your hands, even your pulse, can be analysed for unique characteristics. EU-funded researchers are looking at ways this new technology could protect your security and make identity checking less obtrusive and more accurate" 1 .

Western societies face two paradoxical anxieties regarding political and social regulation: security and privacy. One of the political choices of the European Union trying to solve this double bind resides in the promotion of technological solutions, such as 'soft biometrics'. Funding instruments such as 6 th and 7 th Framework Programmes promoted research in soft biometrics, following the objectives of robust identification while respecting privacy and bodily integrity. This new kind of biometrics shows great promise. As Dr Tzovaras says of the results of the ACTIBIO 2 project: (…) this is a revolutionary improvement for dynamic recognition. And when we combine dynamic and static biometric systems, the equal error rate drops to zero; identification is correct every time. We can see many excellent applications for authenticating individuals and monitoring their behaviours without having to intrude into or interrupt what they are doing" 3 . This non-intrusiveness is promoted as a technical quality which could render biometrical technologies harmless -indeed in some cases democratic -and therefore that could solve the famous "trade-off between security and privacy." Non-intrusive technologies are not only dedicated to biometric uses, but to any monitoring devices incorporating this quality of nonintrusiveness into their technological nature, for example when securing delimited critical infrastructures (CI), which is the objective of the P5 4 and IPATCH 5 . A new form of 1 http://cordis.europa.eu/result/rcn/88445_en.html 2 http://cordis.europa.eu/project/rcn/85410_en.html 3 http://cordis.europa.eu/result/rcn/88445_en.html 4 " "P5 project is the acronym of" "Privacy Preserving Perimeter Protection Project"" and is a European and FP7 funded project for the protection of critical infrastructures to benefit the sustainability of society and future well-being of European Citizens. Our vision is an intelligent perimeter proactive surveillance system that works robustly under a wide range of weather and lighting conditions. The system will monitor the region outside the security area of critical buildings and infrastructures, and give an early warning if terrestrial or airborne threats are approaching. The envisioned system will support, rather than replace, a human operator. A low false alarm rate from animals or other innocuous events, combined with high threat detection sensitivity and privacy standards, are central ambitions of the project."" http://www.foi.se/en/Customer--Partners/Projects/P5/P51/ 5 IPATCH (Intelligent Piracy Avoidance using Threat detection and Countermeasure Heuristics) is also a European and FP7 funded project, whose objectives are the detection of piracy threats in good time in high-risk areas. "IPATCH will provide technology to protect ships and their crews from the modern-day scourge of piracy that is proliferating throughout the world, bringing severe human, financial and political costs, as well as affecting international seaborne trade. The IPATCH system will use advanced sensors and data fusion to provide the Master of the ship with the information surveillance could emerge, lighter and less agressive. The walls become invisible. As underlined by Frank Neisse and Alexandra Novosseloff: "(…) first made of continuous obstacles of concrete or steel at regular intervals, of observation towers, walls progressively incorporate multiple electronic detection equipment. In the United States, drones equipped with infrared cameras now fly regularly along parts of the border. 30-meter-high observation towers have been installed in desert areas: there are soaring metal pylons on which are fixed cameras and radars able of covering 45 kilometers of border. This electronic ensemble constitutes thus a kind of "invisible wall" which will detect nearly 95% of migrants, according to the Border Patrol. This virtual wall, costing an exorbitant amount, has the great advantage of being more "acceptable" in the eyes of the people concerned, because it is less visible and, apparently, less violent." (Neisse & Novosseloff, 2010 :736) The wish of the EU, through the funding of such research, resides in the idea that some political and social issues will be resolved through the possibility of creating virtuous technologies, both respectful of fundamental rights and privacy and yet effective for their monitoring objectives. Thus, the search produced PET (Privacy Enhancing Technologies) and the concept of 'Privacy by Design 6 ,' inaugurated by Ann Cavoukian, has emerged in the research and development sector. By integrating constraints of privacy at the heart of the construction of technological artefacts, one entrusts to technologies the power to solve the social, political and legal issues caused previously by the uses of surveillance. One of the recogniseable attributes of all these surveillance technologies 7 is their nonintrusiveness, which we prefer to designate as virtuality. They are promoted as less invasive to the extent that their control is not "material", that is to say that surveillance is not always palpable in material terms, nor physically felt. Surveillance, in this process of 'invisibilisation', should alleviate the unpleasant weight of social control, while being extremely effective. Virtuality could then be seen as a softening of control: a kind of nonviolent surveillance, but efficient and certain. However, this is not the case. Indeed, this phenomenon of the "virtualization" of surveillance is more an extension and intensification of surveillance power. More materiality must be considered for this virtualization, since it is intended to serve as a form of political management of specific spaces (such as borders or urban areas) and human bodies (which we may designate with the foucaldian term of 'biopolitics').

needed to decide how best to mitigate the threat, be that calling for assistance or bringing the crew into the secure citadel." http://www.ipatchproject.eu/ 6 "In the early 1990s, the concept of Privacy by Design (PbD) was developed to address the systemic effects of ICT and networked data systems. The central thesis of PbD is that privacy cannot be protected solely through compliance with regulatory instruments; rather, technologies should be designed with privacy in mind from the outset. Instead of bolting on privacy enhancing features, privacy enhancing tools e.g. minimisation of unnecessary data collection, should be integrated into systems design" (European Group on Ethics in Science and New Technologies, Jim Dratwa (ed.) ," "Ethics of Security and Surveillance Technologies", Opinion n° 28, (2014): 32. For a presentation of the 7 Fundamental Principles of the privacy by design approach; Cavoukian, Ann, Privacy by design, The 7 Foundational Principles, https://www.ipc.on.ca/images/Resources/7foundationalprinciples.pdf 7 David Lyon defines surveillance as "any collection and processing of personal data, whether identifiable or not, for the purposes of influencing or managing those whose data have been garnered" David Lyon, Surveillance Society: Monitoring Everyday Life (Oxford: Open, 2001), 2.

Meanings of virtualisation in monitored spaces

In his book on the political history of barbed wire, Olivier [START_REF] Razac | Histoire politique du barbelé[END_REF] emphasizes five basic features of virtualisation of spatial boundaries. Although his analysis applies mainly to barbed wire (which represents a milestone in this history of virtualisation), it suggests that virtualization of technologies is as much in evidence in their use of lightweight material as in their frightening effectiveness. Between the old barbed wire and virtual walls made of new surveillance technologies, only the material has changed. What exactly are the meanings of virtualisation, according to Razac?

• Virtualization means first material erasure. We could hit a brick wall, a virtual wall is intangible. • In addition, relief from material allows a gain in mobility. While a fortress wall is difficult to build, barbed wire walls are installed with great ease and without significant costs. • Such a mobility allows high flexibility. Rather than a delimitation of fixed and definitive spaces, a virtual wall can follow movements and flows. Unlike the stone, "the metal wire is a tensile material that bends under the action of an external force. This deformation action has the effect of absorbing the energy impact and increasing the resistance of the wire. (...) Flexibility and mobility combine in order to allow the absorption of aggression, the agressor is entrapped and gradually weakened." (Razac 2009: 150). • Razac also highlights the discretion that a virtual boundary enables. Far from being a sign of weakness, the power of this type of delimitation lies in its discretion. It avoids frontal resistance and opposition. • Finally, virtual boundaries are characterized by their reactivity. Barbed wire walls can slow down an attack and gain time to react. In addition, because any space in front of the wire can be monitored, a panoptic effect reinforces the feeling of being monitored and potentially deters crossing the virtual wall.

Olivier Razac defines the concept of virtualisation of spatial boundaries from the study of a relatively low-tech device: barbed wire. It is therefore not necessary to mobilize digitised surveillance technologies as determining causes to understand this phenomenon of "virtualisation". On the contrary, the sense of the role of these technologies should rather be interpreted with reference to this virtualisation process.

Virtuality as political management of space

How to understand what is crucially at stake in this phenomenon of virtualisation? One must first avoid assimilating virtual to "less real." As Razac points out, "virtualisation does not mean less control of space, on the contrary, a relief from physical presence is made in an act of separation for the direct benefit of the authority's capacity to act " (Razac 2009: 159). One should understand virtualisation as a new form of "political management of space", rather than a de-politicisation of space. It is less control than opening and closing spaces in order to manage the flow of open spaces, "managing permeability." "Controlling population without curbing it", because the goal is not to "block, but to let circulate " (Razac 2009: 125). The main issue is to manage what Michel Lussault call "trans-spatiality" that is to say "the specific action of passing" (Lussault 2012: 71). This management of crossing and access is based on different protocols. Michel Lussault especially evokes the act of spinning or queuing, namely an analysis of the optimization of the queuing process. He also mentions filtering, which "grants access for the purposes of verification -usually the right to penetrate the space and/or content of what an individual or a container carries" (Lussault 2012: 71). Finally, the tracing process consists in "following an item entered into a spatial organization and at least identify its exit, better, its steps and its exit, better yet, all its movements and positions in a real-time process" (Lussault 2012: 72).

Even more than the passing or the crossing, the movement itself becomes the object of control and surveillance. So-called "smart" technologies can automatically detect behaviour considered as abnormal (or potentially abnormal): "it is possible to analyse behaviour considered as suspicious in open or public places: frequent stops, counterflow traffic, excessive or insufficient speed, group size, abandoned object, etc. with all the possible crosses between different chosen criteria" (Razac 2009: 220).

John Amos Lecat-Deschamps also considers videosurveillance as virtual walls (Lecat-Deschamps 2012: 124-9). The cameras are indeed sparsely visible in public space. On the opposite of the physical wall, CCTV do not try to "block", they "do not create any immediate physical consequence". They track and analyze flow. Similarly, they have a panoptical deterrent effect. Individuals know they are seen, interiorizing somehow expected norms of behaviour in specific spaces.

Virtuality as virtue

Let's go further in exploring this virtuality. In the paper "Border work: surveillant assemblages, virtual fences, and tactical countermedia", Tamar Vukov and Mimi Sheller point out the proximity between the words "virtuality" and "virtue": "Virtuality also carries connotations of "virtue" -the virtue of borders, the virtuous traveler, the good passenger versus the unvirtuous, the cheater, the stowaway and the smuggler" (Vukov & Sheller 2013: 225-241). This proximity raises different questions: is it possible to propound a fixed, neutral and objective definition of a normal behaviour? Or is it possible to consider "normality" as a temporal and socially-embedded phenomenon? By classifying the behaviour of moving object as innocuous or as potential threats, virtual fences could define certain kinds of behaviour as virtuous.

For Ajana, "Governments and companies often promote the illusion that algorithmic processes and data-driven systems are purged from human bias and interference leading to more neutral, objective and automated decisions that are devoid of discrimination on the basis of race, ethnicity etc.". However, according to Ajana, such a belief needs to be interrogated. She quotes Dwork and Mulligan: "Both the datasets and the algorithms reflect choices, among others, about data, connections, inferences, interpretation, and thresholds for inclusion that advance a specific purpose [...] classification systems are neither neutral nor objective, but are biased toward their purposes. They reflect the explicit and implicit values of their designers" [START_REF] Dwork | Biométrie: les nouvelles formes de l'identité[END_REF].

The virtue of technologies pretends to stay in a so-called neutrality of values, because of the objectivity of the technological devices. But no technology has never been neutral or deprived of values. In reality, biometrical technologies valorize some norms and behaviours by accepting them or by refusing others, such as smart CCTV programmed to detect abnormal behaviours. This process of sorting contributes to normalized norms and behaviours and to the perception of acceptable body types, movements and behaviours.

Virtuality as virtuosity

Tamar Vukov and Mimi Sheller also point out the semantic proximity between "virtuality" and "virtuosity": "So on entering the virtual border space of the airport one becomes not only a virtual passenger (shadowed by the ''data double'', a kind of informational penumbra), but also a virtuous passenger (performing virtue and virtuosity)" (Vukov & Sheller 2013: 225-241). This second proximity raises a second issue. "Virtual fences" not only monitor a perimeter, they can also "perform" it. Virtual fences do not only detect moving objects, they could also affect these objects. People walking around a monitored perimeter could adjust, with virtuosity, their behaviour to the mechanism of surveillance. Human beings are very specific "moving objects". They are "reflexive moving objects". Virtuosity becomes a necessary quality in order to pass borders and cross areas. Surveillance technologies contribute to the social sorting process, when distinguishing individuals according to their virtuosity to pass borders and to move through spaces. They reactivate domination criteria such as class, race and gender. Virtuosity is the ability to transcend or even to cheat with those criteria. Etienne Balibar points out the "multiple meanings" of borders. Meanings of borders change according to the direction of crossing or according to who crosses, whether a businessman or an unemployed male youth of immigrant origin. "In this latter case, a border becomes almost two distinct entities, which have nothing in common but a name. Today's borders (though in reality this has long been the case) are, to some extent, designed to perform precisely this task: not merely to give individuals from different social classes different experiences of the law, the civil administration, the police and elementary rights, such as the freedom of circulation and freedom of enterprise, but actively to differentiate between individuals in terms of social class" (Balibar 2002 : 81-82).

Virtuality as potentiality

Virtual fences do not only extend the object of surveillance from a spatial point of view, but also from a temporal point of view. The future is also monitored. Early warning system try to detected "potential" threatening behaviours. Monitoring the future raises both epistemological and ethical issues. In R&D projects, the future is envisaged from "projected scenarios" selected by the engineers. It is essential not to confuse these scenarios with reality itself. By definition, the future is not exhaustively foreseeable. We always select and prioritize potentiality, we choose some scenarios over others. Our relation to the future is framed by an "economy of attention" (Balibar 2002 : 81-82).

For Didier Bigo, the risk today is that we deny this radical unpredictability of the future and pretend that we have the capacity "to read the future as if it were a "future perfect8 ". As he says, "security technology professionals now want to reduce all these possible futures to just one; which is often the future of the worst case scenario. And it is this selected future that they read as a future perfect, as a future already fixed, a future they already know (…) [This] is the by-product of the existence of transnational guilds of professionals of (in)security who share the same view of the world to come" [START_REF] Bigo | Cavoukian, Ann, Privacy by design, The 7 Foundational Principles[END_REF].

Reading the future is not only a scientific and a technological task. It is also a political challenge. How to "democratize" this economy of attention? Should we organize a collective deliberation on the "projected scenarios" selected in technological projects?

Virtuality and the political process of bordering

A last question concerns the political process of bordering. Virtual fences could deeply modify the way we understand political borders. To the question "what is a border?" Etienne Balibar responds that it is not possible to give a simple answer: "Basically because we cannot attribute to the border an essence which would be valid in all places and at all times, for all physical scales and time periods, and which would be perceived in the same way in all individual and collective experience" (Balibar 2002 : 81-82). This theoretical complexity contrasts with the practical simplicity with which borders have been build. Balibar writes: "In other words, their practical definition requires a 'reduction of complexity', the application of a simplifying force". Balibar adds: "the consequence has been that the borders within which the conditions for a relative democracy have in some cases been won, have themselves always been absolutely anti-democratic institutions, beyond the reach of any political purchase or practice". That's why it is important to be concerned with "what democratic control is exerted on the controllers of borders -that is to say, on states and supranational institutions themselves". Therefore, virtualization of fences does not lead to a democratization of borders. On the contrary, we should admit the hypothesis that virtualization of surveillance implies a more difficult and complex democratisation of borders. One of the risks is that virtualization increases a high "social acceptability of borders", making them less visible and more discreet, without any democratic debate about their management.

Extension and intensification of surveillance

In conclusion, it seems essential to consider that virtualization does not mean a reduction of supervisory power, but is the exercise of a new materiality of this power, gaining a kind of extension. First, because its objective is not only to cross borders or boundaries, but also to move through space. Moreover, the extension of this power is not solely spatial, it is also temporal, because the purpose of these 'smart' devices is to detect illicit or abnormal behaviours -and even the supposed intention of repressible behaviour. As Btihaj Ajana writes, "the future, as such, is now gradually becoming a computing object made of speculative algorithmic probability" (Ajana 2015: 58-78).

Secondly, virtualization processes do not mean a de-realisation of walls and borders. It would be a mistake to understand the "virtualization of border" as a phenomenon implying the disappearance of the border or the limit. Virtualization does not make a fence less real. By contrast, a characteristic of virtual fences is that "bordering" is not made only by means that are "actual", that is to say, embedded in materiality, but also with "virtual means", in the sense of "potential". By "potential means" should not be understood less real. By "potential means", we understand means which are "actualized" when necessary -an example is a patrol that only intervenes when electronic sensors trigger an alarm [START_REF] Razac | Histoire politique du barbelé[END_REF]. Moreover, virtual fences could be used in combination with a physical fence. Btihaj Ajana argues that virtual fences "augment the function and the intensity of borders" (Ajana 2015: 58-78). Virtual fences can also create a purely virtual limit where it would not have been possible to build a wall for economic, technical or political reasons.

Finally, surveillance is interiorised and intensified. With this new configuration of panoptic power, individuals, knowing they are seen, tend to act in order to comply with the expected normal behaviour. This results in "mental barriers" (Lecat-Deschamps 2012) or "interiorised limits" [START_REF] Sabot | Une société sous contrôle ?[END_REF]. Olivier Razac, referencing Michel Lussault on this phenomenon, writes: "the limits are often mental and immaterial, built into the spatial capital of each operator, and therefore their effects are powerful because they remain necessary even when no physical barriers are erected to organize spatiality" (Lussault 2007:198).

Virtualisation facing biopolitics

We showed that virtuality raises crucial ethical and political issues concerning the political management of space and temporality. What about individuals? How does this virtuality impact them? A strong hypothesis might assume that the pervasiveness of surveillance technologies puts us in a permanent biometric regime, due to the possibility of aggregate data being constantly connected to one or more individuals. Can we imagine the virtualization of technologies actually passing through bodies? Digital surveillance technologies, including biometric technologies, also have the effect of "virtual tagging". They place us in a full biometric regime, to the extent that the collected and aggregated data can be connected to one or more individuals. Our lives are continuously measured, compared, profiled and/or evaluated. This full biometric regime engenders biopolitics, in the sense that identifying, recognizing and monitoring the order of life itself (body or bodily parts) is biopolitical scheduling, much as public health policies target morbidity, birth or epidemics. This is about monitoring masses of bodies while being able to focus on a particular body, deviant, unwanted or dangerous, if the need arises.

Biometrics as a new biopolitics

Let us return to the foundations of biopolitics. In 1977, Michel Foucault defined biopower as a technique of power, acting through the matter of the body, "society's control over individuals is not only carried out through consciousness or ideology, but also through the body and with the body. The body is a bio-political reality; medicine is a bio-political strategy" (Foucault 2010 : 210). Foucault thinks this political investment of bodies occurs on a double level, firstly on the individual level of singular existence and, secondly, in terms of the population, through political economy and the governance of social behaviour. He distinguishes on the one hand anatomo-politics as the study of strategies and practices by which power models individuals, from school to factory; monitoring and straightening individuals' bodies. Then, on the other, he distinguishes biopolitics as the political management of life, targeting not particular individuals, but entire populations; this involves managing health, hygiene, diet, sexuality and natality as political issues. In 1979, he wrote a summary of his lecture 'Birth of Biopolitics' and defined biopolitics as "the way we have tried, since the 18 th century, to rationalize the problems posed to governmental practice by phenomena engendered through an ensemble of livings constituted as a population: health, hygiene, birth, life, race..." (Foucault 2010 : 818).

Let us focus on the genealogy of biometrics. Giorgio Agamben provides an early intuition. He compares biometrical practices to the political paradigm of the concentration camp, because of the tagging of bodies as a means of identification: "Thus, by applying to the citizen, or rather the human being as such, the techniques and devices invented for the dangerous classes, States -which should be in the heart of politics -have transformed the citizen into the 'usual suspect', to the extent that humanity itself becomes a dangerous class. A few years ago, I wrote that the political paradigm of Western societies was not the City anymore, but the concentration camp, and that we had passed from Athens to Auschwitz. It was obviously a philosophical thesis, and not a historical narrative, because one should not confuse phenomena that should rather be distinguished. However, I would suggest that tattooing probably appeared in Auschwitz as the most natural and most economical way to manage the inscription and registration of the deported in concentration camps" [START_REF] Agamben | Non au tatouage biométrique[END_REF]).

Biometrics reactivates the figure of the concentration camp by rigorously identifying the living body with a person's identity, and making a passport from a physical detail. At the same time, biometrics performs this reactivation with an entirely new spirit: by rendering neutral and objective this naturalization of personal identity, and by simply designating it as convenient, useful, efficient and fast, biometrics can delete any infamous intention or degrading tagging. What was an infamous marking becomes a discrete recognition mode, which is difficult to oppose with notions of consent or consciousness. All the strength of biometrics lies in this "discretion", this virtual marking, almost invisible, almost impermanent compared to the logic of concentration camps and tattoos.

From Auschwitz to 9/11

However, we remain within a time of great infamy. Since 9/11, images of borders, migrants and terrorists have replaced those of concentration camps and Jews. Biopolitical practice is still relevant, though far from attaining saturation, in the sense that it overflows across the landscape of the society of control. Boundaries are the territory of post-9/11 biometrics: physical boundaries (sea walls, deserts, etc.) or intangible boundaries ("critical infrastructure", transit zones in airports). Garapon and Foessel (2006) underlined that the generalization of biometrics finds its initial justification in the anonymity that characterises terrorist actions. It seems an appropriate and effective response to the fear of erasing traditionally accepted criteria for danger, such as nationality or religious affiliation. Biometrical parameters can identify any individual without knowing their national or community affiliation and according to criteria that owe nothing to his/her biography. And because of this kind of identification, biometrics allows the tracking of anything, such as monitoring the transport of goods on the principle of "traceability". The challenge is to identify individuals, to store their routes and to deduce a degree of danger from the nature of their observed movements. Garapon and Foessel (2006) believed that ethnic, religious or racial considerations disappear with biometrics. We do not share this opinion: firstly, biometrics is now able to trace and digitize these criteria, and secondly, biometrics uses these criteria by superimposing them. However, any biographical or narrative consideration of race is effectively excluded: it is seen as pollution and noise.

As we have already mentioned, the symbol of the full biometric regime is the migrant. Migrants are exposed to the same biometrical biopolitics: bone tests, hairiness, teething tests, and genital tests are imposed in order to determine the real age of a person, declaring whether he/she is a minor. DNA tests are also conducted to establish the real kinship between two people seeking family reunification, and biometrical tests in order to verify the real identity of an individual... Biometrics is enrolled in a context where generalized surveillance becomes increasingly deterritorialized and intrusive, such as terrorism. Terrorism and biometric practices seem symetrical and become systemic. Terrorism, according to Garapon and Foessel, uses several strategies: firstly, that of individual indiscrimination and of confusion between private and public. Privileged spaces for the terrorist attack are what Marc Augé (1992) calls "nonplaces", places full of crowds but empty of subjects, such as airports, subways, train stations, shopping malls. Thus another terrorist strategy takes place: by targeting non-places, terrorism uses a "strategy of ubiquity": any place, provided it is full, is likely to become a battlefield. "Non-places" are uninhabited, they are crossed by crowd flows, which are essentially anonymous because not recognized as 'subjects' of those places. The figure of the terrorist is built symetrically into this constraint: he/she also wants to be anonymous, invisible -in full enjoyment of the presumption of innocence typical of Western democracies. Thus he/she meets the norm of verisimilitude, the apparent normal stream of everyday life, until the actual trigger point of the terrorist act. Based on this ordinary and quotidian nature, the horror and unpredictability of the act and therefore its effects are increased, occuring in the vast forum of scandalous publicity, relayed by social media and breaking news TV shows. Garapon and Foessel use the term "delayed visibility" to describe this strategy. It is to counteract this strategy that biometrical systems think, anticipate, predict and understand terrorist intentions.

Biometrics is both a biopolitical practice and a set of techno-scientific products from research projects. The full biometric regime is a political choice, relying on the hope of a tipping point between the dissimulation and the visibility of a terrorist. This hope relies on identification criteria, stable because computerized, and encoded in a universal language, and permanent because registered in the permanence of the body.

It is thus the very materiality of the body, taken in the specific readability of the code, that enables a guarantee of identities and intentions. The intention here is not, in the sense that 'Nature' would comprehend them, a naturalization of the body, to assign and individuate. Indeed, bodies subjected to the full biometric regime are a construction, because they need to be read through a variety of biometric technologies. Nonetheless, a form of attachment to the 'naturality' of the body is demonstrated by the primordial nature of the flesh, without being embedded in any process of individuation. Citizens or subjects are not necessary here -what counts is only the materiality of their bodies.

(Human) bodies do not lie

There is an assertion of technoscientific and political truth: the body does not lie, although technology may indeed sometimes misread or hear badly. Faced with a radical and permanent uncertainty, the only possible and visible landmark is the truth of the body. But the truth of the body is enunciated by a neutral and universal technoscience, completely unaware of its privileged and dominant position9 . These modes of veridiction appear normal and natural. This a posteriori naturalization of the physical evidence of the body also plays a role in the attachment to the distinctly 'biological' body, and therefore to the denial and rejection of any narrative or biographical possibility.

What is being played out, therefore, is a possible desubjection that occurs in the very design of biometrical artifacts. Facial Recognition of Emotions is a biometric technology capable of processing the expression of emotions in real-time. In this case, it is neither the emotions nor the feelings themselves that are identified, but only their expression, digitized by algorithms that are in turn derived from deterministic psychological models 10 . Another example are bodycams. These are small cameras attached to police uniforms, that police officers can snap on in the event of contentious situations. Here also, one can observe the conjunction of the body and the artifact producing a regime of truth. Neither the story of the marchers nor the story of the officer has value when compared to the "narrative" of videofootage hooked to the body. In this paper, we have demonstrated that digital virtuality, described in terms of nonintrusiveness or invisibility, cannot elude some very concrete material effects: there is an intensification and extension of the power of surveillance technologies, through the spatiotemporal organization of both borders and urban areas, and through the bodies of individuals. Biopolitics, as described by Foucault, takes a new face and encompasses new challenges. Surveillance technologies have shown their ability to intensify the power of sovereignty and disciplinary techniques. This is especially what Deleuze sensed when writing the "Postscript 10 Paul Ekman is an american professor of psychology. Computerized models for the facial recognition of emotions, based on Ekman's work on the facial expression of emotions (with Friesen, Haggard and Isaacs), allow the improvement of surveillance technologies. See more about Paul Ekman; http://www.paulekman.com/paul-ekman/ 11 The Nigerian child, Francesca, was born May 4 th , 2015, on a boat full of migrants. She touched Italy with her extraordinary birth by representing two biblical figures, Moses saved from the waters and Jesus, born in a stable, "poor among the poor." No doubt that she will receive Italian citizenship as a birth gift ... http://www.theguardian.com/world/2015/may/04/rescued-mediterranean-migrant-givesbirth-baby-girl-italian-navy-ship 12 Becoming (devenir) is a concept coined by Deleuze and Guattari in "A Thousand Plateaus" (1980). on the Societies of Control" in 1990, in which he described a world of surveillance and control written with a digital language, which would be the new regime of power, replacing the old disciplinary societies. "In the societies of control (…) what is important is no longer either a signature or a number, but a code: the code is a password, while on the other hand, disciplinary societies are regulated by watchwords (as much from the point of view of integration as from that of resistance). The numerical language of control is made of codes that mark access to information, or reject it. We no longer find ourselves dealing with the mass/individual pair. Individuals have become 'dividuals', and masses, samples, data, markets, or 'banks'" (Deleuze 1992: 5). Underlining the various regimes of power (sovereignty, disciplinary and control), Deleuze emphasizes the organic link existing between surveillance technologies and the very exercise of control. It is not an isomorphism but a co-generation between technologies, code as language, individuals and society. "Types of machines are easily matched with each type of society -not that machines are determining, but because they express those social forms capable of generating them and using them. The old societies of sovereignty made use of simple machines -levers, pulleys, clocks; but the recent disciplinary societies equipped themselves with machines involving energy, with the passive danger of entropy and the active danger of sabotage; the societies of control operate with machines of a third type, computers, whose passive danger is crashing and whose active one is piracy or the introduction of viruses. This technological evolution represents, even more profoundly, a mutation of capitalism (…)" (Deleuze 1992: 6). How can one withstand virtualization and its effects? A technical answer is proposed through conceptual tools such as Privacy by Design, which is "an approach to protecting privacy by embedding it into the design specifications of technologies, business practices, and physical infrastructures. That means building in privacy up front -right into the design specifications and architecture of new systems and processes 13 ". This proposal incorporates the promises of the field of genetics and gene therapy, which would have us believe that once privacy is enshrined in DNA technology, it will no longer produce counter-privacy effects. In other words, once "vaccinated", technologies revert to a natural state of neutrality. This technological solution is coupled with ethical and legal responses, as illustrated for example by the recommendations of the The European Group on Ethics in Science and New Technologies (EGE) in a recent opinion (Dratwa 2014: 32). This group advocates notably for the application of the principle of accountability, as it argues that "Privacy Impact Assessment procedures must form part of regulatory practice in Member States when new or modified information systems which process personal data are being introduced to the market". And as the UK Information Commissioner's Office 14 says: "Privacy Impact Assessments (PIAs) are an integral part of taking a privacy by design approach. (…) Privacy Impact Assessments are a tool that you can use to identify and reduce the privacy risks of your projects. A PIA can reduce the risks of harm to individuals through the misuse of their personal information. It can also help you to design more efficient and effective processes for handling personal data 15 ." These legal-technical responses certainly possess the virtue of paying attention to ethical and legal issues. The different actors engaged in the birth of these technologies try to moralize these technologies inside their mode of production. However, we wonder if these initiatives allow us to assess and respond to the material effects induced by these new forms of the 13 https://www.ipc.on.ca/english/privacy/introduction-to-pbd/ 14 The UK's independent authority set up to uphold information rights in the public interest promoting openness by public bodies and data privacy for individuals. See https://ico.org.uk/ 15 https://ico.org.uk/for-organisations/guide-to-data-protection/privacy-by-design/ virtualization of control and surveillance? How to measure and evaluate the impact of these forms of political management of space, temporality and bodies? How to respond to the risk of de-subjectivation of the body induced by the management of "naturalized" bodies constructed by biometrical technologies? What are the consequences of the political management of virtual fences regarding the qualification or delineation of common and public spaces? These questions remain open.

  Thus a strange regime of legitimacy is being established: the body is legitimate only if it is depoliticised with regard to the state. Deprived of subjectivity and read as code, dignity only exists insofar as the observed object agrees to be reduced to a 'suffering body' or a 'humanitarian body'. This body then acquires rights, like little Francesca 11 , in May 2015. The humanitarian body, starving in Africa, is granted the opportunity to obtain rights; but political or economic migrants arriving on Europe's borders are being escorted back, because they are undesirable once they have left their 'natural' habitat, Africa. How to describe this bodily attachment embedded in the biometric system? It is biopolitical, inasmuch as it is a commitment to bodily materialities. However this body is dis-integrated, performing a non-integrity process, notably because of this attachment to bodily materialities through which biometric devices scan. The lived or experienced body is not convoked, because it is unable to provide a reliable basis for recognition, nor is the physical body, subject as it is to the vagaries of time and the possibility of concealment. Thus the biometric body is a paradox, insofar as it is both objectified (reduced to computer parameters) and natural (unalterable). Speaking of body attachment is also taking the expression literally: what is the body tied, bound, connected to? These bodies are integrally attached to biometrical technologies and shaped in a systemic process of individuation, or becoming 12 , through these technologies. Technologies shape bodies, despite us and with us; bodies and techonologies are engaged in a hermeneutical relationship that is yet to be written. This hybridity becomes primordial with regard to modes of existence of the body and challenges any ontological or naturalized primacy. No natural body pre-exists in a temporality that is thickened by digital intensification. The biometrical hybrid body is instantiated in a temporality that is understood as a 'future perfect' (cf. supra), with a non-narrative, because encoded, type of performativity.

In french: "un futur antérieur", that is to say, literally, a previous future.

Similarly, american feminists denounced the "male gaze" as a dominant and privileged position. Donna Haraway, among others feminists, compares the male gaze with the status of science when described as neutral, objective or universal. A kind of predation is exerted by the scientist who observes and produces scientific facts from nature.

He has been post-doctoral researcher (chargé de recherches) supported by the F.R.S.-FNRS (Fonds National de la Recherche Scientifique -National fund for scientific research) at the Center for Philosophy of Law (Université catholique de Louvain). He is now "Maître de Conférences en éthique" au Centre d'éthique médicale de l'Université Catholique de Lille. His research interests include ethics of care, hermeneutics and ethics of technological innovation.


Thiago S Copetti¹
email: thiago.copetti@@ufrgs.br

Guilherme C Medeiros²

Letícia M B Poehls²

Tiago R Balen¹
email: tiago.balen@@ufrgs.br

Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs

Keywords: FinFET, SRAM, Resistive Defects, SPICE, PTM

The development of FinFET technology has made possible the continuous scaling-down of CMOS technological nodes. In parallel, the increasing need to store more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The manufacturing process variation has introduced several types of defects that directly affect the SRAM's reliability, causing different faults. Thus, it remains unknown if the fault models used in CMOS memory circuits are sufficiently accurate to represent the faulty behavior of FinFET-based memories. In this context, a study of manufacturing's functional implications regarding resistive defects in FinFETbased SRAMs is presented. In more detail, a complete analysis of static and dynamic fault behavior for FinFET-based SRAMs is described. The proposed analysis has been performed through SPICE simulations, adopting a compact Predictive Technology Model (PTM) of FinFET transistors, considering different technological nodes. Faults have been categorized as single or coupling, static or dynamic.

Introduction

During the last decades, important advances in nano-scale technology have allowed to miniaturize and integrate hundred million transistors in a small silicon area. Since the development of the first commercial Integrated Circuit (IC), miniaturization and integration have been carried out following Moore's Law. Every two years, new circuits designed with smaller technological nodes were announced by the industry. However, significant changes to the paradigms of digital and analog circuit design were required throughout this technological progression of the Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) technology.

In technological nodes below 20nm, the gate terminal begins to lose control over the potential distribution and current flow of the transistor's channel region. This causes a phenomenon denominated Short-Channel Effect (SCE), which occurs due to the proximity between source and drain [START_REF] Colinge | FinFETs and Other Multi-Gate Transistors[END_REF]. In the face of this adversity, new types of transistors have been designed to address the challenges caused by the scaling of CMOS transistors. Two technologies are widely adopted: Silicon-On-Insulator (SOI) MOSFET and FinFET. In fact, FinFET technology is already replacing CMOS transistors in state-ofthe-art ICs -major electronics companies such as Intel [START_REF]Intel: Intel® 22 nm Technology[END_REF] and Samsung [START_REF]Samsung: Strong 14nm FinFET Logic Process and Design Infrastructure for Advanced Mobile SOC Applications[END_REF] have already migrated to FinFET technology owing to its reduced short channel effects, electrostatic characteristics [START_REF] Tang | FinFET-a quasi-planar doublegate MOSFET[END_REF][START_REF] Yu | FinFET scaling to 10 nm gate length[END_REF][START_REF] Chang | Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node[END_REF], and its compatibility with standard CMOS manufacturing process [START_REF] Colinge | FinFETs and other multi-gate transistors[END_REF][START_REF] Bhattacharya | FinFETs: From Devices to Architectures[END_REF].

As a result of this changes in technological paradigms caused by the introduction of the FinFET technology, several circuit devices needed to be redesigned, tested, and evaluated. One special kind of circuit that can be cited in this context are Static Random Access Memories (SRAM), the focus of this research. Due to the always-increasing need to store more and more information on chip, SRAMs have become the main contributor to the overall area of Systems-on-Chips (SoCs) [START_REF]International Technology Roadmap for Semiconductors[END_REF]. Thus, the overall performance of the chip can be improved significantly by optimizing these memory circuits.

As explained in [START_REF] Bosio | Advanced test methods for SRAMs[END_REF], SRAMs are designed with high density and produced at the limit of the technological process. Hence, they are very susceptible to manufacturing defects. The resistive defect model, which can be modeled as resistive-open or resistivebridge, is a well-accepted defect model studied in bulk CMOS technology. A resistiveopen defect is defined as a resistor between two circuit nodes that share a connection [START_REF] Dilillo | Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution[END_REF], while a resistive-bridge is defined as a resistor between two circuit nodes that should not be connected [START_REF] Fonseca | Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes[END_REF][START_REF] Li | Testing for resistive opens and stuck opens[END_REF]. Open defects have traditionally been a concern in the CMOS technology test scenario. More recently, this concern shifted towards weak resistive-open and weak resistive-bridge defects as their probability of occurrence may increase in nanometer technologies due to the ever-growing number of interconnections between layers [START_REF] Dilillo | Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution[END_REF].

While the influence of resistive defects in circuit parameters (e.g. voltage, current) is irrefutable, it is easier to evaluate their impact by analyzing what faulty behaviors they lead to. Functional faults are deviations from expected behavior of the memory under a set of operations [START_REF] Van De Goor | Functional memory faults: a formal notation and a taxonomy[END_REF]. Faults can be static (whose occurrence happens with one operation) and dynamic, in which at least two consecutive operations are required to sensitize the fault. These faults generally cause timing dependent faults, meaning that at least a 2-pattern sequence is necessary to sensitize them [START_REF] Borri | Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test[END_REF]. Moreover, the number of dynamic faults is directly correlated to the presence of weak resistive defects [START_REF] Dubey | Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time[END_REF].

With the scaling down of technological nodes, weak resistive defects are likely to be one of the main reliability challenges in IC design [START_REF] Harutyunyan | Impact of process variations on read failures in SRAMs[END_REF]. This can be partially attributed to the difficulty of detecting these defects, and therefore the dynamic faults they cause. Indeed, open/resistive vias are the most common origin of test escapes in deep-submicron technologies [START_REF] Needham | High volume microprocessor test escapes, an analysis of defects our tests are missing[END_REF]. Many of the standard March algorithms fail to detect dynamic faults [START_REF] Dilillo | Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution[END_REF][START_REF] Borri | Analysis of dynamic faults in embedded-SRAMs: Implications for memory test[END_REF][START_REF] Dubey | Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time[END_REF] or present certain limitations by limiting the number of consecutive operations required to sensitize the fault by no more than two [START_REF] Benso | New March Tests for unlinked dynamic memory faults[END_REF][START_REF] Bosio | March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs[END_REF][START_REF] Hamdioui | Testing static and dynamic faults in random access memories[END_REF]. Recently, a new March test designed for FinFET-based memories was proposed in [START_REF] Harutyunyan | Memory Physical Aware Multi-Level Fault Diagnosis Flow[END_REF]. The authors formulated this new test algorithm based on reports from their previous works in which they observed dynamic faults sensitized by up to eight consecutive read operations [START_REF] Harutyunyan | Test and Repair Methodology for FinFET-Based Memories[END_REF][START_REF] Harutyunyan | Fault modeling and test algorithm creation strategy for FinFET-based memories[END_REF].

Traditionally, characterization of fault behavior observed in defective SRAM cells has been performed following a well stablished methodology based on SPICE electrical simulations. Many works focused on evaluating the resistance in which a certain defect starts to sensitize faults. This resistance, known as critical resistance, is the threshold between a fault-free and faulty behavior [START_REF] Segura | Quiescent current analysis and experimentation of defective CMOS circuits[END_REF]. Critical resistances of resistive-open defects were investigated in [START_REF] Dilillo | Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution[END_REF][START_REF] Borri | Analysis of dynamic faults in embedded-SRAMs: Implications for memory test[END_REF][START_REF] Dilillo | Resistive-open defect injection in SRAM core-cell[END_REF][START_REF] Vatajelu | Analyzing resistive-open defects in SRAM core-cell under the effect of process variability[END_REF] adopting technological nodes of 130nm down to 40nm, while critical resistances of resistive-bridge defects were investigated in [START_REF] Fonseca | Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes[END_REF][START_REF] Fonseca | Impact of Resistive-Bridging Defects in SRAM Core-Cell[END_REF] adopting technological nodes of 90nm down to 40nm.

However, all these previous researches were conducted using planar CMOS technology. So far, little research has been conducted considering resistive defects in Fin-FET memories. In [START_REF] Harutyunyan | Fault modeling and test algorithm creation strategy for FinFET-based memories[END_REF], the authors modeled resistive open and bridge defects taking into account the physical structure of 28nm FinFET devices aiming to observe possible unique faults of this technology. An analysis of faults in FinFET SRAM cells affected by resistive defects was presented in [START_REF] Copetti | Analyzing the Behavior of FinFET SRAMs with Resistive Defects[END_REF]. Simulations were carried out using a 20nm technology model. No further works have been proposed focusing on smaller nodes. This is especially worrisome since 14nm FinFET devices are currently in production [START_REF]Intel: Intel's 14 nm Technology: Delivering Ultrafast[END_REF][START_REF]Samsung: Samsung Mass Produces 14-Nanometer Exynos Processor with Full Connectivity Integration[END_REF].

This work presents a study on the behavior of FinFET-based SRAM cells affected by resistive defects. In particular, this study intends to map and determine how manufacturing defects, specifically resistive-open and resistive-bridge defects, impact in the behavior of FinFET SRAM cells. Resistive defects with different magnitudes were injected in memory bitcells aiming to sensitize static and dynamic faults. The analysis was performed through electrical simulation using HSPICE TM software and adopting Predictive Technology Models (PTM) [START_REF]Nanoscale Integration and Modeling (NIMO): Predictive Technology Model (PTM)[END_REF] of multi-gate transistors based on 20nm, 16nm, 14nm, 10nm, and 7nm bulk FinFET. These analyses demonstrated that smaller FinFET technologies will be more prone to weak resistive defects and therefore dynamic faults, proving the need for specific test methodologies for this unique technology.

The rest of the work is organized as follows. Section 2 explains the concepts related to the design of FinFET SRAMs and the set of fault models adopted in this work. Next, Section 3 describes the simulation setup and the set of resistive defects injected into the SRAM cells. Section 4 discusses the results obtained from simulations and compares the different technological nodes. Finally, Section 5 presents this work's final considerations.

Background

FinFET circuits have been adopted as a way to continue the scaling of ICs and fulfill the performance requirements established by the miniaturization-oriented goals of More Moore. Thus, it is of vital importance to understand the aspects of FinFET-based SRAM arrays and the faults related to this new technology in order to identify discrep-ancies caused by resistive defects. In this Section, main characteristics of FinFET technology and FinFET SRAM design are discussed, followed by the background on the fault models associated to resistive-open and resistive-bridge defects.

FinFET Characteristics

FinFET transistors are quasi-planar, multi-gate devices consisting of vertical silicon islands, denominated "fins", with metal wrapped around the gate and placed on top of the oxide. The first fabricated structure alike FinFETs was the DELTA [START_REF] Hisamoto | A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET[END_REF], a doublegate MOS transistor manufactured in 1989. Afterward, other transistor structures were proposed aiming to surpass the scalability limitations of the CMOS technology [START_REF] Colinge | FinFETs and other multi-gate transistors[END_REF]. It is possible to design different FinFET structures based on the way the transistors are fabricated. In Silicon-On-Insulator (SOI) FinFETs, fins are built over Buried Oxide (BOX) and are isolated from the substrate. In Bulk FinFETs, the fin is connected directly to the substrate through the oxide layer, and a Shallow Trench Isolation (STI) of oxide is formed on the side. FinFETs can also be classified based on their gate configuration. In Shorted-Gate (SG) FinFETs, all three sides of the gate are physically shorted in order to create a single terminal, allowing a higher on-current and lower off-current. In Independent-Gate (IG) FinFETs, the top part of the gate is etched in order to create two independent gate terminals. This offers the possibility of applying different signals in each terminal, enabling the modulation of 𝑉 "# of the front-gate by biasing the back-gate. However, this also implies in a certain area penalty due to the necessity of two separate gate contacts [START_REF] Bhattacharya | FinFETs: From Devices to Architectures[END_REF].

The fundamental design parameters of a FinFET transistor are its fin's height (𝐻 %&' ), its thickness (𝑇 %&' ), and channel length (𝐿 * ). Other parameters, such as Gate Oxide Thickness (𝑇 +, ), Gate Work Function, Body Doping, Source/Drain Doping, and Supply Voltage complete the typical parameters [START_REF] Simsir | Fault modeling for FinFET circuits[END_REF]. Fig. 1 depicts the architecture of a Bulk FinFET transistor and its main parameters. In this work, the bulk-FinFET technology is studied. The main advantage of this technology is to minimize the Short-Channel Effect (SCE), allowing the continuity of the downscaling of integrated circuits. This is possible due the improved control of gates over the conduction channel, bringing other benefits such as high density and low operational voltage.

Static Random Access Memories

A standard 6T SRAM cell is composed of six transistors; four of them form two crosscoupled inverters (M1 & M2, M3 & M4), while the other two act as Pass Gates (PG, M5 and M6), providing read and write access to the cell. The word line (WL) controls the two PG nMOS transistors that are each connected to their respective bit lines (BL and 𝐵𝐿). The value stored in the cell corresponds to the digital representation of the voltage on Q ('1' for 𝑉 .. , '0' for 0V). Fig. 2 shows a schematic of an 6T SRAM cell designed with SG-FinFET transistors. Jointly, a group of SRAM cells forms a matrix structure, allowing data storage in any combination of rows and columns. All cells share electrical connections: vertically, through the bit line, and horizontally, through the word line. Each cell has a unique position (address), so it is possible to access each one of them individually by the appropriate selection of word and bit lines. Address decoders, write drivers, registers, and sense amplifiers complete the set of peripheral circuitry working to guarantee the proper operation of the memory. Fig. 3 depicts an example of this architecture. This structure is well known and a more detailed explanation can be found in literature.

Memories can operate in three distinct modes: hold mode, read mode, and write mode. In hold mode, no operations are being performed on the cell. The word line is off, and the cell has no connection with the rest of the memory array. In read mode, bit lines are pre-charged to V 00 and word line is turned on, enabling the cell to discharge BL or BL based on the stored value. During write mode, word lines are turned on and bit lines are kept in opposite voltage levels in order to force the new value into the cell.

FinFET SRAM

Technology scaling of conventional CMOS SRAMs are limited due to the random variations of threshold voltage (𝑉 "# ) caused by Random Dopant Fluctuation. As high doping is not required in FinFETs due to their enhanced SCE, Random Dopant Fluctuation is expressively reduced, which diminishes 𝑉 "# variations and allows 𝑉 .. to be scaled down. Furthermore, reduced Random Dopant Fluctuation also improves the Static Noise Margin (SNM) and consequently enhances the cell's robustness [START_REF] Bhattacharya | FinFETs: From Devices to Architectures[END_REF]. Moreover, improved sub-threshold swing allows not only lower 𝑉 "# for a given off-state leakage current, but also enhances the on-state current per device width. Such improvements shorten the read and write access times on SRAM cells. Thus, the FinFET technology can bring many specific advantages to SRAM memories' performance and stability.

The SRAM cell's structure is divided into three parts, with the proper notation of (PU:PG:PD) to describe its configuration, where PU, PG and PD stand for: Pull-Up, composed of the two pMOS transistors of the inverters; Pass Gate, consisting of the two pass-through nMOS transistors; and Pull-Down, which are the two nMOS transistors of the inverters, respectively. One of the drawbacks of designing SRAM cells with FinFET technology is the discrete nature of fins limited to a quantized number. Distinct configurations using different numbers of fins have been proposed for FinFET-based SRAM cell designs [START_REF] Karl | A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry[END_REF][START_REF] Jan | A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications[END_REF][START_REF] Burnett | FinFET SRAM design challenges[END_REF]. For this work, the High-Density configuration presented in [START_REF] Burnett | FinFET SRAM design challenges[END_REF] of (1:1:1) was adopted.

Fault Models Associated to Resistive Defects

Due to imperfections on the manufacturing process, memory cells may be affected by manufacturing defects such as resistive-open and/or resistive-bridge defects that can compromise the correct behavior of the device. These defects can be characterized as strong or weak defects based on the nature of the fault they sensitize: strong defects are related to static faults, while weak defects are associated to dynamic faults. Faulty behaviors can be specified using Fault Primitive (FP), which characterizes the sensitizing sequence (S), the faulty behavior observed (F), and the output of read operations (R) [START_REF] Van De Goor | Functional memory faults: a formal notation and a taxonomy[END_REF][START_REF] Hamdioui | Testing static and dynamic faults in random access memories[END_REF], following the notation <S/F/R>. A non-empty set of fault primitives is known as a Functional Fault Model (FFM). FPs can be classified as static or dynamic according to the number of required operations in order to sensitize the fault. Furthermore, the number of necessary operations to sensitize the fault may depend on many factors, such as defect resistance, operating temperature, process corner, among others [START_REF] Dilillo | Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution[END_REF].

Furthermore, an FP can also be classified by the number of cells involved: singlecell and multi-cell FP. In a single-cell FP, faulty behaviors are only observed in the defective cell. In multi-cell FP (also known as coupling-faults), two cells (or two groups of cells) interact to produce a fault. The cell that suffers the faulty behavior is the victim (v-cell), while the cell that triggers the fault is the aggressor (a-cell). It is important to note that the resistive defect can be present either in the a-cell and/or in the v-cell [START_REF] Van De Goor | Functional memory faults: a formal notation and a taxonomy[END_REF][START_REF] Hamdioui | Testing static and dynamic faults in random access memories[END_REF].

Since an FFM is defined as a set of FPs, FFM will assume their characteristics, resulting in the follow classifications: static and dynamic FFM; single-cell and multi-cell FFM. In more details, FFMs can represent the following fault space that was considered in this work, and described in [START_REF] Fonseca | Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes[END_REF] and [START_REF] Van De Goor | Functional memory faults: a formal notation and a taxonomy[END_REF]:

• Stuck-at Fault (SAF): A cell is said to have a SAF (even know State Fault) when the cell is stuck and stores only one logic value '0' or '1'; • No Store Fault (NSF): This fault is the opposite to SAF, where a cell with NSF cannot retain any logic value in their nodes; • Transition Fault (TF): A cell is said to have a TF if it fails to undergo a transition from '0' to '1' or vice versa when it is written; • Write Disturb Fault (WDF): A cell is said to have a WDF if a non-transition write operation causes a transition in it; • Read Destructive Fault (RDF): A cell is said to have an RDF if a read operation performed on the cell changes the data in the cell and returns the incorrect value to the output. This type of fault can also have a dynamic behavior classified as dRDF; • Deceptive Read Destructive Fault (DRDF): A cell is said to have a DRDF if a read operation performed on the cell returns the correct logic value, but changes the contents of the cell. This type of fault can also have a dynamic behavior classified as dDRDF; • Incorrect Read Fault (IRF): A cell is said to have an IRF if a read operation performed on the cell returns an incorrect logic value, even though the correct value is still stored in the cell. This type of fault can also have a dynamic behavior classified as dIFR; • Weak Read Fault (WRF): A cell is said to have a WRF when, during the read operation, the sense amplifier cannot produce the correct logic output due to the small voltage difference between bit lines; • Disturb Coupling Fault (CFds): This fault occurs in groups of at least two cells, called aggressor (a-cell) and victim (v-cell), and is sensitized when a read or write operation in an a-cell affects a v-cell or a group of v-cells, forcing them to change their stored values. This type of fault can also have a dynamic behavior classified as dCFds; • Transition Coupling Fault (CFtr): This fault occurs when a transition write operation performed on the v-cell fails due to a given logic value stored in the a-cell. Thus, the fault is sensitized by a write operation on the v-cell and setting the a-cell into a given state. • Read Disturb Coupling Fault (CFrd): This fault occurs when a read operation performed on a v-cell changes the data in the cell and returns the incorrect value on the output if a given value is present in the a-cell. This type of fault can also have a dynamic behavior classified as dCFrd. • Incorrect Read Coupling Fault (CFir): This fault occurs when a read operation performed on a v-cell returns an incorrect value on the output when a given value is present in the a-cell. This type of fault can also have a dynamic behavior classified as dCFir.

Table 1. Functional Fault Models and their respective Fault Primitives.

FFM FPs SAF < 0/1/->; < 1/0/-> NSF < 0/-/->; < 1/-/-> TF < 0w1/0/->; < 1w0/1/-> WDF < 0w0/1/->; < 1w1/0/-> RDF < 0r0/1/1 >; < 1r1/0/0 > dRDF < 0w0r0/1/1 >; < 0w1r1/0/0 >; < 1w0r0/1/1 >; < 1w1r1/0/0 > DRDF < 0r0/1/0 >; < 1r1/0/1 > dDRDF < 0w0r0/1/0 >; < 0w1r1/0/1 >; < 1w0r0/1/0 >; < 1w1r1/0/1 > IRF < 0r0/0/1 >; < 1r1/1/0 > dIRF < 0w0r0/0/1 >; < 0w1r1/1/0 >; < 1w0r0/0/1 >; < 1w1r1/1/0 > WRF < 0r0/0/? >; < 1r1/1/? > CFds < x;0/1/->; < x;1/0/-> dCFds < xx;0/1/->; < xx;1/0/-> CFtr < x;0w1/0/->; < x;1w0/1/-> CFrd < x;0r0/1/1 >; < x;1r1/0/0 > dCFrd < x;0w0r0/1/1 >; < x;0w1r1/0/0 >; < x;1w0r0/1/1 >; < x;1w1r1/0/0 > CFir < x;0r0/1/0 >; < x;1r1/0/1 > dCFir < x;0w0r0/1/0 >; < x;0w1r1/0/1 >; < x;1w0r0/1/0 >; < x;1w1r1/0/1 >
Table 1 shows the FFMs observed in this work and their respective FPs. As previously mentioned, an FFM is composed by a set of FPs represented by <S/F/R>. On single-cell faults, S may assume none or one operation of read or write for a static FFM, and two or more operations for dynamic FFM.

For simplification purposes, FPs of dynamic FFMs are represented with only two operations. F represents the faulty behavior of the cell, and is represented by a logic '1' or '0'. R is the output of a read operation, represented by a logic '0' or '1'. In case no read operation is performed, '-' is adopted, while '?' is used when it is not possible to determine the output value. For coupling faults, S assumes the form of x;y, in which x is the operation in the a-cell and y is for v-cell. Furthermore, xx is used to represent a dynamic behavior of more than one operation. It's important to note that in this work, dynamic FPs are comprised of a write operation followed by consecutive n read operations. Thus, it's necessary to repeatedly read a cell and evaluate the retrieved value [START_REF] Van De Goor | Functional memory faults: a formal notation and a taxonomy[END_REF] .

Simulation Setup

In order to provide the proposed analysis, electrical simulations have been performed on HSPICE adopting a FinFET SRAM block composed of 1024 lines and 1024 columns each, connected to functional blocks, using a 20nm low-power PTM compact model and considering temperatures of -40ºC, 27ºC, and 125ºC. Furthermore, this work analyzes the impact of resistive defects on SRAM blocks designed in smaller technological nodes, such as 16nm, 14nm, 10nm, and 7nm. Table 2 presents the supply voltage adopted for each node. The operational clock signal frequency chosen is set to 1GHz. In order to simplify and fasten the simulations, only 8 lines consisting of 8 columns each were implemented, while the remaining cells were emulated by capacitances. To recreate an SRAM block as genuine as possible, auxiliary circuitry was used. A differential sense amplifier was adopted for read operations, while write operations were assisted by write buffers. Pre-charge circuits, row-decoders, and registers complete the setup. All circuits, including memory cells, were designed using the low power technological library. As stated before, the SRAM cell was designed using only one fin in each transistor to achieve higher densities.

Modeled Defects

In this work, a set of 12 defects was modeled and injected into a memory cell, one at a time. Six of them are classic resistive-open defects, previously studied for bulk CMOS technology [START_REF] Borri | Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test[END_REF]. In summary, resistive-open defects are non-designed resistances between two nodes that have a connection. Fig. 4 depicts the scheme adopted to model the resistive-open defects.

The other six defects analyzed are considered resistive-bridge defects, which are resistive connections between nodes that, upon design, were not connected [START_REF] Dilillo | Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution[END_REF]. Fig. 5 shows the set of resistive-bridge defects analyzed in this work. DFB1-DFB5 are classic resistive-bridge defects that have been previously analyzed in CMOS technology [START_REF] Fonseca | Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes[END_REF]. DFB6 is a new defect that, considering FinFET architecture, may create a bridge between drain and source of transistors [START_REF] Liu | On modeling faults in FinFET logic circuits[END_REF]. Due to cell's symmetry, only one instance of each defect is necessary to analyze their impact on the cell's behavior.

Evaluation of Defect Size on Fault Behavior

To analyze the impact of each defect on the behavior of memory cells, an automated tool was developed. For each defect, simulations were performed while varying the resistance value of modeled defects up to a maximum of 20MΩ, or until the occurrence of a static fault. The resistance on this iteration is defined as "upper limit" and, based on this resistance value, the tool simulated the circuit again using increasingly weaker resistances in order to observe either dynamic faults or fault-free behavior.

Applying this procedure, it is possible to observe three distinct cases: the defect is too weak to sensitize any type of fault at logic level; the defect is weak, but great enough to sensitize dynamic faults; and the defect is great enough to sensitize static faults. The output of read operations and internal nodes of the cell are analyzed in order to identify faults.

To evaluate defects that result in single static faults, simple verification of the value is performed after the defect is injected. Single write and read operations (0𝑟0, 1𝑟1, 0𝑤0, 0𝑤1, 1𝑤0 and 1𝑤1) are executed to analyze static faults. To evaluate dynamic faults, a write followed by n read operations were performed (0𝑤0𝑟0 7 , 0𝑤1𝑟1 7 , 1𝑤0𝑟0 7 and 1𝑤1𝑟1 7 , where n is number of operations). Note that n was defined to be at maximum 50 read operations. The analysis for coupling faults is similar, with the exception that for this type of fault, operations may be performed in certain cells, while evaluation is performed in a different cell or group of cells in the array.

Results

This Section summarizes the results and discusses the relation between defect size and cell behavior. First, results obtained for resistive-open defects and resistive-bridge defects considering the 20nm node in a nominal temperature of 27°C are presented. Next, an evaluation comparing the behavior of this same node in temperatures of -40°C and 125°C is presented. These analyses were first presented in [START_REF] Copetti | Analyzing the Behavior of FinFET SRAMs with Resistive Defects[END_REF], and are further extended in this work by repeating the same experiment using smaller technological nodes. In all analyses, the obtained results are the fault observed and the critical resistance.

Resistive-Open Defects

Results for resistive-open defects are shown in Fig. 6, which illustrates the relation between defect size and faults observed on affected cells at room temperature (27ºC). For DFO4, within the specified range of 0-20MΩ no faults were observed at 27°C. Observing the remaining defects, it is possible to conclude that DFO1 is the most critical one; it demonstrates a fault free interval of only 15.3kΩ. Dynamic behaviors were only reported for DFO2 and DFO3. It is possible to summarize the results: TFs can be observed for defects DFO1, DFO5, and DFO6. RDF and dRDF can be observed injecting RODF3. Finally, DRDF and dDRDF are observed when injecting DFO2 and DFO3.

Resistive-Bridge Defects

As previously mentioned, resistive-bridge defects create connections between nodes that were not planned upon design. Therefore, depending on the defect size, such defects may actively unbalance the cell and cause faults such as NSF and SAF. The full relation between defect size and observed faults is depicted in Fig. 7. From the obtained results, it is possible to conclude that the most critical resistive-bridge defect is DFB3 as it creates the greatest faulty behavior interval (from 0 to 46kΩ). However, there is a different aspect of resistive-bridge defects the results draw special attention to: as such defects create connections, a resistive-bridge defect affecting one cell may have an impact in other fault-free neighbor cells, causing Coupling Faults (CF). In Fig. 7, this was defined as "Array Impact", and observed in DFB5 and DFB6. It is important to mention that these "Array Impact" faults affected fault-free cells. Fig. 8 depicts this behavior. It shows the simulation of a cell that is located at row 0 and is affected by a resistive-bridge defect (DFB5) that creates a connection between the word line 0 (WL0) and BL 8888 of magnitude 11.5 kΩ. This defect size does not sensitize any fault in a-cell, as shown in Fig. 7. A write '0' operation is successfully performed on the cell, followed by three consecutive read operations in the same cell on row 0. The faulty behavior is observed in a v-cell in row 1, as a dynamic CFrd, and in a v-cell in row 2 as a CFrd. By performing a read operation on row 1 (Fig. 8), BL 8888 is not able to charge as it is being drained by the WL0. This results in an IRF, as can be seen in the Out signal. As all of the three analyzed cells are located on the same column, they all share the same output signal. A subsequent read operation has a bigger impact, causing a dynamic CFrd on the cell. The same destructive behavior is observed when performing subsequently read operations in another fault-free cell from a different row, this time a static CFrd can be observed. Additionally, operations performed on fault-free cells can affect defective cells as long as they are in the same column. This way, the fault-free cell is the aggressor and the faulty cell is the victim. Fig. 9 illustrates this fault behavior on a cell affected by DFB6, which creates a resistive-bridge between source and drain of transistor M5, connecting BL 8888 and Q : . As the fault-free cell on row 2 is written, the value on the defective cell on row 1 is flipped. This happens due to the shared connection between BL 8888 and Q : . As BL 8888 is discharged due to a write '0' operation, Q : discharges as well, causing a misbalancing, and eventually a flip on the stored value. This can also be considered as a "following-signal" behavior, as Q : follows the value on BL 8888 . The same behavior is observed on cells affected by DFB4, as the affected node is now connected to WL. Fig. 10 depicts this particular behavior. It shows the simulation of a cell affected by a DFB4 of magnitude 13kΩ. In Fig. 7, this behavior is classified as SAF. This defect creates a connection between Q : and WL. This way, Q : follows the voltage on WL, causing an inconsistent behavior that may not be trivial to detect. The behavior observed resembles an SAF as the cell can only store '1' while the word line is off.

Analysis considering different operating temperatures

Table 3 shows the comparison between the critical resistances for resistive-open and resistive-bridge defects considering three different temperatures, -40°C, 27°C, and 127°C. Analyzing the results obtained throughout simulations, it is possible to observe that for each defect, a similar relation between critical resistances and temperature exists. In DFO1, DFO2, DFO3, DFO4, DFO6, DFB2, and DFB5 (register) an increased The operating temperature affects the critical resistances, since the current capabilities of the transistors are also affected. In this manner, the process of charging and discharging the nodes and the resistive-open and bridge defect's value are affected by temperature. On the one hand, for resistive-open defects, the high temperature facilitates the occurrence of faults, because it lowers the critical resistance. However, for DFO5, low resistance slightly moved the cell's operational window to a more convenient period within higher temperatures, resulting in an improvement of operation in this design. Further, it is interesting to note, that DF4 only causes faults at the highest temperature setting.

0 0,9 Voltage [V] Resistive Bridge -DF6 Row 0, Q Row 0, 0 Voltage [V] Row 2, Q Row 2, 0 0,9 Voltage [V
On the other hand, resistive-bridge defects are more likely to sensitize faults considering lower temperature. Note that the critical resistance value necessary to cause RDFs decreases with temperature for DFB2 and DFB3, because the resistance alters the discharge characteristics of nodes. Note that for resistive-bridge defects a smaller resistance value represents a stronger defect. Considering DFB5, it is possible to observe that the TF occurs with a smaller resistance value when simulating the memory cell operating at -40ºC. Finally, coupling faults are more prominent in low temperature, since a weaker defect is necessary to cause the fault.

The presented analysis considering different operating temperatures demonstrates a pattern for FinFET-based SRAMs and will further assist in future researches on evaluating weak resistive defects' impact on memory cells.

Analysis considering different nodes

In order to evaluate critical resistances for smaller nodes, an extensive fault mapping process was carried out, adopting different technological nodes: 16nm, 14nm, 10nm, and 7nm. Table 4 to 9 present the faults observed in each simulation setup, including the 20nm node as reference. The resistance values shown represent the critical resistance responsible to sensitize a fault at logic level. The tables are grouped in two sets according to the kind of defect. In the first set, the critical resistance associated to resistive-open defects is analyzed considering three different operating temperatures. The second set presents the results for bridge defects. Table 4 presents the results obtained for resistive-open defects considering the temperature of 27ºC. Analyzing the summarized results, it is possible to observe a significant change in critical resistance for the same defect in different technological nodes. The only exception is DFO1, whose critical resistance remained around 14kΩ. Note that with DFO4 no faults have been observed for the considered temperature range. For all other resistive-open defects, the scale-down of technological nodes made them less relevant as only stronger defects are now necessary to sensitize faults. In fact, the critical resistance for DFO2 in a 20nm node is more than 30 times smaller when compared to its critical resistance in 7nm technology. A similar behavior can be observed in the results shown in Tables 5 and6, which present the results obtained for the simulations injecting resistive-open defects with operating temperature set to 125ºC and -40ºC, respectively. Once again, all defects presented a significant increase in critical resistance, except for DFO1. Note also that DFO4 only caused faults when considering a temperature of 125ºC and the range of resistance used in the executed simulations. In Tables 7,8, and 9, the results obtained from the analysis of faults caused by resistive-bridge defects in the temperatures of 27°C, 125°C and -40°C are shown, respectively. Analyzing the results obtained in Table 7, it is possible to observe a significant change in critical resistance (increasing 84%) for the defect DFB1, when moving from 20nm to 7nm technology. Reducing the technology node also causes some variation to the value of critical resistance for the remaining defects. The lowest values tend to appear for the 14nm technology, while for 7nm the value increases when compared to any other technology node simulated.

It is important to mention that some faults are masked by others. This happens to TF in DFB1, which is masked by NSF and SAF. This also occurs with WRF in DFB2 and DFB3. In older technologies, a well-defined range for such behavior is encountered, while FinFET's technology range of transitions is comparably diffuse, since the critical resistance values often differ by less than 1kΩ. There are presented some faults with the same value, because this faults are noted for some nodes, but are masked for another. For example, in DFB1 for the 7nm technology, WRF and RDF are masked by NSF.

Observing some faults, the SAF can be notice that the value stuck-at could be different, according how the resistance is presented in the cell. For example, in defect DFB2, SAF is stuck-at '1', however this would be '0' if the resistance are connected to Q : . Fr the CFir array faults of DFB5 and DFB6, the value of critical resistance keep the higher in all cases; this event occurs due the variations in the register's sensibility in the set of 𝑉 .. and frequency operation used. Analyzing the data of Table 8 and9, it is observed that the effect of temperature variation is more prominent in the 7nm node, whose the critical resistance in Table 8 is lower than the 20nm node. However, in Table 9 the situation is inversed and the critical resistance of the 7nm node is higher. It may be noted that the dynamic fault occurrence rate is higher when compared to open defects for all nodes.

Final Remarks

This work presents an analysis of the behavior of FinFET-based SRAMs affected by resistive defects. The range of analyzed defects is vast and includes weak resistive-open and weak resistive-bridge defects that may escape manufacturing tests. Faulty behaviors detected by an automated tool were mapped and categorized in different kinds of faults. Further, the impact of defects on other cells of the array was evaluated, showing that defects that do not sensitize faults in the defective cell may still compromise the behavior of other cells. The fault models categorized comprise single and couple, static and dynamic faults. Finally, each defect was further characterized considering three different operating temperatures (-40°C, 27°C, and 125°C) and five technological nodes (20nm, 16nm, 14nm, 10nm, and 7nm). Except for DFO5, increasing the temperature amplify the impact of resistive-open defects on memory cells. Moreover, a significant increase in critical resistance was observed when mapping faults in smaller technologies, especially for DFO4. Thus, it is possible to conclude that only stronger defects will sensitize faults in further scaled memories.

As for resistive-bridge defects, each defect showed a particular behavior when considering different operating temperatures, mainly the 7nm that suffers great variations for temperature variation. Besides some exceptions, lower temperatures increase the critical resistance. Coupling faults were observed in cells affected by DFB5 and DFB6.

Dynamic faults will increase their range of appearance with the reduction of technology, to the open defects consequently the 7nm technology presents a high dynamic fault rate. Considering bridge defect the occurrence of dynamic faults is variable. It is important to mention that weak defects, that do not cause any faulty behavior, may become a reliability concern over lifetime. Under these circumstances, the necessity to adopt defect-oriented test methodologies for performing the manufacturing test procedures increases.

It is important to highlight that weak defects, that do not cause any faulty behavior, may become a reliability concern over lifetime. Under these circumstances, the necessity to adopt defect-oriented test methodologies for performing the manufacturing test procedures increases.

Finally, with this mapping and characterization of different resistive defects, it is possible to start analyzing the impact of these defects when considering memory block's in combination with other reliability issues, such as aging and/or noise tolerance.

Fig. 1 .

 1 Fig. 1. Structure of bulk-FinFET transistors

Fig. 2 .

 2 Fig. 2. FinFET-based SRAM-cell

Fig. 3 .

 3 Fig. 3. Architecture of an SRAM memory.

Fig. 4 .

 4 Fig. 4. Resistive-open defects injected into a SRAM cell.

Fig. 5 .

 5 Fig. 5. Resistive defects injected into a SRAM cell.

Fig. 6 .

 6 Fig. 6. Faults observed during simulations of SRAM cells affected by resistive-open defects of different magnitudes.

  0

  0

Fig. 8 .

 8 Fig. 8. Simulation output of a cell affected by a resistive-bridge causing faults on other cells of the array.

Fig. 9 .

 9 Fig. 9. Simulation output of a cell affected by a resistive-bridge defect suffering a destruction fault caused by an operation in a neighbor cell.

  critical resistance. On the contrary, DFO5, DFB1, DFB3, DFB4, DFB5 (cell and array) and DFB6 are more prominent in lower temperatures.

Fig. 10 .

 10 Fig. 10. Simulation output of a cell affected by a resistive-bridge defect connecting Q : to the word line.

Table 2 .

 2 Supply voltage of the analysed technological nodes.

	Technological Node	𝑉 ..
	20nm	0.90V
	16nm	0.85V
	14nm	0.80V
	10nm	0.75V
	7nm	0.70V

s Size[kOhm] DFB6 (Array Impact) CFir

									DFB1						WRF
																		RDF
			5	10		15	20	25		30		35	40	45	50	NSF
								Defect's size [kOhm]
									DFB2							dRDF
																		RDF
	0		2	4		6	8		10	12		14	16	18		20
								Defect's size [kOhm]					SAF
									DFB3						dRDF
																		RDF
	0		5	10		15	20	25	30		35	40		45	50	TF
								Defect's size [kOhm]					SAF
									DFB4
																		SAF
	0		1,5	3		4,5	6	7,5	9		10,5	12		13,5	15
								Defect's size [kOhm]
										DFB5						IRF
	0		1,5	3		4,5	6	7,5		9		10,5	12	13,5	15	TF
								Defect's size [kOhm]
							DFB5 (Array Impact)			CFir
																		CFrd
	0	3,5	7	10,5	14	17,5	21	24,5	28	31,5	35	38,5	42	45,5	49		CFtr
								Defect's Size[kOhm]
									DFB6
																		CFds
	0		1,5	3		4,5	6	7,5		9		10,5	12	13,5	15	SAF
								Defect's Size[kOhm]
	0	3	6	9	12	15	18	21	24	27	30	33	36	39	42	45	48
								Defect'

Table 3 .

 3 Critical Resistance Values for Different Temperatures.

	DF	-40°C	Temperature 27°C	125°C
	DFO1	16.9kΩ (TF)	15.3kΩ (TF)	13.6kΩ (TF)
	DFO2 297kΩ (dDRDF)	144kΩ (dDRDF)	73kΩ (dRDF)
	DFO3	137kΩ (dRDF)	71.5kΩ (dRDF)	37.2kΩ (dRDF)
	DFO4	-	-	6.6MΩ (dRDF)
	DFO5	1.4MΩ (TF)	1.47MΩ (TF)	1.6MΩ (TF)
	DFO6	2.58MΩ (TF)	2.46MΩ (TF)	2.23MΩ (TF)
	DFB1	54.4kΩ (WRF)	41.6kΩ (WRF)	30.8kΩ (WRF)
	DFB2	13.9kΩ (dRDF)	13.8kΩ (dRDF)	14.8kΩ (dRDF)
	DFB3	54.6kΩ (dRDF)	46.4kΩ (dRDF)	37.8kΩ (dRDF)
	DFB4	14.1kΩ (dRDF)	13.2kΩ (dRDF)	12.8kΩ (dRDF)
	DFB5	1.74kΩ (TF) 57.5kΩ (dCFir)	2.13kΩ (IRF) 49.5kΩ (dCFir)	3.53 kΩ (IRF) 38.2kΩ (dCFir)
	DFB6	11.61kΩ (SAF) 52.6kΩ (dCFir)	10.92kΩ (SAF) 44.0kΩ (dCFir)	10.52kΩ (SAF) 32.0kΩ (dCFir)

Table 4 .

 4 Critical Resistances for resistive-open defects at 27°C.

	Defect	Fault	20nm	Critical Resistance [kΩ] 16nm 14nm 10nm	7nm
	DFO1	TF	15.3	13.8	12.2	13.7	16.6
		DRDF	144.3	225.2	463.9	937.4	4500.0
	DFO2	RDF	165.4	232.2	505.4	-	-
		dDRDF	144.2	224.5	461.0	923.8	4041.2
	DFO3	RDF dRDF	71.6 71.5	103.4 103.3	190.1 189.5	357.9 356.3	1345.9 1324.8
	DFO5	TF	1471.1 1858.0	2385.6	2778.4	3137.5
	DFO6	TF	2457.5 3665.9	5105.0	6055.0	7685.0

Table 5 .

 5 Critical Resistances for resistive-open defects at 125°C.

	Defect	Fault	20nm	Critical Resistance [kΩ] 16nm 14nm 10nm	7nm
	DFO1	TF	13.6	11.5	9.5	10.1	11.2
	DFO2	RDF dRDF	73.1 73.0	93.0 92.8	137.7 137.4	206.3 205.9	420.3 420.0
	DFO3	RDF dRDF	37.3 37.2	46.2 46.1	64.9 64.8	92.8 92.7	182.3 182.1
	DFO4 dDRDF 6598.7 17662.9	-	-	-
	DFO5	TF	1566.9 1947.0	2440.5	2851.4	3145.8
	DFO6	TF	2231.5 3384.4	4671.6	5485.2	6225.0

Table 6 .

 6 Critical Resistances for resistive-open defects at -40°C.

	Defect	Fault	20nm	Critical Resistance [kΩ] 16nm 14nm 10nm	7nm
	DFO1	TF	16.9	16.0	14.9	17.4	21.7
	DFO2	DRDF dDRDF	297.4 296.7	694.6 680.2	-7414.0	--	--
	DFO3	RDF dRDF	136.7 136.6	261.3 260.4	1301.3 1285.0	-9187.6	--
	DFO5	TF	1393.5	1764.7	2278.1	2713.3	3060.8
	DFO6	TF	2575.3	3830.4	5345.0	6360.0	7985.0

Table 7 .

 7 Critical Resistance Values for DFB at 27°C.

	Defect		Fault	20nm	Critical Resistance [kΩ] 16nm 14nm 10nm	7nm
			NSF	26.67	32.93	49.14	58.70	75.78
	DFB1		WRF RDF	43.11 35.21	45.38 37.85	49.14 49.14	58.70 58.70	75.78 75.78
		dRDF	35.39	43.73	50.04	59.80	76.88
		SAF1	11.98	11.09	10.58	11.38	13.40
	DFB2		TF RDF	11.98 13.80	11.09 12.18	10.60 11.36	11.42 12.34	13.92 14.40
		dRDF	14.04	12.20	11.44	14.62	15.56
		SAF0	13.22	12.82	12.56	12.55	15.04
	DFB3		TF RDF	13.46 46.41	13.42 45.48	13.10 45.42	13.14 53.03	17.60 66.92
		dRDF	46.42	45.49	45.44	53.04	67.00
	DFB4	SAF0 RDF	13.20 13.20	12.32 12.82	11.54 12.64	12.56 13.80	15.02 16.26
		Cell	TF IRF	1.65 2.12	1.66 2.02	1.36 1.24	1.37 1.26	2.29 2.34
			CFtr	1.67	1.67	1.36	1.37	2.32
	DFB5	Array	CFrd CFir dCFrd 11.92 11.36 50.19	10.68 26.31 10.86	9.40 24.29 9.61	10.34 27.50 10.66	12.24 38.98 12.36
			dCFir	50.20	10.87	24.40	27.66	39.01
		Cell	SAF0	10.92	10.02	9.67	10.26	11.16
	DFB6	Array	CFds CFir dCFir	11.86 44.00 44.01	10.02 22.83 22.88	9.67 20.81 20.88	10.26 24.02 24.12	11.16 35.50 35.65

Table 8 .

 8 Critical Resistance Values for DFB at 125°C.

	Defect	Fault	Critical Resistance [kΩ] 20nm 16nm 14nm 10nm	7nm
			NSF	18.70	18.52	20.16	27.27	43.88
	DFB1	WRF RDF	32.09 21.88	29.55 20.04	30.31 21.26	35.69 27.63	44.06 43.80
		dRDF	21.97	20.14	21.36	28.07	44.06
		SAF1	11.60	10.12	9.21	9.61	10.78
	DFB2		TF RDF	11.60 14.78	10.12 12.14	9.21 10.44	9.61 10.56	10.80 11.50
		dRDF	14.95	12.20	10.68	10.68	11.60
		SAF0	12.86	11.20	9.88	10.38	11.80
	DFB3		TF RDF	12.86 37.81	12.22 34.63	9.96 32.66	10.42 36.25	12.84 42.77
		dRDF	37.82	34.64	32.68	36.26	42.79
		SAF0	12.84	11.18	9.86	10.36	11.80
	DFB4		RDF	12.84	11.18	10.22	10.36	12.16
		dRDF	12.85	11.19	10.41	10.53	12.17
		Cell	TF IRF	1.57 3.48	157 3.54	1.24 2.77	1.20 2.83	2.00 3.06
	DFB5	Array	CFtr CFrd CFir	1.57 10.74 38.74	1.57 9.19 16.12	1.24 7.60 14.96	1.21 8.11 17.76	2.02 9.20 23.36
			dCFrd	10.78	9.21	7.67	8.19	9.25
		Cell	SAF0	10.52	9.09	8.44	8.84	9.55
	DFB6	Array	CFir dCFir	10.52 31.99	9.09 12.25	8.44 11.09	8.84 13.89	9.56 19.49

Table 9 .

 9 Critical Resistance Values for DFB at -40°C.

	Defect	Fault	Critical Resistance [kΩ] 20nm 16nm 14nm 10nm	7nm
			NSF	47.35	60.60	66.90	83.08 113.81
	DFB1	WRF RDF	55.74 55.05	60.60 60.60	66.91 66.90	83.08 113.81 83.08 113.81
		dRDF	56.14	61.02	67.12	85.45 114.74
		SAF1	12.76	12.34	12.20	13.38	16.22
	DFB2		TF RDF	12.76 13.86	12.40 12.92	12.46 12.44	13.92 13.38	18.48 16.28
		dRDF	14.04	13.73	14.03	16.17	20.14
		SAF0	14.08	13.78	13.56	15.20	18.92
	DFB3		TF RDF	14.99 54.62	15.34 55.99	14.02 58.51	15.70 71.21	22.96 96.33
		dRDF	54.63	56.00	58.52	71.29	97.02
	DFB4	SAF0 RDF	14.06 14.08	13.76 13.76	13.54 13.54	15.20 15.20	18.92 18.92
		Cell	TF IRF	1.74 0.64	1.84 0.58	1.51 0.81	1.55 0.87	2.89 3.16
			dRDF	0.65	1.81	1.52	1.58	2.66
	DFB5	Array	CFtr CFrd CFir	1.74 11.88 57.61	1.84 12.04 33.07	1.52 11.12 31.38	1.54 12.64 38.05	2.85 15.44 49.53
			dCFrd 13.12	12.05	11.44	12.65	15.82
			dCFir 57.62	33.08	31.39	38.06	49.54
		Cell	SAF0 11.62	11.00	10.60	10.96	12.96
	FB6	Array	CFds CFir	12.86 52.58	12.92 28.04	12.86 24.25	14.30 30.92	12.96 42.40
			dCFir 52.59	28.06	24.27	30.94	42.42