Joao Oliveira

Herv É Morel

Dominique Planson

Florent Loiselay

Analysis of Parasitic Elements in Power Modules Based on GaN Components

This paper aims to evaluate a GaN based power module for automotive applications. Simulations and experiments were then performed on a classical double pulse test bench. In regard to EMC, the oscillations on the Vds after device turn-off is quite important. The comparison between a simulation without considering the 3D wiring model and a simulation by considering the wiring elements is presented. The impact of the parasitic elements modelling is seen through the resonance frequencies found. Experimental results of operation of the converter are presented to validate the simulation approach.

Introduction

The need to increase power electronic performances has motivated the development of new researches on semiconductor devices, such as GaN-HEMT switches. They are promising components for fast switching, high efficiency and thus high power density power module design [START_REF] Jones | Review of commercial gan power devices and gan-based converter design challenges[END_REF]. However, as the wide-band gap devices have a high switching speed, combined with parasitic inductive and capacitive elements of the power module, which yields to electromagnetic perturbations [START_REF] Liu | Methodology for emc analysis in a gan based power module[END_REF], [START_REF] Liu | Parasitic elements modeling and experimental identification in a gan hemt based power module[END_REF]. Great efforts have been devoted to the developments of modules based in GaN for medium-voltage switching applications because of their much lower specific onresistance with respect to voltage breakdown when compared with Si-MOSFETs, their higher switching speed than Si-IGBTs, and their high temperature operation capability.

Simulation and Comparison With Double Pulse Test Results

The evaluation plate that we used, consists of a motherboard and an IMS evaluation module. The configuration implemented was a one leg inverter for double pulse tests realization. For all tests we use a switching frequency of 100 kHz. Several double pulse tests based on GS66516B under different load currents were performed. To realize the measurements, we use the differential ISOVU probe TIVH08/TIVH08L with a bandwidth equal to 800 MHz. That probe was used due to the high frequency of oscillation seen on GaN components, so with a normal differential probe some frequencies are hidden.

Operation Point: 100 V and 35 A

As can be seen in the Fig. 2, a good correlation is seen between the simulation and the test results. The frequency 100 MHz is seen on the simulation and with the ISOVU probe, but additional ringing frequencies are present, but not on the simulation. This is the first evidence about the parasitic elements due to PCB tracks.

Operation point: 400 V and 41 A

As can be seen on the simulation and test results of Fig. 2 and3, after the switch turn-off, there is an oscillation at the frequency 1/(2π √ LC) between the output capacitor of the switch (2 × 300 pF@100V and 2 × 150 pF@400V) and the parasitic inductance. This oscillation at the frequency 1/(2π √ LC) is a well-known effect and is for example presented with GaN in the following paper [START_REF] Liu | Parasitic elements modeling and experimental identification in a gan hemt based power module[END_REF]. In the LTSpice simulation, the parasitic power loop inductance was adjusted at 100 V in order to have the measurement and simulation first frequency matching at 100 MHz. Without having to readjust the parasitic inductance value (L = 4.1 nH), we also obtained matching frequency for simulation and tests at 400 V, around 140 -150 MHz. It is also to note that the LTSpice simulation shows an exponential decrease of the oscillation while the measurements of Fig. 3 do not show an exponential decrease.

Tab. 2: Comparison between simulated and measurement results under condition: 400 V and 41 A.

Parameters: LTSpice ISOVU Probe Overshooting (V) 425 438 Rise time (ns) 7.7 11.4 Freq. 1 (MHz) 146 144 Freq. 2 (MHz) --- 223 Freq. 3 (MHz) --- ---
Based on the results achieved, we can conclude that for higher oscillation frequencies, it is noticed a considerable gap between their values and amplitudes. Therefore, it is necessary to add lower capacitances and inductances in the simulation to achieve accurate oscillations simulations at higher frequencies.

3D Model of the Power Loop Inside the Simulation

As the voltage and current increase, the parasitic effects become more evident and new oscillation frequencies can be seen. In order to understand the measurement of oscillations containing multiple frequencies, it was decided to include a 3D model of the power loop inside the LTSpice simulation. The power module is modelled with ANSYS SpaceClaim and then the Q3D Extractor is used to extract of the parasitic elements [START_REF] Liu | Parasitic elements modeling and experimental identification in a gan hemt based power module[END_REF].

For modelling of the power module, some considerations should be given. Initially, the geometry is built on SpaceClaim and then exported to Q3D Extractor. Before running the simulation, it is mandatory to check if there are some contacts between the objects of the 3D model. All intersections must be eliminated. Another important point is the definition of the NETs (region with the same electrical potential). Regions simpler implies to a mesh operation easier, therefore with fewer possibilities of error for the simulation. It is also necessary to define the frequency where we only have surface currents on the device. For this case, it is used 150 MHz.

When using Q3D simulation in LTSpice, PCB trace modelling allows us to see higher frequencies on switching waveforms. This is very important for switching loss estimation and knowing where the design of the converter should be improved [START_REF] Taki | Mod élisations orient ées cem d'un convertisseur de puissance pour une optimisation multi-physique[END_REF].

Operation point: 400 V and 71 A

It is important to emphasize the variation of the midpoint voltage waveforms between 41 A and 71 A operation, as seen in Fig. 3 and4. The simulation (LTSpice with Q3D) and the test results show similar behavior with a none monotonous decrease of the oscillation amplitude. This can be explained by the mutual inductance effect and the accurate calculation of parasitic elements performed by the 3D Model. Stray impedances are extracted by using Q3D extractor providing RLC elements with the same solver by combining finite element method and the method of moments. Moreover, we can note a good frequency match for the operation points evaluated.

Tab
The differences found in the switching frequencies for different level currents at the same voltage can be related to the mutual inductances effect. When we increase the current level that crosses a track, the mutual inductance effect on another conductor is more intense. The strong voltage overshoot value is related to the power commutation loop, as well as the distance between the decoupling capacitors and the IMS power module. The ideal case would be to use the capacitors as close as possible to the switches [START_REF] Lu | A high power-density and high efficiency insulated metal substrate based gan hemt power module[END_REF].

Parasitic Analysis

The modelling of partial inductances is based on 3D model of the power module, on different current paths defined by the position of the Q3D excitation, and on the distance between conductors due the coupling effect [START_REF] Akhbari | Mod èle de cellule de commutation pour les etudes de pertes et de performances cem[END_REF]. In Fig. 5, we can see the modelling of the power module performed on Space-Claim and Q3D. The system is composed of three main parts: PCB driver, IMS power and a heat sink.

Parasitic capacitance is another point very important to PCB design. The voltage applied on the switches increases, the output capacitance decreases, therefore it is possible to observe higher oscillation frequencies. The common mode capacitances have influences from a frequency of 200 MHz, and this is seen by the values from the capacitance matrix generated by Q3D.

To analyse the role of the parasitic elements, we had tried to analyse for instance the impact of the layout between the middle point and the drain of the low-side switch, Fig. 6.

In Fig. 7, it is possible to see the coupling at 100 MHz due the power loop inductance and the equivalent output capacitance, as well as the parasitic elements associated. Similarly, in Fig. 8 we can see that the coupling for a frequency of 280 MHz is due a resonance between the equivalent inductance L eq = 9.1 nH on the drain low side switch and the parasitic capacitances. In this case, the equivalent inductance is calculated considering the self and mutual inductances on the power commutation loop. Also, the capacitance of only one switch is considered to explain the 280 MHz frequency. It is possible because when we have a high current level, the unbalanced current becomes more evident [START_REF] Yade | Improved layout of inverter for emc analysis[END_REF].

In Fig. 9, by the simulation we can see that the equivalent inductance adjusts the source drain voltage (Vds) to match the middle point voltage waveform (Vph). These components are directly linked to the paths of disturbances in common mode, therefore the modelling of these components is essential in the prediction of voltage disturbances [START_REF] Rondon-Pinilla | Conception de convertisseurs électroniques de puissance à faible impact électromagn étique int égrant de nouvelles technologies d'interrupteurs à semiconducteurs[END_REF]. The influence of the parasitic element L eq can be demonstrated using a superposition of voltage waveforms, Eq. ( 1). This paper presents an approach for the evaluation of the parasitic elements of the PCB. The base principle is to regard the three main resonant frequencies in the voltage waveforms of the middle point and drain-source. Good results have been found by simulation. The values of the estimated elements have been compared to the ones extracted by a numerical tool. Clearly the use of a 3D model for extraction of the parasitic elements improves the simulation and measurements fitting.

V ph-calc = V ds + L eq dI d dt (1)
The analysis of the electromagnetic disturbance is easier in the frequency domain than in the time domain. In the frequency domain it is easier to see which frequency bands have more contribution to the source of electromagnetic disturbance and thus to determine a solution to reduce the disturbances.

To further investigate the concept of the parasitic elements on converters based GaN components, the authors are working on an instrumented PCB that will be able to perform impedance measurements, a better 3D modelling and voltage measurements, in order to validate the Q3D model parasitic. The analysis of the role of the parasitic elements need a strong effort to analyse and optimise the layout of the circuit. This will be achieved in a future study.

Fig. 1 :

 1 Fig. 1: Evaluation board from GaN Systems.

Fig. 2 :

 2 Fig. 2: Condition test: 100 V and 35 A. (a) Midpoint voltage from simulation and (b) its FFT. (c) The voltage on the midpoint from measurement results and (d) its FFT from the measurement results.

Fig. 3 :

 3 Fig. 3: Condition test: 400 V and 41 A. (a) Midpoint voltage from simulation and (b) its FFT. (c) The voltage on the midpoint from measurement results and (d) its FFT from the measurement results.

Fig. 4 :

 4 Fig. 4: Condition test: 400 V and 71 A. (a) Midpoint voltage from simulation and (b) its FFT. (c) The voltage on the midpoint from measurement results and (d) its FFT from the measurement results.

Fig. 5 :

 5 Fig. 5: GaN System power module in Q3D Extractor.

Fig. 6 :

 6 Fig. 6: IMS layout between the middle point and the drain of the low side switch.

Fig. 7 :Fig. 8 :Fig. 9 :

 789 Fig. 7: Electric diagram of the resonant loop to the frequency at 100 MHz.


Alban Gossard

Frédéric De Gournay

Pierre Weiss

Off-the-grid data-driven optimization of sampling schemes in MRI

We propose a novel learning based algorithm to generate efficient and physically plausible sampling patterns in MRI. This method has a few advantages compared to recent learning based approaches: i) it works off-the-grid and ii) allows to handle arbitrary physical constraints. These two features allow for much more versatility in the sampling patterns that can take advantage of all the degrees of freedom offered by an MRI scanner. The method consists in a high dimensional optimization of a cost function defined implicitly by an algorithm. We propose various numerical tools to address this numerical challenge.

Introduction

The design of efficient sampling patterns in MRI is a critical issue with a long history [START_REF] Bernstein | Handbook of MRI pulse sequences[END_REF] and a renewed interest in recent years with the advent of compressed sensing and deep learning.

State-of-the-art The most recent trends can be separated in two families

Compressed sensing theory: In a recent set of works, the theory of compressed sensing was improved to more closely fit the practical issues of MRI [START_REF] Chauffert | Variable density sampling with continuous trajectories[END_REF][START_REF] Adcock | Breaking the coherence barrier: A new theory for compressed sensing[END_REF][START_REF] Boyer | On the generation of sampling schemes for magnetic resonance imaging[END_REF][START_REF] Boyer | Compressed sensing with structured sparsity and structured acquisition[END_REF]. In a nutshell, these works suggest that good sampling schemes should have a variable density: the low frequencies should be sampled more densely than the high frequencies (though this has little to do with the quantity of energy present in the signal) and the samples should cover the space locally uniformly. This led a few authors to generate sampling schemes by minimizing the distance bewteen a measure µ belonging to a set of admissible measures and a continuous target probability density function π:

inf µ∈A dist(µ, π), (1)
where dist is a distance that metrizes the weak convergence, such as a discrepancy [START_REF] Gräf | Quadrature errors, discrepancies, and their relations to halftoning on the torus and the sphere[END_REF][START_REF] Chauffert | A projection method on measures sets[END_REF] or the Wasserstein distance [START_REF] Lebrat | Optimal transport approximation of 2dimensional measures[END_REF] and A is a set of admissible probability measures such as the set of discrete measures supported on M points

M M = {µ = 1 m M m=1 δ xm , x m ∈ R d }
or more exotic sets of contraints that more closely describe the physical constraints of a scanner. This approach led to remarkable practical results [START_REF] Lazarus | Sparkling: variable-density k-space filling curves for accelerated t2*-weighted mri[END_REF] that are currently evaluated for clinical routine.

Learning: Motivated by the recent breakthroughs of learning and deep learning, many authors recently tried to learn either the reconstructor [START_REF] Hammernik | Learning a variational network for reconstruction of accelerated mri data[END_REF], the sampling pattern [START_REF] Baran Gözcü | Learning-based compressive mri[END_REF][START_REF] Sherry | Learning the sampling pattern for mri[END_REF], or both [START_REF] Hwan | Self-supervised deep active accelerated mri[END_REF]. In [START_REF] Baran Gözcü | Learning-based compressive mri[END_REF], the authors propose a greedy algorithm that generates a sampling pattern by iteratively selecting a discrete horizontal line that maximizes the SNR of the reconstructed image. A similar principle is proposed in [START_REF] Hwan | Self-supervised deep active accelerated mri[END_REF], but there, the reconstructor is learnt simultaneously. In [START_REF] Sherry | Learning the sampling pattern for mri[END_REF], the authors adopt a similar approach, but replace the greedy algorithm by a bi-level programming approach that controls the number of sampling points using an 1 penalization. Overall, all those works suffer from the same limitations:

• The sampling points are required to live on a Cartesian grid, which is suboptimal.

• The methods cannot incorporate advanced constraints on the sampling trajectory and therefore focus on "rigid" constraints such as imposing to sample horizontal lines.

• The methods are computationally intensive, which may be not be so critical since the sampling schemes are generated offline.

To the best of our knowledge, the only paper that addresses the above criticisms is the just posted [START_REF] Weiss | Pilot: Physics-informed learned optimal trajectories for accelerated mri[END_REF], where the authors simultaneously optimize a reconstructor and a sampling scheme by performing a local optimization of a well initialized trajectory.

Our contribution In this paper, we propose to blend both approaches by using a data-driven distance in (1) rather than more principled approaches. This allows us to avoid all the abovementioned flaws. This also leads us to implement a set of advanced numerical routines to address the computational challenges raised by the proposed cost function.

2 The proposed approach

Preliminaries

We assume that both a set of training images x = (x 1 , . . . , x K ) ∈ C N ×K and a differentiable image quality metric η : R N × R N → R + are available. In this work, we will simply consider the squared

2 distance η(x, x) = 1 2 x -x 2 2 .
In what follows, we let ξ ∈ (R d ) M denote a set of locations in the k-space (or Fourier domain), y ∈ C M denote a set of k-space measurements and R : C M × (R d ) M → C N denote a fixed reconstructor, i.e. for a sampling scheme ξ ∈ (R d ) M and a measurement vector y ∈ C M , we let x = R(ξ, y) denote the reconstructed image. We let A(ξ) ∈ C M ×N denote the forward Fourier transform defined for all

1 ≤ m ≤ M and x ∈ C N [A(ξ)x] m = N n=1 x n exp(-i p n , ξ m ), (2)
where p n ∈ {-N/2, . . . , N/2 -1} d are the positions of grid points in the image space. For a regularization parameter λ > 0, we consider a Tikhonov reconstructor:

R 1 (ξ, y) = argmin x∈C N 1 2 A(ξ)x -y 2 2 + λ 2 x 2 2 , (3)
and a nonlinear compressed sensing type reconstructor

R 2 (ξ, y) = Ψz , z = argmin z∈C P 1 2 A(ξ)Ψz -y 2 2 + λ z 1 , (4
) where Ψ ∈ C N ×P is a redundant wavelet transform.

The principle

The goal here is to replace the distance in (1) by a data-driven cost function. A natural choice reads:

min ξ∈Ξ F (ξ) := E x∈x η(R(ξ, A(ξ)x + b), x) , (P)
where b ∼ N (0, σ 2 I N ) and Ξ ⊆ (R d ) M describes the physical constraints. In words, the term A(ξ)x + b represents noisy data acquisition that we want to reconstruct as well as possible, in average, using the reconstructor R. The expectation is taken w.r.t. the noise realizations.

Differentiating the reconstructors Solving (P) is a real computational challenge. It is high dimensional, the cost function does not have a simple analytic formula and its regularity properties are unclear. Since the cost function is defined through another minimization problem, (P) can be interpreted as a bi-level optimization problem. Various approaches are available to solve it [START_REF] Bard | Practical bilevel optimization: algorithms and applications[END_REF]. Here we will follow the approach suggested in [START_REF] Ochs | Bilevel optimization with nonsmooth lower level problems[END_REF]. Instead of solving the lower-level minimization problems ( 3) or ( 4) exactly, we assume that they are solved approximately using iterative algorithms such as a conjugate gradient method or a proximal gradient descent. The main idea is then to differentiate the algorithm using dedicated libraries such as PyTorch instead of the minimizer itself.

Implementing and differentiating the NUFT The fast implementation of the linear mapping A(ξ) is the backbone of our approach. It corresponds to the non uniform Fourier transform (NUFT). Various efficient approximate implementations have been devised over the past [START_REF] Jeffrey | Nonuniform fast fourier transforms using min-max interpolation[END_REF][START_REF] Greengard | Accelerating the nonuniform fast fourier transform[END_REF][START_REF] Keiner | Using nfft 3-a software library for various nonequispaced fast fourier transforms[END_REF] and Python toolboxes begin to emerge [START_REF] Lin | Python non-uniform fast fourier transform (pynufft): An accelerated non-cartesian mri package on a heterogeneous platform (cpu/gpu)[END_REF]. Our experience using them however led to unstable results due to significant numerical errors. In this work, we therefore opted for a direct (naive) implementation of the NUFT on massively parallel architectures, following the numerical experiments conducted in KeOps. The main observation is that for a GPU with 1TFlop, applying the NUFT to small 128×128 images (which is typical in this field) just requires a fraction of second, which is compatible with large scale computations. We therefore implemented a homemade NUFT within PyTorch, allowing for automatic differentiation.

Optimizing the cost function The previous details allow to automatically compute the derivative of F w.r.t. ξ when replacing the expectation by an empirical average. This in turn allows to use any off-the-shelf optimization solver. In this preliminary work, we simply set Ξ = (R d ) M (i.e. no constraints between samples), and b = 0 (no noise in the measurements) and used a limited memory BFGS algorithm. More advanced stochastic gradient approaches are expected to be used later.

Results

Here we report preliminary results with this approach. Two 64 × 64 images are studied and we compare 3 patterns subsampled at a factor 3.3. Our approach is abbreviated OSP (optimal sampling pattern), we also use a low-frequency pattern (LF) and a variable density sampler with a uniform density (VDS).

The images are reconstructed both with the linear (3) and nonlinear reconstructors (4). Without surprise, LF is good at reconstructing global shape of images and removing noise but the VDS performs better to reconstruct details (with the disadvantage of generating noise). Our OSP combines both advantages. Our approach shows that choosing an optimized k-space improves the peak noise-to-signal ratio (PSNR) between 2dB and 10dB for these test-cases in comparison to variable density sampling or standard low-frequency sampling. In the future, we plan to focus on learning a reconstructor, adding physical constraints to the set Ξ and introducing the noise b.

Figure 1 :Figure 2 :

 12 Figure 1: Original images (1a) square and (1b) phantom. Different k-space sampling pattern: (1d)VDS and (1c) LF random sampling.

Figure 3 :

 3 Figure 3: Reconstructed images with nonlinear reconstructor (4) for LF (3a), VDS (3b), OSP (3c) given in (3d).

Figure 4 :

 4 Figure 4: Reconstructed images with Tikhonov reconstructor (3) for LF (4a), VDS (4b), OSP (4c) given in (4d).

Figure 5 :

 5 Figure 5: Reconstructed images with nonlinear reconstructor (4) for LF (5a), VDS (5b), OSP (5c) given in (5d).

Acknowledgments

This work was supported by the ANR Optimization on Measures Spaces and of ANR-3IA Artificial and Natural Intelligence Toulouse Institute.


Besar Asllani
email: besar.asllani@supergrid-institute.com

Hervé Morel

Pascal Bevilacqua

Dominique Planson

Demonstration of the Short-circuit Ruggedness of a 10 kV Silicon Carbide Bipolar Junction Transistor

Keywords: «Power Semiconductor Device», «Silicon Carbide (SiC)», «Bipolar Junction Transistor», «MOSFET», «Robustness», «Reliability»

Static, switching and short-circuit characterization of a 10 kV-class Silicon Carbide (SiC) Bipolar Junction Transistor (BJT) is reported. The 2.4 mm² SiC BJT show good static and switching behavior. The current gain is low compared to literature, but several issues have been identified and can be improved. For the first time, the Short-circuit ruggedness of a 10 kV SiC-BJT is reported. These tests show outstanding performance with at least 16 µs withstand time. Several samples have been brought to failure and revealed an outstanding 52.1 J/cm 2 of short-circuit critical energy at 32% of breakdown voltage. The failure seems to happen on the top face metallization since the devices failed in blocked mode and the base-emitter terminals shorted. The SiC BJT handles without failing at least 3 times the critical Short-circuit energy of the commercial SiC MOSFETs. In addition, switching performance is much better than that of Si-IGBTs.

Introduction

SiC power devices are now hitting mass production for automotive applications [START_REF]Applications | Automotive[END_REF]- [START_REF]SiC for automotive applications[END_REF]. These devices cover the 650 V-1700 V range. Higher-voltage devices were announced by the main manufacturers, but may take time to be brought to the market because of the high demand for automotive applications. As such, commercial devices for Medium Voltage and High-Voltage Direct Current (MVDC and HVDC) applications are not available yet. For these applications, high voltage (> 10 kV) switches and diodes would be ideal. In addition, for such a high-voltage device, the unipolar conduction mode leads to higher conduction losses than the bipolar conduction mode [START_REF] Johannesson | Potential of ultra-high voltage silicon carbide semiconductor devices[END_REF]. For these reasons, at SuperGrid Institute the choice for bipolar devices was made and the specifications were: 10 kV -50 A SiC Bipolar Junction Transistors (BJT) and PiN diodes. This initiative yielded 3 production runs for PiN diodes and 1 run for BJTs. The fabricated devices were tested in static, dynamic and short-circuit conditions. Their state-of-the-art performance is reported in [START_REF] Asllani | 10 kV Silicon Carbide PiN Diodes-From Design to Packaged Component Characterization[END_REF], [START_REF] Asllani | Static and Switching Characteristics of 10 kV-class Silicon Carbide Bipolar Junction Transistors and Darlingtons[END_REF]. This paper reports the superior short-circuit ruggedness of the 10 kV SiC BJT and provides potential improvement ideas in order to yield an even better device with lower static and dynamic losses.

Static Characteristics

The structure of the BJT is an interdigitated device with a cell pitch between 25 µm and 35 µm. Several geometrical variations were made on the emitter and base width in order to find the optimal design. The tested devices had a size of 2.62.6 mm 2 for an active area of 2.4 mm 2 . They were packaged in a custom packaging for testing purposes only. The structure of the elementary cell pitch, the schematic packaging and the finished device are shown in Fig. 1 from left to right. For the breakdown voltage measurements, a FUG 12,5kV SMU in series with a Keithley 6485 Picoamperemeter was employed, while the device were placed in a vacuum chamber to prevent flashovers. As shown in Fig. 2, the breakdown voltage is half of the targeted one due to a fabrication defect. The peripheral protection implantation dose was higher than expected. This problem has been corrected for the third run of the PiN diodes that withstand more than 12 kV [START_REF] Asllani | 10 kV Silicon Carbide PiN Diodes-From Design to Packaged Component Characterization[END_REF]. The same improvement can be made on the BJT and the same results are expected. The static forward characterization of the devices have been carried out by means of a Keysight B1506. Due to voltage limitations (60 V max) of the Ultra High Current module of the device analyzer, it was impossible to measure the characteristics of the device beyond this limit. A custom test bench was used to enable higher base current and higher collector emitter bias. The output characteristics carried out on the B1506 are reported in Fig. 3 whereas in Fig. 4 they are compared to the results obtained on the custom test bench. The BJT responds well to the base current and a 4.5 A (187 A/cm 2 ) collector current can be injected at 60 V of collector emitter voltage and a base current of 1 A. At 100 A/cm 2 the specific on-state resistance is about 198 mΩ•cm². Bu cm². But at a base current of 2 A and a collector current density of 200 A/cm 2 the on-state resistance drops to 120 mΩ•cm². Bu cm² which shows a resistivity modulation, classical in a bipolar device. For an epitaxy able to withstand 13 kV [START_REF] Asllani | 10 kV Silicon Carbide PiN Diodes-From Design to Packaged Component Characterization[END_REF], this value is slightly better than the unipolar limit and shows that resistivity modulation can be achieved on these devices. The current gain has been measured both by means of a B1506 power device analyzer and with the custom test bench. The results obtained with the B1506 are reported in Fig. 5. The measurements have been carried out at room temperature and at 150 °C. The best performing devices show a β = 9.5 at room temperature. One other issue is related to base current and collector emitter voltage limitations of the device analyzer, which are respectively 1 A and 60 V. As a matter of fact, the size of the device under test is too small and the base access resistance is too high, which leads to a high on-state resistance. B1506 device analyzers are conceived to characterize devices with higher current levels and lower on-state resistance. With the custom test bench used for switching characterizations, we were able to observe current amplification values at a higher voltage. A maximum beta of 21 at a collector current of 20.5 A (854 A/cm²) and a collector emitter voltage of 150 V was measured. The measurements were carried out on a short pulse configuration (< 10 µs) in order to mitigate selfheating effects which could alter the results. These measurements yield a beta of 21 for an on-state resistance of 175 mΩ•cm². Bu cm² at 854 A/cm 2 . The current gain value can be considered to be low as compared to literature [START_REF] Salemi | 15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain[END_REF]- [START_REF] Zhang | 10 kV, 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC[END_REF]. The reasons for this are both technological. First one is related to the thickness of the base layer which is chosen to be thick to avoid its punch. By an improvement of the depth of the base contact etching the thickness of the base layer can be greatly reduced. The second is related to the base current surface recombination due to interface traps present at the interface between the base and the passivation oxide [START_REF] Asada | Determination of Surface Recombination Velocity From Current-Voltage Characteristics in SiC p-n Diodes[END_REF], [START_REF] Asada | Effects of Parasitic Region in SiC Bipolar Junction Transistors on Forced Current Gain[END_REF]- [START_REF] Ghandi | Fabrication of 2700-V 12-Ω•cm². Bu cm2 non ion-implanted 4H-SiC BJTs with common-emitter current gain of 50[END_REF]. To reach a high current gain a small base width is needed, but that yields to a high base access resistance. To improve this, a higher interdigitation must be employed. Several techniques can be employed to improve the second parameter and can drastically lower both the on-state resistance and the power losses in the driver by increasing the current gain of the device. The identified improvements both in terms of breakdown voltage and current gain give hope for a better device with a bigger active area in a near future.

Switching Characteristics

The devices switching performances have been tested on a custom test bench. A 1.4 mH air core inductor in parallel with two 1.7 kV JBS diodes in series were mounted on the high side while the SiC BJT was mounted on the low side. The driver used for the BJT base emitter junction biasing is the formerly commercial GA15DDJT22-FR4 SJT driver from GeneSiC. This driver is capable of providing a typical current of 7 A at the turn on and 2 A continuous. The schematic of the test bench is shown in Fig. 7. The switching waveforms produced with this setup are shown in Fig. 8 and confirm the outstanding performance of the 10 kV-class SiC BJT. Turn-on happens in less than 90 ns and turnoff in less than 100 ns. Both the dV/dt and di/dt measured during the switching are very high compared to silicon devices. The turn-on (at 417 A/cm 2 ) and turn-off (at 854 A/cm 2 ) energies are as low as 133 mJ/cm 2 and 717 mJ/cm 2 respectively. The driver losses are not included in the calculation as the actual driver is not optimized for this device, but for the sake of clarity they are shown in Fig. 9. Driver losses can be significant since the current amplification is relatively low compared to literature. The driver losses are shown in Fig. 9 (right). One can observe that most of the losses are due to the constant base current bias. An optimized BJT with higher current gain would lower these losses and make them negligible compared to the switching losses of the device.

Short-Circuit Tests

The main interest of this paper is the short-circuit robustness of the 10 kV-class SiC BJT. Theoretically SiC BJTs should outperform both planar and trench SiC MOSFETs in terms of shortcircuit withstand time and critical energy. This is expected since the temperature of the MOSFET's channel increases rapidly when submitted to short-circuit conditions and since the channel is close to the gate oxide a significant portion of the heat is transferred to the latter [START_REF] Romano | Short-circuit Failure Mechanism of SiC Power MOSFETs[END_REF]- [START_REF] Fayyaz | Performance and robustness characterisation of SiC power MOSFETs[END_REF]. This endangers the MOSFET especially when very high voltage is applied. On the other hand, the SiC BJT does not have a gate oxide. This means that even if the temperature in the BJT rises above the MOSFET's critical temperature it will not be damaged as much since the conduction happens in the volume of the SiC. To prove this point, for the first time in the knowledge of the authors, short-circuit tests were carried out on a 10 kV SiC BJT. The resulting waveforms are reported in Fig. 10. One can see that the applied voltage is 3250 V and the short-circuit duration has been varied from 3 µs to 16 µs without showing any signs of degradation or failure. The BJT was able to block no matter the duration of the shortcircuit. The energy that was dissipated in the device equals 1.25 J which corresponds to 52.1 J/cm 2 if we consider only the active area. This amount of energy density is at least 3 times higher (16,4 J/cm 2 ) than the best performing (short-circuit wise) 1200 V discrete SiC MOSFET of the market [START_REF] Boige | Caractérisation et modélisation électrothermique compacte étendue du MOSFET SiC en régime extrême de fonctionnement incluant ses modes de défaillance : Application à la conception d'une protection intégrée au plus proche du circuit de commande[END_REF]. Several devices were brought to failure after repetitive (1 s apart) short-circuit events. The results presented in Fig. 12 were obtained while increasing the short-circuit duration. The first pulse which lasts 15 µs is apparently creating some damage. The second attempt reveals the effect of the damage since the collector current exhibits some delay compared to the base current pulse. Once triggered the devices seems to withstand the short-circuit. The collector current rises to the nominal value as compared to the previous test. On the third attempt even though the base current is exactly the same as previously, the device does not switch on but behaves as a current limiter. After measurement, the base and emitter contacts show a short-circuit behavior which witnesses the fusion and shorting of the top layer metallization. This can be considered as a "safe" failure mode since the device would limit the current and slowly shut down instead of going into thermal runaway [START_REF] Boige | Gate leakage-current analysis and modelling of planar and trench power SiC MOSFET devices in extreme short-circuit operation[END_REF]- [START_REF] Chen | Study of short-circuit robustness of SiC MOSFETs, analysis of the failure modes and comparison with BJTs[END_REF]. This behavior has been observed on commercially available 1200 V SiC MOSFETs under very particular short-circuit bias [START_REF] Boige | Caractérisation et modélisation électrothermique compacte étendue du MOSFET SiC en régime extrême de fonctionnement incluant ses modes de défaillance : Application à la conception d'une protection intégrée au plus proche du circuit de commande[END_REF] and is a feature that could be exploited in future application. One advantage of the power BJT is the absence of gate oxide and all the related reliability issues. If no explicit test of the baseplane dislocation aging was carried out, no observation which would imply this phenomenon was made, despite the numerous static characterizations and high-current commutation measurement on the tested BJTs.

Conclusion

The 10 kV-class SiC BJT static, switching and short-circuit performance were assessed. The device has a current gain of at least 21 at a very high current density (854 A/cm 2 ). The gain has to be improved for the sake of the driver simplicity and power losses. The device shows outstanding switching times and an exceptional short-circuit ruggedness. This confirms that the SiC BJTs are far more robust than SiC MOSFETs in terms of short-circuit and may find their place in applications where this property is required. The critical short-circuit energy density of the BJT is 52.1 J/cm 2 . "Safe" short-circuit failure mode was identified where the device shuts down due to a short between base and emitter electrodes. High temperature (> 150°C) applications can be enabled due to the absence of gate oxide and its related robustness issues.

Fig. 1 :

 1 Fig. 1: The elementary cell pitch, the internal connection schematic and the finished packaged device from left to right.

Fig. 2 :

 2 Fig. 2: The measured breakdown voltage of the 10 kV-class SiC BJT.

Fig. 3 :

 3 Fig. 3: The output characteristics of the 10 kV-class SiC BJT obtained with a B1506.

Fig. 4 :

 4 Fig. 4: The output characteristics of the 10 kV-class SiC BJT carried out on a B1506 (red squares) as compared to the results obtained on the custom test bench (black circles).

Fig. 5 :

 5 Fig. 5: Current gain of the BJT as a function of the current collector for 25 °C (black dots) and 150°C (red squares) measured with a B1506.

Fig. 6 :

 6 Fig. 6: Current gain and collector emitter voltage as function of the collector current at a base current of 1 A.

Fig. 7 :

 7 Fig. 7: Double pulse test setup used to characterize the BJT.

Fig. 8 :

 8 Fig. 8: Switching waveforms of 10 kV SiC BJT. Full wave (up), turn-on (left), turn-off (right)Due to the problem with the peripheral protection, the BJT switching performance assessment was limited to a 3 kV bus voltage.

Fig. 9 :

 9 Fig. 9: Base emitter voltage and base current (left) and the resulting drivers power losses (right).

Fig. 10 :

 10 Fig. 10: Short-circuit ruggedness of the 10 kV SiC BJT. No degradation or failure was observed even at 16 µs duration

Fig. 11 :

 11 Fig. 11: Energy dissipated in the 10 kV SiC BJT during a 16 us short-circuit event.

1 3 2 Fig. 12 :

 212 Fig.12: Failure of the 10 kV-class SiC BJT after 2 repetitive short-circuit events 1 s apart. The dotted curves stand for the collector current. On the third try the device behaves as a current limiting device.

Acknowledgements

The authors wish to acknowledge CALY Technologies for their help with the design and fabrication. Acknowledgments are addressed to DeepConcept also for their help with packaging.