Razvan-Cristian Marin

Member, IEEE Antoine Frappé

Student Member, IEEE Răzvan-Cristian Marin

Digital Complex Delta-Sigma Modulators with Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

Keywords: DSM), Complex Delta Sigma Modulator (CDSM), finite impulse response (FIR), multistandard coexistence, digital transmitter;

Digital complex delta-sigma modulators with highly configurable notches for multi-standard coexistence in wireless transmitters

digital signal processing based on Delta-Sigma Modulators (DSM) can enable the use of highly-efficient power amplifier stages in a digital transmitter. Moreover, techniques such as time-interleaving (TI) [START_REF] Kozak | Efficient architectures for timeinterleaved oversampling delta-sigma converters[END_REF] and multi-channel look-ahead [START_REF] Tanio | An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation[END_REF] can be employed in order to overcome DSM integration challenges and increase the maximum operating frequency. As a result, it is shown in [START_REF] Tanio | An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation[END_REF] that an FPGA implementation of a TI DSMbased all-digital transmitter can reach a maximum effective sampling frequency of 28 GHz and meet the transmit mask of IEEE 802.11a WLAN standard in the 5.2 GHz band.

However, there are still two important issues to be handled in digital transmitters, namely the image replicas and the outof-band noise. First of all, image replicas can be seen very close to the signal when the sampling frequency (fS) is not high enough. For instance, in [START_REF] Alavi | A Wideband 2x13-bit All-Digital I/Q RF-DAC[END_REF], for a signal bandwidth of 154 MHz, image replicas will be very close, at ±300MHz from the center frequency (fc).

Secondly, the out-of-band noise floor injected into a nearby receiver (RX) within another band can affect the coexistence of multiple radios on the same chip.

A. Out-of-band noise vs. multi-standard coexistence

The most stringent noise specifications are found for the GPS band around 1575 MHz, due to the low typical power level of the GPS signal (~ -125 dBm). This issue has been highlighted in [START_REF] Wang | A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter[END_REF], where a noise floor of -130 dBm/Hz is measured in the GPS band when transmitting an 802.11g 54 Mbps signal on Channel 1 with a power of 16.35 dBm. In addition, the same noise requirements apply to the GLONASS band around 1602 MHz (27 MHz away from GPS). Hence, the study of standard coexistence with GPS can be further extended to GLONASS.

In order to target advanced communication standards, [START_REF] Marin | Considerations for High-Speed Configurable-bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI[END_REF] presents the design of a single-bit Delta-Sigma Modulator as part of a digital transmitter, focusing on time-interleaving to enable high-speed applications (up to 6 GS/s sample rate) and large signal bandwidths (up to 160 MHz).

A simple analysis regarding the two issues described before, shows that the performance of this DSM architecture is not affected by image replicas, thanks to the high sampling IEEE Transactions on Circuits and Systems I: Regular Papers (ISSN : 1549-8328) 01/2018 DOI : 10.1109/TCSI.2017.2711035 frequency. It is though affected by the out-of-band quantization noise, since the main function of the DSM is to reduce the inband noise (increase SNR) by pushing it out-of-band. Hence, the amount of out-of-band quantization noise will determine the complexity of the succeeding filtering stage needed to meet stringent coexistence specifications with nearby receivers, in particular GPS/GLONASS.

One solution for the reduction of the out-of-band noise is to introduce analog filtering, which generally requires highquality passive components in order to target one specific communication standard. For example, a 6 pole LC bandpass filter [START_REF] Devices Inc | Linear Circuit Design Handbook[END_REF] with the center frequency fc = 2.4 GHz and a bandwidth BW = 300 MHz can achieve an attenuation of around 40 dB around the GPS band.

However, for 1-bit high-speed DSMs, a FIR-DAC based mixed-signal stage, such as the one presented in [START_REF] Gebreyohannes | A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards[END_REF], offers a good alternative to analog filters. Nevertheless, the designed filter requires a large number of signal taps, resulting in area and power consumption penalty due to the implementation of coefficient cells and control logic.

In this case, the digital filtering constraints could be further relaxed in the DSM stage, by placing complex zeros near the frequency bands, where low noise levels are needed, depending on the targeted application. Still, this assumes complex nonconjugated zeros which lead to an asymmetric noise transfer function (NTF).

B. Known implementation methods of asymmetric NTF

In order to obtain an asymmetric NTF, the In-phase (I) and Quadrature (Q) channels can be cross-coupled, resulting in a Complex Delta-Sigma Modulator (CDSM) as shown in [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF], where a 5 th order modulator is used to match both UMTS and DCS 1800 standards out-of-band spurious emissions.

The approach in [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF] combines both linear algebra and control engineering theories in order to optimize the zeros and poles placement using the state matrix, whereas the modulator is assumed to be stable if i) all the zeros are placed on the unit circle (modulus equal 1) using additional integrator feedback coefficients, and ii) all the poles are inside the unit circle and equispaced on a smaller circle centered on z0 = 1 and of constant radius rc < 1.

Furthermore, [START_REF] Schreier | Delta-Sigma Toolbox[END_REF] introduces an effective design tool used to synthesize the NTF for single-path and quadrature Delta-Sigma Modulators. For a quadrature configuration, the parameters considered for the optimization are the following: the order of the NTF, the oversampling ratio (OSR), the center frequency, the rms (root mean square) in-band noise gain, the rms imageband noise gain, and the number of image-band zeros. Thus, the design methodology is simplified by obtaining an optimum and stable architecture through an iterative process based on the requirements of the quadrature DSM. A detailed description of this tool and the associated functions can be found in [START_REF] Schreier | Understanding Delta-Sigma Data Converters[END_REF].

However, both these methods introduce limitations regarding the design of CDSM. First of all, the approach in [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF] is based on large computational effort in the optimization of poles and zeros, which makes it more difficult to apply to other communication scenarios. For example, for the 5 th order CDSM, the characteristic polynomial has 18 different coefficients to be set, so that the five roots (poles) can meet the poles optimization relations.

Secondly, the method in [START_REF] Schreier | Delta-Sigma Toolbox[END_REF] cannot be used to set zeros based on noise level requirements, because the zeros placement is limited to the image-band only, which is symmetric to the transmit band with respect to fc.

In addition, complex transfer functions have been studied also for Sigma-Delta Modulator (SDM)-based ADCs which can be used in the intermediate frequency (IF) stage of a receiver (RX). Reference [START_REF] Bannon | A 2 nd Order 1bit Complex Switched Capacitor Sigma-Delta ADC with 90dB SNDR in a 180kHz Bandwidth[END_REF] presents a 2 nd order single-bit Complex SDM (CSDM) ADC to be used in a very low IF RX path in GSM/ GPRS/ EDGE phone applications for improved noise shaping (complex NTF), whereas only one integrator stage is complex. The coefficients of the architecture were obtained with a DSM specific design tool, because the custom complex zero is placed extremely close to the signal band (z = -0.02j), and has very little impact on the poles position.

Moreover, in [START_REF] Pandita | Designing Complex ΔΣ Modulators with Signal-Transfer Functions having Good Stop-Band Attenuation[END_REF] the SDM design concentrates on complex signal transfer functions (STF) with good stop-band attenuation, in order to reduce the image-band noise aliasing into the signal band. The algorithm is iterative and applicationdependent, assuming the initial loss-pole (transmission zeros) placement derived in [START_REF] Martin | Approximation of Complex IIR Bandpass Filters Without Arithmetic Symmetry[END_REF] and a minimum NTF magnitude at ω = π / OSR.

Finally, [START_REF] Marttila | Frequency-Agile Multiband Quadrature Sigma-Delta Modulator for Cognitive Radio: Analysis, Design and Digital Post-Processing[END_REF] aims to reduce coefficients mismatch between the I and Q paths in a multi-bit CSDM. The method consists in adding feedback paths from the inputs and outputs of the CSDM to all the integrators inputs, which allows coefficients mismatch compensation (in digital domain) based on a matrix representation of mismatched complex operations.

The present paper details the simplification of the design method for digital CDSM architectures, using additional crosscouplings in order to cancel the complex coefficients in the characteristic polynomial. This allows the decorrelation of the poles optimization and the zeros placement, thus eliminating the aforementioned limitations, concerning the position of the zero, the high computational effort and the lack of configurability. The modified architecture can be obtained using automatic tools with flexible custom zeros placement, for optimized out-of-band noise performances.

Section II presents the model of a 1 st order CDSM, as well as the proposed modified 1 st order architecture which is extended to a general approach for the design of higher order CDSM in Section III. Next, Section IV shows the flexibility of the CDSM scheme as part of a digital transmitter for multi-standard coexistence. Finally, Section V demonstrates a fine/coarse control mechanism with reduced overhead, thanks to additional delays introduced in the cross-coupling paths.

II. COMPLEX DELTA SIGMA MODULATOR MODEL

A. General architecture of 1 st order CDSM

A 1 st order Complex Delta-Sigma Modulator is generally obtained from two standard 1 st order DSMs in quadrature, by cross-coupling the I and Q paths in order to implement an asymmetric noise transfer function (Fig. 1). In order to ease the DSM analysis, the quantizer is often linearized by using an input-independent additive white noise model, with the quantization error sequence e[k] [START_REF] Aziz | An overview of sigmadelta converters[END_REF]. Performing a z-domain analysis on the linear model, we obtain [START_REF] Alavi | A Wideband 2x13-bit All-Digital I/Q RF-DAC[END_REF] where the STF and the NTF of the standard DSM are [START_REF] Wang | A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter[END_REF] (3) and the STF and the NTF of the CDSM are (4) [START_REF] Kozak | Efficient architectures for timeinterleaved oversampling delta-sigma converters[END_REF] Here, XI(z), YI(z), EI(z) and XQ(z), YQ(z), EQ(z) are the ztransforms of the input, output and quantization error for the I and Q paths, respectively.

The input signal is filtered by the signal transfer functions (STFD1 for DSM and STFCD1 for CDSM), whereas the quantization error is shaped by the noise transfer functions (NTFD1 for DSM and NTFCD1 for CDSM), in order to push the quantization noise outside the signal band. Furthermore, the NTF in (5) allows the placement of a complex zero, z = r -jc ≠ 0, thus creating an asymmetric noise shaping based on the outof-band noise requirements. The needed complex zero can be obtained by simply replacing the coefficients r and c from [START_REF] Kozak | Efficient architectures for timeinterleaved oversampling delta-sigma converters[END_REF] with the values corresponding to the targeted normalized frequency (fn), which can be obtained using the relationship between the z-transform and the Fourier transform in [START_REF] Tanio | An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation[END_REF]. [START_REF] Tanio | An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation[END_REF] where A is the modulus of the complex number z.

Analyzing the NTF in (5), we notice a close link between the numerator and the denominator, namely the placement of a custom complex zero (c ≠ 0) results in a characteristic polynomial with complex coefficients. This is particularly problematic in the case of higher-order CDSM (for example 5 th order in [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF]), where the resulting transfer function with complex coefficients cannot be treated with design software, such as the Control System Designer toolbox in MATLAB.

Finally, this leads to two possible directions: we can either study the implementation of improved algorithms similar to [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF], or propose a solution which can reduce the poles optimization to a known problem, thus allowing the use of existing design tools.

The second option, which will be further studied in this paper, suggests the decorrelation between the numerator and the denominator, by cancelling the r and c coefficients in the denominator.

B. Proposed 1 st order CDSM

In order to simplify the design of CDSM, we propose to reduce the characteristic polynomial to the known case of a 1 st order DSM (Fig. 1a) without affecting the placement of the custom complex zero. We can indeed introduce additional feedback paths from the quantizers' outputs to the inputs of the complex modulator. In particular, the direct feedback coefficient is modified from "1" to ax = r and a cross-coupling path with the coefficient cx = c is introduced in the modified CDSM architecture (Fig. 2).

Hence, we can obtain the STF and NTF of the proposed 1 st order CDSM (7) [START_REF] Devices Inc | Linear Circuit Design Handbook[END_REF] when setting ax = r and cx = c.

Therefore, using this CDSM scheme, the denominator from (7-8) is reduced to a simple delay z -1 (independent of r and c, no complex coefficients), whereas the numerator in (8) remains identical to [START_REF] Kozak | Efficient architectures for timeinterleaved oversampling delta-sigma converters[END_REF] and enables the placement of the custom complex zero according to [START_REF] Tanio | An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation[END_REF].

Thanks to the decorrelation between the zeros placement and the characteristic polynomial, the proposed architecture has the advantage of increased configurability in targeting multiple communication scenarios. This is demonstrated in Fig. 3, where the STF, NTF and the associated pole-zero plots are shown for four different custom zeros, namely z1 = 0.25+0.97j, z2 = 0.75+0.66j, z3 = 0.75-0.66j, z4 = 0.25-0.97j.

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ( )) z jE z E z NTF z jX z X z STF z jY z Y Q I Q I Q I + × + + × = + ( ) z z STF D 1 1 = ( ) z z z NTF D 1 1 - = ( ) ( ) jc r z z STF CD + - + = 1 1 1 ( ) ( ) ( ) jc r z jc r z z NTF CD + - + - - = 1 1 n f j Ae jc r z p 2 = - = ( ) ( ) z jc r jc a z z STF x x p 1 1 1 = + - - + = ( ) ( ) ( ) ( ) z jc r z jc r jc a z jc r z z NTF x x p - - = + - - + - - = 1
First of all, we notice that the STF is the same for all the cases, as indicated in [START_REF] Marin | Considerations for High-Speed Configurable-bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI[END_REF]. Secondly, the sign of the imaginary part determines the position of the custom zero, namely if Im(z) > 0, then the normalized frequency is fz > 0. Finally, the normalized frequency can be obtained using [START_REF] Tanio | An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation[END_REF], for example in the case of z1 = 0.25+0.97j, fz1 ≈ 0.21.

In conclusion, this feature becomes very useful in the design of higher-order CDSM, because it allows configurable zeros placement while using existing DSM specific tools (NTF with real coefficients) for the poles optimization, which reduces considerably the number of design iterations and the computational effort.

III. HIGHER ORDER CDSM

The proposed 1 st order CDSM scheme can be extended to higher order architectures in order to provide a general approach for the design of CDSMs. Thus, an n th order CDSM can be built starting from (n-k) real DSM stages, followed by k complex DSM stages, whereas k represents the number of custom complex non-conjugated zeros that need to be added based on the targeted coexistence scenario.

This way, we can combine the advantages of both architectures, namely the increased SNR design margin thanks to the number of real stages (n-k), and the custom complex zeros placement using complex stages, respectively.

In conclusion, we can identify two CDSM cases, namely higher order CDSM with one custom complex zero, and with multiple custom complex non-conjugated zeros, respectively.

A. CDSM with one custom complex zero

Let us consider n = 4 and k = 1, namely three real stages in a Cascade-of-integrators feedback form (CIFB [START_REF] Schreier | Delta-Sigma Toolbox[END_REF]), followed by the proposed complex integrator stage (Fig. 4).

In this case, the output in z-domain is the same as in (1), and the corresponding STF and NTF are given in ( 9) and (10) (9) (10) [START_REF] Schreier | Delta-Sigma Toolbox[END_REF] Consequently, the characteristic polynomial den4(z) presents only real coefficients when c = cx, whereas the influence of r can be cancelled by the ax coefficient. Thus, the decorrelation between the zeros placement and the characteristic polynomial allows the implementation of the architecture based on the coefficient set {a1, a2, a3, ax, g1}, resulting in a design which can be reduced to a known case of standard 4 th order DSM (Fig. 5), as it can be seen from the STF and NTF [START_REF] Schreier | Understanding Delta-Sigma Data Converters[END_REF] (13) [START_REF] Pandita | Designing Complex ΔΣ Modulators with Signal-Transfer Functions having Good Stop-Band Attenuation[END_REF] The differences between the transfer functions of the two architectures (highlighted in Eq. (10-11) and (13-14)) show the transition from a DSM to a CDSM by moving a zero from DC (z = 1) to a custom position (z = r -jc), without affecting the optimization of the poles, i.e. the denominators of the STF and NTF are equivalent for ax = a4 + r -1.

Hence, the proposed CDSM can be designed using existing optimization tools specific to DSM (obtain the coefficient set {a1, a2, a3, ax, g1}), and can target different coexistence scenarios without the need of redesign, as in the case of [10] [11]. Furthermore, the multi-standard coexistence depends now on only two coefficients, r and c, making it easier to provide a configurable solution.

This design simplification is demonstrated through simulation in MATLAB of a practical example and will be described next. First of all, using the Schreier Toolbox in MATLAB, we can obtain the coefficients of a 4 th order DSM, with an oversampling ratio OSR = 100 (for high-speed applications) and a peak gain of the NTF equal to 1.6. The resulting values are [a1, a2, a3, a4, g1] = (0.01, 0.1, 0.41, 0.93, 0.002), and were used to obtain the associated noise transfer function (Fig. 6), where we can observe two zeros at DC and two complex conjugated zeros at the edges of the signal band.

Secondly, as it was mentioned before, the same set of coefficients obtained for the DSM can be used in the design of CDSM with configurable custom zeros placement. In order to verify this feature, let us consider two different frequency bands, f0.05 = -0.05 (close to the signal band) and f0.15 = -0.15 (out-of-band). Using ( 6) we can obtain the corresponding complex numbers z0.05 = 0.95 -0.31j, and z0.15 = 0.59 -0.81j. These values are further introduced in Eq. [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF][START_REF] Schreier | Delta-Sigma Toolbox[END_REF] in order to obtain the NTFs shown in Fig. 6, whereas ax,0.05 = 0.93 + 0.95 -1 = 0.88, and ax,0.15 = 0.52.

( ) ( )

z den z STF p 4 4 1 = ( ) ( ) ( ) ( ) ( ) ( ) ( ) z den g z z z NTF p 4 1 2 4 1 1 jc r z - - × + - × - = ( ) ( ) ( ) ( ) ( ) ( ) + - × + + - × - × + - = 2 3 1 2 4 1 1 1 z a g z z z den x a r z ( ) 1 2 1 a z a + - × + ( ) ( ) z den z STF D D 4 4 1 = ( ) ( ) ( ) ( ) ( ) ( ) z den g z z z NTF D D 4 1 2 4 1 1 1 z - × + - × - = ( ) ( ) ( ) ( ) ( ) ( ) + - × + + - × - × + - = 2 3 1 2 4 1 1 1 z a g z z z den D 4 a 1 z ( ) 1 2 1 a z a + - × + IEEE
Hence, we notice that one of the zeros previously at DC is moving its position on the unit circle, depending on the values of r and c, without changing the position of the poles in all three cases (pole-zero plot in Fig. 6).

When compared to the 4 th order DSM, the out-of-band noise integrated in the targeted frequency bands (f0.05 and f0. [START_REF] Martin | Approximation of Complex IIR Bandpass Filters Without Arithmetic Symmetry[END_REF]) is considerably reduced in the CDSM case. However, the complex zeros placement will cause a noise redistribution leading to a degradation of SNR which becomes larger with the distance between the position of the zeros and fc.

This effect (highlighted in Fig. 6) is specific to CDSM architectures in general, and implies a design trade-off between a reduced noise level in a specific frequency band, and overall SNR performances. This type of situation is encountered in stringent multi-standard coexistence scenarios, e.g. in a mobile application an 802.11 transmitter working in the 2.4 GHz band coexisting with a GPS receiver working in the 1.6 GHz band on the same chipset. Hence, it is important to define the SNR requirements at the beginning of the design phase and choose the appropriate modulator's order, oversampling ratio or outof-band NTF gain, to provide adequate design margin and account for the SNR loss due to the complex zeros placement.

As can be seen, the proposed method can be applied independently of a particular value of the OSR, though reducing the OSR will inherently degrade the final SNR.

B. CDSM with multiple complex non-conjugated zeros

The implementation of a NTF with multiple complex nonconjugated zeros can be useful in applications, such as the ones presented in [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF], which target the matching of the UMTS and DCS 1800 standards out-of-band spurious emissions using a 5 th order CDSM with two complex integrator stages and optimized poles.

This architecture can also be implemented using the proposed 1 st order CDSM scheme for n = 5, and k = 2, resulting in three real integrators followed by two complex stages (Fig. 7). Furthermore, we note that both additional cross-couplings are introduced from the I and Q quantizers' outputs, which ensures the cancellation of the complex coefficients of the characteristic polynomial without affecting the position of the custom zeros.

Next, we write the STF and the NTF

(17) A complete decorrelation between zeros placement and poles optimization is achieved when (18) [START_REF] Basetas | A Class of 1-Bit Multi-Step Look-Ahead Σ-Δ Modulators[END_REF] where a4 and a5 are the coefficients of the two last stages of a 5 th order DSM.

Again, using the Schreier Toolbox in MATLAB we can obtain the coefficient set {a1, a2, a3, a4, a5, g1} for a 5 th order DSM, with an oversampling ratio OSR = 100 and a peak gain of the NTF equal to 1.6, namely [a1, a2, a3, a4, a5, g1] = (0.0015, 0.018, 0.113, 0.4215, 0.93, 0.01). In order to compare the design methodology and architecture with [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF], we will illustrate the functionality of the proposed higher order CDSM scheme with multiple custom complex zeros (5 th order), considering the same application, i.e. UMTS and DCS 1800 standard coexistence.

( ) ( )

z den z STF p 5 5 1 = ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) z den g z z z NTF p 5 1 2 5 1 1 2 2 1 1 jc r z jc r z - - × - - × + - × - = ( ) ( ) ( ) [ ] ( ) ( ) ( )+ + - × - × + + - × + - =
In [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF], for the UMTS case, the two complex non-conjugated zeros are placed in the DCS 1800 TX band at fc -0.03, and in the UMTS RX band at fc + 0.05, whereas for the DCS 1800 case, the first zero is placed in the DCS RX band at fc + 0.03, and the second in the UMTS RX band at fc + 0.06, respectively. Furthermore, in both cases there are three zeros (one real and two complex-conjugated) which are placed in the signal band, at the center frequency (fc) and at fc ± 0.01.

By applying (6), we can obtain the complex numbers corresponding to these frequencies, namely in the UMTS case [z1, z2, z3, z4, z5]UMTS = (1, 1+0.063j, 1-0.063j, 0.98-0.18j, 0.95+0.31j), and in the DCS 1800 case [z1, z2, z3, z4, z5]DCS = (1, 1+0.063j, 1-0.063j, 0.98+0.18j, 0.93+0.37j). The complex nonconjugated zero pairs are [r, c]UMTS1 = (0.98, 0.18), [r, c]UMTS2 = (0.95, -0.31), [r, c]DCS1 = (0.98, -0.18), [r, c]DCS2 = (0.93, -0.37). Based on these values we can obtain the NTF and the pole-zero plots for the UMTS and DCS cases (Fig. 8), which are very similar with the results presented in [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF].

We remark that the design of the proposed scheme is considerably easier to perform compared to [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF], while needing only the coefficient set of a DSM (obtained automatically using existing tools), and the custom zeros placement (obtained from the specifications of the out-of-band spurious emissions).

C. General CDSM design method

It was previously shown how an n th order CDSM can be built out of (n-k) real stages followed by k complex stages, where k ≥ 1. The design of the proposed CDSM can be generally reduced to the following steps (Fig. 9): i) define the SNR requirements for the desired signal bandwidths and determine the number of real stages (n-k), ii) identify the frequency bands with stringent noise requirements to obtain the number of complex stages (k) and the position of the custom complex non-conjugated zeros ([r, c] coefficient pairs), and iii) obtain the initial values of coefficients for an n th order DSM with existing design tools. A simple simulation can then be performed on the chosen CDSM to verify that the SNR requirements are met. As described previously, there is a trade-off between the inband SNR and the position of the notches relative to the center frequency. If the requirements are not fulfilled, then an additional margin is taken in the initial design phase and a new set of coefficients is generated and tested. This process requires in most application cases very few iterative steps.

Finally, we may state that the proposed method can in principle be applied to both digital (transmitter) and analog (receiver) DSM applications. Limitations remain those specific to the analog or digital domain. In the digital domain, the coefficients are subject to quantization, whereas in the analog domain the coefficients are impacted by mismatch. Mismatch between in-phase and quadrature paths can in particular be of concern in the analog implementation of complex DSMs (as shown in [START_REF] Marttila | Frequency-Agile Multiband Quadrature Sigma-Delta Modulator for Cognitive Radio: Analysis, Design and Digital Post-Processing[END_REF]).

IV. APPLICATION

This section details one application example in which the proposed method is used to design a 4 th order CDSM as part of a highly-integrated WLAN digital transmitter chain, building upon delta-sigma modulation and efficient switching PA.

The block diagram of a DSM-based transmitter is shown in Fig. 10a, as introduced in [START_REF] Frappé | An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators[END_REF]. This architecture is based on i) two single-bit DSMs working synchronously at 2*fc, ii) a digital to RF mixing (D-RF) stage which ideally interleaves the I and Q paths at 4*fc, and iii) a linear and highly efficient switchingmode power amplifier (PA). The digital implementation of the signal path up to the final PA eliminates potential I-Q mismatch and performance degradation due to this mismatch.

At the digital-to-RF mixer inputs, I and Q 1-bit samples are simultaneously available during a period 1/(2*fc) as illustrated in Fig. 11a. The interleaving operation results in the sequence composed of I(sn) and Q(sn), which translates to I(si) and Q(si) (sn is the sampling instant at 2*fc and si at 4*fc).

However, the samples required for the RF stream RFout at 4*fc are I(si) and Q(si + 1) in order to achieve a correct quadrature operation. Therefore, an interpolator stage (INT) is introduced to derive the missing quadrature sample Q(si + 1), which is equivalent to Q(sn + 1/2), where 1/2 represents the ratio between 2*fc and 4*fc (Fig. 11b).

A CDSM can be introduced in this architecture by crosscoupling the inner stages of quadrature DSMs (Fig. 10b), in order to place custom complex zeros and be able to target multistandard coexistence with nearby receivers.

Following the proposed CDSM design method, the first step is to define the specific SNR requirements for the targeted application, which determine the order of the CDSM. For instance, [START_REF] Marin | Considerations for High-Speed Configurable-bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI[END_REF] describes the design of a 3 rd order DSM targeting signal bandwidths from 20 MHz up to 160 MHz with an SNR larger than 67 dB.

Hence, we use three real stages followed by a complex stage to obtain a 4 th order CDSM (Fig. 12) with competitive output SNR performances.

The structure is very similar to the one reported in Fig. 4, except for an additional delay of 1/(2*fc), introduced in the Qpaths from wQ and yQ to uI, due to the synchronous operation of the I and Q paths of the CDSM. As explained earlier in the section, for the correct interleaving operation, the CDSM is working at half the final sampling frequency (2*fc), thus producing only half the samples on each path.

Adding this delay is mandatory to process the correct I and Q samples when performing the cross-coupling of the quadrature paths.

Fig. 1 .

 1 Fig. 1. Standard 1 st order DSMs in quadrature (a); 1 st order CDSM (b)

Fig. 2 .

 2 Fig. 2. Proposed 1 st order CDSM

Fig. 4 .

 4 Fig.4. 4 th order CDSM: three real integrators (1); proposed complex stage[START_REF] Wang | A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter[END_REF]

  Transactions on Circuits and Systems I: Regular Papers (ISSN : 1549-8328) 01/2018 DOI : 10.1109/TCSI.2017.2711035

Fig. 5 .

 5 Fig. 5. 4 th order DSM: three real integrators (1); standard real stage (2)

  for final publication in IEEE Transactions on Circuits and Systems I: Regular Papers (ISSN : 1549-8328) 01/2018 DOI : 10.1109/TCSI.2017.2711035

Fig. 7 .

 7 Fig. 7. Proposed 5 th order CDSM with two complex integrator stages

Fig. 9 .

 9 Fig. 9. Activity diagram of the proposed CDSM design method

Fig. 10 .

 10 Fig. 10. Digital transmitter: (a) DSM-based [18]; (b) cross-coupled DSMs

Manuscript sent 08/02/2017. This work was supported in part by the Nano 2017 program in the frame of the ST-IEMN common lab, by STMicroelectronics, the Nord-Pas-de-Calais Region and the Research Council of the Catholic University of Lille.

This would not be the case if the DSM operated at 4*fc, yet this would imply higher power consumption and additional timing constraints as a result of the high frequency clock.

The corresponding STF and NTF of the 4 th order CDSM can be expressed as follows, for c = cx [START_REF] Marin | Delta-Sigma Based Digital Transmitters with Low-Complexity Embedded-FIR Digital to RF Mixing[END_REF] (21) (22) where a half period delay (z -0.5 ) is introduced in the equation due to the additional delay elements 1/(2*fc) in the Q paths, relative to the sampling period of 1/(4*fc).

Consequently, using the proposed CDSM scheme, the multistandard coexistence can be made configurable and depends on only two coefficients, namely r and c, whereas the main architecture based on the coefficient set {a1, a2, a3, a4, g1} is the same as in the case of a real modulator. This feature is verified through simulations, for an input signal bandwidth BW = 20 MHz and fc = 2.412 GHz (Fig. 13). Moreover, all the coefficients are quantized to sums of powers of two in order to simplify the digital implementation.

For the same general CDSM architecture, the complex zero is placed at fGPS ≈ 1.6 GHz (close to GPS and GLONASS bands) for [rGPS, cGPS] = (2 -5 , 2 -1 + 2 -2 + 2 -3 + 2 -4 ) in the first example, while it is placed at f3G ≈ 2.17 GHz (close to 3G communication bands) for [r3G, c3G] = (2 -1 + 2 -2 + 2 -4 , 2 -2 + 2 -4 ) in the second example, as highlighted in Fig. 13. We further observe that r has only a minor influence on the NTF. Hence, the dynamic coefficient ax (used in Fig. 4 to compensate the real part of the complex zero in specific coexistence scenarios) can be replaced by the static coefficient a4 of the 4 th order DSM (a4 is now used in Fig. 12 instead of ax from Fig. 4).

When compared to the output of a 4 th order DSM, the out-ofband noise integrated in the critical frequency bands (fGPS and f3G) is considerably reduced in the CDSM case, with ~20 dB at f3G and ~30 dB at fGPS. Moreover, we can notice that for the CDSM with [rGPS, cGPS] (CDSM(GPS) in Fig. 13) there is an additional zero at fadd = 2*fc, which results from the second solution of the polynomial (z -(r -jc . z -0.5 )) in (21), namely zadd = -0.93 (modulus almost equal to 1).

At the same time, as it was identified in a previous section, Fig. 13 reveals that the complex zeros placement leads to a relative degradation of the SNR which is proportional to the distance between the position of the zero and fc. This degradation can be partially compensated through an adequate choice of the SNR design margin and modulator's parameters. A complementary solution may be found in [START_REF] Basetas | A Class of 1-Bit Multi-Step Look-Ahead Σ-Δ Modulators[END_REF], which proposes a 1-bit multi-step look-ahead architecture to improve the input dynamic range and SNR compared to error-feedback structures, while maintaining a low complexity overhead for real-time operation.

Furthermore, it can be seen that the bandwidth of the CDSM (zoom signal band in Fig. 13) can be configured (g1 coefficient in Fig. 12) to address (digitally) the three non-overlapping 20 MHz WLAN channels in the 2.4 GHz band, or to increase the signal bandwidth up to 40 MHz, thus meeting the near-band transmit mask in a worst-case scenario (GPS). Finally, in order to attenuate the noise outside the CDSM bandwidth, solutions such as analog filtering, or FIR filtering [START_REF] Gebreyohannes | A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards[END_REF] can be employed.

V. FINE/COARSE CONFIGURABLE CDSM

It was shown, that using the [r, c] parameters we are able to configure the complex zeros placement, whereas the frequency step (granularity) depends on the number of coefficient pairs and quantization. For example, in order to achieve configurability in the frequency domain [f3G, fGPS] (around 600 MHz range), we need to predefine as many

However, this would add large constraints to a real digital implementation, due to additional paths and increased number of operations. In this case, the maximum operating frequency of the modulator may be reduced, thus limiting its performances (OSR, SNR, noise shaping) and application (limited fc for the communication standard).

Consequently, we propose to minimize the number of [r, c] coefficient pairs, and combine this with a coarse tuning mechanism for band selection using additional delays in the cross-coupling paths of the CDSM (Fig. 14), similar to the principle of asymmetric embedded FIR-filtering in [START_REF] Marin | Delta-Sigma Based Digital Transmitters with Low-Complexity Embedded-FIR Digital to RF Mixing[END_REF].

A. CDSM with delayed cross-coupling paths

The noise shaping of the proposed 4 th order CDSM is very similar to the asymmetric unbalanced embedded-FIR filtering presented in [START_REF] Marin | Delta-Sigma Based Digital Transmitters with Low-Complexity Embedded-FIR Digital to RF Mixing[END_REF], which introduces additional delays in the cross-coupled I and Q paths between the DSM and mixer stages of a digital transmitter chain similar to [START_REF] Frappé | An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators[END_REF].

Furthermore, [START_REF] Marin | Delta-Sigma Based Digital Transmitters with Low-Complexity Embedded-FIR Digital to RF Mixing[END_REF] employs a different number of delays in the cross-coupling paths to compensate for the INT stage, namely d-1 for the I (z -d+1 ) and d for the Q (z -d ) paths ( [START_REF] Marin | Delta-Sigma Based Digital Transmitters with Low-Complexity Embedded-FIR Digital to RF Mixing[END_REF] uses the notation k instead of d). The main advantage of the architecture in [START_REF] Marin | Delta-Sigma Based Digital Transmitters with Low-Complexity Embedded-FIR Digital to RF Mixing[END_REF] is the introduction of configurable notches at specific frequencies (based on d) using simple digital logic, which can relax the filtering constraints of the system.

Hence, we propose to use the same principle of delayed cross-couplings between the inner stages of the CDSM (Fig. 14), to obtain NTF notches at different frequencies.

Simulation results for an input signal bandwidth BW = 20 MHz centered at fc = 2.412 GHz, [rGPS, cGPS], and different values of d (d equal 2, 3, and 4) show that the position of the complex zero changes with d (not linear) without affecting the noise shaping around the transmit band (Fig. 15), thus providing an additional mechanism for band selection in the zeros placement.

Moreover, increasing the number of delays in the crosscoupling paths has the advantage of introducing additional notches out-of-band which relax even more the succeeding filtering stage needed to meet the overall noise requirements.

B. Fine/Coarse tuning mechanism

Let us combine the two aforementioned effects, in order to obtain a fine/coarse tuning mechanism for multi-standard coexistence, whereas the r and c coefficients are used for fine adjustment, and d is used to determine the coarse frequency band selection. In this case, using the same [r, c] coefficient pairs, we can cover several frequency domains for different values of d. Let us assume N [r, c] coefficient pairs which correspond to N complex zeros which are placed in the frequency domain [fcfc/3, fc -fc/5] for d = 2. If we increase d, for example setting d = 4, we will retrieve the N complex zeros at locations which are proportional to the new frequency domain, [fc -fc/7, fc -fc/9]. This feature is highlighted in Fig. 16,for d

), whereas BW = 20 MHz and fc = 2.412 GHz.

Thus, the proposed fine/coarse tuning enables multi-standard coexistence in a digital CDSM-based TX chain over the frequency domain [fc -fc/3, fc], thanks to a reduced number of coefficient pairs combined with configurable band selection for improved performances and relaxed constraints.

In addition, this mechanism can also be applied for the symmetric frequency domain [fc, fc + fc/3] using only two digital inverter cells, namely for inverting the sign of the Q samples at the input of the CDSM, and again in the digital to RF mixing stage (shown in Fig. 10).

In conclusion, the complete mechanism ensures zeros placement configurability over an extended frequency domain [fc -fc/3, fc + fc/3] and greatly simplifies the final architecture implementation, i.e. less coefficient pairs, digital delays for band selection and inverter cells for symmetry.

VI. CONCLUSIONS

This paper describes an improved scheme for the 1 st order Complex Delta-Sigma Modulator which can be used in the design of higher order CDSMs with one or more custom complex non-conjugated zeros, using standard design and optimization tools specific to DSM.

Additional feedback paths allow the decorrelation between the placement of a complex zero and the characteristic polynomial. Hence, compared to other known methods [START_REF] Nsiala Nzéza | Reconfigurable Complex Digital Delta-Sigma Modulator Synthesis for Digital Wireless Transmitters[END_REF] [11], the proposed CDSM can ease multi-standard coexistence using a generic well-known architecture and may achieve a noise level reduction at specific frequency bands of 20-30 dB.

Furthermore, we studied a complementary mechanism for zeros placement, by introducing additional delays in the crosscoupling paths of the CDSM block. Consequently, we obtain a fine/coarse control over the coexistence bandwidth, which simplifies the implementation, thanks to the reduced number of [r, c] coefficient pairs. Finally, the proposed configurable CDSM presents increased flexibility and a "true" single-bit output unlike the unbalanced embedded-FIR scheme in [START_REF] Marin | Delta-Sigma Based Digital Transmitters with Low-Complexity Embedded-FIR Digital to RF Mixing[END_REF], thus allowing low overhead dynamic adjustment of the complex zeros at system level to protect the relevant receive channels in the coexistence scenario.

Răzvan-Cristian


Razvan-Cristian Marin

Antoine Frappé

Bruno Stefanelli

Philippe Cathelin

Andreia Cathelin

Andreas Kaiser

R.-C Marin

Digital RF transmitter with single-bit ∆Σ M-driven switched-capacitor RF DAC and embedded band filter in 28-nm FD-SOI

Keywords: transmitter, body-bias, Delta-Sigma modulation (ΔΣM), finite impulse response filter

à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

mobile devices developed to support emerging Internet of Things (IoT) applications [START_REF] Song | Digitally Intensive Transmitter Employing RF Pulse Width Modulation for IoT Applications[END_REF]. Recent research concentrates on the complete System-on-Chip (SoC) implementation of the transmit chain, as well as pushing the digital signal processing domain boundary closer to the antenna.

The main challenges specific to digital transmitter design are to reduce quantization noise below spectrum mask requirements, to achieve power consumption levels similar or below analog/RF transmitters and to reach carrier frequencies in the GHz range. Proposed approaches in literature range from high-resolution high-speed digital-to-analog converters (DAC) to single-bit Delta-Sigma modulated digital RF signals at multi-GHz clock rates.

A. Speed vs. resolution trade-off in digital transmitters

Various trade-offs between resolution and clock rates have been used in digital to RF conversion (DRFC) approaches, embedding the DAC into the baseband to RF mixer. Examples are the 6-bit switched-capacitor (SC) I/Q sharing DRFC structure in [START_REF] Jin | Efficient digital quadrature transmitter based on IQ cell sharing[END_REF] or the 13-bit RF power DAC in [START_REF] Wang | A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter[END_REF], which present significant conceptual differences, since [START_REF] Jin | Efficient digital quadrature transmitter based on IQ cell sharing[END_REF] optimizes power efficiency using a low-resolution scheme, and [START_REF] Wang | A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter[END_REF] targets improved noise performance thanks to additional resolution and digital pre-distortion. In [START_REF] Roverato | All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise[END_REF], a 10-bit currentsteering DAC is demonstrated and digital Delta-Sigma Modulators (ΔΣM) with mismatch shaping (MS) are used to reduce OOB emissions at a programmable duplex distance. Similarly, a 12-bit resistive quadrature DAC (RQDAC) is presented in [START_REF] Paro Filho | A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise[END_REF] with incremental-charge based operation to reduce the power consumption required to drive the RF load.

Low-resolution ΔΣM-based architectures [START_REF] Hezar | A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications[END_REF], [START_REF] Frappé | An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators[END_REF] have the potential to achieve excellent in-band performance and be efficiently integrated in CMOS technologies. On the one hand, the architecture in [START_REF] Hezar | A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications[END_REF] introduces a 4-bit ΔΣM driving a 1-bit pulse width modulator (PWM), which enables the use of an efficient class-G switched-capacitor PA, similar to [START_REF] Yoo | A Class-G Switched-Capacitor RF Power Amplifier[END_REF]. On the other hand, in [START_REF] Frappé | An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators[END_REF] an all-digital RF signal generator is designed based on single-bit low-pass ΔΣMs and a simplified digital mixer, thus opening the way towards the implementation of an all-digital transmitter scheme based on switching-mode (SM) power amplifier (PA).

Digital RF Transmitter

B. Known filtering techniques

One solution to reduce out-of-band quantization noise is to introduce highly selective analog filtering. Bulk acoustic wave (BAW) filters have been developed for mobile RF-front-ends with significantly higher quality factors (Q up to 1000) than on-chip LC tanks, better temperature stability and power handling capability compared to surface acoustic wave (SAW) devices, and the potential to be fabricated in above-IC approach [START_REF] Dubois | Monolithic Above-IC Resonator Technology for Integrated Architectures in Mobile and Wireless Communication[END_REF]. However, manufacturing cost and yield issues have so far limited above-IC integration at an industrial scale.

Semi-digital solutions based on finite impulse response (FIR) filters represent another attractive approach, thanks to the possibility of digitally adjusting the transfer function. In [START_REF] Pozsgay | A Fully Digital 65nm CMOS Transmitter for the 2.4-to-2.7GHz WiFi/WiMAX Bands using 5.4GHz ΔΣ RF DACs[END_REF], a parallel DRFC structure is introduced to create a 2-tap FIR filter with two notches at ±500 MHz from the 2.45 GHz center frequency. A 5-channel power combiner based on transmission lines was proposed in [START_REF] Flament | A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner[END_REF], allowing a digitally reconfigurable RF FIR filter with binary coefficients. A similar approach was used in [START_REF] Bhat | A >1W 2.2GHz Switched-Capacitor Digital Power Amplifier with Wideband Mixed-Domain Multi-Tap FIR Filtering of OOB Noise Floor[END_REF], integrating a power combiner using on-chip transformers in a 3-tap FIR configuration. The measured noise floor is -149 dBc/Hz in a selected 20 MHz band, whereas the 3.4 Ω output resistance enables 30 dBm peak output power. In addition, a 6-tap FIR-DAC is introduced in [START_REF] Taleie | A Bandpass ΔΣ RF-DAC with Embedded FIR Reconstruction Filter[END_REF] based on 1-bit band-pass (BPF) ΔΣ-DAC and a current-steering FIR reconstruction filter with programmable zero location based on 6-tap digital delay line. These FIR-based quantization noise filtering techniques propose to create notches in the OOB noise spectrum using few taps for the filtering function. To provide a global out-ofband attenuation over the complete spectrum, [START_REF] Gebreyohannes | A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards[END_REF] suggested a 63-tap semi-digital FIR-DAC in a differential current-steering architecture targeting 60 dB stopband attenuation for 802.11 ac/ad signals.

In this paper, a low-power 109-tap RF FIR-DAC taking advantage of a switched-capacitor structure designed for single-bit ΔΣ RF signals is presented. Section II describes the theory of the digital transmit chain and the study of the FIR-DAC non-idealities model. Next, Section III details the 28nm FD-SOI CMOS circuit implementation, emphasizing the integration of the FIR-DAC under a signal pad. The proposed concept is validated with measurement results in Section IV, and Section V concludes this paper.

II. THEORY OF OPERATION

The proposed all-digital RF transmitter architecture is shown in Fig. 1. It comprises two quadrature 1-bit 3 rd order ΔΣMs, working synchronously at twice the carrier frequency (fc), a digital mixer (DRFM) producing a digital RF signal at the final sample rate of 4*fc, a pseudo-differential RF DAC with embedded FIR filtering, and an RLC band-pass filter.

The digital mixing process is simplified by setting the sampling frequency to fs = 4*fc [START_REF] Frappé | An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators[END_REF], allowing the cosine and sine versions of the LO signal period to be expressed as simple sequences, namely {1; 0; -1; 0} and {0; 1; 0; -1}. In this case, one out of two values in the I and Q paths can be dropped. Thus, the mixer is reduced to time-interleaving the appropriate I and Q path samples with positive (IP/QP) or negative (IN/QN) polarity. The resulting mixer output over one LO period can be represented by the sequence {IP; QP; IN; QN} at the sampling frequency 4*fc. Hence, by generating only the useful I and Q samples, the effective sampling rate of the ΔΣM stage can be reduced to 2*fc. Additionally, time interleaving of the ΔΣMs enables multi-GHz carrier frequency operation, as shown in [START_REF] Marin | Considerations for high-speed configurable-bandwidth time-interleaved digital deltasigma modulators and synthesis in 28 nm UTBB FDSOI[END_REF].

Furthermore, the constant-level switching at the output of the ΔΣM allows the implementation of N 1-bit switchedcapacitor DACs, which are recombined to form an FIR filter. The FIR filter function is embedded into the DAC by introducing delays between N successive driver/capacitor sections, which correspond to N delayed versions of the single-bit ΔΣM output (Fig. 2). Relative sizes of capacitors are used to implement arbitrary coefficients in the FIR filter, which has linear phase, thanks to the symmetrical capacitor ratios, i.e. Ci = CN-i+1, where i = 1…N/2.

Combinations of elementary DAC cells can be used to create programmable coefficients of an N-tap digital FIR filter, embedded in the DAC stage. With respect to its current-source counterpart, the SC scheme has the advantages that it does not require stringent transistor matching and has constant ©IEEE Version submitted for final publication in IEEE Transactions on Microwave Theory and Techniques (ISSN : 0018-9480) 03-2019. DOI: 10.1109/TMTT.2019.2897929 impedance seen from the output. Furthermore, in a switchedcapacitor DAC, signals can be combined on an inductor in series with the load [START_REF] Yoo | A Switched-Capacitor RF Power Amplifier[END_REF]. The total DAC capacitance and the inductor form the LC matching network to the load resistance, where L and C are tuned to resonate at the carrier frequency. The band-pass filter created around fc contributes to quantization noise filtering, thus being highly useful in relaxing the design constraints of the FIR filter.

A. FIR filter design optimization

In a conventional DAC, the number of bits is set according to the target minimum noise floor, even though the OOB noise requirements are not uniform over the entire spectrum. To avoid overdesign, a configurable FIR filter is used to i) set a lower overall target noise rejection of 70 dBc, and ii) adjust the zeros placement to target 80 dBc noise rejection only at specific frequency bands for multi-standard coexistence. We note that 80 dBc corresponds approximately to the thermal noise floor, when considering a 20 MHz channel bandwidth, a succeeding power amplifier with an average output power of 20 dBm, and 40 dB isolation from antenna to antenna [START_REF] Ye | Design Considerations for a Direct Digitally Modulated WLAN Transmitter IEEE Transactions on Microwave Theory and Techniques[END_REF].

The FIR filter was designed in MATLAB using a window method, i.e. convolution in frequency domain between the ideal impulse response filter and a window function to derive a finite impulse response filter. Different types of integration windows (same conditions on filter length and coefficient quantization) were evaluated, in order to obtain a trade-off between near-band and far-out-of-band noise attenuation. The ΔΣM is designed according to [START_REF] Marin | Considerations for high-speed configurable-bandwidth time-interleaved digital deltasigma modulators and synthesis in 28 nm UTBB FDSOI[END_REF] as a single-bit 3 rd order CIFB (Cascade-of-integrators feedback form) with quantized coefficients and OSR (oversampling ratio) of 100, resulting in a peak SNR (signal to noise ratio) of ~90 dB, and requires extensive filtering of the quantization noise, as shown in Fig. 3(a). The required performance can be achieved by an FIR filter using a Hann window [START_REF] Oppenheim | Discrete-Time Signal Processing[END_REF] with 109 symmetric coefficients quantized to 8 bits. The total number of unitary filter taps, i.e. DAC cells, is estimated by summing the 109 quantized coefficients (lowest is 1, largest is 256), which adds up to ~14500. Hence, building such a filter is not physically feasible, as it would produce a tremendous overhead in wiring, which will negatively impact electrical performance.

The first optimization step is to co-design the FIR filter together with the output RLC band-pass filter (Fig. 3(b)). By relaxing the filtering constraints, the resolution of the FIR coefficients can be reduced to 5 bits (largest is 32), which lowers complexity by 8 times (1800 total unitary cells), and facilitates integration in advanced CMOS technology nodes.

B. FIR-DAC architecture optimization

The second optimization step addresses the optimization of the switched-capacitor scheme, by reducing switching redundancy and power consumption [START_REF] Song | Digitally Intensive Transmitter Employing RF Pulse Width Modulation for IoT Applications[END_REF] where the factor αSC represents the contribution of the singlebit ΔΣM (driving N delayed paths of the FIR-DAC) switching activity to the average dissipated energy, CT is the total output node capacitance, VDD the supply voltage, and fs the sampling frequency, respectively. (2) Now, both symmetric coefficients and corresponding driving signals are equivalent. As a result, the symmetric sides become redundant and one side of the filter is simply removed (Fig. 4(b)). Though it is a classic technique in digital FIR filter design, it is the first time it has been applied to FIR-DAC design, being driven by the need to implement a very large number of FIR coefficients.

Hence, 109-tap FIR filter performance can be achieved using only half the filter coefficients, namely 55 out of 109, whereas the coefficients C1..54 keep their initial value and the middle non-symmetric coefficient C55 is halved. In practice, this translates to the digital signal processing of 109 consecutive samples, to obtain 55 signal streams RF1..55 which drive 55 DAC cell groups. With respect to the straight-forward approach, the FIR complexity is reduced by 16 times in terms of total number of cells, and 2 times in terms of number of signal streams for similar OOB noise performance. Thus, for a (the total output node capacitance is halved), which also changes the RLC quality factor. Moreover, the three remaining possible combinations of positive and negative driving signals, RFP/RFN = {1/0; 0/0; 0/1}, result in a pseudo-differential configuration, which might cause increased even-order harmonics due to non-ideal differential to single-ended conversion. Finally, the key advantage of the proposed architecture is that it combines the increased output power of the differential architecture with the performance of the single-ended architecture in terms of switching power, area, number of unitary cells and input signal drivers.

s DD T SC SC f V C P × × × = 2 a ï î ï í ì = = = = = = + - + - + - + - m m k N k k N k m m k N k k N k in RFN in NOR in RFN RFN in RFP in AND in RFP RFP

C. FIR-DAC switching model

A comprehensive study of the switching model for switched-capacitor PA schemes is shown in [START_REF] Yoo | A Switched-Capacitor RF Power Amplifier[END_REF], where the unitary PA cells are activated based on the input signal amplitude during the first half-period, whereas in the second half, all the cells are switched-off, so that the switching power does not depend on the cell switching transitions. However, in the proposed architecture (Fig. 4), the unitary cells are de-/activated during a complete time period, based on the control signals derived in the FIR filter, meaning that the switching scheme model has to take into consideration also the previous state (on/off) of the cells (transitions). To evaluate the average switching power, the simplified switching model in Fig. 5 is considered at the switching instants t0 and t1. The capacitances are denoted Cij, where the first index i corresponds to the connection of the bottom plate at time t0, and the second index j corresponds to time t1 ("1" denotes VDD and "0" denotes GND). The output voltages V0 and V1 at time instants t0 and t1 The average switching power PSC can be expressed as the total energy Ex spent during NP periods divided by the number of periods NP and the sampling period Ts = 1/(4*fc) (4)

Combining ( 1) and (4), the average switching activity αSC is computed with the voltage drop difference on Cij [START_REF] Paro Filho | A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise[END_REF] where all the capacitances Cij are normalized to the total capacitance CT, namely αij = Cij / CT.

Hence, considering (5), the power consumption is reduced This is highlighted in Fig. 6, in addition to the validation of the switching combining (1) and ( 5) using behavioral Spectre RF simulations. We may remark that the switching activity is almost independent of the input signal amplitude (before DSM). Furthermore, generating only 55 out of 109 signal streams leads to a significant reduction of complexity and power consumption of the FIR-DAC driving circuit.

ï ï î ï ï í ì × + = × + = DD T DD T V C C C V V C C C V 01 11 1 10 11 0 å = × × = P N i i x s P SC E T N P 1 , 1 ( ) ( ) P N i i i i i i i SC N P å = + × + + × =

D. FIR-DAC non-idealities model

In this section, a model for the unitary DAC cell nonidealities is proposed and the impact of circuit integration on the FIR filter function is evaluated. First, the switch driving signals RFP/RFN are subject to non-idealities due to rise/fall time (tr/tf), propagation delays (tPLH/tPHL) and jitter (tj,var). We assume that all parameters are specific to each path and normally distributed, with Δtr, Δtf, ΔtPLH, and ΔtPHL constant throughout simulation, and variable cycle-to-cycle tj,var. System-level simulations reveal that jitter causes the main noise performance degradation, rendering part of the FIR filter zeros indistinct compared to the ideal case. Still, when considering the combined switching non-idealities (Fig. 7), we remark that the noise level near the signal-band is lower than in the case of jitter only, which may be accounted for by a slight cancellation effect between the variable propagation delay and jitter which lowers overall deviation.

A different source of non-ideality arises from the matching errors of the unitary capacitances, which directly impacts the FIR filter coefficients and transfer function (Fig. 8). It is seen that for large deviations, the proposed FIR-DAC can achieve a noise attenuation performance similar to a conventional 11-bit RF DAC at specific critical bands. Also, the proposed scheme does not create additional signal images, like in an RF DAC [START_REF] Alavi | A Wideband 2times 13-bit All-Digital I/Q RF-DAC[END_REF], where a trade-off is made to reduce baseband sampling Fig. 9. Output spectrum: effect of voltage supply variation with respect to the tolerated supply resistance kr.

frequency and power consumption. The 11-bit RF DAC is modelled as in [START_REF] Alavi | A Wideband 2times 13-bit All-Digital I/Q RF-DAC[END_REF], with 1/3 of the total number of bits binary and 2/3 thermometer coded, respectively.

Moreover, the variation of the voltage supply has a significant impact on both switching and coefficient nonidealities (Fig. 9), because it is mainly dependent on the cycleto-cycle switching current ISC and it may become critical in high-frequency switching schemes. The supply variation is defined here as ΔVDD = kr . ISC, where kr is used to derive the tolerated supply resistance for the filter transfer function. We note that an increase of kr determines a gradual degradation of the near-band noise performance.

Finally, the signal-band performance of the proposed FIR-DAC is evaluated in the presence of non-idealities, showing very good EVM (error vector magnitude) performance, when applying static correction of the I/Q constellation similar to [START_REF] Bhat | Design Tradeoffs and Predistorion of Digital Cartesian RF-Power-DAC Transmitters[END_REF]. In the case of an orthogonal frequency-division multiplexing (OFDM) 20 MHz 16QAM (quadrature amplitude modulation) signal, the resulting rms EVM of the transmit chain is close to 1.5%.

III. CIRCUIT DESCRIPTION

A top-level schematic of the proposed digital RF transmit chain is presented in Fig. 10. The digital inputs DSI and DSQ are single-bit ΔΣ modulated signals generated externally, and a serial-to-parallel (S/P) converter was inserted to reduce digital core operating frequency, leading to a 4-phase system configuration on both I and Q paths at a sample rate fc/2. The FIR-DAC SIGGEN blocks generate the baseband level delayed control signal groups, in the I and Q paths, for the 55 switching blocks of the FIR-DAC. The complete design of the digital blocks was done based on VHDL/Verilog descriptions with digital synthesis tools, although some custom design was needed at the interface with the FIR-DAC. The simulated power consumption of the digital core is estimated at ~16 mW, when operating at a center frequency fc = 0.9 GHz. Moreover, integrating the two ΔΣM would add ~6 mW power consumption, as described in [START_REF] Marin | Considerations for high-speed configurable-bandwidth time-interleaved digital deltasigma modulators and synthesis in 28 nm UTBB FDSOI[END_REF].

B. FIR-DAC circuit design

The unitary cell of the FIR-DAC comprises a CMOS inverter and a metal-oxide-metal (MOM) capacitor, which were co-designed to enable a performance optimization in terms of power consumption and area, achieving ~1.4 μW per GHz switching frequency for an area of 1.6x1.8 μm 2 . The integration of the complete FIR-DAC under flip-chip (FC) RF pads is achieved through a specific multi-layer structure in a 10 metal (Me) process (3D view in Fig. 12).

The CMOS inverter is built up to Me1, inter-/intra-cell connections on Me2 to Me4, and the MOM capacitor on Me4 up to Me8 (CMOM ≈ 1.7 fF), whereas the top-plates of the capacitors are connected together directly to the pad on Me10 and Alucap. Furthermore, in order to reduce layoutinduced parasitic elements on the output, unit cells are grouped by 4, which presents the following advantages:

1) The ring provides isolation between the cell groups;

2) There is no inner-group ring, thus reducing the parasitic capacitance seen at the output terminal;

3) The free space can be used for supply decoupling. The FIR-DAC has a total of 1152 unitary cells, divided into a 32 by 36 matrix to fit under the 58x58 μm 2 flip-chip pad (Fig. 13). Post-layout simulations of the FIR-DAC and the switching cells indicate a power consumption of 4 mW for the inverters and 2.5 mW for the capacitor banks, when operating in the 900 MHz band.

IV. EXPERIMENTAL RESULTS

The circuit is fabricated in 28nm FD-SOI CMOS from STMicroelectronics and integrates the FIR-DAC SIGGEN, the DRFM and the FIR-DAC, with a total active area of 0.047 mm 2 , including RF output pads. The IC is mounted on a 5x5 mm 2 dedicated flip-chip ball grid array (BGA), which embeds RF inductors to create the LC matching network, as well as additional decoupling capacitors. The device is connected to a dedicated printed circuit board (PCB), with RF differential output traces designed as adapted transmission lines at the targeted center frequency to complete the RLC filter. The chip micrograph and dedicated flip-chip BGA package are shown in Fig. 14.

The digital data inputs are generated externally in MATLAB, including the S/P conversion process, and streamed in using synchronized Tektronix AWG7000A arbitrary waveform generators at a clock rate fdata = fc/2, whereas the main clock frequency is 2*fc. At the output, the differential to single-ended conversion is provided by an ©IEEE Version submitted for final publication in IEEE Transactions on Microwave Theory and Techniques (ISSN : 0018-9480) 03-2019. DOI: 10.1109/TMTT.2019.2897929 Agilent E2695A RF probe, and the RF output is measured on 50Ω using a Keysight N9030A PXA signal analyzer.

In Fig. 15, the measured output spectrum of a 3 MHz baseband (BB) single-tone at 6 dB back-off from the peak output power of 4.6 dBm emphasizes the out-of-band attenuation provided by the combined 109-tap FIR and RLC filtering. The in-band (100 MHz band) SNR is ~61 dB, which corresponds to 10 effective number of bits (ENOB). The carrier frequency is 900 MHz and the voltage supply is set to 1 V for an overall power consumption of 34.5 mW, out of which the RF output stage, differential RF FIR-DAC, consumes 8.3 mW and the digital blocks, FIR-DAC SIGGEN and DRFM, consume 26.2 mW. Measurements also confirm the results in Fig. 6 regarding the relatively constant switching power consumption in the FIR-DAC, regardless of the signal amplitude.

It was previously described that the 2-step MUX-based digital mixer is highly sensitive to clock duty-cycle errors (~30dB image rejection degradation at ΔDCE = ± 0.1%). Duty-cycle errors can be corrected by tuning the body-bias voltage, which enables a balanced pMOS-nMOS switching operation. Fig. 16 highlights the efficiency of this mechanism in correcting DCE, thus finding an optimal operating point, where image and LO rejections are improved up to ~60 dBc at 6 dB back-off (~52 dBc at peak output power). With respect to Fig. 11, we remark similar LO and image rejection characteristics, from which we could estimate the body-bias compensation range, corresponding to a clock duty-cycle error |ΔDCE| < 0.05%. Furthermore, it is seen that increased even-order harmonics are present in the output spectrum, due to the three-state output of the FIR-DAC, which is less effective for common mode rejection. Moreover, third order counter inter-modulation (CIM3) products at -49 dBc are present in the adjacent channel (Fig. 15), which is subject to stringent constraints in terms of spurious emissions. In [START_REF] Chen | An LTE SAW-less transmitter using 33% duty-cycle LO signals for harmonic suppression[END_REF] and [START_REF] Bhagavatula | A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS[END_REF], it is shown that CIM3 can be improved by canceling the signal third harmonic at 3*fc-fBB, which intermodulates with the desired signal at fc+fBB, resulting in spurious emissions at fc-3*fBB, due to non-linearity.

The measured spectrum for LTE 10 MHz (LTE10) and 20 MHz (LTE20) transmitted signals with 6 dB peak-to-average power ratio (PAPR) is shown in Fig. 17. The average output power and ACLR for LTE10 are -1.2 dBm and -33/-43 dBc, whereas for LTE20 we obtained -1.5 dBm and -34/-43 dBc, respectively, with an overall consumption of ~38 mW at 1 V supply voltage. Baseband digital predistortion (DPD) could be studied further to improve ACLR, as it is widely used in literature to increase linearity and reduce spectral regrowth and unwanted emissions into adjacent bands [START_REF] Gaber | A 21-dBm I/Q Digital Transmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology[END_REF]. Still, the DPD implementation would add extra cost in surface and power consumption for the dynamic correction feedback loop. Further description and comparison of existing DPD models can be found in [START_REF] Xu | Generalized Two-Box Cascaded Nonlinear Behavioral Model for Radio Frequency Power Amplifiers with Strong Memory Effects[END_REF].

The noise floor measured in a 3 MHz bandwidth is lower than -125 dBm/Hz at 200 MHz offset frequency, when transmitting both single-tone and LTE signals at the center frequency fc = 900 MHz, and showed no dependency on the IEEE Transactions on Microwave Theory and Techniques (ISSN : 0018-9480) 03-2019. DOI: 10.1109/TMTT.2019.2897929 input signal amplitude. In addition, digital replicas appear at fc ± fc/2, due to baseband sampling at fdata = fc/2. The 28nm FD-SOI transmit chain performance is summarized and further compared with digital-intensive architectures in the same technology node (Fig. 18). In [START_REF] Jin | Efficient digital quadrature transmitter based on IQ cell sharing[END_REF], a 6-bit switchedcapacitor quadrature DRFC takes advantage of improved switching efficiency by disabling opposite cells. Next, mismatch shaping (MS) is introduced in [START_REF] Roverato | All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise[END_REF] to minimize DAC static mismatch effects and reduce OOB noise by scrambling the order of conversion cells at each sampling instant. Furthermore, [START_REF] Paro Filho | A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise[END_REF] describes a 12-bit incrementalcharge based scheme to minimize dissipated power, while driving a 50 Ω load at 3.5 dBm peak output power.

The proposed digital transmit chain based on single-bit switched-capacitor RF FIR-DAC is very scalable, and the occupied silicon area can be drastically reduced, thanks to the tolerable mismatch of the unit cells. The total active area is 4 times smaller than the smallest previous design. The LO and image rejections compare favorably thanks to the body-bias-based duty-cycle correction, whereas the measured CIM3 is close to -50dBc. Delivering similar output power levels, the output stage of our system consumes less than [START_REF] Roverato | All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise[END_REF] and [START_REF] Paro Filho | A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise[END_REF], while the power consumption of the digital part is similar to [START_REF] Roverato | All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise[END_REF]. Nevertheless, since the measured ACLR values are lower than in the two other designs, additional digital linearization techniques would be required, and add to the power consumption and area of the system.

Finally, the present FIR-DAC architecture is compatible with the PA design features detailed in [START_REF] Bhat | A >1W 2.2GHz Switched-Capacitor Digital Power Amplifier with Wideband Mixed-Domain Multi-Tap FIR Filtering of OOB Noise Floor[END_REF], such as stacked transistors operating at twice the supply voltage, power combining, and on-chip matching to a very low output resistance ~3 Ω, and could achieve an output power level enabling operation as stand-alone 5G LTE-M compliant power amplifier. With a modest amount of additional circuitry, the Delta-Sigma modulators and FIR transfer function could also be reconfigured for different resolution and bandwidth requirements. As shown in [START_REF] Gebreyohannes | A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards[END_REF] and [START_REF] Marin | Considerations for high-speed configurable-bandwidth time-interleaved digital deltasigma modulators and synthesis in 28 nm UTBB FDSOI[END_REF], up to 160MHz of signal bandwidth is achievable for 802.11 specifications by a DSM associated to a FIR-DAC of similar complexity to the one described in this paper.

V. CONCLUSIONS

The present paper describes the system-level design of an all-digital transmitter based on a hybrid architecture, combining single-bit DAC stages in a 109-tap FIR filter, and the integration of the RF FIR-DAC output stage in 28nm CMOS FD-SOI. The general idea behind this concept is to rely only on basic circuit elements, inverters and capacitors, arranged in a straightforward matrix of unit cells, with only one cell to develop, in addition to digital library cells. Still, maintaining the output power level at low supply voltages requires the use of lower load resistances, which raises additional issues in terms of interfacing the circuit to the antenna.

The single-bit core digital transmitter offers an attractive alternative to both traditional design based on highresolution DAC architectures, and digital-intensive transmitters up to date, by shifting analog processing towards the digital domain, and pushing the digital domain up to the antenna. The true digital nature of the proposed solution provides extensive design space for digital processing enhancement towards flexible software defined radio, making this architecture an ideal candidate for next generation IoT devices.

Fig. 1 .

 1 Fig. 1. Proposed all-digital RF transmitter architecture and conceptual representation of the 1-bit digital input signal spectrum and the analog output signal spectrum of the transmitter.

Fig. 2 .

 2 Fig. 2. Conceptual view of the proposed N-length FIR-DAC.

Fig. 3 .

 3 Fig. 3. Output spectrum: (a), (b) 1-bit ΔΣM; (a) FIR with 8-bit coefficient quantization; (b) FIR with 5-bit coefficient quantization and RLC filter.

©IEEE

  Fig. 4. Differential FIR-DAC: (a) conventional; (b) optimized with reduced switching activity and number of unitary cells.

Fig. 5

 5 Fig. 5. 2-bit SC scheme: switching activity from time instant t0 (a) to t1 (b); On-transistors are depicted in black and off-transistors in grey.

Fig. 6 .

 6 Fig. 6. Switching activity αSC as function of the input signal amplitude; validation of the theoretical switching model by Spectre simulations.

  on Microwave Theory and Techniques (ISSN : 0018-9480) 03-2019. DOI: 10.1109/TMTT.2019.2897929by ~60% in the case of the proposed FIR-DAC (Fig.4(b)), with respect to the conventional scheme (Fig.4(a)) for the same OOB noise performance, thanks to optimized switching (20%), and architecture simplification (50%).

Fig. 7 .

 7 Fig. 7. Output spectrum: ideal and non-ideal switching -σtr/tf = 0.5% . Ts, σPLH/PHL = 0.5% . Ts, σj,var = 1% . Ts. σj,var ≈ 2.8 ps when fc = 900 MHz.

Fig. 8 .

 8 Fig. 8. Output spectrum: coefficient mismatch -standard deviation 10%; Comparison with 11-bit RF DAC with ideal upconversion.

  Finally, the groups are processed by digital RF mixers (DRFM), which work as interconnection matrixes to derive the digital streams at 4*fc, namely RFP = {IP1, QP1, IP2, QP2, IP3, QP3, IP4, QP4}, and RFN = {IN1, QN1, IN2, QN2, IN3, QN3, IN4, QN4}, which drive the switching blocks of the positive and negative sides of the pseudo-differential FIR-DAC. IEEE Transactions on Microwave Theory and Techniques (ISSN : 0018-9480) 03-2019. DOI: 10.1109/TMTT.2019.2897929A. Digital RF signal generationThe FIR-DAC SIGGEN block uses the output of a single-bit quadrature ΔΣM to provide the necessary signals that implement (2) to perform the FIR filter simplification. At the input, a shift register holds 112 consecutive samples I/Q[1,…,112] at each time period (2/fc).

Fig. 10 .

 10 Fig. 10. All-digital RF transmit chain block diagram.

Fig. 11 .

 11 Fig. 11. Relative LO and image rejection degradation vs duty-cycle error

  errors (DCE) causing I/Q mismatch. System-level simulations showed that clock DCE determine an overall degradation of the noise performance (including image, LO, noise floor) in the first multiplexing ©IEEE Version submitted for final publication in IEEE Transactions on Microwave Theory and Techniques (ISSN : 0018-9480) 03-2019. DOI: 10.1109/TMTT.2019.2897929 step (separate I and Q paths) and introduce I/Q mismatch in the second multiplexing step (I/Q path interleaving), which mainly impacts the image rejection, as shown in Fig. 11 (for ΔDCE = ± 0.1%, where the duty cycle is DC = 50% + ΔDCE).In addition, an interface buffer is included between the digital RF signal generator and the FIR-DAC, according to a theoretical estimation of the line load in each path and an RC extraction of the output stage.

Fig. 13 .

 13 Fig. 13. (a) Group of 4 power cells; (b) DAC under FC pad.

Fig. 14 .

 14 Fig. 14. Die micrograph and IC mounted flip-chip BGA package cavity. The cavity includes also SMD inductors and decoupling capacitors.

Fig. 15 .

 15 Fig. 15. Measured spectrum: 3 MHz single-tone at 6dB back-off.

Fig. 16 .

 16 Fig. 16. Measured duty-cycle error correction using wide range FD-SOI body-bias tuning

Fig. 17 .

 17 Fig. 17. Measured output spectrum: (a) LTE 10MHz; (b) LTE 20MHz.

Fig. 18 .

 18 Fig. 18. Performance summary and comparison with state-of-the-art.

  With Single-Bit ΔΣM-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28nm FD-SOI Răzvan-Cristian Marin, Member, IEEE, Antoine Frappé, Senior Member, IEEE, Bruno Stefanelli, Member, IEEE, Philippe Cathelin, Andreia Cathelin, Senior Member, IEEE, and Andreas Kaiser,

	Senior Member, IEEE

C ©IEEE Version submitted for final publication in IEEE Transactions on Microwave Theory and Techniques (ISSN : 0018-9480) 03-2019. DOI: 10.1109/TMTT.2019.2897929

This work was supported in part by the Nano 2017 program in the frame of the ST-IEMN common lab, in part by STMicroelectronics, in part by the Hauts-de-France Region and in part by the Research Council of the Catholic University of Lille.

Răzvan-Cristian Marin