Tom Ranger
email: tom.ranger@univ-reims.fr

Algebraic Synthesis and Logical Filter Approach for the Control of Cyber-Physical Manufacturing Systems

RESEARCH PROBLEM

Within the framework of the development of Industry 4.0, the control of automated production systems is being rethought. Industry 4.0 proposes a distributed vision, leading to the concept of cyber-physical systems, where the control system is highly connected and communicating. In order for this new vision of the industry to succeed, more flexible and reliable systems are needed. Currently the controller is carried out by direct implementation of programs controller obtained by interpreting informal specifications provided by the specification. This way of designing the control requires a long time before implementation, without any guarantee of operation. Moreover, the lack of method limits the reuse of the knowledge acquired during the design process. It is therefore difficult to capitalize on the work done. It is therefore necessary to rethink the methods and tools used.

Many works deal with the synthesis of controllers by formal methods. However, these approaches focus mainly on the use of SCT (Supervisory Control Theory) definied by [START_REF] Ramadge | Control of discrete event systems[END_REF], 30 years ago. A large body of theoretical results has appeared since then, but there is still a gap between the theoretical development and the limited number of applications of SCT in the industry using PLC [START_REF] Fabian | Plc-based implementation of supervisory control for discrete event systems[END_REF], [START_REF] Cantarelli | Reactive control system design using the Supervisory Control Theory: evaluation of possibilities and limits[END_REF], [START_REF] Zaytoon | Synthesis and implementation of logic controllers -a review[END_REF]. Indeed, the main problems are the difficulty of modeling complex systems, the combinatorial explosion and the asynchronism hypothesis which is unsuitable for implementation on Programmable Logic Controllers (PLCs) operating synchronously. Other formal approaches that can be found in the literature concern code verification and validation, mainly by model-checking or theorem proving. Among the existing formal approaches, two have caught our attention. The first is algebraic synthesis [START_REF] Roussel | Design of Logic Controllers Thanks to Symbolic Computation of Simultaneously Asserted Boolean Equations[END_REF], a tool for solving a system of equations of Boolean algebra. The second is the notion of logical filter (Pichard, a https://orcid.org/0000-0003-3091-2337 2019), this method is based on adding filters to existing codes to ensure user and system security.

It is in this context that our research work takes place. Based mainly on algebraic synthesis and logical filters, we wish to address the following issues :

• Which formal tools will allow us to synthesize controllers suitable for PLC implementation?

• How to ensure optimal use of these formal tools when designing control laws?

• How can the effectiveness of the methods used and the validity of the control laws obtained be evaluated?

OUTLINE OF OBJECTIVES

In this section we will present the objectives we have set ourselves in order to respond to the issues raised.

For each problematic we will define the objectives necessary to solve them.

Develop Formal Tools for the Synthesis of Controllers Suitable for Implementation on PLCs

We have decided to base ourselves on algebraic synthesis. This tool can already be used to obtain parametric solutions to a problem. However, in order to make better use of this tool, we must be able to guarantee the conformity of the results generated in relation to the specifications. In order to facilitate the implementation of the command laws generated by the algebraic synthesis, we wish to use a Structure Text (ST), definied by (IEC 61131-3, 2013), code generation tool. The objective is to automate the generation of the code parts for which the designer does not need to provide knowledge. This will save time and avoid errors that can be caused by human processing of information.

Propose a Methodology Based on Formal Tools to Synthesize Control Laws

Despite the fact that automation engineers do not use formal tools or specific methods to generate their control laws, they rely on a set of good practices derived from field experience. It is therefore interesting to be able to formalize the use of these good practices.

If we wish to develop the most effective methodology possible it is necessary to ensure that each action is carried out using the right tool. Indeed, all the steps involved in the design of a control law do not have the same modelling needs or the same approaches. It would therefore be illusory to imagine being able to design a complete control law using a single tool. Our goal is therefore to use modeling tools other than algebraic synthesis for cases where it would be more efficient. For this it is necessary to identify the most suitable tools for the realization of each task. In addition, it is necessary to be able to define a method for using these tools to ensure that they are always used to their maximum potential.

In order to obtain a more modular control, we decided to detach ourselves from the sensor/actuator vision at the design stage. We prefer to use a taskdistributed control vision, where the system is divided into elementary tasks that it is capable of performing. The control problem then becomes the definition of the task synchronization in order to meet the specifications. To make this method effective, it is first necessary to determine the optimal granularity to which the system should be subdivided. In addition, we must be able to translate a precise functional constraint into a constraint on the tasks synchronization. In addition to this task-based vision we aim to use logical filters to manage security constraints. In addition, we would like to extend the use of these filters to functional constraints.

Develop Methods and Criteria for Evaluating the Methods Developed and Validating Control Laws

In order to be able to correct design errors as well as possible and to be able to identify their source we would like to be able to check the validity of our formalized problem before proceeding to the resolution. Indeed, the earlier a defect is identified, the easier it is to correct it. It is therefore necessary to be able to analyze the system of Boolean equations. To do this we want to represent its structure in the form of a discrete event systems model and to analyze it. It is therefore necessary to define which criteria we want to check and how to evaluate them.

While this verification at the level of the formalization of the problem makes it possible to detect and correct possible errors, it is not sufficient. It is necessary to validate the final controller, whether in terms of functional properties or safety.

Finally, in our method development process we must be able to quantify the effectiveness of a method in the face of a given problem. This will allow us to compare different methodologies in order to obtain the most efficient method as possible.

STATE OF THE ART

In this section we will focus on the two approaches that we have chosen for the conduct of our research.

Algebraic Synthesis

Algebraic synthesis is used in the case of sequential discrete event systems as represented in figure 1. Such system controllers are equipped with p Boolean inputs (u i ), q Boolean outputs (y i ) and r Boolean state variables (x l ). The algebraic modeling of control laws requires the generation of (q + r) switching functions of (p + q) variables. The generation of those functions has to be automatised due to combinatorial explosion. As a matter of fact the Figure 1 controller can send 2 q outputs combinations and can express (2 2 (p+r) ) (q+r) sequential behaviours. This automation, defined by [START_REF] Hietter | Synthèse algébrique de la loi de commande d'un système à évènement discrets logique[END_REF]) is achievable thanks to results on Boolean algebra presented by [START_REF] Brown | Boolean Reasoning[END_REF].

Initially, algebraic method has been used to synthesize the full control law [START_REF] Roussel | Algebraic synthesis of logical controllers despite inconsistencies in specifications[END_REF]. It follows a methodology, starting from functional and safety requirements formalization to finish with the choice of one solution to implement in the PLC, based on optimization criteria, However, this approach is not suitable for large systems and it is difficult to formalize and to validate all requirements. Moreover, the obtained solution is often difficult to read. The proposed approach is quite different. We intend to use algebraic synthesis not to synthesize the full control law, but only parts of it, where it seems very efficient. Indeed, it exists for instance very efficient tools to specify simple sequences like GRAFCET (IEC 60848, 2012). It is frequently used in the industry to model independent task sequences.

The latest work related to algebraic synthesis [START_REF] Roussel | Design of Logic Controllers Thanks to Symbolic Computation of Simultaneously Asserted Boolean Equations[END_REF] present the whole method applied to an example in order to enhance the benefits and limitations of the approach. The main advantage emphasised in this paper is the independence between the synthesized control law and the requirement interpretation. However, this means that the method is highly dependant on the relevance and correctness of the requirements. The solver used is a software tool developed in Python. The inputs of this tool are a set of known and unknown variables and a set of requirements, defined as combination of those variables. It can provide two kinds of outputs. If the requirements set is consistent, a parametric solution of each unknown variable will be given. On the other case, the inconsistency conditions will be given. With this tool we can also prioritise the relations in order to rise inconsistency. Expression to maximise or minimise can be declared in this software to reduce the parametric solution to a unique one thanks to the works of (Leroux and Roussel, 2012).

Logical Filter

A logical filter takes place after the program execution as shown in Figure 2. This notion first appeared in the works of [START_REF] Marangé | Synthèse et filtrage robuste de la commande pour des systèmes manufacturiers sûrs de fonctionnement[END_REF], then was extended by those of [START_REF] Coupat | Méthodologie pour les études d'automatisation et la génération automatique de programmes Automates Programmables Industriels sûrs de fonctionnement[END_REF]. Two kinds of modifications can occur to the command law. In the case of a blocking filter, a constraint violation will lead the system to a predetermined and stable state. In the case of a corrective filter, a constraint violation will lead to an output adjustment to fit with the filter constraint set. A corrective filter generation depend on the functional program and, more precisely, if it has been created with the knowledge of the logical filter.

The contribution of Pichard [START_REF] Pichard | Contribution à la commande des systèmes à événements discrets par filtre logique[END_REF] to logical filter brings a formalism to the definition of logical constraints which enable him formal verification for logical filter consistency. Nevertheless, this formalism is accompanied by strong restrictions for the constraints redaction. This results to a lower power of expression than our algebraic synthesis approach.

METHODOLOGY

One of the constraints we have set ourselves is to generate control laws that can be used in the industrial environment and therefore on PLCs. It is therefore necessary for us to be able to go as far as the implementation phase. In a first step, we will use an operating parts simulator. We will use Factory I/O (Figure 3) for this. This software allows us to create our own scenes and integrates a physics engine as well as the possibility to simulate defects in sensors and actuators. In addition to allowing us to test our control laws the passage through simulation will allow us to retrieve operating data for a large simulation time. The analysis of this data could enable us to obtain control strategies, particularly in terms of tasks synchronisation.

Concerning the stages of verification and validation of the controller, we intend to go through the model checking. However, we cannot directly analyze our system of Boolean equations or our ST code with a model checking tool. It is first necessary to model our control by state machines. This type of modeling should allow us to check properties on our control at the implementation level. As for checking the conformity of the problem formalization to the specifications, we are considering another method. In the case of dealing with a task synchronization problem, we can represent the task scheduling in the form of a Petri net. This will allow us to use the analysis tools specific to this type of model.

Evaluating the effectiveness of a design method in terms of usability and speed seems difficult to quantify internally. This is why we intend to test our methods in concrete cases with different types of population. Initially we intend to solicit other researchers in our laboratory in order to obtain feedback from a scientific point of view. However, as the methods we wish to develop are intended to be used by industry, it is essential to go beyond the academic framework for our tests. This is why we are also going to solicit industrial players to evaluate our methods. Finally, as we are also in contact with students through teaching Finally we will have to use a mathematical approach to be able to demonstrate formal properties on the results obtained in algebraic synthesis.

EXPECTED OUTCOME

First of all, let's take a look at the tools we want to develop. At the level of algebraic synthesis, the goal is to bring formal proofs at the level of optimization criteria. Indeed, we want to be able to guarantee the reduction of a solution space to a single solution in a precise number of criteria. In this way it will be possible to define a methodology based on the algebraic synthesis ensuring the achievement of unique solutions. Concerning the automatic code generation tool, we want to be able to obtain a code that can be implemented in a PLC by providing only our formalized constraints.

In a second step, let's focus on the methodology. The goal is to obtain an efficient method based on a task-based vision and the use of control filters to guide the design of a control law. For this it is also necessary to establish a catalogue of practical cases, in order to provide a method adapted to each situation. Finally, we need to know how to define our system of equations in order to translate properties and behaviors expected for the system. Finally, let's look at the methods of verification and validation. We want to be able to determine the accuracy of the formalized problem and to provide elements of solutions if necessary. In addition, it is necessary to be able to certify the respect of the specifications at the time of implementation as well as to guarantee the security of the users and the system.

STAGE OF THE RESEARCH

Regarding our tools, we have developed software in C for automatic code generation. It will retrieve the inputs/outputs of a Factory I/O scene as well as command specifications in order to generate ST code. The specifications can only be integrated as GRAFCET for the moment but we would like to add the possibility of integrating a Boolean equation system later on. The output file can be generated in order to be usable by the UNITY and CODESYS software.

Concerning the methods, we first wanted to test the capacity of the algebraic synthesis to solve various control problems. In particular, we succeeded in implementing blocking and corrective filters. Then, thanks to these security filters we were able to implement a manual mode. As for the task-based approach, we were able to ensure task synchronization by algebraic synthesis for simple cases. However, with the increasing complexity of the systems to be studied this synchronization proved to be difficult to achieve. Therefore, we need to progress on design methods with a task-based vision, especially at the level of task anteriority definition.

Figure 1 :

 1 Figure 1: A sequential discrete event system.

Figure 2 :

 2 Figure 2: Principle of implementation of the logic filter in a PLC.

Figure 3 :

 3 Figure 3: Software Factory I/O

ACKNOWLEDGEMENTS

I would like to thank Bernard Riera and Alexandre Philippot for their contributions to this line of work.


Dominique Planson
email: dominique.planson@insa-lyon.fr

Dominique Tournier

Pascal Bevilacqua

Nicolas Dheilly

Herve Morel

Christophe Raynaud

Mihai Lazar

Dominique Bergogne

Bruno Allard

Jean-Pierre Chante

SiC Power Semiconductor Devices for new Applications in Power Electronics

Keywords: SiC-device, High temperature electronics, Power semiconductor device, High voltage Device, Power integrated circuit

This paper addresses the benefits of SiC semiconductor, owning excellent physical properties able to fulfill new scope of applications in terms of high temperature, high voltage and for more specific applications. Devices and applications developed at Ampere laboratory are detailed.

I. INTRODUCTION

The first unipolar power silicon carbide devices (Schottky diodes) were commercialized in 2001 [START_REF] Stephani | Status, prospects and commercialization of SiC power devices[END_REF], [2]. Nowadays power JFETs are available as engineering samples [START_REF] Round | A SiC JFET Driver for a 5 kW, 150 kHz Three-Phase PWM Converter[END_REF], [4] . These two devices enable to build a large number of power switching converters. It is worth listing the scope of applications for which silicon carbide devices can advantageously replace classical silicon power semiconductor devices. The first kind of applications for SiC power devices are applications for which the use of silicon is impossible or restricted. The second kind of applications for SiC devices correspond to systems in which mass reduction is a key issue, e.g. for embedded systems like in transport. Figure 1 illustrates the on-state resistance for different semiconductor materials. It yields the optimal onresistance limit versus breakdown voltage of an infinite plane junction for different semiconductor materials. These are theoretical limits. Stars correspond to power device demonstrators. It is clear that there are over the theoretical limit of Si and also from the SiC limits. From this figure, it is clear that there is still a great margin to get the optimal performances of SiC devices.So, clearly, SiC power device applications are high temperature and/or high voltage applications. However, most of recent studies have shown that the use of SiC devices does not consist in a simple replacement of silicon devices by silicon carbide devices. Indeed a new design of power electronic systems must take advantage of the properties of the new SiC power devices.

II. HIGH VOLTAGE APPLICATIONS

Such applications are medium term applications because high voltage devices are not ready for industrial applications. However 10 kV demonstrators have been developed, 15kV demonstrators are under development even 30kV and further may soon be obtained. The interest in such devices is huge since they enable to :

• replace heavy 50Hz high voltage electrical transformers by high voltage static power electronics. • replace AC-current distribution networks by DCcurrent distribution networks and eliminating numerous associated problems like instability (wind-power farm ...) even blackout. This enables an easier integration of renewable energy sources (Photovoltaic, Wing power...) and removes the need of 50Hz electric transformers. • improve the high voltage system protection with very fast active protection systems. The main issues of these new applications are :

• availability of high bipolar diodes and switches (BJT, Thyristors, ...), • electrical insulation of the high voltage converters (packaging, passivation, ...), • thermal cooling of the high voltage converters, highly insulated driver for high voltage converters even multi-level converters. Ampere lab works are divided in several tasks:

A. Design of high voltage periphery protection

Design of efficient peripheral protection is fundamental for high voltage devices. This protection should have an optimum geometry in order to avoid local critical electric field areas. There are various possible protections such as JTE (Junction Termination Extension), Mesa, field plates 2488 978-1-4244-1742-1/08/$25.00 c 2008 IEEE or guard rings [START_REF] Baliga | Modern Power Devices[END_REF]. Design of classical JTE needs an accurate control of the doping dose to reach the complete depletion of the termination well for a given reverse voltage (V BR ). The peripheral protection efficiency is the ratio between breakdown voltage of the protected diode and of the ideal diode (plane parallel junction), this last being named theoretical breakdown voltage afterwards. JTE process for SiC device is most often an ionic implantation followed by a thermal annealing. Figure 2 shows the breakdown voltage of a bipolar diode against the termination doping dose for several JTE lengths. With an epitaxial layer thickness of 50μm and a doping level of 10 15 cm -3 , the diode is able to sustain 7.5kV . The JTE depth is 0.8μm. As can be observed from Figure 1, breakdown voltage is very sensitive to the implanted dose. Besides this voltage is almost independent from the well length if the JTE is longer than 100μm. The breakdown voltage is calculated by numerical bi-dimensional simulation using MEDICI T M software [START_REF]MEDICI: Two dimensionnal semiconductor device simulation[END_REF] and impact ionization coefficients published by Konstantinov [START_REF] Konstantinov | Ionization Rates and Critical Fields in 4H-SiC Junction devices[END_REF]. V BR is defined as the voltage involving a leakage current of 1μA.μm -1 . JTE with variable lateral doping is a good way to get an efficient protection valid for a wide range of doping concentration. Thanks to the diffusion process, it is possible to realise this kind of JTE in silicon. However, due to the lack of dopant diffusion in SiC, variable doping JTE is very difficult to obtain. A good alternative is a JTE with multiple constant doping zones to approximate the optimum lateral profile. Figure 3 presents a SiC bipolar diode protected by a three-zone JTE that has been optimized to achieve a breakdown voltage that is as close as possible to the theoretical breakdown voltage.

Each zone is defined by its doping dose D i and its length X i . Figure 4 shows 5 possible configurations of doping variation of the three zones enabling a V BR of 7500 V i.e. 99% of the theoretical breakdown voltage. The highest doped zone is the first one and its variation range is the widest. For the two other zones, dose choices are more critical, because of the wider D2 variation range, and of the narrower D3 one.

A 7500 V breakdown voltage can be obtained using

B. Fabrication of high voltage bipolar devices

The aim of this study is to show potentialities of silicon carbide for high voltage power systems. Test structures are SiC bipolar diodes able to sustain 1.3kV and 5kV . Emitter and periphery protection (JTE) are obtained by ion implantation of Aluminium in epitaxial n-type layer grown on commercial substrate. The number of devices which exhibit efficiency > 84% has been improved during the last four years. Indeed 70% of the 1.3kV diodes with an emitter implanted at 300˚C and a long JTE (120 m) exhibit a breakdown voltage higher than 1100V (up to 1300V ) without any impact of the ambient conditions (air or SF6 gas or dielectric liquid). The ambient conditions impact breakdown voltage only for diodes with short JTE length (50m) [START_REF] Lazar | The role of the ion implanted emitter state on 6H-SiC power diodes behavior. A statistical study[END_REF]. These results show in the same time that post-implantation annealing realized in the lab furnace [START_REF] Lazar | The role of the ion implanted emitter state on 6H-SiC power diodes behavior. A statistical study[END_REF] allows a full activation of dopants in JTE. In forward state, current densities and efficiency have been improved (200 A/cm2 @ 5 V at room temperature) also due to the improvement of metallization step and subsequent annealing at IMM Bologne [START_REF] Nipoti | Contact Resistivity of Al/Ti Ohmic Contacts on p-Type Ion Implanted 4H-and 6H-SiC[END_REF]. Results of acceptable ohmic contacts on highly doped P+ zones are comparable with other results already published in literature [START_REF] Crofton | Finding the Optimum Al-Ti Alloy Composition for Use as an Ohmic Contact to P-Type SiC[END_REF]. As it can be observed in Figure 5, Ampere-lab is now able to present results of breakdown voltage in the range of 4 kV, with a maximum of 4.8 kV with low reverse current density in fluoride ambient (Galden and SF6) [START_REF] Raynaud | fabrication and characterization of 5 kV 4H-SiC p+n planar bipolar diodes protected by junction termination extension[END_REF]. Without passivation, breakdown voltage is only 1.3kV for these devices with a JTE length of 250m (optimized with respect to the semiconductor properties). This clearly proves the need for passivation in order to fully take benefit of SiC properties for high voltage applications. Theoretical interest to use passivation materials with high dielectric permittivity ( ) in order to reduce electric field outside SiC have been shown using simulation software MEDICI on a 5 kV bipolar diode protected by JTE. For a given structure, only a sufficiently high value allows to reduce electric field peaks both at emitter and JTE extremities, by stretching space charge region outside the JTE [START_REF] Locatelli | Study of suitable dielectric material properties for high electric field and high temperature power semiconductor environment[END_REF]. Another advantage to use a high material is to significantly reduce the sensitivity on breakdown voltage with respect to the optimal dose of JTE. From the technological point of view, choice of such material (with high ) and a compatible deposition method remains to be solved before obtaining experimental results. Among available and practical insulating materials, polyimide materials specifications exhibit good dielectric together with good thermal properties under usual conditions. Thus an experimental characterization using MIM and MIS structures has been launched in order to quantify their effective characteristics within an extended temperature range. For high voltage (up to 50kV ) and high temperature (up to 500˚C) measurements, a specific set-up has to be developed.

1) Fabrication of high voltage thyristor: Since silicon based technology is reaching its physical limits concerning blocking and power handling capability, GTO thyristors based on SiC are under investigation for compact future pulsed power systems [START_REF] Scharnholz | IEE Proc. of the 1st European Pulsed Power Symposium (EPPS)[END_REF]. Reaching breakdown voltages of 19kV [START_REF] Sugawara | kV 4H-SiC pin diodes with low power loss[END_REF], the potential of SiC based devices appears very interesting. According to primary device simulations using the finite element code MEDICITM, the developed GTO-thyristors should be able to block voltages up to 6kV . For the device realization, a ntype 4H-SiC wafer material is obtained from Cree Re-searchTM, including a P P -NP + (from the wafer up to the top) epitaxial layer structure [START_REF]MEDICI: Two dimensionnal semiconductor device simulation[END_REF]. Anode P+ type Fig. 6. Thyristor structure with planar electrodes for anode and gate and combined periphery protection: MESA and JTE and gate N+ type layers were obtained by Aluminium (Al) and Nitrogen (N ) ion implantation doping followed by a high temperature annealing in the 1700˚C/30min range in order to activate the dopants. Mesa structures were fabricated by Reactive Ion Etching with Ni masks with a particular attention to avoid micromasking formation and preserving the initial roughness of the surface. Ohmic contacts are formed by deposing layers composed on Al/N i/T i alloys followed by a RTA annealing at 1000˚C during 1 to 2 min. Measurements have been performed on chip, in oil and as shown in Figure 7 a breakdown voltage of nearly 5kV has been reached.

III. SPECIFIC APPLICATIONS USING SIC DEVICES

The ability for SiC devices to operate in the high temperature range, 250˚C up to 600˚C allows applications not possible with conventional silicon devices, especially for mains-operated systems.

A. Current limiting devices

To protect power electronic circuits against over-current or over-voltage either serial protection (SP) or a parallel protection (PP) can be used. For the serial protection (8, usually used components are Serial Protection Device (SPD) or Current Limiting Device (CLD), being either fuses, mechanical contactors, superconductors or polymers. In all cases it is necessary to dissipate the overload energy through the protection device which has to sustain high voltage and high current simultaneously. These constraints imply a very fast temperature increase. So, when the protection device is active it has to sustain high junction temperature. All these constraints will globally define the electrical specifications of this kind of device. Up to now, only few semiconductor current limiter structures have been described in the literature [START_REF] Sanchez | Design and fabrication of a new high voltage current limiting device for serial protection applications[END_REF], [START_REF]Current limiter circuit[END_REF]. Although Current Regulative Diode components already exist, their voltage and current capabilities (V BR = 100V , I MAX = 10mA), do not allow to use them in power systems. A promising application of SiC-based devices is current limitation for power system protection, which benefits from its high thermal conductivity and wide band gap. In the steady state operating mode (or passive state), the voltage drop across the component must be as low as possible. In the active state, (limiting phase), the current limiter must sustain a high current, under high voltage bias. The resulting high power density must not cause the component failure. Two specific current limiting devices (CLD) have been studied [START_REF] Tournier | Current limitation with SiC devices[END_REF], [START_REF] Tournier | Optimal layout for 6HSiC VJFET controlled current limiting device[END_REF], [START_REF] Nallet | Very low R/sub ON/ measured on 4H-SiC accu-MOSFET high power device, Power Semiconductor Devices and ICs[END_REF] taking into account previous considerations.

Figure 9 shows a cross section schema of the VJFET and the main parameters to adjust. This device has a channel divided in two parts: a vertical one and a lateral one. The source is grounded and current flows from drain to source. P-buried layers are designed so that the VJFET is normally-on and presents a low specific resistance. When the drain voltage rises, the current saturates at a voltage corresponding to the pinch-off of both vertical and horizontal channels. In the saturation mode, the device presents an important on resistance (R ON ), resulting from the serial resistance of both parts of the channel and the drift resistance of the epitaxial layer. Due to self heating, current decreases as the voltage increases (since electron mobility decreases and induces a current reduction). This effect is amplified while increasing the limiting current density. When a negative bias is applied between gate and source, the PN junction formed by the Pwell and the epitaxial layer is reverse biased leading to current modulation. The device optimization job consists in the design of buried layer (the gate electrode of the devices, which is formed by either high energy implantation or epitaxial process), and the tuning of horizontal channel parameters. A trade off between specific resistance and blocking capabilities was investigated by means of analytical model and finite element simulations. Figure 10 presents the vertical JFET structure, 3 terminals device, with all parameters to be optimised by simulation with ISE TCAD. An AccuMOSFET, 2 terminals device, has also been designed and fabricated.

Fabrication process (7 level masks) complexity is similar to silicon power device one. The samples were manufactured at Centro Nacional de Microelectronica, in Barcelona. Key points of the device fabrication are high energy implantation, annealing activation and ohmic contact formation. Based on CNM-SiC technology, specific steps have been optimized: horizontal channel definition (implanted doses value as well as geometrical parameters) for both the VJFET and the AccuMOSFET. An additional step has been tuned for the AccuMOSFET: the MOSFET channel oxide layer. First batch of small area devices has been fabricated. Figure 11 presents the measured electrical characteristics for an unidirectional VJFET. Measurements were done by applying 0.5s pulse (f = 2Hz), with drain biased up to 400 V. The specific on-resistance varies from 176mΩ.cm 2 up to 237mΩ.cm 2 . The maximum pulsed power density dissipated by the CLD in the limiting mode is 160kW/cm 2 . Limiting capabilities have also been measured for a bi-directional device made of two unidirectional devices connected head to tail (i.e. drain connected). This one exhibits a specific onresistance of 700mΩ.cm 2 . Highest breakdown in current limiting state were measured to be 810V , corresponding to a high pulsed power density of 140kW/cm 2 . As it can be observed from Figure 12, the current limiting device is able to react in a very short time (less than 1μs). Based on small area devices optimization work, larger area AccuMOSFET (S = 0.3cm 2 ) have been fabricated.

Static characterizations have been performed using a specific pulsed power measurement setup. Depending on the layout of the device (geometrical variation), saturation current in the range of 300A to 450A has been measured (Figure 13), with a pinch-off voltage around V P = 12V . Self heating effect for short time pulses (t P = 100μs) has been estimated by an analytical model. Mobility, i.e. current, reduction of 9% for a 100μs pulse gives an internal temperature increase estimation of 10˚C. Based on experimental measurements, analytical modeling and electro-thermal finite element simulations, the short circuit energy capability of an AccuMOSFET CLD has been estimated to be ECC max = 35J. We report on both simulation work, fabrication process and experimental results of a unidirectional and bi-directional current limiter structure based on a VJFET and ACCUMOSFET, with improved current capabilities (specific resistance as low as 40mΩ, and a saturation current between 200A < I SAT < 450A). The design was made using the ISE software with respect to the technological limitations. The first demonstrator exhibits optimistic dynamics characteristics. Bi-directional components were measured by associating two devices head to tail. Short circuit demonstration was done using 5W -240V bulbs as a load on low current rating devices. Very low response time to short circuit has been measured (as low as t R = 1μs). Using such a component with increased current ratings should permit a complexity reduction of classical mechanical device. Next challenges consist in both current sensing and current modulation in limiting state using the gate electrode so that to reduce short circuit power losses.

B. Monolithic converters

Hybrid approaches suffer from interconnection reliability. Integration appears to be a more effective approach providing capable power devices and passive components. Due to their physical properties, semiconductors with large band-gap are very interesting in this case. The integration allows to reduce considerably the switching time and to reduce losses and parasitics related to the device interconnections. This integrated system based on the design of SiC lateral JFET with a breakdown voltage of 900V is presented in Figure 14. In order to improve the blocking voltage and to reduce the Ron-resistance, the RESURF technique [START_REF] Ludikhuize | A Review of RESURF Technology[END_REF] is applied in this work to design SiC lateral JFETs. The P + type region (gate), N + type region (source and drain), N type active layer and Ptype top layer are realized by ion implantation. The epitaxial layer at the top of the substrate is defined by a Ptype region with a uniform doping concentration. A double-junction is created in the top and the bottom of the active ntype layer, improving its lateral depletion and allowing increasing of its doping. The ntype active layer constituting the JFET channel, this technique allows to obtain a JFET with higher channel doping and so a lower on-resistance by keeping a high V BR . A relationship between the doping concentration and the thickness of layers must be respected to vertically deplete both the ptype top layer and ntype channel layer before the lateral junction breakdown. The structure of these devices was studied with MEDICI T M . In each area of the device structure, different parameters are defined such as profile and concentration of doping impurities which were estimated by Monte-Carlo simulations taking into account the 4H-SiC crystalline structure. The lateral JFET is a normally-on device. A negative gate voltage is required to turn the device off. The channel doping is 2.10 17 cm -3 and its thickness is 0.40μm which is smaller than the thickness of the depleted region produced by the applied drain-tosource voltage. The thickness of the ptype top layer is 0.12μm The potential line distributions in the double RESURF SiC JFET in forward blocking mode are shown in Figure 15 for different doping concentrations of the top layer varying from 5.10 16 cm -3 to 5.10 17 cm -3 .

The V BR variation is also presented in Figure 16. The potential lines are distributed mainly in the p-type epilayer due to the low doping concentration of this layer. The presence of the top layer with a low doping concentration (5.10 16 cm -3 -Figure 15-a) generates a potential line distribution transversally at the device surface. In this case, the value of blocking voltage is equal to 385V . In the same way, a high doping concentration of the top layer with a high doping concentration (5.10 17 cm 3 -Figure 15-d) makes difficult to deplete this layer. The maximum value of electric field is obtained at the drain side. In this case, the potential lines are concentrated that involves the device to reach prematurely the blocking voltage.

The potential distribution is optimum, when the doping concentration of the top layer ranges between 10 17 cm -3 and 2.10 17 cm -3 , thus obtaining a trapezoidal electric field profile between the drain and the gate. In this case, the Space Charge Region (SCR) surface is wider when he VBR of the JFET is increased up to 1kV , as presented in Figure 16. The lateral JFETs run is performed (Figure 17). The first results show that in blocking state, the RESURF structures are validated in terms of voltage rating. Breakdown voltage values as high as 600V were obtained which is conform to the specific requirements for which these devices have been designed.

IV. CONCLUSION

This paper shows the already existing devices and applications using SiC devices. Higher theoretical values could be reached but the environment of the devices remains a critical issue. Dealing with Current Limiting Devices, although we demonstrate they are able to sustain high current densities, the packaging and interconnections are limiting their performances. It seems to be clear that for high voltage devices, the periphery protection must now combine several classical techniques, and must take into account the passivation features (dielectric permittivity, thicknesses and interface states density). There is still works to be done to reach the real performances of SiC semiconductor material, for the fabrication of high voltage, high temperature and integrated power systems.

Fig. 1 .

 1 Fig. 1. On state resistance for unipolar devices for various semiconductor materials.

Fig. 2 .

 2 Fig. 2. Breakdown voltage against implanted dose for a constant lateral doping profile and for several JTE lengths.

Fig. 3 .

 3 Fig. 3. Vertical cross-section of the triple JTE (D1, D2 and D3) protected diode.

Fig. 4 .

 4 Fig. 4. Five possible dose configurations and their variation ranges to obtain a 99% protection efficiency.

Fig. 5 .

 5 Fig. 5. Reverse I-V characteristics of 5kV bipolar diodes measured in three different ambient conditions: air, galden and SF6. Active area A = 0.05mm 2 .

Fig. 7 .

 7 Fig. 7. Forward blocking characteristics of the device.

Fig. 8 .

 8 Fig. 8. Circuit using the protecting device

Fig. 9 .

 9 Fig. 9. VJFET parameters to be optimized.

Fig. 10 .

 10 Fig. 10. JFET structure with its parameters.

Fig. 11 .

 11 Fig. 11. Electrical measured characteristics for unidirectional and bidirectional limiter.

Fig. 12 .

 12 Fig. 12. Switching waveforms of the current limiter with gate control.

Fig. 13 .

 13 Fig. 13. Electrical measured characteristics for unidirectional high current liming AccuMOSFET device.

Fig. 14 .

 14 Fig. 14. Schematic presentation of the SiC lateral JFET with a double RESURF structure.

Fig

  Fig. 15. Potential distribution for the lateral JFET with a doping concentration of the Ptop layer : 5.10 16 cm 3 (a), 1.10 17 cm 3 (b), 2.10 17 cm 3 (c)and5.10 17 cm 3 (d)

Fig. 16 .

 16 Fig. 16. V BR versus top layer doping for the JFET structure.

Fig. 17 .

 17 Fig. 17. Top view of the SiC lateral JFETs with different inter-digitated structures and different sizes.

13 th International Power Electronics and Motion Control Conference (EPE-PEMC 2008)

13 th International Power Electronics and Motion Control Conference (EPE-PEMC 2008)

ACKNOWLEDGMENT

The authors would like to thank all the financial support from different institutions and companies, namely DGA, CNRS, ISL, Schneider-Electric, ST micro-electronics, Alstom and Hispano-Suiza. Authors also gives special thanks to Philippe Godigon of the "Centro Nacional de Microelectronica" of Barcelona for clean-room SiCprocess support.