voltage V VGbN Ground-plane N voltage V VGbP Ground-plane P voltage V VK Cathode voltage V VON Turn-ON voltage V VR

Keywords: 3.6. Conclusion, 3.7. References, Conclusion and perspectives, Publications, Résumé du manuscrit, FD-SOI, ultrathin film, electrostatic doping, virtual diode, Esaki diode, carrier lifetime, bandmodulation devices, 1T-DRAM, logic switch, Z 2 -FET

VA

Anode voltage V VAprog Programing anode voltage V VAread Reading anode voltage V VE Emitter voltage V VG Gate voltage V VG1, VG2 Front-and back-gate voltages in MSDRAM V VGF Front-gate voltage V VGB Back-gate

wonderful people around me. First or foremost, I would like to thank the members of the jury for the time spent to evaluate this work and attend my Ph.D. defense. Thank you, Prof. Olivier Bonnaud, Prof. Ray Hueting, Prof. Carlos Sampedro and Prof. Gérard Ghibaudo.

I would like to express my deepest sense of gratitude to my supervisors, for their patient guidance, enthusiastic encouragement and useful critiques of this research work. My flourishing three year Ph.D. life had begun thanks to you, Maryline. During the project, not only the knowledge I acquired but also lots of skills in professional meetings are very precious. I learned how to deal with the problem and I could have never met various people in academia and industry without this opportunity. Words like thank you are not enough to say how I feel to you, Sorin. Your support in many aspects of my life and studies encouraged me a lot during my stay in France. I would not have finished successfully my Ph.D. without you.

I am happy and deeply grateful for spending cool and funny moments in the office 217 with Mukta, my best chatty friend, I could never forget the time we spent in our office next to each other.

Hyung-jin has been always there encouraging me as a Korean mafia colleague. The life and soul of our office -Dimitris, Lici, Miltos and Namanu-the long hours in the lab were always delightful and fun thanks to you guys. Thank you, Elodie for your kindness to clumsy new-comer 3 years back. There are lots of more friends who shared my great time in IMEP-LAHC. Thank you all. Also, many thanks are due to Xavier and Martine for their valuable technical support and patience throughout the whole years. Furthermore, I kindly thank for the help that I received from all the HR team members.

To all of my awesome friends in Grenoble: life here without you would not have been worth it. I cherish all the great memories with you all. Thank you for being with me whenever I was happy or sad. To my best friends who encouraged and cared about me long away from Korea or even visited me here: you were my drives and motivators of my life and it will always be.

Last but not least, I love my family who keeps supporting me and watching over by my side.

Mom and Dad, you have always tried to help and encourage me as if you got through 3 years in France with me. My sister and brother, thanks for cheering me up during my career. Photos of Coco sent from you were like rain for a drought.

Thank you all for being part of my life in France.

Physics in capacitorless 1T

-DRAM Z 2 -FET operation •••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.2.1. DC operation •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.2.

Transition between DC and pulse mode

••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.2.3. Transient characteristics ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.3. Experimental validation of Z 2 -FET memory operation •••••••••••••••••••••••••••••••••••••••••••••••••••• 3.3.1. DC operation •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.3.2. Transient mode operation ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.3.2.1. Standard memory operation •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.3.2.2. Retention •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.3.2.3. High temperature measurement •••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.4. Advanced Z 2 -FET memory •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.4.1. Advanced Z 2 -FET structure: dual ground-plane ••••••••••••••••••••••••••••••••••••••••••••••••••• 3.4.2. Selection-transistor-free Z 2 -FET memory array •••••••••••••••••••••••••••••••••••••••••••••••••••• 3.5. Z 2 -FET as a logic switch ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.5.1. Z 2 -FET with single ground-plane •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.5.2. Novel Z 2 -FET with dual ground-plane •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

Mots clés

FD-SOI, film ultra-fin, dopage électrostatique, diode virtuelle, diode Esaki, durée de vie des porteurs, dispositifs à modulation de bandes, 1T-DRAM, interrupteur logique, Z 2 -FET.

Introduction FD-SOI

Electrostatic doping vs. physical doping

Sharp-switching device

1T-DRAM Contents 1. SOI technology •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.1.
State-of-arts and trends:

MOSFETs ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.2. Migration to FD-SOI •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.3. FD-SOI technology •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 2. Physical doping vs. Electrostatic doping ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 2.1. Physical doping: Ion implantation ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 2.2. Electrostatic doping ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3. Sharp-switching devices ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.1. Tunnel FET (TFET) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.2. Impact ionization-MOSFET (I-MOS) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.3. Nano-electro-mechanical FET (NEM-FET) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.4. Ferroelectric-FET (Fe-FET) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3.5. Band-modulation device: Z 2 -FET •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4. 1T-DRAM: Capacitorless Dynamic Random Access Memory •••••••••••••••••••••••••••••••••••••••••••••• 4.1.
State-of-the art: the need for new memory for Internet of Things (IoT

) •••••••••••••••••••••• 4.2. Conventional 1T+1C DRAM •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4.3. Resistive RAM (ReRAM) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4.4. Spin Torque Transfer-RAM (STT-RAM) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4.5. Floating-Body DRAMs (FB-DRAMs) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4.5.1. Meta-stable DRAM (MSDRAM) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4.5.2. A2RAM •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4.5.3. Z 2 RAM (Z 2 -FET RAM) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 5. References ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

SOI technology 1.State-of-art and trends: MOSFETs

Ever since the invention of the Field-Effect-Transistor (FET) at Bell laboratories by W.

Shockley [1], J. Bardeen and W. Brattain [2] (Nobel Prize 1956) in 1948, and the first Integrated Circuit (IC) created by J. Kilby [3] (Nobel Prize 2000) following, the CMOS technology emerged as the dominant fabrication method for semiconductor integrated circuits [4]. As the CMOS technology is a driving force, the MOS transistor (Fig. 1.1) was exclusively fabricated on Bulk silicon substrate (P-type for nMOS and N-type for pMOS). The source and the drain are realized by implantation of donor/acceptor dopants next to the conduction channel. Considering the p-type silicon substrate, the source and the drain contacts are N + type. The gate is separated from the substrate by a dielectric layer.

The down scaling increases the on-chip transistor density. Nowadays, a chip can contain a few billion transistors. However, the fast downscaling puts almost an end to Moore's law [5].

Until roughly 2012, transistor fabrication costs continued falling at rapid rates. At the 22/20 nm technology node, which went into volume production around 2012 at Intel, the cost of transistor is no longer decreasing as fast as before while the equipment investment increases aggressively (Figure 1.2) [6].

The bulk planar silicon MOSFET is facing severe problems as miniaturization continues particularly with respect to power consumption [7], [8]. When the gate length shrinks, the depletion regions of source (S) and drain (D) can overlap affecting the channel electrostatic control induced by the gate bias. The potential distribution in the channel therefore depends on both transverse electric field (controlled by the gate) and longitudinal electric field (induced by the drain bias) which results in many forms of undesirable electrical characteristics [4]. Short-channel effects [9] (SCE) which are critical issues in low-power operation devices, such as threshold voltage roll-off, subthreshold swing (SS) degradation, mobility degradation and drain induced barrier lowering (DIBL) have been on the rise. Although there have been new technologies and architectures (Metal Gate, LDD implant, Halo implant, etc.) proposed to solve the SCE, the improvements are still insufficient for harsh scaling-down.

Migration to FD-SOI

The MOS transistor implementation became more and more complex. In order to address this challenge and improve the device performance, adoption of new technologies, new materials and new architectures is required. One candidate, SOI has traditional merits: total insulation of devices, thin junctions to reduce leakage currents and parasitic capacitances, robustness to irradiation, etc. [10].

However, they were not enough to disrupt the conventional CMOS technology. When the miniaturization of transistors has been blocked, it has been shown that the only way to keep moving forward on Moore's law is to reduce their thickness. This argument was decisive not only to re-establish the SOI technology, but also to give birth to FinFET technology.

A thin MOS transistor is by nature completely depleted, which gave the FD-SOI name. The concept of full depletion has been long known, already at the time of the SOS (1970s) and SIMOX (1980s) technologies [11], [12]. Numerous models and techniques of characterization have been developed [10], [13] with commitments of French researchers (CNRS, LETI). The great value of the contributions of IBM, Sematech and the SOI Consortium [14] led by Soitec is noteworthy. Following multiple technology developments and design tools in the 2000s, STMicroelectronics decided to launch its FD-SOI pipeline.

FD-SOI technology

The The SmartCut® technique (UNIBOND) is being continuously updated by SOITEC [16], the world's first SOI wafers provider. The main processing steps are shown in Fig. 1.3.

1. Formation of an oxide layer on a silicon substrate (wafer A in Figure 1.3) followed by hydrogen ions implantation.

2. Hydrophilic bonding at room temperature of wafer A to a wafer B. Both wafers are previously cleaned using a modified RCA process.

3. Two-phase treatment of the stack in order to split it into two parts at hydrogen ions level.

4. In order to get a uniform and clean surface, a final touch-polishing of SOI wafer is performed.

The typical configuration of a FD-SOI MOS transistor is shown in Fig. 1.4.

FD-SOI MOS transistor has typical characteristics and features outstanding advantages [17], [18]:

i. Ultrathin and undoped body of the transistor for better electrostatic control, reduction of shortchannel effects (SCE), and minimum subthreshold swing (SS);

ii.

Thin BOX for reduction of parasitic capacitances between source/drain contacts and the substrate;

iii.

Ground plane (N + or P + ), located under the BOX, is used as a back gate (with contact brought back to the surface); iv. Gate dielectric with high permittivity; In contrast, SOI technology presents some drawbacks such as self-heating and floating-body effects (FBE). However, the FBE is a key principle for dynamic memory applications developed in this dissertation.

Electrostatic doping vs. Physical doping

As a result of pursuing Moore's law for the last 40 years [5], major technical challenges were encountered in achieving today's small feature sizes. The number and difficulty of the technical challenges are continuing to increase. One of the important processes in device fabrication which suffers from film thinning is the doping technique. In this section, we address the conventional doping method and its limits which bring up a new doping concept: electrostatic doping.

Physical doping: Ion Implantation

Ion implantation is the introduction of dopant atoms into a substrate by bombardment with ions in the keV to MeV energy range [19]. Implantation is the most popular chemical doping method known for precise control of dose/depth profile, low-temp process, and excellent lateral dose uniformity compared to thermal diffusion, or in-situ growth of dopants. Ion implantation equipment (Fig. 2.1) [20] Figure 2.1. Schematic of ion implanter [20].

consists of a source to produce ions of the desired element, an accelerator to provide the ions with high energy, and a target chamber. Ionized particles penetrate into the target wafer upon impact after particles are accelerated by electric field and separated by magnetic field. Even though ion implantation methods have evolved following the trends in miniaturization of electronic, optoelectronic or photonic devices, with few nanometer dimensions, they reach their technical limits [21]. The non-uniform distribution of dopants or defects made during the implantation process raise the variability issue and tiny effects in bulk devices are blown out of proportion in nano-scale devices [21]- [25]. The accurate control of doping type, level, and spatial distribution in emerging materials and nanowire/tube structure are also challenged due to their complex growth mechanisms and geometrical constraints [26], [27].

Electrostatic doping

Electrostatic doping (ED) aims at replacing donor/acceptor dopant species with free electron/hole charges induced by the gates in ultrathin MOS structures. The first notion of ED was introduced within carbon nanotube (CN) diode [28] and now spreads not only to CMOS technology but also to emerging materials. The ED is a fascinating feature of FD-SOI technology. In an ultrathin SOI device, the electron population induced by a positive gate bias spreads into the entire body (volume inversion or accumulation [29]). The body behaves as an N-doped region albeit it was originally undoped. Reciprocally, negative gate bias turns the body into a P-type region. Such doping metamorphosis has already been used for conceiving novel devices containing reconfigurable P-N junctions: TFET [30], [31], GDNMOS [32], I-MOS [33]. Thyristor-like band-modulation devices, such as FED, Z 2 -FET and Z 3 -FET [34]- [38], take advantage of the action of two gates to achieve sharpswitch characteristics. A virtual diode on SOI has been proposed by Hueting et al. [39], where a fixed ED, so called plasma charge, was induced by two MOS stacks with controlled work-functions.

This thesis is dedicated to the investigation of the Hocus-Pocus (HP) diode [40] which is an advanced version of reported ED device in FD-SOI. In chapter 1, after presenting the fundamentals, we review the family of electrostatically-doped devices fabricated with emerging or mature technologies (nanowires, nanotubes, 2D materials, FD-SOI). The multiple facets of the Hocus Pocus (HP) diode are discussed by underlining the difference with classical physical diodes in chapter 2. The ED gave rise to a number of band-modulation devices with outstanding memory and sharp-switching capability. The concept, intrinsic mechanisms and typical applications are described in detail in chapter 3.

Sharp-switching devices

Low-power operation has been challenged especially after reaching CMOS downscaling limits.

The subthreshold swing (SS) is defined as the change in gate voltage (VG) required for one order change in the drain current (ID): SS ≡ dVG/dlog10(ID) [10]. In MOSFET operation, electric charges movement is controlled by a barrier from source to the channel. Only electrons with energies greater than the barrier height can contribute to the current. In the ideal case, this should change the height of the barrier by qVG. The electrons follow a Boltzmann distribution, and the current through the channel is proportional to exp(qVG/kT), where k is the Boltzmann constant and T is temperature. Thus, the VG must change by kT•ln10/q = 60 mV to modify the current by a factor of ten at room temperature.

Overcoming the non-scalability of subthreshold swing (SS) is a desperate research target for the next generation of logic switches.

We introduce sharp-switch variants which have been developed in the hope of going below 60 mV/decade swing. First approach is by modifying the carrier transport mechanism within the channel.

Tunnel FET (TFET)

TFET is a gated P + -I-N + diode [30] operating under reverse bias mode. In OFF-state (Fig. 3.1b)

where the gate voltage VG is low, there are no energy states available in the channel for band-to-band tunneling (BTBT) to occur. With sufficiently high VG, N + region is emulated under the gate (Fig. 3.1c) triggers BTBT as in a Zener diode (Fig. 3.1a). Figure 3.2 shows the transfer characteristics of N type all-Si TFET with a subthreshold swing SS = 52.8 mV/decade at low ID current [41]. Despite the enhanced SS, all-Si TFET suffer from a poor current ratio ION/IOFF. Even with a good SS achieved the best ON current is still low (46 µA/µm) in comparison with MOSFET [41], [42]. There have been attempts to increase ON current by enlarging the tunneling area and amplifying the BTBT current [43]- [45]. However, the TFET roadmap is still full of challenges and needs more convincing experimental validation.

Impact Ionization-MOSFET (I-MOS)

(a) (b)

I-MOS [46], [47] structure is similar to an asymmetric P-I-N diode partially covered by a gate (Fig. 3.3a). Without gate bias (VG = 0 V) the diode is in OFF-state featuring a fully depleted channel and low leakage current IOFF. The ON mode consists of increasing the number of holes in the channel, such as to reduce the length of the depleted region and induce avalanche breakdown. For this purpose, the gate is negatively biased and the drain is highly polarized (VD > 10 V) leading to a sharp switch ID-VG as shown in Fig. 3.3b [47]. However, the high drain bias is not suitable for practical applications.

Nano-electro-mechanical FET (NEM-FET)

Figure 3.4 shows the nanoelectromechanical FET [48], [START_REF] Akarvardar | Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logic[END_REF] where a metal gate is suspended over the oxide/semiconductor channel of a MOS transistor by an anchor. The gate insulator is air-gap instead of SiO2 in conventional MOSFET. The NEM-FET operates in enhancement-mode by biasing the front gate. The gate is pulled up in OFF-state with negative VG and down in ON-state with positive VG. Since the gate comes close to the surface, an electron channel is formed underneath. However, it requires a high gate voltage to switch ON and suffers from severe short-channel effects due to weak gate-to-channel coupling in the OFF state. In order to improve its operation, [START_REF] Kam | A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics[END_REF] proposed accumulation-mode NEM-FET where the channel is depleted when the gate is pulled down (VG < 0 V).

Competitive NEM-FETs, with nanometer-thick air-gap, have still to be demonstrated.

Ferroelectric FET (Fe-FET)

Ferroelectric material is a dielectric crystal which shows a spontaneous electric polarization; based negative capacitors is published in [START_REF] Cheng | Low-voltage steep turn-on pMOSFET using ferroelectric high-κ gate dielectric[END_REF], [START_REF] Lee | Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies[END_REF]. The SS swing of 8 mV/decade was reported with single-crystal BiFeO3 capacitor [START_REF] Khan | Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor[END_REF]. However, they suffer not only from reliability issues (cycling) but also from technical problems such as controlling ferroelectric layer thickness.

Band-modulation device (Z 2 -FET)

Perfect solution to overcome 60 mV/decade subthreshold swing in a MOSFET transistor is the band-modulation device. FD-SOI technology has allowed the recent discovery of the band-modulation devices. Z 2 -FET offers unrivalled switching capability and has a great opportunity thanks to its full compatibility with existing technology. of holes that lowers the barrier of the electrons and vice versa [66] [67]. Unlike the classical thyristor, the working principle of band-modulation devices is not based on the impact ionization. This explains the name given to the device: Z 2 -FET (zero subthreshold swing and zero impact ionization) [35]. Z 2 -FET has already been utilized for ESD protection [START_REF] Solaro | Innovative ESD protections for UTBB FD-SOI technology[END_REF], [START_REF] Solaro | Z 2 -FET: A promising FDSOI device for ESD protection[END_REF] made possible by the sharp switching characteristics. A similar band-modulation device is the field-effect diode which features two top gates [37]. A restriction of the FED is the gap between the two front-gates which affects ON current and the high frequency performance of the device.

Other applications of the Z 2 -FET as capacitorless 1T-DRAM and sharp logic switch will be investigated in chapter 3 where the operation principles and detailed device physics are discussed in details.

1T-DRAM: Capacitorless Dynamic Random Access Memory

State-of-the art: the need for new memory for Internet of Things (IoT)

The Internet of Things (IoT) technology [57] is now an ubiquitous concept for interconnection

Conventional 1T+1C DRAM

Traditional Dynamic Random Access Memory (DRAM) consists of one access MOS transistor and a storage capacitor where the information is saved in form of charges. There have been lots of attempts for the scaling of the transistor and the implementation of new material/structure for capacitor in response to the aggressive scale-down. The downscaling of memory elementary cell is still going on.

However, difficulties related to process integration of both capacitance and access transistor are becoming insoluble. Especially for the integration in IoT devices, embedding 1T+1C cells inside the chips is paramount challenge. For this purpose, breakthrough architectures without external storage capacitor as alternatives to conventional DRAM memories draw keen attention.

Resistive RAM (ReRAM)

Spin Torque Transfer-RAM (STT-RAM)

STT-RAM has become a leading candidate for future massive implementation. The principle of operation is somehow similar to that of resistive junctions (switching back and forth between highresistance and low-resistance states, Fig. 4.2), but instead of using a dielectric material, it is based on a Magnetic Tunneling Junction (MTJ) [START_REF] Ohno | Magnetic Tunnel Junctions for Spintronic Memories and Beyond[END_REF], [START_REF] Mahmoudi | Design and applications of magnetic tunnel junction based logic circuits[END_REF]. The MTJ is stable, the memory is non-volatile and requires no refreshing. The drawback, however, is the complexity of materials needed to form the MTJ.

The device is more expensive and there are scalability issue due to the multiple structure compared to ReRAM. Both ReRAMs and STT-RAMs have already demonstrated their potential in terms of energy

(a) (b)

(~pJ) and speed. Despite their promising potential, there is an insurmountable blockage for both approaches: the cost for additional process steps and special materials to be acceptable in CMOS. Thus, it seems that ReRAMs and STT-RAMs are for the future storage-class memory rather than for the embedded cache memory.

Floating-Body DRAMs (FB-DRAMs)

The concept of single-transistor DRAM (1T-DRAM) came out more than 20 years ago [START_REF] Wann | A capacitorless DRAM cell on SOI substrate[END_REF] and many enthusiastic variants have since been proposed [35], [36], [START_REF] Tanaka | Scalability study on a capacitorless 1T-DRAM from single-gate PD-SOI to double-gate FinDRAM[END_REF]- [START_REF] Song | 55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure[END_REF]. In general, 1T-DRAMs take advantage of the floating-body effects that were usually regarded as parasitic and detrimental. In '1'-state, excess majority carriers (holes) are stored in the body and increase the potential, lower the threshold voltage and yield high current. State-'0' features lower current achieved by removing the holes from the body.

However, 1T-DRAMs have not yet reached the market for two main reasons:

-Conventional DRAMs were pacing successfully and there was no emergency for replacement.

-None of the 1T-DRAM versions was entirely convincing. Either the writing mechanisms were too demanding in power/voltage/reliability or the device compatibility with standard FD-SOI process was limited.

Here we describe three main variants and compare their operation mechanisms.

Meta-Stable DRAM (MSDRAM)

MSDRAM is a 1T-DRAM [START_REF] Bawedin | A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation[END_REF] based on Meta-Stable-Dip (MSD) effect where the dynamic coupling between front and back interfaces gives rise to a hysteresis in ID-VG characteristics. The frontgate voltage VG1 is swept from 'accumulation' to 'depletion' and vice-versa, and the difference in frontsurface potential is reflected, by coupling effect, in the back-channel current which is monitored. The '0'-state corresponds to the case where both interfaces are in depletion and the OFF-current is small. In '0'-state, the system is in non-equilibrium deep-depletion because there are no holes available. Thus, it requires 'refresh'. The '1'-state, defined when an inversion channel is formed at the back interface, is programmed by band-to-band generation at very negative front-gate voltage. The '1'-state does not require 'refresh' since accumulation of hole guarantees the equilibrium state. By applying a low VD within the memory window (Fig. 4.3), the '0' and '1'-state can be read. Relatively thick MSDRAMs feature wide memory window (hysteresis), high memory margin I1/I0 and seconds-long retention. The fatal issue is film thinning used in advanced FD-SOI technology [START_REF] Cristoloveanu | Evidence of Supercoupling Effect in Ultrathin Silicon Layers Using a Four -Gate MOSFET[END_REF]. Below 10 nm, the supercoupling effect denies the co-existence of electron and hole channels facing each-other. The MSD effect vanishes because the electron channel is needed to read the memory state, while the hole channel serves for charge storage.

A2RAM

A2RAM [START_REF] Rodriguez | Novel capacitorless 1T-DRAM cell for 22-nm node compatible with bulk and SOI substrates[END_REF], an advanced version of ARAM [START_REF] Rodriguez | A-RAM memory cell: Concept and operation[END_REF], features the same operating principle as MSDRAM, except that the bridge where the electrons are physically-doped is realized by epitaxy or ion implementation, unlike the MSDRAM where the channel is electrostatically-charged by the backgate bias. The A2RAM features direct compatibility with SOI and bulk substrates without changes in design, whereas most of other FB-DRAMs cells are tied to SOI substrates or require major modifications to bulk technology. A negative gate bias is applied to accumulate holes at the top interface; the presence of this accumulated charge defines the '1'-state bit (Fig. 4.4a). Under these circumstances, the gate electric field is screened by the accumulated charge and the carrier concentration in the N-Bridge is hardly affected by the gate bias. The electron concentration in the N-Bridge corresponds to the doping level leading to a current flow between source and drain (state '1', Fig. 4.4b). If holes are temporarily removed from the top interface, while negative gate bias is maintained, the gate-induced field is no longer screened, affecting the electron concentration of the N-Bridge (Fig. 4.4c). The N-Bridge will become fully depleted, therefore preventing any current flow between source and drain

Z 2 -RAM (Z 2 -FET RAM)

Z 2 -FET [35], unlike MSDRAM and A2RAM, is free from supercoupling effect and technological process constraints. The device has been already presented in section 3.5 and will be investigated in details in chapter 3 as a capacitorless 1T-DRAM. The Z 2 -FET (Fig. 3.6) operation is similar to a TFET but operated in forward-bias mode. Electrostatic barriers are formed, via gate disposition and biasing, to prevent electron/hole injection into the channel until the gate or drain bias reaches a turn-on value. The front and back gates induce electrostatic doping in the undoped body so the device looks like a N + PNP + thyristor, although the mechanisms of operation differ [28]. The gate action leads to band modulation along the channel that blocks the current flow. A positive feedback mechanism between the electron and hole injection barriers causes the device to abruptly switch (< 1 mV/decade) from OFF '0'-state with low leakage current to ON '1'-state with high drive current. The output I-V characteristics exhibit a large hysteresis useful for single-transistor memory. In chapter 3, the difference between the various modes of operation (steady-state, transient and memory) will be outlined. We will present experimental results and discuss the device physics, architecture, and performance of the Z 2 -FET.

•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.2. Electrostatic doping ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.3. Why electrostatic doping? ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.3.1. Semiconductor technology ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.3.2. Electrostatic doping in FD-SOI technology ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.4. Emerging material devices with electrostatic doping ••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.4.1. Carbon nanotube ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.4.2. Graphene •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.4.3. Silicon (Si) nanowires ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.4.4. Two Dimensional (2D) materials •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.5. FD-SOI devices with electrostatic doping •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.5.1. Tunneling Field Effect Transistor (TFET) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.5.2. Lateral Double-diffused Metal Oxide Silicon (LDMOS) •••••••••••••••••••••••••••••••••••••••• 1.5.3. Impact ionization Metal Oxide Silicon (IMOS) ••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.5.4. Gated Diode merged NMOS (GDNMOS) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.5.5. Charge Plasma Diode •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.5.6. Bipolar Charge Plasma Transistor ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.6. Conclusion •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.7. References ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1.1

. Introduction

In this chapter, the concept of electrostatic doping and different variants of electrostaticallydoped devices are presented. Here, electrostatic doping implies replacing donor/acceptor dopant with free electron/hole charges induced by the gates in ultrathin layers. The role of electrostatic doping in semiconductor technology is highlighted. After presenting the basic concepts and fundamentals, the family of electrostatically-doped devices fabricated with emerging or mature technologies are discussed:

nanowires, nanotubes, two-dimensional (2D) materials, FD-SOI, etc.

Electrostatic doping

The 'electrostatic doping' refers to the gate-induced free carriers in nano-size structures:

nanotubes, nanowire, 2D materials and fully depleted silicon-on-insulator (FD-SOI). Thanks to the volume inversion/accumulation [1], electron or hole charges spreads in the body entirely. In bulk semiconductor or thick layer however, it is impossible to have such effect because gate-induced charges form a layer only at the interface of the device body. The concept of 'electrostatic doping' in ultrathin layer can be understood by simple schematics. A standard P-N diode with physical doping performed by ion implantation, thermal diffusion, or in-situ growth of dopants is shown in Fig. 1.1a. In Fig. 1.1.b, we consider a semiconductor layer only with ohmic-contacts at each terminal which is not a diode. Even though top and bottom MOS gates are included as shown in Fig. 1.1c, the device cannot be called as a diode. However, the free electrons and holes can be induced via two front-and back-gates forming a virtual P-N diode (Fig. The 'electrostatic doping' is basically an extension of volume inversion/accumulation which is different from the interface charge (inversion layer or 2D gas). The gate-controlled diode [2] does not belong to the electrostatically-doped devices. This diode is formed in bulk semiconductor with a P-N junction between a physically-doped region and an inversion layer confined at the interface rather than extending down at the end of the body. The N-or P-type electrostatic doping occurs in thin layers and has a gate bias dependence. The thinner the film, the more uniform the carrier distribution in the layer.

In addition, doping concentration is reconfigurable at demand. The fascinating aspect of electrostatic doping is the possibility to emulate junctions, out of nothing, in a body that was initially undoped or even fully depleted.

The first notion of 'electrostatic doping' was introduced in 1999 by Antonov and Johnson [3] for carbon nanotube (CN) diode. By controlling the electrostatic doping of the CN diode body, they obtained the behavior of diode current. After then, 'electrostatic doping' has been utilized in graphene and nanotube devices for improved end contacts [4]- [7]. The charge plasma diode by Heuting et al. [8] adopted 'electrostatic doping' as gate-induced doping. Also, Allibert et al. [9] reinforced the performance of the device with electrostatic doping by lowering series resistance as a result of backgate extension underneath the source and drain terminals.

In section 1.3, we review the state of the art electrostatic devices: applications in nanowires, 2D materials and fully-depleted SOI (FD-SOI). The operation and performance of band-modulation devices for applications in the domains of memory, electrostatic protection (ESD), fast logic and sensing are also described.

Why electrostatic doping? 1.3.1. Semiconductor technology

Since the invention of the integrated-circuit (IC) technology more than 40 years ago, there has been tremendous and continuous progress in development of the IC technology [10]. The most remarkable characteristic was that the geometric size of the transistors was scaled down by Moore's Law [11] every 12-18 months. Now, the system enabled by Moore's scaling is increasingly challenged due to the skyrocketed demand for high performance devices. As the device shrinks, more complex the fabrication process becomes. For this reason, scaling has been slowed down recently in terms of the gate length, mainly due to the complexity of the doping profile control, etc. The 10 nm node process technology based on FinFET transistors with a 30-40 nm fin pitches was introduced in 2017. Now, three main semiconductor industries (Intel, Samsung and TSMC) are currently working on 7 nm technology node [12]. Significant challenges need to be overcome to continue the historical trend. Doping by ion implantation, thermal diffusion, or in-situ growth of dopants has been a key process in development of today's semiconductor technologies [10]. However, with few nanometer dimensions of devices, the conventional doping technology reaches their technical limits. In shallow and narrow junction, the formation of abrupt junction which is necessary to reduce the sheet resistance and leakage current is practically difficult [13]. Damage and defects generated during the implantation for S/D fabrication may cause different doping profiles after anneal cycles, and lead to different final junction profiles [14]. As a result, the downscaling of transistor dimensions brings out variability issues since inconsistent dopant distribution for each transistor results in a corresponding doping fluctuation from device to device. This variability mainly causes a shift of the threshold voltage which is severe problem in circuit design [15].

Doping nano-scale devices with emerging materials and architecture such as nanowire, nanotube, etc. is another challenge in terms of doping type, level and distribution control because the dynamics of such structure growth is complex [16]. Nanowires and nanotubes grown vertically on the substrate have doping profiles which are defined vertically in contrast to traditional planar devices. This vertical geometry poses special challenges for diffusion and ion implantation which are the two currently dominating doping methods for planar devices. To overcome the limitations of chemical doping in nano-scale semiconductor devices, electrostatic doping is a broadly investigated alternative to provide regions with a high electron or hole density.

Electrostatic doping in FD-SOI technology

The band-modulation devices in FD-SOI technology draw attention especially due to their superior sharp switching capability [17] and possible application for the memory [18]. The key mechanism for the band-modulation principle is based on the electrostatic doping adjusted by the gates bias. FD-SOI devices feature ultrathin silicon layer which is essential for the volume inversion of the where half of the body is controlled by the separate back-gates is a possible option in standard FD-SOI technology. The front-gate can be removed and there is possibility to be used for photonic application (Fig. 1.4c) with simplified fabrication process. Electrostatic doping in FD-SOI devices is interesting with their modifiability in terms of number of the gates and applications with CMOS compatibility.

Hueting et al. [19] presented the theory of electrostatic doping induced by metal work-function or gate bias as well as the physics of Schottky-barrier devices, including their charge plasma diode [8].

The role of electrostatic doping in TFETs and reconfigurable multi-gate MOSFETs is discussed by Knoch et al. [15]. In section 1.5, we review the state of the art of electrostatic devices from a different angle: alternative devices fabricated on FD-SOI (LDMOS, IMOS, etc.) with special interest for virtual diodes and band-modulation transistors. Chapter 2 deals with the properties and metamorphosis of the Hocus-Pocus diode and chapter 3 describes the operation and performance of band-modulation devices for applications in the domains of memory and logic switch.

Emerging material devices with electrostatic doping 1.4.1. Carbon nanotubes

The carbon nanotube P-N junction was experimentally demonstrated [7] with two buried gates as depicted in Fig. 1.5a. By biasing the gates negatively, hole conducting channel is established above the gate. On the other hand, the electron conduction channel is constructed from the positive gate bias.

When the two gates are negatively and positively biased, a P-N junction is formed along a single nanotube by electrostatic doping. The diode characteristics show forward conduction and rectification in reverse mode. For low bias conditions, the characteristics follow the ideal diode equation with an ideality factor ~1 [7].

Another set of nanotube devices with Schottky contact is illustrated in Fig. 1.5b. The Si substrate was used as back-gate VGB and two metal electrodes are deposited for source and drain terminals [3]- [5]. The negative VGB leads to an accumulation of holes and an increasing conductance of the nanotube, while the positive VGB makes the holes depleted, and yields a lower conductance. Here, the nanotube diameter is so small (~ 1.4 nm) that the accumulation charges are formed in bulk not in 2D as in a regular MOSFET. The notion of 'electrostatic doping' is actually applied to nanotube before being extended to other thicker structures [3]. Unlike the pseudo-MOSFET with pressure-induced ohmic contacts [20], the carbon nanotube FET deals with Schottky barriers which are responsible for high leakage current in OFF state. Bachtold et al. [6] successfully demonstrated logic circuits with carbon nanotube transistors. The local metal gate is insulated from the nanotube by a gate oxide layer of only a few nanometers thickness which enables strong electrostatic doping of the nanotube with gate capacitive coupling (Fig. 1.5c). The local-gate layout allows integration of multiple devices such as inverter, a logic NOR, a static random-access memory cell, and an AC ring oscillator for digital logic operations.

Graphene

Silicon (Si) nanowires

Si nanowire based Schottky barrier FET was proposed by Koo et al. [22]. The schematic of the device including Schottky contacts with Si nanowire is drawn in Fig. 1.7a. Depending on the bottom back-gate bias, the device shows ambipolar characteristics with both N-and P-type conduction according to the electrostatic doping type in nanowire. Hence, this 'top-down' Si nanowire process is free from reliability issue with doping level control and contact properties in nanowire. Fig. 1.7b [23] is an evolved configuration with additional top control gate on the Si nanowire. It operates very much as a pseudo-MOSFET [20]. The ambipolar characteristics can be suppressed and conduction of the channel is controlled by the additional gate while the back gate defines the polarity of the conduction.

There have been several attempts to operate the devices at low voltage by replacing back-gate with two additional front gates as shown in Fig. 1.8a [24]. Two programming gates on top of the Schottky junctions are added. The central gate is called 'control' gate (CG) which manipulates the current density and 'program' gates control the Schottky barriers. Simulation results demonstrate proposed device possesses a degree of freedom for both low-power and high performance switching applications. Zhang et al. [25] have successfully demonstrated reconfigurable Si transistor comprising 4 stacked nanowires. The N-and P-MOSFET configuration can be chosen at demand with three independent gate-all-around gates (Fig. 1.8b). Unlike conventional threshold voltage modulation devices, the control is achieved by modulating potential barriers at the source/drain interfaces and in the channel without trade-off between ON/OFF current. Furthermore, if the two side 'program' gates are oppositely biased, the device can be operated as a P-I-N diode or TFET. However, this triple-gate implementation may restrict the downscaling of the channel length and the high-frequency performance due to inter-gate parasitic capacitance.

Reconfigurable Si nanowire device with only two electrodes was introduced by Heinzig et al. [26]. The gate on the source interface controls the amount of injected carriers while the drain gate filters the type of carriers allowed to pass (Fig. 1.8c). Typical characteristics of N-channel and P-channel MOSFETs were measured for positive or negative PG-gate bias, respectively. This nano-transistor helps to realize a simple and compact hardware platform for logic computations yielding high flexibility in circuit design.

Two dimensional (2D) materials

Ilatikhameneh et al. [27] recently reported the performance of tunnel field-effect transistors

FD-SOI devices with electrostatic doping

Electrostatic doping is a key mechanism in number of FD-SOI band-modulation devices with outstanding memory and sharp-switching capability. In this section, we highlight alternative devices fabricated on FD-SOI with special interest for TFET, LDMOS and charge plasma diode.

Tunneling Field Effect Transistors (TFETs)

Tunneling FETs (TFET) have been intensively investigated for future logic circuits with low voltage operation (VG < 0.5 V) and reduced stand-by power consumption. TFETs function when the band-to-band tunneling (BTBT) occurs by the gate bias. The P-channel TFET structure is P-I-N diode with the gate on top of the intrinsic body (Fig. 1.10a). In OFF state with no gate bias, the BTBT cannot be triggered. The distance between P + and N + contacts is so large that tunneling of electrons from the valence band of P + region into the conduction band of N + region is unfeasible. The tunneling mechanism relies on the 'electrostatic doping'. In ON-state (Fig. 1.10b), the gate is biased negatively and induces P * electrostatic doping which extends the P + contact close to N + junction. Now, electron can tunnel through the narrow band. The BTBT current is not limited by the thermal Maxwell-Boltzmann tail of carriers (thermionic limit) as in MOSFETs. The subthreshold swing is less than 60 mV/decade in theory at room temperature which enables low power conduction. The N-channel TFET is operated in the same structure with positive bias on the source terminal and the gate.

V GF (V) V GB = 10 V V GF V GB
the bi-layers of electrons and holes. For the vertical tunneling to occur, the two bilayers need to be in proximity.

However, the coexistence of electron and hole layers stacked on each other is not happening in less than 10 nm thick films because one type of carriers displaces the other [33]- [35]. Supercoupling was demonstrated experimentally using an ultra-thin G 4 -FET transistor (Fig. 1.12) [35], with N + contacts (source and drain) and P + body contacts. It makes it possible to measure simultaneously the current of electrons circulating between the contacts N + and the current of the holes between the contacts P + . In Fig. 1.12, the back-gate voltage, VGB = +10 V, is set to induce an electron channel at the film-BOX interface. However, as soon as the gate voltage becomes negative and causes a channel of holes to appear at the upper interface, the electron channel disappears. There is no longer a region where the two channels coexist, as was the case in thicker transistors. The failure of the EHB concept reveals one limit of electrostatic doping.

One solution for improving the ON current is amplifying the small BTBT current. The Bipolar-Enhanced Tunneling FET (BET-FET) is a bipolar transistor where the base is partially covered by the gate (Fig. 1.13a) [36]. An electrostatically doped P * region is formed underneath the gate with negative bias. The BTBT tunneling occurs at the P * -N + collector junction and the electrons are aspired by the

Lateral double-diffused Metal Oxide Silicon (LDMOS)

LDMOS is a transistor with long underlapped lightly doped N drift region and P doped body (Fig. 1.14a). The drift region has the pivotal role of enhancing the break down voltage which is aimed for power management, USB ports, etc. [38]. Without doping, the device fails because the drift region is fully depleted and impedes the current flow. The doping control done by ion implantation is very difficult in sub-10 nm thick films. Therefore, LDMOS takes advantage of electrostatic doping. Figure 1.14b shows an advanced LDMOS with double ground-plane (DGP) which is available in standard FD-SOI technology. The role of the N-doped GP is to adjust the electrostatic doping of the drift region.

Depending on the target performance such as series resistance, drive current, ON (output) resistance and breakdown voltage, the doping can be controlled. On the other hand, the P-doped GP located under the gated region serves for tuning the threshold voltage, leakage current and subthreshold swing.

Impact ionization Metal Oxide Silicon (IMOS)

The IMOS is a P-I-N diode (Fig. 1.15) with partially covered gate operated at high reverse drain voltage. In OFF state (VGF = 0), the body is fully depleted and the N + and P + terminals are too far apart for the impact ionization to occur. When the front-gate is negatively biased, the P * electrostatic doping builds up underneath the gate. As a result, the P + terminal extends virtually approaching the N + terminal. Then, the device becomes short bodied P-I-N diode where the lateral electric field suddenly increases.

The impact ionization is triggered and the device turns ON. The measured transfer characteristics are indeed very sharp (~2 mV/decade) [39]. However, there are two main reasons that the IMOS is not suitable for low-power sharp-switching CMOS: (i) the drain voltage needed for the impact ionization to take place is excessively large (~10 V) and (ii) the device is prone to the early aging from the high electric field.

Gated Diode merged NMOS (GDNMOS)

A novel device named GDNMOS (Fig. 1.16) comprises a gated-diode and a MOSFET sharing the N + middle contact. The electrostatic doping enables the device to operate in two different configurations. The N * doping under the transistor gate results in a lateral P-I-N diode whereas P * doping transforms it into a thyristor [40]. In thyristor configuration (Fig. 1.16), it shows high breakdown voltage and latch up free behavior which is suitable for ESD application. Note that the common N + region can also be electrostatically doped (by ground plane or an additional top gate), leaving more room for flexible operation.

Charge Plasma (CP) diode

The charge plasma diode (Fig. 1.17a) features a P-N junction formed by work-function induced electrostatic doping [8], [41]. Two separate metallic gates are sputtered on top of a SOI film and are isolated from the top of the body by a dielectric layer. Two different metals that serve as ohmic contacts extend on top of the dielectric layer. Depending on the selected work-function of the deposited metals, electrostatically doped N * and P * regions are defined with constant concentrations of electrons and holes.

The I-V characteristics (Fig. 1.17b) are diode-like with high ON/OFF ratio depending on the metals combination [8], [19]. In chapter 2, our Hocus-Pocus diode, the upgraded version of the charge plasma 54 diode, will be discussed in detail.

Bipolar Charge Plasma transistor

The charge plasma diode concept has been extended to design a lateral BJT device. Kumar and Nadda [42] proposed and investigated the charge plasma based lateral BJT by replacing the doped emitter, base, and collector regions of a conventional bipolar device with electrostatic doping regions using metals with different work-functions as shown in Fig. 1.18. The metals at extremities are selected to create N * emitter and collector regions whereas a third metal gate serves as contact to the P-type base.

Simulation results show I-V curves similar to a conventional BJT with high current gain.

Conclusion

The electrostatic doping gives a tremendous opportunity in ultrathin structures, either planar

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(FD-SOI, 2D materials, nanotubes) or vertical (bottom-up nanowires, FinFETs, etc.). Well-known devices such as diodes, MOSFETs and bipolar transistors can be reproduced by replacing the physical doping with gate-induced electron and hole charges. A unique benefit is the possibility to create N + and P + terminals even in materials where the chemical doping techniques could not be applied. It is very interesting that the manipulation of the doping polarity and concentration in the same body region is possible.

The ultimate advantage of electrostatic doping is for conceiving new types of devices with enriched performance and functionality useful in reconfigurable integrated circuits. The bandmodulation concept is actually the fruit of electrostatic doping. We have reviewed several variants of prototypes with FD-SOI technology; the devices show enriched performance thanks to the electrostatic doping as will be discussed in the following chapters.

Other innovative devices, where P-N virtual junctions are emulated or abolished to match userdefined specifications, will certainly be conceived soon. Given the enormous potential of electrostatically-doped devices, their dedicated modeling is a need. The challenge is to account for gatetunable doping with 2D or 3D profile and dynamic variation. Whether billions of minuscule gates will terminate the dinosaur-like ion-implanters is a question to be contemplated in the future.

Introduction

In this chapter, the Hocus-Pocus (HP) diode, an electrostatically doped diode which can emulate various configurations of virtual diodes and band modulation devices, is presented. The device fabrication and the general principle of operation are investigated in the context of 28 nm FD-SOI technology. The virtual P-N diodes are formed by appropriately biasing the front and back gates of an undoped body. Systematic current-voltage I-V characteristics are shown revealing similarities and major differences with those of conventional physically doped P-N diodes. In addition, Esaki-diode characteristics are observed in low temperature measurement with the virtual P-N diode configuration.

TCAD simulation was performed for the verification of the device operation. Not only the characteristics of P-N and P-I-N diodes are demonstrated but also the characteristics of the bandmodulation devices such as TFET and Z 2 -FET are discussed. Extraction methods of the carrier lifetime, which is one of the most important parameter in device operation, are proposed for ultrathin film by using the HP diode.

The Hocus-Pocus (HP) diode

Device fabrication

The Hocus-Pocus diode (see Fig. gate leakage. It is connected via a mid-gap metal layer (TiN or AlTiN) with a low resistance poly-Si electrode. The thicknesses of Si film and buried oxide (BOX) are 7 nm and 25 nm, respectively. The Si body is undoped fully depleted film (residual doping NA = 10 15 cm -3 ). To reduce series resistance, highly doped N + and P + terminals (~ 10 20 cm -3 ) were formed by epitaxial regrowth and two-step ion implantation. In situ Si epitaxy was also done on the ungated body region (Lin). A highly doped P-type ground plane (NA = 10 18 cm -3 ) separated by the BOX acts as a back-gate and prevents depletion in the substrate. The measured devices are relatively long diodes with equal length of gated region (Lg) and ungated region (Lg = Lin = 500 nm).

The reverse and forward current for different combinations of front-gate and back-gate biases

are measured with Agilent B1500A semiconductor device analyzer. The N + cathode contact is grounded (VK = 0) and the voltage VA is applied to the P + anode (Only in section 2.3.3, VA = 0 and VK is swept).

The current compliance was set at 10 mA to avoid device damage. All measurements were conducted at room temperature except in section 2.3.6 (low temperature measurement, down to 77 K).

Principle of operation

The Hocus-Pocus (HP) diode is basically a P-I-N diode (configuration E in Fig. 2.2) without gate bias (VGF = VGB = 0). Note that "i" is for nearly intrinsic silicon film. The virtual electrostatic doping in the gated and ungated regions is induced according to the front-gate (VGF) and the back-gate modify the characteristics. In the following, the reverse and forward characteristics of the diode are examined and distinct characteristics of HP diode are discussed in more detail.

Reverse current characteristics

In a classic P-N diode, the reverse current is governed by carrier generation and diffusion mechanisms [6]. The generation current Ig depends on the width of lateral space charge region WD, intrinsic carrier concentration ni, carrier lifetime τg and junction area Aj:

I g = q•W D •n i 2•τ g • A j (2.1)
Ig increases with negative bias applied to anode VR as a result of the expansion of WD. In long diodes, the diffusion current is given:

I d = q • n i 2 • ( D n N A •L n + D p N D •L p ) • A j (2.2)
where Dn,p and Ln,p are diffusion coefficients and diffusion lengths for electrons and holes. In very short 67 diodes, Ln,p can be replaced by gate lengths Lg and Lin. In our HP diode, the diffusion lengths and the body lengths are comparable, so Eq. (2.2) is rewritten as [7]:

I d = q • n i 2 • ( D n N A •L n •tanh W p L n + D p N D •L p •tanh W n L p ) • A j (2.3)



Both the WD and Id depend on the physical doping concentrations NA,D. In our diode, the average virtual doping of N * -side is expressed by the conventional MOS theory:

N * = C BOX •(V GB -V tb,n ) q•t Si (2.4)
where Vtb,n is the threshold voltage for the back electron channel. The calculation of the virtual doping of the P * -side under the front-gate is complex for two reasons:

(i)

The field induced from the anode contact reduces the effective front-gate voltage to VGF -VR under the gate region. The anode P + terminal acts as a body contact and the virtual doping decreases with increasing |VR| until the region under the gate becomes fully depleted.

At this point, the body contact is no longer efficient, even further increase of VR will not modify the surface potential of the body. For VGF < 0, the body is either P-type or fully depleted. Even for reverse anode bias exceeding VGF (i.e., |VR| > |VGF|), doping type does not change from P-type to N-type.

(ii)

The positive back-gate bias increases the threshold voltage Vtf,p of the front hole channel.

According to the coupling model [8], ΔVtf,p ≈ 𝑡 𝑂𝑋 𝑡 𝐵𝑂𝑋 •ΔVGB. For example in our HP diode, VGB = +10 V increases Vtf,p by more than 1 V, diminishing the hole carrier concentration under the front-gate. Note that this coupling effect is eliminated in TCAD simulation by simplifying the device structure as shown later in Fig. 2.6a.

The average P * -type doping is evaluated as:

P * = C OX •(V GF -V tf,p ) q•t Si (2.5)
In the HP diode, the electron carrier concentration is in the range of ~ 10 19 cm -3 for VGB = +10 V. A similar concentration for holes is obtained for VGF = -2 V and VGB = 0 V.

The reverse current characteristics in Fig. 2.4 have two different behaviors. For relatively low VR, the current remains extremely low (10 -14 A/µm, close to the measurement noise level) since the P *doping under the front-gate is maintained. When VR ≈ VGF -Vtf,p, a sudden increase in current occurs because the body under the gate becomes fully depleted. Here, the device configuration changes from P-N diode (Fig. 2.2A) to fully depleted P-I-N diode (Fig. 2.2F). Holes are eliminated under the gate and their concentration P * reduces exponentially in subthreshold region. Then, the voltage drop and electric field at the central P-N junction reach maximum values; further increase in VA augments the electric field at the anode P + -body junction. In addition, massive carrier generation is triggered at the interface since the surface generation centers are no longer screened by the hole and become promptly active.

Increasing |VGF| shifts the curves proportionately to the left (Fig. 2.4a), expanding the low-leakage current region. This region is suppressed at high VGB (Fig. 2.4b,c), unless |VGF| is increased concomitantly.

Band-to-band tunneling can also explain the increase of the reverse current. As soon as the back-gate action takes over the front-gate action, electrons populate the gated region (Fig. 2.4c). Then, band-to-band tunneling can be initiated near the anode as in TFET operation, leading to a net increase in reverse current with VGB, as shown in Fig. 2.4. the electrostatic doping level.

Forward current characteristics

(iii) VA > 1 V: The current is limited by high injection and series resistance effects at high anode voltage. The ideality coefficient degrades rapidly in high injection regime.

In Fig. 2.5b, the diffusion current behavior is indicated in linear scale. It is worth noting that the forward characteristics especially the diffusion current are far less sensitive to the gate bias (i.e., virtual doping concentrations) than the reverse current. This is because the virtual diode always operates in consistent 'configuration A' in forward mode. The positive anode voltage gradually reinforces the doping under the gate, which makes a clear difference compared to the physical diode. As a result, the barrier height at the virtual junction tends to increase whereas the depletion width WD decreases as shown by simulation results in the next section.

TCAD Simulation

Sentaurus TCAD simulations [9] were performed for investigation and comparison with the experimental results. Standard simulation modules were used: doping dependent Shockley-Read-Hall (SRH) generation-recombination with the Scharfetter lifetime model [10], drift-diffusion transport using fermi statistics, and nonlocalpath band-to-band tunneling model [11]. Including the surface SRH model at the silicon/oxide interface did not bring any significant change in the gated diode behavior in such ultrathin films. Quantum confinement was assumed to have minor contribution.

We simulated a simpler virtual diode (Fig. 2.6a) with identical oxide thickness at front and back gates. Since there is no gate overlap, each gate controls exactly half of the body without affecting the vicinity of the controlled region (unlike the experimental case where VGB has an impact on the whole body).

Numerical simulations provide the 2D carrier profiles of the virtual P-N diode as shown in Fig. 2.6a. The hole carrier concentration P * decreases downward from the front-gate whereas the electron concentration N * decreases upwards from the back-gate. The key consequence of vertical carrier profiles is an in-depth variation of the depletion width. According to [12], the boundary (black dotted lines) of the space charge region is defined by the point where the carrier concentration drops to half the equilibrium value far from the junction, at same depth. On either side of the junction, the space charge region extends from 1 nm in the highly doped section (~10 19 cm -3 ) to 10 nm in the lowly doped section with ~10 17 cm -3 . These values roughly match the 1D model. The highly inhomogeneous distribution of the space charge affects the validity of Eq. 2.1, same as the vertical carrier profiles do for the diffusion current Eq. 2.3. Further results also indicate that the barrier height at each position is given by the classical theory: ΦB = kT/q•ln•(N * P * /ni 2 ), where the free carrier concentrations N * and P * replace the physical doping.

Figure 2.6b shows the forward and reverse characteristics which reproduce qualitatively the experimental trends showing the typical diode regions governed by carrier generation and tunneling in reverse mode and by recombination and diffusion in forward mode. The ideality factor varies from 2 to 1 (Fig. 2.6c), confirming that the virtual P-N diode features rather conventional forward characteristics.

At high positive bias, the ideality factor degrades as a result of high injection and series resistance effects.

Asymmetric characteristics

In a standard diode, the current-voltage characteristics are identical for both anode and cathode biasing. However, the HP diode features different characteristics according to the grounded terminal.

The reason is that the concentration of the gate-induced charge is modified dynamically by the bias as illustrated in Fig. 2.7a. For example, P * concentration increases with VA in forward mode and decreases in reverse mode. In contrast, since VK = 0, the effective back-gate voltage is rather constant and the N * doping is hardly affected. Reciprocally, when the anode is grounded, the N * concentration is altered by the cathode bias whereas the P * doping is maintained constant. Figure 2.7b,c show that the I-V curves are more asymmetrical in reverse mode.

Semi-virtual P-N diode

The HP diode can emulate semi-virtual diodes where the junction is located at one of the terminals. Positive front-and back-gate bias shifts the P-N junction from center towards in-between the P + terminal and the N * -type body (Fig. 2.8c). Here the junction is physically defined by the P + implanted anode contact, whereas the N * region is still virtually doped. The front-gate bias has a primary role which governs the virtual doping at the junction. The back-gate bias modulates the series resistance. Fig. 2.8 shows I-V forward characteristics of the full virtual and semi-virtual diodes. The reverse current for diode (C) is 4 orders of magnitude higher than in the virtual diode (a). This difference is due to the working principle in configuration 2.8c where the diode in reverse sweep mode is actually an N-channel TFET [13]: Band-to-band tunneling (BTBT) occurs at the junction and increases substantially the reverse current.

The left-sided semi-virtual diode where the junction is shifted to the N + cathode terminal is shown in Fig. 2.8b. The body is P * -type doped thanks to the negative bias on both gates. The forward characteristics of diodes (b) and (c) are qualitatively similar; small quantitative differences shed light on the quality of the N + and P + junction. In Fig. 2.8, diode (b) shows much smaller reverse current. This result indicates a significantly lower BTBT rate at the N + terminal. Indeed, diode (b) can be considered as a P-channel TFET controlled by the back gate. Due to the difference in thickness of front and back oxides, the electric field induced by the back gate at the bottom left of the body is weaker than the frontgate field at the upper right corner of body (c). Increasing further the back-gate voltage causes an exponential rise of the reverse current.

Esaki diode characteristics

Following the discovery of the Esaki tunnel diode, with negative differential resistance (NDR) in forward direction [14], many attempts [15]- [19] were made in various materials to improve the performance. The fabrication constraints are crystal perfection and fine control of doping profile and concentration in order to enable inter-band tunneling. In III-V compounds, the lattice mismatch (and associated dislocations), impurity scattering, polarization charges, and instability of space charge adversely affect the Esaki diode operation [15], [16]. Schmid et al. [17] have succeeded to fabricate Si nanowire Esaki diodes with remarkable performance; the processing, based on vapor-liquid-solid growth on degenerated Si wafer is, however, rather complex.

In this section, we reveal for the first time, a surprising doping-free Esaki diode. We use a pragmatic approach based on commercially-available FD-SOI technology with ultrathin and undoped Si film. Instead of high-dose dopant implantation, which would generate crystal defects, we use MOS gates (HP diode). The front gate is negatively biased to induce a hole channel, whereas the positive back-gate voltage attracts electrons. Direct tunneling takes place from the degenerate conduction band into the empty part of the valence band (reciprocal Zener effect) [1]. The primary conditions for interband tunneling are favorable band alignment, achieved through high doping levels, and narrow tunneling barrier. In a relatively thick SOI layer (> 20 nm), each gate induces a 2D gas confined at the corresponding interface. The killing problem is that the distance between the front hole channel and the back electron channel is too long for tunneling to occur [20]. This disqualifies the use of electron and hole bi-layers facing each other vertically.

Ultrathin films have distinct merits:

(i) The gate-induced carriers spread in the whole body, from one interface to the other, according to the principle of volume inversion [21] or accumulation. The concentration of free carriers (P * or N * ) is referred to as 'electrostatic' doping [2]. We have already seen that a virtual Hocus-Pocus P-N junction, can be emulated in the middle of the undoped body (Fig. 2.2A). Instead of the vertical stack of electron and hole layers which is ineffective, we use the lateral proximity of P * and N * regions.

(ii) The tunneling distance across the junction, or even diagonally between the 'interface' channels, is short (10 nm or less).

(iii) Unlike the Esaki diode with fixed physical doping, the HP diode is infinitely reconfigurable via gate-adjustable electrostatic doping.

We explore the properties of such electrostatic Esaki diodes by systematic measurements and simulations. The length of gated (P * ) and ungated (N * ) HP diode regions is 300 nm and the body width is 500 nm. The P + anode contact is grounded for gate dielectric protection against overvoltage (|VGF| + VA). The current is monitored as a function of cathode voltage (VK < 0) for variable gate voltages. The measurements were performed with SUSS Microtec cryoprober (Fig. 2.9) from room temperature down to 77 K.

The negative front-gate bias (VGF = -1.4 V) induces electrostatic P * doping under the gate and the positive back-gate bias (VGB = +10 V) fills the ungated region with N * virtual doping. Given the overlapping of the gates, a sharp virtual P * -N * junction (Fig. The NDR region is modulated by the front and back gates. Figure 2.11 shows the impact of relatively low front-gate voltage. The maximum PVCR is obtained at VGF = -1.4 V (for VGB = +10 V) and diminishes for lower gate bias (VGF = -1 and -0.6 V, see Fig. 2.11b). The peak current does not change much but, for smaller VGF, it tends to appear at lower VK. When VGF is too small for sustaining a strong enough P * -doping in the virtual junction, the interband tunneling stops and the NDR becomes invisible (for VGF = -0.2 V in Fig. 2

.11b).

On the other hand, at high gate voltage (Fig. 2.12), we note the gradual modification of the NDR peak into a plateau (VGF = -1.6 V) and then a hump (VGF ~ -2 V). This 'excess' current is attributed to trap-assisted tunneling [14], [22]. Electrons can tunnel from the degenerate conduction

I A (A) V K (V) V GB = 5 V V GF = -1.4 V V GB > 0
band of N * region into empty deep traps located in the forbidden gap of P * side. Alternatively, they tunnel from filled traps of N * region gap into the valence band of P * side. The excess current is modulated by the gate voltage which modifies the position of quasi-fermi levels. In principle, the trapassisted tunneling governs the valley current [14], [22] but, in our case, the contribution of the recombination current (due to massive carrier recombination at interfaces [23] ) can also be invoked.

Figure 2.13 illustrates the back-gate effect. At low bias (VGB = +5 V), the concentration N * of free electrons is insufficient for tunneling to occur. The NDR peak observed for VGB = +10 V transforms in a hump (VGB = +15 V) showing one order of magnitude higher tunneling current. However, for higher bias (VGB = +20 V) and stronger N * concentration, the excess tunneling current decreases significantly which seems surprising. This effect results from the competition between the top and bottom gates as discussed below.

Our measurements unambiguously demonstrate that Esaki diodes can be emulated out-ofnothing in ultrathin Si layers. The virtual diode brings a paradigm shift in the family of Esaki diodes.

However, compared with physically doped 1D tunnel diodes, there are significant differences due to the special 2D configuration of the HP device: (i) The bottom gate extends all the way underneath the body, which provides sharp virtual junction but counteracts the front-gate action. Too high VGB dilutes the hole concentration P * imposed by VGF, weakening the tunneling rate, as shown in Fig. 2.13 for VGB = +20 V. This issue can be solved with the dual ground-plane structure proposed in [24], where each groundplane controls half of the body. It follows that the right-hand ground plane can be independently biased (VGB < 0) to reinforce the front-gate action instead of weakening it.

(ii) Sweeping VK increases dynamically the electron concentration N * .

(iii) The electrostatic doping is tunable, meaning that the tunneling path can be shrunk by increasing the gate bias up to the limit of oxide breakdown.

(iv) The in-depth profiles of electrostatic doping are not uniform: P * decreases downward from the front gate whereas N * increases (Fig. 2.14a). The thinner the film, the more homogeneous the carrier distributions are. It follows that the junction barrier and the depletion region (Fig.

2.14a) also vary with depth.

Sentaurus TCAD simulations [9] were performed with appropriate modules: doping-dependent Shockley-Read-Hall (SRH) generation-recombination with the Scharfetter lifetime model [10],

nonlocalpath band-to-band tunneling model [11], etc. The simulated diode has simplified configuration (Fig. 2.6a) where the front-and back-gates are symmetrical and cover half of the body each. Here, the inter-gate coupling in the gated region is eliminated for easier interpretation. The gate oxide is 3 nm and the Si film thickness is 7 nm, and the body doping is NA ~ 10 15 cm -3 . The simulations confirm that turning-off the tunneling model makes the NDR region disappear. Fig. 2.14b shows the band structure:

band alignment is favorable to tunneling at the bottom interface but not in the middle of the film where the bands do not cross.

Electron tunneling can also occur diagonally from the conduction band at the bottom of the ungated section into the valence band at the top of the gated region. Since the populations of electrons and holes are adjacent, rather than on top of each other, the Esaki diode is immune to supercoupling effect [25] which would kill the interband tunneling [20], [26].

In summary, our primary finding is the activation of Esaki NDR effect in electrostaticallydoped virtual diodes. Peak-to-valley-current-ratio above 3.5 are measured at 77 K. At room temperature, the tunneling effect is masked by the high generation current resulting from the very short carrier lifetime (~ 10 ns, dominated by interfaces). The virtual Esaki diode is very simple and fully compatible with mainstream FD-SOI technology. It is suitable for applications aiming at THz detection, oscillators and sharp-switch logic circuits in SOI platform. This device concept can be extended to nanowires and FinFETs by using two adjacent gates. However, the inherent spacing of the gates will lead to less sharp junction than in the case of FD-SOI with top and bottom gates.

The virtual P-I-N diode 2.4.1. Characteristics

A typical P-I-N diode (Fig. 2.15a) is the diode structure itself by keeping the gates grounded. In An interesting aspect is that diodes (b) and (c) also correspond to the operation of I-MOS device [28]. The I-MOS is strongly reverse-biased and the gate is scanned from zero to negative voltage. When the gated section of the body is depleted (a) in OFF state, the diode is too long to trigger impact ionization, hence the very low current flows. As soon as the virtual doping P * is consolidated (b), the effective length of the body shrinks. Then, the high impact ionization occurs due to the high lateral electric field. However, sharp switch ON is observed only at very high anode voltage (~15 V), which evokes reliability issues and disqualifies the I-MOS for low-power applications. semiconductors. It also plays a significant role in the operation of various devices: gain of bipolar transistors, leakage current in MOSFETs, switching capability of power devices, performance of photodetectors and solar cells, etc. In fully depleted SOI MOSFETs, the carrier lifetime controls the activation and amplitude of floating-body mechanisms such as kink effect, parasitic bipolar transistor, transient currents and memory mechanisms. A short lifetime impedes the accumulation of majority carriers within the body, attenuating/suppressing the floating-body effects [34], [35] for the benefit of logic CMOS. Lifetime is also of paramount relevance for the operation of SOI band-modulation devices [29], [33], [36]- [39] as it governs the sharp switching and hysteresis. Since it controls the diffusion and generation-recombination mechanisms, short lifetime increases the turn-on voltage and degrades the retention in memory application. Conversely, too long lifetime eliminates the sharp switching capability.

Many techniques have been developed to evaluate carrier lifetime in MOS devices [40]- [44].

However, measuring lifetime in ultrathin SOI films remains a technically demanding task which explains the lack of information in the literature. In section 2.6.1.1, the lifetime extraction methods in conventional thick MOS devices and their limitations are discussed in detail.

Another difficulty, from measurement viewpoint, is that the carrier effective lifetime τeff is very short in FD-SOI, being dominated by the proximity of interfaces:

1 τ eff = 1 τ v + S 1 +S 2 t Si (2.6)
where τv is the volume lifetime and S1,2 are surface generation-recombination velocities. For example, in a 10 nm thick film with reasonable interface quality (S1,2 ~ 100 cm/s), the lifetime will not exceed 10 ns.

Deep depletion techniques

In the classical Zerbst method [40], a bulk-Si MOS capacitor is pulsed into deep depletion and the capacitance return to steady state, governed by the generation of minority carriers (i.e., lifetime), is monitored versus time (Fig. 2.17a). Right after the pulse applied to the device, the bulk body experiences deep depletion with maximum space charge region and minimum capacitance. As minority carriers are being generated until the equilibrium state is reached, the carrier lifetime can be calculated from the variation in time of the capacitance.

However in ultrathin film, this technique is not valid because the depletion width exceeds over the film thickness. Similarly, the dual-gate deep-depletion technique for generation lifetime extraction was proposed by Barth and Angell [41]. As illustrated in Fig. 2.17b, the test device is a dual-gate transistor and the transient current is measured from the drain terminal while the source terminal is grounded. The front-gate is biased over the threshold voltage which results in an inversion layer at the upper surface. Then, a high negative pulse is applied from the back-gate. No holes are immediately available to form the requested accumulation channel at the back interface. The body potential drops in non-equilibrium condition which makes the front-channel inversion charge disappears completely, and the front channel will be turned off. In the absence of hole injection from either the source or drain P-N junctions, the carriers are generated by SRH process to restore equilibrium state within the transistor body. If such generation is limited to thermal generation, recovery will take a fairly long time. By modeling the time-dependent generation current, lifetime can be extracted as documented in [43], [45].

According to our experiments, in ultrathin film, this technique does not work being again restricted by supercoupling effect [25]. The coexistence of electrons and holes, necessary in this experiment, reveals impossible.

Photo-conductance decay technique

The photo-conductance decay (PCD) technique [44] was developed for measuring the carrier lifetime in 160-180 nm thick active layers of silicon-on-insulator (SOI) substrates.

The wavelength of the light source is chosen to match the absorption depth in silicon which coincides with the thickness of the active layers in the SOI wafers measured. Excess carriers injected with lamp flash and conductivity σ is measured as a function of time. This method is not effective in 10 nm thick films due to poor light absorption. governed by the diffusion of holes in the lower doped N region. Thus, Eq. 2.9 holds for P * >> N * whereas for P * ≈ N * the contributions of electrons and holes to the reverse current should be added [6], [7], [48].

We focus on the transition from recombination current to diffusion current. 85 determine the transition voltage V * , to be used in Eqs. 2.8 and 2.9, from the experimental curves at n = 1.33.

Equating Eqs. 2.8 and 2.9 yields:

L p •n i N D •tanh ( L in L p ) • exp ( V * 2kT ) = W D (2.10)
Equation 2.10 is used to determine the recombination lifetime. Numerical TCAD simulation [9] was performed for the verification of this method, in the standard P-N diodes. The I-V characteristics are traced with several lifetime values in Fig. 2.21. The corresponding transition voltage V * is taken from Fig. 2.21b and the lifetime is extracted with Eq. 2.10. The extracted recombination lifetime is compared with the input value in the simulation as shown in Table 2.1. The results are satisfactory and validate the method, at least for conventional diodes. A deviation by a factor of 2 is acceptable given the simplified form of Eq. 2.10 and the wide range of lifetime in silicon, from ns to ms.

The carrier lifetime is extracted from the experimental results shown in Fig. 2.18 where the virtual doping is high. For example, the combination of gates biases (VGF = -0.8 V, VGB = +10 V, GO1) results in average N * /P * doping concentrations of 6 × 10 18 cm -3 , leading to a depletion width of ~ 20 nm.

Since the space charge region in HP diode has a 2D distribution (diamond-like, Fig. 2.14a), we took the average value of WD (depleted area divided by film thickness). This approximation is not restrictive since only the area of the depletion region counts. The lifetime determined from Eq. 2.10 is very short (0.14 ns). Similarly, for the other condition (VGF = -1.2 V/VGB = +15 V), the doping concentration results in ~ 10 19 cm -3 and ~ 10 nm of the depletion width. The lifetime is calculated as 0.2 ns. In devices with thicker gate oxide (GO2), the ideality factor is always higher than the theoretical condition n = 1.33, as shown in Fig. 2.18b. We selected the inflection point (ideality factor n = 1.5) to evaluate the lifetime which appears to be equally short: 0.2 ns for VGF = -1.2 V/VGB = +10 V and 0.13 ns for VGF = -2 V/VGB = +15 V (Fig. 2.18b).

Input

Recombination and diffusion current

An a priori simple method consists in exploiting the recombination-dominated section of the I-V characteristic. Linear extrapolation (in semi-log scale) of the recombination current at VA = 0 yields, in principle, the nominal value of IR0, see Eq. (i) Linear extrapolation of IR0 on log-scale causes exponential errors;

(ii) Such extrapolation requires the region governed by the recombination current to be well defined and wide enough. The longer the lifetime, the smaller the recombination current and the narrower the recombination-dominated region, as shown in Fig. 2.21a. In other words, the method is more applicable for very short lifetimes.

These limitations make the method unreliable at experimental level. No consistent value of IR0 could be extrapolated from the I-V curves of Fig. 2.18a. The reason is that the recombination region is distorted from the ideal behavior (n = 2). Due to the high concentrations of the virtual doping, band-to-band tunneling may occur, as in Esaki diodes [14], and mix with the recombination current. In Fig. 2.19, n factor is higher than 2, whereas in Fig. 2.21 the extrapolation yields a large IR0 current. As a result, the calculated lifetime is 1-2 orders of magnitude shorter than the method in section 2.6.2.1 which seems more feasible.

The possibility to use the diffusion current and Eq. (2.7) has also been evaluated. Linear extrapolation of the diffusion current region to VA = 0 leads to inaccurate ID0 value. To discriminate the pure diffusion current from the total current, we established the recombination current. Even with this precaution, the extracted carrier lifetime is unrealistic, far too short since the limitations for the recombination current extraction militate against this method.

Reverse Recovery Transient (RRT) method

A reverse recovery transient (RRT) method proposed in [46] relies in measuring the current transient after an ON/OFF switch of the diode. This method can be equally applied to the HP diode with negative front-gate bias (VGF = -2 V) and positive back-gate bias (VGB = +10 V) which emulate a heavily-doped virtual P-N diode. The diode is abruptly pulsed from forward mode to reverse mode and the current is measured as a function of time. Since the excess charge stored in the diode cannot be adjusted instantaneously after the switch, a small forward voltage is maintained across the junction.

This induces temporarily a large reverse current IR, the value of which depends on the resistance of the external circuit. The excess minority carriers (electrons under the gate and holes in ungated region) are gradually eliminated by the reverse current and by recombination. As the junction depletion width tends to expand, the high reverse current eventually falls to almost zero, the steady-state value. The average lifetime of minority carriers can be determined from the time-dependent current response. The transient variation of the stored excess charge Qc after a sharp switch is given by [48]:

Q c (t) = τ • {(I F + I R ) • exp ( -t τ ) -I R } (2.11)
where τ is the lifetime of holes in the lower doped N * region and IF is the forward current. The time needed to evacuate the stored charge (i.e., excess holes in N * side) is referred to as storage delay time td. It is obtained by setting Qc(td) = 0 which yields a simple relation between the reverse recovery current and the delay time [48]:

t d = τ • ln(1 + I F I R ) (2.12)

The virtual P-N diode

The RRT characteristics of a virtual P-N diode are tested under a forward-to-reverse bias switch at anode (Fig. 2.22a) or at cathode (Fig. 2.22b). In both cases, the reverse current is much larger than the normal saturation current of the diode and lasts for about 30 ~ 60 ns. In Fig. 2.22a, where the anode is switched from forward (VA = +1.5 V) to reverse (VA = -1 V) mode, the current variation with time follows the classical model [48]. Three typical regimes are visible: (i) high forward current IF at forward bias, (ii) abrupt reverse recovery current IR during a short delay time td, and (iii) constant and very low leakage current in the reverse mode. The cathode voltage switch shows similar trends (Fig.

2.22b).

According to the experimental curves in Fig. 2.22a and Eq. 2.12, the recombination lifetime is 3 ~ 8 ns. Figure 2.22c shows reverse recovery current for three different anode ramping voltage (1.5 V to -1 V, 1.2 V to -1.2 V and 1 V to -1 V): the extracted lifetimes are 3 ns, 5 ns and 8 ns, respectively.

In Fig. 2.22d, the reverse current is triggered by cathode switch for low gate biases (-0.5 V, -1 V and -1.2 V); the resulting change in electrostatic P * doping does not affect the carrier lifetime (~6 ns), at least for relatively small hole concentrations.

We now take a close look at Eq. 2.12 which is subject to several approximations that are examined in the context of virtual diodes:

-Asymmetrical P + -N -diode -The electrostatic doping levels N * and P * are gate-controlled and set on demand. Either high-low P + -N -or Esaki-like P + -N + junctions can be emulated. Nevertheless, the -Long N --region exceeding the hole diffusion length -Considering a lifetime of 5-10 ns and a hole mobility of 10-20 cm 2 /Vs (at high hole concentration) yields a diffusion length of 300 nm, which is comparable or smaller than the length of the ungated region. Theoretical corrections have a marginal effect [7]. Instead, we explore in the next section. The case of P-I-N diodes which comply with the model assumptions.

-Ideal vertical switch -Detailed measurements are performed with variable ramp time, tRamp from 50 to 500 ns, of anode bias (2 V to -1 V). Cp of the equipment (cables, contacts, chuck, etc.) [45]: which explains the larger current measured with fast ramp (Fig. 2.23a). The plot of Imeas versus the reciprocal ramp time 1/tRamp is indeed linear (Fig. 2.24b) and confirms Eq. 2.13. The slope indicates the parasitic capacitance whereas the extrapolation at 1/tRamp = 0 produces the pure reverse current (IR ~ 82 μA). Using these updated values, the lifetime in the virtual P-N diode, calculated with Eq. 2.12, is 34 ns.

I meas = I R + C p • dV dt (2.13)

The virtual P-I-N diode

The HP diode offers the possibility to emulate three P-I-N diodes in the same body. We compare a full-body P-I-N diode (Fig. 92 experimental data. These values are slightly larger than for the P-N diode. The lifetime in P-I-N diode ranges from 39 to 58 ns.

Double gated P-I-N diode technique

An additional experiment was performed in ultrathin film for validation of the techniques with a different gated P-I-N structure. The method documented by Ernst et al [47] is adapted to our ultrathin P-I-N diode with the gate extending all the way from cathode to anode (Fig 2 .28a) and tested under several bias conditions. The front and back gates are biased such as the in-depth potential profile becomes quasi-flat when the concentrations of electrons and holes are roughly constant in the whole body volume. The forward current is governed by the double injection of electrons and holes. The measurement is performed at fixed and low value of anode bias (where the recombination mechanism dominates) as a function of gate voltage. Peak values of current observed in Fig. 2.28 correspond to the maximum rate of electron-hole recombination. Here, the quasi-Fermi levels are equidistant from the mid-gap, so that the concentrations of electrons and holes become equal: n= p = n i • exp (qV/2kT).

According to the model, the excess peak current ΔIF is reproduced by simply multiplying the maximum recombination rate Rmax = n/τ by the volume of the body [47]:

∆𝐼 𝐹 = 𝑞•𝑛 𝑖 𝜏 𝑛 • exp ( 𝑞𝑉 𝐴 2𝑘𝑇 ) • (𝐿 • 𝑊 • 𝑡 𝑆𝑖 ) (2.14)
The lifetime calculated from Fig. 2.28a with Eq. 2.14 is 9.5 ns. The lateral shift of the current peak position reveals the role of the back gate. If VGB decreases, fewer electrons are available at the back interface, hence the front gate voltage has to be increased in order to compensate. The peak current increases with VA as shown in Fig. 2.28b. Nevertheless, excessive anode bias (VA > 0.6 V) brings the diffusion mechanism into play and invalidates Eq. 2.14.

Conclusion

In this chapter, the Hocus-Pocus (HP) diode, where the implanted donor/acceptor species are replaced by gate-induced electron and hole charges, is demonstrated. The concentration of the electrostatic doping is controlled by tuning the front and back gate biases. The concept of virtual diode with gate-adjustable doping is the result of the recent development of FD-SOI technology. Both experimental results and numerical simulations show conventional 'diode-like' characteristics with extremely low leakage current, high ON/OFF ratio, and high breakdown voltage. As compared with standard diodes with ion-implantation, several differences originate from the intrinsic properties of the electrostatic doping: (i) non-constant, tunable doping level, (ii) dynamic variation of the electron and hole charge with anode/cathode voltage, (iii) 2D profile of the space charge region and carrier distributions. These aspects are challenging for developing a 2D model for virtual diodes. Our measurements demonstrate the exceptional flexibility of the HP diode which can transform in a variety of useful devices: full/semi-virtual diode, P-I-N diode, TFET, band modulation FET, etc. This capability of metamorphosis offers opportunities for designing reconfigurable circuits, where P-N junctions can be emulated or suppressed on demand to match user-defined applications.

The emulation of a virtual Esaki diode with negative conductance region is a striking result.

The HP Esaki diode is fully compatible with standard FD-SOI technology and opens innovative applications in the RF and THz domains.

The HP diode provides solutions for lifetime evaluation in ultrathin FD-SOI films. We have tested and compared several extraction methods by taking advantage of the flexibility and properties of the gate-controlled virtual diode. The direct exploitation of I-V characteristics to determine the transition from recombination to diffusion regimes or the reverse recombination/diffusion currents is subject to large experimental errors. Far more convincing is the reverse recovery time method which can be applied to either P-N or P-I-N diodes. The carrier lifetime appears to be very short in sub-10 nm thick SOI devices. Our results converge to 30-50 ns lifetime, depending on the concentration of electrostatic doping. This extremely short carrier lifetime explains why our band-modulation devices, also based on electrostatic doping, feature a nearly vertical switching capability in both transfer and output characteristics [39]. For the same reason, the gain of the parasitic bipolar transistor in sub-10 nm thick FD-SOI MOSFETs was found to be modest [34]. For comparison, earlier measurements in thicker FD-SOI devices, where the interface contribution is less severe, resulted in lifetime values in the 1 µs range [47]. The HP diode appears as a new, useful tool for ultrathin film characterization. The lifetime has been extracted with first-order 1D models. They can be customized by considering the special 2D behavior of the virtual diodes: in-depth variation of electrostatic doping and extension of the lateral space charge region. Given the applications of the virtual diode, a dedicated model deserves to be constructed. Based on our results, a realistic rather than guessed value for the carrier lifetime can now be introduced in TCAD tools for the simulation of switching, memory and power SOI devices.

Introduction

Two applications originating from the original concept Z 2 -FET [1] are investigated in this chapter. Characteristics of the Z 2 -FET such as sharp switching occurring along with a large hysteresis effect is the base of the working principle for single-transistor dynamic random access memories (1T-DRAM as briefly mentioned in section 2.5 [1]- [6]). In section 3.2, the device physics in Z 2 -FET operation will be discussed with the support of experimental and simulation results. Promising experimental results, shown in section 3.3, were obtained in terms of low-power memory operation. In section 3.4, advanced Z 2 -FET structure with dual ground-plane and a method for Z 2 -FET array operation without selection-transistor are proposed. Also the possibility to utilize Z 2 -FET as a logic switch [7] will be addressed in section 3.5. complex physical phenomenon that is governed by the balance and imbalance between generationrecombination (G-R) and diffusion currents in the DC operation, and by non-equilibrium mechanisms in pulsed mode (discussed in later section). The hysteresis induced by the VA sweep direction originates from an S-shaped I-V characteristic which can be measured by anode current source (Fig. 3.1b). The hysteresis comprises two different current states ('1' and '0') corresponding to high or low current levels for the same value of anode voltage, making Z 2 -FET as an attractive choice to design capacitorless memory cell [8].

Physics in capacitorless 1T-DRAM Z 2 -FET operation 3.2.1. DC operation

To understand the details of the Z 2 -FET operation, 2D simulations were performed with Synopsys TCAD simulator [9] using standard models of doping and mobility (doping dependence, potential under the front gate significantly increases with VA tending to create a depletion region. Note that in the ungated region, the potential variation is limited (∼0.1 V), highlighting that carrier concentration in this region changes marginally. At the end of the OFF-state regime, the potential under the gate reaches its maximum value even if the hole injection barrier (body/P + barrier) is lowered from 1.1 V (point 'a') to 0.5 V (point 'j'). The central barrier increases steadily with VA. In this region, the current is dominated by the generation-recombination current, which depends on the carrier lifetime [11], [12]. Once the potential under the gate reaches its maximum value, a further increase in VA does not modify the central barrier anymore, but it reduces the hole injection barrier at the anode-body junction. Due to that barrier lowering, holes start to diffuse from anode into the channel and get recombined at the ungated region and cathode junction. The potential in the ungated side and electron injection barrier (N + /body barrier) are significantly reduced (from point 'j' to point 'm' in Fig. 3.4b) which helps electrons to diffuse from cathode into channel and get recombined at the gated region and at the anode junction. Since in the exponential region of anode current, the current is dominated by diffusion process, the classical slope of 60 mV/dec is observed (Fig. 3.3). Lowering of electron and hole injection barriers further facilitates the carriers to flow into the channel leading to positive feedback effect. At this point, the continuity between the diffusion current at one junction and recombination current at the other junction can no longer be sustained (point 'n' in Fig. 3.4b) [11]. As a result, anode current rises sharply at the steep transition point turning the device ON. Device behaves like an ON state P-I-N diode, leading towards double injection [13]. Pre-Write '0' (Fig. 3.9) -The anode voltage stays 0 V and the gate pulse drops to 0 V from the high voltage level. As VGF decreases, the hole injection barrier is remarkably reduced (step 2 to 3) which Write '0' (Fig. 3.10) -The gate voltage being maintained at 0 V, the electron concentration under the gate decreases by more than 10 orders of magnitude (center panel, between the step 3 and 4), which is

Transient characteristics

Experimental validation of Z 2 -FET memory operation

DC operation

To evaluate the IA-VA characteristic of Z 2 -FET, different front-and back-gate voltages were applied before scanning the anode voltage. The detailed device physics in DC operation were discussed in section 3.2.1. Figure 3.20 shows the back-gate bias effect in terms of memory window and leakage current. When VGB = -0.5 V, the OFF leakage current tends to increase as VGF increases (Fig. 3.20a).

However, when VGB = -1 V (Fig. 3.20b), the leakage current stays always low due to the high electrostatic barrier and because the memory window is larger than for VGB = -2 V (Fig. 3.20c). Since the back-gate action also affects the gated region, the optimal compromise between the front-and backgate bias is achieved for VGB = -1 V. Therefore, the specific value VGB = -1 V is chosen for further transient measurements and provides the best retention behavior for 28 nm node architecture/technology. mV/decade) and remarkable transition from low to high current, enabling an ION/IOFF ratio of 10 decades.

The turn-ON voltage increases as VGF reinforces the barrier at anode side. The turn-OFF occurs for ~ 0.7 V during the reverse scan of VA. Note that the front-gate voltage should be over 1 V to bring on a window effective for memory applications.

Transient mode operation

To test the memory performance of Z 2 -FET, several preliminary patterns (same as in Fig. 3.7)

were applied to the device at room temperature. Two different observation periods were compared. (i)

The short one of 13 μs comprises a programming time of 200 ns, holding time 2 μs and reading time 4

μs. (ii) The other period is 100 times longer (1.3 ms), with a programming time of 100 μs, holding and reading times of 150 μs. The comparison of the "short and long" programming-holding-reading cycles allow us emphasis the effect of the capacitive coupling on the reading current level. Anode voltages from 0.9 to 1.2 V were applied while ranging the front-gate bias from 1 to 1.4 V in order to evaluate the bias required to achieve the targeted current margin.

Standard memory performance

For the standard short and long patterns, if the anode and gate biases are selected in the appropriate range (details below), a negligible '0'-state current level and the minimum required current margin can be achieved (Fig. 3.21a and Fig. 3.22a). Note that the '0'-state starts to be degraded when the anode voltage is too high and/or the required front-gate bias is undervalued, see For the short pattern where the VA slope is steeper than in the longer pattern, little spikes are observed at turning ON/OFF of VA pulse due to the capacitive discharge current through the measurement equipment (mainly cables). In Fig. 3.23, the maximum current during programming and reading '1'-state is plotted vs.

VGF for different VA. The black line which crosses the current curves indicates the front-gate voltage limit when the '0'-state starts to be degraded (on the right side of this line, no degradation of the '0'state current is observed during the reading-holding sequence). Note that as VA increases, the "degradation voltage" VGF becomes higher showing quasi-linear behavior. To operate the Z 2 -FET memory without '0'-state degradation, the bias range to be selected is then located on the right side of the dash line. The anode current levels for both short and long patterns are comparable but the '0'-state degradation margin for the short pattern is wider (i.e. lower VGF needed) than for the longer pattern.

Refering to section 3.2.3 (Fig. 3.13, Read '0'), when the VA is high during reading '0', the electron injection barrier at cathode decreases and electron concentration under the gate tends to increase. When the duration gets longer for reading operation, the risk of '0'-state degradation increases due to carrier generation. Therefore, the faster the operation, the better the performance we obtain, which is the Since operation of programing '0'-state has no power dissipation (VA = VGF = 0 V), there is only one possibility for power consumption reduction by controlling programming '1'-state. By decreasing the anode voltage, the power consumption can be efficiently reduced. Even with small anode pulse, the P-I-N diode can inject enough electrons to the body to establish the '1'-state. In Fig. 3.26, the writing '1'-state current with VA ≤ 0.5 V is negligible and it reduces power consumption during writing operation compared with the nominal value of VA (~1 V). Therefore, the total power dissipation of the memory operation cell is reduced by a factor of two since power consumption occurs when the device is ON (Programming and reading '1'-state). Furthermore, the read '1'-state current remains high even with small writing VA. Such a low voltage operation capability is unrivalled by any other emerging memory such as resistive, phase change or spin [1], [16]- [18]. of time and is still lower than the '1'-state current.

For the constant reading retention test, the pattern of Fig 3 .29 was applied with the P1-H-R-H-P0-H-R-P1-H-R-H operations. The retention test under continuous reading after programming '0' and '1'-state is shown in Fig. 3.30. No degradation for the '0'-state is observed in Figs. 3.30a,d. However, the '0'-state is degraded in Fig. 3.30b,c because again the front-gate bias is not high enough. It is worth mentioning that the '0'-state is more prone to degradation for the periodic reading operation than for the constant reading test. Even with the same bias condition, '0'-state degradation is observed in cyclic retention test while there is no degradation for continuous reading (Fig. 3.28b and Fig. 3.29d). This conclusion needs to be verified with further investigation where the VA pulse rising time is identical for both patterns, otherwise the discharge current may affect the read current.

From the retention tests of the Z 2 -FET, we conclude that the VGF control is very important. In order to avoid rapid '0'-state degradation, a higher difference between VGF and VA than in the standard memory operation is required. 122

High temperature operation

In this section, we highlight that the Z 2 -FET is fully functional at high temperature. As the temperature increases, not only are the barriers weaker but also the carriers gain energy.

For instance, the current I1 measured at 85 °C is 50 % higher than at room temperature, which implies that the memory can be operated with lower anode voltage. Since the OFF current I0 also tends to increase at high temperature, the solution for maintaining a respectable sensing margin is to adjust VGF to a slightly higher value [3].

In Fig. As already demonstrated, in pulse-mode operation, the '0'-state is mostly affected during the hold (whereas '1'-state is stable). The '0'-state starts to be degraded when the anode voltage is too high and/or the required front-gate bias is undervalued. For example, if the gate bias is selected about 100 123 mV higher than the anode bias, a negligible '0'-state current level and an excellent current margin can be achieved (Fig. 3.32b). Figure 3.32d shows that the reading '1'-state current increases as the temperature increases without '0'-state degradation up to 120 °C . For comparatively low gate and anode biases, no degradation of '0'-state was observed at high temperature (not shown). The '0'-state failure at 130 °C is shown in Fig. 3.32c. However, the retention of the '0'-state can be improved by adjusting the front-gate voltage. It follows that the Z 2 -FET memory is functional in a wide temperature range.

The following is a brief summary of the roles played by the main parameters of the memory:

-Anode voltage determines I1 current.

-VGF defines the hole injection barrier and I0.

-VGB controls the electron injection barrier. A lower VGB reinforces the front-gate action. The doping of the ground-plane can be adjusted such as to operate the memory with VGB = 0 and facilitate peripheral circuitry [19].

-Gate oxide and BOX should be as thin as possible in order to reduce the gate bias.

-Length defines the barrier width and blocking capability; scaling leads to weaker barriers (narrower and shorter) but is possible at least down to 30 nm [20].

-Shorter lifetime increases VON but negatively affects the retention. Conversely, for long lifetime, the Z 2 -FET operates as a diode without sharp switch. In practice, the carrier lifetime is technology-related and cannot be easily engineered in ultrathin FDSOI films. It follows that semiconductors with high lifetime may not be suitable.

-Higher carrier mobility increases ON current and carrier diffusion length [12].

-Short pulses with fast ramping time are beneficial.

Advanced Z 2 -FET memory

Advanced Z 2 -FET structure: dual ground-plane

The novel structure fabricated in 14 nm FD-SOI node, Z 2 -FET DGP [2], is shown in Fig. 3.33.

The device is similar to the standard 28 nm node Z 2 -FET except that an additional N-type Ground Plane (GP-N) is located underneath the gated region. The gated and ungated region are independently affected by the two back-gates. The benefit is that the competition between front-gate and GP-P to control the potential in the gated region is eliminated. Both ground planes are heavily doped (~10 18 cm -3 doping concentration). Like for standard Z 2 -FET, the buried oxide (tBOX = 25 nm) and silicon film thicknesses (tSi = 7 nm) are identical in 14 nm node.

The dual ground-plane Z 2 -FET is expected to show advanced performance compared to the standard single ground-plane Z 2 -FET since the two ground-planes can be biased separately. The back bias (VGbN > 0) under the gated region reinforces the front-gate action rather than counteracting it as in standard Z 2 -FET with single ground-plane. Therefore, there is a possibility to reduce the operating voltage VGF since the VGB does no longer affect the hole injection barrier. Figure 3.36 shows the memory operation at low ground-plane voltages of VGbP = -1 V, VGbN = 0 V. Compared to the bias at VGbP = -2 V, VGbN = +2 V shown before, ON current is slightly less (but still high) despite the hole injection barrier is less strong. In addition, '0'-state was degraded when the voltage difference VGF -VA is more than 0.1 V (not shown).

The measured dual ground-plane Z 2 -FET performance confirms the possibility to achieve lowpower operation. Although more investigation (bias optimization, retention tests) is needed for new runs of devices that are in the processing line.

Selection-transistor-free Z 2 -FET memory array

In this section, we propose a method for the Z 2 -FET memory array operation without selection-transistor (Fig.

(a) (b)

128 indicates disturbance created in the unselected word lines (WL2/3) where a gate bias increase is used to prevent the anode current to flow. The last read operation was performed to check if the '0'or '1'state is still maintained (this operation is supposed to be performed in the selected word line WL1). The anode current shows whether the device is blocked or not with higher front-gate bias. The third reading operation highlights that the memory still works with the biases as previously set. Anode voltages from 0.95 to 1.15 V were applied while ranging the front-gate bias from 0.95 to 1.15 V in order to evaluate the bias required to achieve the current cut-off performance while reading.

(a) (b)

anode and gate biases are selected in the appropriate range. To block the current in adjacent lines, the front-gate voltage should be about 100 mV higher than the front-gate voltage already used for programming '1'-or '0'-state. In other words, the front-gate should be biased in the range that guarantees the device in OFF-state. If not, the current flows as if the WL2 is selected (Fig. 3.39a and 3.40a).

When the reading operation in WL2 is short enough (~1 μs), even if the front-gate voltage is applied for a long time (~1 ms), the current can be blocked and the reading '1' in WL1 is possible (Fig. 3.41).

However, higher leakage current is observed for longer reading ((a) 6 μs and (b) 7 μs) as shown in Fig.

3.42.

By manipulating the gate bias in memory array operation, the additional selection-transistors used in conventional DRAM memory array may be eliminated from the Z 2 -FET memory array. This study proves that the capacitorless Z 2 -FET memory array has a chance to succeed in future generation memory market.

Z 2 -FET as a logic switch

In this section, transient experiments are presented showing the possibility of eliminating, in specific conditions, the typical hysteresis between turn OFF and ON. The capability of Z 2 -FET to operate as a logic switch is demonstrated. The presence of hysteresis in transfer ID-VG characteristics has handicapped so far logic applications. However, fast pulses on the gate result in hysteresis-free 131

The electron/hole injection barriers are set by the front-gate (VGF > 0 V) and the ground plane (VGB < 0 V). Typical characteristics in DC mode are shown in Fig. 3.43. Both output ID (VD) and transfer ID (VGF) characteristics present bias-adjustable hysteresis and sharp-switch (~1 mV/decade). Abrupt switch-on occurs when the barriers totally collapse. As VGF increases in Fig. 3.43a, the anode barrier is higher and more electric field (i.e., higher VA) is needed to break it. The ON/OFF ratio is 7-10 orders of magnitude and the turn-ON voltage is tunable to fit various applications. The ON current increases with anode bias as in a regular P-I-N diode, without being much affected by the gates. The switch-off requires lower anode voltage (Fig. 3.43a) or higher gate voltage (Fig. 3.43b) in order to reconstruct the barriers. In Fig. 3.43b, a little increase in VA demands a much higher VGF to block the device. Even worst, if VA is too high, the gate might be unable to turn-OFF the device. This difficulty has inhibited the use of Z 2 -FET for logic switch. To eliminate the hysteresis in DC transfer characteristics (Fig. 3.43b), we use fast gate pulses that turn the device ON and OFF at same VGF. When VGF signal increases sharply, the electron concentration underneath the gate cannot be adjusted instantly, hence the anode barrier becomes higher than in DC mode. (This non-equilibrium mechanism is actually the primary condition for Z 2 -FET 1T-DRAM operation) In other words, the gate voltage needed to block the device is lower in pulsed mode than in DC. For example, pulsing up and down VGF by only 0.5 V is sufficient to switch the device OFF and ON. Much higher VGF was used in DC mode to turn-OFF the device (Fig. 3.43b). It follows that power consumption can be significantly reduced in pulsed operation.

We now examine the optimum conditions for the switch. Figure 3.44a indicates the impact of anode bias when the gate is pulsed down and up between 1.5 V and 1 V. Proper switching characteristics, with negligible leakage current, are obtained by maintaining VA below 1V (bold curves). Increasing VA from 0.7 to 0.9 V doubles the ON current. For VA ≥ 1V, the gate voltage (1.5 V) is no longer able to fully block the device: while the effect of switching is still visible, the OFF current is too high. The solution is to increase the gate bias, as shown in Fig. 3.44b. Here, VA = 0.8 V and VGF pulses of 0.5 V amplitude and variable top level are applied. Gate voltage of 1.4 V or higher results in a perfect, leakage free switch. A lower gate bias (1.2 V) is not sufficient to generate strong enough barrier, leading to high OFF current.

The leakage current can be further controlled through the ground-plane, as shown in Fig. 3.45a.

A too positive VGB demolishes the electron barrier at cathode whereas a negative bias counteracts the effect of the gate on the hole injection barrier at anode, unless VGF is increased. Both cases lead to unacceptable OFF current. Systematic data summarized in Fig. 3.45b indicate that the switch operates ideally with 0 < VGB < 1 V.

The device response in time domain is shown in Fig. Reaching back the OFF state is more challenging but very short pulse prove to be effective (for example, 50 ns pulse in Fig. 3.46). The rise time of the gate pulse is critical for obtaining sharp switchoff. The idea is to rebuild the gate barrier faster than the time needed for carriers to arrive. A faster rise time also accentuates the non-equilibrium condition (similar to deep depletion in bulk MOS [14], [15]) and makes the gate barrier higher. The relation between pulse rise time tr and carrier transit time tt = L/v (v being the carrier velocity), tr << tt, suggests that faster pulses (beyond the limit of 50 ns in our equipment) enhance the switching performance, which is exactly what digital circuits are aiming at.

Novel Z 2 -FET with dual ground-plane

The dual ground-plane configuration offers superior flexibility in barrier management by their independent control. The DC transfer characteristics (Fig. 3.47) are similar to those in SGP Z 2 -FET (Fig. 3.43), except that the latch can be more easily suppressed. At high VA, where the device may fail to turn OFF, one can use VGbN > 0 to increase the gate barrier and block the current. This approach has the advantage of maintaining VGF at a reasonable low level.

The reinforcement of the hole injection barrier with VGbN > 0 is clearly illustrated in Fig. 3.48a.

The OFF-state current is fully suppressed for VGbN = +2 V even at VGF as low as 0.5 V. However, these conditions are no longer sufficient if the anode bias is increased to achieve a higher drive current (Fig.

3.48b

). Rescue comes from the second ground plane. A negative bias (VGbN ≤ -1 V) reinforces the barrier at cathode and guarantees low OFF current. The ION/IOFF ratio exceeds 6 orders of magnitude. Note that the ground plane biasing does not modify the ON current.

The interplay of gate, anode and ground-plane voltages is even more important as the devices are scaled down. Our results indicate that in shorter devices, where the barriers become narrower and 135 mainly from the sampling rate of the data treatment in our program. Although the rise/fall time set as 30 ns, the fall time of collected VGF signal is longer, ~60 ns. In addition, since the current initiates by the gate discharge current ΔQG/Δt, the SS may significantly improve for faster VGF switching.

Conclusions

The rationale for developing Z 2 -FET 1T-DRAMs has been documented as a target for lowpower memory cell. The Z 2 -FET sharp switch and its application as 1T-DRAM have been described by revealing the detailed mechanisms that occur in quasi-static, transient and memory operation.

Additional information is available in a series of articles dedicated to Z 2 -FET [4], [19]- [22]. The experiments and simulations have been focused on the devices fabricated with 28 nm FD-SOI technology. The novel 14 nm FD-SOI technology has also been investigated emphasizing the role of dual ground-planes that control respectively the gated and ungated sections of the body. Other implementations are under investigation: thinner body, intentional N-type doping in the ungated region to suppress the need for back bias [19], and gateless Z 3 -FET where the barriers are set by independent ground planes [23]. The Z 2 -FET memory is unrivalled in terms of retention time, low-power consumption, memory margin and non-destructive reading. Another practical advantage is the full compatibility with the FD-SOI process, without any additional technology module needed. We have experimentally demonstrated low-voltage operation with ~1 V read bias and program bias as low as 0.4-0.5 V. These assets make the Z 2 -FET very attractive as high-speed, low-power embedded memory.

Z 2 -FETs have successfully been used for capacitorless DRAM memory, but the presence of an inherent hysteresis has handicapped so far logic applications. The solution suggested here utilizes fast pulses on the gate that result in hysteresis-free switching: the device turns ON and OFF at same gate bias. Z 2 -FET switches have extremely low OFF-state leakage and a high speed gate pulse enables abrupt switching between the two logic states. They can be operated at relatively low voltage (0.5 V gate swing and sub-1 V anode bias), suggesting superior energy efficiency than CMOS transistors.

Faster switching increases their attractiveness: (i) sharp turn-OFF due to higher non-equilibrium barrier, (ii) easier turn-ON via gate-discharge current, and (iii) less time in ON state for limited power consumption.

Z 2 -FET is user adaptable since turn-ON voltage can be tuned depending on the applications.

TCAD simulations indicate that the device can be scaled down to less than 50 nm for both the gated and ungated regions [20]. Albeit the device and bias parameters interact with each other, at given power consumption (VA and IA) and dimensions, the gate and ground-plane voltages are selected to ensure the blocking capability of the injection barriers and optimal switching performance. Since the groundplanes and anode receive constant bias and only the gate is switched, the barrier height at the anode side

Résumé du manuscrit

Chapitre 1

Le dopage électrostatique offre une grande opportunité pour les structures ultra-minces: FD-SOI (Fig. 1a), nanotubes (Fig. 1b), matériaux 2D (Fig. 1c) ou nanofils verticaux (Fig. 1d), FinFET, etc.

Les dispositifs bien connus tels que les diodes, les MOSFET et les transistors bipolaires peuvent être reproduits en remplaçant le dopage physique par des charges d'électrons et de trous induits par la grille.

Cette méthode offre la possibilité de créer des terminaux N + et P + même dans des matériaux où les techniques de dopage chimique ne peuvent pas être appliquées. Il est aussi intéressant de noter que la polarité et la concentration du dopage, dans la même région du corps, sont ajustables par la tension de grille.

L'avantage ultime du dopage électrostatique est la conception de nouveaux types de dispositifs avec des multiples performances améliorées et des fonctionnalités enrichies pour les circuits intégrés reconfigurables. Le concept de modulation de bande est en réalité le fruit du dopage électrostatique.

Nous avons examiné plusieurs variantes de prototypes fabriques en technologie FD-SOI. Les dispositifs V GF < 0 V GB > 0 de 1 µs. La diode HP apparaît comme un nouvel outil utile pour la caractérisation de films ultra-fins.

La durée de vie a été extraite avec des modèles 1D de premier ordre; ils peuvent être personnalisés en considérant le comportement 2D particulier des diodes virtuelles: variation en profondeur du dopage électrostatique et extension de la région de charge d'espace latérale. Compte tenu des applications de la diode virtuelle, un modèle dédié mérite d'être construit. Sur la base de nos résultats, une valeur réaliste plutôt que supposée de la durée de vie des la porteurs peut désormais être introduite dans les outils TCAD pour la simulation de dispositifs SOI à commutation rapide ou à mémoire.

Résumé

  La récente technologie Fully Depleted SOI (FD-SOI) est une excellente alternative à la technologie conventionnelle CMOS (Complementary Metal Oxide Semiconductor) qui a mené le développement incessant des circuits intégrés. FD-SOI offre une faible consommation d'énergie et un contrôle électrostatique amélioré pour les transistors MOS, même dans les noeuds très avancés (14 et 28 nm). En raison de leurs dimensions nanométriques, aussi bien en épaisseur qu'en longueur, les transistors FD-SOI présentent des mécanismes de fonctionnement et des caractéristiques très spécifiques. L'état de l'art du FD-SOI est décrit en insistant sur les atouts des composants, les effets physiques particuliers et les techniques de caractérisations dédiées. La diode Hocus-Pocus (HP) est un exemple de dispositif innovant rendu possible par la flexibilité sans égal de la technologie FD-SOI. En modifiant le type de dopage électrostatique, N ou P, un dispositif peut être reconfiguré en diode P-N virtuelle, diode Esaki virtuelle, diode semi-virtuelle, diode P-I-N, TFET ou FET à modulation de bande. Chaque configuration fonctionne comme un dispositif physiquement dopé. Les aspects inédits découlent d'un changement dynamique de la concentration des porteurs. Des applications originales telles que l'extraction de la durée de vie des porteurs et la diode virtuelle Esaki sont explorées. Le Z 2 -FET (Zero subthreshold slope and Zero impact ionization) est un dispositif particulièrement prometteur en raison de ses caractéristiques attrayantes (commutation abrupte, faible courant de fuite, tension de déclenchement réglable et rapport de courant élevé ION/IOFF). Dans ce travail, nous nous concentrons sur une mémoire dynamique sans capacité (1T-DRAM) et un interrupteur logique rapide. Les mécanismes de fonctionnement en courant continu et transitoire ainsi que les performances du dispositif sont étudiés en utilisant de simulation TCAD et validés à l'aide de résultats expérimentaux systématiques.

Figure 1 . 1 .

 11 Figure 1.1. Schematic cross-section of N-type MOSFET transistor on 28 nm Bulk technology.

Figure 1 . 2 .

 12 Figure 1.2. (a) Transistor manufacturing cost and (b) minimum scaling cost at recent technology nodes (GlobalFoundries 2015).

  dynamic adjustment of the threshold voltage Vth of the transistor by biasing the back gate represents a unique virtue of FD-SOI which is absent in competing FinFET technology. An increase of 200 mV in Vth reduces the consumption in OFF-state by three orders of magnitude. In ON-state, on the other hand, the performance is optimized by lowering the Vth and improving carrier mobility through strain engineering and/or replacing Si with SiGe. This is the determining reason for the advantageous position of the FD-SOI circuits in the market for low-voltage and low-power components for the Internet of Things (IoT). The variability of the Vth is a critical problem for low-power operating transistors. Since FD-SOI MOSFETs are undoped, the main source of variability (random fluctuations in dopants) disappears. Although fluctuations in layer thicknesses are a priori a source of additional variability, SRAM FD-SOI memories show splendid performance [15]. The RF-SOI circuits are also ranked in the most prominent position in silicon industry. They benefit from much lower parasitic capacitances than FinFET, as well as from high-resistivity substrates designed and manufactured by SOITEC. The general consensus is that the FD-SOI is economic (cost-effective) and complementary to FinFET.

Figure 1 . 3 .

 13 Figure 1.3. Schematic of SOI wafers fabrication using SmartCut® technique supported by SOITEC [16].

Figure 1 . 4 .

 14 Figure 1.4. (a) Schematic of FD-SOI MOS transistor [17] and (b) TEM cross-section of nMOS device (Lg = 24 nm) with 7 nm ultrathin SOI [18].

Figure 3 . 1 .

 31 Figure 3.1. Schematic view and energy band diagram of (a) a Zener diode in reverse bias and an N-type TFET in (b) OFF and (c) ON states [30].

Figure 3 . 2 .Figure 3 . 3 .

 3233 Figure 3.2. (a) SEM image of N-type Si TFET and (b) ID-VG characteristics of a SOI TFET showing SS < 60mV/dec at room temperature[41].

Figure 3 . 4 .

 34 Figure 3.4. (a) Schematic of NEM-FET and (b) ID-VG characteristics [48].

Figure 3 .

 3 6a encloses the structure of the band-modulation device: It is essentially a P-I-N diode where the gate covers only half of the body. A positive gate voltage emulates N * virtually-doped region, and P * region is induced by a negative substrate voltage (Fig. 3.6b).It results in the formation of a virtual thyristor-like NPNP structure which remains blocked even in direct polarization of the anode (VA > 0). The gate voltages form potential barriers that prevent the injection of the holes from the anode and the electrons from the cathode. The energy bands are modulated along the channel by the applied voltages (Fig.3.6b). When VA reaches a VON value, the barriers collapse, suddenly unblocking the device. The transition between the OFF and ON states is remarkably steep (~ 1 mV/dec). The mechanism consists of a positive feedback between the injection

Figure 3 . 5 .

 35 Figure 3.5. Schematic of Fe-FET and working principle [51].

Figure 3 . 6 .

 36 Figure 3.6. (a) Schematic of Z 2 -FET and (b) working principle.

Figure 4 . 1 .

 41 Figure 4.1. Schematic and TEM cross-section for the 1S+1R Cu-ReRAM cell [61].

Figure 4 . 2 .

 42 Figure 4.2. (a) MTJ basic structure and (b) 1T/1MTJ structure [61].

Figure 4 . 3 .

 43 Figure 4.3. Measured drain current depending on the front-gate sweep direction in MSDRAM [69]. The each gate is biased in moderate inversion to induce a back electron channel.

Figure 4 . 4 .

 44 Figure 4.4. Schematic A2RAM operation. (a) Holding '1': the p-body is charged, screening the gate field. (b) Reading '1': majority carrier (electron) current flows through the n-bridge. (c) Holding '0': the p-body is discharged (deep depletion), and the n-bridge is depleted. (d) Reading '0': the current through the nbridge is negligible [74].

Figure 1 . 1 .

 11 Figure 1.1. Conventional P-N diode with physical doping, (b) fully depleted layer with ohmic contacts, (c) fully depleted layer with ohmic contacts and top and bottom gates, (d) virtual P-N diode emulated by gates biasing.

Figure 1 . 2 .

 12 Figure 1.2. (a) Conventional bulk MOS structure featuring a surface inversion layer above the depletion and neutral regions. In ultrathin film, the gate induces electrons (b) or holes (c) in the full body according to the principle of volume inversion/accumulation.

Figure 1 . 3 .

 13 Figure 1.3. (a) Large nanowire where the inversion layer is confined at the surface, (b) small nanowire and (c) FinFET with volume inversion/accumulation.

Figure 1 . 4 .

 14 Figure 1.4. Schematic view of different band-modulation Z-FET devices: (a) standard Z 2 -FET, (b) Z 2 -FET with dual ground-plane and (c) Z 3 -FET without front-gate.

Figure 1 . 5 .

 15 Figure 1.5. (a) Carbon nanotube reconfigurable transistor [7], (b) carbon nanotube ambipolar transistor with back-gate action [3]-[5], (c) carbon nanotube MOSFET with local and global back-gates [6].

Figure 1 .

 1 Figure 1.6 shows a single-layer graphene P-N junction in which carrier type and doping are controlled by a local gate [21]. Graphene sheet was deposited on a SiO2/Si stack and covered with Al2O3.A local top gate controls the electrostatic doping (N or P) concentration underneath the gate whereas the global back gate (Si substrate) defines doping in the ungated area. This feature allows, via gates bias, graphene-based bipolar technology comprising P-N junction and reconfigurable devices in a single graphene layer. This technique sets the foundation for a FD-SOI electrostatic doping device which will be discussed in chapter 2.

Figure 1 . 6 .

 16 Figure 1.6. The schematic of single-layer graphene diode [21].

Figure 1 . 7 .

 17 Figure 1.7. (a) Si nanowire MOSFET with program back-gate [22], (b) Si nanowire MOSFET with control top gate and program back-gate [23].

Figure 1 . 8 .

 18 Figure 1.8. (a) Si nanowire transistor with one central control gate and two adjacent side gates that program the Schottky barriers to form N-channel and P-channel MOSFETs or TFET [24], (b) implementation in stacked nanowires [25], (c) MOSFET with two top junction gates that control the injection rate at source and program the polarity of carries at drain [26].

(

  TFETs) based on 2D transition metal dichalcogenide (TMD) materials investigated by atomistic quantum transport simulations. Fig. 1.9 shows the structure of an electrostatically doped device controlled by two gates. A virtual P-N junction can be created in this structure by applying biases of opposite polarity. Atomically thin 2D material-based devices are very interesting in the context for TFET applications, due to the tight gate control over the channel that results in high electric fields at the tunnel junction. The atomistic simulations of such electrostatic doped 2D material transistor showed a different behavior from devices with same equivalent oxide thickness (EOT). The authors argued a new scaling theory and design guidelines for such devices are needed.

Figure 1 . 9 .

 19 Figure 1.9. The schematic of single-layer graphene diode [27].

Figure 1 . 10 .

 110 Figure 1.10. Configuration of P-channel TFET and energy bands showing how the electrostatic doping enables the switch from (a) OFF to (b) ON state.

Figure 1 . 11 .Figure 1 . 12 .

 111112 Figure 1.11. Configuration of bilayer TFET.

  collector. In the meantime, the holes flow into the floating base which makes the emitter-base barrier get low. Therefore, the small amount of hole current generated by BTBT (i.e., small base current) triggers a large number of electrons to flow from emitter into the collector. According to simulations, this in situ amplification mechanism may increase the ON current by 3 orders of magnitude and maintain a sub-60 mV/decade swing over 7 decades of current (Fig.1.13b) when |VG| = |VE|= 1 V[37].

Figure 1 .

 1 Figure 1.13. Configuration of BET-FET on FD-SOI. Electrostatic P * doping underneath the gate causes BTBT current that is amplified by the lateral bipolar transistor, (b) comparison of ON current and subthreshold swing in BET-FET and regular TFET [37].

Figure 1 .

 1 Figure 1.15. Schematics of IMOS [39].

Figure 1 .

 1 Figure 1.14. Schematics of (a) conventional single-gate architecture of SOI LDMOS, (b) triple-gate LDMOS with one top gate, two ground-planes and electrostatic doping in the drift region fabricated in advanced FD-SOI technology [38].

Figure 1 .

 1 Figure 1.16. Schematics of GDNMOS [40].

Figure 1 .

 1 Figure 1.17. (a) The schematic of the charge plasma diode [8], (b) current-voltage characteristics [41].

Figure 1 . 18 .

 118 Figure 1.18. The schematic of bipolar charge plasma transistor [42].

  Figure 2.1. Cross-section view of standard Z 2 -FET in 28 nm FD-SOI technology featuring undoped ultrathin silicon film (tSi = 7 nm), buried oxide (tBOX = 25 nm) and epitaxial layer reducing the series resistance (tepi = 15 nm).

(

  via ground plane, VGB) bias. Each region can be N-type, P-type or fully depleted depending on the gates bias which leads to 9 possible configurations as shown in Fig.2.2. The name Hocus-Pocus was given to reflect the versatility of our structure to change configuration from one embodiment to many others[2].

Figure 2 . 2 .

 22 Figure 2.2. The HP diode with 9 different configurations according to the front and back gates bias.

Figure 2 . 3 .

 23 Figure 2.3. Experimental I-V characteristics of P-N virtual diodes for different carrier concentrations. (a) VGF = -1.2 V (red curve), -1 V (black curve) and VGB = +5 V, (b) VGF = -1.2 V (red curve), -1 V (black curve) and VGB = +10 V The reverse current is in absolute value. Diode configuration as in Fig. 2.1 with Lin = Lg = 500 nm, width = 100 µm, T = 300 K.

Figure 2 . 4 .

 24 Figure 2.4. Experimental I-V characteristics of a P-N virtual diode for different carrier concentrations. (a) VGF = -1.2 V (red curve), -1 V (black curve) and VGB = +5 V, (b) VGF = -1.2 V (red curve), -1 V (black curve) and VGB = +10 V The reverse current is in absolute value. Diode configuration as in Fig. 2.2A with Lin = Lg = 500 nm, width = 100 µm, T = 300 K.

Figure 2 .

 2 Figure 2.5 shows the forward I-V characteristics and ideality factors (n from I = I0 (e qV/nkT -1))of the virtual P-N diode emulated in HP diode. It exhibits all the regions of standard operation documented for physically doped P-N diode[6]:

Figure 2 . 5 .

 25 Figure 2.5. Forward current-voltage characteristics of the HP diode (configuration Fig. 2.2A) measured for variable bias on front and back gates: VGF = -1.6 V and VGB = +5 V (black curve), VGF = -1.2 V and VGB = +10 V (red curve), VGF = -2 V and VGB = +15 V (blue curve), (a) Semi-log scale, (b) linear scale and (c) ideality factor. Parameters as in Fig. 2.3.

Figure 2 . 6 .

 26 Figure 2.6. Simulated 2D distribution of the gate-induced carrier concentrations near the virtual P-N junction. The black dotted contour delimits the space charge region. VGB = |VGF| = 2.5 V, VA = VK = 0, Lin = Lg = 200 nm and T = 300 K, (b) Current-voltage characteristics and (c) corresponding ideality factor.

Figure 2 .

 2 Figure 2.7. (a) Schematic of P * doping change by VA < 0 bias. Virtual diode characteristics measured by grounding either the anode or the cathode. (b) VGF = 0 and VGB = +10 V, (c) VGF = -2 V and VGB = +10 V. Lin = Lg = 500 nm, width = 100 µm, T = 300 K.

Figure 2 .

 2 Figure 2.8. I-V characteristics of the HP diode operated as semi-virtual diodes (b) and (c) compared to the virtual diode (a). Gate bias: (a) VGF = -2 V and VGB = +10 V, (b) VGF = -2 V and VGB = -10 V and (c) VGF = +2 V and VGB = +10 V. Other parameters as in Fig. 2.7.

Figure 2 . 9 .

 29 Figure 2.9. SUSS Microtec cryoprober for low temperature measurement.

  2.2A) is formed at the left extremity of the gate. The average virtual doping level is calculated with MOS theory: N * ~ CBOX(VGB -VK -Vtb) and P * ~ COX(VGF -Vtf), where COX,BOX and Vtf,b are the oxide capacitances and threshold voltages at the front/back interfaces [6]. The doping level reaches ~ 10 19 cm -3 . Experimental I-V curves are shown in Fig. 2.10. At room temperature, the diode characteristics correspond to the classic behavior I ≈ IS exp(qV/nkT) of a physically doped diode [6]. The current is dominated successively by carrier recombination (n = 2 for |VK| < 0.8 V), diffusion (n = 1 for |VK| > 0.8 V) and finally by high injection and series resistances, as documented in [6]. As the temperature decreases, the turn-ON voltage shifts to higher voltage. The typical characteristics of Esaki diode are clearly observed at 77 K as shown in Fig. 2.10b. The negative differential resistance (NDR) is captured around VK = -0.8 V with maximum tunneling current of 5.5 A/cm 2 and convincing peak-to-valleycurrent-ratio (PVCR) of 3.59.

Figure 2 . 10 .Figure 2 .

 2102 Figure 2.10. Temperature dependence of HP diode characteristics. At 77 K, Esaki diode characteristic is observed with PVCR = 3.59 at VGF = -1.4 V and VGB = +10 V.

Figure 2 . 12 .Figure 2 . 13 .

 212213 Figure 2.12. Esaki diode characteristics at high gate voltage. (a) Log-scale and (b) linear scale at 77 K and VGB = +10 V.

Figure 2 . 14 .

 214 Figure 2.14. Simulation results of a virtual Esaki diode. (a) Profiles of electrostatic doping and contours of space charge region, (b) band diagram according to the depth in the film. VA = +0.04 V, VGF = -2.5 V, VGB = +2.5 V and T= 77 K.

Fig. 2 .

 2 Fig. 2.15, low-voltage region where the current increases exponentially is observed. This mode of operation corresponds to two forward-biased side diodes connected through the large series resistance of the body. At higher voltage (> 1 V), the device enters in double injection mode dominated by the excess electron-hole plasma in the body. The current is following a power law, I ~Vm , where m tends to 2 [27].

Figure 2 .

 2 Figure 2.15. I-V characteristics of several P-I-N diodes emulated in the same device. (a): VGF = VGB = 0; (b): VGF = -2 V and VGB = 0; (c) VGF = 0 and VGB = +10 V. Other parameters as in Fig. 2.3.

Figure 2 . 17 .

 217 Figure 2.17. The schematic of (a) Zerbst method and (b) double-gate deep-depletion lifetime extraction technique.

Figure 2 .

 2 19 shows the variation of the ideality factor n, calculated from I = I0•exp(qV/nkT -1), between recombination (n ≈ 2) and diffusion (n ≈ 1). The transition voltage V * is defined when the two currents are equal. As V * varies with doping and is difficult to extract, we use instead the corresponding ideality factor. To find the relevance of the ideality coefficient as a metric, calculations were performed with standard diode equations for various combinations of doping concentrations and carrier lifetimes (Fig.2.20). The results indicate that the ideality factor n is systematically ~ 1.33 at transition voltage V * . Therefore, we

Figure 2 . 19 .

 219 Figure 2.19. Ideality factors. (a) GO1: Lg = Lin = 200 nm, width = 1 μm, (b) GO2: Lg = Lin = 500 nm, width = 100 μm, T = 300 K.

Figure 2 .

 2 Figure 2.20. (a) Simulation of recombination and diffusion current in a basic diode with physical doping (NA= ND = 5×10 19 cm -3 ). The transition point is where the recombination and diffusion current are identical. (b) Ideality factor is ~ 1.33 at the transition point.

Figure 2 .

 2 Figure 2.21. (a) Simulated forward I-V characteristics of a conventional P + -N diode for variable recombination lifetime. (b) Corresponding ideality factors.

Figure 2 . 22 .

 222 Figure 2.22. Reverse recovery current measured on a virtual diode. (a)VA sweep, (b)VK sweep, (c) VA sweep with different biases and (d) VK sweep with different gate biases. GO2, Lg = Lin = 500 nm, width = 100 µm, T = 300 K.

Figure 2 . 23 .

 223 Figure 2.23. Reverse recovery current measured on a virtual P-N diode with different VA ramp time: (a) 0.07 μs, (b) 0.09 μs, (c) 0.2 μs and (d) 0.3 μs. GO2, Lg = Lin = 134 nm, width = 112 nm.

Figure 2 .

 2 23 shows a marked transformation of the recovery transient signature. From panel (a) to panel (d), the switching is slower, resulting in a longer storage delay time and a lower reverse current. Obviously, Eq. (2.12) will deliver different lifetime values according to the ramp speed which is not acceptable. In order to eliminate parasitic capacitive effects and determine the accurate parameters to insert in Eq. (2.12), we follow the systematic correction procedure proposed by Dutta et al.[45].

Fig. 2 .

 2 Fig. 2.24a shows linear variation of the delay time with the ramp time. Extrapolation at tRamp = 0 yields the delay time (~ 60 ns) that would correspond to a perfectly vertical switch, as assumed in the model of Eqs. 2.11 and 2.12. The measured reverse current is affected by the parasitic capacitance

Figure 2 . 24 .

 224 Figure 2.24. Linear fit of measured (a) storage delay time td and (b) measured reverse recovery current Imeas of a full-bodied P-N diode. GO2, Lg = Lin = 134 nm, width = 112 nm.

  2.25) with virtual half-body diodes obtained by extending the P + terminal (VGF > 0, Fig. 2.26) or the N + terminal (VGB > 0, Fig. 2.27) into the body. These P-I-N diodes match better the device configuration used to devise the recovery transient model [48]. Figures 2.25

- 2 .

 2 27 show the extraction of the genuine values of delay time and reverse current from the raw

Figure 2 . 25 .

 225 Figure 2.25. Linear fit of measured (a) storage delay time td and (b) measured reverse recovery current Imeas of a full-bodied P-I-N diode. GO2, Lg = Lin = 134 nm, width = 112 nm.

Figure 2 . 26 .

 226 Figure 2.26. Linear fit of measured (a) storage delay time tsd and (b) measured reverse recovery current Imeas of a right half-bodied P-I-N diode. GO2, Lg = Lin = 134 nm, width = 112 nm.

Figure 2 . 28 .

 228 Figure 2.28. Measured forward current versus gate bias in a fully depleted P-I-N gated diode. (a) Impact of back-gate voltage for VA = +0.5 V, VK = 0. (b) Influence of the anode voltage. Diode length = 400 nm, width = 100 µm, T = 300 K.

Figure 2 . 27 .

 227 Figure 2.27. Linear fit of measured (a) storage delay time tsd and (b) measured reverse recovery current Imeas of a left half-bodied P-I-N diode. GO2, Lg = Lin = 134 nm, width = 112 nm.

Z 2 -

 2 FET (Zero Impact Ionization and Zero Subthreshold Slope Field Effect Transistor) works in forward bias operation of a gated P-I-N diode by inducing electrostatic barriers using the front-gate (VGF) and back-gate (VGB) biases. The current blocking is achieved by creating a thyristor-like NPNP structure via gate controlled band-modulation. The flattening of these electrostatic barriers results in a sharp switch of the current level of the diode. The blocking/unblocking of the current in Z 2 -FET is a

Figure 3 . 1 .

 31 Figure 3.1. (a) Experimental hysteresis in IA-VA curves of Z 2 -FET for different VGF by VA ramping, (b) experimental IA-VA curves for different gate voltages by forcing the anode current to reach the S-shaped curve. Lg = Lin = 200 nm, width = 100 μm, T = 300 K and VGB = -1 V.

Figure 3 .

 3 Figure 3.1 shows hysteresis in experimental anode current (IA)-anode voltage (VA) characteristics for various front-gate voltages in standard Z 2 -FET (Fig. 2.1). The back-gate bias VGB is kept at -1 V in order to form an electron injection barrier (N + P). For increasing VA, unlike standard P-I-N diode, Z 2 -FET remains OFF until the turn-ON voltage (VON) is reached. At VON, the current undergoes a sharp transition turning the device ON. VON strongly depends upon the applied gate voltages. The value of the minimum VON is higher or equal to a standard silicon diode turn-ON voltage. Depending on the applied VGF, VON can exceed a silicon diode turn-ON voltage (~0.6 V) from 100 mV to 1 V. The occurrence of the steep switch also differentiates Z 2 -FET from a standard diode operation. During the reverse sweep, i.e., the use of a lower anode voltage, results in different turn-OFF voltages (VOFF < VON). The modulation of VON and VOFF allows to induce a hysteresis. The width of the hysteresis window increases with VGF as a result of the progressive shift of VON due to stronger barriers created by the gates.

Figure 3 . 2 .

 32 Figure 3.2. ( a ) Applied voltage pattern for voltage ramp, (b) IA-VA characteristics for current ramp (snapback) and slow voltage ramp (hysteresis) for τmax of 10 -9 s and 10 -10 s (simulation) [12]. For holes, τmax is taken as 0.3 times of the τmax for electrons (default value), τmin = 10 -12 s and Qox = 10 11 ~ 2×10 12 cm -2 .

Figure 3 . 4 .

 34 Figure 3.4. Electrostatic potential profile at the center of the device (y = TSi/2) (a) during OFF stat e (simulation) and (b) during the exponential and ON states (simulation) [12].

Figure 3 .

 3 Figure 3.7 shows the bias pattern used for Z 2 -FET memory operation. With the help of numerical simulations, we can follow the evolution of the injection barriers and carrier populations during the critical steps of the memory cycling. The simulations have been performed with a given set of parameters (length, thickness, carrier lifetime and mobility). Modification of these parameters does not change qualitatively the sharp switching ability of the Z 2 -FET, albeit VON is modified. The numbers in Fig. 3.7 indicate the biasing points that are further elaborated in Figs. 3.8 to 3.19. Each figure shows the barrier heights (left panel), the electron concentration (center) and the hole concentration (right).

Figure 3 . 7 .

 37 Figure 3.7. Chronogram of memory operation indicating the steps elucidated in the following figures.

Figure 3 . 8 .

 38 Figure 3.8. Quasi-DC initial state. Potential barriers and electron/hole concentrations along the device.

Figure 3 . 11 .

 311 Figure 3.11. Evolution during Hold '0'.

Figure 3 .

 3 Figure 3.10. Write '0' stage.

Figure 3 . 9 .

 39 Figure 3.9. Evolution during the gate voltage drop before writing '0'.

Figure 3 . 12 .

 312 Figure 3.12. Evolution during the rise of anode voltage in preparation of reading '0'.

Figure 3 .

 3 Figure 3.13. Read '0' state.

Figure 3 .

 3 Figure 3.20 confirms that band-modulation effect enables sharp switching characteristics (< 1

Figure 3 .

 3 Figure 3.19. (a) Read '1' turns the diode on. (b) Comparison of the injection barriers during reading '0'and '1'-states.

Figure 3 .

 3 Figure 3.20. IA-VA characteristics of the Z 2 -FET depending on the front-gate bias: (a) VGB = -0.5 V, (b) = VGB = -1 V, (c) VGB = -2 V. Lg = Lin = 200 nm, width = 100 μm and T = 300 K.

Fig 3 .

 3 21b and 3.22b.

Figure 3 . 21 .

 321 Figure 3.21. Short standard pattern. Operation of Z 2 -FET under proper biased conditions (a) VGF = 1.3 V, VA = 1.2 V. The output signal shows that the '0'-state starts to be degraded when Z 2 -FET is out of the proper bias range as (b) VGF = 1.2 V, VA = 1.2 V. VGB = -1 V, Lg = Lin = 200 nm, width = 100 μm and T = 300 K.

Figure 3 . 22 .

 322 Figure 3.22. Long standard pattern. The operation of Z 2 -FET under proper biased conditions (a) VGF = 1.3 V, VA = 1.1 V. The output current shows that the '0'-state is degraded when Z 2 -FET is out of the proper bias range as (b) VGF = 1.15 V, VA = 1.05 V. VGB = -1 V, Lg = Lin = 200 nm, width = 100 μm and T = 300 K.

Figure 3 .

 3 Figure 3.24. '1'-state reading current versus VA reading voltage for different VGF. VGB = -1 V, Lg = Lin = 200 nm, width = 100 μm.

Figure 3 .

 3 Figure 3.23. Imax-VGF curve of the Z 2 -FET with different VA when programming/reading '1'-state with (a) 13 μs and (b) 1.3 ms period pattern at room temperature. The black line indicates the VGF limit values when the '0'-state starts to be degraded. VGB = -1 V, Lg = Lin = 200 nm, width = 100 μm and T = 300 K.

Figure 3 .Figure 3 . 29 .

 3329 Figure 3.25. Logic '1' (a) and '0' (b) read currents versus front-gate voltage VGF for variable anode voltage VA. Lg = Lin = 200 nm, width = 100 μm and T = 300 K.

Figure 3 . 30 .

 330 Figure 3.30. The constant reading test for programming '0' and '1'-state. No degradation for the '0'-state is observed for (a) VA = 1.05 V and VGF = 1.25 V. The '0'-state degradation appears for (b) VA = 1.1 V and VGF = 1.25 V, and (c) VA = 1.05 V and VGF = 1.2 V. There is no '0'-state degradation for VA = 1.1 V and VGF = 1.3 V. The '1'-states are always stable. VGB = -1 V, Lg = Lin = 200 nm, width = 100 μm and T = 300 K.

Figure 3 .

 3 Figure 3.31. IA-VA characteristics of the Z 2 -FET showing hysteresis according to the front-gate bias at (a) 25 ℃, (b) 100 ℃ and (c) 130 ℃. (d) Turn-on voltage of Z 2 -FET depending on the temperature for each gate bias. VGB = -1 V, Lg = Lin = 500 nm and width = 100 μm.

  3.31a-c, the anode output current IA is shown as anode voltage VA is swept at room temperature, 100 °C and 130 °C . From the room temperature to 100 °C , the IA-VA characteristics remain consistent. At 110 °C , the leakage or current increase and the memory window is shifted to the left. In other words, the turn-ON voltage starts to decrease at 110 °C (Fig. 3.31d).

Figure 3 . 32 .

 332 Figure 3.32. Standard memory operation of the Z 2 -FET with VGF = 1.2 V and VA = 1.1 V at (a) 25 ℃, (b) 100 ℃ and (c) 130 ℃. (d) Maximum current of '0'-and '1'-state according to the temperature. VGB = -1 V, Lg = Lin = 500 nm and width = 100 μm.

Figure 3 .

 3 Figure 3.34 shows the IA-VA characteristics of the dual ground-plane Z 2 -FET featuring the best performance in terms of memory window and variability. A smaller gate bias, VGF = 1 V, is sufficient to obtain enough memory window in DC operation.

Figure 3 .

 3 Figure 3.35 shows the memory performance of dual ground-plane Z 2 -FET with VGbP = -2 V, VGbN = +2 V. Anode voltage defines the '1'-state current regardless of the gate bias as in standard Z 2 -FET and current ratio is very high I1 ~ 32 μA/um at VA = 1.1 V. The key difference compared to the

Figure 3 .

 3 Figure 3.34. IA(VA) DC characteristics of dual ground plane Z 2 -FET. (a) Lg = Lin = 200 nm, width = 500 nm and VGbP = -1 V and VGbN = +1 V, (b) same device as (a) with VGbP = -2 V and VGbN = +2 V.

Figure 3 . 33 .

 333 Figure 3.33. Schematic of Z 2 -FET in 14 nm FD-SOI node technology with dual ground-plane.

Figure 3 . 35 .

 335 Figure 3.35. Standard memory operation of dual ground plane Z 2 -FET depending on the bias (VGbP = -2 V, VGbN = +2 V). Lg = Lin = 200 nm, width = 500 nm and T = 300 K.

  Fig. 3.37) while reading or programming '1'-state of the selected one (WL1). The principle relies on the barrier strengthening by increasing the gate bias in WL2 and WL3 during the reading or programming of WL1.

Figure 3 . 37 .

 337 Figure 3.37. The schematic of the Z 2 -FET memory array without selector.

Figure 3 . 39 .Figure 3 . 38 .

 339338 Figure 3.39. The operation of Z 2 -FET (VA = 1 V) showing that current is not blocked for (a) VGF = 1.25 V. The output signal shows that the device is blocked for (b) VGF = 1.3 V. Lg = Lin = 200 nm and width = 100 μm and T = 300 K.

Figure 3 .

 3 Figure 3.39b and 3.40b show that the reading '1' current can be completely blocked when the

Figure 3 . 40 .Figure 3 . 41 .

 340341 Figure 3.40. Operation of Z 2 -FET at increased anode voltage (VA = 1.05 V). The current in WL2 and WL3 is not blocked for VGF = 1.3 V (a) and is blocked for VGF = 1.37 V (b). Lg = Lin = 200 nm and width = 100 μm and T = 300 K.

Figure 3 . 42 . 3 . 5 . 1 . Z 2 -Figure 3 .

 34235123 Figure 3.42. Patterns applied to the Z 2 -FET for transient measurements for longer 'read' in WL2. Reading operation for (a) 6 μs and (b) 7 μs. Lg = Lin = 200 nm and width = 100 μm and T = 300 K.

Figure 3 .

 3 Figure 3.44. (a) Device switch at VGF = 1.5 V and VGB = 0 V, showing the impact of VA, (b) Device switch at VA = 0.8 V and VGB = 0 V, showing the impact of VGF. tSi = 7 nm, Ln = Lp = 500 nm, width =100 µm and T= 300 K.

Figure 3 .

 3 Figure 3.44a shows pulsed characteristics obtained by VGF sweep. First, VA is swept up from the reference voltage (0.5 V due to equipment limitations). The device stays OFF when the VGF is high and turns ON when VGF is pulsed down. Then, pulsing up VGF successfully turns the device OFF, which is the key result for logic applications.

Figure 3 .

 3 Figure 3.45. (a) Device switch at VGF = 1.2 V and VA = 0.8 V showing the impact of positive and negative VGB, (b) OFF current depending on VGB. tSi = 7 nm, Ln = Lp = 500 nm, width =100 µm and T= 300 K.

  3.46 for pulse signals with various rise times. Switch ON occurs naturally in Z 2 -FETs due to barrier collapse which is facilitated by the gate discharge current ΔQG/Δt. When the gate signal drops, the extra charge ΔQG to be eliminated gives rise to a current able to turn the device ON [6]. The shorter the fall time of the pulse, the more effective the discharge current is.

Figure 3 . 46 .

 346 Figure 3.46. Device switch at VGF = 1.3 V and VA = 0.8 V showing the essential role of fall.time of VGF. tSi = 7 nm, Ln = Lp = 500 nm, width =100 µm and T= 300 K.

Figure 3 .

 3 Figure 3.47. IA(VGF) transfer characteristics for various anode bias VA at VGbP = -1 V, VGbN = 0 V. For VA = 1.1 V, the barrier is improved at VGbP = -1 V, VGbN = +1 V. tSi = 12 nm, Ln = Lp = 138 nm and Width = 300 nm.

Figure 3 . 49 .

 349 Figure 3.49. Dynamic subthreshold-swing (SS) of the Z 2 -FET logic switch. tSi = 12 nm, Ln = Lp = 200 nm and T = 300 K.

Figure 3 . 48 .

 348 Figure 3.48. Gate switching showing the impact of (a) VGbN and (b) VGbP on OFF state current in dual groundplane Z 2 -FET. tSi = 12 nm, Ln = Lp = 200 nm and T = 300K.

Fig. 1 . 2

 12 Fig. 1. (a) Vue schématique d'un Z 2 -FET standard, (b) Transistor reconfigurable à nanotubes de carbone, (c) Diode graphène monocouche, (d) Transistor à nanofil de Si avec une grille de commande centrale et deux grilles adjacentes qui programment les barrières Schottky pour former des MOSFET ou TFET à canal N et à canal P.

Fig. 2 .

 2 Fig. 2. Caractéristiques expérimentales I-V des diodes virtuelles P-N pour différentes concentrations de porteurs. (a) VGF = -1.2 V (courbe rouge), -1 V (courbe noire) et VGB = +5 V, (b) VGF = -1.2 V (courbe rouge), -1 V (courbe noire) et VGB = +10 V. Le courant inverse est en valeur absolue. Configuration de la diode avec Lin = Lg = 500 nm, W = 100 µm, T = 300 K.

Chapitre 3

 3 La motivation pour développer des DRAM Z 2 -FET à 1 transistor (1T) a été documentée en tant que cible des cellules mémoire basse consommation. La commutation rapid de Z 2 -FET et son application en tant que DRAM-1T ont été décrite en révélant les mécanismes détaillés qui se produisent lors des opérations quasi-statiques, transitoires et mémoire (Fig.4). Les expériences et les simulations ont été axées sur les dispositifs fabriqués avec la technologie FD-SOI 28 nm. La nouvelle technologie FD-SOI 14 nm a également été étudiée en insistant sur le rôle des plans de masse doubles contrôlant respectivement les sections du corps couvertes et non-couvertes par la grille. La mémoire Z 2 -FET est inégalée en termes de temps de rétention, de faible consommation d'énergie, de marge mémoire et de lecture non destructive. Un autre avantage pratique est la compatibilité totale avec le processus FD-SOI, sans qu'aucun module technologique supplémentaire ne soit nécessaire. Nous avons démontré expérimentalement un fonctionnement en basse tension avec une polarisation de lecture d'environ 1 V et une polarisation de programmation aussi faible que 0,5 V (Fig.4b). Ces atouts rendent le Z 2 -FET

Fig. 4 .

 4 Fig. 4. (a) Hystérésis dans les courbes expérimentales IA-VA de Z 2 -FET pour différentes tensions VGF, (b) Opération de Z 2 -FET dans des conditions de polarisation appropriées pour l'application mémoire: VGF = +1.1 V, VA = +1.05 V et VAprog1 = +0.5 V.

Fig. 5 .

 5 Fig. 5. (a) Caractéristiques de transfert IA (VGF) pour différentes polarisations anodiques VA à VGbP = -1 V, VGbN = 0 V. Pour VA = +1.1 V, la barrière est améliorée à VGbP = -1 V, VGbN = +1 V. tSi = 12 nm, Ln = Lp = 138 nm et largeur = 300 nm, (b) commutation de porte montrant l'impact de VGbN.

  and interaction between smart objects (devices with embedded sensors, on-board data processing capability, and means of communication). Since IoT is the convergence of memory, sensor, information, communication, and actuation technologies, they will use smaller and more energy efficient embedded

	sensor/communication technologies, advanced data analysis, and more sophisticated actuators to collect
	and process information. As IoT field is growing rapidly, new memory technology suited for their
	design is demanded. The crucial requirement for IoT memory is low power operation because it must
	be kept always in ON-mode. In addition, most of IoT devices will use multichip-package (MCP) designs
	to incorporate the CPU, GPU, memory and flash memory in one chip. As a result, developers have to
	reconsider their design goals, by using memory in new and innovative ways. The vast majority of
	embedded memories are currently charged based (DRAM, FLASH) or flip-flop based (SRAM). The
	other alternative storage options (which are not yet mature from commercial perspective) can be
	grouped into three categories: ReRAM (resistive) or MRAM (magnetic), and body-charged memories
	(so called floating-body DRAMs, FB-DRAMs).

  OxRRAM is an interesting alternative because it relies on a Metal/Insulator/Metal (MIM) stack and has better compatibility with CMOS processes. In addition, Cubased Resistive Random Access Memory (Cu-ReRAM) [61] technology shows <10 ns Set/Reset speed and 10 M cycles of program endurance with huge capacity but they are still prototypes. In general, ReRAM are foreseen only as Flash replacement.

	compatibility [58]-[60].
	Resistive Random Access Memory (ReRAM) cells work on the principle of reversible
	switching of certain dielectrics between a conductive and a more resistive state under suitable bias
	conditions (Example in Fig. 4.1). These two states can represent the logic values '1' and '0', respectively.
	Conductive Bridge RAM (CBRAM) [57] takes advantage of a reversible creation of an
	electrochemically induced nanoscale conductive link in a special dielectric acting as an ionic conductor
	(so-called memristor behavior). The process of writing '1' and '0' in CBRAM cells is very fast (10-100
	ns) and low-power. However, CBRAM is suited only as an important contender for Flash storage, since
	it cannot reach yet the DRAM or SRAM requirements essentially due to endurance issues and CMOS

Table 2 .

 2 1. Carrier lifetime extracted in standard SOI P-N diode from simulations of the transition between recombination and diffusion regimes and from the recombination current.

Acknowledgements

This 3 years journey would not have been possible without the dedicated support of such is the most sensitive parameter. Z 2 -FETs with dual ground-plane show the best potential.

Abbreviations

The Hocus-Pocus diode:

-Fabrication

-Device operation -Applications

Configuration (A): The virtual P-N diode is obtained by biasing negatively the front-gate to induce a positive charge (virtual doping P * ) that extends the anode P + contact into the body. At the same time, a positive back-gate bias generates an electron charge (virtual doping N * ) which expands the cathode N + contact. The details are discussed in sections 2.3.1-2.3.4.

Configuration (B), (C):

The semi virtual P-N diode is obtained by negatively (B)/positively (C) biasing both of the two front and back gates to induce a virtual doping P * /N * that extends the anode P + contact (B)/cathode N + contact (C). The details are discussed in section 2.3.5.

Configuration (D), (F):

The half-bodied P-I-N diode (D) is emulated by positive front-gate bias for the extension of P + anode terminal (VGB = 0). Contrarily, the half-bodied P-I-N diode (F) is obtained by negative back-gate bias extending the N + anode terminal (VGF = 0). The details are discussed in section 2. 4.

Configuration (G), (H):

The device (G) has positively biased front-gate and grounded back plane.

Device (H) is obtained by negatively biasing the back plane with grounded front-gate. Details are given in section 2.5.2.

Configuration (I):

The thyristor-like N + P * N * P + structure is formed with positive front-gate bias and negative back-gate bias. The concept is introduced in section 2.5.2 and more details are discussed in chapter 3.

There are two major differences compared to the charge plasma diode which inspired the development of the HP diode concept [3]- [5]:

-The carrier type and the electron and hole concentrations are tunable on demand, by controlling the gates bias, rather than being fixed by the selected metal work-functions.

-For the virtual P-N diode, the P * and N * regions are in contact as in a conventional P-N diode.

On the other hand, the charge plasma diode works more as a P-I-N diode due to the intergates separation.

The virtual P-N diode

Typical I-V characteristics of the electrostatic P-N diode (Configuration A) are shown in Fig. In forward mode (VA > 0), structure (Fig. 2.16a) operates in Z 2 -FET band-modulation mode.

The curve is totally different with the current increasing abruptly at a given voltage. The injection of holes from P + terminal and of electrons from N + terminal is blocked by gate-induced potential barriers.

Therefore, the current remains very low until a triggering voltage is reached and enables positive feedback between the two barriers [29]- [31]. The NPNP structure resembles a thyristor, except that the inner P * and N * regions are virtual and Z 2 -FETs are free of impact ionization and body contacts. The hysteresis is due to the difficulty to re-build the potential barriers once the P-I-N diode operates in double-injection regime. The hysteresis window in Fig. 2.16b is used for 1T-DRAM memory [31], [32] and ESD protection devices [30], [33] working principle. Details about Z 2 -FET operation are discussed in chapter 3.

Lifetime extraction in ultrathin film

Lifetime extraction methods

The carrier lifetime is an important figure of merit for evaluating the crystal quality of

Lifetime extraction methods using Hocus-Pocus diode

In this section, we introduce, adapt and compare several methods for lifetime evaluation in ultrathin FD-SOI devices by taking advantage of the flexibility of the HP diode. We exploit the forward diode characteristic by focusing on the transition between recombination and diffusion current. First, lifetime is calculated either from the transition point (where the recombination-dominant and diffusiondominant currents are equal) or from the recombination/diffusion current in section 2.6.2.1-2. A second approach is by adopting the Reverse Recovery Transient (RRT) method, pioneered by Kingston [46] and explained in section 2.6.2.3. It monitors the recovery current as a function of time just after the P-N diode has been switched sharply from ON to OFF state. The RRT technique can be adapted to virtual P-N and P-I-N diodes, for consistent lifetime determination in ultrathin FD-SOI. The carrier lifetime values are compared with those obtained by applying Ernst's method [47] to ultrathin SOI films in section 2.6.2.4.

Forward I-V characteristics

Only the forward I-V characteristic is considered because the reverse current is either too small (within the noise level of the measurement) or affected by band-to-band tunneling which makes the extraction procedure inaccurate or very complicated. Figure 2.18 illustrates the successive regions of operation of a P-N diode: recombination current, diffusion current, high-level injection and series resistances [6]. For V > 6kT/q, the reverse current contribution is negligible and the current-voltage relationship becomes exponential: For simulating the DC I-V curves for Z 2 -FET two approaches were followed: (1) voltage ramping and, (2) current ramping. To avoid convergence failure in the case of a voltage ramp, a slow anode voltage transient is applied as shown in Fig. 3.2a. Prior to a slow VA ramp (50 s from 0 V to 2 V), fast transient (10 ns) pulses were applied at both gates (VGF, VGB) to emulate a similar biasing environment of DC experimental measurements. The obtained hysteresis (Fig. 3.2b) between the increasing and decreasing VA is similar to the experimental data (Fig. 3.1a). On the other hand, the Sshape snapback curves (Fig. 3.2b) was reproduced by anode current ramping as in the experiment (Fig.

3.1b

). It is interesting to note that the snapback, which depicts the negative resistance region, is embedded within the hysteresis window. prior to VA slow ramp (simulation) [12]. The gates are ramped from 0 V to 1.2 V with a fast pulse (100 ns) followed by VA pulse (as for the DC simulation case). This means that the two wells are filled by the gate pulses before ramping VA. Faster

Transition between DC and pulse mode

VA ramp time has two important effects: (1) higher VON, and (2) high leakage current during the OFF state. We can consider the case of 100 ms ramping time as a quasi-static DC operation. For faster ramp times (< 10 ms), additional transient effects (mainly linked to the carrier lifetime and displacement currents) affect the Z 2 -FET characteristics. The characteristics depending on the ramp time highlight the difference between DC operation and pulse mode Z 2 -FET operation. In transient or pulsed modes, when the electron/hole concentrations do not reach the steady-state, the IA-VA characteristics are modified. For example, when the gate is pulsed from 0 V to a positive voltage, electrons are expected to fill the gated region. However, there is no source of electrons other than the generation process or junction leakage. Since electrons cannot be supplied promptly enough, the body potential is in nonequilibrium condition anymore (similar state as in the deep depletion mode of MOS capacitors [14], [15]). As a result when the ramp time decreases, the energy barrier opposing the injection of holes from anode is temporarily increased and the turn-ON voltage VON is higher (Fig. 3.5). The shorter the pulse, the higher the VON. Therefore, the selection of reading operation voltage VA is very critical for the memory application. If VA is higher than the transient VON, the device always turns ON, preventing any difference between states '0' and '1'. Similarly, there is no memory effect when VA is smaller than the DC VON because the device is unable to turn ON. The proper choice of VA is between VON values in DC and transient modes: the device turns ON for state '1' reading and remains blocked for state '0' reading. lowering the operation voltage. In Fig. 3.6a, a VA value slightly smaller than the DC VON is chosen, hence a relatively long pulse (quasi-static DC mode) for read '1' cannot unblock the device since VA is not high enough to collapse the barrier. However, for very fast VA pulse, the device turns ON being triggered by the gate discharge current ΔQG/Δt as shown in Fig. 3.6b and explained in [1].

Shorter pulse duration also reduces the time when the device is in ON state: the device dissipates less power. Indeed, our measurements with 320 ns pulse (equipment limitation) show energy saving by 2 orders of magnitude compared with 120 µs pulse, without any degradation in memory performance. Simulations anticipate successful operation at 1ns access time. The memory keeps working even at 0.1 ns at the expense of degraded current margin (higher I0 current) [6]. continues to attempt increasing.

Pre-Write '1' (Fig. 3.15) -As VA increases again, the hole barrier is immediately reduced. In the gated region, the electron concentration decreases because the gate bias is less effective (VGF -VA), and more holes arrive.

Write '1' (Fig. 3.16) -The gate is pulsed down to 0 V and the anode voltage is high. As soon as VGF is brought to 0 V, both barriers collapse and the central junction becomes forward biased. The P-I-N diode 112 is ON and the concentrations of electrons and holes are high and comparable everywhere in the body.

Post-Write '1' (Fig. 3.17) -Even if VGF returns to high level (1.2 V), the diode is still in ON state.

Hold 'W1' (Fig. 3.18) -The gate bias returns high. Only after VA is pulsed to 0 V are the barriers reconstructed. The device is in equilibrium state, therefore, the barriers are lower than the Hold '0' situation (Fig. 3.14) and turn-ON voltage decreases. The electron concentration is far higher than in Hold '0' which enables discriminating '1'-and '0'-states.

Read '1' (Fig. 3.19a) -The anode pulse turns on the diode. The barriers are lower than in the '0'-state and high current flows. The VA pulse is now able to collapse both barriers bringing high current and electron/hole concentrations.

In conclusion, the transient memory characteristics of Z 2 -FET are governed by the barrier modulation. Figure 3.19b shows the status of the injection barriers for reading '1' and '0'. '0'-state means that the device is blocked and the barrier is high with negligible current flow. In contrast, in '1'state, the current flows because the barriers are demolished.

Retention

The ability to keep the states after 'writing' is one of the most crucial issues in memory performance. Our memory retention is defined by the time needed for electrons to repopulate under the gate region during the hold '0'-state. The '1'-state is stable and does not require refresh. The read '1'state current consists of electron and hole contributions and is high. The electrons are blocked by the barrier during the 'Hold'.

To test the retention of the Z 2 -FET, different patterns are applied. One pattern consists of programing ('0' or '1'-state) operation followed by a reading/holding cycle. Figure 3.27-28 show the pattern of programming of '1' or '0'-state in 200 ns with 150 μs hold and read sequence (total period of 4.3 ms). The programming of '1'-state followed by reading-holding cycles does not reveal any 119 degradation (Fig. 3.27) thanks to the '1'-state stability (equilibrium-state, section 3.2.3). For the '0'state retention (Fig. 3.28a), the front-gate bias needs to be few tens of millivolts higher than the anode voltage to operate the Z 2 -FET without degradation during the cyclic read-hold operation. The '0'-state is clearly degraded if the front-gate bias is not high enough, see Figs.

Conclusion and Perspectives

This study was aimed at exploring the concept and applications of Hocus-Pocus (HP) diode in 28 nm and 14 nm FD-SOI technology nodes. The crucial principle of the device, electrostatic doping, can be seen as two different perspectives:

- Although this work attempted to provide a detailed study of HP diode and applications, several aspects could not be fully covered. They deserve to be addressed in future investigations:

-Investigation of the virtual Esaki diode in a new technology node.

-Transfer the concept of HP diode to FinFETs, tri-gate, and nanowires architectures.

-Further Z 2 -FET structures optimization and reliability tests.

-1T-DRAM cell array simulation and benchmark.

-Advanced investigation of 14 nm node technology as a 1T-DRAM and logic switch. À des fins de comparaison, les mesures antérieures effectuées sur des dispositifs FD-SOI plus épais, pour lesquels la contribution de l'interface est moins sévère, ont donné des valeurs de durée de vie autour