M Antoine Frappé

M Andreas Kaiser

Keywords: WiFi, WiGig, IEEE 802.11ac, IEEE 802.11ad, WLAN, Transmitter, Multi-standard, Multi-band, Multi-mode, Configurable, DAC, FIR, DRFC, DDRM, High pass, Low pass, Band pass, Delay line, Filter, Delta-Sigma, Half-Band, DSP, CMOS, FDSOI, 28nm

Proliferation of application specific wireless communication standards have resulted in the multiple standards, multiple devices for one user scenario of today. Consequently, research in multi-standard, and multi-band systems, architectures, and circuits has been a popular theme. The vision is to have devices which can hope seamlessly from one network to the other while delivering excellent functionality on different radio access technologies.

Configurable transmitter architectures targeting complementary use cases of the multi-Gb/s WiFi-WiGig standards have been studied. Novel approaches based on high speed configurable semi-digital FIR DACs are proposed and published in international journal. In this architectures, transmitter mask and linearity requirements are respected because the single-bit FIR DAC is inherently linear and combines in its functionality both digital-to-analog conversion and filtering of noise. A delta-sigma modulator can be employed for resolution conversion so that baseband signals with wide range of bandwidths and resolutions are processed.

FIR DACs require long filters with high resolution coefficients to achieve stopband attenuation levels that meet out-of-band noise requirements. Normally, this limits high speed multi-standard operation, and results in large silicon area and complex layout. In this work, circuit techniques are developed so that a unit circuit element realizing a coefficient of one transfer function can be re-used in realizing a different-valued coefficient of another transfer function. This multi-modal hardware-sharing capability of the FIR DAC is maximized by system-level coefficient optimization.

The work also proposes topologies that exploit digital signal processing at advanced nodes to implement quadrature modulation while realizing up conversion, digital-to-analog conversion and image and quantization filtering in one configurable passband FIR DAC block. A prototype high pass filter FIR DAC chip which can be configured for the operation of the IEEE 802.11ac and IEEE 802.11ad standards was implemented in STMicroelectronics R CMOS 28nm FDSOI technology. The test of this chip has demonstrated the validity of the proposed transmitter architectures. The prototype chip can process passband OFDM signals as wide as 136 MHz at a clock frequency of 3 GHz and reaches an output carrier frequency of 1.5 GHz in the 802.11ac mode. It also can channelize random SC signals as wide as 700 MHz at a clock frequency of 1.4 GHz and reaches an output carrier frequency of 700 MHz. The chip has a total power consumption 103.07 mW in the 802.11ac and 86.89 mW in the 802.11ad modes at 1.4 GHz clock frequency. It is supplied with three separate voltage

Acknowledgments

These past three years and eight months have been a period of personal journey. It was also a period of education and development for me as a researcher. More importantly, though, it has given the opportunity to interact with a number of wonderful people. This PhD work has come to fruition due to the enormous help many individuals have been kind enough to provide it me.

I would like to bestow my heartfelt gratitude to my director of research, Prof. Andreas Kaiser. I have been fortunate enough to learn from him and work with him. His guidance through out my research work has been invaluable, and the standard he sets as a professional is something I have personally admired. I would also like to thank my supervisor, Dr. Antoine Frappé, for his dedication, kindness and keeping his office door always open for every one of my questions.

Since my initial correspondence with the SMART Integrated Circuits Design Group in early 2013, I have benefited immensely from the generosity of the team members. Dr. Bruno Stefanelli has shared with me his valuable experience during my presentations, design reviews, chip assembly and measurement. Dr. Jean-Marc Capron was always there for my presentations, and he is a genuinely nice person. I thank Dr. Axel Flament for his comments and for coming to my presentations. Thank you, Axel, also for the enjoyable afterwork football matches. Florence Alberti welcomed me to this beautiful city on a Sunday morning at Euralille. I would like to thank her for guiding me through the intricate world of French administration.

I would like to thank members of the Silicon Microelectronics Group at IEMN, specifically Prof. Emmanuel Dubois, Dr. Jean-François Robillard, and Matthieu Berthomé. Thank you Dr. Pascale Diener for helping me with the pick and place machine during the chip assembly.

My test chip characterization has been carried out at the IRCICA Telecom Platform during many months. I would like to extend my sincere gratitude to Rédha Kassi and his coworkers for making it convenient for me to work there. I would like to thank the following past and present members of the SMART-ICD Group: fellow PhD students Dr. Baptiste Grave, Dr. Ilias Sourikopoulos, Cristian Marin, Justine Philippe, Matteo Causo, Dr.

Camilo Salazar and Dipal Ghosh; postdocs Dr. Pietro Maris, Dr. Stephane Mebaley Ekome, Dr. Walid Bourennane and Dr. Benoit Larras for their support. I have shared the office with Dipal and Walid for a year now, but it is like they were here for a couple of months. It was great discussing with you all the interesting questions of Science, Technology, History and, of course, 140 GHz oscillator. iv Chapter 0. Acknowledgments I have shared the longest part of my stay with Ilias and Cristian. I thank them for their advices and friendship. It was a pleasure to have shared with you the many fun lunch times. They are some of the highlights of my stay in Lille. Pietro, Stephane and Bruce Ferrer for their friendship during their stay here in Lille. It was great to have you guys around.

I also would like to thank the employees of ISEN Lille which were always glad to help me in the rare cases I had asked for it. Thank you Nathalie Rousseau, Josée Vanbouvelen, and others. Valérie Vandenhende is a pleasant person and a great ambassador to the school. 6.13 Model of equivalent impedance of routed data lines for coefficient 32 with 254 UCCs . . 102 6.14 RC interconnect models that can be used for fast, less accurate estimation of delay . . . 103 6.15 The layout view of the a five-stage driver used for the biggest coefficients in the center of the 802.11ac impulse response. Additional stage inserted not to invert the data. Supply connected using parallel thin wires to ensure low current density. . . . . . . . . . . . . . 105 6. 16 The clock is distributed with a seven stage clock tree to the UCC array, and a single leaf of this tree to the delay line. The inverters in the tree are sized have a fan out of 4. This is kept in the inverter chain to the delay line using dummy inverters. . . . . . . . . . . . 106 6.17 The layout view of the final stage buffers of the clock tree. Each PMOS and NMOS are sized 2 6 times the first stage transistors. The fingers are arranged as such so that the clock tree outputs of each of the 64 rows are routed straight to the UCC array with short wires and with minimum distance between the rows of the UCC array. . . . . . . . . . . . . . 107 the transmitter chain as it determines the maximum achievable carrier frequency and the corresponding signal bandwidth, spectral purity of the analog output, and the lowest power consumption and circuit area that can be targeted.

Even though the solid literature in the area of traditional multi-bit DAC has eased the burden of derivation required in the design of a configurable multi-standard FIR DAC, the scarcity of works in the specific area of high speed configurable FIR DACs required analysis of each design decision and has led to some original contributions.

A top-down research methodology was followed during implementation of the FIR DAC chip. The specifications for the baseband transmitter system were based largely on IEEE 802.11ac and IEEE 802.11ad transmitter standard requirements. Specification for each block in the baseband chain, mainly the FIR DAC block, were then drawn; and those were translated as targets for the parameters of the FIR DAC circuit. Then, simulation at transistor, layout and extracted abstraction levels were carried out until the desired margin was respected.

2

Chapter 1. Introduction

Original contributions

These are the main original contributions of this PhD work:

• Novel digital wireless transmitter architectures based on:

low pass filter FIR DAC high pass filter FIR DAC band pass filter FIR DAC

• System-level validation of a configurable low pass filter FIR DAC transmitter as communicated in [START_REF] Tsigabu | A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards[END_REF] • A semi-digital FIR DAC for LP SC 60 GHz IEEE 802.11ad as communicated in [START_REF] Tsigabu | Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60GHz transmitter[END_REF] • Matlab based modeling and simulation alogrithms for EVM of a IEEE 802.11ac/ad transmitter • Chapter 5: presents the system-level validation of the baseband of a digital transmitter based on a low pass filter FIR DAC. High level design and simulation results of each block of the transmitter are included. The chapter ends with further discussion of the high level design of a configurable FIR DAC.

•
• Chapter 6: details the circuit implementation of a prototype configurable FIR DAC in 28nm CMOS FDSOI. A novel pseudo double common centroid placement method, and the FIR DAC floorplan are discussed. Design of each block of the prototype converter are presented in great detail.

• Chapter 7: is where the results of the measurement of the prototype are explored. The experimental setup, the different ways by which the configurable FIR DAC is characterized are elaborated.

• Chapter 8: stipulates the main conclusions. It also extends the scope of this work by proposing plausible future research directions.

Chapter 2

Wireless Communication Systems

The aim of this chapter is to give an overview of wireless communication standards. It covers a bit of history and a bit of the expected future of communication standards. Since the focus of this work is on multi-mode DAC for multi-standard transmitters, some motivations are listed in this chapter. It starts with evolution of standards in section I. In section II, a discussion of challenges and solutions with regard to 5G networks in included. The prototype chip targets the complementarity that exists in the WiFi-WiGig use cases; it is in section 3. The chapter closes with a customary summary and conclusions section.

Aggregation of Standards

Cellular technology has evolved from the analog, voice only 1G to the current Gb/s data rate LTE-A 4G standard. To accommodate this increase in throughput, the transmission frequencies has also increased from sub-GHz carrier frequency to 2-3 GHz range that is at work today. However, this increase is not totally attributed to increase in available transmission bandwidth. One technology that contributed to this increase is the evolution of access technologies from FDMA to TDMA to CDMA to contemporary access technology based on OFDM.

The same can be said of the evolution of the WLAN standards, namely WiFi. It has evolved from the early 2 Mb/s data rate local area network to the current multi-Gb/s 802.11ac/ad standards. Other standards including short distance, low power Zigbee and Bluetooth, and long distance, low data rate GPS still add their own set of requirements on the design of devices.

Therefore, the proliferation of application specific wireless communication standards have resulted in the multiple standards, multiple devices per user scenario of today. The need for design of multi-standard devices is exacerbated by the crowded spectrum, and the resulting tough out-of-band requirements. Moving to higher carrier frequency, and, thus, broader bandwidths could relax the requirements, and fulfill the increasing demand for faster communication rates. However, the challenges of designing multi-standard devices at higher carrier frequencies or broader bandwidths will be harder to overcome.

Innovation in access technologies, similar to the gains made by using OFDM, will not suffice either.

A single innovation in either of transmission frequency, access technologies, channel bandwidth, or type The evolution of theoretical data rates of cellular and WiFi standards through the years is plotted in Figure 2.1. The latest standards of WiFi achieve several Gb/s data rates-with the 802.11ac at 160MHz and the IEEE 802.11ad at 2.16GHz maximum channel bandwidths. The uplink and downlink data rates of the latest cellular standard also reaches Gb/s with a maximum of 20MHz channel bandwidth. There is, however, a difference in the achievable distance between these standards. For example, IEEE 802.11ad has an expected reach of less than 10 m. Future networks can be envisioned where the capabilities in both short and long distance standards are combined seamlessly for best user experience. In the next section, a brief summary of the discussion on future 5G networks is presented. The METIS project, in its initial project, had also set five requirements that a mobile network in 2020 should support with the same cost and energy dissipation of contemporary networks. These are 1000x increase in mobile data throughput, 10 to 100x increase in number of connected devices and increase in user data, 10x longer battery life for low power massive machine communication, and 5x reduced end-to-end latency [START_REF] Olav | [END_REF]. These are achievable objectives with the technologies available today, but require innovation at the network, system and architecture levels.

Networks of the future

Some of the techniques that has been mentioned for meeting these requirements include increase in bandwidth by moving to new unlincensed spectrum, denisification of networks with shorter transmission distance, massive MIMO with greater antenna elements, more efficient transmission schemes to improve OFDM, and flexible radio interfaces [START_REF] Olav | [END_REF].

Chapter 2. Wireless Communication Systems

Challenges and Solutions

Many of the proposed solutions are an extension of the current technologies. Still, there are many challenges that have to be overcome. A good depiction of the capabilities of a 5G device, with a focus to the communication block, is in Figure 2.4. It shows the challenges and the expected innovations at different parts of the device. For example, of interest to the scope of this work are the number of RATs the transceiver baseband is expected to process, the multi-standard design at the RF parts of the transceiver and the resulting challenges at the front-end module, and the expected challenges of a multi-antenna operation. In this subsection, a brief discussion of the challenges and solutions proposed for future 5G networks are presented.

One of the proposed solutions to free up spectrum and serve more users is decreasing the distance between base stations also called densification. While this allows the incorporation of short-distance communication standards in the 5G network, it faces some challenges, among which the cost of increased infrastructure due to deployement of large number of base stations within small area, and the support of fast and efficient handoff in an environment where there are many RATs [And+14].

A more viable solution for future high data rate networks is increasing bandwidth in an unlicensed spectrum. The challenges to this solution in the PHY layer are design of power efficient and small form factor transceiver architectures that can support MU-MIMO, and antennas that overcome the propagation loss and atmospheric absorption at mm-waves. These challenges are already being tackled by circuit and antenna designers at this time to some degree. Yet, novel architectures may be needed if massive MIMOs are to be part of mobile terminals [START_REF] Bangerter | Networks and devices for the 5G era[END_REF].

Another solution for increasing throughput is novel spectral efficient modulation technique and access technology. While OFDM is a widely used modulation technique, it presents drawbacks. One is the high PAPR that limits the linearity and efficiency of power amplifiers although this may not be a critical problem in a dense network where the transmitted signal does not need to have high power. The other is the need for synchronization and the fact that a big part of an OFDM symbol is taken by the guard interval. It is also a usual practice to fill the edge of an OFDM symbol with null subcarriers. This also results in decreasing the spectral efficiency of OFDM. A technology where the advantages of OFDM are kept with improvements on its drawbacks will be important for 5G networks. Some candidate technologies are already being proposed to supercede OFDM in a 5G network. They are discussed in detail in [START_REF] Banelli | Modulation Formats and Waveforms for 5G Networks: Who Will Be the Heir of OFDM?: An overview of alternative modulation schemes for improved spectral efficiency[END_REF].

The WiFi-WiGig Complementarity

The The 802.11ac and 802.11ad standards have created a good test case for seamless operation of short distance and medium distance communications. Due to its high data rate at low power capabiities, 802.11ad can be used for tasks that require small time duration. For instance, device-to-device data transfer, wireless sync, and wireless display to name a few. Hence, it can be turned on for such tasks. On the contrary, the 802.11ac requires higher power consumption to reach Gb/s data rates. Thus, it is better suited for medium distance, traditional local area network applications.

Tri-band WiFi Radio

The 802.11n, 802.11ac and 802.11ad stretch the reach of WiFi from the crowded 2.4 GHz bands, to 5 GHZ, and mm-wave frequencies respectively. Both 802.11ac and 802.11ad are backward compatible.

802.11ac can be considered as a 5 GHz, wide channel bandwidth version of 802.11n. The idea of triband radio is to employ 2.4 GHz 802.11n for existing networks, 802.11ac for new faster medium distance applications, and 802.11ad for short distance, low power applications [START_REF] Verma | Proliferation of Wi-Fi: Opportunities in CE ecosystem[END_REF].

There has been some demonstration of this idea in commericial products with the Intel R Tri-band Wireless-AC 17265 and WiGig Antenna-M10041R. The research in this area is to maximize hardware sharing between the mm-wave 802.11ad and 5 GHz 802.11ac while guaranteeing good performance.

Under the WENDY project of the French National Research Agency, the idea of tri-band radio was targeted. The objective of the project was to research techniques by which a 60 GHz standard could be part of the WiFi ecosystem with respect to how its use cases are entertained and how its circuits are implemented. It targeted the second generation of WiGig based products-the first being standalone WiGig chipsets. Although WiHD was released earlier than WiGig, it specifically targets video streaming application as HDMI cable replacement and was not suited, for instance, with respect to cost, for wireless transfer of general data of other nature.

To implement a highly integrated, configurable and low power tri-band transceiver, the MAC, digital baseband, and the RF front-end circuits should be configurable for operations in all bands. A common frequency synthesizer can deliver a low phase noise signal to all the baseband and mixing blocks at low power constraints. In the RF front-end, the project investigated among other issues how to:

• digitally process baseband signals ranging from 20 MHz to 2 GHz,

• implement digital-to-analog conversion of those baseband signals, and

• upconvert and downconvert IF and RF transmission frequencies of as diverse as 2.5 GHz, 5 GHz, 20 GHz and 60 GHz.

The general block diagram of the transceiver is shown in Figure 2.5. Prototype chips were fabricated for some parts of the tranceiver. In the receiver side, subsampling techniques were employed to solve the problems listed above [START_REF] Baptiste Grave | A Reconfigurable IF to DC Sub-Sampling Receiver Architecture With Embedded Channel Filtering for 60 GHz Applications[END_REF]. In the frequency synthesizer, a wide tuning range mm-wave voltage controlled oscillator was implemented in CMOS 28nm FDSOI [START_REF] Vallet | A mmW low power VCO with high tuning range in 28nm FDSOI CMOS technology[END_REF]. In the transmitter side, it should be understood that the starting objective of this thesis work was to investigate the questions listed above.

Summary and conclusions

An overview of wireless communication standards commensurate with the scope of this dissertation is presented. Special attention has been given to future networks in line with the initial aim of this PhD work. Recent literature on future 5G networks from both academia and industry is briefly introduced with focus on the challenges and proposed solutions.

Finally, a summary of the ANR project, WENDY, under which this work was started is introduced.

The objective of the project was to demonstrate next generation tri-band WiFi transceiver. Design of a configurable mixed-signal block in the transmitter part of such a transceiver was the initial goal for this work.

Chapter 3

Multi-standard Digital Transmitters

This chapter investigates the methods that can be implemented for multi-standard transmitter operation.

Before that, it will introduce briefly the theoretical operation of a transmitter. Signal processing in cartesian, polar and outphasing transmitter systems is discussed along with modulation schemes. The first section is closed with a highlight of the fundamental transmitter metrics such as transmit mask, EVM, and ACPR.

In the next section, I/Q transmitter architectures are discussed with additional details. It starts with classical architectures such as direct conversion or low-if, heterodyne or two-step transmitter architectures, and ends with a review of modern architectures used in wireless devices. Only the architectures with relevant specs will be discussed.

The last part of this chapter is a theoretical discussion of the possible methods available for implementing a multi-standard transmitter using the traditional architectures. The focus is on the opportunities in the baseband part of the transmitter. Similar to the previous section, this section closes with a mention of recent publications of multi-standard transmitters.

Brief Theory of Transmitter Operation

From the scope of this dissertation, the name transmitter will refer to the blocks in the lower part of Figure 3.1. However, for completeness, a general block diagram of a WLAN transmitter is shown including the MAC layer. The MAC layer prepares the data units that are exchanged with the PHY according to the transmission format of the standard. It adds the necessary header and defines the payload structure for each user. For example, the 802.11ac standard defines a MU-MIMO capability where an access point transmits data units to multiple receiving stations with one or more antennas. In this case, the MAC layer could define multiple independent data units. The data bits are filled in the PHY layer.

The physical layer mainly performs FEC, and modulation in its digital baseband part and, traditionally, frequency translation, digital-to-analog conversion, filtering and amplification in its analog/RF part. Modulation consists of constellation mapping where bit streams are mapped to complex constellation points, and where the complex symbols are converted to time domain blocks. In a single carrier Chapter 3. Multi-standard Digital Transmitters modulation transmitter, only constellation mapping is done, and the rest of the functions fall under the responsibility of the analog/RF designer. In other words, they are not necessarily implemented in digital baseband. That is the case in 802.11ad where the mapped high speed baseband data can be upconverted and converted to analog without much digital processing (more on this later).

However, advancement in digital signal processors have enabled digital implementation of traditionally analog blocks. The possibility to tune and calibrate digital circuits for best performance have relegated the analog implementation only to the blocks close to the antenna such as the power amplifier or co-existence band pass filter. With this comes the opportunity to implement different standards using one digital hardware. This is the main topic of the final section of this chapter.

MAC Digital Baseband

Analog &RF

Modulation

D A

Error Correction Figure 3.1: Essentials blocks of a basic WLAN transmitter. In traditional transmitter, the mixer follows the DAC. However, they can also be implemented in the same circuit.

Modulation

Modulation is the mapping of information carried in one electrical signal, called the modulating signal, into the amplitude, frequency, and/or phase of another signal, called the carrier. Modulation has many advantages in wireless communication which are well covered in many wireless communication text books [START_REF] Haykin | Communication systems[END_REF].

Single Carrier

There are three main modulation types. AM is when the modulating signal controls the amplitude of the carrier, it is FM when it controls the frequency, and PM if the modulation is on the phase of the carrier.

Both FM and PM are called angle modulation because, ultimately, both phase and frequency variation can be obtained by varying the angle of the carrier. Each modulation types have different bandwidth efficiency. Probability of error versus energy per bit per spectral noise density ( E b N o ) graphs are used for comparing different modulations schemes.

An analog signal modulated by a single carrier of frequency, f c , can be generally expressed in polar form as: y(t) = a(t)cos(2π f c t + θ(t)).

(3.1)

This can be expanded to:

y(t) = a(t)cos(θ(t))cos(2π f c t) -a(t)sin(θ(t))sin(2π f c t). (3.2)
The cartesian form of the modulated signal is then:

y(t) = x I (t)cos(2π f c t) -x Q (t)sin(2π f c t).
(3.3)

Where x I (t) = a(t)cos(θ(t)) and x Q (t) = a(t)sin(θ(t)). The modulating signal x(t) is generally given by:

x I (t) + jx Q (t) = a(t)e jθ(t) .
The amplitude a(t) follows the modulating signal, x(t), in AM with no modulating signal information on the phase θ(t); and the angle θ(t) varies according to the modulating signal, x(t), in angle modulation with no modulating signal information on the amplitude a(t). In digital modulation, the modulating signal is a sequence symbols. ASK, FSK, and PSK are the digital modulation versions of AM, FM and PM respectively. There are higher order digital modulation schemes such as M-PSK, M-ASK, and M-QAM which are more spectrally efficient. The constellations of 16-QAM and π 2 -QPSK are shown as an example in Figure 3.2.

OFDM

Modern wireless communication standards such as IEEE 802.11ac rely on different mechanisms to increase spectral efficiency. Higher order modulation schemes are used to reach Gb/s data rates, for example, 256-QAM in 802.11ac. In addition, OFDM is used to increase throughput in a crowded spectrum.

The basic stages in the generation of one OFDM symbol in the baseband of a transmitter is shown in Figure 3.3. The stream of bits are converted to parallel and are mapped to N subcarriers according the complex constellation points of the modulation scheme selected. Then the orthogonal subcarriers are summed using an IFFT or IDFT block and converted to time domain. A guard interval is inserted at the end of the summed signal to prevent inter-symbol interference due to multi-path propagation. The IFFT output and the guard interval, can be implemented using cyclic prefix, form an OFDM symbol.

An example based on the 802.11ac standard is given in Figure 3.4 and 3.5. The symbol is generated by mapping a random bit stream to 468 16-QAM data subcarriers, 16 pilot subcarriers and the remaining The roles of the remaining transmitter blocks are, basically, converting this signal to analog, frequency translating it to the band allocated to the standard and amplifying it. The first task can be carried out by using multi-bit DAC. The output signal, in time-domain, shown in Figure 3.5, has multi-bit resolution with the high magnitude samples occuring less frequently. The high magnitude samples can be clipped to relax the requirements on the DAC [START_REF] Denis | Analysis of clipping effect in DMTbased ADSL systems[END_REF]. The SNR loss that results from this process should not degrade the EVM to a degree where the remaining transmitter blocks are put on stringent EVM requirements. Depending on the constellation size, number of subcarriers of the OFDM modulator, Frequency translation of the OFDM modulator output can be carried out in single stage or two-step depending on the transmitter architecture. It can also be implemented by digital upconversion if the mixer precedes the DAC, but this requires an RF DAC. If cartesian transmission is required, then the real and imaginary components of the OFDM output signal has to be transmitted separately using I/Q transmitter architecture [START_REF] Razavi | RF microelectronics[END_REF]. One of the main alterantive is to convert the complex samples to their amplitude and phase components and impart the amplitude on the phase modulated component in the amplifying block or upconversion block in a polar transmitter architecture [START_REF] Wang | An improved Kahn transmitter architecture based on delta-sigma modulation[END_REF].

Chapter 3. Multi-standard Digital Transmitters

Cartesian Transmitters Architectures

Frequency translation is basically time-domain multiplication of the baseband output by an exponential signal at the desired carrier frequency, f c . It is generalized by Equations (3.1) and (3.3) for SC signal.

Mathematically, y(t) = x(t)e j2π f c t (3.4) For a complex modulating signal x(t), y(t) can expressed by expanding the real, x I (t), and imaginary,

x Q (t), components of x(t) and multiplying by the exponential. Further, the exponential can be expanded using Euler's formula to its trigonometric equivalents:

y(t) = x I (t) + jx Q (t) cos(2π f c t) + j sin(2π f c t) (3.5) y(t) = x I (t) cos(2π f c t) -x Q (t) sin(2π f c t) + j x Q (t) cos(2π f c t) + x I (t) sin(2π f c t) (3.6)
Therfore, complex upconversion can be achieved with four multipliers, two adders and a single-tone signal and it's 90 0 shifted component [START_REF] Martin | Complex Signal Processing is Not Complex[END_REF]. Downconversion of the transmitted output is easily down by replicating the upconversion process in the receiver. There are practical problems resulting from the difference of the carrier signals in the receiver and transmitter sides, but theoretically x(t) is fully recovered.

In I/Q modulation transmitter, upconversion is carried out with only the real part of Equation (3.4) as shown in Equation (3.7). This is possible because a real upconverted signal has also an image on the negative frequency. If the transmitted output signal is multiplied by the same orthogonal functions, cosine and sine, in the receiver, x(t) can still be recovered after filtering. The clear advantage is the ease of generating the cosine and sine signals and the reduced number of multiplication and additions required. Both x I (t) and x Q (t) are translated to f c andf c . The downside of using real version of the complex modulation is the image filtering problem in the receiver. Quadrature modulation is then:

y(t) = x I (t) cos(2π f c t) -x Q (t) sin(2π f c t) = x(t)e j2π f c t (3.7)

Direct Conversion Transmitter

Direct implementation of Equation (3.7) results in a single-step upconversion transmitter architecture, also known as direct conversion transmitter, shown in Figure 3.6. If there is no filter between the summed output of the mixers and the power amplifier, carrier leakage to the output from the mixers could be problematic [START_REF] Razavi | RF microelectronics[END_REF]. Another problem is the receive band noise floor can be affected by the outut from

f LO1 + f LO2 .
Quadrature modulation is performed at lower frequency with less effect from the PA. Nevertheless, the mixing products in the two blocks can interfere with each other and proper filter is required [START_REF] Razavi | RF microelectronics[END_REF]. Another problem of the heterodyne transmitter is the effect of the increased number of filtering and mixing stages on silicon area and power consumption.

Polar Transmitter Architecture

An alternative architecture to the cartesian-based transmitters is a polar transmitter architecture shown in Figure 3.8. The amplitude, also envelope, and the phase of the OFDM or SC baseband output are extracted for separate digital or analog processing. In a conventional architecture, the envelope controls the supply of a non-linear amplifier while the angle modulated bandpass signal is its input. It performs both PM and FM as ω(t) = dθ(t) dt . The angle modulator can be a PLL with a DCO or a VCO. One of the main limitation of this architecture is inherent to the nature of its amplitude and phase inputs. The fact that amplitude and the phase can change abruptly lowers the spectral efficiency of this architecture. This can be explained by following how the amplitude and the phase change during constellation mapping.

Any two consecutive data to be transmitted can take any two values in the complex constellation of the modulation scheme selected. This means the in-phase and quadrature components can assume any two values, 0 or 1, and change to the other in the next. Then there is a chance that the amplitude or magnitude of the complex points can move from a III-Quadrant to the I-Quadrant, from the IV-Quadrant to the II-Quadrant, or vice versa. This causes the amplitude component to abruptly change its timedomain value which creates a wideband spectra full of harmonics in the frequency domain. Similary, there is a chance the phase component can change its value abruptly by 180 0 which requires also broad bandwidth.

Thus, the polar architecture needs around 3 times bandwidth of their cartesian counterparts for effective representation of its amplitude and phase components [START_REF] Werquin | Multiple Rates Multiple Paths Wideband Digital Transmitter With Low Spurious Emissions Applied to Opportunistic Radio[END_REF]. With limitation in maximum sampling frequency due to technological and power consumption issues, this main problem of the polar architecture limits its applicability to narrow-band applications. Another major disadvantage with this architecture is the different amplitude and phase branches. For perfect operation, the timing of the two branches has to be matched. This is difficult given the fact that they have different circuit blocks in each branch unlike the I/Q modulator. Dummy blocks can be inserted to lower the timing misalignments [START_REF] Pieter | Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission[END_REF].

A critical difference between the polar and the I/Q modulator transmitter is the way the output is obtained. In I/Q modulator, the output is a linear sum, at least ideally, but in the polar architecture it is a product of amplitude and phase components. This means spurs from each of the branches can mix and move to the desired bandwidth [START_REF] Pieter | Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission[END_REF].

Innovative circuit techniques have been used to mitigate most of the problems discussed above. A great deal of that discussion is in [START_REF] Pieter | Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission[END_REF][START_REF]Multi-mode/multi-band RF transceivers for wireless communications: advanced techniques, architectures, and trends[END_REF]. For the sampling frequencies, and signal bandwidths targeted in this work, the polar transmitter is less effective. Hence, the reviews of the transmitters in this remaining part of this chapter are focused on the I/Q modulation architecture.

Transmitter Performance Metrics

Here some important transmitter parameters are defined. They are useful to the discussions in this manuscript. The main metrics are EVM, the spectral mask of the transmitter output, ACPR in the case of a simulation/measurement carried out using a proper channel of a standard. The simulation of the proposed transmitter architecture in Chapter 5 is assessed based on the parameters that will be briefly discussed in this subsection. There are also some less reported results at the baseband part of the transmitter such as the spectrum flatness. It is a measure of how much difference in power there is between the spectral tones of a desired channel bandwidth. A brief discussion of the rest follows.

Error Vector Magnitude

EVM is one of the parameters by which the modulation accuracy of a transmitter is measured. It is a measure of the degree by which the actually transmitted bits, after reception, decoding and measurement, are different from the intended ideal constellation. For example, for the SC PHY EVM of the 802.11ad, the EVM is calculated according to the formula [START_REF]telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements. Part 11, Amendment 3[END_REF]:

EV M = 20 log 10 1 N s P avg N s i=1 I i -I * i -I 0 2 + Q i -Q * i -Q 0 2 dB (3.8)
Where N s is the number of samples, P avg is the average power of the ideal constellation, I * i and Q * i and I i and Q i are the coordinates of the complex points of the i th ideal and measured symbols respectively.

I 0 and Q 0 are complex DC components which the designers can chose so that the EVM is reduced.

Several factors contribute to the degradation of the EVM. In an I/Q transmitter, an imbalance, whether in gain or phase, between the two channels leads to a shift of the received constellation points. Every circuit block in each channel contributes to this imbalance. In baseband, the bits to be transmitted are shaped using a pulse shaping filter to reduce ISI [START_REF] Gu | RF system design of transceivers for wireless communications[END_REF]. These filters are designed for a flat passband so Chapter 3. Multi-standard Digital Transmitters that the frequencies components, or subcarriers in the case of OFDM, at the edge of the band does not experience a different gain.

Transmitter Spectrum Mask

The transmit mask defines the level of the output transmitted power at different frequencies from the center of the band. It is a primary restictions of a given standard. There are additional far-out spectrum restictions such as the out-of-band noise profile. The transmitter output power spectral density should be such that it does not raise the receive-band noise floor of communication standards at nearby frequencies.

A discussion of this in relation to IEEE 802.11ad and IEEE 802.11ad standards is in available in Chapter 5.

Adjacent Channel Power Ratio

The occupied power is integrated for a given channel at a given resolution bandwidth of the output transimtted spectrum. The ratio of the occupied power of the main desired channel bandwidth to be transmitted to the adjacent channel is expressed by ACPR. ACPR is also sometimes called Adjacent Channel Leakage Ratio. The center of the upper and lower adjacent channels are usually defined as BW, the desired bandwidth, away from the center of the main channel bandwidth, i.e. with no gap between the main and the adjacent channels. Similar expression can be specified also for the upper and lower alternate, sometimes nonadjacent, channels. The ratio of the power occupied in the main channel to that of the upper or lower alternate channel is called the Alternate CPR. An illustration of these definitions are shown in Figure 3.9. In this figure, f c is the carrier frequency at which the desired channel is transmitted. Some standards such as GSM and CDMA specify the width of the adjacent channel and the offset frequencies at which the estimation or measurement should be done.

Review of Digital Transmitter Architectures

Advanced CMOS technologies have opened the opportunity to leverage digital signal processing in assisting or replacing the analog front-end of wireless transmitters. The objective in the design of transmitter has been then to push the realm of DSP towards the antennna at the same time reducing the pure analog blocks. As the DSP blocks are more scalable, and configurable, the transmitter as a system becomes more flexible for multi-modal operation.

Architecturally, there has been attempts, regardless of their effectiveness, in simplifying or totally taking out the analog reconstruction filter following the DAC, even pushing the digital implementation all the way to the final amplifying stages by driving the PA by digital signals in PDAC-based transmitters.

In this section, recent digital transmitters in literature are discussed.

Digital Quadrature Modulators

Traditionally, quadrature modulation is carried out using multipliers. Multiplier-free digital domain implementation of quadrature modulation is reported in [START_REF] Vankka | A digital quadrature modulator with on-chip d/a converter[END_REF]. Selected samples of the orthogonal Cosine and Sine signals are multiplied with input I and Q digital signals for frequency translating these inputs to fractional frequencies of f s -anywhere from baseband (low pass) to f s 4 (band pass) to f s 2 (high pass) sections of the first Nyquist zone. The output summed complex data was used to drive a 12-bit segmented DAC to obtain the analog IF. The concept is validated for GSM, EDGE, and WCDMA. The desired transmit filters are met by oversampling the input I and Q signals using half-band interpolation filters.

Due to the limit on the highest sampling rate of the DAC, 500 MHz, the digital quadrature modulation of the above implementation was valid only as replacement for the first analog mixer stage. Another frequency translation stage is required.

A more advanced CMOS node was used in [START_REF] Frappe | An All-Digital RF Signal Generator Using High-Speed ÎΣ Modulators[END_REF] where the first 1-bit digital RF signal generator using delta-sigma modulation was reported. It implements the baseband DSP and I/Q modulation of a delta-sigma based digital-IF transmitter in 90nm CMOS chip. A low pass delta-sigma modulator converts a moderately oversampled high resolution input to single-bit as shown in Figure 3.10. This architecture is validated for WCDMA application and some cases of the UMTS standard. A higher frequency band is achieved in this work, and it shows that the 1-bit digital I/Q modulated output, f clk 4 , can be directly used to drive a DAC without the need for analog frequency translation. In [START_REF] Flament | A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner[END_REF] the realm of the digital is further pushed to the antenna by feeding the digital 1-bit output to PDACs to implement the power amplifier. Quantization noise filtering is performed using bandpass FIR filters embedded in the PDAC structure.

The above two works show that for below 3-GHz bands, an analog frequency translation circuit may not be needed. Direct digital-to-analog conversion of the output of a digital quadrature modulator may suffice. To reach higher bands, though, different architectures have been proposed. One of them is using RF DACs. In the following sub-section, works employing the RF DAC concept are reviewed.

The RF DAC Concept

The RF DAC concept is the mergig of the digital-to-analog converter and mixing stages of a direct conversion transmitter into a common circuitry. In a current-steering architecture, the unit cell of the conventional DAC is replaced by the circuit of a Gilbert mixer whose RF inputs are driven by digital data destined to the DAC [START_REF] Mohr | An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS[END_REF]. With some design choices, such as the LO frequency being at integer multiples of the clock driving the digital data so that the output power is higher than what is normally achieved with a sin(x)/x response of the DAC, the conversion and mixing functionalities are delivered [START_REF] Luschas | Radio frequency digital-to-analog converter[END_REF].

RF DAC In Direct Conversion Architectures

Early demonstration of the RF DAC concept is in [START_REF] Zhou | A 10-bit wide-band cmos direct digital rf amplitude modulator[END_REF] using L-fold interpolation. In ZOH sampling, a data is sampled by a clock rising or falling edge and the next data in the next clock cycle. The idea with L-fold interpolation is instead of waiting for the next clock cycle holding the actual value, the output of the DAC can be made to progressively increase/decrease, L times, in one clock cycle. Since the holding times are shorter, Fourier Series indicates that the frequency response rolls faster for a high image rejection. However, due to increased number of unit current cells and high number of clock activity, high power consumption is expected. The concept is demonstrated for L=16, for a 3.3 MHz input bandwidth at 50 MHz clock and 1 GHz carrier frequencies. Another early demonstration of the RF DAC concept using an RZ output is in [START_REF] Luschas | Radio frequency digital-to-analog converter[END_REF] for a half-GSM bandwidth of 17.5 MHz at a center frequency of 942 MHz in 0.18µm CMOS. The carrier frequency reached, however, does not show the advantage of the RF DACs over the digital quadrature modulators discussed above.

Naturally, a high order analog output LC BPF is used for filtering of emissions in RF DACs. In [START_REF] Eloranta | A Multimode Transmitter in 0.13Î 1 4[END_REF], a DDRM, shown in Figure 3.11, was implemented in 0.13µm CMOS. Front-end digital filters are used for performing most of the transmit mask requirements of GSM/WCDMA/WLAN standards.

In this work, the output of the DDRM can be transmitted without an additional frequency translation circuit.

The number of mixing unit cells of the RF DAC can be lowered by inserting a delta-sigma modulator.

The shaped quantization noise is filtered by a combination of output analog filter and high OSR. This method increases the operating speed and results in higher power consumption. In [START_REF] Pozsgay | A fully digital 65nm CMOS transmitter for the 2[END_REF], a combination of FIR and IIR digital filters perform most of the channel shaping while oversampling the data by In [START_REF] Morteza | A Wideband 2x13-bit All-Digital I/Q RF-DAC[END_REF], digital IQ modulation is further pushed to include some level of power amplification using digital-to-RF amplitude converters. The converters are formerly used in a polar transmitter architecture in [START_REF] Cruise | A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS[END_REF]. They are combined with the RF DAC concepts in a direct conversion transmitter architecture.

The I/Q modulation is carried out using four 25% duty-cycle non-overlapping LO signals. Each LO phase switches either positive or negative components of the in-phase or quadrature inputs. Output summing is realized by using an on-chip balun combining network. The concept is demonstrated in a 2x13-bit DAC 65nm CMOS implementation. ACPR of -19dBr is obtained for a 154.1 MHz bandwidth, 1024-QAM, SC input at 2.4 GHz output frequency, and up to -44 dBr ACPR for 7 MHz input using digital predistortion.

RF DAC in Heterodyne Architectures

In [START_REF] Jerng | A Wideband Digital-RF ÎΣ Modulator for High Data Rate Transmitters[END_REF], shown in Figure 3.12, two-step upconversion is implemented in a direct-conversion transmitter architecture. Delta-sigma modulators are used for lowering input data resolution in a moderate OSR operation. The first-step complex mixing translates the digital data to f clk 4 while canceling either negative or positive frequency replicas. The second-stage upconversion is implemented using an RF DAC with an output 4 th -order Bessel LC BPF tunable for a wideband 260 MHz transmission.

In two-step upconversion digital transmitters, the RF DAC can implement second stage mixing of summed complex data. Thus, the I/Q modulation can be performed in the first stage mixing at lower speeds. In [START_REF] Taleie | A Linear ÎΣ Digital IF to RF DAC Transmitter With Embedded Mixer[END_REF], shown in Figure 3.13, a digital-IF heterodyne transmitter [START_REF] Leung | Digital-IF WCDMA handset transmitter IC in 0.25-Î 1 4 m SiGe BiCMOS[END_REF] inspired architecture implements a bandpass delta-sigma modulator that converts the high resolution quadrature output to single-bit stream for second-stage upconversion using FIR RF DAC. The filtering of the shaped quantization noise is performed using the embedded six-tap bandpass FIR filter of the RF DAC. Depending on the order of the FIR filter, the output analog filter is relaxed. Any analog filter implemented is only for far-out spectra filtering to mitigate emission to nearby communication. For high stopband rejection and meeting the transmit mask requirements of modern wireless standards, the FIR filter has to be high order with high resolution coefficients. This digital-IF transmitter reports a bandwidth of up to 15 MHz bandwidth at 1 GHz LO frequency.

The summary of the reviewed digital transmitters is in Table 3.1. The main characteristics of the works are tabulated. The differences in their architecture with respect to their upconversion stages, the number of RF signals processed in their conversion stage, the main co-existence filtering mechanisms, order of a ∆Σ used and the resolutions of their DACs are contrasted. In addition, measurement results relevant to the discussion in this section are compared. Although some of the works have higher clock rates, and most of the RF DACs have both clock and LO frequencies, they are compared by the final f c , carrier frequency, at which the data can be transmitted.

Multi-standard Digital Transmitters

Due to the various applications and radio standards that address them, devices are expected to operate over wide spectrum while maintaining the usual requirements such as efficient power management and small form factor. To address these demands, system, and architectural level solutions have been proposed [START_REF] Mitola | Cognitive Radio Architecture Evolution[END_REF]. On transmitter circuit design, the challenges boil down to hardware reusability and ability to reconfigure the hardware for a range of channel bandwidths, modulation and coding indexes, power Chapter 3. Multi-standard Digital Transmitters Table 3.1: Summary of the reviewed digital transmitters Multi-standard operation could be achieved by reconfigurable circuit block, or an innovative architecture. Reconfigurability in circuit blocks is usually achieved by leveraging most transmitter operations to DSP or based on digitally-assisted analog circuits. A purely analog reconfigurable circuit would require big area, is less tunable, and power hungry. In this section, a review of recent multi-standard digital transmitters is presented with a focus to novel solutions in the digital-analog interface.

Parameters [YJ03] [LSH04] [Elo+07] [Poz+08] [Moh+12] [JS07] [Tal+08] [Fra+09]
.3 V 1.8 V 1.2 V 1.2 V 2.5-3.3 V 2.5 V 2.5 V 1 V 1.3 V

Multi-modal Transmitters in Literature

Wireless standards that are transmitted at nearby carrier frequencies with similar channel bandwidths, and whose transmitter parametric requirements-EVM, ACPR for instance-are quantitatively close to each other offer the best scenario for multi-modal circuit design. A set of common requirements can be drawn for each parameter, and a common circuit can be designed on those requirements. The multi-standard transmitter in some cases can have only one signal chain and without a need for complex external reconfiguration. This scenario was exploited in [START_REF] Eloranta | A Multimode Transmitter in 0.13Î 1 4[END_REF] with digital-to-RF converter based direct conversion transmitter for GSM/EDGE, WCDMA and WLAN. The WLAN transmitter has the stringent requirement in channel bandwidths (16.6 MHz), MCS (64-QAM), and EVM (5.6% with 64-QAM); the WCDMA transmitter has additional requirement which is a power control range of 74 dB;

and the GSM/EDGE transmitter also requires a receive band noise of -162 dBc/Hz. The multi-standard transmitter in [START_REF] Eloranta | A Multimode Transmitter in 0.13Î 1 4[END_REF] has 10-bit digital-to-RF converters with an OSR of eight. This fulfills the receive band noise requirement. Filtering of images and quantization noise is done by a digital front-end IIR filter which also incorporates FIR filter with notches to target specific input signal replicas. Power control is provided by digital control of biasing current sources of the DRFC.

The innovative DRFC circuit block simplified the multi-standard design by eliminating the circuit blocks (mixer and analog reconstruction filter) which contribute highly to non-ideal performance in a traditional direct conversion transmitter. However, if one of the standards, say IEEE 802.11a WLAN,

were replaced by a one with wider channel bandwidth, say 80 MHz of the IEEE 802.11ac, the approach would be difficult to follow. For one thing, high oversampling requirement, due to wider channel bandwidth, would push the clock rate to multi-GHz ranges, and design of a multi-bit, multi-GHz RF DAC while still fulfilling narrow channel bandwidth mask requirements is challenging. Additional DSP signal chains, or circuit blocks only specific to one standard, could be used with a common digital-analog interface. Otherwise, the DSP chain would be overly complex. This is true in [START_REF] Pozsgay | A fully digital 65nm CMOS transmitter for the 2[END_REF] where an RF DAC based direct conversion transmitter is demonstrated for all bands of WiFi-WiMAX standards. Additional oversampling signal chains are included to arrive at the Chapter 3. Multi-standard Digital Transmitters needed sample rates at the input of the digital-analog interface. Although many interpolation stages are used in the digital front-end to oversample the data by a factor larger than 60, the reliability of the digital circuits even at advanced CMOS nodes should enable them to deliver the expected performance.

In some works, only the blocks that are bottlenecks for realizing a multi-standard transmitter are

presented. An implicit performance expectation is put on the remaining blocks of the transmitter. In GHz [START_REF] Engel | A 14b 3/6GHz current-steering RF DAC in 0.18Î 1 4 m CMOS with 66dB ACLR at 2.9GHz[END_REF] and this enables them to convert GHz range input data frequencies. They do not support any filtering, mask requirements are fulfilled with sheer increase in resolution of the converters as shown in Table 3.2. In other words, the baseband quadrature modulation is carried out with no reduction in resolution. An analog filter at the output is necessary at least for image rejection. 3 Gs/s 14-bit 600 mW 1.5 GHz 0.18µm CMOS While the approach is novel for multi-standard transmitter operation, they come at large power consumption cost even disregarding the power consumption of the remaining transmitter blocks. The reported bandwidth may be enough for most cellular applications. However, the output frequency of the quadrature modulator can not be guaranteed to be within that bandwidth.

Rather than increase the sampling speed of the DAC, it is possible to use n-path parallel RF DACs to target images which are very close to the fundamental signal so as to increase the supported input bandwidth [START_REF] Deveugele | Parallel-path digital-to-analog converters for Nyquist signal generation[END_REF][START_REF] Balasubramanian | Ultimate Transmission[END_REF]. This is demontrated in [START_REF] Jamin | A time-interleaved multi-mode delta-sigma RF-DAC for direct digital-to-RF synthesis[END_REF] where a reconfigurable 2-path parallel delta-sigma RF DACs sample the quadrature digital output of a digital-IF transmitter. The parallel ∆Σ RF DACs are clocked with 180 0 phase-shifted clocks to cancel input images. The ∆Σ modulators can be configurable for band pass or high pass noise shaping, at f s 4 , f s 2 , and 3 f s 4 , for processing wideband IF inputs. Although not shown, the digital quadrature modulator has also to support this reconfigurability. The concept is implemented in 130nm SiGe BiCMOS; it can process up to 50 MHz bandwidth at maximum sampling clock rate of 2 GHz for all ∆Σ modes. Even though the achieved bandwidth is not wide enough for modern wireless applications, such as IEEE 802.11ac, the method of using n-path parallel ∆Σ RF DACs after the quadrature modulator is novel and interesting. The bandwidth can be improved by increasing the clock rate or the resolution. The image rejection is highly dependent on the timing delay difference between the two clocks. Thus, increasing the clock rate or the resolution does not scale linearly with image rejection as the former increases timing errors and the latter contributes to timing errors by increasing the number of elements to be clocked and the area. For high image rejection, incorporating an embedded image filtering into the structure and finding a trade-off between the filter order and the clock rate to improve timing alignment could enhance performance.

FIR DAC Based Multi-modal Transmitter Archtiectures

As a continuation to the discussion on multi-standard transmitters, in this sub-section, digital transmitter architectures based on FIR DACs are proposed. They are original contributions of this work. They are not previously published except one, in [START_REF] Tsigabu | A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards[END_REF]. The system level results of this published work are presented in Chapter 5. The others are qualitatively discussed in relation with the IEEE 802.11ac standard.

Three of the architectures have similarity to those architectures based on mixing-DACs except they incorporate semi-digital filtering with no analog mixing. The second architecture is similar to the RF DAC implementation in [START_REF] Jerng | A Wideband Digital-RF ÎΣ Modulator for High Data Rate Transmitters[END_REF] except it does not incorporate analog mixing.

LPF in Direct Conversion Transmitter

A LPF FIR DAC based direct conversion transmitter is shown in Figure 3.14. To maximize hardware sharing, the different input rates are resampled to a common sample rate. Then a delta-sigma modulator is used to decrease the resolution and its coefficients can be reconfigured to realize different OSR settings. The FIR DAC coefficients are also reconfigurable to meet the transmit mask requirements of each channel bandwidth. Finally, quadrature modulation is performed in analog domain at the desired carrier frequency.

The advantages of using FIR DAC are three fold. Firstly, even with long filters and high resolution coefficients, the embedded FIR filter can be designed to fulfill the desired mask, EVM, and out-ofband noise floor requirements. This is the difference between RF DAC approaches where a missing reconstruction filter results in using LC bandpass filter to attentuate images and generally high OSR.

Secondly, the FIR DAC coefficients can be reconfigured to realize a different impulse response with the same number of elements used representing the coefficient set of the first filter. Although using long filter with high resolution coefficients for a standard that can be implemented with a simpler filter and coefficient resolution is not efficient, reconfigurability in similar channel bandwidths can be carried out efficiently. Thirdly, the 1-bit FIR DAC, for L = 1, is inherently linear, and coefficient mismatch errors only result in changes in the stopband rejection of the filter.

However, the limitation of this architecture also emanates from the FIR DAC. To achieve high stopband rejection, -40 dBr for 802.11ac transmit masks at 3 f CH-BW 2 , the filter tends to be long and the coefficients have high resolution. This could result in big area which, in turn, can increase the clock timing errors, and decrease the maximum achievable SFDR.

The quadrature mixers in Figure 3.14 can be implemented in analog. The passive voltage upconversion mixers discussed in [START_REF] He | A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end[END_REF] can also be used for SAW-less implementation so that the output can directly drive a power amplifier.

BPF in digital-IF Direct Conversion Transmitter

A BPF FIR DAC in a direct conversion architecture is shown in Figure 3.15. To generate a bandpass input signal to the FIR DAC, the output of the delta-sigma modulator is fed to a digital complex mixer with complex output. The output is at n f s 2 for band pass or high pass operation of the FIR DAC. The final mixing is carried using 90 0 phase shifted clocks of the two FIR DACs.

Image suppression in this architecture is achieved by the 90 0 shifted clocks, i.e., at the summed output. The effectiveness of this is left for investigation.

The summed signal at the output of the FIR DACs can reach up to f s 2 . A HPF mode achieves higher carrier frequency than the BPF implementation.

BPF/HPF in Digital-IF Transmitter

A BPF/HPF FIR DAC based digital-IF transmitter architecture is shown in Figure 3.16. In this case, the quadrature modulation is carried out digitally. The delta-sigma modulator and the FIR DAC are operating 2 }, and the ∆Σ and FIR DAC can be reconfigured as easily [START_REF] Vankka | A digital quadrature modulator with on-chip d/a converter[END_REF].

The FIR DAC in this architecture has to work at higher clock rate and input frequency. It is possible to 34 Chapter 3. Multi-standard Digital Transmitters use another mixer following the FIR DAC if the desired carrier frequency is too high to be implemented with reasonable performance in the FIR DAC. Additionally, to decrease the effect of the SINC roll-off on the FIR DAC response, the NRZ holding has to be replaced with a RZ-type pulse holding [START_REF] Yuan-Shih Chen | Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis[END_REF].

Summary and Conclusions

The chapter introduces basic transmitter operation. It discusses modulation in SC and OFDM transmitters, and briefly summarizes the pros and cons of traditional Cartesian transmitter architectures and polar transmitters. It also highlights some important performance metrics for transmitters.

All-digital transmitter architectures from recent literature are thoroughly reviewed. A special attention is given to digital-to-RF converters. A summary table of the discussed works is also included.

In accordance with the target application of this work, multi-standard transmitters are reviewed. More importantly, novel multi-standard transmitters architectures based on LP, BP, and HP FIR DACs are also proposed. The FIR DAC concept is discussed in Chapter 4.

Chapter 4

Configurable Finite Impulse Response Digital-to-Analog Converter

Operation of a DAC

A digital-to-analog converter is used for converting digital signals into analog signals. In wireless communication transmitters, it is usually followed by an analog reconstruction filter to smooth the staircase signal into pure analog form. Digital processing blocks can be used to change the resolution of the signal before it is fed to the converter.

In this section we are going to introduce time and frequency domain operation of an ideal DAC in a classical wireless transmitter. It will be followed by a discussion of a semi-digital FIR DAC. To help explain the FIR DAC, a brief highlight of traditional multi-bit DAC specifications and architectures are included.

Traditional Multi-bit DAC

The operation of a DAC in time domain is shown in Figure 4.1. An L-bit digital word is the input to an L-bit resolution DAC. The DAC reads the input data at instance nT s and holds the new output until (n + 1)T s for a clock period, T s , in what is called an NRZ scheme. The DAC could also read the sample and hold the output for half the period of the clock and return the output to zero for the remaining half in an RZ scheme. In time domain, the response of the DAC can be approximated by a rectangular pulse with a width of T s .

The rectangular pulse in time domain is a SINC function in frequency domain. The duty cycle of the RZ DAC in time sets the zero-crossings in frequency as shown in Figure 4.2. While the RZ has a flatter magnitude response in the first Nyquist zone, the NRZ is more selective. For input signals whose bandwidth stretches to near f s 2 , using RZ response ensures a smaller ripple across the desired band. Given a sampled input as shown in Figure 4.1, the NRZ response can attenuate the immediate image signal by more than 10 dB. However, the attenuation provided by the DAC response is for most applications not

Multi-bit DAC Specification

The performance of a DAC is commonly specified as static performance, dynamic performance and frequency domain performance. In this sub-section, the main DAC performances metrics are defined, and some formulas are derived in some cases to clarify the concepts. A graphically summary is shown in Figure 4.3.

Resolution

Normally, an N-bit input signal is converted to analog by using a N-bit resolution DAC. However, that is not always the case as ∆Σ modulators can be used to ease design complexity and lower input signal resolution so that an originally N-bit signal can be converted to analog by using a lower resolution DAC at higher speed.

Output Signal Bandwidth

In wireless communication, a Nyquist rate DAC is designed to convert input signal bandwidths up to half its update rate. The problem with such a target is that the reconstruction filter that follows the DAC becomes complex as it has to filter out a nearby image when the desired signal is close to f s 2 .

Nonlinearity

Nonlinearity of a DAC are measured by the INL and DNL. DNL is defined as the maximum difference between the LSB and the measured difference of two consecutive output values. On the other hand, INL is a measure of the total deviation of the time-domain response of the DAC from the ideal response.

Settling Time

At each update time, the output may change to a new value, and the time it takes to reach within some range of the value is the settling time. The range of values are usually defined as the percentage of the final theoretical value and they are called percentage tolerance.

Clock Feedthrough

This is a manifestation of the clock in the output spectrum. This happens due to parasitic capacitances which link the input side, usually digital, to the analog output. It is easily noticeable in the output spectrum because it appears at the clock frequency and its harmonics.

Spurious Free Dynamic Range

SFDR measures the relative power difference between the desired signal and the highest harmonic or spur at the DAC output. This measurement is carried out using a single tone input signal as shown in HD n measures the ratio of the power of the n th harmonic to the power of the fundamental signal. The total harmonics distortion is the ratio of the power of the fundamental to the total power of all the harmonics.

The Third-Order Intermodulation Product IMD3 is a measure of the ratio of power of the third order intermodulation product to the power of the fundamental input signals. If the two input single tones are f 1 and f 2 , the third-order intermodulation product is one of 2 f 1 ± f 2 , or 2 f 2 ± f 1 which falls in the signal band.

Dynamic Range

DR measures the difference between the maximum output power, also called the full-scale output, and the minimum output power. The minimum output power can be approximated by the total noise at the output. The noise may include the quantization error, thermal noise, and flicker noise depending on the application and their influence on the circuit.

R-2R Ladder DAC

The most straightforward method of implementation is based on switching binary weighted values depending on the N-bit digital input to the output. The values can be realized using voltage/current division in voltage/current mode implementation respectively or charge-redistribution. If we take the R-2R ladder network as an example, Figure 4.4, a reference voltage is divided according binary-weighted resistance ladder, and the digital inputs bits are used to switch the corresponding weighted resistor to a common node or ground. Usually an op-amp is used for summation [START_REF] Baker | CMOS: circuit design, layout, and simulation[END_REF].

V ref b 0 b 1 b N-1 b N b 2 R R R R 2R 2R 2R 2R 2R 2R R f V out Figure 4.4: A N -bit R-2R resistance ladder DAC

Resistor String DAC

This is a more bulkier type of implementation because it has all the possible analog values of an N-bit digital input. The digital inputs are used to decode which value to send to the output. In resistor string implementation, a reference voltage is divided using identical resistors such that all the analog values can be tapped to the output depending on the digital input as shown in Figure 4.5. The decoding could be done as shown in the figure, with a switch array or even with a row/column matrix to lower the required number of components or to improve dynamic performance.

Current Steering DAC

This is the type of implementation more suitable for high speed, high resolution DAC implementation. In the case of thermometric implementation, Figure 4.6, the output is obtained from summation of identical valued current sources. The digital inputs control an identical number of current source proportional to their values. Since there is an LSB (I unit ) difference between consecutive output values, the transition is smooth and the glitch energy associated with it is low. Mismatch could also be reduced due to the identical nature of the current cells.

The thermometric current steering approach requires a large number of unit current cells for high resolution DACs. The routing requirement limits the achievable speed. To remedy this, a segmented

V ref b 0 b 1 b N-1 b N b 2 R R R R V out N-to-2 N DECODER {b 0 ,

Finite Impulse Response DAC

A general L-bit, N-tap FIR DAC architecture is shown in Figure 4.8. C 1 to C N are the filter coefficients which are implemented by using an L-bit DAC. N is the length of the filter.

A FIR DAC can be viewed as a digital filter whose coefficients are implemented in analog. It can be used as a DAC because its coefficients can be designed to form any desired frequency response and shape the analog output. It can also be seen as a general structure from which the traditional multi-bit The main strengths of the general FIR DAC structure is the flexibility to configure the coefficients to obtain any desired frequency response. The output is a linear sum of each tap output. The other strength is the inherently linearity of the output for the case that the coefficients in the taps are linear.

Iout M-to-2 M-1 DECODER {b M , b N } M Iunit 2 M-1 Iunit b 0 b M-1 2 M-1 Iunit 2 M-1 Iunit 2 M-1 Iunit 2 M-1 Iunit
Each DAC has as an input which is the delayed version of the input to the FIR DAC. Therefore, the output is a sum of the delayed and scaled versions of the input. If L equals one, the DACs realizing the coefficients can be replaced by a single switch device that controls a passive or active realization of a coefficient value. This arrangement leads to an N-tap, 1-bit FIR DAC. For the case where both L and N are greater than one, it is an L-bit, N-tap FIR DAC. The classical DAC is considered as an L-bit, 1-tap FIR DAC.

There are many important differences between an L-bit, N-tap; 1-bit, N-tap; and L-bit, 1-tap FIR DACs. They differ in the ease of dealing with mismatches, the maximum speed each can achieve under the same constraints, the area required to implement them and other parameters [START_REF] Vital | Integrated mixed-mode digital-analog filter converters[END_REF]. In the following sub-section, the general issues common to all flavors of the FIR DAC structure are discussed. Subsequently, a quantitative comparison of the different flavors is presented. At the end, the comparisons are summarized in a table.

FIR DAC Implementation Issues

The delay cells are usually implemented using clocked dynamic or static or semistatic logic. They can also be implemented with analog circuits. Some power consumption reduction could be obtained using non-clocked delay cells, but the resulting delay inaccuracy could be detrimental to the performance of the filter [START_REF] Mehmet | Effects of Random Delay Errors in Continuous-Time Semi-Digital Transversal Filters[END_REF].

To faithfully replicate the transfer function, the coefficients have to be realized with high degree of accuracy. Thermometric implementation of the coefficients gives higher accuracy. On the contrary, weighted implementation of the coefficients is prone to mismatch errors, but could be arranged to save area.

For analog implementation, coefficients have to be quantized as their quantitative values have to be translated to hardware. In other words, accurate coefficients are difficult to realize. In addition to quantization, coefficients assume random values. It increases mismatch errors due to loss of symmetry.

Furthermore, the fact that the coefficients are random means we have to look into asymmetrical layout methods to decrease systematic process mismatches during layout. Therefore, coefficient quantization helps in representing one coefficient as a ratio of another smaller one. If integer relationship is maintained for all ratios between any two coefficients, all of them can be represented as a sum of a unit coefficient.

The other source of error is the spread of the coefficients. When there is large spread, the number of required unit coefficients increases exponentially. Therefore, filter design should target low resolution coefficient set. The length of the filter is another factor that increases the number of unit coefficients. Long filter are required to achieves high stopband rejection, but results in large area and big unit coefficient count.

All these factors have to be considered during selection of a FIR DAC topology. Topologies that use passive components to implement FIR DACs can result in big areas due to the relative size of the unit passive component realizing the unit coefficient. For large bandwidth applications, the unit coefficients should be able to switch at high speeds. In this regard, current-steering architectures are preferable.

Topologies that exploit the symmetry of FIR DAC impulse responses have generally lower area due to hardware sharing. Because an implementation of a coefficient would be reused to realize two samevalued coefficients in the left and right side of the impulse response. However, the circuit implementing the coefficient now has to entertain additional conditions. For example, a 1-bit input could be translated to a 0 or a 1 for a coefficient, but a 0, 2, and -2 i.e. 1.5-bit for two coefficients. These would be require a different implementation of the coefficient.

L-bit, N-tap FIR DAC Design Challenges

Generally, filter design is a compromise between the number of coefficients of the filter, the transition band and the passband and stopband ripples. With strict requirements on the transition band and stopband rejection for narrowband applications in crowded spectrum, a long filter length is needed. On the other hand, in broadband applications where the required stopband rejection ais low, a short filter length can achieve the required transition band.

The digital input of the FIR DAC can be oversampled to reduce quantization noise and complexity of analog low pass reconstruction filter. The oversampling process eases filtering, so short length filter with 4.3. Finite Impulse Response DAC 43 low coefficient spread could be used. In this scenario, the L-bit, N-tap FIR DAC shares the challenges of a traditional L-bit DAC and would closely follow the linearity of the L-bit DAC.

A delta-sigma modulator is used for converting the resolution of the digital input, then the FIR DAC has low number of input bits and high number of coefficients with considerable coefficient spread to reduce quantization noise. In this scenario, the L-bit, N-tap FIR DAC has to maintain matching N number of L-bit DACs. In other words, a single L-bit DAC would outperform the multi-tap FIR DAC.

The advantage of the L-bit, N-tap FIR DAC over the the L-bit DAC would be in image rejection.

Σ Z -1 L x[n] y[n] C 1 C 2 C 3 C N Z -1 Z -1

N-tap, 1-bit FIR DAC Design Challenges

A 1-bit, N-tap FIR DAC is inherently linear. This is because the 1-bit DACs realizing the coefficients are inherently linear and the output is a sum of the delayed and scaled versions of these linear outputs.

The 1-bit, N-tap FIR DAC is best suited, then, for obtaining high filtering performance. However, it has to work at higher speeds compared to an L-bit, N-tap FIR DAC. This is because the serial data at the 1-bit FIR DAC input passes through a conversion stage containing an oversampling and delta-sigma modulator blocks with higher OSR.

A comparison of the three common structures of a FIR DAC is provided in Table 4.1. Some of the assumption used for comparison are shown as a footnote. The first two structures are assumed to have the same resolution in their coefficients and, also, equal number of coefficients. The third structure is the traditional multi-bit DAC. It is presented in the table as a special FIR DAC with a single-tap, or no delay cell, between its coefficients. Besides, its coefficients are implemented with only weights of two.

As expected, an L-bit, N-tap FIR DAC have the worst mismatch linearity and speed. A traditional multi-bit DAC can achieve the highest speed due to the absence of a delay line, lowest number of unit coefficients and smaller coefficient spread. A 1-bit, N-tap FIR DAC can achieve the same coefficient

‡ L > 1 § N > 1 ¶ Traditional multi-bit DAC Thermometric implementation assumed

Frequency Translation of FIR DACs

Once a low pass filter is designed, a bandpass and a high pass filter can be generated by only changing the delay line while keeping the coefficients values the same. In circuit implementation, this behavior of the FIR filter makes it amenable to reconfiguration. By only adding redundant delay cells which can be switched to be in the signal path of the active delay line or not, the filter is frequency translated. Since delay cells consume relatively low power and occupy relatively small area, the share of this frequency translation feature on the total FIR DAC power and area budget is negligible.

LPF to HPF Transformation

A linear-phase symmetrical or asymmetrical low pass FIR filter impulse response can be changed to a high pass filter response centered at f s 2 by multiplying each coefficient by (-1) n where n is the tap to which the coefficient belongs. Mathematically, this can be expressed as [START_REF] Richard | Understanding digital signal processing[END_REF]:

h hp [k] = h lp [k] S shi f t [k] (4.1) S shi f t [k] = {. . . , 1, -1, . . .} (4.2)
In circuit design, this is simply implemented by changing the flip-flops of the delay line. One method in a 1-bit FIR DAC is to drive coefficients by the negative output, Q of flip-flops, every other tap. For reconfigurability, the coefficients can be switched between the positive output, Q, and negative output, Q, for low pass and high pass filtering respectively. An impulse response in Figure 4.9, which will be revisited in subsequent chapters, is used for explaining the discussed transformation. The LPF impulse response is multiplied by (-1) n to convert it to a HPF response with the same number of coefficients. The resulting frequency response can be seen in Figure 4.10 where the HPF has the same magnitude as the LPF.

LPF to BPF Transformation

A linear-phase symmetrical or asymmetrical low pass FIR filter impulse response can be frequency translated to a band pass filter centered at f s 4 by multiplying every other coefficient by 1 and -1 and inserting additional zeros in between each multiplication. Mathematically, this can be expressed as [START_REF] Richard | Understanding digital signal processing[END_REF]:

Chapter 4. Configurable Finite Impulse Response Digital-to-Analog Converter h bp [k] = h lp [k] S shi f t [k] (4.3) S shi f t [k] = {. . . , 1, 0, -1, 0, . . .} (4.4)
In circuit implementation, this is easily realized by adding an untapped delay line between the taps that are switched to the positive output and negative output at every other tap. This transformation, however, comes at a cost due to the inserted zeros. For the same filter length, the magnitude response of the resulting band pass filtering FIR DAC decreases by 6 dB. Nonetheless, the good news is that the effective length of the filter is also decreasing. Thus, for a LPF FIR whose length is twice than desired can be designed and transformed to a BPF filter, and still the resulting number of non-zero coefficients will be the same. The LPF impulse response from the previous example is again transformed to a BPF response as shown in Figure 4.11. The magnitude response of the resulting band pass filter is lower by 6dB, as can be witnessed in Figure 4.12, while the number of coefficients have decreased

Configurable 1-bit FIR DAC Delay Line

The implementation of the above discussed transformation in a 1-bit FIR DAC is straightforward. By designing a reconfigurable delay line with a minimum cost of power consumption and area, a set of FIR DAC coefficients designed for LPF mode can be made to work in BPF and HPF modes also. Figure 4.13 shows the frequency translation of a 1-bit FIR DAC by only exploiting the delay line. This means, the components implementing the coefficients can remain unchanged. The advantages of this approach Figure 4.12: Magnitude response of LPF FIR and its frequency translated BPF version is that the frequency behavior of the FIR DAC can be changed without modifying the placement and routing of the coefficient circuits array.

FF D Q Q FF D Q Q FF D Q Q FF D Q Q FF D Q Q C 1 C 2 C N + S 1 S 2 1 S 1 S 1 S 3 S 3 S 2 CLK DATA Analog Output Figure 4
.13: Transformation of a 1-bit FIR DAC from LPF to BPF and HPF using a configurable delay line Assume the switches in their current state in Figure 4.13 are in state 1, and the other state is 0, then the following table could be used to obtain the transformation discussed in the previous topics.

The configurable delay line can be optimized further by fixing the position of switch S 1 to the output of the positive output of a delay cell as shown in Figure 4.14. For this delay line, the additional hardware needed is 2(N -1) switches and N -1 delay cells for a total of 2N -1 delay cells. The power consumption and area contribution of these additional cells and switches, which are required for the configurability, is a small fraction of the total power consumption and area of the total FIR DAC.

FF D Q Q FF D Q Q FF D Q Q FF D Q Q FF D Q Q C 1 C 2 C N + S 2 1 S 3 CLK DATA Analog Output S 3 S 2

FIR DAC Architectures in Literature

In this section, the discussion on FIR DAC topologies will continue by reviewing briefly previously published works. Initially, a discussion on reported FIR DAC architectures, their application, and specifications will be presented. The discussion focuses on FIR DAC implemented on the transmitter side.

However, it is important to mention that they are also applied in the receiver side as part of the analogto-digital converter. In [START_REF] Ashry | A generalized approach to design CT Delta-Sigma Modulators based on FIR DAC[END_REF], a discussion of the design of continuous time sigma-delta modulators based on FIR DACs is presented.

Multi-bit FIR DACs

Traditional transmitter architectures have a digital filter followed by a DAC and then a reconstruction analog low pass filter. Early works targeted reducing the complexity of the digital filters using what they called digital-analog filter converters [START_REF] Vital | Integrated mixed-mode digital-analog filter converters[END_REF]. This removed power consuming, silicon area demanding, albeit flexible, multiplication blocks while combining two functionalities into one. A silicon demonstrator of this approach was fabricated in 3µm CMOS technology where the coefficients of a 4-tap FIR filter are implemented using 8-bit algorithmic DACs. The operational amplifier based swtichedcapacitor summing output generally is a speed bottleneck and could have limited the reported speed of 20 kHz.

A more recent implementation of a multi-bit dac is the 4-bit, 60-tap semidigtal filter implementation in [START_REF] Lin | A CMOS Oversampled DAC With Multi-Bit Semi-Digital Filtering and Boosted Subcarrier SNR for ADSL Central Office Modems[END_REF]. The idea in the work of Lin et al. is to filter shaped quantization noise out of a delta-sigma modulator using a steep transition band semidigital filter. The drooping at the edge of the passband of the semidigital filter is compensated by a pre-emphasis digital filter. Since steep transition, and high stopband rejection require long filter length, the semidigital filter was designed using interpolated coefficients. The problem with this approach is that it requires a complex analog low pass filter to remove the additional passband in the middle of the semidigital filter response. A third-order low pass filter is used in their work due to the high oversampling ratio, 88, in their frequency planning. For lower OSR values, a higher order analog LP filter would have been used. In other words, effective bandwidth of output signal is exchanged for complexity of analog filter.

1-bit Semi-digital Reconstruction Filter

The potential of an Ntap, 1-bit FIR DAC to lower the complexity of the analog reconstruction filter A method to reduce the number of filter coefficients based on interpolation was reported in [START_REF] Kim | An Area-Efficient Sigma-Delta DAC With a Current-mode Semidigital IFIR Reconstrution Filter[END_REF].

A sharper transition band filter is obtained from a filter with twice large passband by upsampling its coefficient set. In other words, delays are inserted, i.e. zero values, between coefficients of an impulse response of a filter normally designed for a twice large passband than is desired. This method results in an unwanted additional passband at f s 2 . To circumvent this problem, an interpolated low pass ∆Σ modulator that generates an additional low noise region at f s 2 is used. The high linearity performance of Ntap, 1-bit semi-digital FIR is employed in the signal path of a dual-truncation ∆Σ DAC. In this switched-capacitor 0.18 µm CMOS implementation, the symmetry of a 67-tap FIR impulse response is exploited using a folded delay chain to reduce the number of capacitors by half [START_REF] Francese | A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering[END_REF]. While the method of employing complementary clocks to reuse a coefficient decreases the area required, it normally limits high speed operation due to delay in the decoding logic.

In a similar application to the work in [START_REF] Francese | A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering[END_REF], a 1-bit semi-digital FIR is employed together with a digital filter to suppress shaped quantization noise in [START_REF] Barkin | A CMOS Oversampling Bandpass Cascaded D/A Converter With Digital FIR and Current-Mode Semi-Digital Filtering[END_REF].

In [START_REF] Doorn | An audio FIR-DAC in a BCD process for high power class-D amplifiers[END_REF], a semi-digital 322-tap FIR DAC with only positive coefficients is designed for quantization noise filtering at audio frequencies. Silicon area limits the use of high resolution coefficients in long filter implementation. This problem is overcame in [START_REF] Doorn | An audio FIR-DAC in a BCD process for high power class-D amplifiers[END_REF] by limiting the coefficient spread to

I out

Analog Output Normally, dynamic circuit implementations have problems of charge injection, and charge sharing. For a robust FIR DAC design at high speeds, a static or semi-static delay line is more robust against noise at the expense of increase in the total power and area by a small percentage.

I-to-V Conversion

Programmable Filtering DAC

The compatability of the FIR DACs approach for implementing programmable filtering DACs was demonstrated at a bigger area and power cost in [START_REF] Henriques | A high-speed programmable CMOS interface system combining D/A conversion and FIR filtering[END_REF]. The delay line of the FIR DAC was improved by adding redundant delays which were useful for realizing different filter responses. Each tap of the FIR DAC were implemented by segmented 8-bit current steering DACs. The programmability of coefficients was possible by changing the overdrive voltage of current sources in the segmented DAC. Current steering implementation enabled them to switch at higher rates than previously reported. Programmability of FIR DACs was revisited using a novel current steering architecture in [START_REF] Aga | A CMOS digitally programmable current steering semidigital FIR reconstruction filter[END_REF]. A constant bias current was divided into two positive and negative output branches using a set of differential switches as shown in Figure 4.16. The number of differential switches at each tap are proportional to the coefficient values and are enabled or disabled by a control switch that ensures programmability. A wide swing cascode current source mirrors the currents in the output branches. The frequency domain performance of the architecture depends on the high frequency linearity of the current mirrors at the output. This concept was demonstrated for a 64-tap FIR DAC with limited coefficient spread for audio

Q 1 Q 1 Q N Q N VDD

Receive-band Noise Filter

The Ntap, Lbit FIR structure is also embedded in DIDIMO transmitters for receive-band noise filtering. In

FIR Power DAC

Delta-sigma noise shaped digital outputs can be directly frequency translated by using image-reject digital mixers [START_REF] Frappe | An All-Digital RF Signal Generator Using High-Speed ÎΣ Modulators[END_REF]. The resulting single-bit stream can be directly fed to parallel power DACs for amplification and digital-to-analog conversion. The power DACs, tapered buffers, can also form the coefficients of an FIR filter for bandpass filtering of their combined output.

In [START_REF] Flament | A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner[END_REF], a 5-tap reconfigurable bandpass FIR filter with unity positive and negative coefficients is implemented in 65nm CMOS process. The outputs of 56 TPSC dynamic flip-flops of the delay line are connected to three multiplexer. The multiplexers select five taps to drive five power DACs as shown in .17: General structure of the reconfigurable bandpass FIR power DAC architecture in [START_REF] Flament | A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner[END_REF] requirements. However, the architecture is not fit for applications where the out-of-band noise profile of the transmitter is expected to respect co-existence issues in a crowded spectrum.

High Speed 1-bit, N-tap FIR DAC Design

Unlike passive components, current mode DAC architectures are amenable for high speed operation.

Their mismatch is characterized, they occupy lower area and are scalable. In this analysis, current steering FIR DAC architectures are assumed.

The analysis presented in this section are important contributions of this PhD work. As explained in the conclusions chapter at the end of this dissertation, a scarcity of literature providing design formulas for estimating non-idealities of high speed current-steering thermometric FIR DAC implementations was the reason that led to these derivations.

Current Steering Architecture

Current mode implementation of a FIR DAC is shown in Figure 4.18. The current sources are weighted to implement the coefficients. The differential output enables implementing signed coefficients. For example, the cross-connected outputs of the first and last coefficients realize a negative coefficient values relative to the other coefficients in Figure 4.18.

A UCC is a circuit realization of a unit coefficient. It contains analog current source and a digital latch. It can be replicated in all coefficients as many times as the quantized coefficient values to create a resultant current in the desired sign and magnitude of the coefficient as in Figure 4.18. All that is required is to maintain an integer ratio between all the coefficients. This can be accomplished by quantizing the coefficients in a fixed number of bits where the largest coefficient represents 2 quantization_bits . Then the GCD of the integer values of the coefficients becomes the value of the unit coefficient that is realized by one UCC. If there is no GCD greater than one, the unit coefficient becomes one, still realized by one

Performance Metrics and Modeling

In a current steering DAC architecture, the main sources of non-idealities are current source mismatch, finite output impedance of current sources, clock feedthrough, global and local timing errors, output and cell dependent errors. Modeling these non-idealities and factoring them in the design of the DAC is important for the measurement to match the theory. In this section, we are going to analyze how these non-idealities influence the performance metrics discussed earlier in this chapter.

Effect of Coefficient Mismatch

The main advantage of a single-bit FIR DAC is the inherent linearity of the 1-bit DACs it uses at each tap. Coefficient mismatch has negligible effect on the passband of the transfer function, but it puts a limit on the stopband attenuation to a degree that even an increase in the length of the filter would not affect

it. An FIR filter output is given by the following equation:

y[n] = N k=1 c k x[n -k -1] (4.5)
Where c k are the coefficients and N is the length of the filter. The filter transfer function for a general An average standard deviation of all the coefficients which are implemented with unit coefficients can be found from the pooled variance as:

input x[n] = e -jωn , where -∞ < n < ∞, is [PS08]: H(ω) = N-1 k=0 c k+1 e jωk
σ ave = σ 2 u |c 1 |+σ 2 u |c 1 |+...+σ 2 u |c N | N (4.9)
The error on the magnitude response can then be modified to A new formula for estimation of magnitude variation due to coefficient mismatch and more suitable to a current-steering FIR DAC architecture can then be found using:

|H e (ω)| = √ π N k=1 |c k | 2 σ u (4.11)
To put this in perspective, an impulse response of an 802.11ad FIR DAC is used in Figure 4.19.

The mismatch error magnitude for a 14% standard deviation on each unit coefficient can be estimated using Equation (4.11) to be 0.0143. In other words, the passband can vary from 0.9857 to 1.0143(i.e.

-0.1251 to 0.1233 in dB). The passband ripple, A p , is then 0.2484 dB. The stopband, now at < -33 dB or < 0.02239, is raised by this error to 0.03669 or -28.71 dB. The stopband ripple, A st , is then 4.29 dB.

Then, it can be concluded that the mismatch error affects the stopband more than the passband. The stopband can be affected by the mismatch error to a degree where even longer filter would not deliver better stopband attenuation.

As will be seen in 4.5.2, this estimate gives an optimistic value. A more accurate ripple due to coefficient mismatch is obtained using large number simulation such as Monte Carlo.

Yield Model

This parameter can be further utilized in defining a yield of a FIR DAC. A FIR DAC functionality is dependent on faithfully rendering the theoretically designed transfer function, the yield is defined as the number of FIR DACs that have an acceptable transfer function. Coefficient inaccuracy results in changes in the stopband rejection, then the transfer functions that crosses a certain limit in the stopband can be rejected.

A transfer function with stopband rejection of δ 2 can be guaranteed to be below a desired stopband rejection level of δ2 at a maximum standard deviation σ ave,max of with a probability of p given by [START_REF] Petraglia | Effects of coefficient inaccuracy in switchedcapacitor transversal filters[END_REF]:

p = e -1 N δ2 -δ 2 σ ave,max 2 (4.12)
This approach was used in the design of an LP SC mode 802.11ad FIR DAC as reported in [START_REF] Tsigabu | Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60GHz transmitter[END_REF].

The percentage of the FIR DAC transfer functions that fulfill the 802.11ad mask with a margin are plotted against the standard deviation of the random mismatch in the current sources implementing the coefficients. It was concluded that the stopband of the transfer function does not raise to above 5 dB of the lowest part of the transmit mask with as big as 14% random mismatch standard deviation at a confidence level of 3σ. This is shown in Figures 4.20a

Random Device Mismatches

Transistors which implement the coefficients are prone to process mismatches. These mismatches can be tackled by classifying them into two: random and systematic mismatches. The random mismatches are dependent on device size, biasing conditions and some technological constants whereas the systematic mismatches appear over the chip area and impart a relativistic error on a device as a function of its distance from the center of the chip (more discussion on this in Chapter 6).

In [START_REF] Marcel | Matching properties of MOS transistors[END_REF], a relationship between the device size and biasing and the standard deviation of the normalized random errors of a current flow through the device are observed.

δ 2 ∆I u I u = 1 Area A β + 4A VT V 2 OV (4.13)
Where Area = WL of the current source transistor, V OV is the overdrive voltage, and A β , and A VT are technological constants.

δ ∆I u = I u

1 Area A β + 4A VT V 2 OV (4.14)
Equation (4.14) can be inserted in Equation (4.9) to find the maximum σ ave from transistor level parameters. The σ ave can be used to calculate the probability until an acceptable confidence level is obtained.

Effect of Finite Output Impedance

The effect of finite output impedance on the dynamic behavior of the FIR DAC can be analyzed by considering the unary implementation in Figure 4.18.

VDD_ANA + - ΔV out R load R load Z out Z out Z out Z out Z out N n N p + - V out, p + - V out, n Figure 4.21
The current sources that implement the coefficients have a finite output impedance. The effect of this on the output voltage of a current-steering DAC is analyzed in [START_REF] Miki | An 80-Mhz 8-Bit CMOS D/A Converter[END_REF]. Similar approach can be followed for a current-mode FIR DAC modeled as shown in Figure 4.21. N p , and N n indicate the total number of current sources that correspond to the coefficients contributing to the positive and negative branches of the output line respectively. Since differential implementation is considered, the negative coefficients which are driven by a 0-bit are grouped under N p ; and the positive coefficients driven by a 0-bit are grouped under N n as the negative coefficients driven by a 1-bit.

I load,p = N p (I out -G out V out,p ) (4.15) I load,n = N n (I out -G out V out,n ) (4.16)
Where I load,p , I load,n are the output currents belonging to positive and negative coefficients respectively; G out is the output resistance of a unit current source; and I out is the ideal full scale current divided by the number of current sources. The output voltages of the positive and negative coefficients V out,p , V out,n are given as:

V out,p = R load I load,p (4.17)

V out,n = R load I load,n (4.18)
The above pair of equations can be combined with equations (4.17) and (4.18) to arrive at:

V out,p = I out N p R load 1+N p R load G out (4.19)
Similarly for the negative branch,

V out,n = I out N n R load 1+N n R load G out (4.20)
The differential output of a current-mode FIR DAC with G out current source output impedance is then:

∆V out = V out,p -V out,n = I out R load N p -N n (1+N p R load G out )(1+N n R load G out ) (4.21)
In the ideal case, where 1 G out is ∞, ∆V out is the difference between the total output currents of positive and negative coefficients times the load resistance. However, for finite output resistance, it changes depending on ratio between the load resistance and the total output resistance of the paralleled current sources, N R out . This creates data dependent distortion on the output. This has been analyzed in [START_REF] Bosch | Static and Dynamic Performance Limitations for High Speed D/A Converters[END_REF]. The SFDR determined by the second-order harmonic for a FIR DAC with N number of current sources is [START_REF] Bosch | Static and Dynamic Performance Limitations for High Speed D/A Converters[END_REF]:

S FDR 2 = NR load 4R out +2NR load (4.22)
Similar derivation were followed to obtain an expression for the third order harmonic distortion, IMD3, of a fully-differential implementation [START_REF] Luschas | Output impedance requirements for DACs[END_REF]:

I MD3 FD = 14 3 G 2 out N 2 + 16 3 (G 2 load +G load G out N) G 2 out N 2 (4.23)
Where G load is the load conductance.

4.5. High Speed 1-bit, N-tap FIR DAC Design 59 Differential circuits cancel even harmonic distortions. Thus, the SFDR is determined by the dominant third order harmonic component. For the case where the output resistance of the current sources is much greater than the load resistance times the number of current sources, R out NR load , the n th harmonic distortion components due to the finite output resistance can be simplified by a general formula [START_REF] Palmers | A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS[END_REF]:

HD n ≈ NR load 4R out n-1 (4.24)
Furthermore, the output impedance decreases with frequency. This affects the dynamic performance of the FIR DAC. To ensure high linearity in the 802.11ad mode, the current sources has to maintain the required Z out up to near GHz output frequencies.

Assuming Figure 4.22a is the current source in cosideration, the parasitic capacitances from the drains of M CAS and M CS to the ground set the poles and zeroes of Z out versus frequency curve [START_REF] Bosch | Static and Dynamic Performance Limitations for High Speed D/A Converters[END_REF].

If the layout of the transistors of the differentially-switched cascode current source shown in Figure 4.22a is such that the parasitic capacitances of the interconnects between each transistor is minimal, the output impedance can be made to keep its DC value even at frequency values. This type of placement is discussed in Chapter 6.

Effect of Noise on FIR DAC Dynamic Range

The generated noise at the output of the current sources of the FIR DAC puts a limit on its dynamic range.

For the output of the circuit to have the desired DR, the circuit has to be modeled and the noise output should also be quantified. The analysis is based on the differentially switched cascode current source of The assumption is that the noise sources are uncorrelated. The output-referred noise of each source are superposed to obtain the total noise output. Then, the ratio of the total signal power to the total noise at the output is the DR.

I 2 n,total ≈ I 2 n,CS + I 2 n,CAS + I 2 n,S W + I 2 n,load
I n1 + V x r o1 + V x S C gs2 + V x r o2 + g m2 V x - V y r o2 = 0 (4.26) V y S C g3 + 1 r o2 + 1 r o3 + g m3 -g m2 V x - V x r o2 + I out R load r o3 = 0 (4.27) I n,CS + g m3 V y + I out R load r o3 + V y r o3 = 0 (4.28)
The above three equations can be combined to solve for the gain from I n1 to output-referred component I n,CS ,

I n,CS I n1 = K 1 = AB r o2 g m3 + 1 r o3 -AB R load r o3 +1 - r o2 g m3 + 1 r o3 1+ R load (1-A) r o3
(4.29)

Where A =

g m3 + 1 r o3 1 r o2 + 1 r o3 +g m3 +S C gs3
, and B =

g m2 + 1 r o2 1 r o1 + 1 r o2 +g m2 +S C gs2
. Similar approach can be followed to find the gains from I n2 to output-referred component I n,CAS , and from I n3 to output-referred component I n,S W to arrive at: 4.5. High Speed 1-bit, N-tap FIR DAC Design 61

I n,CAS I n2 = K 2 = A(B+1) -AB r o2 R load r o3 -1 g m3 + 1 r o3 +1+ R load r o3 - AR load r o3
(4.30) . The flicker noise is represented in the same manner as the drain thermal noise from drain to the source. Thus, the drain noise of the three transistors can be formulated as follows [START_REF] Gray | Analysis and design of analog integrated circuits[END_REF].

I n,S W I n3 = K 3 = 1-1 A + g m2 + 1 r o2 Dr o2 R load r o3 -1 A R load r o3 -1 + g m2 + 1 r o2 Dr o2
I 2 n,d = I 2 n,t + I 2 n, 1 f = 4γkT g m + K I UCC f ∆ f (4.32)
The other noise components is the thermal noise of the resistor and is given by: Where γ is device dependent coefficient. A value of 2/3 is taken for long channel devices, but it increases for devices in nanometer processes [START_REF] Gray | Analysis and design of analog integrated circuits[END_REF]. k = 1.38x10 -23 is Boltzmann's constant, T = 300 • K is taken for room temperature, K is another device dependent constant and ∆ f is the bandwidth over which the noise is integrated.

I 2 n,load = 4kT 1 R load ∆ f (4.33) -g m3 V y I n,CAS V out V x -g m2 V x r o3 r o1 V y C gs2 I 2 n2 C gs3
I 2 n,CS = K 2 1 I 2 n,d | g m =g m1 (4.34) I 2 n,CAS = K 2 2 I 2 n,d | g m =g m2 (4.35) I 2 n,S W = K 2 3 I 2 n,d | g m =g m3 (4.36)
The total noise power at the output is then: Some assumption could be taken to simplify expressions of K 1 , K 2 , and K 3 . For example, r o 1 g m . Another assumption is the product of the load resistance and the drain-to-source conductance is much smaller than one: R load r o 1. At the frequency of operation g m S C gs . A and B are approximated to unity with those assumptions. D ≈ g m2 g m3 .

P noise = NI 2 n,total = N I 2 n,CS + I 2 n,CAS + I 2 n,S W + I 2 n,load (
K 2 1 ≈ r o2 g m3 2 (4.38) K 2 2 ≈ 2g m3 g ds2 + g m3 2 ≈ 4 (4.39) K 2 3 ≈ 1 (4.40)
With this new values the total noise power is approximated to:

P noise ≈ 4kT BW g m1 r o2 g m3 2 + 4g m2 + g m3 + K I UCC 5 + r o2 g m3 2 ln BW (4.41)
The average signal power is a summation of the full-scale current flowing in the load resistors. The transconductance term in K 1 can be replaced by an equation containing the current value, I UCC , and some technological constants. However, the r o2 term in K 1 would have to be calculated for each new current value. Hence, it is not straightforward to run multiple simulations with this expression of DR. As can be seen from the values of the gains, the noise contribution from the current source transistor, M CS , is much greater than the contribution from both the cascode transistor, M CAS , and the switch device, M S W . This is because the ratio (r o2 g m3 ) 2 is on the order of hundreds as per transistor-level simulation of a differentially-switched cascode current source circuit. Therefore, if some additional tolerance is taken on the output noise value of the current source transistor, it simplifies the analysis to ignore the switch and cascode devices. For that, let (r o2 g m3 ) 2 be K CS _R then: This DR expression can be further expanded so that it is expressed only in terms of I UCC and constants. The transconductance of the current source transistor, g m1 , can be expressed in terms of I UCC .

g m1 r o2 g m3 2 + 4g m2 + g m3 ≈ g m1 K CS _R
Since M CS is expected to be in saturation, the transcondcutance is given as:

g m1 = 2k ox W L I UCC (4.47)
This can be inserted in Equation (4.46) to arrive at an expression for DR which is more insightful.

DR ≈ 10 log 10

NI 2 UCC D 1 √ I UCC +D 2 I UCC (4.48)
Where k ox is a technological constant, the left-hand side denominator constant, D 1 is 8kT BW 2k ox W L K CS _R , and the right-hand side denominator constant, D 2 is K K CS _R ln BW. It is observed in simulation that K CS _R decreases as current increases due to decrease in drain-source output resistance. Therefore, the dynamic range value given by Equation (4.48) increases with increase of unit current, I UCC , and then plateaus. If the I UCC is to be controlled off-chip by a reference current as is the case in the implementation of the prototype FIR DAC discussed in Chapter 6, then the dynamic range can be improved by using higher reference current values.

Summary and Conclusions

Starting from basic DAC operation, specification, and architecture, the chapter has evolved to analysis of FIR DACs. A detailed treatment of the pros and cons of the different FIR DAC architectures has been presented. The traditional multi-bit DACs are classed under the a general FIR DAC structure as Lbit, 1-tap, and they are compared with L-bit, N-tap, and 1-bit, N-tap FIR DACs. Furthermore, frequency translation of FIR DACs, from LPF to BPF, and LPF to HPF, is explained theoretically with examples using impulse responses. A novel configurable delay line that can be used to implement these frequency translation is also introduced.

A thorough literature review on FIR DAC is conducted by grouping the different works according to their applications-multi-bit, 1-bit, programmable, receive-band noise filter and amplifying FIR DACs.

Finally, analysis of a current-steering FIR DAC is presented where expressions for coefficient mismatch, yield model, and effect of finite output impedance are derived. The discussion of the last section will be useful in Chapter 6 where the implementation of a FIR DAC in 28nm CMOS FDSOI is discussed.

Chapter 5

Proposed IEEE 802.11ac/ad Transmitter

Baseband Architecture

In the discussion of multi-standard transmitters in Chapter 3, the possibility of multi-standard operation by modifying some circuit blocks of the transmitter has been studied. Many of the works that were reviewed focused on the interface between digital and analog parts of the transmitter. In Chapter 4, the FIR DAC was introduced as a key enabling block for multi-standard transmitter. In this chapter, a FIR DAC based multi-standard, multi-mode transmitter baseband architecture is presented.

The proposed architecture is validated using MATLAB R on system level for two recent multi-Gb/s standards. The chapter will start by introducing these standards. Then in the next section, the main components that make up the digital processing block are presented. This is followed by developing the FIR DAC specification for these standards. The chapter ends by presenting some interesting simulation results.

Specification of the standards

This work takes the IEEE 802.11ac and IEEE 802.11ad WiFi standards as target application. The reason this two standards are selected is the extreme nature of their baseband signals-802.11ac has high resolution, medium bandwidth baseband data and 802.11ad has low resolution, wideband baseband data.

The FIR DAC specification was driven with the requirements of these two standards in mind. In this section, a brief overview of the features, applications and requirements of these standards is stipulated.

IEEE 802.11ac

The IEEE 802.11ac is a VHT WiFi standard that is transmitted in frequency bands at 5 GHz. It extends the 802.11n standard by adding new channel bandwidth options that achieve higher data rates. It also comes with the advantage of avoiding the crowded 2.4 GHz standard. It supports MIMO to reach gigabit data rates. It has the capacity to support data rates of 7 Gb/s using an 8 x 8 MIMO architecture and a 256QAM modulation. However, for portable devices, only a single spatial stream is envisaged, providing An IEEE 802.11ac conforming transmitter has an output spectrum that conforms to the spectrum mask shown in Figure 5.1a. The transmit mask shapes for all of the contiguous channel bandwidths are the same with only the offet frequency changed. A common transmit constellation error is also defined equally for all the contiguous channel bandwidths. There are other additional requirements; however, with respect to the scope of this work they are not applied here.

IEEE 802.11ad

Obstruction and propagation losses, at 60 GHz, limit the applicability of the 802.11ad to line-of-sight and short-range services such as wireless display of data, wireless sync, wireless docking, and high speed file transfer between devices. Since the application area which this standard targets are different from the other standards, the possibility of tri-band single radio operation with the 2.4 GHz 802.11n standard and the 5 GHz 802.11ac standard was discussed in Chapter 2.

The IEEE 802.11ad standard, adopted from WiGig, utilizes the unlicensed spectrum from 57 GHz-66 GHz in Europe [START_REF]telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements. Part 11, Amendment 3[END_REF]. There are four available channels that have a channel spacing of 2.16 GHz.

The 802.11ad PHY supports four modes of with distinct MCS. They are the Control PHY which is transmitted using π 2 -DBPSK modulation; the SC PHY which is transmitted using π 2 -BPSK, π 2 -QPSK, and π 2 -16QAM modulation methods and at different coding rates; the LP SC PHY which shares the same MCS as the SC PHY except for the absence of the π 2 -16QAM; and finally the OFDM PHY which in addition to the MCS listed in the SC PHY includes 64-QAM in its MCS.

All the first three modes have a chip rate of 1.76 GHz whereas the OFDM mode has a 2.64 GHz sample rate. The standard offers data rates up to 6757 Mb/s in OFDM, 4620 Mb/s in SC, and up to 2503 Mb/s with the low power version of the SC mode. In the transmitter side, a common preamble is defined for both OFDM and SC. While a windowing function is defined for the OFDM, the SC fields are not A common transmit mask is defined as shown in Figure 5.1b, and different EVM values for each MCS of the OFDM and SC PHYs. The OFDM mode has additional requirements. However, the target applications of this work are mainly low power mobile devices. Transmission with OFDM tend to result in higher power consumption. Hence, the LP SC PHY of the 802.11ad standard is the target mode.

System Level Simulation of Proposed Transmitter Architecture

The purpose of the system level simulation was to obtain a better understanding of the FIR DAC as part of a complete multi-standard transmitter baseband. It helped to set realistic specifications on the rest of the transmitter chain and assess the potential performance limits of the FIR DAC. Furthermore, from a design point of view, a top-down approach helps to keep exploring a single block without losing sight of what the specifications set on the lower level abstraction of that block guarantee on system level.

Standard Coexistence

As a 60 GHz standard, 802.11ad offers only a line-of-sight, short-range wireless networking. The fact that it does not interfere with nearby communication is one of its strengths. On the contrary, a 802.11ac

transmitter has to still be designed with consideration for its out-of-band noise profile so that it can coexist with others standards. This is despite the fact that the 802.11ac bands at 5 GHz are less crowded than the 2.4 GHz bands.

There are many standards within one octave below the carrier frequencies of the 802.11ac bands.

Some of the nearby standards such as GPS, for example, require the interfering emissions in their receive noise floor to be limited to less than or equal to -174 dBm/Hz . This is the same value as the thermal noise floor at room temperature.

If possible the required value for the PSD of the out-of-band noise profile of the 802.11ac transmitter should not also be greater than -174 dBm/Hz. To take this into consideration while designing the FIR DAC transfer function, some practical assumptions can be taken. The expected output PSD at the receiver due to the interfering out-of-band noise of the transmitter can be equated as:

PS D OOB -P BPF -P ANT -174dBm/Hz

(5.1)

Where P BPF and P ANT are the the power losses which the out-of-band noise experiences on its way to the receiver. A coexistence bandpass filter at the output of the transmitter can be expected to attenuate the noise by about 40 dB. Then there is coupling loss from antenna of 802.11ac to the receiving antenna of the other standard. This can be taken to be around 12 dB.

PS D OOB -40dB -12dB -174dBm/Hz

(5.2) The stopband rejection is then estimated relative to this maximum PSD. Therefore, the filter has to attenuate its stopband spurs by at least -60 dB relative to the PSD in the passband of the transmitted output signal for PS D OOB to be lower than -122 dBm/Hz.

The same approach can be followed for the other modes of the 802.11ac. The PSD for the 20 MHz channel bandwidth becomes -53 dBm/Hz in the passband of the 20 MHz channel, which is about 10 dB higher than that of 160 MHz, at the maximum output power of 20 dBm. Everything being the same, the 20 MHz mode of the FIR DAC has to reduce its spurs by further 10 dB for PS D OOB to be lower than -122 dBm/Hz. Therefore, the filter in the 20 MHz mode of the 802.11ac has to be designed for -72 dBc out-of-band attenuation. The good news is that the 20 MHz channel bandwidth can expect a higher SNR from the DSP blocks compared with the 160 MHz due its higher OSR.

Transmitter Baseband Architecture

This architecture targets devices that normally operate in a high-throughput 802.11ac standard, but can switch the hardware to an 802.11ad configuration for specific LP multi-Gb/s services. Therefore, the two standards complement each other to deliver power-efficient and high speed communication.

Chapter 5. Proposed IEEE 802.11ac/ad Transmitter Baseband Architecture

One of the challenges in designing a single-hardware 802.11ac/ad multistandard transmitter stems from the extreme difference in the nature of the signal to be transmitted, as summarized in Table 5.3.

The 802.11ac presents high-resolution and narrow-to-medium bandwidth channels. On the other hand, the 802.11ad has a low-resolution broadband input. Additionally, the transmitter mask requirements in the 5 GHz bands are more stringent than those at 60 GHz.

A traditional way of transmitting these data is depicted in Chapter 3 using direct conversion architectures with oversampled DACs followed by low-pass filters to reject the image replicas and respect the required transmission masks. To address a multi-standard within the same hardware, one of the works discussed in Chapter 3 introduces a direct-digital RF modulator for 802.11g WLAN, WCDMA, and GSM/EDGE [START_REF] Eloranta | A Multimode Transmitter in 0.13Î 1 4[END_REF]. However, this approach is limited to narrow bandwidth signals because of high OSR requirements. In addition, this architecture requires additional image replica filtering or needs highly programmable sample rate converters, as proposed in [START_REF] Roverato | A programmable DSP front-end for all-digital 4G transmitters[END_REF], to adapt to the appropriate radio channel.

Multi-standard transmitters take advantage of high OSR by introducing noise-shaping ∆Σ modulators to reduce the DAC resolution. This is only possible in the highly oversampled 802.11ac digital front-end path. In the 802.11ad path, the low OSR limits the noise-shaping capability of the modulator. Noise-shaping architectures produce a great deal of quantization noise outside the band of interest, and filtering of this noise is challenging. Otherwise, a high oversampling configuration and an off-chip LC bandpass filter to reject image spectra and minimize the shaped out-of-band quantization noise is required [START_REF] Mohr | An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS[END_REF]. However, the required rejection is hardly achievable for large bandwidths with this method.

In order to overcome image and quantization noise requirements, this architecture proposes a lowpower multi-mode, multi-standard transmitter based on a 1-bit semi-digital filtering DAC, which is configurable for both narrow band and broadband standards, while optimally reusing hardware. The idea is to configure the semi-digital filter to remove the quantization noise in the 802.11ac mode and to shape the broadband channel according to the mask requirements of the 802.11ad standard. This would advantageously replace the multi-bit DAC and the analog low pass filter, while moderately increasing the complexity of the DSP blocks.

DSP Blocks of 802.11ad

The LP SC baseband output of the 802.11ad has a chip rate of 1.76 GHz with a resolution of 1-bit in each I/Q branch in QPSK modulation. To ease filtering of image replicas, the data can be oversampled by a minimum of two to a sample rate of 3.52 GS/s at the FIR DAC input. This can be justified by considering the filtering required to attenuate sampling images sufficiently. A 3.52 GHz clocked DAC output will attenuate the images by at least 2 dB starting from an offset of 2.64 GHz from the center of the desired band of the 802.11ad. However, the required rejection is more than 22 dB, Figure 5.1b, which can be achieved using a reconstruction analog low pass filter following the DAC. Assuming a 2 nd -order filter, it has at least 12 dB/octave roll-off starting the cut-off frequency. Since 2.64 GHz is more than 3 octaves, the desired image rejection is achieved with the a simple analog circuitry. With no oversampling, the same analysis can be done and a complex high-order analog filtering is required to fulfill the spectrum mask requirements. There are different types of oversampling processes that can be implemented for the 802.11ad mode.

Oversampling of the 802.11ad LP SC data with interpolation filters is not required at this stage to avoid adding resolution to the data. As that necessitates usage of multi-bit digital to analog converter, or a delta-sigma modulator to convert it to 1-bit. In the second scenario, as the noise shaping capability of a delta-sigma converter is dependent on the OSR of its input data, a modulator with an OSR of two would not achieve high SNR in its in-band. For example, with a 3 rd -order CRFB 1-bit output delta-sigma modulator at an OSR of two, the peak theoretical in-band SNR is less than 2 dB. It only stabilizes at less than 0.67, i.e. -3.5 dB, of the full scale amplitude [START_REF] Schreier | Delta Sigma Toolbox[END_REF]. A different approach and a different structure of a modulator may achieve better results than the predicted peak, but generally high OSR is required for the delta-sigma to add value.

There was also a possibility to choose an OSR of more than two. In this scenario, the usage of a Chapter 5. Proposed IEEE 802.11ac/ad Transmitter Baseband Architecture delta-sigma modulator is justified as it shapes the noise with high SNR in its in-band. For example, a 2 nd -order modulator with an OSR of six is employed here [START_REF] Bhide | An 11 GS/s 1.1 GHz Bandwidth Interleaved ÎΣ DAC for 60 GHz Radio in 65 nm CMOS[END_REF] for 802.11ad transmitter that also processes higher order modulations such as 16-QAM of the SC mode. For the low power application sought usng the LP SC mode of the 802.11ad, however, an oversampling of two is chosen . An oversampling method which does not introduce new data are upsampling, also called zeroinsertion, and ZOH response. The SINC response of the ZOH introduces passband drooping which degrades the EVM. Thus, a zero-insertion process is chosen as it requires no additional hardware and keeps the passband ripple unchanged. Zero-insertion leaves the added zeros to be shaped by an interpolation filter. The FIR DAC, in this case, is functioning as an interpolation filter.

DSP Blocks of 802.11ac

The required out of band attenuation for the 802.11ac is 60 dBr (discussed in sub-section 5.2.1). The same reconstruction filter as for the 802.11ad is assumed, 2 nd -order low pass filter with 12 dB/octave roll-off. This filter is not considered in the simulation in this chapter. It is only being assumed for analysis. For the 160 MHz channel bandwidth, a stopband rejection of 60 dBr would be obtained at an offset of 2560 MHz assuming the cut-off frequency of the filter is 80 MHz. In other words, the data has to be oversampled by an OSR of 2560 160 or 16. To operate the FIR DAC at lower speeds, a higher order reconstruction filter than the 2 nd -order assumed is needed to filter out the images.

An interesting frequency plan is to use a single clock for the FIR DAC for the two standards. To use 3520 MHz clock rate of the 802.11ad at the FIR DAC, the OSR of 802.11ac has to increase to 22 for the 160 MHz mode. Similarly, the other modes of the 802.11ac are oversampled as tabulated in Table 5.2.

Intermediate DSP blocks clocking requirements are easily derived from the same frequency synthesizer due to the integer relationship between the different sampling rates. This is a necessary sacrifice to optimize hardware sharing, and it makes the proposed architecture, as detailed in Figure 5.3a, easier to adapt to a complete transceiver implementation.

Half-Band Filters

Z -1 f13 Z -1 Z -1 f12 Z -1 Z -1 f11 Z -1 Z -1 f10 Z -1 Z -1 f9 Z -1 Z -1 f8 Z -1 Z -1 f7 Z -1 Z -1 f6 Z -1 Z -1 f5 Z -1 Z -1 f4 Z -1 Z -1 f3 Z -1 Z -1 f2 Z -1 Z -1 f1 Z -1
F2 Sub-filter The responses of the main half-band filter and its sub-filters, F 1 and F 2 , are shown in Figure 5.6.

Sub-filter F1 has a length of five whereas F2 is 14. Interpolation is included in the structure. The plot shown are for an interpolation by two.

As an illustration, for the 160 MHz of the 802.11ac case, the data is resampled by two to reach an sampling rate of 320 Ms/s. The spectrum of the output of the half-band filter for this case is shown in Figure 5.7.

ZOH

The 320 MS/s data are then oversampled by a ZOH by a ratio of 11 to reach the final 3.52 GS/s sampling rate. Interpolation using a ZOH method is straightforward but produces residual images at 320-MHz offsets. However, these images will be eliminated by the semidigital low-pass filtering provided to remove

Delta-Sigma Modulator

A configurable third-order 1-bit delta-sigma modulator, at a noise transfer function gain of 1.6, with coefficient sets adjusted for the four different OSR values, delivers the lowest in-band noise floor for each channel bandwidth of the 802.11ac standard. The modulator has scaled coefficients to guarantee maximum input range and stability. This modulator uses the CRFB topology of the Schreier Toolbox [START_REF] Schreier | Understanding delta-sigma data converters[END_REF]. The configurability of this block can be implemented at the register transfer level with minimum hardware overhead. A 3 rd -order delta-sigma modulator with CIFB architecture whose coefficients are quantized for the four modes of the 802.11ac standard, albeit at relatively higher OSR, is also reported in [START_REF] Marin | Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI[END_REF].

The signal transfer function of the CRFB structure can be made flat in the passband as shown in Figure 5.10 by feeding the input only on the first adder in Figure 5.9 [START_REF] Schreier | Delta Sigma Toolbox[END_REF]. The noise transfer function is optimized to implements a zero in the in-band of the signal.

The output of the ∆Σ modulator with the ZOH output signal as its input is shown in Figure 5.10.

FIR DAC In Three Modes

Coefficients are designed based on mask requirements. Four transmit masks for each mode of 802.11ac and an additional mask for the 802.11ad standard require five sets of coefficients. In the case of 802.11ac, optimization was performed to utilize one set of coefficients for more than one mode. This is based on the SNR of the delta-sigma modulator output and the spectral mask requirements. For the 802.11ad, the transmit mask and EVM performance of different filter types at different lengths were simulated.

802.11ad Mode

FIR filter can be designed with windowing method. The basic idea of this method is that a desired brick-wall filter in frequency domain can be generated by using an infinitely long SINC shaped impulse response in time domain. As this is practically impossible to implement, the length of the SINC function has to be truncated. This results in filter whose frequency response has a transition band with a fast roll-off, but with ripples in the passband. The reason for this behavior is because of multiplication of the SINC function by a rectangular window during truncation.

A better approach is to use a window function which prioritizes some parameter-either passband ripple, stopband ripple or transition band. A Kaiser-Bessel window function has a parameter to trade-off transition band with stopband ripple. This gives the designer a degree of freedom.

Initially the 802.11ad filters was designed based on Kaiser-Bessel window function. The results obtained were a good approximation of the minimum filter length required to achieve the stopband attentuation desired. Then the EVM performance of the designed FIR DACs were compared with the standard requirements. In the case of 802.11ad, the simulated EVM of the designed filter was within a small margin of the standard requirement (-15dB for π 2 -QPSK) even at high filter orders. A large EVM contribution from our blocks puts stringent design requirements on remaining analog circuits of the transmitter. Hence, the Kaiser-Bessel function has to be replaced. The output fulfills the transmit mask requirements with more than 15dB margin.

Since the receive filter for EVM measurement is specified to be an RRC filter with a roll-off factor Chapter 5. Proposed IEEE 802.11ac/ad Transmitter Baseband Architecture of 0.25 [START_REF]telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements. Part 11, Amendment 3[END_REF], it was only right to design the transmit filter with an RRC filter too. The EVM that resulted with the matched filter approach, -52 dB, was found to be a great improve to the methods tried previously.

A simulated FIR DAC response in the 802.11ad mode is shown in Figure 5.11. The coefficients of the 802.11ad filter are quantized to 6-bit and they are compared with the ideal coefficients, shown with 16-bit quantization. As can be seen, the output of the FIR DAC respects the spectrum mask requirements with a large margin.

802.11ac Mode

The delta-sigma modulator coefficients can be reconfigured for each mode of the 802. A 60 dBr stopband rejection is required of the 160 MHz filter. This requirement applies only at the frequencies where transmit mask plateaus ( 3 2 f s in Figure 5.1a). For frequencies before 3 2 f s , the filter need only cancel the delta-sigma modulator shaped noise to less than the mask requirements. To take advantage of this fact, the filters are designed based on an equiripple method with decaying stopband. It has the advantage from equiripple method of having low ripple passband. A stopband that decays by 1 f N avoids the problem of using a long equiripple filter to address the stopband requirements that exist at 3 2 f s but not necessarily earlier frequencies. The passband ripple is set to less than 0.5 dB, the filter order is The EVM of the 160 MHz 802.11ac mode FIR DAC was simulated using Matlab R , and the result for 16-QAM is shown in Figure 5.13. The results compared with the standard requirement leaves a Chapter 5. Proposed IEEE 802.11ac/ad Transmitter Baseband Architecture 12dB margin for the subsequent analog blocks of the transmitter. The results for the other modes of the 802.11ac is in [START_REF] Tsigabu | A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards[END_REF]. The EVM simulation method is discussed in Appendix-2.

From Transfer Function to Circuit Parameters

A configurable FIR DAC is implemented for the 160 MHz 802.11ac and the 802.11ad modes. The circuit level discussions are the subject of Chapter 6. In this section, the system level results obtained are further developed in order to arrive at a thorough multi-standard FIR DAC specification. The discussion include filter coefficient quantization, and choices concerning the FIR DAC performance along the lines of the discussion in Chapter 4.

Coefficient Quantization

The designed 16 th -order 802.11ad filter transfer function with ideal and finite coefficient resolutions is shown in Figure 5.11. Filters with arbitrary valued coefficients are prone to process gradient mismatches, require custom design and layout of coefficients, and have large current source count. Coefficient quantization simplifies the design and allows flexible reconfiguration. Nonetheless, coefficient quantization limits the achievable stopband attenuation level of the filter. The coefficients are quantized to 6-bit. It is interesting to see the degradation due to quantization effects. In the 802.11ad standard, the adjacent channel starts at an offset of 1.22 GHz from the channel center. Quantization with less than 6-bit introduces leakage of up to 15 dB [START_REF] Tsigabu | Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60GHz transmitter[END_REF].

The 20/40/80 MHz mode of the 802.11ac filter design benefits from a higher SNR resulting from the higher OSR of the respective bandwidths at the ∆Σ modulator. Hence, 6-bit quantized coefficients meet the requirements of each mode associated with this filter. For the 160-MHz coefficient set, a ratio of 2 8 exists between the biggest center tap coefficient and the smallest. This is done to reach a higher stopband rejection. This ratio, also called coefficient spread, becomes 2 6 for the 802.11ad and the 20/40/80-MHz cases. Figure 5.15a has the quantized coefficient transfer functions in one plot.

Multi-standard FIR DAC Specifications

As discussed in Chapter 4, the standard deviation of coefficient mismatch can be set to the maximum tolerable stopband value of the transfer function. In the 160 MHz 802.11ac mode, the coefficient values were simulated with a 1.7% standard deviation, and the resulting transfer function is in Figure 5.14. The simulation assumed all the unit elements realizing a coefficient have an independent Gaussian mismatch as discussed in Chapter 4. While it is possible to go further with smaller mismatch requirement, it comes at the cost of area of the current source transistor implementing a coefficient. This is, then, the first design choice to be made when proceeding to FIR DAC implementation.

To implement the two quantized coefficients, those of 160 MHz 802.11ac and 802.11ad, in one FIR DAC circuit, one set of coefficients must be represented by the other. Since the 802.11ac mode has the highest mismatch requirement, the 802.11ad coefficients has to be constructed from it. The 802.11ac coefficients are composed of unit elements, as in unary implementation, with specified mismatch requirements. Then the 802.11ad coefficients has to be integer multiples of these unit coefficients so that they will be constructed using simple analog circuit addition and subtraction. It is important to mention that when each set of coefficients are quantized, each coefficient of a particular set is represented as an integer multiple of a unit coefficient of that coefficient set. Therefore, it should be understood that the 802.11ac and 802.11ad coefficients are quantized by 8-bit and 6-bit, respectively, and their center taps would be 2 8 and 2 6 times the unit coefficients respectively.

The choice of ratio between one set of coefficient and another of a configurable FIR DAC circuit can be made by equating the DC-sum of their coefficients. It is as if equating the full-scale current, in a current steering implementation, of the two coefficient sets. The original sum of the 802.11ad coefficients is 187 11ad-unit coefficients and those of 160 MHz 802.11ac are 4974 11ac-unit coefficients. A ratio of twenty between the two unit coefficients results in 3740 11ac-unit coefficients for 802.11ad mode, and 4974 11ac-unit coefficients for the 802.11ac mode. Therefore, a maximum of 3740 unit coefficients can be shared between the two modes. Figure 5.15b illustrates the coefficients values relative to the unit coefficients of the combined multi-standard FIR DAC.

All the coefficients of the 802.11ad mode may not be obtained by addition and subtraction of the 802.11ac coefficients. In this case, some unit coefficients are added for fine-tuning the sums or difference ‡ I unit is unit coefficient current § Current-Steering Architecture Assumed The specifications of the multi-standard FIR DAC are summarized in Table 5.3. The parameters can used as a starting point of a multi-standard FIR DAC circuit design. Clearly, the FIR DAC has a single sample rate for the two modes. However, the bandwidth of the 802.11ac mode is smaller than the 802.11ad mode. However, the stringent mismatch requirement in the 802.11ac mode is consisent with the requried higher stopband rejection in this mode. The output of the two modes are taken at the same nodes. Their load resistors are also the same. Only their output swing is scaled according to their number of unit coefficients.

Summary and Conclusions

In this chapter, a multi-standard transmitter architecture based on a LPF FIR DAC structure is validated on system level. The specific parametric values for each DSP block of each mode of the transmitter are presented. Further, the response of each block for an 160 MHz OFDM signal are included.

The multi-mode FIR DAC specification that is developed at the end of the chapter will be an input to the next chapter. The coefficients of the multi-mode FIR DAC implemented in Chapter 6 will be the same as those discussed in this chapter. However, a high pass FIR DAC delay line is used for implementation of the circuit. The transistor level implementation of the FIR DAC depends on the coefficient values developed here in this chapter.

Chapter 6

Design and Implementation of A

Configurable Transmitter Baseband in

CMOS 28nm FDSOI

The configurable semi-digital FIR DAC part of the proposed transmitter baseband architecture was fabricated using STMicroelectronics CMOS 28nm FDSOI. In the previous chapter, the discussion was mainly system level validation using MATLAB R based simulation results. In this chapter, transistor level discussions of the circuits used for implementing the explained system, and some layout related issues are explored.

It starts from the a brief introduction of the specification drawn in the previous chapter for the configurable FIR DAC. While the implementation is based on the direct form FIR filter structure discussed, there are some challenges in placement of UCCs. The placement method followed in the implementation of the FIR DAC chip is explained by comparing it to those in traditional multi-bit DACs. Part of this discussion is also part of a published work in [START_REF] Tsigabu | Multi-standard semidigital FIR DAC: A design procedure[END_REF]. The next section explores circuit blocks of the implemented chip. A brief discussion of circuit operation, design, and layout related issues is included.

From System Level to Floorplan

The In the 802.11ad mode, the mode selection signal, S EL, switches the input of the drivers to the second input, in blue in Figure 6.1. All of these inputs are taken from the outputs of the first 17 delay cells. This is consistent with the length of the 802.11ad impulse response. Some of the 17 outputs of the first 17 delay cells are inputs to more than one driver. In other words, that particular tap is driving the sum of the 802.11ac coefficients which correspond to all the drivers connected to that tap. The RoutingMatrix is discussed later in the next section. Coefficients C 64 toC 76 are small valued coefficients which are added to the summed coefficients of the 17 taps to arrive at the exact coefficient values of the 802.11ad.

Mismatch Errors and Layout Floorplan

FIR DAC performance is highly dependent on the accuracy of its coefficients. Coefficient accuracy is in turn dependent on the absolute and relative accuracy of the method used to implement the coefficient.

For example, the FIR DAC is realized using a current-steering DAC structure where current sources are used for implementing the coefficients. Accuracy, in this case, depends on the random errors that are independently defined by the characteristics of the current source implementing a particular coefficient;

and the systematic errors across the array of current sources which contribute a relativistic inaccuracy to that particular coefficient.

MOS transistor mismatch errors are classified as random errors and systematic errors. Random errors are uncorrelated errors that are specific to a particular device. They are defined by technological constants, the area a device occupies and the biasing conditions [START_REF] Marcel | Matching properties of MOS transistors[END_REF]. The systematic errors are a combination of first order linear errors and higher order errors. The linear errors are caused mainly by 6.2. Mismatch Errors and Layout Floorplan 87 IR drop along a ground line, oxide thickness gradients, doping gradients; and the main contributors to the higher order errors are thermal gradients, oxide stress, etc [START_REF] Cong | Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays[END_REF]. It can be understood that the systematic errors are there because of the distance between two or more devices. There is a short enough distance at which the systematic errors are insignificant; or their values are less than the random errors and can be neglected. One design strategy is, then, to make the systematic errors smaller than the random errors regardless of distance.

The random errors can be tackled by sizing the area of the current sources according to the standard deviation required. The bigger a MOS transistor is the lower its random mismatch errors. However, this contributes to the systematic mismatch errors by making the chip large. Some of the systematic errors such as the IR drop along the ground line can be minimized by using power and ground distribution grid for the chip and wide ground lines. However, for large number of devices this results in a significant increase in the total area of the chip. A more effective solution is to place the devices in an array and target the mismatch errors with a systematic placement or switching scheme that results in the cancellation of gradients effects and minimization of higher order errors. This is the solution used in many high resolution current-steering DAC implementation [START_REF] Bosch | Static and Dynamic Performance Limitations for High Speed D/A Converters[END_REF]. Unfortunately, this solution is not effective for a current-steering FIR DAC with long filter lengths.

Pseudo-Double Centroid Placement Method

Unit current cell layout in many high resolution DACs is divided into two or, maybe three, transistor array blocks. The switching parts are placed in one array and the current source transistors in a different array [START_REF] Bosch | Static and Dynamic Performance Limitations for High Speed D/A Converters[END_REF]. Some of the reasons are the following: to minimize the current source array area, to separate the switching and the current source devices, reduce wiring capacitance between switch and cascode transistors [START_REF] Palmers | A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS[END_REF].

One reason that makes the adoption of the aforementioned method possible is the symmetrical power of two weights present in a conventional multi-bit DAC. Since weights are implemented by scaling the width of the current source transistor, total current is divided evenly into each current source transistor.

The errors that occur due to distance can be dealt with effectively if the current source elements are placed in one array. If some of the weights were not power of two, each current source transistor element would carry different current. Error reduction mechanisms such as switching schemes would not be effective. If the non-power-of-two weights are few, they can be implemented as lumped elements. Dummy elements can be used to compensate for any spatial asymmetry that results. However, if all the weights are random, non-power-of-two, dummy elements are the solution.

Another enabling reason for the adoption of that method is because of the relatively reduced number of routing required from the switch array block to the current source array block. For instance, an 8-6 segmented 14-bit DAC has 255x16 unit current sources in unary implementation [START_REF] Vandenbussche | A 14 b 150 Msample/s update rate Q^2 random walk CMOS DAC[END_REF]. These number of current sources are close to those number of unit current cells, 4974, that could have implemented the 802.11ac mode in this FIR DAC. Here, an assumption is made that the smallest coefficient of the FIR DAC is not divided into power of two units. Otherwise, the number of unit current source transistors would be 4974x16. In the example, the distinct number of signals routed from the switch array block to the current source array are only eight. This reduced number allows for employing a switching scheme where the current sources that share the same routing signal can be dispersed as desired. Nonetheless, in the FIR DAC case, this number would have been 63-equal to the number of filter taps. If the current sources are as dispered as a particular switching scheme may demand them to be, then the complexity and speed penalities corresponding to routing 63 signals from a switch array block to a current source array block would be immense. To put it in perspective, if a 64x68 matrix is used for the current source array as the switching scheme in this example [START_REF] Deveugele | A Gradient-Error and Edge-Effect Tolerant Switching Scheme for a High-Accuracy DAC[END_REF], twelve out of the 63 coefficients of the 802.11ac

would have one unit current source in each column and also in each row. That is there would have been at least twelve interconnects in each column since there are twelve coefficients whose values are greater than or equal to 68. The amount of parasitic capacitance mainly due to sidewall capacitance between parallel routing metals would significantly affect the output impedance of those current sources, Equation (4.21) in Chapter 4. Therefore, the idea of placing the current sources in a block separate from the switching blocks was dropped.

To target high speed operation, the placement method for FIR DAC has to be such that the whole unit current cell is placed as if it was a unit current source transistor. The unit current cell, also UCC, contains the digital latch and analog current source that implements a unit coefficient. The unit coefficient is a value which can be combined to arrive at all other coefficients only using addition or subtraction. In a placement method where the UCC is placed as one unit element in an array, the analog signals within The only problem to high speed operation with this placement method increased time constant due to parasitic capacitance and wire resistance. The digital signals are routed in parallel in the array, so resulting parasitic capacitance between them contributes to increase of time constant and signal may be degraded due to crosstalk. These problems can be tackled with careful choice of metals, shielding and wire sizing.

Other placement methods which were explored to be utilized for FIR DACs are those that are used in switched-capacitor filters. These filters have capacitors whose ratios are random, not power of two as traditional multi-bit DAC weights. The switched capacitor filters can also be long. These characteristics of switched-capacitor filters makes their placement method interesting enough for adoption in FIR DACs.

There are many placement methods that are designed for capacitor arrays where linear and quadratic mismatch errors are cancelled even when the values of the capacitors and their ratios are random [START_REF] Fernando | Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization[END_REF]. Nevertheless, the main limitation in adopting these techniques to FIR DAC implementation is the fact that a UCC has nine terminals that has to be routed, unlike two for unit capacitors. Thus, randomly dispersing the UCCs as per the capacitor array placement method dictates does not work. Therefore, a more simpler placement method based on centroid scheme was employed.

A big contribution to systematic errors comes from the first two orders -linear and quadratic.

Mismatch Errors and Layout Floorplan 91

If the diagonals of the device array are assumed to be aligned with the axes of the systematic errors, mathematically, the errors for a device implemented as one unit can be expressed as follows:

(x, y) = lin (x, y) + quad (x, y) (6.1) lin (x, y) = k l,x x + k l,y y (6.2) quad (x, y) = k q,x (x 2 ) + k q,y (y 2 ) (6.3) k q = k q,x cos(θ), and k q = k q,y sin(θ) (6.4) k x and k y are gradient error constants in the x and y directions respectively, and k q,x and k q,y are constant in the x and y directions of the quadratic error, and θ is the angle the axes of the error makes with the x-axis. In a common-centroid scheme, one device is divided in four units which are placed in each quadrant.

Clearly, the linear errors of the device are canceled, but not the quadratic errors. The strategy is to equalize the quadratic errors of all the devices. The best strategy for that is double common-centroid as shown in Figure 6.2. In this scheme, all the devices with more than four unit elements have at least one unit element in each quadrant. For those that have a multiple of four, the quotient are placed in each quadrant in a common-centroid scheme around the center of each quadrant, and the remainder in the center of the UCC array. The units elements of the devices with less than four unit elements including the remainders of those devices represented by more than four units are placed symmetrically around the center of UCC array, i.e. in the CENTER. This scheme approximates the net quadratic error of each device to be equal to the value if the devices were placed as a single device at the center each quadrant.

92

Chapter 6. Design and Implementation of A Configurable Transmitter Baseband in CMOS 28nm FDSOI Let N i be the number of UCCs required to implement a coefficient C i , where 1 i N tap , and N tap is the number of taps of the filter.

N i = 4Q i + R i (6.5)
Q i are number of UCCs of C i placed in each quadrant, and R i are placed in the CENTER of the UCC array. Q i of each quadrant are placed in a common-centroid configuration within that quadrant.

Since the impulse response is symmetrical about the center coefficient, the UCCs that belong to the coefficients that are in the left of the impluse response, in Figure 6.2, are placed in the left parts of each quadrant. Those in the right are mirrored horizontally from those in the left. Quadrant-I is quadrant-II mirrored horizontally, and quadrants III and IV are copied from II and I by mirroring them vertically.

The center coefficients of this odd-numbered impulse response appears in all quadrants in both LEFT and RIGHT. Because of the fact that the placement in each quadrant is not strictly common-centroid, it is called pseudo double common-centroid. A more thorough common-centroid placement method could be used for the Q i s in each quadrant using methods reported in [START_REF] Fernando | Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization[END_REF]. However, since coefficients with units in one quadrant have also units in other quadrants, the linear parts of their systematic errors are generally canceled. Moreover, the other placement methods come with additional costs in routing area and complexity.

The linear and quadratic components of the systematic errors are reduced by this method. For coefficients that has Q i 4, the center of their net quadratic error will be at each section of the quadrant. For example, quadratic errors for two hypothetical coefficients, C 1 and C 2 , with 12 UCCs each in the four quadrants of the UCC array and positioned as the coefficients C 68 and C 72 are shown in Figure 6.4. The figure is scaled with focus on the center of each quadrant so that it fits the page with good visibility. The axis of the quadratic error are assumed to be aligned with the X and Y axis. The three UCCs of C 1 and C 2 in each quadrant have a quadratic error of:

quad,C1,i = k q (x 2 C1,i + y 2 C1,i ) (6.6) quad,C2,i = k q,x (x 2 C2,i + k q,y y 2 C2,i ) (6.7)
and the total error for C 1 and C 2 in all the four quadrants can approximated as:

quad,C1 ≈ 4 3 k q,x x 2 C1,IIL + k q,y y 2 C1,IIL (6.8)
quad,C2 ≈ 4 3 k q,x x 2 C2,IIR + k q,y y 2 C2,IIR (6.9) Thus, the net resultant quadratic error for a coefficient is proportional to the distance between the center of a section of a quadrant and the center of the array. This creates a difference between the 6.2. Mismatch Errors and Layout Floorplan 93 coefficients in the right side of the impulse response and those in the left as those in the right are placed near the center. For C 1 and C 2 , this difference can approximated as:

quad,C1 ≈ 4 3 k q,x ∆ 2 X,C1C2 (6.10)
Besides, there is also quadratic error difference between coefficients with Q i 4 and the smallvalued coefficients that has Q i < 4. The latter has all their UCCs in the CENTER, so their quadratic error is expected to be relatively much smaller. Besides, those coefficients that are around the center of the impulse response have the highest because of they are implemented with higher number of UCCs.

For example, the quadratic error difference between the coefficients C 1 and C 2 and the coefficients C 31 and C 33 highlighted in Figure 6.3 can be approximated as:

quad,C1C31 ≈ 4 k q,x (63x 2 C1,IIL -3x 2 C31,IIL ) + k q,y (63y 2 C1,IIL -3y 2 C31,IIL ) (6.11) quad,C2C33 ≈ 4 k q,x (63x 2 C2,IIR -3x 2 C33,IIR ) + k q,y (63y 2 C2,IIR -3y 2 C33,IIR ) (6.12)
This estimate can be used in the design of the UCC. The effect of the error on the transfer function can be simulated by incorporating this relative error in to the value of each coefficient. Since each coefficient experience different error magnitude, it is preferable to simulate the transfer function with this non-uniform error distribution. However, it is also possible to design the UCCs for a random error which is large enough to accommodate the quadratic error.

One advantage of the placement method is, then, to distribute the UCCs of the highest coefficients around each quadrant so that the cumulative quadratic error of a big coefficient is a sum of the errors that belong to the UCCs near the center of the array, this error is relatively close to zero, and those far away from the center of the quadrant. This way the total sum is reduced.

This advantage is obtained while still canceling the major contributor of the systematic errors-the linear part. The fact that the UCCs of a coefficient are distributed around the array is also a positive feature of this method.

Layout Floorplan

The layout floorplan of the FIR DAC is shown in Figure 6.5. The single bit input data pass vertically to the UCC array, the clock is supplied horizontally from the left using a clock tree and the outputs are summed with a similar output tree in the right. The digital Delay Line outputs are fed to the Routing Matrix which is a matrix of interconnects that enables the UCCs to be driven by the digital data outputs from one or more taps of the delay line. The routed matrix of interconnects are inputs to the Mode Selection 94 Chapter 6. Design and Implementation of A Configurable Transmitter Baseband in CMOS 28nm FDSOI block which basically selects the data out of the delay line. This is done using a mode selection S EL input. The DATA DRIVERS are inserted to compensate for the speed degradation that may result from routing the data to the latches in the UCC array. At the center is the UCC array where the UCCs of the coefficients are placed according to the method discussed in subsection 6.2.1. At the center of the UCC array are the biasing circuits for each section of the four quadrants. The biasing circuits are divided into two parts-Global and Local. The Global circuits at the center of the the chip (GCM block) mirror the input reference current and are supplied with a separate voltage supply. The supply, V DD_BIAS and the reference current are fed to chip from the bottom side as shown in Figure 6.5 and 6.7. There is a common supply voltage, V DD DIG , to all circuits except the biasing circuits. The supply to the biasing circuits is V DD BIAS , and the reasons for this are explained in 6.3.7. The common V DD DIG is routed along with the ground line using a distribution grid. The grid lines pass through each one of the 64 rows and 82 columns of the UCC array. This density is maintained also on the clock tree, and vertically up to the DelayLine. The empty space outside the circuit blocks is filled with decoupling capacitors.

In the UCC array, two high speed analog outputs, power and ground lines, high speed digital clock The mode selection S EL signal was optimized to turn-off the UCC if it is not operating in the selected mode. The S EL signal is also used to: select data inputs in the multiplexers of the mode selection block, set the input of the non-selected multiplexers to ground, and to turn-on and turn-off UCCs.

The digital lines from the output of the DAT ADRIV ERS are routed to the columns where their corresponding UCCs are accessible. There are two data lines in the first column, three in the second column, increasingly towards the middle of a section of a quadrant. This is because most the of UCC in the middle belong to a coefficient with small number of Q i (the number of UCC that belong to a coefficient in one quadrant). As a result, there are more parallel data lines, up to eight, in the middle of a section of each quadrant. For this reason, the data lines in the middle are more loaded with sidewall parasitic capacitance than those data lines on the left and right side of the a section of a quadrant of the UCC array. However, with respect to total parasitic capacitance looking from the output of their respective drivers, the data lines in the middle feed to only a few UCCs and experience smallest input capacitance loading. On the other hand, those at the edge are driving up to 16 UCCs in one section of a quadrant, and experience more loading. This, nevertheless, has been discussed more precisely in subsection 6.3.4.

Since it is a custom layout, careful column by column optimization was done to decrease the number of data lines routed vertically. For example, horizontally propagating data lines using a free metal layer to UCC that belong to the same coefficient. In the UCC layout, the nearby analog signals in one side of the UCCs, the two outputs and two biasing signals, are separated by some horizontal gap and vertically by using different metal layers. The fringe capacitances that resulted were minimal.

Design and Layout of Each Block

The circuit blocks are briefly introduced in subsection 6.2.2 when discussing the floorplan. In this subsection, the circuit topology used, and design strategies followed in each circuit block are discussed.

Digital Delay Line

The outputs of the digital delay line are taken through the routing matrix to the input of the Mode Selection block. Depending on the mode, the output can drive up to seven multiplexers. In the 802.11ac mode, the outputs of each of the flip-flops of the delay line are connected one-to-one with the inputs of the

Mode Selection

In the 802.11ac mode, the mode selection block is a line of multiplexers with as many multiplexers as there are flip-flops in the delay line. There is a one-to-one matching between the delay line outputs and the mode selection inputs. In the 802.11ad mode, these line of multiplexers are driven by a shorter delay line, 17. Since the coefficients of the 802.11ad are only approximated when the 802.11ac coefficients are combined, additional coefficients are needed for fine-tuning. The inputs to these additional coefficients still come from the delay line but they operate only in the 802.11ad mode. Hence, similar to the multiplexers corresponding to the coefficients working only in the 802.11ac mode, one of their inputs are tied to the ground.

The multiplexers are designed based on a transmission gate logic to transfer both high and low values effectively as shown in Figure 6.9. Input and output inverters are inserted to balance loading experienced by the outputs of the delay line and the inputs of the data drivers respectively.

Routing Matrix

The routing matrix is the main block which enables configurability of the FIR DAC. The function of this matrix is to route delay line outputs to multiple coefficients so that a new set of coefficients can be Figure 6.9: A 2-by-1 multiplexer for mode selection created. In the 802.11ac mode, the coefficients match one-to-one with the delay line outputs according to the filter impulse response of 802.11ac in chapter 5. In the 802.11ad mode, they have to be routed according to a summation table.

Data Drivers

The input data to the FIR DAC are sampled first time at the flip-flops of the delay line, and they are synchronized again at the latches that drive the differential switches of the UCCs. Thus, there are two set of paths between the arrival of the data at the input of the DelayLine and at the differential switches of the UCCs. The data time delay between the delay line and the latches has to be less than one clock period minus the hold time required at the flip-flops and the setup time required at the latches. To ensure the data arrives ahead of the clock edge, drivers are inserted between the mode selection and the UCC array. The delay from the output of the delay line to the driver is a small fraction of the period of the clock. However, the delay from the output of the drivers to the input of the latches may not be within the expected margin. The design of data drivers depends on the total load of each data line. For smaller number of UCCs and when the input capacitance of the UCCs, C UCC , is such that the total input capacitance defines the time constant, tapered buffer design which only considers the capacitance as a load can be followed to arrive at to size the drivers. Parity in time delay for each data line can then be reached by sacrificing some area and power consumption by choosing drivers with equal number of stages for even the data lines with smaller number of UCCs. Nevertheless, in some cases, the data lines on the left and right edges of a section of a quadrant drive a high number of UCCs. This is because the UCCs that belong to the biggest coefficients in the impulse response of the FIR DAC are placed in the outer edges of the quadrants with the UCCs that belong to the smallest coefficients in the middle of the quadrants. This is done to equalize the quadratic errors of the randomly-valued coefficients. These data lines normally drive up to 256 UCCs, for example, for the center tap. On the other hand, when there is a long RC interconnect in such a way that the τ rc > τ driver , the equivalent load impedance of the wires should be calculated. The driver has to be designed to make sure the required data rate, and the required bandwidth of the system can be met.

To further explain the point above, Figure 6.12 shows the routing from the output of the driver for coefficient 32 in the 802.11ac impulse response, which is realized with 254 UCCs. The UCCs, as expected, are in common-centroid configuration with two remainders in the center. Each UCC has different RC interconnect delay between itself and the driver. This is clearly shown in Figure 6.13. The All the latches of all the UCCs are clocked with the same signal. The delay difference between the clock edges at two different latches of the 254 UCCs is insignificant; or it is expected to be corrected by the binary tree of the output network. As a result, it is only enough to estimated the worst delay from the driver to one of the latches of the 254 UCCs. The UCCs placed furthest away from the driver are the obvious candidates. To find the worst delay, the total RC interconnect between the driver and the UCC of interest has to be modeled.

A simple RC lumped wire model from the driver output to the input of the UCC of interest may not give us an accurate estimation of the delay-tends to be pessimistic [START_REF] Rabaey | Digital integrated circuits: a design perspective[END_REF]. Hence, unnecessary over design of wire widths, usage of higher metals while not needed could result. Common approximation for a distributed wire model are shown in Figure 6.14. A distributed wire model with the Π-model Figure 6.14: RC interconnect models that can be used for fast, less accurate estimation of delay approximation results in a more accurate, compared with the lumped model, delay estimation. However, the amount of calculation required to estimate the component values could be complex even for a few interconnects. An elaborate wire model may consider metal-to-substrate capacitance, metal-to-metal fringe capacitance, overlap cap, routing resistance, via resistance, etc. In advanced technologies where there are up to ten metal levels, and in a dense layout, this may not be an easy feat.

One formula which gives a practical delay estimation for an RC network with simpler calculations is the Elmore delay formula. The formula assumes a network with one source node where there are no resistive loops and all the capacitors are between a node and ground [START_REF] Rabaey | Digital integrated circuits: a design perspective[END_REF]. Although it is a first-order approximation, its simpler calculation makes it attractive.

Depending on the complexity of the coefficients, the RC segments in Figure 6.13 can be replaced with lumped model of the approximation in Figure 6.14. The Elmore delay from a source S , the driver, to node i, one of the UCCs, is given as [START_REF] Rabaey | Digital integrated circuits: a design perspective[END_REF]:

τ si = N k=1 C k R ik . (6.13)
Where k is a capacitive node in the circuit, and N is the number of nodes. There is a possiblity that the formula can result in large errors. However, it is predicted to work better when the node of interest is farther from the source [START_REF] Alpert | RC delay metrics for performance optimization[END_REF].

It is interesting to derive some quantitative expression for bandwidth limitation calculation using The value of the coefficient can be approximated to 2 B , B is quantization bits. Out of four data lines routed to four quadrants, 2 B 4 UCCs are connected to one. Considering Figure 6.13, each one-fourth of 2 B 4 are placed in one location feeding from a tap from this line. The RC segment between the UCC in each group is neglected. The Elmore delay from the driver output to the furthest UCC along the data line in the left-end of the figure can be calculated as a sum of:

τ si ≥ 2 B 4 C in_UCC R 1 + 2 B 4 C in_UCC R 2 + 2 B 4 C in_UCC R 3 + ( 2 B 4 -1)R 4 + C in_UCC R total_line (6.14) Where R 1 , R 2 ,
τ si ≥ 2 B 4 C in_UCC (R 1 + R 2 + R 3 + R 4 + R total_line ) (6.15) τ si ≥ 2 B 4 C in_UCC (4(Z eq0 + Z eq1 + Z eq2 + Z eq4 ) + 2Z eq8 ) (6.16)
If Z eq8 RC segment is close in length as the other segments, 4(Z eq0 + Z eq1 + Z eq2 + Z eq4 ) + 2Z eq8 can be approximated to be around 3.5R total_line . Then the maximum time constant of this particular line is given as:

τ si ≥ 3.5 2 B 4 R total_line C in_UCC (6.17)

For example, to achieve a bandwidth of 3.52 GHz with 8-bit quantized coefficient and with C in_UCC of around 400 fF, the left-end data line has to be ≤ 1.3KΩ. This can be difficult to fulfill, so it is advisable to use non-shared data lines to a group of UCCs when possible.

The data drivers have a fan-out of four and range from two stage to five stage. A more square layout is obtained by breaking down the longest stages into layers as shown in Figure 6.15. After the final layout of the UCC array, the wire resistance and capacitance were again estimated, and the widths of the wires were changed and choices of adjacent metals changed adjusted in some cases to shorten time delay.

Clock Tree and Output Tree

Two circuit blocks in the chip require clocking. They are the digital delay line, and the synchronizing latches in the UCC array. Due to its size, the clock in the UCC array is distributed with the help of a binary clock tree. The delay line occupies SMALLER area compared to the array. No clock tree is used for the delay line. The clock is supplied with a single metal running across all 63 flip-flops in the delay line. The delay from the clock at the PAD output to the delay line and to that of the clock tree output are equalized by using identical structures. The clock to the digital delay lien is driven by a seven stage buffer whose sizing is equal to a single lea f of the binary clock tree as shown in Figure 6.18. To maintain equal loading at each stage of buffer for the delay line, dummy inverters which have the same sizing as their counterparts in the binary clock tree are used.

The UCC array is arranged by taking the clock distribution into consideration into 64 equally-spaced rows. A top metal is used to route the clock signal along each row from the output of the tree to decrease the capacitance to adjacent metals and to the substrate. The output clock signal of all the 64 rows is shorted with a top metal spine. This is done to reduce timing differences between rows.

The binary clock has seven stages. Each buffer stage is designed at a fan-out of four. The layout is such that the loading at the nodes of a stage are the same; for example, equal width, length and level of wires, and same size of vias.

Although the final clock signal at the output of the binary tree is distributed with a low capacitance top metal routing, there are still timing differences among the UCCs along a single row. Practically, the UCCs to the side of the clock tree are clocked earlier than those farthest in the right. That is the output of those in the left will appear earlier. To balance this difference, a similar binary tree is used for summing FDSOI Figure 6.16: The clock is distributed with a seven stage clock tree to the UCC array, and a single leaf of this tree to the delay line. The inverters in the tree are sized have a fan out of 4. This is kept in the inverter chain to the delay line using dummy inverters. the outputs.

Unit Current Cell

The UCC comprises both the digital and analog current source in one block. A single-ended data is its input. A circuit consisting of a transmission gate and an inverter create the signal for differential switching of the current source. The PMOS and NMOS transistors of the transmission gate are sized in the same ratio as those of the inverter. The differential signals are clocked using a steep transition latch [START_REF] Lin | A 12 bit 2.9 GS/s DAC With IM3 <60 dBc Beyond 1 GHz in 65 nm CMOS[END_REF]. The output of the latches drive the differential switches of the current source. Off-chip loads resistors are used.

Since the data is routed a long distance, a synchronizing latch is added. Each UCC has a synchronizing latch. Some power and area savings could be obtained by sharing one latch for a number of UCC, Figure 6.17: The layout view of the final stage buffers of the clock tree. Each PMOS and NMOS are sized 2 6 times the first stage transistors. The fingers are arranged as such so that the clock tree outputs of each of the 64 rows are routed straight to the UCC array with short wires and with minimum distance between the rows of the UCC array. Figure 6.18: The layout view of the clock tree i.e. data out of one latch to drive switches of multiple current sources that belong a coefficient. The disadvantage in this case is the errors that are incurred due to small timing differences in the switching of the current source of the different UCCs being driven by one latch. This errors depend on the layout and sizing of the latch and the UCCs, but the hard task of placing UCCs in different locations to mitigate mismatch and sharing an equidistant latch for all of them remains. To decrease SFDR degradation due distortion caused by timing differences, the latches of a UCC are placed as close as possible to the differential switches.

One of the advantages of the selected latch is the fact that the output of the latches intersect below the middle point of the signals. By following the latches with inverters, the outputs which control the switches are crossing above the middle point This prevents the possibility of the NMOS differential switches turning off simultaneously. It also guarantees the current never is interrupted as the controls signals allow smooth transition of current from one branch to the other. The crossing point is also set high enough so that the common source node fluctuation is minimized [START_REF] Bastos | A 12-bit intrinsic accuracy high-speed CMOS DAC[END_REF].

The latch was sized so as to decrease its contribution to the total local timing error of the FIR DAC. The following expression for SDR due to random local timing errors is used in the simulation [START_REF] Doris | Widebandwidth high dynamic range D/A converters. The international series in engineering and computer science[END_REF]:

S DR = N (8 f sig f s σ 2 ) (6.18)
where N is the number of unary elements in the 802.11ac or 802.11ad modes of the FIR DAC, f sig is the data bandwidth, f s is clock rate and σ is the standard deviation of the random timing errors.

Contribution to the spread of the timing errors is calculated from mismatch of clocked transistors using capacitive loading, biasing current and technological parameters. Similar approach was used to estimate and consider the error that can be contributed due to capacitive loading difference between the gates of the differential switches of the UCC and the final driving tri-state inverters' output load capacitance.

The tri-state inverters are sized taking the timing errors, and the high crossing control signals for the differential switches into consideration [START_REF] Chen | The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences[END_REF].

A combo of tri-state inverters and input grounding is used to turn-off the UCC when it is not part of the operating mode impulse response. This mechanism ensures that the differential switches stay turnedoff. The same signal as the mode selection signal is the input to the tri-state buffers. Therefore, the signal that selects a standard in the ModeS election block all turns off unused UCCs of the other mode. These arrangement does not change the high-crossing output expected of the tri-state inverters.

The back-to-back inverters are sized small, and they help in reducing the clock feedthrough to the output [START_REF] Bosch | Static and Dynamic Performance Limitations for High Speed D/A Converters[END_REF]. The gate-to-drain charge feedthrough in the differential switches introduces distortion in the outputs. Different methods to mitigate this problem: one is to add a cascode transistor on top of the switches. This method does not suit advanced CMOS nodes as it requires higher analog voltage The overdrive voltage and size of the current source transistor are designed to meet the random mismatch requirement as given by Equation (4.13) in Chapter 4. That is the drain voltage of the current source transistor, M CS , is set to V OV + V tol higher than the overdrive voltage. V tol is a to ensure saturation operation. To operate the cascode transistor in saturation region, the common source node of the switch transistors has to be at least 2V OV + 2V tol . The unit current is set by the dynamic range required at the FDSOI output as explain at the end of Chapter 4. Large number of UCCs, 4974 in the 802.11ac mode, sum up to a large output swing. This takes big part of the voltage headroom in a low voltage supply operation of the UCC. To ensure saturation region operation of the differential switch transistors V DD ANA -N unit R load I unit 3V OV + 3V tol .

(6.19)

The effect of data dependent output impedance on the dynamic performance of the FIR DAC is already discussed in chapter 4. To ensure high output impedance up to higher frequencies, minimizing unnecessary interconnects during layout of the UCC is important. The contribution of the parasitic capacitances due to interconnect is minimum in this implementation. That means the output impedance will stay flat up to higher frequencies, but the actual values depends on the sizing and biasing of the transistors. This was set through simulation in Cadence R and MATLAB R by tweaking the biasing voltages and sizes of the transistors.

To obtain a more square layout of the current source transistor, it is realized using two identical transistors in series. The current source and cascode transistors are placed inside a guard ring. To stabilize the supply voltage of the UCC, a NMOS decap is connected in the gap between V DD and GND planes.

Biasing circuits

For best dynamic performance of the UCC, the current mirror needs to target ideal requirements. The relationship between SFDR of UCC and output impedance is already stated in Chapter 4. Ideally, a current mirror should also have low input resistance. Technological limits such as supply voltage also limit the input and output voltage swings a particular topology of a current mirror can offer. These practical parameters can be used from the selection of the circuit topology to its sizing.

Although supply voltage limit in advanced CMOS nodes discourages use of cascoding, the high speed operation targeted requires high output impedance, and cascode current mirrors generally fulfill that requirement. A classic cascode current mirror circuit is shown in Figure 6.21a. It offers high output resistance and low input resistance given by the equation (6.20). Assuming the threshold voltages of both transistors are equal to V T , replacing V G4 by V G3 , and V S 4 by

V D3 , V G3 -VT > V D3 , (6.23) V G3 -VT -V S 3 > V D3 -V S 3 . (6.24)
As a result, V DS of M 3 is normally one V T lower than gate voltage of V 4 . It is also useful to note that the aspect ratio of M 3 is a fraction of the sizes of the other transistors(M 1 , M 2 , M 4 ) which have identical sizes. This can introduce some non-uniformity in the layout. In this implementation M 3 is replaced with two gate-shorted transistors M 3b and M 3a whose length should effectively add.

With some assumptions of equal threshold voltages, an approximate size of M 3 can be calculated.

Both are working in triode, then their input drain current can be approximated by this equation

I in1 = K 2 W L 3b 2(V GS 3b -V T )V DS 3b -V 2 DS 3b = K 2 W L 3a 2(V GS 3a -V T )V DS 3a -V 2 DS 3a (6.25) 6.3. Design and Layout of Each Block 113 K is a technological constant. 2(V GS 3b -V T )V DS 3b -V 2 DS 3b = 2(V GS 3a -V T )V DS 3a -V 2 DS 2 (6.26)
If we make further assumption that drain-source voltage of M 3b is V OV , and that of M 3a to be V OV 2 , (6.26) leads to

2(V G -V OV 2 -V T )V OV -V 2 OV = 2(V G -V T ) V OV 2 - V 2 OV 4 (6.27) V G -V T = 7V OV 4 (6.28)
Another equation can be derived from the drain currents of M 4 and M 3b as follows:

I in1 = K 2 W L 4 V GS 4 -V T 2 = K 2 W L 3b 2(V GS 3b -V T )V DS 3b -V 2 DS 3b (6.29)
The ratio of transistor M 4 to M 3 can then be written as:

W L 4 W L 3b = 2(V GS 3b -V T )V DS 3 -V 2 DS 3b V GS 4 -V T 2 (6.30)
Equating (6.28) and (6.29) and substituting the previous assumption on the drain-source voltages of M 3a and M 3b and , the ratio can be simplified to

W L 4 W L 3b = 2 7V OV 4 - V OV 2 3V OV 2 - V 2 OV 4 7V OV 4 -V OV 2 (6.31) W L 4 W L 3b ≈ 6. (6.32)
While the design is robust with respect to output resistance, input resistances, and minimum output votage, the input voltages of this configuration proposed in this implementation are higher compared to those in Figure 6.21a and Figure 6.22. As a result, it is important to calculate the minimum input voltage for both branches so that the minimum supply voltage can be known. This helps in determining the suitability of this configuration for low voltage operation. V DD_BIAS ,min = max(V in1,min , V in2,min ) + 2(V T + V OV ) = 3V T + 9V OV

V in1,min = V GS 4 + V DS 3b + V DS 3a V T + V OV + V OV + V OV 2 V T + 5V OV 2 (6.33) V in2,min = V GS 1 V T + V OV (

(6.35)

To support this theoretical calculation, a simulation of the circuit shown is done in CMOS 28nm FDSOI. The result can be seen in Figure 6.24.

Summary and Conclusions

In this chapter, the system-level results of a configurable FIR DAC from the previous chapter were used to design the circuit blocks of the FIR DAC. A thorough discussion starting from the floorplan to the circuit blocks of the DAC has been provided. A pseudo-double common centroid placement method for current steering FIR DAC architectures is introduced. The strength and weakness of this placement method based on its resilience to systematic mismatch errors is also discussed. The layout floorplan of the FIR DAC chip is detailed.

Besides, the different challenges faced during circuit design of each block are examined. Layout level discussion are included as needed to clarify the approaches followed. In the next chapter, a report of measurement of the designed circuit is included. To characterize the prototype FIR DAC circuit, it was first packaged in a QFN40 plastic open cavity package. Then a test PCB was designed using Altium R PCB designer. The package has small leads and only in its underneath. An efficient and reliable way to solder the package is to use an automatic or a semi-automatic machine. The JFP Microtechnic R PP7 semi automatic pick and place die bonder was used for soldering the packaged die to the PCB at the right temperature gradient.

This chapter begins with the experimental setup section. Any specific choices with the designed PCB, or the instruments and connectors used are discussed in this section. The prototype FIR DAC is characterized using different inputs. Thus, the transmitter setup in Matlab R from which the input data is generated is also explained. In the next section, the actual measurement results for the two modes of operation of the FIR DAC are discussed separately. Discrepancies between theoretical or simulated results and the measured results are also presented in the same section. Finally, the chapter is closed with a last section which compares the obtained results to other works in the same area.

Experimental Setup

The designed circuit is that of a high pass FIR DAC that implements two impulse responses. The prototype chip in

PCB Design

The S EL input is switched HIGH for the impulse response of the 160 MHz 802.11ac, and it is LOW for that of IEEE 802.11ad. It can be supplied from V DD DIG and GND. The DAT A input takes 1-bit digital data with the HIGH value set at V DD DIG and the LOW value set at GND. The clock is also a digital input, set on the same levels. Since both DAT A and CLOCK have on-chip input drivers, the CLOCK input can also be driven with a sinusoidal waveform and a DC offset. For standard 802.11ac measurement, the DAT A is first generated in Matlab R and then transferred to a Data Timing Generator.

The supply inputs are all within a range of any standard source meter, so they are directly connected on the board. The differential outputs have to be connected to load resistors.

The chip was packaged in QFN40 plastic package using standard wirebond techniques. The PCB was separately designed using standard FR4 material in two layers. The instrument-generated high speed inputs are connected using SMAs, so a 50Ω track from the SMAs was terminated with 50Ω SMD resistors close to the package pads of CLOCK and DAT A as shown in a circuit depiction in Figure 7.2a.

Stabilizing capacitors are connected to V DD DIG and V DD BIAS . The rest of the inputs are connected using screw connected power connectors. The analog outputs were initially designed to be connected to 25Ω load resistors. The initial solution was to use a transformer. However, the available bandpass baluns were not suitable for low frequency measurement. Besides, directly connecting the outputs to probes was found to be less susceptible to noise. The final measurement was carried out using 50Ω load resistors from probes. The analog outputs were directly connected to an oscilloscope and spectrum analyzer using Agilent E2695A differential SMA probe head and Agilent U1818A active differential probe. The probe head has a bandwidth of around 7 GHz which is above the expected maximum output frequency. The circuit of the probes is The unit coefficient is equivalent to a drop of 2.7 µA on a 50 Ω load, and the current values for the rest of the coefficients are an integer multiples of I REF on the same load. The passband of the magnitude responses experience a drop of 6.5 dB and 10 dB, compared to the a 0 dB gain full-scale values, for the 802.11ac and 802.11ad modes respectively. The reason this value of reference current was selected is to adjust the DC bias conditions to the load resistors of the output differential probes. High reference current results in the triode operation of the switch transistors of the UCC for the analog supply voltage indicated in Figure 7.2a. In cases where a different value of reference current is used, for different reasons, it will be indicated. However, the figures should help as a reference at this value of current.

The FIR DAC was characterized for its performance as a standalone filter and as a FIR DAC as part of a transmitter in each mode of operation. In the 802.11ac mode, actual 802.11ac modulated signal was used to test the chip for wideband operation with different MCSs. Then PRBS input data was used to characterize the FIR DAC as a filter. Single-tone signals were also used to check the dynamic performance of the FIR DAC, and they are included in the last parts of 802.11ac sub-sections.

Biasing Circuits

The first sub-section is measurement of the wide-swing biasing circuits used in the FIR DAC. A detailed analysis of the circuits in transistor level of abstraction is already included in Chapter 6. During measurement, the operation of the mirroring circuits at different parts of the FIR DAC chip was tested by varying the biasing voltage. There were wide-swing mirroring circuits in each of the quadrants of the UCC array. An additional replica circuit was used to generate the UCC current source biasing voltages-V CAS and V CS -for testing purposes. The measurement shown in Figure 7.7 is the values of these output UCC bias voltages.

As their name suggests, V CS is the gate bias voltage of the current source transistor and V CAS is the gate bias voltage of the cascode transistor of the current source of the UCC. The current flow is mainly controlled by V CS . This value also sets the overdrive voltage which is critical to the value of random current source transistor threshold voltage mismatch used in design. Both voltages set the DC bias, output impedance of the cascode current source. Thus, it is important the circuit works where both the bias voltages are stable.

The current gain is estimated by dividing the measured total current flow in analog supply voltage to the product of the total number of UCCs in the 802.11ac, 4974, and the reference current, 2.7 µA. This measurement is independent of input signal type and clock frequency. The result as can be seen in Figure 7.7 closely follows the transistor level simulation plot at the end of Chapter 6. The bias supply voltage, V DD BIAS , is selected, as expected, at values where the current gain plateaus and the bias voltages are stable.

Power Consumption

The total power consumption of the chip in each mode of the FIR DAC chip is obtained by summing the power consumption of the digital circuits, which are supplied by V DD DIG , the static current sources,

Measured Results

123

which are supplied by V DD ANA , and the biasing circuits, whose supply is V DD BIAS .

The digital part of the power consumption changes with frequency of the clock. In order to find the maximum average power consumption, the chip was run at the highest input bandwidth, up to f s 2 , at different clock frequencies. A PRBS input which has a pattern cycle period of 2 23 -1 and a mark density of 1 2 was employed as an input. The measured power consumption and supply voltages for the two modes of the chip up to 1.4 GHz clock frequency is plotted in Figure 7.8. As explained in sub-section 7.2.3 in this chapter, the digital circuit were run at higher supply voltages after 650 MHz. The value of the digital supply voltage is taken where no significant change in the current consumption of the digital circuits was observed. The circuit was run up to a maximum value of 1.325 V in 1.4 GHz as shown in Figure 7.8. As expected the power consumption of the digital circuits in the 802.11ad mode is lower owing to the smaller number of UCCs in this mode. It is also true that the consumption increases linearly with frequency: first in the 100 MHz to 600 MHz range for a constant V DD DIG of 1 V, and then beyond 650

MHz. The effect of the small incremental changes in the digital supply voltage beyond 650 MHz is more pronounced in the 802.11ad power consumption.

Similarly, the consumption of the analog current sources is higher in the 802.11ad mode than the 802.11ac mode. It shows a proportional increase, independent of the clock frequency or type of input signal, due to the fact that the number of unit current sources in the 802.11ac mode are approximately 1.3 times those in 802.11ad mode. The results are shown in Table 7.1. Although the power consumption * Actually, ≈ 1.9 V including IR-drop in 50Ω common mode resistor † For a 2.7 µA reference current contribution from the biasing circuits is minimal, their power consumption is also tabulated in Table 7.1.

The power consumption of the biasing circuits are the same for the two modes.

The table also contains total power consumptions for both the 802.11ac and the 802.11ad modes.

Two results at two clock frequencies, 600 MHz and 1.4 GHz, are shown to put the change in the digital supply voltage in perspective.

Finally, when the measured power consumption at 1.4 GHz is compared with the simulated values, it has almost doubled. For example, a total power consumption of 115 mW from a 1 V digital supply was simulated in the 802.11ac mode at 3.52 GHz clock frequency. If the power consumption contribution from the digital circuits was adjusted to 1 V assuming the same current is drawn, as with the 1.325 V supply, at 1.4 GHz, the consumption would still be higher by around 50% compared to the simulated value. Similar comparisons can be made in the 802.11ad mode.

IEEE 802.11ac Mode

In Besides, it can be seen that the ripple in the desired band has changed due to the NRZ clocking used in x attenuation across the desired band. This introduces a ripple in the passband which degrades the desired spectral flatness. The smaller the desired bandwidth, the smaller the ripple due to the holding nature of the clock. The effect of this for a bandwidth of 27.3 MHz at a 600 MHz clock is about 1.6 dB as can be seen in Figure 7.9. The FIR DAC is expected to have a bandwidth of 4.54 MHz output at 100 MHz clock. However, the input is only 1 3 at 1.51 MHz. The filter attenuates the images as can be seen in Figure 7.10 with the ∆Σ modulator input superimposed on the output. Besides, a power level of -18 dBm is reached with a reference current of 3.2 µA. The input is plotted by DC blocking the Matlab R -generated pattern.

Characterization as a Filter with PRBS DAT A

The FIR DAC 802.11ac mode was further characterized with a 1-bit PRBS data which has a pattern cycle period of 2 23 -1 and a mark density of 1 2 . The data is generated using a Tektronix R DTG 5334 data timing generator. The test was carried out at different clock frequencies. In this mode, the bandwidth of the filter was set to f CLK 2 by connecting the S EL input to ground. The setup from Figure 7.2a is also used here except the analog supply voltage is decreased to 1.6 V. This is because the full-scale output current decreases in this mode and the switch transistors of the current sources in the UCCs has to be protected from drain-to-source over-voltage.

To test the chip as a DAC in the 802.11ad, the 1-bit input data has to be upsampled by two as indicated in the transmitter architecture discussed in Chapter 5. For the high pass FIR DAC circuit implemented in this work, the input has to be mixed and upconverted so that the center of its bandwidth lies at f s 2 . For a truly random signal, this process does not change the frequency characteristics of the signal. Hence, a PRBS signal clocked at the update rate of the FIR DAC is employed for characterizing the chip in this mode of operation. The large clock feedthrough observed in Figure 7.14 normally should be at a level which is a fraction of the maximum output swing. In this case, it tends to be on the same power as the frequency components in the passband of the FIR DAC. Another mechanism is to select the output at the first image. One reason for this is that there is less passband ripple at around 1.5 f s as the NRZ response of the FIR DAC plateaus at the middle of the first side lobe. Another advantage for selecting this image is to obtain a higher carrier frequency for transmission. However, this comes at a cost. One disadvantage is that output has a large power reduction as the lobes of the sin(x) x response of the FIR DAC decrease by more than 10 dB at around 1.5 f s .

Characterization of Channelization of PRBS DAT A

Characterization of Impulse Response with Known Sequence

The 802.11ad mode unit coefficient is scaled 20 times the 802.11ac mode unit coefficient. For this reason the impulse response of the 802.11ad have bigger sized coefficients, and it is easier to measure even with low reference current values. Since this measurement is strictly about the coefficient sizes, it is measured at lower clock frequencies to avoid effect of high frequency dynamic errors.

The output of the FIR DAC in the 802.11ad mode for a repetitive 34 sample sequence, given as:

Data = 1, 1, 0, 0, . . . , 0, 0 Tests were carried out with increased digital supply voltage. In the 802.11ac mode, PRBS data was used to check the output power performance of the chip at 1 GHz and 1.4 GHz. As can be seen in Figure 7.17, the output swing of the UCC drops fast as the update rate increases. For a 1 GHz clock rate, the power spectral density is barely crossing -54 dBm/1.1 MHz.

Decreasing the input bandwidth does improve the filtering performance of the chip. In Figure 7.18, the output power reaches a -44 dBm/3 MHz spectral density across the bandwidth.

Comparison with the State of the Art

In this subsection, the performance of the test chip is compared with other digital-to-RF converters targeting low power all-digital wireless transmitters. Some of the interesting differences are tabulated in It can be seen that, the work outperforms in processing wideband signals, up to 700 MHz in the 802.11ad mode. This bandwidth is measured with a clock frequency of 1.4 GHz. In the 802.11ac mode, higher clock frequency, a maximum of 3 GHz, are reached by increasing the digital supply voltage.

However, due to the medium bandwidth targeted with this mode, the input signal bandwidth is limited to 136 MHz.

The advantage of the high pass FIR DAC structure over the LPF and BPF structures is its ability to achieve higher carrier frequency for the same clock speed. A maximum output carrier frequency of 1.5

GHz in the 802.11ac mode and 700 MHz in the 802.11ad mode.

The output power is reported for the full-scale current at a 50 Ω output load network. The output swing is improved compared with what is reported in the other works with an exception to the value reported in [START_REF] Morteza | A Wideband 2x13-bit All-Digital I/Q RF-DAC[END_REF] where a combining output network is used to reach a peak output power of 22.8 dBm.

Although this work is expected to take advantage of technology scaling to lower the power consumption, it suffers from increased number of UCCs. This is mainly due to the targeted out-of-band noise profile of -60 dBr required up to 4974 UCCs. The power consumption values in the table are at a clock frequency of 1.4 GHz. The power consumption for measurements with a wideband OFDM input signal § f CLK = 1.4GHz ‡ P Cons = Total power consumption 7.3. Conclusions 135 tend to plateau when the clock frequency increases to its maximum value of 3 GHz. One observation common to all cases of measurement was the robustness of the circuit to delay difference between the CLOCK and DAT A signals. The delay could be varied up to 5 ns with the data timing generator. The circuit was tested with a ∆Σ modulator output signal where the input DAT A was delayed, sweepingly, from 0 ns upto 1 2 f s . The circuit was able to deliver expected output even when the input pattern was run for a fixed number of loops. The reason for this is the robustness of the digital delay line against set-up time errors.

There are many conclusions that can be drawn for the measurements presented in this chapter. Despite the fact that the measurement results differ from the theoretically expected results, the validity of the configurable FIR DAC concept is shown. The concept of digitally switching unit current sources and summing them in analog to implement a DAC with different filtering behavior is validated.

While the static part of the FIR DAC circuit has worked reliably. The expected parametric results in the dynamic parts of the circuit were not obtained. Common to both modes is the failure in high clock frequency. The contribution of technology maturity is not to be underestimated, but there are also some improvements that should have been made in circuit implementation that could have decreased the noise level observed in the single-tone measurements results.

The next chapter will include some recommendations for improving the performance of configurable, high speed, high resolution FIR DACs.

Chapter 8

Conclusions and Future Directions Conclusions

This work provides theoretical analysis, simulation-based validation of FIR DAC based circuits and transmitter architectures. Besides, a prototype chip is measured to validate the use of FIR DAC for multi-standard transmitter implementation. The circuit is tested to work up to a clock frequency of 3 GHz in the medium bandwidth mode while consuming a power consumption of 108.9 mW. It is also characterized in the wide bandwidth mode up to a clock frequency of 1.4 GHz while consuming 86.89 mW of power.

Future Directions

Some recommendations are listed below to improve the multi-mode FIR DAC circuit to achieve a stateof-the-art performance at multi-GHz digital-to-RF conversion.

• As discussed in Chapter 6, the data drivers were placed on one-side of the UCC array. A discussion was included on the possible bandwidth limitation that could result due to parasitic loading. To solve this problem, another set of data driver can be inserted in the middle of the UCC array. There will not be a significant increase in power consumption as the load is divided. Similar technique can be followed for the clock. Additional set of driver can be inserted in the CENT ER of the UCC array to balance the delay between two UCC at each end of the clock line.

• As mentioned in the Chapter 7, the output of the HP FIR DAC suffered from the ZOH nature of the clocking used. To improve this, the FIR DAC UCC can be redesigned for an RZ implementation, or better yet other types of implementation which have a peak at around f s 2 .

• The FIR DAC circuit area can be improved by designing a UCC which exploits the symmetry that exists in a linear-phase FIR filter impulse response. The obvious method is to use some decoding logic to reuse the same UCC. The way this works is that the UCC is turned-off when the two coefficients have opposite data values and works normally for the other two cases. To turn-off the 138 Chapter 8. Conclusions and Future Directions UCC, the current source or the two switches can be turned-off. Thus, there will be two control signals for each tap. However, this can affect the speed that can be reached and, more importantly, distortion may be caused due to mismatches on the timing of turn-off and operation of UCC.

To decrease this distortion, an easier way is to redesign the UCC to have three switches to smoothly transfer I UCC into two output and one additional redundant branches for the possible combination values of two taps i.e. -2, 0, and 2. However, still two control signals are needed.

• The clock and data signals are on metal layers four and ten respectively. This prevents crosstalk. However, to separate them, the placement method has to change. A new placement which maintains the strengths of the pseudo-double common centroid placement method, but separates the digital and analog grounds, crossing of digital signals among other things can bring improvement.

• There are works at multi-GHz frequencies that embedded filtering in a DAC. However, the FIR DAC structure is yet to be reported at those frequencies. Had there been one, it would have been a good reference for comparing a 1-bit, N-tap digital-to-RF processor performance against a traditional L-bit, 1-tap DAC. Transistor level simulation of the work reported in [START_REF] Tsigabu | Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60GHz transmitter[END_REF] showed promising results. A demonstrator chip of the system-level findings in that paper could provide the reference work to appraise the strengths and weakness of the FIR DAC approach.

• A final recommendation is on the general FIR DAC structure. It would be interesting to quantitatively compare the three structures presented in Chapter 4: L-bit, N-tap; 1-bit, N-tap; and L-bit, 1-tap. i f eq ( SEL , 1 ) SigRx ( 1 : 2 8 , i ) = SigFFT ( 3 : 3 0 , i ) ; SigRx ( 2 9 : 5 6 , i ) = SigFFT ( 3 5 : 6 2 , i ) ; e l s e i f eq ( SEL , 2 )

SigRx ( 1 : 5 7 , i ) = SigFFT ( 4 : 6 0 , i ) ; SigRx ( 5 8 : 1 1 4 , i ) = SigFFT ( 6 9 : 1 2 5 , i ) ; e l s e i f eq ( SEL , 3 ) SigRx ( 1 : 1 2 1 , i ) = SigFFT ( 4 : 1 2 4 , i ) ; SigRx ( 1 2 2 : 2 4 2 , i ) = SigFFT ( 1 3 3 : 2 5 3 , i ) ; e l s e % E x a c t P o s i t i o n o f p i l o t and d a t a s u b c a r r i e r s f o r t h e 160 MHz mode SigRx ( 1 : 1 9 , i ) = SigFFT ( 5 : 2 3 , i ) ; SigRx ( 2 0 : 4 6 , i ) = SigFFT ( 2 5 : 5 1 , i ) ; SigRx ( 4 7 : 8 1 , i ) = SigFFT ( 5 3 : 8 7 , i ) ; SigRx ( 8 2 : 1 0 8 , i ) = SigFFT ( 8 9 : 1 1 5 , i ) ; SigRx ( 1 0 9 : 1 1 7 , i ) = SigFFT ( 1 1 7 : 1 2 5 , i ) ; SigRx ( 1 1 8 : 1 2 6 , i ) = SigFFT ( 1 2 9 : 1 3 7 , i ) ; SigRx ( 1 2 7 : 1 5 3 , i ) = SigFFT ( 1 3 9 : 1 6 5 , i ) ; SigRx ( 1 5 4 : 1 8 8 , i ) = SigFFT ( 1 6 7 : 2 0 1 , i ) ; SigRx ( 1 8 9 : 2 1 5 , i ) = SigFFT ( 2 0 3 : 2 2 9 , i ) ; SigRx ( 2 1 6 : 2 3 4 , i ) = SigFFT ( 2 3 1 : 2 4 9 , i ) ; SigRx ( 2 3 5 : 2 5 3 , i ) = SigFFT ( 2 6 1 : 2 7 9 , i ) ; SigRx ( 2 5 4 : 2 8 0 , i ) = SigFFT ( 2 8 2 : 3 0 8 , i ) ; SigRx ( 2 8 1 : 3 1 5 , i ) = SigFFT ( 3 1 0 : 3 4 4 , i ) ; SigRx ( 3 1 6 : 3 4 2 , i ) = SigFFT ( 3 4 6 : 3 7 2 , i ) ; SigRx ( 3 4 3 : 3 5 1 , i ) = SigFFT ( 3 7 4 : 3 8 2 , i ) ; SigRx ( 3 5 2 : 3 6 0 , i ) = SigFFT ( 3 8 6 : 3 9 4 , i ) ; SigRx ( 3 6 1 : 3 8 7 , i ) = SigFFT ( 3 9 7 : 4 2 3 , i ) ; SigRx ( 3 8 8 : 4 2 2 , i ) = SigFFT ( 4 2 5 : 4 5 9 , i ) ; SigRx ( 4 2 3 : 4 4 9 , i ) = SigFFT ( 4 6 1 : 4 8 7 , i ) ; SigRx ( 4 5 0 : 4 6 8 , i ) = SigFFT ( 4 8 9 : 5 0 7 , i ) ; end end

  My work was initially funded through the French ANR WENDY project. It was a collaborative project among IEMN, STMicroelectronics and IMS Bordeaux. I would like to thank the team members of that project: Prof. Yann Deval, Dr. Didier Belot, Dr. Mathieu Vallet, Dr. Olivier-cro Richard, and Dr. Sebastien Dedieu. Yann and Didier are also members of my doctoral jury. I would like thank them and the other members of the jury for accepting the invitations. I am also grateful to Dr. Andreia Cathelin and Dr. Philippe Cathelin for the important comments and suggestions they had given me at different periods of my research. Finally, I would like to thank my friends and my family members. My brothers, my sisters and my parents have always been supportive, considerate and appreciative of whatever endeavor I have taken. I send them my heartfelt gratitude. The last eight months of my doctoral study have been the most satisfying. I thank Seli for her support and love! vi List of Figures2.1 Evolution of theoretical data rates of wireless technologies from first generation networks to current giga-bit data rate 4G networks . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Mobile data traffic by 2020 as predicted by Cisco in [CVM16]. Global mobile data traffic is expected to grow eightfold between 2015 and 2020 with a compound annual growth rate of 53% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Expected IMT-2020 capabilities as compared with those of IMT-Advanced [ITU15] . . . 8 2.4 A 5G device will have to support multiple existing RATs and new ones. The expected capabilities that different parts of the device are shown here[Ban+14b] . . . . . . . . . . 9 2.5 Block diagram of a configurable transceiver for WiFi and WiGig applications . . . . . . 10 3.1 Essentials blocks of a basic WLAN transmitter. In traditional transmitter, the mixer follows the DAC. However, they can also be implemented in the same circuit. . . . . . . 14 3.2 Constellation diagrams of 16-QAM modulation in 802.11ac and 802.11ad standards, and π 2 -QPSK modulation of the LP SC mode of the 802.11ad standard . . . . . . . . . . . . 16 3.3 Basic blocks in the generation of one OFDM symbol . . . . . . . . . . . . . . . . . . . 16 3.4 PSD of a 160 MHz, 802.11ac OFDM symbol using a hann window . . . . . . . . . . . . 173.5 Time domain plot of a 160 MHz, 802.11ac OFDM symbol . . . . . . . . . . . . . . . . 17 3.6 Direct Conversion transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Heterodyne transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 General block diagram of a polar transmitter . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 The ACPR is defined based on the spacing of the main, adjacent and alternate channels in this figure. The ACPR and Alternate CPR measurement results of Chapter 7 are also consistent with this definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 Block diagram of the digital quadrature mixer based on LPF ∆Σ modulator in [Fra+09] . 24 3.11 Block diagram of the DDRM in [Elo+07] . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Block diagram of the digital-IF direct conversion transmitter in [JS07] . . . . . . . . . . 26 3.13 Block diagram of the digital-IF transmitter with embedded FIR filtering RF DAC in [Tal+08] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 Block diagram direct conversion transmitter architecture for IEEE 802.11ac based on LPF FIR DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 x List of Figures 3.15 Block diagram direct conversion transmitter architecture with upconverted ∆Σ input to a BPF FIR DAC. r is ratio of f IF to f CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 Block diagram of digital-IF transmitter architecture based on ∆Σ BPF/HPF FIR DAC . . 4.1 Time domain operation of a DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Frequency domain operation of a DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Metrics of the dynamic performance of a DAC . . . . . . . . . . . . . . . . . . . . . . . 4.4 A Nbit R-2R resistance ladder DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 A Nbit resistor string DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 A thermometric current steering DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 A segmented current steering DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 A general L-bit, N-tap FIR DAC architecture . . . . . . . . . . . . . . . . . . . . . . . 4.9 Impulse response of LPF FIR and its frequency translated HPF version . . . . . . . . . . 4.10 Magnitude response of LPF FIR and its frequency translated HPF version . . . . . . . . 4.11 Impulse response of LPF FIR and its frequency translated BPF version . . . . . . . . . . 4.12 Magnitude response of LPF FIR and its frequency translated BPF version . . . . . . . . 4.13 Transformation of a 1-bit FIR DAC from LPF to BPF and HPF using a configurable delay line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 An optimized configurable delay line with only 2(N -1) switches and 2N -1 delay cells. 4.15 Current-mode FIR DAC architecture in [SW93] . . . . . . . . . . . . . . . . . . . . . . 4.16 Current steering FIR DAC architecture in [AR01] . . . . . . . . . . . . . . . . . . . . . 4.17 General structure of the reconfigurable bandpass FIR power DAC architecture in [Fla+08] 4.18 Current-steering structure for implementing a FIR DAC . . . . . . . . . . . . . . . . . . 4.19 Impulse response of the 802.11ad FIR DAC. The values from Equation (4.11) . . . . . . 4.20 The change in passband ripple is small as predicted. The transfer function can withstand coefficient mismatches up to 14%, and still fulfill the stopband attenuation with at least 5 dB margin. The percentage yield is plotted against random coefficient mismatch of unary current sources with coefficients realized as a sum of independent unary current sources. 4.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 a) Differentially switched cascode current source, b) Small signal model to find the output-referred noise due to I n1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Small signal model to find the output-referred noise due a) I n2 b) I n3 . . . . . . . . . . . 5.1 The transmit masks of the IEEE 802.11ac and IEEE 802.11ad standards . . . . . . . . . 5.2 160 MHz Baseband Signal at 802.11ac Transmitter Input . . . . . . . . . . . . . . . . . List of Figures xi 5.3 Poposed transmitter architecture for IEEE 802.11ac/ad standards and the DSP part of the 802.11ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Schematic of the multiplierless half-band filter with coefficients of sub-filter F1 shown . 5.5 Schematic of the sub-filter F2 with its 14 long coefficients . . . . . . . . . . . . . . . . . 5.6 The frequency responses of the main interpolation by two half-band filter and its sub-filters 5.7 Signal at the Output of Half-band Filters for 160 MHz Input . . . . . . . . . . . . . . . 5.8 Output of Zero-Order-Hold for 160 MHz Baseband Input . . . . . . . . . . . . . . . . . 5.9 Schematic of a 3 rd -order, 1-bit Delta-Sigma modulator with CRFB topology . . . . . . . 5.10 Noise and signal tranfer functions of the 3 rd -order, 1-bit Delta-Sigma modulator with CRFB topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 The output of the 802.11ad FIR DAC for 6-bit quantized and 16-bit quantized coefficients. The output fulfills the transmit mask requirements with more than 15dB margin. . 5.12 The FIR DAC filter roll-off cancels the rising quantization noise from the ∆Σ-modulator output in the 160MHz mode of the 802.11ac . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Simulated EVM with 16-QAM modulation in the 160MHz mode of the 802.11ac . . . . 5.14 The transfer function of the 160MHz of the 802.11ac mode with a unit coefficient mismatch of 1.7% standard deviation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 The transfer functions and impulse responses of the 20/40/80 MHz, 160 MHz of the 802.11ac and the LP SC 802.11ad mode. The samples in the impulse responses are scaled according to the number of unit coefficient elements required to implement each coefficient. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 FIR DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 A Pseudo double common-centroid placement for UCC fo FIR DAC coefficients. The blue shaded coefficients in the left of the impulse response are placed in the outer sections of each quadrant, and those in green inside. The unmatched center tap is placed in all quadrants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 The placement of the UCCs in II_LEFT and II_RIGHT of the UCC array. Two coefficients, C 31 and C 33 , equidistant from the center tap, C 32 , of the 802.11ac impulse response are highlighted. Two fine-tuning 802.11ad only coefficients, C 68 and C 72 , are also highlighted. They are also equidistant from the center tap, C 70 , of the fine-tuning coefficient set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Systematic error differences between even valued coefficients left and right of the center tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii List of Figures 6.5 FIR DAC floorplan. The current mirrors are local and global-LCM and GCM. The data is propagated from the top starting from 63-flip-flop delay line, to 76-multiplexers mode selection, then to 76 drivers. The clock tree has 64-rows and the output is obtained from differential outputs of a 64-row tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.6 A section of the UCC array. Dummy UCCs surround the edge of the array as shown. The data, clock, output, bias and select signal lines of the UCC are routed such that the array area is exactly the sum of the areas of the UCCs. . . . . . . . . . . . . . . . . . . 95 6.7 FIKRDAC Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.8 A semi-static Flip-Flop for the delay line of the FIR DAC . . . . . . . . . . . . . . . . . 98 6.9 A 2-by-1 multiplexer for mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.10 This shows how the coefficients of 802.11ad are created from 802.11ac. The number at the top indicate taps of the 802.11ad. Each tap is drives the taps 802.11ac taps listed below it and the taps for fine-tuning from 64-76. . . . . . . . . . . . . . . . . . . . . . 100 6.11 The layout of the digital delay line, routing matrix and the mode selection blocks. One of the inputs of the Muxs is directly connected to the flip-flops whereas the other is connected according to the matrix shown above in the table. . . . . . . . . . . . . . . . 100 6.12 The placement of 254 UCCs of coefficient 32 and a depiction of the routing of the data line from driver to the UCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6. 18

 18 The layout view of the clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.19 Transistor level schematic of a Unit Current Cell which works in 802.11ac mode and is controlled by S EL signal to turn-off in 802.11ad . . . . . . . . . . . . . . . . . . . . . . 108 6.20 The layout view of a unit current cell used in both modes. . . . . . . . . . . . . . . . . . 109 List of Figures xiii 6.21 A simple Cascode current mirror and small signal analysis of its output resistance . . . . 6.22 Cascode current mirror biased with two branches . . . . . . . . . . . . . . . . . . . . . 6.23 Sooch cascode current mirror for local and global biasing . . . . . . . . . . . . . . . . . 6.24 A simulation of minimum bias VDD that ensures flat current gain . . . . . . . . . . . . 7.1 Configurable FIR DAC prototype die micrograph. It is fabricated in ST 28nm CMOS FDSOI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Schematic of test board and the test board with the packaged die on board. The high speed input and outputs are connected with SMAs, and power connectors were used for the static signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Instruments used in the measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 7.4 The test bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 The transmitter architecture used to generate 802.11ac data for the chip characterization . 7.6 Transfer functions of the 802.11ac and 802.11ad modes with reference current 2.7µA and load resistance of 50Ω. The passband is expected to be attentuated by around 6.5 dB and 10 dB in the 802.11ac and 802.11ad modes respectively. . . . . . . . . . . . . . . . 7.7 The biasing voltages of the current source of the UCC, and the current gain, I UCC I REF , for different values of the biasing voltage supply. The current gain plat . . . . . . . . . . . . 7.8 Power consumption of the digital circuits, supplied by V DD DIG , of the FIR DAC chip at different clock frequencies in the 802.11ac mode and in the 802.11ad modes. . . . . . . 7.9 Output of the FIR DAC for a ∆Σ input in the 802.11ac mode. It is measured at a clock frequency of 600 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 Output of the FIR DAC for a thrice oversampled ∆Σ input in the 802.11ac mode. It is measured at a clock frequency of 100 MHz. . . . . . . . . . . . . . . . . . . . . . . . . 7.11 Filtered output at 50 MHz and 600 MHz clock of a PRBS input generated from the DTG 7.12 Passband AND Stopband ripple deviations for a PRBS input in the 802.11ac mode . . . 7.13 The signal used as an input for this experiment, b) The measured plot, and c) SFDR in dBc in the bandwidth of the FIR DAC for a clock frequency of 600 MHz. . . . . . . . . 7.14 Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.15 Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16 Time domain measurement for an input sequence at a clock frequency of 10 MHz. . . . . xiv List of Figures 7.17

  Filtered output at 1 GHz and 1.4 GHz clock frequencies of a PRBS input generated from the DTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.18 Output of the FIR DAC for a thrice oversampled ∆Σ input in the 802.11ac mode. It is measured at a clock frequency of 2.4 GHz. The input digital pattern DAT A from the data timing generator is shown in yellow, and the measured output in blue. . . . . . . . . . . 132 7.19 Channel power, ACPR, and alternate CPR measurements across different clock frequencies for a ∆Σ output pattern as an input to the FIR DAC in the 802.11ac mode. . . . . . 133 7.20 Out-of-band profile of the fundamental and image stop bands measured at two points for a ∆Σ output signal as an input. The effect of ZOH clocking on these two stop bands is also shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 List of Tables 3.1 Summary of the reviewed digital transmitters . . . . . . . . . . . . . . . . . . . . . . . 3.2 A summary of RF DACs for cable TV transmitters . . . . . . . . . . . . . . . . . . . . 4.1 Comparison among the three structures of an FIR DAC . . . . . . . . . . . . . . . . . . 4.2 Switch states of delay line for frequency translation of the 1-bit FIR DAC . . . . . . . . 5.1 Summary of the Specifications of the 802.11ac and 802.11ad standards . . . . . . . . . . 5.2 Frequency Planning for IEEE 802.11ac/ad Transmitter . . . . . . . . . . . . . . . . . . 5.3 Summary of the specifications of the multi-standard FIR DAC . . . . . . . . . . . . . . 6.1 Weights of the 802.11ad mode fine-tuning coefficients . . . . . . . . . . . . . . . . . . . 7.1 Power Consumption of the FIR DAC chip in two modes . . . . . . . . . . . . . . . . . 7.2 Comparison with the state of the art in digital-to-RF converters of all-digital transmitters 7.3 Performance summary of the configurable FIR DAC . . . . . . . . . . . . . . . . . . .

-•

  A delay-line of a 1-bit FIR DAC configurable for a LPF/BPF/HPF operations • Thorough small-signal analysis of the noise-limited dynamic range of a differentially-switched cascode current source • A novel pseudo double common centroid placement method for unary-implementation of a FIR DAC as communicated in [GFK16b] Analysis of its bandwidth limitation -A novel floorplan based on this placement method • A yield model for thermometric FIR DACs based on stopband rejection of their filtering transfer function Design of a prototype FIR DAC that is configurable for 160MHz channel bandwidth of the IEEE 802.11ac and IEEE 802.11ad standards proves for the first time a low power, multi-GHz operation of a 63-order 1-bit high pass filtering FIR DAC • The prototype high pass FIR DAC chip is characterized up to a clock frequencies of 3 GHz in the 802.11ac mode, consumes 103.07 mW at 1.4 GHz, and can process passband OFDM signals as wide as 136 MHz. In the 802.11ad case, it can processes SC signals up to a bandwidth of 700 MHz at a clock frequency of 1.4 GHz and consumes 86.89 mW. The work is divided into eight chapters as follows: • Chapter 1: introduces the problem statement the work has tried to solve. It sets the scope of the study, lists the main original contributions, and gives an outline of the dissertation. • Chapter 2: examines the historical background of the application area of this work. It recapitulates the predictions related to the capabilities of future 5G standards, and introduces the principal challenges and solutions. The chapter puts the application of this PhD work in perspective with the predicted possible evolution of radio systems. • Chapter 3: briefly introduces theoretical operation of a modern wireless transmitter. It reviews digital cartesian transmitter architectures. It further delves into review of multi-modal digital transmitters architectures in recently published works. The chapter closes with a proposal of novel FIR DAC based multi-modal transmitter architectures. • Chapter 4: starts with basics of a traditional multi-bit DAC: its operation, specifications, and architectures. Then it follows it with a general discussion of the design challenges of Lbit, Ntap FIR DACs. It introduces a novel configurable delay-line for a 1-bit FIR DAC. A thorough review of published transmitter-side filtering DACs paves the way for analysis of high speed 1-bit FIR DAC design. Main performance metrics of a 1-bit current-steering FIR DAC architecture and its modeling is derived.

Figure 2 . 1 :

 21 Figure 2.1: Evolution of theoretical data rates of wireless technologies from first generation networks to current giga-bit data rate 4G networks

Figure 2

 2 Figure 2.2 [CVM16]. These exponential demands have pushed many governing bodies to plan for the networks of the future. Flagship projects such as METIS 2020 project, 5GNOW, and 5G PPP in Europe, and IMT-2020 under the International Telecommunication Union have led the way for the development and standardization of 5G networks-a generic name for the networks of 2020.

Figure 2 . 2 :

 22 Figure 2.2: Mobile data traffic by 2020 as predicted by Cisco in [CVM16]. Global mobile data traffic is expected to grow eightfold between 2015 and 2020 with a compound annual growth rate of 53%

Figure 2 . 3 :

 23 Figure 2.3: Expected IMT-2020 capabilities as compared with those of IMT-Advanced [ITU15]

Figure 2

 2 Figure 2.4: A 5G device will have to support multiple existing RATs and new ones. The expected capabilities that different parts of the device are shown here[Ban+14b]

  802.11ad was developed from the WiGig MAC and PHY. However, WiGig has now merged with WiFi under the WiFi Alliance and standardized in 802.11ad. Initially released in 1997, WiFi, as standardized by the IEEE 802.11, has hugely impacted the 10 Chapter 2. Wireless Communication Systems medium distance local area and personal communications. The latest flavor, 802.11ac, enables WiFito keep its medium distance capability and reach multi-Gb/s using MIMO. On the other hand, 802.11ad strengthens WiFi in for low power, short distance applications by increasing its capability to multi-Gb/s data rate without the need for MIMO and using simpler modulation schemes. The two standards have made WiFi an indispensable standard, and a candidate for highly dense future networks[START_REF] Verma | Wifi on steroids: 802.11 ac and 802.11 ad[END_REF].

Figure 2 . 5 :

 25 Figure 2.5: Block diagram of a configurable transceiver for WiFi and WiGig applications

Chapter 3 .Figure 3

 33 Figure 3.2: Constellation diagrams of 16-QAM modulation in 802.11ac and 802.11ad standards, and π 2 -QPSK modulation of the LP SC mode of the 802.11ad standard

Figure 3

 3 Figure 3.4: PSD of a 160 MHz, 802.11ac OFDM symbol using a hann window

Figure 3 . 6 :

 36 Figure 3.6: Direct Conversion transmitter

Figure 3 . 8 :

 38 Figure 3.8: General block diagram of a polar transmitter

Figure 3

 3 Figure 3.9: The ACPR is defined based on the spacing of the main, adjacent and alternate channels in this figure. The ACPR and Alternate CPR measurement results of Chapter 7 are also consistent with this definition.

Figure 3 .

 3 Figure 3.10: Block diagram of the digital quadrature mixer based on LPF ∆Σ modulator in [Fra+09]

Figure 3 .

 3 Figure 3.11: Block diagram of the DDRM in [Elo+07]

Chapter 3 .

 3 Multi-standard Digital Transmitters more than 60. The delta-sigma modulator is used to decrease resolution of data input to the RF DACs. Similar techniques are used in [Moh+12].

Figure 3 .

 3 Figure 3.12: Block diagram of the digital-IF direct conversion transmitter in [JS07]

Figure 3 .

 3 Figure 3.13: Block diagram of the digital-IF transmitter with embedded FIR filtering RF DAC in [Tal+08]

[ McM+14 ;

 McM+14 [START_REF] Spiridon | A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 <-58 dBc in 40 nm CMOS[END_REF]; EKR12], although their target applications are cable TV transmitters, they can be used for wireless communication standards. Direct sampling digital-to-RF converters are designed to support wideband input frequencies with the assumption that digital quadrature modulation is carried out at low IF frequencies using standard DSP blocks. Their input is then a complex output of that quadrature modulator. The clock speed of these converters reaches up to 5 GHz[START_REF] Spiridon | A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 <-58 dBc in 40 nm CMOS[END_REF], 4.6 GHz[START_REF] Daniel | A 160 Channel QAM Modulator With 4.6 Gsps 14 Bit DAC[END_REF], 3

Chapter 3 .

 3 Figure 3.14: Block diagram direct conversion transmitter architecture for IEEE 802.11ac based on LPF FIR DAC

Figure 3 .Figure 3

 33 Figure 3.15: Block diagram direct conversion transmitter architecture with upconverted ∆Σ input to a BPF FIR DAC. r is ratio of f IF to f CLK .

Figure 4 . 1 :

 41 Figure 4.1: Time domain operation of a DAC

Figure 4 . 2 :

 42 Figure 4.2: Frequency domain operation of a DAC

Figure 4. 2 .

 2 Figure 4.2.

Figure 4

 4 Figure 4.3: Metrics of the dynamic performance of a DAC

  4.2. TraditionalDAC Topologies 39

Figure 4

 4 Figure 4.5: A Nbit resistor string DAC

Figure 4

 4 Figure 4.7: A segmented current steering DAC

Figure 4

 4 Figure 4.8: A general L-bit, N-tap FIR DAC architecture

Figure 4

 4 Figure 4.9: Impulse response of LPF FIR and its frequency translated HPF version

Figure 4 .

 4 Figure 4.11: Impulse response of LPF FIR and its frequency translated BPF version

Figure 4 .

 4 Figure 4.14: An optimized configurable delay line with only 2(N -1) switches and 2N -1 delay cells.

  that follows a DAC in a classical transmitter architecture is demonstrated in 1.2µm CMOS technology in[START_REF] Su | A CMOS oversampling D/A converter with a current-mode semidigital reconstruction filter[END_REF]. The implementation is shown in Figure4.15. A 128-tap current-mode FIR DAC, clocked at 7.76 MHz, is used to remove shaped quantization noise at the output of a ∆Σ modulator. Such a long filter implementation normally has a big area and systematic mismatch errors are a big concern.

Figure 4

 4 Figure 4.15: Current-mode FIR DAC architecture in [SW93]

Figure 4

 4 Figure 4.16: Current steering FIR DAC architecture in [AR01]

  [START_REF] Fukuda | Direct-digital modulation (DIDIMO) transmitter with-156dBc/hz rx-band noise using FIR structure[END_REF], a 3 + 7 segmented DAC realizes the coefficients of 3-tap FIR filter. Due to the large circuitry at each tap of the filter, the length of the filter is usually short. The coefficients are also equal to avoid mismatch problems. The only flexibility in generating different impulse responses is obtained by controlling the number of delays between the taps. This technique makes the FIR filter in DIDIMO transmitters suitable as a notch-filter to target a specific receive band. The digital signals are directly fed to the filtering structure without major filtering previous stages. Hence, high oversampling ratios are used and high resolution RF-DAC are implemented in each tap of the filer[START_REF] Wagdy | A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter[END_REF].

Figure 4 .

 4 Figure4.17. The outputs of the PDACs were, then, combined to realize three different bandpass filters. Unity coefficient, short length filters may reduce the quantization noise to even fulfill transmit mask

Figure 4 .

 4 Figure 4.18: Current-steering structure for implementing a FIR DAC

(4. 6 )

 6 If each c k has a mismatch generated error k , then the error transfer function can be written as:H e (ω) = N-1 k=0 k+1 e jωk (4.7)The filter magnitude response variation due to error is derived in[START_REF] Petraglia | Effects of coefficient inaccuracy in switchedcapacitor transversal filters[END_REF] with the assumption that k are uncorrelated Gaussian random variables which are identically distributed with zero mean and standard deviation σ :|H e (ω)| = is importantin the characterization of FIR DAC coefficient mismatch errors, it is derived based on the coefficient being implemented as a lumped component. It fails to take into account that coefficients are implemented by replicating a single unit coefficient. A standard deviation which is representative of the errors of all the coefficients should be taken. A slight modification can be applied for the current steering implementation based on unit coefficient. If all the unit coefficients have errors that are uncorrelated Gaussian random variables which are identically distributed with zero mean and a standard deviation of σ u , then a coefficient with a c k unit coefficients has a standard deviation of σ u √ |c k |.

4. 5 .

 5 Figure 4.19: Impulse response of the 802.11ad FIR DAC. The values from Equation (4.11)

  and 4.20b.

Figure 4

 4 Figure 4.20: The change in passband ripple is small as predicted. The transfer function can withstand coefficient mismatches up to 14%, and still fulfill the stopband attenuation with at least 5 dB margin. The percentage yield is plotted against random coefficient mismatch of unary current sources with coefficients realized as a sum of independent unary current sources.

Figure 4 .

 4 Figure 4.22a. The noise sources are mainly drain current thermal noise and 1 f noise of the transistors, and thermal noise of the resistors. [Raz01].

Figure 4

 4 Figure 4.22: a) Differentially switched cascode current source, b) Small signal model to find the outputreferred noise due to I n1

  1 r o2 + g m2 + S C gs2 . Each of the drain noise components, I 2 n,1 ,I 2 n2 , I 2 n3 , contain both thermal noise, I 2 n,d , and flicker noise, I 2 n, 1 f

Figure 4

 4 Figure 4.23: Small signal model to find the output-referred noise due a) I n2 b) I n3

  4.37) N is number of UCCs in the FIR DAC implementation. The gate-source parasitic capacitance are evaluated at the bandwidth of the FIR DAC. It is 880 MHz for the 802.11ad mode, and 160 MHz for the 802.11ac 160 MHz modes.

PBW g m1 r o2 g m3 2 +4g

 2 sig = 0.5NI 2 UCC (4.42) 4.5. High Speed 1-bit, N-tap FIR DAC Design 63 m2 +g m3 +K I UCC 5+ r o2 g m3

(4. 45 ) 2 UCC8kT

 452 Then the dynamic range formula can be simplified to an expression containing technological constants and the variables N, unit current, I UCC , and bandwidth, BW. DR ≈ NI BWg m1 K CS _R +K K CS _R I UCC ln BW (4.46)

Chapter 4 .

 4 Configurable Finite Impulse Response Digital-to-Analog ConverterThe dynamic range formula in Equation (4.48) is used to find the optimum current value in the design of the UCC in Chapter 6. Since the BW and the number of UCCs, N, are different for in the two modes of operation the FIR DAC is designed, the unit current values for the same DR in each mode are separately estimated. A maximum value of the two I UCC which guarantees the required dynamic range for the two modes is taken.

Chapter 5 .

 5 Proposed IEEE 802.11ac/ad Transmitter Baseband Architecture data rates up to 780 Mb/s. It is also backward compatible with the older WiFi standard such as the 802.11n. The standard support four contiguous channel bandwidths-20 MHz, 40 MHz, 80 MHz, and 160 MHz-and additional non-contiguous 80+80 MHz channel bandwidth [Int+14]. The 80 MHz, 160 MHz and 80+80 MHz channel bandwidths are new additions compared to the 802.11n 2.4 GHz standard. However, only 20 MHz, 40 MHz and 80 MHz are mandatory, the 80+80 MHz and 160 MHz are stipulated under those the VHT STA can optionally support. The 802.11ac VHT PHY is only defined for OFDM with total number of subcarriers 56, 114, 242, 242, and 484 for the channel widths 20 MHz, 40 MHz, 80 MHz, 80+80 MHz and 160 MHz respectively. The supported modulation methods are BPSK, QPSK, 16-QAM, 64-QAM, and an optional 256-QAM.

FsFigure 5 . 1 :

 51 Figure 5.1: The transmit masks of the IEEE 802.11ac and IEEE 802.11ad standards

Figure 5

 5 Figure 5.2: 160 MHz Baseband Signal at 802.11ac Transmitter Input

Figure 5 . 3 :

 53 Figure 5.3: Poposed transmitter architecture for IEEE 802.11ac/ad standards and the DSP part of the 802.11ac

Figure 5 . 4 :F1

 54 Figure 5.4: Schematic of the multiplierless half-band filter with coefficients of sub-filter F1 shown F1 Sub-filter

Figure 5 . 5 :

 55 Figure 5.5: Schematic of the sub-filter F2 with its 14 long coefficients

Chapter 5 .

 5 Figure 5.6: The frequency responses of the main interpolation by two half-band filter and its sub-filters

Figure 5 . 7 :Figure 5 . 9 :

 5759 Figure 5.7: Signal at the Output of Half-band Filters for 160 MHz Input

Figure 5 .

 5 Figure 5.11: The output of the 802.11ad FIR DAC for 6-bit quantized and 16-bit quantized coefficients.

  11ac. It operates with the OSR values shown in Table 5.2. The purpose of the FIR DAC transfer function is to cancel the high pass noise shape coming from the delta-sigma modulator. A single filter transfer function can be used for 20 MHz, 40 MHz, and 80 MHz modes and still fulfill the transmit mask requirements of each of the three modes.

Figure 5 .

 5 Figure 5.12: The FIR DAC filter roll-off cancels the rising quantization noise from the ∆Σ-modulator output in the 160MHz mode of the 802.11ac

  63 in both the 160 MHz and the combined 20 MHz, 40 MHz and 80 MHz modes. Since the filters has symmetrical impulse response, they have linear phase responses. The response of the FIR DAC and the delta-sigma modulator in the 160 MHz mode of the 802.11ac are shown in Figure 5.12. It can be seen that the rising quantization noise at the output of the modulator is canceled by the decaying stopband of the FIR DAC response to less than the requirements of the transmit mask. The margin between the stopband and the transmit mask is large because the stopband rejection value is designed considering standard coexistence.

Figure 5 .

 5 Figure 5.13: Simulated EVM with 16-QAM modulation in the 160MHz mode of the 802.11ac

5. 3 .

 3 Figure 5.14: The transfer function of the 160MHz of the 802.11ac mode with a unit coefficient mismatch of 1.7% standard deviation.

Figure 5

 5 Figure 5.15: The transfer functions and impulse responses of the 20/40/80 MHz, 160 MHz of the 802.11ac and the LP SC 802.11ad mode. The samples in the impulse responses are scaled according to the number of unit coefficient elements required to implement each coefficient.

Figure 6

 6 Figure 6.1: FIR DAC block diagram

Figure 6

 6 Figure 6.2: A Pseudo double common-centroid placement for UCC fo FIR DAC coefficients. The blue shaded coefficients in the left of the impulse response are placed in the outer sections of each quadrant, and those in green inside. The unmatched center tap is placed in all quadrants.

  one UCC are routed short distance. The only analog signals which will be routed long distance are the output signals of the FIR DAC. Digital signals from the drivers to the UCC are routed vertically or horizontally, but long distance. Now instead of long distance routing of current source analog signals, it is digital signals that drive the switches which will be routed long distance.

Figure 6 . 3 :

 63 Figure 6.3: The placement of the UCCs in II_LEFT and II_RIGHT of the UCC array. Two coefficients, C 31 and C 33 , equidistant from the center tap, C 32 , of the 802.11ac impulse response are highlighted. Two fine-tuning 802.11ad only coefficients, C 68 and C 72 , are also highlighted. They are also equidistant from the center tap, C , of the fine-tuning coefficient set.

Figure 6

 6 Figure 6.4: Systematic error differences between even valued coefficients left and right of the center tap

Figure 6

 6 Figure 6.5: FIR DAC floorplan. The current mirrors are local and global-LCM and GCM. The data is propagated from the top starting from 63-flip-flop delay line, to 76-multiplexers mode selection, then to 76 drivers. The clock tree has 64-rows and the output is obtained from differential outputs of a 64-row tree.

  Figure 6.6: A section of the UCC array. Dummy UCCs surround the edge of the array as shown. The data, clock, output, bias and select signal lines of the UCC are routed such that the array area is exactly the sum of the areas of the UCCs.

Figure 6 Figure 6

 66 Figure 6.7: FIKRDAC Layout

76 ValuesFigure 6

 766 Figure 6.10: This shows how the coefficients of 802.11ad are created from 802.11ac. The number at the top indicate taps of the 802.11ad. Each tap is drives the taps 802.11ac taps listed below it and the taps for fine-tuning from 64-76.

Figure 6

 6 Figure 6.12: The placement of 254 UCCs of coefficient 32 and a depiction of the routing of the data line from driver to the UCCs

Chapter 6 .CENTERFigure 6

 66 Figure 6.13: Model of equivalent impedance of routed data lines for coefficient 32 with 254 UCCs

  the pseudo double common-centroid UCC array placement. It is observed that the RC interconnect associated with the biggest coefficient results in higher time constants. The biggest coefficients are placed in the perimeter of the sections of the quadrants. A driver for a coefficient whose value is almost equal to the biggest coefficient, the center tap in a symmetrical FIR DAC impulse response, requires four data line routing. Two lines in the left and right side of a section of a quadrant, and two in the other. A 104 Chapter 6. Design and Implementation of A Configurable Transmitter Baseband in CMOS 28nm FDSOI fifth for the center if it has a remainder after division by four.

Figure 6

 6 Figure 6.15: The layout view of the a five-stage driver used for the biggest coefficients in the center of the 802.11ac impulse response. Additional stage inserted not to invert the data. Supply connected using parallel thin wires to ensure low current density.

108Chapter 6 .Figure 6

 66 Figure 6.19: Transistor level schematic of a Unit Current Cell which works in 802.11ac mode and is controlled by S EL signal to turn-off in 802.11ad

6. 3 .

 3 Design and Layout of Each Block 109 supply. It is also possible to lower the swing of the control signals. This method negatively affects the maximum speed at which the UCC can operate [CG07]. A method preferred here is to add two dummy switches with floating sources and are driven opposite to the switches with the same complementary control signals. If they are sized the same as the switches, the problem of charge feedthrough is reduced [LCD00].

Figure 6 .

 6 Figure 6.20: The layout view of a unit current cell used in both modes.

  r out = (g mCS + g mCAS )r oCAS + 1)r oCS + r oCAS (6.20) r in ≈ r o1 (6.21) However, it has a high minimum output voltage which eats away on the possible load voltage swing of the UCC. An alternative is to use two simple current mirroring biases as shown in Figure 6.22. It solves the problem of high minimum output voltage by lowering it to 2V OV and still maintains high

Figure 6

 6 Figure 6.21: A simple Cascode current mirror and small signal analysis of its output resistance

Figure 6 .

 6 Figure 6.22: Cascode current mirror biased with two branches

Figure 6 .

 6 Figure 6.23: Sooch cascode current mirror for local and global biasing

  Figure 6.24: A simulation of minimum bias VDD that ensures flat current gain

Chapter 7 Measurement

 7 Results of FIR DAC PrototypeA configurable high pass FIR DAC was fabricated in ST 28nm FDSOI with a 10 metal layer CMOS process. The chip is fully custom designed, and occupies an active area of 0.84mm 2 . The chip micrograph is shown in Figure7.1. Due to metal filling, the circuit blocks are not visible. It has a 4x10 PAD ring.

Figure 7 . 1 :

 71 Figure 7.1: Configurable FIR DAC prototype die micrograph. It is fabricated in ST 28nm CMOS FDSOI.

  Figure 7.1 has eleven distinct PADs. The rest of the PADs are used for V DD DIG and GND to lower IR drop. Two of the inputs: DAT A and CLOCK are high speed digital; one is static DC input: S EL; four are current reference and voltage supplies: I REF ,V DD DIG , V DD BIAS ,GND, and V DD ANA ; two are analog high speed outputs: VOUT POS , and VOUT NEG ; and two are DC outputs: VOUT CAS , and VOUT CS .

Figure 7

 7 Figure 7.2: Schematic of test board and the test board with the packaged die on board. The high speed input and outputs are connected with SMAs, and power connectors were used for the static signals.

Figure 7 Figure 7

 77 Figure 7.3: Instruments used in the measurement Setup

Figure 7

 7 Figure 7.7: The biasing voltages of the current source of the UCC, and the current gain, I UCC I REF , for different values of the biasing voltage supply. The current gain plat

Figure 7 . 8 :

 78 Figure 7.8: Power consumption of the digital circuits, supplied by V DD DIG , of the FIR DAC chip at different clock frequencies in the 802.11ac mode and in the 802.11ad modes.

  this sub-section, sub-GHz clock frequencies were used to test the FIR DAC. The tests with clock frequency beyond 650 MHz are included in the last part. The data driver circuits of the FIR DAC were not operating at the GHz speeds for a digital supply voltage of 1 V. This was ascertained by observing the time domain output signals at near 1 GHz clock frequencies where some of the outputs values was achieving expected swing albeit at lower update rate during a test with known input sequences. The simulation results showed functionality up to 3.52 GHz with a PRBS DAT A at a digital supply voltage of 1 V. The possible source of this problem is increased capacitive loading on the outputs of the DAT A DRIV ERS than what was expected during chip simulation. This could have resulted from less accurate models. Moreover, the transistor flavor used for the implementation of the digital circuits might not have the expected high frequency functionality. This problem was remedied by increasing the digital supply voltage up to 1.325 V depending the clock frequency.Performance of the DAC for a Wideband Modulated DAT AIn this mode, the bandwidth of the filter is set to f CLK 22 . The output of the FIR DAC for a QPSK modulated OFDM 802.11ac signal at a clock frequency of 600 MHz is shown in Figure7.9. The signal is generated with a frequency plan of 3.52 GHz at the FIR DAC using Matlab R . Thus, the bandwidth of the actual measured signals is approximately 27.3 MHz.As explained in Chapter 5, the raising quantization noise is canceled by the roll-off in the filter transition band. The quantization noise is reduced by almost 40 dB for the 600 MHz clock frequency.

Figure 7

 7 Figure 7.9: Output of the FIR DAC for a ∆Σ input in the 802.11ac mode. It is measured at a clock frequency of 600 MHz.

Figure 7 .

 7 Figure 7.10: Output of the FIR DAC for a thrice oversampled ∆Σ input in the 802.11ac mode. It is measured at a clock frequency of 100 MHz.

Figure 7 Figure 7

 77 Figure 7.11: Filtered output at 50 MHz and 600 MHz clock of a PRBS input generated from the DTG

A

  measurement is conducted to show the filtering characteristics in this mode. The measurement result in Figure 7.14 was carried out at 200 MHz clock frequency and the same speed PRBS input data from the data timing generator.

Figure 7 .

 7 Figure 7.14: Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG

Figure 7 .

 7 Figure 7.15: Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG

Figure 7 .

 7 Figure 7.16: Time domain measurement for an input sequence at a clock frequency of 10 MHz.

  Figure 7.16. The simulated resulted, from Matlab, is shown in red. The measured result is shown in the second plot. The oscilloscope samples this input at 10 GHz. The superimposed plot at the top is obtained by downsampling the measured data points fro 10 GHz to the clock frequency of 10 MHz. As can be seen, the measured data trace almost exactly as the simulated one; they have equal peak-to-peak voltages, and also their periods are the same. This shows that the static part of the FIR DAC is working as expected at least at 10 MHz clock frequency.

Figure 7

 7 Figure 7.17: Filtered output at 1 GHz and 1.4 GHz clock frequencies of a PRBS input generated from the DTG

Figure 7 .

 7 Figure 7.18: Output of the FIR DAC for a thrice oversampled ∆Σ input in the 802.11ac mode. It is measured at a clock frequency of 2.4 GHz. The input digital pattern DAT A from the data timing generator is shown in yellow, and the measured output in blue.

Figure 7 .

 7 Figure 7.19: Channel power, ACPR, and alternate CPR measurements across different clock frequencies for a ∆Σ output pattern as an input to the FIR DAC in the 802.11ac mode.

Figure 7 .

 7 Figure 7.20: Out-of-band profile of the fundamental and image stop bands measured at two points for a ∆Σ output signal as an input. The effect of ZOH clocking on these two stop bands is also shown.

F

  u n c D e l S i g . Fs = Fs * OSR ; F u n c D e l S i g . Name= ' D e l t a S i g m a ' ; F u n c D e l S i g . O r d e r = O r d e r ; F u n c D e l S i g . t o p o SigShapedR = [ SigShapedR , z e r o s ( 1 , GrpDelay_DS ) ] ; [ S i g D e l S i g O u t R ] = D e l t a S i g m a 3 r d O r d e r ( SigShapedR , F u n c D e l S i g ) ; S i g D e l S i g O u t R = S i g D e l S i g O u t R ( GrpDelay_DS +1: end ) ; P l o t F r e q u e n c y R e s p o n s e ( S i g D e l S i g O u t R , 3 . 5 2 e9 ) ; %% S e m i d i g i t a l FIR DAC SigAnalogOutR = f i l t e r ( C o e f f , 1 , [ S i g D e l S i g O u t R , z e r o s ( 1 , FIRDLY ) ] ) ; SigAnalogOutR = SigAnalogOutR ( FIRDLY+1: end ) ; %% F o r Q-p a r t % i f i s e m p t y ( S i g T y p e ) % [ SigShapedQ , ~] = OverSample ( S i g I n I m a g , OSR ) ; % Zero -Order -Hold %% ZOH p h a s e c o m p e n s a t i o n ZOH = [ 1 , 1 , 1 , . . . OSR t i m e s , 1 ] ; g r p d e l a y = ( o s r -1 ) / 2 ; SigInImagUP = u p s a m p l e ( SigInImagHFNBit , OSR ) ; % SigInImagUP = u p s a m p l e ( SigInImagHF , OSR ) ; SigShapedQ = f i l t e r (ZOH, 1 , [ SigInImagUP , z e r o s ( 1 , c e i l ( ( OSR -1 ) / 2 ) ) ] ) ; % Zero -Order -Hold d e l a y c o m p e n s a t i o n SigShapedQ = SigShapedQ ( c e i l ( ( OSR-1 ) / 2 ) + 1 : end ) ; %% D e l t a Sigma M o d u l a t o r w i t h D e l a y C o m p e n s a t i o n SigShapedQ = [ SigShapedQ , z e r o s ( 1 , GrpDelay_DS ) ] ; [ S i g D e l S i g O u t Q ] = D e l t a S i g m a 3 r d O r d e r ( SigShapedQ , F u n c D e l S i g ) ; S i g D e l S i g O u t Q = S i g D e l S i g O u t Q ( GrpDelay_DS +1: end ) ; P l o t F r e q u e n c y R e s p o n s e ( SigDelSigOutQ , 3 . 5 2 e9 ) ; %% SigAnalogOutQ = f i l t e r ( C o e f f , 1 , [ SigDelSigOutQ , z e r o s ( 1 , FIRDLY ) ] ) ; SigAnalogOutQ = SigAnalogOutQ ( FIRDLY+1: end ) ; %% S c a l e Back t o O r i g i n a l M a g n i t u d e s S i g A n a l o g O u t . R = ( SigAnalogOutR . / AmpFS ) . * max ( a b s ( S i g T y p e ) ) ; S i g A n a l o g O u t . Q = ( SigAnalogOutQ . / AmpFS ) . * max ( a b s ( S i g T y p e ) ) ; % S i g A n a l o g O u t . R = SigAnalogOutR ; % S i g A n a l o g O u t . Q = SigAnalogOutQ ; %% ACPR s i m u l a t i o n [ACPR . Q I n t e r , ~, ~] = ACPRTest ( SigShapedQ , ACPRPara ) ; [ACPR . QDelSig , ~, ~] = ACPRTest ( SigDelSigOutQ , ACPRPara ) ; [ACPR . QSemi , ~, ~] = ACPRTest ( S i g A n a l o g O u t . Q, ACPRPara ) ; %% SPECTRAL FLATNESS [ S p e c F l a t . Q] = S p e c t r a l F l a t n e s s T x W i F i ( SigAnalogOutQ , F s _ O r i g i n a l , OSR ) ; % e l s e %% ACPR S i m u l a t i o n I n p u t D a t a [ACPR . R I n t e r , MainChPowerR , AdjChPowerR ] = ACPRTest ( SigShapedR , ACPRPara ) ; %# ok [ACPR . RDelSig , MainChPowerR , AdjChPowerR ] = ACPRTest ( S i g D e l S i g O u t R , ACPRPara ) ; %# ok [ACPR . RSemi , MainChPowerR , AdjChPowerR ] = ACPRTest ( S i g A n a l o g O u t . R , ACPRPara ) ; %# ok i ) = SigMapped ( 1 : 2 8 , i ) ; %% p o s i t i o n o f p i l o t and d a t a s u b c a r r i e r s i s n o t 41 SigZP ( 3 5 : 6 2 , i ) = SigMapped ( 2 9 : 5 6 , i ) ; 42 e l s e i f eq ( SEL , 2 ) 43 SigZP ( 4 : 6 0 , i ) = SigMapped ( 1 : 5 7 , i ) ; %% p o s i t i o n o f p i l o t and d a t a s u b c a r r i e r s 44 SigZP ( 6 9 : 1 2 5 , i ) = SigMapped ( 5 8 : 1 1 4 , i ) ; % Downsample SigDn = downsample ( S i g R f ( : , i ) , OSR ) ; % OSR f o r Fs mode SigOFDMRx ( : , i ) = SigDn ; %% GI Removal SigGIRx ( : , i ) = SigOFDMRx ( Ncp +1: Nsc+Ncp , i ) ; %% FFT SigFFT ( : , i ) = 1 / Nsc . * f f t ( SigGIRx ( : , i ) , Nsc ) ; %% Removal o f z e r op a d d i n g

  Current networks are not expected to support the data demand of the future. This is because of the explosive rise in user data demand coupled with the increasing number of new applications that require low latency, high data rate communications. The 2015 virtual networking index report by Cisco shows that 4G mobile networks account for 47% of mobile data traffic with just 14% of mobile connections increase in mobile devices does not imply similar proportion of growth in other networks, it does show the exponential demand for faster data. The mobile data traffic growth from 2015 to 2020 is shown in

while 3G networks contribute for 43% traffic with 34% of connections. In general, a 4G traffic takes the biggest share with 85% more traffic than a non-4G connection. It also reports an increase of more than half a billion in global mobile devices and connections in 2015. Although the growth in mobile data and 2.2. Networks of the future 7

Table 3

 3

	[Spi+13]	5 Gs/s	9-bit	375 mW	2.2 GHz	40nm CMOS
	[McM+14]	4.6 Gs/s	14-bit	2.3 W	1 GHz	0.18µm CMOS
	[EKR12]

.2: A summary of RF DACs for cable TV transmitters References Sampling rate Resolution Power Effective Bandwidth Technology

s 3T s 4T s 5T s 6T s 7T s 8T s T s 2T s 3T s 4T s 5T s 6T s 7T s 8T s Discrete Output NRZ RZ Discrete Output Digital Input

  Chapter 4. Configurable Finite Impulse Response Digital-to-Analog Converter

	00 000
	00 001
	00 010
	00 011 00 101 00 011	D	A
	00 010
	00 100
	00 001
	N bits		T s 2T

Table 4 .

 4 1: Comparison among the three structures of an FIR DAC ‡ N-tap 1-bit, N-tap § L-bit, 1-tap ¶

			FIR DAC
	Parameters L-bit, Mismatch Linearity --	++	-
	Speed	--	-	++
	Image Rejection	++	++	-
	Coefficient Spread	--	++	++
	Number of Unit Coefficients	--	-	++
	spread as a multi-bit DAC, but the number of unit coefficients usually increase as N increases. Image

rejection is better in the first two structures due to the flexibility to implement a filter responses sharper than a SINC function.

Table 4 .

 4 2: Switch states of delay line for frequency translation of the 1-bit FIR DAC Frequency Response Switch, S 1 Switch, S 2 Switch, S 3

	LPF FIR DAC	0	1	0
	HPF FIR DAC	X	X	1
	BPF FIR DAC	X	0	0

Table 5 .

 5 1: Summary of the Specifications of the 802.11ac and 802.11ad standardsThe system level simulation was carried out for the different channel bandwidths and transmission modes of the 802.11ac and 802.11ad. While it is less challenging to demonstrate the system for the channel bandwidths of 20 MHz and 40 MHz in the 802.11ac case, the potential of the proposed system to integrate with new applications that take advantage of the full potential of the 802.11ac standard would be demonstrated better if the system is validated for the new channel bandwidth flavors of 80 MHz and

	Parameter		802.11ac		802.11ad
	Bandwidth (MHz)	20	40	80	160	1760
	Input Resolution	9-bit 10-bit 11-bit 12-bit	1-bit
		@ 16-QAM ( channelized )	@ π / 2 -QPSK
	Mask ( @ offset in MHz )		-40dBr @		-30dBr @
		30	60	120	240	3060

Table 5

 5

	.2: Frequency Planning for IEEE 802.11ac/ad Transmitter
	Standard	IEEE 802.11ac	IEEE 802.11ad
	Channel Bandwidth (MHz) 20 40 80 160	1760
	Half-band filter OSR	16 8	4	2	upsample by 2
	New Sample Rates (MHz)	320		3520
	Common ZOH OSR	11			N/A
	Multi-standard rate			3.52 GHz

Table 5 .

 5 3: Summary of the specifications of the multi-standard FIR DAC

	Parameter	802.11ac mode 802.11ad mode
	Clock Speed	f s	f s
	Bandwidth	f s 22	f s 2
	Unit Coefficient Mismatch, σ u	1.7%	1.7%
	Coefficient Spread	2 8	2 6
	Load Resistance §	R load	R load
	Full-Scale Swing ‡	4974I unit R load	3804I unit R load
	Number of UCC Only in	1246	76
	Number of UCC Shared	98% of 802.11ad used in 802.11ac
	to make them equal to the actual 802.11ad values.

  R 3 , and R 4 are resistive approximation ofZ eq0 + Z eq1 + Z eq2 , Z eq0 + Z eq1 + Z eq2 + Z eq4 , Z eq0 + Z eq1 + Z eq2 + Z eq4 + Z eq8, and Z eq0 + Z eq1 + Z eq2 + 2Z eq4 + Z eq8 . R total_line can be approximated as a sum of: Z eq0 + 2Z eq1 + Z eq2 + 2Z eq4 + Z eq8 because the RC segment between two UCCs of the same group is neglected. This leads to

Table 7 .

 7 1: Power Consumption of the FIR DAC chip in two modes

	Part	Mode	Current Voltage Power Consumption
		802.11ac 19.4 mA	1 V	19.4 mW
	Digital Circuits at 600 MHz
		802.11ad 16.4 mA	1 V	16.4 mW
		802.11ac	65 mA	1.325 V	86.13 mW
	Digital Circuits at 1.4 GHz
		802.11ad	56 mA	1.32 V	73.92 mW
		802.11ac 14.07 mA 1.2 V *	16.88 mW
	Analog Circuits
		802.11ad 10.76 mA	1.2 V	12.91 mW
		802.11ac 51.3 µA †	1.2 V	61.56 µW
	Biasing Circuits	802.11ad 51.3 µA	1.2 V	61.56 µW
		802.11ac		36.34 mW
	Total Power Consumption at 600 MHz
		802.11ad		29.37 mW
		802.11ac		103.07 mW
	Total Power Consumption at 1.4 GHz
		802.11ad		86.89 mW

Table 7 .

 7 2. Table 7.2: Comparison with the state of the art in digital-to-RF converters of all-digital transmitters

			Type		Max.	Max.	Max.	Max.
	REF.	Tech.	of	Mode	BW	f s	f out	P out	P Cons	‡
			DAC		[ MHz ] [ MHz ] [ MHz ] [ dBm ] [ mW ]
		65nm	RF	-
	[Ala+14]				154.1	3500	2400	22.8	-
		CMOS	DAC
		0.25µm	FIR	-
	[Tal+08]				15	250	1062	-5.4	122
		CMOS	RF DAC
		130nm SiGe TI ∆Σ RF	BP			510	-4.5
	[McC+15]				50	2000			55
		CMOS	DAC	HP			990	-7.5
	This	28nm CMOS HP FIR	11ac	136	3000	1500	3.93	103.07 §
	Work	FDSOI	DAC	11ad	700	1400	700	1.61	86.89 §

Table 7 .

 7 3: Performance summary of the configurable FIR DAC summary of the measurement results of the FIR DAC chip is presented in Table7.3. The maximum input bandwidth for 802.11ac mode is at a clock frequency of 1.4 GHz for a PRBS input shown in Figure7.17b. It would have strengthened the claim to present EVM results, but it has not been possible to carry out these measurements so far. For the 802.11ad, the maximum input bandwidth is at 600 MHz clock frequency. Nonetheless, the circuit can operate in the 802.11ac mode up to clock speeds of 2.4 GHz starting at a 1.325 V digital supply voltage. Further tests at higher supply voltages were not carried out at the moment. The chip has also functionality up to 1.4 GHz in the 802.11ad starting at a digital supply voltage of 1.325 V.In the 802.11ac mode, results are obtained at digital supply voltage as low as 0.6 V. As expected, 136 Chapter 7. Measurement Results of FIR DAC Prototype this happens when the data and clock signal levels are scaled to the corresponding V DD DIG level and at frequencies below 100 MHz. Further tests with varying digital supply voltage were not possible at this moment.

	Parameter	802.11ac mode	802.11ad mode
	Bandwidth	f s 22	f s 2
	Maximum Output Carrier Frequency	1500 MHz	700 MHz
	Maximum Measured Input BW	136 MHz	700 MHz
	Full-Scale Output Current, I REF = 2.7µA	14.07 mA	10.76 mA
	Power Consumption at 1.4 GHz	103.07 mW	86.89 mW
	Total Number of UCCs	4974	3804
	Clock Speeds, f s	10MHz f s 3GHz 10MHz f s 1.4GHz
	Supply Voltages	V DD DIG V DD BIAS V DD ANA
		0.6 to 1.55 V	1.2 V	1.2 V
	Hardware Sharing	98% 802.11ad UCCs used in 802.11ac
	Maximum Stopband Rejection	55 dB in 802.11ac mode
	Output Load Network	50 Ω differential probes
	Clock and Data Input	Single-ended, 50 Ω to ground
	Die Packaging	QFN40 plastic package
	Active Circuit Area		0.83 mm 2
	Transistors Used	Regular V th
	Technology	28nm CMOS FDSOI
	7.3 Conclusions

A

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 2.3. The WiFi-WiGig Complementarity

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 2.4. Summary and conclusions

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 3.1. Brief Theory of Transmitter Operation

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 3.2. Review of Digital Transmitter Architectures

† L-fold Interpolation ‡ Not Used § Not Implemented, but can be embedded in PDAC Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 3.3. Multi-standard Digital Transmitters

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 4.1. Operation of a DAC

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 4.3. Finite Impulse Response DAC

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 4.4. FIR DAC Architectures in Literature

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 5.2. System Level Simulation of Proposed Transmitter Architecture

(a) (b)

Thèse de Fikre Tsigabu Gebreyohannes, Université de Lille, 2016 © 2016 Tous droits réservés. lilliad.univ-lille.fr 6.2. Mismatch Errors and Layout Floorplan

e l s e i f eq ( SEL , 3 )

Chapter 7. Measurement Results of FIR DAC Prototype

The transmitter function implements half-band filter and resampler blocks for oversampling. Then the data is converted to 1-bit using a low pass delta-sigma modulator. A complex mixer is used for frequency translating the data to f s 2 . The 1-bit input sequence is loaded on the data timing generator as an input to the FIR DAC chip. The complex baseband data of a IEEE 802.11ad is not windowed. Only oversampling by a factor of two is needed before the data is frequency translated to f s 2 . To simplify the test of this mode of the FIR DAC, non-oversampled PRBS data at the same rate as the clock was used.

Measured Results

The expected transfer functions for the two modes are recalled in Figure 7.6. The coefficient values of the two transfer functions are adjusted to the reference current and load resistors used in the measurement. measurement of the output, the resolution bandwidth is scaled proportional to the update rate of the FIR DAC to exclude any reading differences. The change in the stopband ripple was caused by slow decrease in the power of the passband when the clock frequency of the FIR DAC increases. The actual stopband power stays constant, only the rejection changed. This can be expected as the static parameters, those that cause change in coefficient values, are constant. The result in Figure 7.12 is then an indication of the failure of the output node of the current sources of the FIR DAC to charge and discharge fast enough to achieve the maximum output swing at each cycle of the clock.

Characterization of Dynamic Performance

It is customary to use single tones sinusoidal waves for DAC dynamic performance measurement. The signals can be filtered to a degree where the noise floor of the input sinusoid is not higher than the noise floor of the spectrum analyzer. While it is fairly straightforward to do that when the input is multi-bit, it becomes harder to generate 1-bit test signals. This is because a ∆Σ modulator has to be used for converting the multi-bit low noise single-tone signal to a stream of 1-bit input data. The SNR of the 1-bit data depends on the SNR of the modulator used. For our case, only a 3 rd -order modulator was used, i.e.

Appendix .1 Transmitter Chain Simulation in Matlab

The matlab code given here is used for simulation of the transmitter chain in Chapter five. The function is also used improved for generating the patterns used in the test of the prototype FIR DAC chip in Chapter seven.

There may be some codes here and there that are mistakenly commented or some values which were chosen for some particular frequency plan, but generally the code can be easily improved to be used for a DSP of transmitter chain simulation.

Unfortunately, the other codes that has been written for each block of the transmitter are not included here. Hopefully, they will available somewhere sometime. % G e n e r a t e a S i g n a l w i t h t h e i n p u t c h a r a c t e r i s t i c s % S i g I n = T e s t S i g n a l s ( SigType , 5 0 , 1 , F s i g , Fs ) ; % F s i g = [ ] ; % was u s e f u l when g e n e r a t i n g i n p u t s i g n a l w i t h i n t h i s f u n c t i o n f o r s i n g l et o n e % what i f t h e q u a n t i z e r f u l l s c a l e were 2 , 0 , -2? S i g I n R e a l = ( r e a l ( S i g T y p e ) . * AmpFS ) . / max ( a b s ( S i g T y p e ) ) ;