Keywords: Défaillance opérationnelle, tolérant à la panne, redondance, contrôle distribué, reconfiguration, continuité de mission, entrelacement, modulaire, extensible, chaine circulaire Fail-operational, fault-tolerant, distributed control, reconfiguration, mission continuity, interleaving, modular, scalable, circular-chain

correcteur pour l'optimisation de la réponse transitoire est proposée. Les singularités de chaque approche sont discutées et des simulations sont fournies à des fins de vérification.

Le Chapitre IV présente l'élaboration d'une nouvelle approche originale de contrôle distribué pour l'entrelacement des signaux de commande, ainsi que son analyse. Il s'agit d'une approche à signaux mixtes, composée de quelques éléments de logique numérique et d'un noyau analogique. L'étude théorique et l'évaluation de cette nouvelle technique d'entrelacement sont présentées, ainsi que des résultats de simulation. Une preuve de concept a été élaborée en utilisant des composants CMS associées sur une carte de circuit imprimé. La réponse dynamique est vérifiée expérimentalement pour les perturbations modales, cas de démarrage et de reconfiguration. Le comportement lors d'un événement de panne de communication est également observé, comprenant le cas d'un court-circuit de ligne à la masse et de court-circuit de ligne à ligne.

Les systèmes d'aide à la conduite automobile sont en mesure de prendre le contrôle du véhicule en cas de danger. La redondance et la capacité de reconfiguration en cas de panne des ordinateurs embarqués sont fondamentales pour assurer la continuité de la mission.

L'alimentation des coeurs des processeurs se fait généralement à l'aide de convertisseurs multiphases qui offrent naturellement plusieurs chemins de courant (redondants) vers le processeur en raison de leur topologie parallèle. Cependant, l'organe de contrôle du convertisseur représente une faiblesse en termes de disponibilité car implanté majoritairement de manière centralisé. NXP Semiconductors a initié un partenariat avec le laboratoire LAPLACE afin de financer cette thèse pour l'étude d'un mode de contrôle distribué tolérant à la panne. Cette thèse se focalise sur l'utilisation d'une méthode de contrôle distribué, ne présentant aucun point de panne singulier, pour développer un organe de gestion de l'entrelacement des signaux de commande, modulaire et redondant, ainsi que pour maitriser son fonctionnement, en termes de temps de réponse et de stabilité.

Le Chapitre I présente le contexte et l'état de l'art. Le contexte concerne la stratégie de sûreté de fonctionnement intégré utilisée par NXP ; une étude des exigences et des technologies récentes est présentée pour comprendre les enjeux de la conception des alimentations des processeurs modernes ; la tendance de l'augmentation de la charge de calcul requise et de la consommation électrique résultante est mise en évidence ; et l'adoption de convertisseurs multiphases est justifiée. Un état de l'art couvre alors principalement les techniques de contrôle distribué modulaire appliquées à la régulation de la tension de la charge et à l'équilibrage des courants des phases, puis aux techniques d'entrelacement, nécessaires au fonctionnement des convertisseurs multiphases.

Les Chapitres II et III présentent l'étude théorique et l'évaluation respectivement de deux techniques d'entrelacement par approche distribuée préexistantes La même approche de modélisation est appliquée dans chaque chapitre pour obtenir un modèle à multiples entrées et multiples sorties conforme aux spécificités de chaque approche, dans le but d'identifier enfin les conditions de stabilité à respecter. Les particularités liées à la modélisation et à la mise en oeuvre des simulations de validation sont décrites. Par la suite, une technique de choix de

List of figure

List of tables

Table I-

List of acronyms

General introduction

The mobility sector passes nowadays through a revolution. Electrical assistance is widely available in bikes and scooters. Fully autonomous vehicles are already available in the market. These vehicles can be individual or fit small groups of people, such as cars we know today. Recently general public flying taxis are being tested. These vehicles are composed of multiple electronic devices and computers. High availability and safety concerns have to be handled to avoid injures and damage. To overcome these challenges, safety strategies are evolving from the level "fail silent" (device disabled) to "fail operational" (fault corrected onthe-fly), when the device reconfigures to guarantee mission continuity in case of a failure. Chapter II and III present the theoretical studies and evaluations of two preexisting distributed interleaving techniques. Chapter II studies a digital approach and chapter III studies an analog approach. The same modeling technique is applied in each chapter to develop a Multiple Inputs Multiple Outputs (MIMO) model compliant with the specificities of each approach and then reveal the stability concern. Modeling and simulation issues are described and a transient response optimization technique is proposed. Multiple specific items of each approach are discussed and simulations are provided for verification.

This

Chapter IV presents the conception of an improved original interleaving approach and its analysis. It is a mixed signal approach, composed of a few digital logic devices and an analogue core. The theoretical study and evaluation of the new interleaving technique is presented. Simulation results are shown and a proof-of-concept to validate the mixed signal interleaving approach presented. The modular distributed controller was conceived using functions on SMD components and multiple of them were associated on a printed circuit board.

The dynamic response of this interleaving approach is verified for modal disturbances, cases of start-up and reconfiguration, where a module is inserted during operation. The behavior during communication fault event are also shown, comprising the case of a line shorted to ground.

In the same manner, Annex F presents a top level view of the architecture used for development of an integrated circuit using NXP SmartMOS10 technology applying the concepts developed in this document. Each module integrated is composed of a half-bridge power stage, a distributed carrier generator, a current sense and balance loop, a voltage regulation loop and a voltage reference.

Author's bibliography

Context and state of the art

The While the governments are enforcing regulations, the automotive industry is developing more sophisticated Advanced Driver-Assistance Systems (ADAS) to take control of the vehicle in case of danger. ADAS can be defined as the group of electronic systems that assists the drivers in driving and parking functions. Anti-lock braking systems (ABS), traction control, cruise control and automatic braking are some examples of ADAS systems. These ADAS systems require sensors, processors and actuators.

At the same time, the embedded computers workload is rising also because of the autonomous driving trend. These embedded computers are critical, so redundancy and reconfiguration ability are fundamental to ensure mission continuity in case of fault occurrence.

This thesis is dedicated to improve the availability of the energy conversion stages that supply those computers.

Other demand from the very competitive automotive market is to offer very flexible and scalable solutions capable to address a wide range of market segments, i.e. being able to adapt to a wide range of computing workloads and consequently the required electrical power. The supply of computer cores is made usually with multiphase converters. Multiphase converters use parallel topology to offer naturally multiple (redundant) current paths to the load. However, their weakness in terms of availability is due to the use of a centralized converter controller.

NXP Semiconductors is the world leader in power management solutions for the automotive industry. Willing to propose solutions with these two characteristics, redundancy and scalability, NXP Semiconductors started the partnership with the LAPLACE laboratory in a research project leading to this thesis. The track to be studied is the use of distributed control: scalable, reconfigurable, and without Single Point Of Failures (SPOFs); a current topic in the LAPLACE research line.

This chapter will provide an introduction about the NXP safety strategy, the control architectures, an overview on processor's power supplies as well as an overview of the current trend on the processor's market. The end of this chapter will be dedicated to a brief state of the art on voltage regulation, leg current balance and also the generation of interleaved signals.

Safety strategy

NXP plan to introduced new safety solutions is shown in Figure I-1. The actual solutions are able to detect and react to a failure. However the reaction is limited, essentially by turningoff the power system and asserting an output signal to, for example, turn-off the communications and prevent non-correct information to be delivered. The context of this work is to go further and propose a processor power supply with features able to reach the fail operational status, where a reconfiguration is performed in case of failure to keep the system operational and guarantee the mission continuity. Differently of the common sense, the different features making a system can have different safety goals, such as supplying correctly a processor. It is not necessary to all the features to be fail operational to classify a system as fail operational. This work will focus only on the control structure of the microprocessor power supply.

Control architectures

As computer networks and electric grids can have multiple architectures, the same is applicable to control systems. When multiple control elements are put together in order to achieve a common task, the control architecture can be conceived in multiple different ways.

Those control architectures can be summarized in three different categories: centralized, The centralized approach is based on a leader element and many followers. They are the most common, being easy to design and fast to develop, scalable but prone to failures, mainly because of the dependent failure with root cause in the leader.

The decentralized approach is based on a nest with many hubs where the followers are connected. They are less prone to failures than a centralized architecture, but the hubs still being cause of dependent failures.

In distributed approach, all elements are in the same rank, multiple connections are used and hubs are avoided. As a result, no Single Point Of Failure (SPOF) is present, eliminating completely dependent failure. The circular chain of communications is an example of scalable and distributed architecture.

Power management

As the processors evolve, its power management functions evolve as well. As the technological node reduces and workload increases, lower voltages and higher currents are required. Some techniques to minimize the processor power dissipation are described in the Texas Instruments application report "Adaptive (Dynamic) Voltage (Frequency) Scaling -Motivation and Implementation" [3].

Usually, to a given technological node, the processor performance increases with its supply voltage level, meaning faster clock signals can be applied and higher workload can be handled. Due to process variations, some processors can handle faster clocks than others at the same voltage, but its current and power dissipation are higher.

Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) were introduced to optimize the power consumption to each specific device. AVS adjusts the supply voltage for process and aging, while the DVS adjusts for temperature. Originally, most of the digital circuit power consumption was related with gate switching, i.e. clock frequency. However, process evolution and parameter optimization led to a significant increase of leakage power, i.e. power consumption not related to the clock, responsible for around 50% of the power consumption since 45 nm process, as shown in Figure When using clock modulation, the power consumption is no more constant, as seen in Once multicore processors were introduced, the power management become trickier because each core may require a different optimal supply voltage based on its own workload. Since the introduction of processors to the consumer market, the number of phases increases. This tendency is mainly due to the increase of the delivered power as the supply voltage within the processor technological node is reduced, resulting in higher current. With the FIVR introduction and its ability locally to divide the voltage by two and double the current, the voltage delivered by the upstream VRM took a step back and increased, while the phase number stabilized.

Numerous power supply topologies were introduced and abandoned, such VRMs with coupled inductors, as well as the FIVR which was not kept in the following generation.

However, Intel may reintroduce it as technology evolves or different trade-offs will appear. Aiming to reduce the power conversion losses, processors can be supplied with direct conversion from 48V without intermediate rails. This solution was first introduced in datacenter application where the amount of converted power is very high, but it can also be used in automotive applications as 48V battery lines are available in some hybrid vehicle topologies.

The most common approach is based on isolated solutions, where the high conversion ratio is achieved thanks to a transformer. To improve scalability and keep redundancy, these approaches use as well multiphase solutions. In contrast with the multiphase solution, the VTM's one seems to present multiple SPOF.

The multiphase Buck converter intrinsic redundant characteristic contribute to obtain high reliability. For that reason, the multiphase is still the most adapted solution for the automotive industry, where the operating conditions, lifetime and cost requirements are tougher than in datacenter applications.

To improve even more the multiphase Buck reliability, the fail operational status has to be reached by applying a control architecture without SPOFs and able to reconfigure in case of fault. For this reason, the next section will introduce the state-of-the-art of the decentralized and distributed control methods applied for multiphase Buck converters.

State of the art

This state of the art gives an overview of the decentralized and distributed control techniques developed for the multiphase Buck converters. The state of the art is divided in two distinct sections. One will be dedicated to a few examples of voltage regulation techniques combined with the leg current balance. The second will be dedicated to a deep analysis and classification of the carrier interleaving techniques.

The state of the art will focus in techniques where all elements have equal importance, so called democratic, master-less, decentralized, or distributed. These solutions are preferred because of modularity and present no controller SPOF.

I.4.1. Voltage regulation and current balance

The multiphase Buck converter voltage regulation and current balance can be done in multiple different ways. This state-of-the-art will highlight only few options. The voltage regulation can be either centralized or distributed in a cooperative way. In most of the cases, the controllers use droop sharing techniques, like associating multiple converters with AVP.

The current balance can be done by sharing the average current though a shared wire or by a circular chain of communications. Four examples will be presented to illustrate these four possible combinations.

Current balance distribution

The first step to distribute the converter controller is to balance the current in a distributed manner, i.e. resulting in a partial distributed system. In these systems, a local adjustment is made to equalize the leg current based on the available information without a central controller intervention.

Shared wire

International rectifier introduce in 2003 a scalable partial distributed approach based on a centralized voltage controller (IR3080) and a multiple phase IC (IR3086). The phase IC is composed of power stages, drivers and controllers able to combine the average current value in a shared wire and adjust it. This sharing technique was patented much earlier in 1988 by K. T.

Small and all in "Single Wire Current Phase Paralleling Of Power Supplies" [9] and discussed in [10] by Lin and Chen. It is shown in [START_REF] Bolloch | New masterless modular current-sharing technique for DC/DC parallel converters[END_REF].

Voltage regulation distribution

When the voltage regulation is distributed, each leg becomes an independent converter.

A converter using a classical PI voltage controller behaves in closed loop like an ideal voltage source. As a result, the legs can no more be connected in parallel because of the concurrent voltage loops, as very high recirculation currents would flow in between then, leading to potential destruction or useless power dissipation.

One solution to connect them together is to allow each converter to behave as a nonideal voltage source. The converters can be connected together through real resistors, but virtual ones can be emulated by using the AVP technique (load line), resulting in limited recirculation currents with no unnecessary power dissipation. This technique works because the sensed load voltage carries the information of the current that shall be delivered. It is known that this technique has poor current balancing ability, because of mismatches in the voltage references, controller droop gains or load voltage sensors. For that reason, an additional current balancing technique can be added to improve the accuracy of the control system.

Shared wire

To improve the current balancing, a shared wire can be added to either obtain the leg current average value or take the average value of the reference voltages. The method using the average value of the reference voltages was proposed by Zhang and Huang [START_REF] Zhang | MVRC and its tolerance analysis for microprocessor power management[END_REF], as shown in

Circular chain

To avoid SPOF and improve current balance, the association of droop converters with a circular chain current balancing technique was proposed by COUSINEAU in [START_REF] Cousineau | Fully masterless control of parallel converter[END_REF]. In each leg, the difference of the local leg current and the adjacent currents is used by the controller to adjust the droop and obtain the same current in all legs, as shown in This technique presents a drawback as the average current appears as a gain in the control loop, so the balance has different performances with different current values.

Voltage regulation and current balance techniques summary

As a conclusion, the droop technique with the circular chain current balancing technique is the most suitable to obtain modularity with no SPOF, as shown in Table I-1, because centralized control and shared wires shall be avoided. The first group represents the ones using a centralized controller, called also multiphase controller. The centralized controller is associated with a specified number of switching-cells integrated or not in a power module.

The second group represents the scalable controllers, also called stackable or modular.

In this approach, controller and power stage are associated in the same chip. Each chip is a complete converter that can be associated with others to build a multiphase converter.

In both cases, the switching-cell modulator requires interleaved clock signals or interleaved carriers. The interleaved carriers can be, in many cases, obtained from the interleaved clocks. Therefore, in both operation modes, a Multiphase Clock Generator (MCG) is required.

Some interleaving solutions are dedicated exclusively to scalable solutions, such as detecting the switching instant, interleaving bus, reducing the output subharmonic oscillation.

Others are adaptations of centralized interleaving solutions to scalable operation.

This section presents how are implanted classical centralized MCGs and how they are implanted in the scalable approaches.

Centralized Multiphase Clock Generators

There are several different ways to generate interleaved clocks. This section will present the most used, such as the ring oscillator, DLL, a clock divider, and others. These techniques were also described and used in scalable converters. They will not be presented necessarily in this document. The reconfiguration ability will be discussed later.

Master-Slave Clock Generators

The leader-followers techniques have at least an element (the leader) that works in a different manner regarding to the other devices (the followers).

Voltage Controlled Delay Loop

The use of a ring oscillator was described in a patent by Hendrix and all in [START_REF] Hendrix | Interleaved switching converters in ring configuration[END_REF]. It shows an odd number of converters using a ring configuration to achieve interleaving. The reconfiguration is an issue in this approach because two converters have to be bypassed each time to avoid the oscillator from stopping.

Linear Technologies introduced in 1999 the PolyPhase TM trend mark [START_REF] Chen | High efficiency, high density, PolyPhase converters for high current applications[END_REF]. Interleaving is achieved without a master controller. A digital sawtooth signal, i.e. a counter output, is used for synchronization. GATEAU implanted in [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF] a similar technique but using

Masterless techniques

The previous techniques require a leader controller to send the clock and the followers roles are well defined by their connections. It introduces SPOFs, limits flexibility and reconfiguration capabilities. This section will present some masterless interleaving techniques, where all elements are equal and observe the whole system from the same point of view. The solutions compose two main categories: the interleaving bus and the circular chain.

Interleaving bus

The interleaving bus category is a generalization of all techniques that use a commonly sensed shared information to achieve interleaving.

PERREAULT introduce an analogue interleaving bus in [START_REF] Perreault | Distributed interleaving of paralleled power converters[END_REF] to interleave a multiphase converter, as shown in These two techniques are very interesting because they transmit the phase-delay reference and the optimal position in the same wire. Nevertheless, the shared wire is a SPOF and should be avoided. For that reason, techniques using only shared information or local sense emerged. Some of them will be presented here.

Local measurement

FENG and all introduced an automatic interleaving method for a parallel converter in [START_REF] Feng | Implementation of an automatic interleaving approach for parallel DC/DC converter without interleaving bus[END_REF] based on the detection of the switching instants. The switching instants were observed over the output voltage through the high frequencies emitted during the switching-cell commutation.

A PLL is implanted similarly as the one in the interleaving bus approach.

(a) (b) More recently, DUTTA and all presented a similar approach for a cascaded multilevel DC-AC converter in [START_REF] Dutta | Decentralized Carrier Interleaving in Cascaded Multilevel DC-AC Converters[END_REF]. Each local controller senses the output current with the combined effect of all switching-cells and adjust the local phase-delay to reduce the sub-harmonic oscillations. The principle scheme is shown in SINHA and all presented a decentralized interleaving technique for a parallel converter in [START_REF] Sinha | Decentralized interleaving of paralleled dc-dc buck converters[END_REF] where each local controller uses only the local phase current information. The connection scheme is shown in It can be noted the technique used by SINHA may have issues related to noise immunity and mismatches because the other elements contribution is measured indirectly. This solution may also impact the filter design or impose restrictions, as well as the response time, becoming an application issue. This technique may not be suitable for high performance PoL applications.

Circular chain

This category is composed by modules connected in a daisy chain communication architecture. Each element only exchanges a signal with its neighbors to achieve interleaving.

COUSINEAU introduced in [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF] an analogue interleaving approach where the elements communicate their triangular carrier, as shown in

Phase-delay

Local Global

Phase reference

Local

Circular chain [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF]- [START_REF] Murray | Masterless Interleaving Scheme for Parallel-Connected Inverters Operating with Variable Frequency Hysteretic Current-Mode Control[END_REF] Voltage controlled delay loop [START_REF] Kohama | New synchronizing circuit for switching power module with automatic interleaving operation[END_REF], [START_REF] Zhang | A novel distributed interleaving scheme to achieve scalable phase design for microprocessor power management[END_REF] Global Global reference [START_REF] Seleme | Decentralized Controller for Modular Multilevel Converter[END_REF] Phase splitter

Interleaving bus [START_REF] Perreault | Distributed interleaving of paralleled power converters[END_REF], [START_REF] Kudtongngam | Automatic interleaving technique using single interleaving bus for paralleling power converters[END_REF] Local measurement [START_REF] Feng | Implementation of an automatic interleaving approach for parallel DC/DC converter without interleaving bus[END_REF]- [START_REF] Sinha | Decentralized interleaving of paralleled dc-dc buck converters[END_REF] The technique using local measurements has the global phase-delay and phase reference information without SPOF. However it does not seem to be compatible with VRM applications due to the reasons already exposed.

The techniques using the circular chain combine local averaging computations to obtain the phase-delay and the phase reference. This technique is modular and reconfiguration can be obtained by bypassing the communications based on a local decision. This technique seems to be the most adapted to obtain modularity and reconfiguration ability in a VRM application.

Scientific approach

This thesis proposes and applies a formal method to model a system composed of identical control elements, called local controllers, all connected in a circular chain. It consists on the modeling of the individual local controller and the required communication links to set the whole system using matrix approach. The stability concern is simply solved using system diagonalization. This technique is applied on three different distributed interleaving systems, the third one being a new improved self-interleaving method. Concern involving the discontinuity on the angle are discussed, being fundamental for model simulation purposes.

The chapter II is dedicated to the study of the technique involving the circular chain of communications introduce by GATEAU [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF] that uses a shared clock line (global phase reference). This study will allow further understanding of the circular chain technique not yet fully exposed, including the modeling, the system diagonalization and the stability concern. A transient response optimization method is proposed. Operators to avoid wrong interleaving for simulation purposes and practical implementation are described. Model simulations involving modal response, reconfiguration and start-up are shown. The particular case of a local controller with the correction disabled is studied, such as the case of communication/connection issue. An additional case with multiple circular chains, i.e. connections with the second/third/… neighbor, is studied. A generalization is proposed to generalize the results to a generic system using shared wire approach.

The chapter III is dedicated to the study of the technique involving the circular chain of communications introduce by COUSINEAU [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF] where the local controllers exchange only the triangular carriers. A procedure similar to the one in chapter II is applied. The first part of the study include the modeling, system diagonalization and stability concern. A transient response optimization method is proposed and applied to design the equivalent controller. Model simulations involving modal response, reconfiguration and start-up are shown using the operator to avoid wrong interleaving. The steady-state values are revealed as a function of the start arrangement. Some relations between mismatch and interleaving accuracy are provided.

The particular case of a controller with infinite gain (comparator) is briefly analyzed. Circuit

Digital interleaving study

This chapter focuses on the solution introduced in [START_REF] Grégoire | Real-Time Simulation of Interleaved Converters with Decentralized Control[END_REF], [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF] The challenge here, related to the stability analysis of this system in steady-state, is the large number of variables to manage and their coupling, i.e. the multiplicity of feedback loops involved. The PDs are state-variables and must be studied all together. Several differential excitation modes exist. Therefore, the stability of the decentralized interleaving device must be carefully analyzed for both start-up and reconfiguration singular cases.

Decentralized interleaving and analytic model

In this approach, each sub-system is composed by a PDLC that provides a PD and a carrier generator. A global synchronization clock signal at the switching frequency is used by the carrier generator as phase reference, i.e. the rising edge of the clock signal is considered as the zero angle position. The carrier generator implements an internal signal generator which uses the local PD parameter to generate a phased carrier with respect to the phase reference imposed by the external clock.

The PDLC involves a digital feedback loop to put the local PD in between the PDs of its neighboring cells. The PDLC will be modelled in this sub-chapter to reveal the system behavior. The iterations are considered synchronous for modelling, i.e. an iteration is done once all PDs have been updated. The PD values treated in this work are normalized, i.e. in between 0 and 1, and the quantization effects are not taken into account.

II.1.1. Local controller modelling

In this approach, the PDs are numeric and sampled data due to the numerical For practical reason, it is important to mention that the values of the carrier positions are normalized, i.e. ranging from 0 to 1 instead of 0 to 2π radians. Their average value is the target position 𝜃𝜃 � 𝑘𝑘 for the next iteration, computed at the iteration k, evaluated by the simple Eq. (II-1).

𝜃𝜃 � 𝑘𝑘 = 0.5 �𝜃𝜃 𝑃𝑃 𝑘𝑘 + 𝜃𝜃 𝑆𝑆 𝑘𝑘 � (II-1)
𝜃𝜃 𝑘𝑘 is the local PD, and 𝜀𝜀 𝜃𝜃 𝑘𝑘 is the local PD error evaluated by Eq. (II-2).

𝜀𝜀 𝜃𝜃 𝑘𝑘 = 𝜃𝜃 � 𝑘𝑘 -𝜃𝜃 𝑘𝑘 (II-2)
∆𝜃𝜃 𝑘𝑘 is the correction applied at the next iteration, given by the generic discrete transfer function 𝐶𝐶(𝐶𝐶) in Eq. (II-3). The stability study has to choose the 𝐶𝐶(𝐶𝐶) to ensure convergence.

𝛥𝛥𝜃𝜃(𝐶𝐶) 𝜀𝜀 𝜃𝜃 (𝐶𝐶) = 𝐶𝐶(𝐶𝐶) (II-3)
Eq. (II-4) gives the new PD obtained 𝜃𝜃 𝑘𝑘+1 for the local controller at the iteration 𝑘𝑘 + 1.

𝜃𝜃 𝑘𝑘+1 = 𝜃𝜃 𝑘𝑘 + 𝛥𝛥𝜃𝜃 𝑘𝑘 (II-4)
The block diagram of an PDLC is shown in

𝜃𝜃(𝐶𝐶) ′ 𝜃𝜃(𝐶𝐶) = 𝐶𝐶(z) 1 𝐶𝐶 -1 (II-5)
where 𝜃𝜃(𝐶𝐶) and 𝜃𝜃(𝐶𝐶) ′ represent respectively an injection and measurement to obtain the open-loop transfer function.

The closed-loop pole values depends on the corrector 𝐶𝐶(𝐶𝐶). Discrete control theory establishes that the system is stable if the closed-loop poles absolute value are less than 1, i.e.

each poles must be located into the unit circle, the circle itself being the stability limit criterion.

Eq. (II-6) is the closed-loop local controller discrete response including the corrector 𝐶𝐶(𝐶𝐶) in the Z-domain taking into account the initial value 𝜃𝜃 0 and the input 𝜃𝜃 � . Two terms are

shown, the first one corresponds to the free response dependent on the start value 𝜃𝜃 0 and the second corresponds to the forced response dependent on 𝜃𝜃 � (𝐶𝐶).

𝜃𝜃(𝐶𝐶) = 𝐶𝐶 𝐶𝐶 -[1 -𝐶𝐶(z)] 𝜃𝜃 0 + 𝐶𝐶(z) 𝐶𝐶 -[1 -𝐶𝐶(z)] 𝜃𝜃 � (𝐶𝐶) (II-6)
However, the variable 𝜃𝜃 � is a combination of the previous and next PDs, i.e. other statevariables connected through the circular chain. Therefore, the study of the system response by only focusing on the behavior of independent local loops is not accurate. The stability of the local loop does not guarantee the stability of the overall system. Later on, a similar expression will be shown for the complete system.

II.1.2. Overall system modelling

The study of the system's stability with a generic number 𝑁𝑁 of PDLCs including the several connections existing between them has to be performed. The overall system will be then modeled using a matrix approach. The PD values 𝜃𝜃 of all PDLC are numbered arbitrarily from (II-7)

This matrix is used to calculate the PD errors 𝜀𝜀 𝜃𝜃1 to 𝜀𝜀 𝜃𝜃𝑆𝑆 present in the column vector 𝜺𝜺 𝜽𝜽 derived from 𝜽𝜽. The error vector at iteration 𝑘𝑘 is calculated with Eq. (II-8), where 𝝋𝝋 is an additive term, required to insure continuity of the computation in a trigonometric circle, that will be discussed latter. The 𝝋𝝋 vector is considered here constant and will be calculated by the "phase-delay target operator". Its value does not affect the stability study.

𝜽𝜽(𝐶𝐶) ′ 𝜽𝜽(𝐶𝐶) = -𝑳𝑳 𝐶𝐶(z) 1 𝐶𝐶 -1 (II-9)
The system closed-loop discrete transfer function can be written as represented by Eq.

(II-10) that is comparable with Eq. (II-6) (monovariable), where 𝑰𝑰 is the identity matrix and 𝜽𝜽 𝟎𝟎 is a column vector filled with the starting values of the PDs.

𝑳𝑳 6 = ⎣ ⎢ ⎢ ⎢ ⎢ ⎡ -1 0.5 0 0 0 0.5 0.5 -1 0.5 0 0 0 0 0.5 -1 0.5 0 0 0 0 0.5 -1 0.5 0 0 0 0 0.5 -1 0.5 0.5 0 0 0 0.5 -1 ⎦ ⎥ ⎥ ⎥ ⎥ ⎤ 𝜽𝜽(𝐶𝐶) = �𝐶𝐶𝑰𝑰 -�𝑰𝑰 + 𝑳𝑳 𝐶𝐶(𝐶𝐶)�� -1 𝐶𝐶𝑰𝑰 𝜽𝜽 𝟎𝟎 + �𝐶𝐶𝑰𝑰 -�𝑰𝑰 + 𝑳𝑳 𝐶𝐶(𝐶𝐶)�� -1 𝐶𝐶(𝐶𝐶)𝑰𝑰 𝝋𝝋(𝐶𝐶) (II-10)
Now, the system's stability can be verified by diagonalization or eigendecomposition.

In this case the diagonalization is convenient because the corrector 𝐶𝐶(z) has a generic transfer function and its root locus can be plotted. The diagonalization and stability study will be performed analytically with respect to 𝐶𝐶(z). The system diagonalization reveals the decoupled system dynamics, called the modal responses, and which determine the response of the overall system to external excitations. The whole system is stable if all modal responses are stable.

Circulant matrices

The matrix 𝑳𝑳 and the feedback loops couple all PDs together. A change of basis allows to decompose the original coupled system into several independent systems. The matrices 𝑳𝑳 is real, symmetric and circulant due to the circular chain architecture. Several interesting properties come from the fact that a matrix is circulant.

II.2.1. Circulant matrix diagonalization

Circulant matrices of order 𝑁𝑁 are diagonalisable with the Discrete Fourier Transform [START_REF] Hunt | A matrix theory proof of the discrete convolution theorem[END_REF] (DFT) matrix 𝑾𝑾 (eigenvectors) for 𝑁𝑁 samples, as shown in Eq. (II-11). The change of basis matrix 𝑾𝑾 is the unitary DFT matrix, so 𝑾𝑾 * × 𝑾𝑾 = 𝑰𝑰, with 𝑾𝑾 * = 𝑾𝑾 -1 , where 𝑾𝑾 * is the conjugate transpose of 𝑾𝑾 and equals to its inverse. Thus, the multiplication of 𝑾𝑾 * with the PD vector 𝜽𝜽 produces the DFT of the PDs.

𝑾𝑾 = 1 √𝑁𝑁 ⎝ ⎜ ⎛ 1 1 1 ⋯ 1 1 𝜔𝜔 𝜔𝜔 2 ⋯ 𝜔𝜔 (𝑆𝑆-1) 1 𝜔𝜔 2 (𝜔𝜔 2 ) 2 ⋯ 𝜔𝜔 2(𝑆𝑆-1) ⋮ ⋮ ⋮ ⋱ ⋮ 1 𝜔𝜔 (𝑆𝑆-1) 𝜔𝜔 2(𝑆𝑆-1) ⋯ 𝜔𝜔 (𝑆𝑆-1) 2 ⎠ ⎟ ⎞
where

𝜔𝜔 = 𝑒𝑒 √-1 2𝜋𝜋 𝑆𝑆 (II-11)
Any circulant matrix 𝑪𝑪 is a sum of a the shift matrix 𝑺𝑺, shown in Eq. (II-12).

𝑪𝑪 = � 𝑐𝑐 𝑖𝑖 𝑺𝑺 𝑖𝑖 𝑆𝑆-1 𝑖𝑖=0 𝑺𝑺 = ⎝ ⎜ ⎛ 0 1 0 ⋯ 0 0 0 1 ⋯ 0 0 0 0 ⋱ ⋮ ⋮ ⋮ ⋮ ⋱ 1 1 0 0 ⋯ 0 ⎠ ⎟ ⎞ (II-12)
The eigenvalue matrix 𝚲𝚲 𝑪𝑪 of the circulant matrix 𝑪𝑪 can be derived from Eq. (II-13).

𝚲𝚲 𝑪𝑪 = 𝑾𝑾 𝑪𝑪 𝑾𝑾 -𝟏𝟏 = � 𝑐𝑐 𝑖𝑖 𝑼𝑼 𝑖𝑖 𝑆𝑆-1 𝑖𝑖=0 𝑼𝑼 = ⎝ ⎜ ⎛ 1 0 0 ⋯ 0 0 𝜔𝜔 0 ⋯ 0 0 0 𝜔𝜔 2 ⋯ 0 ⋮ ⋮ ⋮ ⋱ ⋮ 0 0 0 ⋯ 𝜔𝜔 (𝑆𝑆-1) ⎠ ⎟ ⎞ (II-13)

II.2.2. Complex conjugate orthogonal eigenvectors

The matrix 𝑾𝑾 columns are denoted 𝑤𝑤 𝑖𝑖 with 𝜆𝜆 = 0 … 𝑁𝑁 -1. Even if the columns 𝑤𝑤 𝑖𝑖 are orthogonal eigenvectors, some of them can be written such as the conjugate of another, as shown in Eq. (II-14). As matrix 𝑾𝑾 is symmetric, it is also valid for its rows and the same property is valid for 𝑾𝑾 * . As all the processed PDs 𝜽𝜽 are real, the modal coefficient 𝜃𝜃 * 𝑆𝑆-𝑖𝑖 found with those 𝑤𝑤 𝑖𝑖 * vectors will be the complex conjugate of those found with 𝑤𝑤 𝑆𝑆-𝑖𝑖 * .

λ 𝑆𝑆-𝑖𝑖 = λ 𝚤𝚤 � 𝑤𝑤 𝑆𝑆-𝑖𝑖 = 𝑤𝑤 𝚤𝚤 ��� 𝜽𝜽 ∈ ℝ 𝑵𝑵 ⇔ 𝜃𝜃 * 𝑆𝑆-𝑖𝑖 = 𝑤𝑤 𝑆𝑆-𝑖𝑖 * 𝜽𝜽 = 𝑤𝑤 𝚤𝚤 ��� * 𝜽𝜽 = 𝜃𝜃 * 𝚤𝚤 ���� 𝜆𝜆 = � 1 … 𝑁𝑁 -1 2 , 𝜆𝜆𝑓𝑓 𝑁𝑁 𝜆𝜆𝑖𝑖 𝑜𝑜𝜃𝜃𝜃𝜃. 1 … 𝑁𝑁 2 ⁄ -1, 𝜆𝜆𝑓𝑓 𝑁𝑁 𝜆𝜆𝑖𝑖 𝑒𝑒𝑣𝑣𝑒𝑒𝑒𝑒. (II-14)
As a consequence, 𝑁𝑁 coefficients can represent the intrinsic information. The complex eigenvectors give two coefficients while the real ones gives only one. Those rows that can be written such as the conjugate of another have also the same eigenvalue. The matrix 𝑳𝑳 has only 𝑀𝑀 different eigenvalues, where 𝑀𝑀 is an integer that satisfies the condition of Eq. (II-15).

𝑀𝑀 = � 𝑁𝑁 + 1 2 , 𝜆𝜆𝑓𝑓 𝑁𝑁 𝜆𝜆𝑖𝑖 𝑜𝑜𝜃𝜃𝜃𝜃. 𝑁𝑁 2 ⁄ + 1, 𝜆𝜆𝑓𝑓 𝑁𝑁 𝜆𝜆𝑖𝑖 𝑒𝑒𝑣𝑣𝑒𝑒𝑒𝑒.
(II-15)

A reduced representation can be used as decomposition matrix to represent the carried information. This matrix is named 𝑽𝑽. Each of them has an equivalent row in 𝑽𝑽 * , denoted 𝑣𝑣 * 𝑚𝑚 , that has a number of cycles 𝜆𝜆 related to its fundamental frequency. This number of cycles 𝜆𝜆 will be used thereafter as the For that reason, the indexation starts from 0. The vector 𝑣𝑣 * 0 is real constant, so it will provide the average value, or also the common mode information of the decomposed variable. The eigenvectors of the double modes (𝑁𝑁 = 8, m from 1 to 3) are complex and are naturally in quadrature (orthogonal) with their real part.

II.2.3. L matrix eigenvalues

The eigenvalues of the circulant matrix are indeed known. All eigenvalues of 𝑳𝑳 have to be identified to ensure the stability of all modal responses and to adjust the convergence speed.

Gerschgorin's theorem shows that the eigenvalues of 𝑳𝑳 are real and in between -2 and 0. The eigenvalues of 𝑳𝑳 are shown in Eq. (II-16), where the complex exponential is rewritten in the cosine form. The 𝑁𝑁 diagonal elements λ 𝑖𝑖𝑖𝑖 of 𝜦𝜦 are denoted λ 𝑖𝑖 for 𝜆𝜆 = 0 … 𝑁𝑁 -1.

λ 𝑖𝑖 = 𝑒𝑒 √-1 2𝜋𝜋𝑖𝑖 𝑆𝑆 + 𝑒𝑒 -√-1 2𝜋𝜋𝑖𝑖 𝑆𝑆 2 -1 = cos 2 𝜋𝜋 𝜆𝜆 𝑁𝑁 -1, 𝜆𝜆 = 0 … 𝑁𝑁 -1 (II-16)
As said previously, the 𝑀𝑀 different values can be found with 𝜆𝜆 = 0 … 𝑀𝑀 -1. As this system has only 𝑀𝑀 different eigenvalues, the study of the system can be done using only these 𝑀𝑀 eigenvalues of 𝑳𝑳.

Change of basis

The state matrix 𝑳𝑳 diagonalization is described in Eq. (II-17).

𝜦𝜦 = 𝑾𝑾 * 𝑳𝑳𝑾𝑾 (II-17)
This system will be studied using the eigenvalues and the transformation matrices of 𝑳𝑳 to reveal its stability. To do so, a change of basis expressed by the set of Eq. (II-18) is applied to the system, resulting in the Discrete Fourier Transform of all system signals.

(a) (b)

𝜽𝜽 * = 𝑾𝑾 * 𝜽𝜽, 𝝓𝝓 * = 𝑾𝑾 * 𝝓𝝓, 𝜺𝜺 𝜽𝜽 * = 𝑾𝑾 * 𝜺𝜺 𝜽𝜽 𝜽𝜽 𝟎𝟎 * = 𝑾𝑾 * 𝜽𝜽 𝟎𝟎 (II-18)
It should be noted that 𝜺𝜺 𝜽𝜽 * , the error vector DFT, can be used to visualize the corrector performance, i.e. modal settling time, by looking the time required to mitigate it. Expression to compute its absolute value is shown in Eq. (II- [START_REF] Zhang | A novel distributed interleaving scheme to achieve scalable phase design for microprocessor power management[END_REF]. [START_REF] Huang | A scalable multiphase buck converter with average current share bus[END_REF]. The components express the residual disturbance contained in each mode during simulation. It has to converge to zero as the system goes to steady-state.

|𝜺𝜺 𝜽𝜽 * | = 𝑎𝑎𝑎𝑎𝑖𝑖�𝜃𝜃𝑓𝑓𝑑𝑑( 𝜺𝜺 𝜽𝜽 )� = 𝑎𝑎𝑎𝑎𝑖𝑖( 𝑾𝑾 * 𝜺𝜺 𝜽𝜽 ) (II-19) Each element of |𝜺𝜺 𝜽𝜽 * | is shown in Eq. (II-
|𝜀𝜀 𝜃𝜃 * | 𝑚𝑚 = 𝑎𝑎𝑎𝑎𝑖𝑖( 𝒘𝒘 * 𝒎𝒎 𝜺𝜺 𝜽𝜽 ), 𝜆𝜆 = 0 … 𝑀𝑀 -1 (II-20)
The others coefficients not chosen in Eq. (II-20) are duplicated (complex conjugated) because 𝜺𝜺 𝜽𝜽 is always real. The open-loop discrete transfer function in the Z-domain in Eq. (II-9)

is rewritten in a diagonal form in Eq. (II-21).

𝜽𝜽 * (𝐶𝐶)′ 𝜽𝜽 * (𝐶𝐶) = -𝜦𝜦 𝐶𝐶(z) 1 𝐶𝐶 -1 (II-21)
As the eigenvalue matrix 𝜦𝜦 is diagonal, Eq. (II-21) can be rewritten in 𝑁𝑁 independent modal open-loop transfer functions (OLTF) as denoted in Eq. (II-22) using the diagonal index 𝜆𝜆, where the 𝑁𝑁 diagonal elements of 𝜦𝜦 are denoted λ 𝑖𝑖 for 𝜆𝜆 = 0 … 𝑁𝑁 -1.

𝜃𝜃 𝑖𝑖 * (𝐶𝐶)′ 𝜃𝜃 𝑖𝑖 * (𝐶𝐶) = -λ 𝑖𝑖 1 𝐶𝐶 -1 𝐶𝐶(z), 𝜆𝜆 = 0 … 𝑁𝑁 -1 (II-22)
It should be noted that the diagonal OLTF in Eq. (II-22) is quite similar to the previous local OLTF of Eq. (II-5) where the only difference is the multiplicative term -λ 𝑖𝑖 . Nevertheless, its value is important and can compromise the system stability. Eq. (II-22) shows that the OLTF of each mode has the same identical corrector 𝐶𝐶(z) multiplied with different eigenvalues. As a result, the modes cannot be independently controlled because of the feedback matrix L. Using different correctors for each PDLC invalidates the approach presented here witch rely on identical correctors 𝐶𝐶(z) to make the diagonalisation.

The closed-loop transfer function (CLTF) of Eq. (II-10) can also be written in a diagonal form such as in Eq. (II-23).

𝜽𝜽 * (𝐶𝐶) = �𝐶𝐶𝑰𝑰 -�𝑰𝑰 + 𝜦𝜦 𝐶𝐶(𝐶𝐶)�� -1 𝐶𝐶𝑰𝑰 𝜽𝜽 𝟎𝟎 * + �𝐶𝐶𝑰𝑰 -�𝑰𝑰 + 𝜦𝜦 𝐶𝐶(𝐶𝐶)�� -1 𝐶𝐶(𝐶𝐶) 𝝋𝝋 * (𝐶𝐶) (II-23)
Eq. (II-23) can be rewritten as a system of 𝑁𝑁 independent transfer functions provided by Eq. (II-24) because all matrices in Eq. (II-23) are diagonal.

𝜃𝜃 * 𝑖𝑖 (𝐶𝐶) = 𝐶𝐶 𝐶𝐶 -�1 + λ 𝑖𝑖 𝐶𝐶(𝐶𝐶)� 𝜃𝜃 0 * 𝑖𝑖 + 𝐶𝐶(z) 𝐶𝐶 -�1 + λ 𝑖𝑖 𝐶𝐶(𝐶𝐶)� 𝜑𝜑 * 𝑖𝑖 (𝐶𝐶), 𝜆𝜆 = 0 … 𝑁𝑁 -1 (II-24)
It should also be noted that the diagonal CLTF term of Eq. (II-24) is quite similar to the previous local CLTF of Eq. (II-6) where the only difference is the multiplicative term -λ 𝑖𝑖 , as expected. The eigenvalues λ 𝑖𝑖 must be found to establish the stability criteria and determine the several independent modal responses.

The revealed transfer functions are similar to the case of one single loop (II-6), but with the eigenvalues λ 𝑖𝑖 playing as a multiplicative factor, instead of the constant -1. Two important points have to be highlighted here. At first, the mode 0 (common mode) pole is always equals to 1 because λ 0 = 0 . Second, all differential modes, i.e. 𝜆𝜆 = 1 … 𝑀𝑀 -1 cannot be independently controlled because the eigenvalues come from the feedback matrix 𝑳𝑳 imposed by the circular chain architecture, as described previously. It is also important to note that all local controllers are identical, so they use the same corrector. These conclusions are valid for any type of local controller chosen.

It should be noted finally that this system does not take in account the average value of the PDs (common mode value) with the PDLC computations. As a consequence, this system is not able to impose any PD value because the common mode is not controllable, only relative values are controlled. The PDs and their average values may have any absolute value. If this observation is an issue, it can be avoided in noise sensitive applications using one constant PD for instance, but this solution may raise other stability considerations addressed in section II.8.

Stability concern

The corrector 𝐶𝐶(𝐶𝐶) has to guarantee stability and convergence of all differential modes.

To do so, in this discrete system model, all closed-loop poles have to be located inside the unit circle. Besides that, the controller specifications normally impose basic closed-loop constraints, such as steady-state error (static gain), settling time and damping. The corrector can be very simple or more complex, depending on the flexibility required. However, best trade-offs can be made with higher number of poles and zeros provided by the corrector 𝐶𝐶(z). Eq. (II-25) shows four possible correctors 𝐶𝐶(𝐶𝐶) , which are respectively proportional, integral, proportionalintegral, and lead-lag. All closed-loop poles are visible in these figures. Note that the mode 0 corresponds to the common mode which is not regulated. Each modal CLTF has different poles values due to its specific eigenvalue, but all zeros overlap. The integral controller is the only one in these particular cases that do not present a stable root locus, all poles are on the unit circle. This is because the open-loop transfer function becomes a double integrator, then, as known, a double integrator is always in stability limit, leading to undamped oscillations.

Proportional Integral Proportional-Integral Lead-Lag (II-25) 𝐶𝐶(z) = α 𝐶𝐶(z) = α 𝐶𝐶 𝐶𝐶 -1 𝐶𝐶(z) = α 𝐶𝐶 -𝐶𝐶 𝑂𝑂𝑂𝑂 𝐶𝐶 -1 𝐶𝐶(z) = α 𝐶𝐶 -𝐶𝐶 𝑂𝑂𝑂𝑂 𝐶𝐶 -𝑝𝑝 𝑂𝑂𝑂𝑂
The proportional controller has only one coefficient, so a trade-off has to be made between the static gain, the settling time and the damping factor. It means that the coefficient α has to be as high as possible to ensure a small static error, but not too high to prevent the poles going outside the unit circle. As shown in From now, a complete study of the stability and system dynamic responses for the proportional and lead-lag correctors will be developed. It will be done for any α and 𝑁𝑁 to reveal the stability criteria and to optimize the settling time.

II.4.1. Proportional corrector

The proportional corrector represented by the gain α is the simplest case because the transfer function order does not change and all pole values are real. In this study, the gain α is also called "the convergence factor". The system dynamics can be easily identified from Figure II-4, Eq. (II-9) and Eq. (II-10). The state matrix 𝑨𝑨 , in Eq. (II-26), can be easily introduced for the stability study.

𝑨𝑨 = 𝑰𝑰 + 𝛼𝛼 𝑳𝑳, (II-26)
The stability can now be studied using the eigen decomposition of the matrix 𝑨𝑨, revealing the system eigenvalues, i.e. the poles of the system. The eigenvalue matrix of 𝑨𝑨 is named 𝚲𝚲 𝑨𝑨 .The 𝚲𝚲 𝑨𝑨 expression is shown in Eq. (II-27).

𝚲𝚲 𝑨𝑨 = 𝑾𝑾 * 𝑨𝑨𝑾𝑾 = 𝐈𝐈 + α 𝚲𝚲 (II-27)
The 𝑁𝑁 diagonal elements λ 𝐴𝐴𝑖𝑖𝑖𝑖 of 𝚲𝚲 𝑨𝑨 , named λ 𝐴𝐴𝑖𝑖 for 𝜆𝜆 = 0 … 𝑁𝑁 -1, are the 𝑁𝑁 modal poles of the diagonal representation shown in Eq. (II-28). As shown earlier, there are only 𝑀𝑀 different eigenvalues, so only 𝑀𝑀 modes have to be studied. As a result, the poles of the diagonal modal transfer function described in (II-24) are revealed in Eq. (II-28).

λ 𝐴𝐴𝑚𝑚 = 1 + α λ 𝑚𝑚 , 𝜆𝜆 = 0 … 𝑀𝑀 -1 (II-28)

Stability Criterion

To guarantee the stability, all differential modes (𝜆𝜆 ≠ 0) have to be damped correctly, i.e. its eigenvalues' absolute value must be less than 1, so the convergence factor α has to respect the condition 0 < α < 1 to ensure stability. The demonstration is shown in Eq. (II-29).

Assuming then

|λ 𝐴𝐴𝑚𝑚 | = |1 + α λ 𝑚𝑚 | < 1, -2 ≤ λ 𝑚𝑚 < 0, m = 1 … 𝑀𝑀 -1 |1 + α λ 𝑚𝑚 | < 1 ⟺ -1 < 1 + α λ 𝑚𝑚 < 1 ⟺ 0 < α < 1 (II-29)
It makes a difference compare to the model taking into account only one single loop. Indeed, the system seemed to be stable for α between 0 and 2 because the eigenvector does not appear.

Settling Time Optimization

The settling time of a mode depends both on the local controller computation frequency/ period and on the corrector parameters. Indeed, there is no physical process behind this interleaving system, i.e. no inertia, power or energy involved. The computation period can also be completely independent of the carrier period. The computation period is limited mainly by the serial communication bandwidth, if used, and by the computation delays.

Based on the corrector parameters, initial value 𝜃𝜃 0 * 𝑖𝑖 and 𝜑𝜑 * 𝑖𝑖 (𝐶𝐶), the discrete domain modal responses 𝜃𝜃 * 𝑚𝑚 (𝑘𝑘) can be computed to each mode by taking the inverse Z-transform (operator noted ℒ -1 ) of 𝜃𝜃 * 𝑖𝑖 (𝐶𝐶), shown in Eq. (II-24). This result is shown in Eq. (II-30), where 𝜃𝜃 * 𝑚𝑚ℎ (𝑘𝑘) is the natural (homogeneous) response and 𝜃𝜃 * 𝑚𝑚𝑚𝑚 (𝑘𝑘) is the forced (non-homogeneous) response, m is the mode number, H is the Homogeneous marker and F is the non-homogeneous (Forced) marker.

𝜃𝜃 * 𝑚𝑚 (𝑘𝑘) = ℒ -1 {𝜃𝜃 * 𝑖𝑖 (𝐶𝐶)} = 𝜃𝜃 * 𝑚𝑚𝑚𝑚 (𝑘𝑘) + 𝜃𝜃 * 𝑚𝑚𝑚𝑚 (𝑘𝑘), 𝜆𝜆 = 0 … 𝑁𝑁 -1 (II-30)
where

𝜃𝜃 * 𝑚𝑚𝑚𝑚 (𝑘𝑘) = ℒ -1 � 𝐶𝐶 𝐶𝐶 -�1 + λ 𝑖𝑖 𝐶𝐶(𝐶𝐶)� 𝜃𝜃 0 * 𝑚𝑚 � 𝜃𝜃 * 𝑚𝑚𝑚𝑚 (𝑘𝑘) = ℒ -1 � 𝐶𝐶(z) 𝐶𝐶 -�1 + λ 𝑖𝑖 𝐶𝐶(𝐶𝐶)� 𝜑𝜑 * 𝑚𝑚 (𝐶𝐶)�
Then, based on the corrector parameters, the number of iterations for convergence can be computed, for example, by the number k of iterations necessary to reduce the absolute value of each natural (homogeneous) differential mode response 𝜃𝜃 * 𝑚𝑚𝑚𝑚 to less than 5% of its initial value 𝜃𝜃 0 * 𝑚𝑚 . The natural (homogeneous) modal response 𝜃𝜃 * 𝑚𝑚ℎ shown in Eq. (II-31) is found by computing the inverse Z-transform shown in Eq. (II-30).

𝜃𝜃 * 𝑚𝑚𝑚𝑚 (𝑘𝑘) = λ Am k 𝜃𝜃 0 * 𝑚𝑚 , k ≥ 0, 𝜆𝜆 = 1 … 𝑀𝑀 -1 (II-31)
Eq. (II-32) shows the general formula for the number of iterations required derived from Eq. (II-31).

𝑎𝑎𝑎𝑎𝑖𝑖 � 𝜃𝜃 * 𝑚𝑚𝑚𝑚 (𝑘𝑘) 𝜃𝜃 0 * 𝑚𝑚 � = 𝑎𝑎𝑎𝑎𝑖𝑖�λ Am k � ≤ 5% ⇒ 𝑘𝑘 5%_m ≥ 𝑙𝑙𝑜𝑜𝑙𝑙(0.05) 𝑙𝑙𝑜𝑜𝑙𝑙�𝑎𝑎𝑎𝑎𝑖𝑖(λ Am )� , 𝜆𝜆 = 0 … 𝑀𝑀 -1 (II-32)
Table II-1 shows the number of iterations required for the convergence of the differential modes in the cases of Figure II-8. The mode 4 is at the limit of stability and oscillates with α = 1. The modes 1 and 2 speeds up when α increases. It shows explicitly the number of iterations required for each differential mode with a given α parameter. With different configurations observed, it is not easy to guess which would be the optimal one. As numerous performances depend on the same parameter, a criterion has to be proposed to find a trade-off helping to choose α. Each differential mode eigenvalue has to be reduced in absolute value to speed up the response. One option is to improve the worst case by reducing as much as possible the absolute value of the larger eigenvalue. The minimum value using the absolute maximum criterion is found with α = 0.87. It is also the point where the absolute values of λ A1 and λ A4 are equal. The minimum value using the 𝚲𝚲 𝐀𝐀 eigenvalue least squares criterion is found with α = 0.62. Finally, the minimum value using the 𝑘𝑘 5% least squares criterion is found with α = 0.78. Each criterion gives different optimum values. For this configuration with 𝑁𝑁 = 8, a convenient value is about 3/4.

It should be noted, in this system, the convergence dynamics depend also on which modes are excited. Indeed, if only fast modes are excited the convergence is faster. For instance, if mode 1 is not excited with α = 1/2, its convergence would be faster than the case where α = 3/4 and all modes are excited. An example will be shown latter.

Eigenvalues and Stability vs. Number of Active PDLCs

Using this distributed democratic approach for the interleaving of the carriers, the ability of self-reconfiguration if an active PDLC is added or removed is inherent to this system. When α is equal to 1 with 𝑁𝑁 even, the last mode 𝑁𝑁/2 reaches the stability limit.

Nevertheless, if 𝑁𝑁 is odd, the value of the last mode does not reach -1, but only if N tends towards infinity. Thus, the limit of stability is never reached for the case of 𝑁𝑁 odd. Therefore, this system is stable for any value of 𝑁𝑁 if 0 < α < 1.

A reconfiguration event is the modification during operation of the number 𝑁𝑁 of active PDLCs. Non-active PDLCs are bypassed in order to maintain closed the chain of communications and become invisible (transparent) to active PDLCs. As seen before, all eigenvalues depend on a single convergence factor α, and a trade-off has to be made. On the other hand, when a reconfiguration is made, α remains the same and the eigenvalues have to continue, in a reasonable limit, to ensure stability and fast convergence time. The bypassed PDLCs are no longer taken into account in the stability analysis. Eigenvalue

A i N = 8 A 0 A 1 A 2 A 3 A 4 -1 0 1 = 3/4 -1 0 1 -1 0 1 Imaginary Axis -1 0 1 -1 0 1 -1 0 1 Real Axis -1 0 1 N = 10 = 1 -1 0 1 N = 9 -1 0 1 N = 8 Imaginary Axis -1 0 1 N = 7 -1 0 1 -1 0 1 N = 6
Real Axis

As shown in the figure, the number of existing modes is a function of 𝑁𝑁. As 𝑁𝑁 increases, the eigenvalues shift to the right, and the new ones appear on the left. As the eigenvalues change, they stay always in the same range between 1 -2α and 1, e.g. [-1/2 1] for α equal to 3/4 and [-1 1] for α equal to 1. As previously demonstrated in section II.4.1.1 Stability Criterion, this system is stable for any value of 𝑁𝑁 if 0 < α < 1.

The 5% response should also be optimal when 𝑁𝑁 varies. However the number of active modules is unknown and all local controllers should be equal. To simplify the design, the same α is used for any 𝑁𝑁 value and a relative time response degradation is observed.

The parameter 𝑘𝑘 5%_m shows the performance of each mode independently. However, to optimize all modes together, a new parameter combining all mode performances has to be The several curves show the minimum is in general between 0.6 and 0.9, and it goes up with 𝑁𝑁 . This happens because λ 1 goes down with 𝑁𝑁 and the 1 𝑠𝑠𝑡𝑡 mode (𝜆𝜆 = 1) becomes dominant. The curves would shift slightly to the right for 𝑁𝑁 odd because the eigenvalues are slightly smaller in this case. A global optimum can be chosen at 3/4, where most of the curves loose less than 10% relative to the optimum. More information about the parameter combining all mode performances can be find in [START_REF] Hillesheim | Eigendecomposition of a digital iterative decentralised interleaving for multicellular converters[END_REF].

II.4.2. Lead-lag corrector

The lead-lag corrector shown in Eq. (II-25) brings more flexibility to the controller design because three parameters can be chosen, i.e. gain, zero and pole values. These parameters are considered as Open-Loop (OL) zero 𝐶𝐶 𝑂𝑂𝑂𝑂 and pole 𝑝𝑝 𝑂𝑂𝑂𝑂 , both real numbers. The properties developed during the previous study of the proportional controller are still valid here using the proposed corrector. Complementary explanations about the corrector design will be given here.

Stability criterion

With the lead-lag corrector, the new expression of the modal natural (homogeneous) response 𝜃𝜃 * 𝑚𝑚ℎ is shown in Eq. (II-33). It can be used to define the stability criterion and the dynamic responses of the differential modes, i.e. the settling time or 5% response. 𝜃𝜃 * 𝑚𝑚ℎ is found by inserting the corrector transfer function 𝐶𝐶(𝐶𝐶) at the first term of Eq. (II-30), where m is the mode number and h is the homogeneous marker.

𝜃𝜃 * 𝑚𝑚ℎ (𝐶𝐶) = 𝐶𝐶 2 -(𝑝𝑝 𝑂𝑂𝑂𝑂 + 1) 𝐶𝐶 + 𝑝𝑝 𝑂𝑂𝑂𝑂 𝐶𝐶 2 -(𝑝𝑝 𝑂𝑂𝑂𝑂 + 1 + α λ 𝑚𝑚 ) 𝐶𝐶 + (𝑝𝑝 𝑂𝑂𝑂𝑂 + α λ 𝑚𝑚 𝐶𝐶 𝑂𝑂𝑂𝑂 ) 𝜃𝜃 0 * 𝑖𝑖 , m = 0 … M -1 (II-33)
To simplify the study and further implementation, some relations are proposed. The stability criterion and its constraint are shown in Eq. (II-34). This result is valid for any value of 𝑁𝑁.

0 < α < 1 + 𝑝𝑝 𝑂𝑂𝑂𝑂 1 + 𝐶𝐶 𝑂𝑂𝑂𝑂 ⟺ 0 < 𝐶𝐶 𝑂𝑂𝑂𝑂 < 𝑝𝑝 𝑂𝑂𝑂𝑂 < 1 (II-34)
The demonstration is shown in Annex A.

Transient response optimization

To optimize the transient response, the 5% settling time remains a good criterion. An eigen decomposition can be performed and the eigenvalues can be used to compute the number of iterations required for convergence. However, if only the dominant pole is considered, it would be inaccurate because the zeros of the transfer functions disturb and delays the response.

For this reason, the diagonalization is preferred. The number of iterations for 5% convergence 𝑘𝑘 5% should be the number 𝑘𝑘 > 0 of iterations necessary to reduce the absolute value of each natural (homogeneous) differential mode response 𝜃𝜃 * 𝑚𝑚ℎ to less than 5% of its initial value 𝜃𝜃 0 * 𝑚𝑚 . The envelope on Bode diagram is considered to simplify the analysis. So 𝑘𝑘 5% is the number of iterations 𝑘𝑘 > 0 when the envelope reaches the 5% criterion. Depending on the modal eigenvalue λ 𝑚𝑚 and α, four different pole cases can be found: two complex conjugate poles, two real coincident poles, two real different poles or one real pole. Their partial fraction decomposition is shown in Eq. (II-35) with its envelope, found by applying the inverse Ztransform to the partial fractions.

𝑝𝑝 1 , 𝑝𝑝 2 ∈ ℂ, 𝑝𝑝 2 = 𝑝𝑝 1 * 𝑟𝑟 1 -𝑝𝑝 1 𝐶𝐶 -1 + 𝑟𝑟 * 1 -𝑝𝑝 1 * 𝐶𝐶 -1 2 |𝑟𝑟| |𝑝𝑝 1 | 𝑘𝑘 (II-35) 𝑝𝑝 1 , 𝑝𝑝 2 ∈ ℝ, 𝑝𝑝 2 = 𝑝𝑝 1 𝑟𝑟 1 1 -𝑝𝑝 1 𝐶𝐶 -1 + 𝑟𝑟 2 𝑝𝑝 1 𝐶𝐶 -1 (1 -𝑝𝑝 1 𝐶𝐶 -1 ) 2 |𝑟𝑟 1 + 𝑘𝑘 𝑟𝑟 2 | |𝑝𝑝 1 | 𝑘𝑘 𝑝𝑝 1 , 𝑝𝑝 2 ∈ ℝ, 𝑝𝑝 2 ≠ 𝑝𝑝 1 𝑟𝑟 1 1 -𝑝𝑝 1 𝐶𝐶 -1 + 𝑟𝑟 2 1 -𝑝𝑝 2 𝐶𝐶 -1 |𝑟𝑟 1 |𝑝𝑝 1 | 𝑘𝑘 + 𝑟𝑟 2 |𝑝𝑝 2 | 𝑘𝑘 | 𝑝𝑝 1 ∈ ℝ 𝑟𝑟 1 1 -𝑝𝑝 1 𝐶𝐶 -1 + 𝑟𝑟 2 𝐶𝐶 -1 1 -𝑝𝑝 1 𝐶𝐶 -1 �𝑟𝑟 1 + 𝑟𝑟 2 |𝑝𝑝 1 | � |𝑝𝑝 1 | 𝑘𝑘
A settling time solution can be found analytically for the first and last cases, but only numeric solution can be used for the others.

The time response depends on numerous parameters (𝐶𝐶 𝑂𝑂𝑂𝑂 , 𝑝𝑝 𝑂𝑂𝑂𝑂 , α, 𝑁𝑁 and 𝜆𝜆) and all of them could be optimized based on the closed-loop criteria. It gives a 5 𝑡𝑡ℎ order problem where a comparison criterion has to be defined. In practice, results are hard to visualize and verify.

For simplification proposes, the values 𝐶𝐶 𝑂𝑂𝑂𝑂 = 1/4 and 𝑝𝑝 𝑂𝑂𝑂𝑂 = 1/2 are chosen without further justification because they provide a good trade-off. The stability is ensured for 0 < α < 1.2 (6 5 ⁄ ) . Table II-2 shows the number of iterations required for convergence of the differential modes. The mode 4 is at the limit of stability and oscillates for α = 6/5. The curves show the minimum is in general between 0.9 and 1.1, and it goes up with N.

It happens because λ 1 goes down with 𝑁𝑁 and 1 𝑠𝑠𝑡𝑡 mode (𝜆𝜆 = 1) becomes dominant. The curves would shift slightly to the right for 𝑁𝑁 odd because the eigenvalues are slightly smaller in this case. A unitary α seems to be a global optimum, for which in most cases the performance will be only 10% worse than the optimum.

In this system, the convergence dynamics is less dependent on which modes are excited because their related 5% settling times are harmonized, more uniform, i.e. the modal settling times are almost the same. This is due to the additional parameters provided by the lead-lag corrector.

Diagonal Response

The dynamic behavior of the overall system will be simulated and the settling times compared with the ones predicted. A Multiple Input Multiple Output (MIMO) transfer function based model is defined and simulated using MathWorks MATLAB ® . In the simulations performed hereafter, the system starts in its expected equilibrium state with all the carriers well interleaved. Each mode is excited individually one after the other, from the common mode (mode 0) to the last one (mode 4) using the system eigenvectors (lines of the DFT matrix) as signal components. To do so, the disturbance signal 𝑫𝑫(𝐶𝐶) , composed of a sequence of orthogonal disturbances shown in Eq. (II-36), is summed with the corrector output.

𝑫𝑫(𝐶𝐶) = 1 2 𝑁𝑁 𝒗𝒗 0 𝐶𝐶 -4 + � 𝑟𝑟𝑒𝑒𝑎𝑎𝑙𝑙(𝑎𝑎 𝑚𝑚 𝒗𝒗 𝑚𝑚 ) 𝐶𝐶 -10𝑚𝑚-1 𝑀𝑀-1 𝑚𝑚=1 (II-36)
where 𝑎𝑎 𝑚𝑚 are complex coefficients.

II.4.3. General case stability criterion

As mentioned earlier, the proportional, integral, and proportional-integral are particular cases of the lead-lag controller. Eq. (II-37) shows the general stability criterion with its constraint for all correctors previously introduced, allowing to choose the α range where the system is stable to a given pole and zero couple. It should be noted this expression is not yet mathematically proven and acts only as a rule-of-thumb.

0 < α < 1 + 𝑝𝑝 𝑂𝑂𝑂𝑂 1 + 𝐶𝐶 𝑂𝑂𝑂𝑂 ⟺ 0 ≤ 𝐶𝐶 𝑂𝑂𝑂𝑂 ≤ 𝑝𝑝 𝑂𝑂𝑂𝑂 ≤ 1 𝑝𝑝 𝑂𝑂𝑂𝑂 -𝐶𝐶 𝑂𝑂𝑂𝑂 < 1 (II-37)
This expression is valid for the proportional controller (𝐶𝐶 𝑂𝑂𝑂𝑂 = 𝑝𝑝 𝑂𝑂𝑂𝑂 ), where the 𝐶𝐶 𝑂𝑂𝑂𝑂 and 𝑝𝑝 𝑂𝑂𝑂𝑂 compensate each other, and for the proportional-integral controller ( 𝑝𝑝 𝑂𝑂𝑂𝑂 = 1 ) also.

Moreover, it should be noted the integral controller, which is instable, no does not respect the second constraint (𝑝𝑝 𝑂𝑂𝑂𝑂 = 1, 𝐶𝐶 𝑂𝑂𝑂𝑂 = 0, then 𝑝𝑝 𝑂𝑂𝑂𝑂 -𝐶𝐶 𝑂𝑂𝑂𝑂 = 1).

Since the stability condition established and the dynamic responses verified, the implementation related issues will be discussed. This study aims to guarantee the implemented system behaves as predicted by the model developed previously.

Phase-delay target operator and wrong interleaving discussion

The principle of correction by comparison with the neighbors has been used previously in the literature for different purposes. For instance, in [START_REF] Bolloch | New masterless modular current-sharing technique for DC/DC parallel converters[END_REF] a current balance system equalizes the values of several inductor currents with the circular chain. With this principle applied for the interleaving, it should be noted the system equalizes the PD differences between the neighbors, not its absolute values. In the approach presented in [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF], the PD differences and their corrections are made in a relative manner to each local carrier.

In the approach presented here, the PDs are related to a global phase reference, as shown in As the expected target position 𝜃𝜃 � 1 is different from the 𝜃𝜃 1 position, i.e. the neighbors' position average, this system requires then additional operations such as those described in [START_REF] Grégoire | Real-Time Simulation of Interleaved Converters with Decentralized Control[END_REF], [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF], [START_REF] Phan | Modified Decentralized Control for Multiphase Converters[END_REF]. Issues are described in [START_REF] Broadmeadow | Self-organising technique for carrier synchronisation and phase offset distribution in modular, fault-tolerant converters[END_REF] as "ambiguous phase ordering" and "ambiguity in steady-state", linked with the error signal calculation. The "phase-delay target operator"

introduced here are able to evaluate the error and compute a new PD value despite the discontinuity.

To The sum of all the elements of the 𝝋𝝋 vector is null. This vector has always the same shape and can be generalized for any value of 𝑁𝑁. Any of its 𝑁𝑁 rotations 𝑺𝑺 𝑖𝑖 𝝋𝝋, 𝜆𝜆 = 0 … 𝑁𝑁 -1, is a valid vector, only the discontinuity is moved. The PD discontinuity is in between its non-null values, in this case between the 5 𝑡𝑡ℎ and the 1 𝑠𝑠𝑡𝑡 . Their signs define if the PD values are in an increasing or decreasing sequence. In the real system, each 𝜑𝜑 𝑖𝑖 value is evaluated locally in real time in the 𝜆𝜆 𝑡𝑡ℎ PDLC, taking into account the local and the neighbors' PDs. For this reason, special attention has to be paid to the initial values of the PDs to obtain a proper 𝝋𝝋 vector and avoid any mistake in the interleaving. Eq. ( 28) shows the solution for 𝜽𝜽 and 𝝋𝝋 related to With all these precautions, the PD discontinuity around 1 and 0 is overcome and considered as if it does not exist. In the simulations, the 𝝋𝝋 vector is kept constant and the second operator is applied using post-processing. In the case (a), as the number of elements is odd, the system seems to be well interleaved. In case (b), in contrast, where the number of elements is even, there is an evident interleaving problem because some PDs are coincident. This issue appears if the phase differences (1/N) are multiplied by any integer in between 2 and N. In the limit case, for any N value, all PDs are coincident, i.e. the phase differences are equal to 1 (or zero) and no interleaving effect is observed.

(a) (b) To ensure a correct interleaving, the 𝝋𝝋 vector has to contain only one discontinuity (±0.5 values). So special care has to be taken during start-up and reconfigurations to avoid going to these states. To do so, the PD values have to be in an ascending order where coincident values can be tolerated. Concerning a reconfiguration during operation, the bypass of a deactivated PDLC is simple because the system normally is already correctly interleaved and so ordered.

On the other hand, in order to anticipate an insertion of a "sleeping" PDLC, its PD has to be pre-positioned between its neighboring PDs to anticipate an insertion, such as it being active but not visible.

The start-up disposition of the PDs requires also special care to obtain correct interleaving. The expression on Eq. (II-45) generalizes the condition to obtain an ideal start-up condition that leads to correct interleaving arrangement, where the summation represents the sum of true statements. The cases that respects this condition are called a "Proper Interleaving

Arrangement" (PIA). It consists on having only one PD that is not in a non-strict growing sequence, i.e. the next PD greater than or equal to the local PD. In a PIA, the only elements that do not respect this rule are the ones close to the phase-delay discontinuity.

� 𝜃𝜃 𝑖𝑖 > 𝜃𝜃 𝑖𝑖𝑆𝑆𝑖𝑖𝑖𝑖𝑡𝑡 𝑖𝑖=𝑆𝑆 𝑖𝑖=1 = 1 � 𝜃𝜃 𝑖𝑖𝑆𝑆𝑖𝑖𝑖𝑖𝑡𝑡 = 𝜃𝜃 𝑖𝑖+1 , 𝜆𝜆𝑓𝑓 𝜆𝜆 < 𝑁𝑁 𝜃𝜃 𝑖𝑖𝑆𝑆𝑖𝑖𝑖𝑖𝑡𝑡 = 𝜃𝜃 1 , 𝜆𝜆𝑓𝑓 𝜆𝜆 = 𝑁𝑁 (II-45)
This concept can also be applied in steady-state arrangements. It can be noted that the

Convergence and steady-state value

It is well understood now that the steady-state value depends on the target vector 𝝋𝝋, which, in turn, depends on the vector 𝜽𝜽. The vector 𝝋𝝋 𝟎𝟎 is constant if the vector 𝜽𝜽 is properly chosen at the beginning, then the 𝝋𝝋(𝐶𝐶) signal is expressed in Eq. (II-46).

𝝋𝝋(𝐶𝐶) = 𝐶𝐶 /(𝐶𝐶 -1) 𝝋𝝋 𝟎𝟎 (II-46)
In this way, as this system is causal, the value 𝜽𝜽 converges in steady-state towards the value 𝜽𝜽 𝐬𝐬𝐬𝐬 that can be calculated using the Final Value Theorem (FVT) if all differential modes are damped and the 𝝋𝝋(𝐶𝐶) common mode is limited. The mathematical expression to calculate the steady-state value for this discrete system is shown in Eq. (II-47).

𝜽𝜽 𝐬𝐬𝐬𝐬 = lim 𝑘𝑘→∞ 𝜽𝜽 𝑘𝑘 = lim 𝑧𝑧→1 (𝐶𝐶 -1) 𝜽𝜽(𝐶𝐶) (II-47)
When in steady-state, 𝝋𝝋(𝐶𝐶) is constant and its common mode is null i.e. 𝑖𝑖𝑢𝑢𝜆𝜆(𝝋𝝋) = 0, the result in Eq. (II-48) is found by inserting Eq. (II-10) in Eq. (II-47) and solving.

𝜽𝜽 𝐬𝐬𝐬𝐬 = 𝜽𝜽 𝟎𝟎 ��� -𝑳𝑳 + 𝝋𝝋 𝟎𝟎 (II-48)
where 𝜽𝜽 𝟎𝟎 ��� = 1 𝑁𝑁 ⁄ 𝟏𝟏 𝑆𝑆𝑖𝑖𝑆𝑆 𝜽𝜽 𝟎𝟎 is a vector in which each element is the average value of 𝜽𝜽 𝟎𝟎 , and 𝑳𝑳 + is the pseudo-inverse of 𝑳𝑳. It should be noted that the matrix 𝑳𝑳 is singular because one eigenvalue is null and has no inverse. 𝑳𝑳 + can be evaluated using Eq. (II-49).

𝑳𝑳 + = 𝑾𝑾 𝜦𝜦 + 𝑾𝑾 -1 (II-49)
where 𝜦𝜦 + is formed from 𝜦𝜦 by taking the reciprocal of all the non-zero elements.

Eq. (II-48) reveals that, as expected, the steady-state depends on the start-up configuration 𝜽𝜽 𝟎𝟎 that provides also 𝝋𝝋 𝟎𝟎 , and, more importantly, on 𝑳𝑳 + that comes from the communication chain configuration matrix 𝑳𝑳. The steady-state value does not depend on the corrector 𝑪𝑪(𝐶𝐶). It should be noted that if 𝜽𝜽 𝐬𝐬𝐬𝐬 is outside the range 0 to 1, the correct result is obtained by applying the modulo operator to each value.

Reconfiguration and start-up simulations

As soon as the state of a PDLC changes, activated to be inserted into or deactivated to be removed from the chain, the remaining PDLCs have to modify their PDs to reach a new steady-state disposition where all the carriers are correctly interleaved again. The behavior of the several PDs in reaction to a reconfiguration event has to be studied carefully. A reconfiguration event excites the different modes, and the convergence towards the correct interleaving must be guaranteed. One can notice that these simulations of reconfiguration proposed here illustrate a real case of a decentralized interleaving operation.

The following simulations are performed using the lead-lag controller presented earlier.

As the phase-delay target operator cannot be implanted in Matlab when using annexed code, the 𝝋𝝋 vector is predefined to a convenient value using pre-processing, and the modulo operator is applied using post-processing. The reconfiguration responses are analyzed hereafter, first with the removal case, followed by the insertion case and then with the specific case studies of start-up.

II.7.1. PDLC removal

The simulation of a reconfiguration proposed here illustrates the cases of a PDLC removal (the PDLC is bypassed). The removal is the simplest reconfiguration case because the system is already interleaved and there is no initial value to care about.

II.7.2. PDLC insertion

The simulation of a reconfiguration event proposed here illustrates the cases of a PDLC insertion, i.e. a previously bypassed sleeping PDLC becoming visible to its neighboring PDLCs in the communication chain. This event also excites all the different modes, and the convergence towards the correct interleaving must be guaranteed. As a conclusion, to avoid wrong interleaving arrangements, at the beginning of a reconfiguration event, the 𝜽𝜽 vector has to respect a specific shape to generate a proper 𝝋𝝋 vector.

To do so, inactive PDLCs (bypassed) have to keep their PD computations active and correctly positioned in between their neighbors.

II.7.3. Convergence behavior vs. start-up positions

Now that reconfiguration events, insertion and removal cases, have been considered, it is important to focus on the stat-up of the system. Indeed, depending on the original positions of the carrier, the system may or not converge towards the appropriate interleaving. Several start-up cases have to be considered. In both cases the convergence is ensured and the settling times are slightly different.

Indeed, the 𝜽𝜽 values at the beginning determine the disturbed modes. In case (a), the differential modes 1, 2 and 3 are disturbed, while in case (b), the differential modes 2 and 4 are disturbed.

The correct steady-state interleaving is reached in both cases and the global settling times are similar because their modal settling times are quite uniform. A slow mode can be avoided to is the slower. As case (a) does not disturbs the mode 4, it would converge even if mode 4 is at the limit of stability.

The case (b) brings redundancy because more than one PD can be considered in phase opposition. It is an important feature for fault tolerant systems and gives more flexibility during start-up.

Freeze a carrier phase-delay

In some applications using the proportional controller [START_REF] Grégoire | Real-Time Simulation of Interleaved Converters with Decentralized Control[END_REF], [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF], [START_REF] Phan | Modified Decentralized Control for Multiphase Converters[END_REF], one PD is freeze (cannot change value) to overcome instability with α = 1. Other applications have specific requirements to avoid noise issues. For example, one PD is imposed to overcome the impact of the switching noise. An imposed carrier position may be required by applications using an external clock with synchronous requirements. This section introduces the eigenvalue study, the time response and its dynamic analysis for the case with one PD kept constant.

When the original position of a carrier is imposed and permanent, its local controller gain is null and its PD is no longer computed. The computations made inside its PDLC are turned off. It is equivalent to canceling the terms of the corresponding row of the 𝑳𝑳 N matrix.

The communication chain configuration with six carriers (𝑁𝑁 = 6), where θ 1 is constant, is named 𝑳𝑳 6-1 and expressed in Eq. (II-50).

(II-50)

The 𝑳𝑳 N-1 eigenvalues are real, ranging between -2 and 0. It is no longer circulant, so the diagonalization matrix 𝑾𝑾 is not the DFT matrix anymore. Then, the concepts of common mode and sinusoidal components are no longer valid. The eigenvalues of 𝑳𝑳 N-1 can be computed using Eq. (II-51) for any N value. This expression is not proven analytically.

λ 𝑖𝑖 = cos 𝜋𝜋 𝜆𝜆 𝑁𝑁 -1, 𝜆𝜆 = 0 … 𝑁𝑁 -1 (II-51)
There are two differences to the general case. The first one is all modes are simple, no double modes. As a result, 𝑀𝑀 is equal to 𝑁𝑁. The second difference is that λ 𝑖𝑖 is never equal to 2 (-2 < λ 𝑖𝑖 < 0). So the general stability criterion upper limit becomes non strict, i.e. α can be equal to the upper limit and the system is still stable with 𝑁𝑁 even, as shown in Eq. (II-52). Table II-3 presents the iteration number for convergence for the case with 𝑁𝑁 = 8 and one PD constant, for α equal to 1, 3/4 and 1/2. The last mode, mode 7 in this case, is stable and no longer in stability limit with α = 1 for any 𝑁𝑁 value. However, mode 1 is almost 4 times slower than the case where PD can change values.

II.8.2. Reconfiguration response

Multiple circular chains

Others circular chain arrangements can be used to improve redundancy or settling time. Eq. (II-53) is the open-loop discrete transfer function in the Z-domain.

𝜽𝜽(𝐶𝐶) ′ 𝜽𝜽(𝐶𝐶) = -�𝑘𝑘 1 𝑳𝑳 1 + 𝑘𝑘 2 𝑳𝑳 2 + ⋯ + 𝑘𝑘 𝐽𝐽 𝑳𝑳 𝐽𝐽 � 1 𝐶𝐶 -1 𝐶𝐶(z) = -� 𝑘𝑘 𝑗𝑗 𝑳𝑳 𝑗𝑗 𝐽𝐽=𝑆𝑆 j=1 1 𝐶𝐶 -1 𝐶𝐶(z) (II-53)
where 𝑘𝑘 j are the gains associated to the 𝑗𝑗 𝑡𝑡ℎ neighbor connection, i.e. the error related to the 𝑗𝑗 𝑡𝑡ℎ neighbors.

The gain 𝑘𝑘 j is normally a positive real number or equal to zero when the connection is not used or not available. 𝑳𝑳 j = 0.5�𝑺𝑺 -j + 𝑺𝑺 j � -𝑰𝑰 and its diagonal form is 𝜦𝜦 j = 𝑾𝑾 * 𝑳𝑳 j 𝑾𝑾 = 0.5�𝑼𝑼 -j + 𝑼𝑼 j � -𝑰𝑰. It shall be noted the terms 𝑗𝑗 in 𝑳𝑳 j and 𝜦𝜦 j are not powers of 𝑳𝑳 and 𝜦𝜦, even if The CLTF on Eq. (II-54) can also be written in a diagonal form such as in Eq. (II-55).

The diagonalization is made using the DFT matrix, as shown previously. It is known that all λ 𝑖𝑖 𝑗𝑗 are comprised between -2 and 0 (-2 ≤ λ 𝑖𝑖 𝑗𝑗 < 0). The general stability criterion for the previously presented controllers is shown in Eq. (II-57).

0 < � 𝑘𝑘 𝑗𝑗 𝐽𝐽=𝑆𝑆 j=1 < 1 + 𝑝𝑝 𝑂𝑂𝑂𝑂 1 + 𝐶𝐶 𝑂𝑂𝑂𝑂 ⟺ 0 ≤ 𝐶𝐶 𝑂𝑂𝑂𝑂 ≤ 𝑝𝑝 𝑂𝑂𝑂𝑂 ≤ 1 𝑝𝑝 𝑂𝑂𝑂𝑂 -𝐶𝐶 𝑂𝑂𝑂𝑂 < 1 α = 1,
𝑘𝑘 𝑗𝑗 ≥ 0 (II-57)

If pushed to the limit, this approach consists in using Full State Feedback (FSF) offering the possibility to implement any closed-loop behavior. At last, this approach is no longer considered because modular aspect would be lost and the complexity of the communication network, i.e. the number of connections involved in the global system, increases drastically.

II.9.1. Settling time

In the approach previously presented, the lower modes are normally slower because their related eigenvalues are closer to zero (smaller in absolute value). When using a second circular chain, other set of modes can be privileged. The controller can be simplified to 𝐶𝐶(𝐶𝐶) = 1 to compare this approach with the proportional controller previously presented. The modal pole values in the general case with 𝐶𝐶(𝐶𝐶) = 1 are shown in Eq. (II-58).

λ 𝐴𝐴𝑚𝑚 = 1 + � 𝑘𝑘 𝑗𝑗 λ 𝑚𝑚 𝑗𝑗 𝐽𝐽=𝑆𝑆 j=1 = 1 + 𝑘𝑘 1 λ 𝑚𝑚 1 + 𝑘𝑘 2 λ 𝑚𝑚 2 + ⋯ 𝑘𝑘 𝐽𝐽 λ 𝑚𝑚 𝐽𝐽 , 𝜆𝜆 = 0 … 𝑀𝑀 -1 (II-58)
where λ 𝑚𝑚 are the diagonal elements of 𝜦𝜦 and 𝑘𝑘 𝑗𝑗 is the gain associated with the 𝑗𝑗 𝑡𝑡ℎ neighbors connection.

To illustrate this, a system with nine PDLCs (𝑁𝑁 = 9, 𝑀𝑀 = 5) with a second circular chain is proposed, where each PDLC is communicating with the third neighbors in the chain.

For the proportional controller 𝐶𝐶(𝐶𝐶) = 1, the modal poles are defined in Eq. (II-59).

λ 𝐴𝐴𝑚𝑚 = 1 + 𝑘𝑘 1 λ 𝑚𝑚 1 + 𝑘𝑘 3 λ 𝑚𝑚 3 , 𝜆𝜆 = 1 … 𝑀𝑀 -1 (II-59)
This expression can be compared with the case where only the first neighbor circular chain was used, shown in Eq. ( 22). It can be noted 𝑘𝑘 1 is equivalent to α and λ 𝑚𝑚 1 is equal to λ 𝑚𝑚

itself. An additional freedom degree linked with the third neighbor connection 𝑘𝑘 3 can be noted.

Table 1 shows the number of iterations required for convergence of the several differential modes in the cases of Figure II-24. The table shows the modes 1, 2 and 4 go faster as 𝑘𝑘 1 goes down to zero and 𝑘𝑘 3 goes up to 2/3. However, the mode 3 slows down and become uncontrollable when 𝑘𝑘 1 = 0 because λ 3 3 = 0, i.e. λ A3 is not dependent on 𝑘𝑘 3 .

II.9.2. Convergence behavior

A particular convergence behavior can be noted when 𝑘𝑘 3 is privileged over 𝑘𝑘 1 . The PDs reach the expected interleaving very fast in the case (a). However, in case (b)

the PDs reach the expected interleaving very fast with their third neighbor because 𝑘𝑘 3 (𝑗𝑗 = 3) is privileged. As 𝑁𝑁 = 9, three well interleaved groups (𝑁𝑁/𝑗𝑗) are formed. When the remaining disturbed modes are damped, mode 3 in this case, all PDs are well interleaved.

II.9.3. Reconfiguration

This special circular chain is not suitable for reconfiguration. When a PDLC is bypassed, besides sending the previous and next neighbor's PDs, it has to maintain the circular chain with the 𝑗𝑗 𝑡𝑡ℎ as well. Nevertheless, this is not feasible with the circular chain. It should be noted that changing the topology of the communications network due to reconfiguration event requires for each case a complete and dedicated stability study.

Shared wire generalization and discussion

The modeling techniques shown here can also be extrapolated to reveal the stability criteria of a hypothetical system using the shared wire technique. In this case, each LC compares the average value of the PDs shared on a single wire with its local PD. All error can be compute by the specific operator 𝑳𝑳 shown in Eq. (II-60), that is a circulant matrix, and the eigenvalues are revealed.

𝑳𝑳 = 𝑾𝑾𝚲𝚲𝑾𝑾 * = 1 𝑁𝑁 𝟏𝟏 𝑆𝑆𝑖𝑖𝑆𝑆 -𝑰𝑰 λ 𝑖𝑖 = � 0, 𝜆𝜆 = 0 -1, 𝑜𝑜𝑑𝑑ℎ𝑒𝑒𝑟𝑟𝑤𝑤𝜆𝜆𝑖𝑖𝑒𝑒 (II-60)
It shall be noted that the common mode cannot be controlled because its first eigenvalue (𝜆𝜆 = 0) is null and all the differential modes have the same transient response because all related eigenvalues are equal.

All modes have the same behavior with the shared wire approach because a disturbance applied in any LC will be seen in an equal manner by all LCs, while in the circular chain, the closest connection LCs will perceive the disturbance earlier than the others.

Conclusions

In this chapter, a complete analytical study of a digital iterative distributed interleaving The ability to quickly converge towards the expected steady-state has been demonstrated both for the particular case of system reconfiguration during operation with the removal or the insertion of a local controller and for the case of system start-up with different phase-delay for the carriers. Guidelines for the implementation of the PDLC are provided, ensuring correct steady-state disposition. Recommendations for the reconfiguration and startup dispositions are also provided with an analytical expression of the dispositions reached after convergence.

The stabilizing effect of using a constant position for one carrier has been also highlighted. In that particular case, an unconditional stability is obtained at the cost of a loss of dynamic performance, even when using the best value for the convergence coefficient. The effect of multiple circular chains is also analyzed and revealed as well as the general case with all elements contributing on a single shared wire.

The robustness of this distributed interleaving strategy is limited due to the shared line needed to share the phase-delay reference, i.e. the shared clock. This also adds the requirement either to provide of an external clock or one LC must send its clock to the others LCs. In the second case, one element would have a feature different to the others, resulting in a singular element and consequently an additional SPOF.

In case of detection of fault occurrence leading to a defective PD communication line, the system can reconfigure to keep constant the phase-delay of the LC that cannot receive the correct information. However, the shared clock remains a concern in terms of SPOF. For that reason, this approach is not recommended for system requiring high availability and mission continuity in case of fault occurrence.

Triangular carrier self-alignment study

The triangular carrier self-alignment modular approach studied in this chapter was first described by COUSINEAU in [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF]. It uses only analog circuits to generate interleaved triangular carriers. In this approach, a given number 𝑁𝑁 of Triangular Carrier Generators (TCG), are connected in a circular chain, where each TCG receives the neighboring TCG's triangular waveforms and send them back its own triangular waveform. This approach is modular and suitable to reconfiguration, as inactive TCG bypass its connections in the chain. This approach is different to the numeric interleaving approach previously presented in chapter II. Then a summary list with advantages and disadvantages is given.

Advantages:

-No global clock required; -Full modularity and no SPOF; -No phase delay discretization.

Disadvantages:

-Triangular signal shape changes during reconfiguration disturbing the duty-cycle / PWM signal relation; -Noise immunity issues on analog connections; -Matching issues on triangular signal (DC level, peak-to-peak amplitude, slew-rate symmetry, frequency).

This system has been implemented in real applications [START_REF] Cousineau | Fully masterless control of parallel converter[END_REF] using an structure based on current sources. The experimental results proof its effectiveness. Nevertheless, the complete modelling and stability study has not been already proposed and verified. This study is now detailed hereafter. Besides providing the stability criterion, closed-loop performance constraints (settling time vs. static error) are shown and a settling time optimization procedure is proposed.

A limited study reveals the mismatch (frequency, DC level) effect on static error.

Working principle and modeling

The -𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 (𝑑𝑑) -𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖 (𝑑𝑑) -𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑆𝑆 (𝑑𝑑) As the slew rate are considered equal and constant, the PD changes at each commutation of 𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚 , i.e. each change of the slope sign, and is kept constant until the next commutation. The resulting ∆𝑑𝑑 𝑉𝑉 𝑡𝑡𝑡𝑡𝑡𝑡 (𝑑𝑑) is similar to a continuous-time waveform reconstruction from a sample sequence ∆𝑑𝑑 𝑉𝑉 𝑡𝑡𝑡𝑡𝑡𝑡 𝑘𝑘 using a zero-order hold, such as shown in Eq. (III-3), where 𝑟𝑟𝑒𝑒𝑐𝑐𝑑𝑑( ) is the rectangular function.

∆𝑑𝑑(𝑑𝑑) = � ∆𝑑𝑑 𝑉𝑉 𝑡𝑡𝑡𝑡𝑡𝑡 𝑘𝑘 ∞ 𝑘𝑘=-∞ 𝑟𝑟𝑒𝑒𝑐𝑐𝑑𝑑 � 2 𝑑𝑑 -𝑖𝑖 0 /2 -𝑘𝑘 𝑖𝑖 0 𝑖𝑖 0 � (III-3)
The signal ∆𝑑𝑑 𝑉𝑉 𝑡𝑡𝑡𝑡𝑡𝑡 (𝑑𝑑) can be modelled as the output of a linear time-invariant system with impulse response equal to a rectangular function, where the inputs are a sequence of Dirac functions scaled to the sampled values. The sampling frequency is equal to 2 𝑓𝑓 0 because each period 𝑖𝑖 0 induces two samples.

A normalized PD 𝜃𝜃 is evaluated with Eq. (III-4), resulting in values ranging between 0 and 1.

𝜃𝜃 𝑘𝑘 = ∆𝑑𝑑 𝑉𝑉 𝑡𝑡𝑡𝑡𝑡𝑡 𝑘𝑘 𝑖𝑖 0 (III-4)
Now the similarity of the obtained PD signal with a discrete system representation is shown, the input sampled values expression has to be found to complete the model. (III-5).

III.1.2. Single TCG model

𝜃𝜃 � 𝑘𝑘 = 0.5 �𝜃𝜃 𝑃𝑃 𝑘𝑘+1 + 𝜃𝜃 𝑆𝑆 𝑘𝑘 � + 𝜑𝜑 𝑘𝑘 (III-5)

where 𝜑𝜑 𝑘𝑘 represents the PD target operator result required to handle the PD discontinuity as discussed in chapter II.

The local PD 𝜃𝜃 𝑘𝑘 is used to evaluate the local PD error 𝜀𝜀 𝜃𝜃 𝑘𝑘 , expressed in Eq. (III-6).

𝜀𝜀 𝜃𝜃 𝑘𝑘 = 𝜃𝜃 � 𝑘𝑘 -𝜃𝜃 𝑘𝑘 (III-6)
Now, it must be considered the discrete transfer function 𝐶𝐶(𝐶𝐶) that establishes the relationship between the correction applied for the next iteration ∆𝜃𝜃 and the error 𝜀𝜀 𝜃𝜃 . The expression of 𝐶𝐶(𝐶𝐶) can be determined analyzing the waveforms around to the commutation instant using a geometric approach as demonstrated in Annex B. The result is shown in Eq.

(III-7) with its validity conditions to guarantee the geometric consistency. The corrector 𝐶𝐶(𝐶𝐶)

is equivalent to a proportional gain 𝛼𝛼 called here "convergence coefficient"

𝐶𝐶(𝐶𝐶) = 𝛥𝛥𝜃𝜃(𝐶𝐶) 𝜀𝜀 𝜃𝜃 (𝐶𝐶) = 𝛼𝛼 = 4 𝛽𝛽 1 + 2 𝛽𝛽 , 𝜃𝜃 𝑃𝑃 𝑘𝑘+1 ≤ 𝜃𝜃 𝑘𝑘 ≤ 𝜃𝜃 𝑆𝑆 𝑘𝑘 𝜃𝜃 𝑆𝑆 𝑘𝑘 -𝜃𝜃 𝑃𝑃 𝑘𝑘+1 2 ≤ 0.5 -0.5 < 𝛽𝛽 < +∞ ⇔ -∞ < 𝛼𝛼 < 2 (III-7)
It should be noted that this expression is valid even beyond these limits. If -0.5 < 𝛽𝛽 < 0, 𝛼𝛼 is negative, resulting in a positive feedback, so this range shall be rejected. If 𝛽𝛽 → +∞, 𝛼𝛼 tends to 2 and the operation is equivalent of using comparators, such as in [START_REF] Xiao | Modular interleaved carrier generator using a straightforward implementation method[END_REF].

Eq. (III-8) gives the new PD obtained 𝜃𝜃 𝑘𝑘+1 reached by the local triangular signal at the iteration 𝑘𝑘 + 1. It is made up of the previous PD plus the correction applied and a disturbance parameter 𝜃𝜃 𝑘𝑘 . The disturbance parameter is a consequence of the triangular waveform imperfections and will be discussed latter in III.7. To solve this problem, the modelling of the overall system is required, including the whole closed chain of communications.

𝜃𝜃 𝑘𝑘+1 = 𝜃𝜃 𝑘𝑘 + 𝛥𝛥𝜃𝜃 𝑘𝑘 + 𝜃𝜃 𝑘𝑘 (III-8)

III.1.3. Overall system modelling

A system with a generic number 𝑁𝑁 of LCs is now considered. The LCs in circular chain are numbered from 1 to 𝑁𝑁 in the next direction, so the PD values are numbered from 𝜃𝜃 1 to 𝜃𝜃 𝑆𝑆 , and can be represented by a column matrix 𝜽𝜽 (in bold in the equations). For computation purpose, the Previous PD vector 𝜽𝜽 𝑃𝑃 and the Next PD vector 𝜽𝜽 𝑆𝑆 are defined in Eq. (III-10) using the circular shift matrix 𝑺𝑺 and its conjugate transposed 𝑺𝑺 * , equal to its transposed 𝑺𝑺 𝑇𝑇 because 𝑺𝑺 is real.

𝜽𝜽 𝑃𝑃 = 𝑺𝑺 𝜽𝜽 𝜽𝜽 𝑆𝑆 = 𝑺𝑺 * 𝜽𝜽 (III-10)
The shift matrix 𝑺𝑺 for the case with 𝑁𝑁 = 4 is shown in Eq. (III-11).

𝑺𝑺 = � 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 � (III-11)
The matrix form of Eq. (III-5), (III-6) and (III-8) are shown in Eq. (III-12), (III-13) and

(III-14), respectively.

𝜽𝜽 � 𝑘𝑘 = 0.5 �𝜽𝜽 𝑃𝑃 𝑘𝑘+1 + 𝜽𝜽 𝑆𝑆 𝑘𝑘 � + 𝝋𝝋 𝑘𝑘 (III-12)

𝜺𝜺 𝜃𝜃 𝑘𝑘 = 𝜽𝜽 � 𝑘𝑘 -𝜽𝜽 𝑘𝑘 (III-13)

𝜽𝜽 𝑘𝑘+1 = 𝜽𝜽 𝑘𝑘 + 𝛼𝛼 𝜺𝜺 𝜃𝜃 𝑘𝑘 + 𝒅𝒅 𝑘𝑘 (III-14)
where 𝝋𝝋 𝑘𝑘 is the target operator result vector and 𝒅𝒅 𝑘𝑘 is the disturbance vector. The closed-loop discrete transfer function of the system is shown in Eq. (III-17) with the initial condition 𝜽𝜽 𝟎𝟎 , where 𝜽𝜽 𝟎𝟎 is a column vector filled with the starting PD values and 𝑰𝑰 is the identity matrix.

𝜽𝜽(𝐶𝐶) = (𝐶𝐶𝑰𝑰 -𝑨𝑨) -1 �𝐶𝐶𝑰𝑰 𝜽𝜽 𝟎𝟎 + (𝑰𝑰 -𝛼𝛼 0.5 𝑺𝑺 ) -1 �𝛼𝛼 𝝋𝝋(𝐶𝐶) + 𝒅𝒅(𝐶𝐶)�� (III-17)
The system stability can be verified by diagonalization followed by root-analysis. The system diagonalization reveals the several decoupled dynamics, called the modal responses, which help to determine the response of the overall system to any external excitation. The whole system is stable if each of the modal dynamics are stable.

III.1.4. Model validity domain

The model validity domain determines the operational conditions where this study results are valid, i.e. stability criterion and settling time. Two main concerns have to be discussed, the model itself and the corrector transfer function.

The local PD correction 𝛥𝛥𝜃𝜃 is not always proportionally dependent on the error 𝜀𝜀 𝜃𝜃 . As mentioned previously, the difference of the neighbors' triangular carriers 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 is superimposed to the local carrier levels 𝑉𝑉 𝑚𝑚 and 𝑉𝑉 𝑂𝑂 . Considering the neighbor signals as static, i.e. no correction applied to them, a mapping of the correction obtained as a function of all possible combinations of neighbor PDs differences named 𝛥𝛥𝜃𝜃 𝑃𝑃,𝑆𝑆 = 𝜃𝜃 𝑆𝑆 -𝜃𝜃 𝑃𝑃 , the error 𝜀𝜀 𝜃𝜃 and the particular case with gain 𝛼𝛼 = 0.5 is shown in Figure III-8. As a conclusion, the corrector transfer function 𝐶𝐶(𝐶𝐶) is valid around a steady-state operation point considering limited disturbances in some particular cases, e.g. 𝛥𝛥𝜃𝜃 𝑃𝑃,𝑆𝑆 close to zero or close to 1. Modal excitations and reconfigurations involving small disturbances can be simulated with high confidence. However the results for the start-up case may be less reliable.

Change of basis and modal transfer functions

The change of basis allows to decompose the original coupled system into several independent monovariable systems. It requires rewriting the system's equations in a diagonal The system's equation, shown in Eq. (III-17), after diagonalization is made up using 𝑾𝑾 and shown in Eq. (III-20).

𝜽𝜽 * (𝐶𝐶) = {𝐶𝐶𝑰𝑰 -𝜦𝜦 𝐴𝐴 } -1 {𝐶𝐶𝜽𝜽 𝟎𝟎 * + (𝑰𝑰 -𝛼𝛼 0.5 𝑼𝑼 ) -1 [𝛼𝛼 𝝓𝝓 * (𝐶𝐶) + 𝒅𝒅 * (𝐶𝐶)]} (III-20)
where 𝜦𝜦 𝐴𝐴 is the closed-loop diagonal eigenvalue matrix, shown in Eq. (III-21).

𝜦𝜦 𝑨𝑨 = 𝑾𝑾 * 𝑨𝑨𝑾𝑾 = (𝑰𝑰 -𝛼𝛼 0.5 𝑼𝑼 ) -1 [(1 -𝛼𝛼) 𝑰𝑰 + 𝛼𝛼 0.
𝜃𝜃 * 𝑖𝑖 (𝐶𝐶) = 𝐶𝐶 𝐶𝐶 -λ 𝐴𝐴𝑖𝑖 𝜃𝜃 0 * 𝑖𝑖 + 1 𝐶𝐶 -λ 𝐴𝐴𝑖𝑖 1 1 -𝛼𝛼 0.5 λ 𝑖𝑖 �𝛼𝛼 𝜑𝜑 * 𝑖𝑖 (𝐶𝐶) + 𝜃𝜃 * 𝑖𝑖 (𝐶𝐶)� , 𝜆𝜆 = 0 … 𝑁𝑁 -1 (III-22)
It can be noted that each closed-loop eigenvalue corresponds to a modal closed-loop pole. The Eq. (III-23) shows the analytical expression of 𝜆𝜆 𝐴𝐴𝑖𝑖 as a function of the gain 𝛼𝛼 and 𝜆𝜆 𝑖𝑖 .

𝜆𝜆 𝐴𝐴𝑖𝑖 = 1 -𝛼𝛼 (1 -0.5 𝜆𝜆 𝑖𝑖 * ) 1 -𝛼𝛼 0.5 𝜆𝜆 𝑖𝑖 𝜆𝜆 = 0 … 𝑁𝑁 -1 (III-23)
The 𝑺𝑺 eigenvalues are known and shown in. Eq. (III-24) for any value of 𝑁𝑁.

λ 𝑖𝑖 = exp �𝑗𝑗 2 𝜋𝜋 𝜆𝜆 𝑁𝑁 � = 1∠ 2 𝜋𝜋 𝜆𝜆 𝑁𝑁 𝜆𝜆 = 0 … 𝑁𝑁 -1 (III-24)

Stability Concern

The corrector has only one degree of freedom, the gain 𝛼𝛼 . The common mode eigenvalue does not depends on 𝛼𝛼 and is equals to one (𝜆𝜆 𝐴𝐴0 = 1). To guarantee stability and convergence in this discrete system, all closed-loop poles of the differential modes (i ≠ 0) have to be located inside the unit circle, i.e. their eigenvalues' absolute values must be less than 1.

The stability condition with its constraints are shown in Eq. (III-25). This result is valid for any 𝑁𝑁 value.

|λ 𝐴𝐴𝑖𝑖 | < 1 ⇔ 0 < α < 2 ⇔ 0 < β < +∞, 𝜆𝜆 = 1 … 𝑁𝑁 -1 (III-25)
The demonstration is provided in Annex C.

In order to illustrate with an example, the root locus for a system with 𝑁𝑁 = 8 are shown Based on the z-domain model, this plot confirms that a limited positive gain 𝛽𝛽 leads to a stable system. If comparators are used (𝛽𝛽 → +∞), all differential modes are in stability limit (all poles placed on the unitary circle) and oscillates.

In Chapter II, the open-loop modal transfer functions have real eigenvalues that appeared as gain factors, so only one root locus exists and all pole-zero are located there, independently of the 𝑁𝑁 value. However, in the present case, such simplicity cannot be observed.

The closed-loop eigenvalues can be expressed as a function of the matrix 𝑺𝑺 eigenvalues. The matrix 𝑺𝑺 eigenvalues are complex, their absolute values are all equal to 1, but their arguments are different, such as 𝜆𝜆 𝑖𝑖 = 1∠𝜌𝜌, where 𝜌𝜌 depends on 𝑁𝑁 and 𝜆𝜆.

𝜆𝜆 𝐴𝐴𝑖𝑖 |𝛼𝛼 = 2 = 𝜆𝜆 𝑖𝑖 * ⇒ |𝜆𝜆 𝐴𝐴𝑖𝑖 | |𝛼𝛼 = 2 = |𝜆𝜆 𝑖𝑖 * | = |𝜆𝜆 𝑖𝑖 | = 1, 𝜆𝜆 = 0 … 𝑁𝑁 -1 (III-26)
It should be noted that the poles' placement presents a symmetry with respect to the real axis. The symmetric poles correspond to the double modes, where 𝑤𝑤 𝑆𝑆-𝑖𝑖 = 𝑤𝑤 𝑖𝑖 * and λ 𝐴𝐴(𝑆𝑆-𝑖𝑖) = λ 𝐴𝐴𝑖𝑖 * . To avoid showing redundant information, the modal index 𝜆𝜆 = 0 … 𝑀𝑀 -1 can be used, where 𝑀𝑀 is defined as in the previous study.

III.3.1. Settling time and voltage gain design

The settling time depends on the triangular signal frequency 𝑓𝑓 0 and on the number of iterations required to reject a disturbance. The value of the triangular signal frequency is imposed by the application.

The number of iterations for convergence can be computed, for example, by the number 𝑘𝑘 of iterations necessary to reduce the absolute value of each differential mode natural (homogeneous) response 𝜃𝜃 * 𝑚𝑚ℎ to less than 5% of its initial value 𝜃𝜃 0 * 𝑚𝑚 . The modal natural (homogeneous) response 𝜃𝜃 * 𝑚𝑚ℎ shown in Eq. (III-27) can be found by applying the inverse Ztransform to the first term of Eq. (III-22), where 𝜆𝜆 is the mode number and ℎ is the homogeneous marker.

𝜃𝜃 * 𝑚𝑚ℎ (𝑘𝑘) = λ Am k 𝜃𝜃 0 * 𝑚𝑚 = |λ Am | k �1∠φ λ Am � k 𝜃𝜃 0 * 𝑚𝑚 , � k ≥ 0 λ Am = |λ Am | ∠φ λ Am 𝜆𝜆 = 1 … 𝑀𝑀 -1 (III-27)
Eq. ( 24) shows the general formula for the number of iterations derived from Eq. (III-28).

𝑘𝑘 5%_m = 𝑙𝑙𝑜𝑜𝑙𝑙(0.05) 𝑙𝑙𝑜𝑜𝑙𝑙(|λ Am |) , 𝜆𝜆 = 1 … 𝑀𝑀 -1 (III-28)
Table III-1 shows the number of iterations required for convergence for the several differential modes in the case 𝑁𝑁 = 8. Note that no mode converges when α = 2. The minimum value using the eigenvalue least squares criterion is found with α = 0.8, while the minimum value using the k5% least squares criterion is found with α = 0.95. The least squares of k5% criterion is preferable because the response is more uniform due to the smaller response time dispersion. As a conclusion, for 𝑁𝑁 = 8, the optimal voltage gain 𝛽𝛽 would be in the range 0.4 and 0.5.

Considering the first model with only the local loop, the case 𝛼𝛼 = 1 (𝛽𝛽 = 0.5) corresponds to the one shoot response, and is similar to the digital system described previously.

However, the overall digital implementation is not stable in this condition, while the Triangular Carrier Self-Alignment seems to be stable, according to the proposed model.

III.3.2. Eigenvalues and stability vs. number of active LCs

This system has the intrinsic ability to reconfigure, so the eigenvalues have to be All λ A0 related to the common mode are constant, equal to 1 and not shown. All differential modes are controllable because their eigenvalues depend on the parameter 𝛼𝛼. All differential modes are double and have a pole symmetrical to the imaginary axis (its conjugate), except when 𝑁𝑁 is even, where the mode 𝑁𝑁/2 is a single mode.

A reconfiguration event is the modification during operation of the number 𝑁𝑁 of active LCs. Non-active LCs are bypassed, i.e. the chain of communication remains closed, and become invisible to active LCs. As seen before, all eigenvalues depend on a single convergence factor 𝛼𝛼, and a trade-off has to be made. On the other hand, when a reconfiguration is made, 𝛼𝛼 remains the same, but the eigenvalues change.

The 5% response convergence speed should also be optimal when 𝑁𝑁 varies. However the number of active modules is unknown and all local controllers have to be equal by definition.

To simplify the design, the same 𝛼𝛼 is used in all cases and the relative response degradation is The curves show the minimum for 𝛼𝛼 is in general between 0.7 and 0.9, and it goes up with 𝑁𝑁. The least squares of 𝑘𝑘 5% give a best time response trade-off. The optimum is much more dependent on 𝑁𝑁 than in the previous case, being between 0.65 and 1.05 in the range of 𝑁𝑁

shown. The simulations presented here after are made using 𝑁𝑁 = 8 ± 1, so 𝛼𝛼 is chosen around the optimized value to 𝑁𝑁 = 8 using the least squares of λ A and the least squares of 𝑘𝑘 5% , being 0.8 and 1.0, respectivelly.

In this approach, the corrector is of type proportional represented by the Convergence Coefficient 𝛼𝛼. So, other than the transient response, 𝛼𝛼 impacts the static gain and consequently the steady-state error. It would be natural to choose a higher 𝛼𝛼 value to further reduction of the steady-state error. The disturbance impact in the steady-state error will be discussed in III.7.

Diagonal response

The dynamic behavior of the overall system has been simulated and the settling time compared with the one predicted. A space state system based model is defined and simulated using MathWorks MATLAB ® . In the simulations performed hereafter, the system starts in its expected equilibrium state with all the carriers well interleaved. Each mode is excited individually one after the other, from the common mode (mode 0) to the last one (mode 4) using the system eigenvectors (lines of the DFT matrix) as components of the disturbance signal 𝒅𝒅.

Reconfiguration simulations

As soon as a TCG state changes (activated/deactivated), the active TCGs evolve their triangular signal PDs to reach a new steady-state arrangement where all the carriers are correctly interleaved again. The model is used in reconfiguration simulations and its responses are analyzed hereafter, first with the removal case, then the insertion case. The simulations show the differential modes are excited at the beginning and the responses have the same dynamics revealed previously on Table III-1.

III.5.1. TCG removal

The simulation of a reconfiguration proposed here illustrates the cases of a TCG removal (one TCG is bypassed). The removal is the simplest reconfiguration case because the system is already interleaved and there is no initial value to care about.

III.5.2. TCG insertion

The insertion reconfiguration is optimal when the reactivated TCGs are pre-positioned in between its neighbors, not necessarily in the middle. As a result, the errors are small, corrector non-linear behavior is avoided and settling time is known. The model proposed in this work is not able to reveal what happens when the system is outside the linear zone. However, it can be thought that if the reactivated TCGs is not too far from the linear zone, i.e. close enough to the area bounded by the neighbors, its neighbors are likely to be in the same condition, so the system shall converge to the correct interleaved state.

For large differences, no conclusion can be stated due to the system nature. There is a risk of convergence to an incorrect or a non-usual interleaved arrangement. It can only be verified through simulation and practical implementation. For that reason, in any cases, a disabled TCG will always be pre-positioned in between its two neighbors.

Convergence and steady-state value

The discrete time transfer function can be used to reveal the PDs' steady-state arrangement to a given start condition if the system's start condition (all PD errors) is in a linear region. To do so, a valid target vector 𝝋𝝋 required by the model has to be computed from the PD initial values 𝜽𝜽 𝟎𝟎 at start-up. Then, the PDs' steady-state values 𝜽𝜽 𝐬𝐬𝐬𝐬 can be calculated using the Final Value Theorem (FVT) if all differential modes are damped. The result in Eq. (III-29) is found by inserting Eq. (III-17) into Eq. (II-47) and solving. The steady-state depends on the start-up configuration 𝜽𝜽 𝟎𝟎 that provides 𝝋𝝋, and, more importantly, on 𝑳𝑳 + , related to the circular communication chain configuration. As a result, the gain 𝛼𝛼 and the delay on 𝜽𝜽 𝐏𝐏 connection do not affect 𝜽𝜽 final values.

𝜽𝜽 𝐬𝐬𝐬𝐬 = 𝜽𝜽 𝟎𝟎 ��� -𝑳𝑳 + �𝝋𝝋 + 1 𝛼𝛼 𝒅𝒅� (III-29)
Again, a term related to the disturbance input 𝒅𝒅 appears in the expression. This expression is valid if 𝒅𝒅(𝐶𝐶) is constant, i.e. 𝒅𝒅(𝐶𝐶) = 𝒅𝒅 𝑢𝑢(𝐶𝐶), where 𝑢𝑢(𝐶𝐶) is the step function, and the common mode of 𝒅𝒅 is null, i.e. the sum of all elements of 𝒅𝒅 is null (𝒅𝒅 * 0 = 0), what prevents 𝜽𝜽 from sliding permanently.

It can be highlighted, like in any control system using proportional gain, the interest of increasing the corrector gain to reduce the disturbance impact in the steady-state values. The relationship between the disturbance 𝒅𝒅 and the steady-state local error 𝜺𝜺 𝜃𝜃 𝐬𝐬𝐬𝐬 is revealed in the same way in Eq. (III-30).

𝜺𝜺 𝜃𝜃 𝐬𝐬𝐬𝐬 = - 1 𝛼𝛼 𝒅𝒅 (III-30)
To choose the minimum gain 𝛼𝛼, the expression of 𝒅𝒅 has to be analyzed. The term 𝒅𝒅 is related to all existing disturbances in the system, such as frequency mismatch, triangular wave mismatch, and electronic circuit mismatch.

To obtain 𝜃𝜃 ̅ from Δ𝑉𝑉 0 and 𝛿𝛿𝑣𝑣 dm , the term 𝜃𝜃 ̃ has to be supressed. It can be done by computing the PD difference between two non-consecutive iterations 𝛿𝛿𝜃𝜃, as shown in Eq.

(III-32).

𝛿𝛿𝜃𝜃 = 𝜃𝜃 𝑘𝑘+2 -𝜃𝜃 𝑘𝑘 = 𝜃𝜃 𝑘𝑘+1 + 𝜃𝜃 𝑘𝑘 = 2 𝜃𝜃 ̅ ∴ 𝜃𝜃 ̅ = ½ 𝛿𝛿𝜃𝜃 = 𝛿𝛿𝑖𝑖/𝑖𝑖 0 = 𝛿𝛿𝑣𝑣 dm Δ𝑉𝑉 0 (III-32)
Similarly, to obtain 𝜃𝜃 ̃ from Δ𝑉𝑉 0 and 𝛿𝛿𝑣𝑣 dm , the term 𝜃𝜃 ̅ has to be suppressed. It can be done by computing the difference between two consecutive iteration PD differences 𝛿𝛿𝜃𝜃, as shown in Eq. (III-33).

𝛿𝛿𝜃𝜃 = (𝜃𝜃 𝑘𝑘+2 -𝜃𝜃 𝑘𝑘+1 ) -(𝜃𝜃 𝑘𝑘+1 -𝜃𝜃 𝑘𝑘 ) = 𝜃𝜃 𝑘𝑘+1 -𝜃𝜃 𝑘𝑘 = 2 𝜃𝜃 ̃ ∴ 𝜃𝜃 ̃= ½ 𝛿𝛿𝜃𝜃 = 2 𝛿𝛿𝑣𝑣 cm 𝑉𝑉 DC0 (III-33)
As a general rule, all mismatches impacting the frequency (e.g. average slew rate) can be generalized on the 𝜃𝜃 ̅ value, while the mismatches impacting the symmetry (e.g.

positive/negative slew rate) will impact the components 𝜃𝜃 ̃i.

The expressions in Eq. (III-34) shows the relations between the disturbance 𝜃𝜃 ̅ to a frequency deviation 𝛿𝛿𝑓𝑓 through a small signal approximation, where 𝑖𝑖 and 𝑖𝑖 0 are the local and reference carrier periods, respectively, and 𝑓𝑓 and 𝑓𝑓 0 their frequencies, respectively. The average local error 𝜀𝜀 𝜃𝜃 ��� is also shown in Eq. (III-34).

1 + 𝛿𝛿𝜃𝜃 = 1 + 2 𝜃𝜃 ̅ = 𝑖𝑖 𝑖𝑖 0 = 𝑓𝑓 0 𝑓𝑓 0 + 𝛿𝛿𝑓𝑓 ≅ 1 - 𝛿𝛿𝑓𝑓 𝑓𝑓 0 𝑖𝑖 = 1 𝑓𝑓 ⁄ 𝑖𝑖 0 = 1 𝑓𝑓 0 ⁄ 𝑓𝑓 = 𝑓𝑓 0 + 𝛿𝛿𝑓𝑓 ∴ 𝜃𝜃 ̅ ≅ - 1 2 𝛿𝛿𝑓𝑓 𝑓𝑓 0 ∴ 𝜀𝜀 𝜃𝜃 ��� ≅ 1 2𝛼𝛼 𝛿𝛿𝑓𝑓 𝑓𝑓 0 (III-34)
To guarantee the validity of the model, the disturbance common mode 𝒅𝒅 * 0 has to be null, even if the local components 𝜃𝜃 ̅ i are not null. It is achieved when the reference triangular signal frequency 𝑓𝑓 0 is the average frequency of all active modules. As a consequence, the steady-state frequency is the average of all active TWGs' frequencies and the interleaving error is only due to their frequency mismatches.

Even if the average value of the oscillating component 𝜃𝜃 ̃ is null, it also affects the PWM signals PD generated from the triangular carrier. It is because the PWM signal is referenced only to one commutation (valley or peak), resulting in a systematic shift. This is a weakness of this approach, as the PD error is dependent not only on the frequency but also on the signal symmetry, so frequency trimming is not effective to reduce interleaving error.

To conclude, mathematical expressions can be derived and used to provide design recommendations such as local controller gain and frequency accuracy requirements to achieve the local error accuracy target. For instance, with a required local error accuracy 𝜀𝜀 𝜃𝜃 ��� = ±1%, the frequency accuracy has to be better than ±2% if the local controller gain 𝛼𝛼 = 1. The complete expression of the final error regarding all parameters is not developed in this document.

Particular case using comparators (𝜶𝜶 = 𝟐𝟐)

The approach presented by XIAO in [START_REF] Xiao | Modular interleaved carrier generator using a straightforward implementation method[END_REF] uses comparators to change the slope direction of the triangular signals, similar to applying an infinite voltage gain (𝛼𝛼 = 2). Considering the model still valid in this case, all poles are on the unit circle and all differential modes oscillate, and theoretically, there is no convergence.

However, even if there is no convergence when the gain 𝛼𝛼 = 2, all triangular carriers change the sign of their slope at the neighbors' crossing instant, such as in a correctly interleaved system with no mismatches. As these are contradictory situations, the system cannot be correctly interleaved.

As shown previously, a DC level mismatch causes an oscillating disturbance. To solve the convergence issue, XIAO added in his approach a saturation in the triangular signals to keep them between 𝑉𝑉 𝑂𝑂 and 𝑉𝑉 𝑚𝑚 , avoiding DC level mismatch and force convergence.

Circuit based simulations

Circuit based simulations are realized to validate the model proposed. where FCx stands for 𝑥𝑥 𝑡𝑡ℎ LC, also named LCx. It can be noted that the start-up by groups converges faster (Mode 1 is not disturbed) than the start-up with one LC in phase opposition as revealed by the model. Considering the first model with only the local loop, the case 𝛼𝛼 = 1 (𝛽𝛽 = 0.5) corresponds to the one shoot response, and is similar to the digital system described previously.

However, the overall digital implementation is not stable in this condition, while the Triangular Carrier Self-Alignment is shown with these simulations.

Conclusion

This chapter has presented a complete model of the triangular carrier self-alignment approach and analyzed its stability criterion.

The proposed model shows the system is robust and can work properly in a wide range of gain and large number of LCs. However, the proportional controller (one freedom degree) limits the system performance because it links directly the transient response with the static error, requiring a trade-off.

The interleaving method using analog signals at the communication links between devices complicate bypass circuits (analog switches and buffers are needed). Moreover, intrinsic mismatch between triangular signal generators (analog signals) cause phase-delay (interleaving) errors that cannot be avoided by frequency adjustment (trimming). The ability to compute a proper correction even when the local phase-delay not in between the neighbors is an additional strength. Nevertheless, its inability to interleave between coincident neighbors makes start-up with numerous coincident carriers risky. Moreover, the mismatch impact in this condition (at start-up with very close neighbors) is still unknown.

Reconfiguration disturbs the PWM signals when the triangular signal play the role of carrier. Using the control signal superimposed on only one threshold would improve this point, e.g. making correction on triangle peak threshold if duty cycle is low. However the triangle peaks would be well interleaved while the triangle valleys would be subject to the mismatch, resulting in an increase on interleaving error.

The following 4 points summarize the triangular carrier self-alignment approach main weaknesses to be addressed in order to improve the system:

-Non-flexible controller; -Uses analog signal;

-Unable to interleave between coincident neighbors; -PWM disturbance during reconfiguration.

New approach: digital signal self-interleaving system

This chapter introduces a new modular distributed self-interleaving approach based on elements exchanging only digital signals, such as clock signals. This chapter includes the design process required to obtain the system parameter values leading to high availability with good transient and static performances. A model and the study of its dynamic behavior are provided.

Additionally, fault events in the communication lines are considered, described and simulated.

The methods to detect and overcome this fault events are also described.

Self-interleaving features

The circular-chain numeric interleaving and the triangular carrier self-interleaving methods have been deeply studied in chapter II and III respectively, where models have been proposed, their stability criterion stablished and their performance limits demonstrated.

The interleaving system features can be classified in three main categories: topology, availability and performance. The feature categories and their goals for this interleaving system are listed on Table IV-1.

Table IV-1 -New interleaving system features/goals.

Feature category Goal

Topology Modularity, scalability, unrestricted carrier type a. Modularity: all modules are equal, i.e. no master required; b. Fail-operational when a communication line fails (note a fault detection is however required).

Advantages of the circular-chain numeric interleaving due to its digital implementation: c. Digital communications, i.e. high noise immunity; d. Flexible local controller corrector (not only proportional), i.e. better closed-loop performance; e. Several possible carrier waveform choices and modulation techniques, i.e. carrier generator dissociated from the local controller; f. No mismatch issue.

Advantages of the triangular carrier self-interleaving mainly due to its analog implementation: g. No shared wire, i.e. no wire connecting all elements (a global clock signal for instance); h. Theoretical unlimited scalability and with perfect interleaving: Continuous phase-delay values (not pre-defined/discrete).

It should be noted the circular-chain numeric interleaving has a major drawback due to the required global clock share-wire. This common wire is a SPOF. So a system architecture such as the triangular carrier self-interleaving should be considered. However, its limitations and weaknesses, mismatches and noise dependences for instance, have to be improved. This will be discussed thereafter.

IV.1.2. Limitations, features to improve

To develop a robust circular chain interleaving system, the triangular carrier selfinterleaving weaknesses have to be listed and discussed. The main issues are: By nature, the equivalent local controller implied by the analog computation is a simple proportional. A more sophisticated controller allowing to implement a more complex control law has to be identified, so that the different closed-loop performance indicators (static gain, settling time, damping) can be set independently.

e. Carrier choice: the interleaving principle is attached to the triangular carrier;

The local controller computes the neighbors' triangular carrier difference and superposes it on the triangular signal generator thresholds. A more generic method has to be proposed that dissociates these two intrinsic points, i.e. the shape of the carrier and the interleaving management.

f. Inter-connection number issue: a large number of connections is required (4 per LC).

To reduce communication lines, each neighbor connections can be a input/output and perform AND operations by wire. E.g. if the outputs are of type open drain, when connected together, each local controller would obtain on the wire the AND result of the LCs outputs.

However, reducing the number of connections may compromise the fail-operational status and potentially add some SPOFs.

These 6 points can be summarized as the following actions to take: The study of the new interleaving technique will be described thereafter.

New improved self-interleaving technique building blocks

To avoid signal mismatches, the module communications have to be based on digital signals, such as a clock signal. Many multiphase control structures do not require interleaved carriers but only interleaved clocks, such as peak/valley detection current-mode control or Digital PWM (D-PWM). In the literature and in many commercial applications, the interleaved clocks are generated from a global synchronization clock and a local Delay Locked Loop (DLL).

In these applications, one oscillator generates the global synchronization clock and imposes the frequency to the other modules. The local interleaved clocks are generated using DLLs. Then, for our case, if a carrier is required, it can be generated using the same phase-delay of the local interleaved clock one. Now, in order to remove any SPOF, if the global synchronization clock is avoided, an oscillator has to be associated to each local interleaved signal. To obtain the targeted interleaving, a Voltage Controlled Oscillator (VCO) has to be used and a feedback loop is required to position its phase-delay in the middle of other two neighboring signals. It is comparable to a PLL system that locks the VCO output clock signal 𝑐𝑐𝑙𝑙𝑘𝑘 𝑜𝑜 to an input clock signal 𝑐𝑐𝑙𝑙𝑘𝑘 𝑖𝑖 , using a phase detector and a loop filter, such as the one shown in However, to provide the interleaving with this new approach, a particular phase detector has to be designed, not only to observe the clock frequency, but also to interleave the local VCO clock signal 𝑐𝑐𝑙𝑙𝑘𝑘 with the two external clock signals 𝑐𝑐𝑙𝑙𝑘𝑘 𝑃𝑃 and 𝑐𝑐𝑙𝑙𝑘𝑘 𝑆𝑆 . It should be noted that the triangular carrier self-interleaving system, previously described in chapter III, is an application case of this approach, but using some analog shortcuts.

Indeed, in that previous case, the "PLL" function is resulting of the analog computations made and is not that clear such as a classical PLL circuit: the subtraction of the neighbors' carriers is equivalent of a phase detector, the voltage gain is equivalent to the loop filter, the triangular carrier generator with adjustable threshold acts like a VCO and includes a built-in feedback.

VCO

Thereafter, the implementation of each function composing the expected selfinterleaving block diagram has to be identified.

IV.2.1. VCO and triangular carrier generator

The objective of this new system is to interleave clock signals and then obtain interleaved carrier signals of any shape if required. So, a VCO that generates a clock signal is required. It is known that the carrier generator, previously described in chapter III, has an internal digital signal that is locked on the triangular carrier. So the digital signal Phase-Delay

IV.2.2. Phase detector

The PDs present between the local and the neighbors' digital signals can be computed The XOR gate reacts to the rising and falling edges of the signals, resulting in two measurements per period. However, the double measurement can bring issues. For instance, if the clock signal duty-cycles are not equal, a dead-zone around the region where the error is close to zero may appear. This dead-zone will generate jitter and must be eliminated. A different logic can be used to solve this issue, such as detecting only the phase-delay around one edge, for instance around the falling edge (triangle valley) shown in Eq. (IV-4).

𝑈𝑈𝛥𝛥 = 𝑐𝑐𝑙𝑙𝑘𝑘 𝑃𝑃 ������ • 𝑐𝑐𝑙𝑙𝑘𝑘 𝐷𝐷𝑁𝑁 = 𝑐𝑐𝑙𝑙𝑘𝑘 ���� • 𝑐𝑐𝑙𝑙𝑘𝑘 𝑆𝑆 (IV-4)
This single edge approach provides the same results as the ones of the XOR gate, but the error measurement operator gain is divided by 2.

Now special care has to be taken regarding the dead-zone around the region where neighbors are coincident, i.e. ∆𝜃𝜃 𝑃𝑃,𝑆𝑆 = 0. This region can bring uncertainty during start-up.

Moreover, when high number of local controllers is used, it may result in non-deterministic steady-state condition. This approach has also a limited lock-in range, so the frequency difference of the clock signals has to be small.

In a real case with disturbances, the dead-zone can lead to a wrong interleaving even if the start condition is PIA. Then, the linear region can be increased around the origin (𝜀𝜀 𝜃𝜃 = 0, ∆𝜃𝜃 𝑃𝑃,𝑆𝑆 = 0) to guarantee a correct interleaving in steady-state. Other DPD options to increase the linear region around the origin are discussed in Annex E.

The single edge approach is adopted, due to the continuity insured in the whole PD operational domain. Its transient response could be slower in some cases due to the perceived error being smaller than the real error outside the linear region. However, the system stays in the linear region in normal operation even in extreme cases where some elements are in the The single edge approach presents the advantage of performing the interleaving base on the detection of only one edge of the clock signal, either the rising or falling-edge. Then, the events synchronized with these edges will be correctly interleaved. For instance, when a triangular carrier is used with low duty-cycle, in order to avoid any PWM signal interleaving error related to carrier symmetry mismatches, it is better to interleave the edges related to the triangle valley.

IV.2.3. Loop filter

The The charge-pump output is connected to a capacitor 𝐶𝐶 to store the resulting charges within a full clock period, producing a voltage 𝑣𝑣 𝑆𝑆 proportional to the average 𝜆𝜆 𝑃𝑃 value. Then, 𝑣𝑣 𝑆𝑆 is sampled, i.e. a copy is stored in the capacitor 𝐶𝐶 𝑚𝑚𝑜𝑜𝑙𝑙𝑛𝑛 , using the "smp" signal. When "smp"

is not active, 𝐶𝐶 𝑚𝑚𝑜𝑜𝑙𝑙𝑛𝑛 holds the last sampled voltage. Then, 𝑣𝑣 𝑆𝑆 is reset to zero using the signal "rst" at each period, avoiding any integration effect. The resulting maintained voltage is noted 𝑣𝑣 𝜀𝜀 𝜃𝜃 The 𝜆𝜆 𝑆𝑆 signal FFT presents several high frequency harmonics. The desired information is provide at low frequency (here 𝑓𝑓 0 /10), but the dominant harmonic at the carrier frequency𝑓𝑓 0 has to be filtered. It can be noted most of the high frequency harmonics are mitigated with the 〈𝜆𝜆 𝑆𝑆 〉 𝑇𝑇 0 signal FFT.

Corrector

The corrector 𝐶𝐶(𝑖𝑖) add compensation poles and zeros to ensure the system closed-loop criteria, such as a small static error, the system stability and the transient response performances.

The controller output 𝑢𝑢 (VCO control voltage input) should also be kept constant each period to avoid disturbing the slope of the VCO triangular signal during reconfigurations and steadystate operation. However, as a periodic average of the error is made, the voltage 𝑢𝑢 will vary slowly during the period if the corrector 𝐶𝐶(𝑖𝑖) has proportional behavior. The controller C(s) can be implemented by several means. For instance, with a simple analog Op-Amp and its appropriate feedback made of resistors and capacitors. The resulting controller would be very flexible because many different transfer functions could be synthetized.

The correction is considered to have slow variation between two successive samples and to be constant in steady-state. A switched capacitor approach could also be considered to implement the sampling circuit and the corrector C(s) at the same time in a unique stage (both functions would be merged).

Considering all these elements, a small-signal model of one interleaving bloc will be proposed. Then the whole system with 𝑁𝑁 interleaved carriers will be modelled and its stability criteria will be revealed.

Single loop model

The static behavior of all elements was developed in the previous section. Now, a small signal continuous time model of a single interleaving element is proposed. As presented earlier, three subsystem have to be modeled. They are:

1. The Error Detector 𝑉𝑉 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖), composed by: a. The Phase Detector, b. The Charge-Pump, c. The Periodic Average circuit, 2. The Corrector 𝐶𝐶(𝑖𝑖), composed by: a. A stage providing the appropriate poles and zero, 3. The VCO 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖).

The error detector, noted 𝑉𝑉 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖), combine three subsystems that are involved in an unique transfer function.

IV.3.1. Error detector

The analog triangular carrier self-interleaving circuit shown in the previous chapter share its triangular carrier waveform with its neighbors. In that case, the PD measurement of the local carrier seemed to be sampled, but this is not correct. Indeed, the triangular carrier PD is available during the whole period, its value is constant and the corrections are sampled when the triangular signal slope changes.

In this new approach, the clock signals edges are used to obtain the PD and the PD can be identified only during the switching instant. In the single edge approach, the PD is observed only once a period. As a result, the PD measured is by nature sampled. However, the correction signal 𝑢𝑢 is a continuous signal. In this simulation, the local clock signal period is assumed to be always uniform equal The capacitor 𝐶𝐶 sampled voltage expression is shown in Eq. (IV-6). The capacitor 𝐶𝐶 voltage 𝑣𝑣 C (𝑘𝑘 𝑖𝑖 0 ) can be written using its fundamental expression related to the integral of the charge-pump output current 𝜆𝜆 P (𝑑𝑑). Its expression shown in Eq.

(IV-7) is composed by the current integral during a period 𝑖𝑖 0 plus its initial voltage value. Due to the reset circuit, it is assumed the initial capacitor voltage 𝑣𝑣 C �(𝑘𝑘 -1) 𝑖𝑖 0 � is null. Then, it become easy to determine the charge stored into the capacitor during the k 𝑡𝑡ℎ period, noted 𝑄𝑄 𝑘𝑘 .

𝑣𝑣 C (𝑘𝑘 𝑖𝑖 0 ) = 1 𝐶𝐶 � 𝜆𝜆 P (𝑑𝑑) 𝑘𝑘 𝑇𝑇 0 (𝑘𝑘-1) 𝑇𝑇 0 𝜃𝜃𝑑𝑑 + 𝑣𝑣 C �(𝑘𝑘 -1) 𝑖𝑖 0 � = 𝑄𝑄 𝑘𝑘 𝐶𝐶 (IV-7)
The charge-pump output current 𝜆𝜆 C (𝑑𝑑) expression is shown in Eq. (IV-8), where 𝐼𝐼 P is a constant reference current, 𝑈𝑈𝛥𝛥(𝑑𝑑) and 𝐷𝐷𝑁𝑁(𝑑𝑑) are its digital input control signals.

𝜆𝜆 P (𝑑𝑑) = 𝐼𝐼 P [𝑈𝑈𝛥𝛥(𝑑𝑑) -𝐷𝐷𝑁𝑁(𝑑𝑑)] (IV-8)
The charge 𝑄𝑄 𝑘𝑘 can be identified from Eq. (IV-7) and then solved, as shown in Eq. (IV-9).

𝑄𝑄 𝑘𝑘 = � 𝜆𝜆 P (𝑑𝑑) From now, all required relations to determine 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) are known and can be solved to express the perceived error. By substituting Eq. (IV-12) in Eq. (IV-11), then successively in Eq.

(IV-10), Eq. (IV-9), Eq. (IV-7), Eq. (IV-6) and finally Eq. (IV-5), the expression of 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) in Eq. (IV-13) is obtained after a rearrangement. Some matrix notation representing convolution sum have been also used to simplify the equation. The simplified expression of 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) is detailled in Eq. (IV-15).

𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) = 2 𝐼𝐼 P 𝑖𝑖 0 𝐶𝐶 𝛿𝛿(𝑑𝑑 -𝑖𝑖 0 2 ⁄ ) * ℎ ZOH (𝑑𝑑) * � � 0.
𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) ≅ 2 𝐼𝐼 P 𝑖𝑖 0 𝐶𝐶 𝛿𝛿(𝑑𝑑 -𝑖𝑖 0 2 ⁄ ) * ℎ ZOH (𝑑𝑑) * � � 0.5 𝛿𝛿(𝑑𝑑 -𝑖𝑖 0 𝑁𝑁 ⁄ ) -1 0.5 𝛿𝛿(𝑑𝑑 + 𝑖𝑖 0 𝑁𝑁 ⁄ ) � 𝑇𝑇 * � 𝜃𝜃 𝑃𝑃 (𝑑𝑑) 𝜃𝜃(𝑑𝑑) 𝜃𝜃 𝑆𝑆 (𝑑𝑑) � • 𝛿𝛿 � 𝑑𝑑 -𝑘𝑘 𝑖𝑖 0 𝑖𝑖 0 � ∞ 𝑘𝑘=-∞ (IV-15)
The Laplace transform 𝑉𝑉 ε 𝜃𝜃 (𝑖𝑖) of 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) approximation in Eq. (IV-15) is expressed in Eq. (IV-16).

𝑉𝑉 ε 𝜃𝜃 (𝑖𝑖) = ℒ � 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) � = 2 𝐼𝐼 P 𝑖𝑖 0 𝐶𝐶 𝑉𝑉 𝑍𝑍𝑂𝑂𝑚𝑚 (𝑖𝑖) 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑 (𝑖𝑖) � 0.5 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑃𝑃 (𝑖𝑖) -1 0.5 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑆𝑆 (𝑖𝑖) � 𝑇𝑇 � Θ 𝑃𝑃 (𝑖𝑖) Θ(s) Θ 𝑆𝑆 (𝑖𝑖) � (IV-16)
where: This applicative case plant 𝛥𝛥(𝑖𝑖) has acceptable phase margin (>57°) at 7.85 kHz, where its magnitude is 0 dB. As conclusion, this system does not present particular stability issues.

𝑉𝑉 𝑍𝑍𝑂𝑂𝑚𝑚 (𝑖𝑖) = ℒ { ℎ ZOH (𝑑𝑑) } = 1 -e -𝑠𝑠𝑇𝑇 0 𝑖𝑖𝑖𝑖 0 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑 (𝑖𝑖) = ℒ { 𝛿𝛿(𝑑𝑑 + 𝑖𝑖 0 2 ⁄ ) } = e -𝑠𝑠𝑇𝑇 0 2 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑃𝑃 (𝑖𝑖) = ℒ { 𝛿𝛿(𝑑𝑑 -𝑖𝑖 0 𝑁𝑁 ⁄ ) } = e -𝑠𝑠𝑇𝑇 0 𝑆𝑆 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑆𝑆 (𝑖𝑖) = ℒ { 𝛿𝛿(𝑑𝑑 + 𝑖𝑖 0 𝑁𝑁 ⁄ ) } = e
Assuming a closed-loop cutoff frequency 𝑓𝑓 𝑐𝑐 equals to 7.85 kHz, the expected damping factor is 𝜉𝜉 ≅ 𝛥𝛥𝑀𝑀 100 ⁄ = 0.58 if the corrector do not changes the phase in 𝑓𝑓 𝑐𝑐 region. A proportional controller with a unitary gain would provide the expected transient response. A phase lag can be added to increase the static gain and cancel the steady-state error.

At this point, the model of one local control loop is known, but it cannot reveal the stability criterion and dynamic behaviors of the global system. To do so, similar studies made in the previous chapters on the global system response will be carried out with this one.

Overall system modelling

As in the previous chapters, the local errors are computed using the matrix 𝑳𝑳 that represents the circular chain of communications, i.e. the connections between the LCs. It is assumed that all LCs in the circular chain are identical, including an error detector, a VCO, and a controller as well.

The same procedure is adopted here to find the overall system model. The study of the system stability with a generic number 𝑁𝑁 of LCs, including the several connections existing between them, is performed using a matrix approach. According to the circular-chain sequence, the PDs are numbered arbitrarily from 1 to 𝑁𝑁, from previous to next direction, from 𝜃𝜃 1 to 𝜃𝜃 𝑆𝑆 , For computation purpose, the previous PD vector 𝜽𝜽 𝑃𝑃 and the next PD vector 𝜽𝜽 𝑆𝑆 are defined in Eq. (IV-18) using the circular shift matrix 𝑺𝑺 expressed in Eq. (III-11) and its conjugate transposed 𝑺𝑺 * , equal to its transposed 𝑺𝑺 𝑇𝑇 because 𝑺𝑺 is real.

𝜽𝜽 𝑃𝑃 = 𝑺𝑺 𝜽𝜽 𝜽𝜽 𝑆𝑆 = 𝑺𝑺 * 𝜽𝜽 (IV-18)
The target PD in the vector format, noted 𝜽𝜽 � (𝑑𝑑), is shown in Eq. (IV- [START_REF] Zhang | A novel distributed interleaving scheme to achieve scalable phase design for microprocessor power management[END_REF], where 𝝋𝝋(𝑑𝑑)

vector is calculated by the "target operator". 𝝋𝝋(𝑑𝑑) does not affect the stability study. The corrector and the VCO matrix transfer functions, 𝑪𝑪(𝑖𝑖) and 𝑯𝑯 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖), are diagonal.

Their expressions are provided in Eq. (IV-26), where 𝑰𝑰 is the identity matrix and 𝑫𝑫(𝑖𝑖) the VCO frequency disturbance vector.

𝑪𝑪(𝑖𝑖) = 𝑼𝑼(𝑖𝑖) 𝑬𝑬(𝑖𝑖) = 𝐶𝐶(𝑖𝑖) 𝑰𝑰 𝚯𝚯(𝑖𝑖) = 𝑯𝑯 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) � 𝑼𝑼(𝑖𝑖) 𝑫𝑫(𝑖𝑖) � = � 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) 𝑰𝑰 1 𝑖𝑖 𝑰𝑰 � � 𝑼𝑼(𝑖𝑖) 𝑫𝑫(𝑖𝑖) � (IV-26)
The connections between the error detector and the corrector have in common the same disturbances, noted 𝑵𝑵(𝑖𝑖) in the vector format as shown in Eq. (IV-27).

𝑬𝑬(𝑖𝑖) = 𝑽𝑽 ε 𝜃𝜃 (𝑖𝑖) + 𝑵𝑵(𝑖𝑖) (IV-27)
The plant transfer function comprising the Multiple Inputs and Multiple Outputs (called a MIMO system) of this system is noted 𝑷𝑷(𝑖𝑖) and shown in Eq. (IV-28). Eq. (IV-31) can be rewritten as a system of 𝑁𝑁 independent transfer functions in Eq.

𝑷𝑷(𝑖𝑖

( It should be noted that 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) can be split in a real and a complex components as shown in Eq. (IV-33). Indeed, classical control system have null complex component. The diagonal components of 𝑳𝑳(𝑖𝑖) are complex-coefficient systems as shown in [START_REF] Troeng | Complex-coefficient systems in control[END_REF]. It should be noted that 𝑉𝑉 * 𝑖𝑖 (𝑗𝑗0) = 𝜆𝜆 𝑖𝑖 . Additionally, it can be noted for 𝜆𝜆 = 4 (higher gain) that 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) ≅ 𝜆𝜆 𝑖𝑖 are similar until the expected cutoff frequency ±7.85 kHz. For the other 𝜆𝜆 = 1, 2, 3, the components of |𝑉𝑉 * 𝑖𝑖 (𝑖𝑖)| become different of |𝑉𝑉 * 𝑖𝑖 (-𝑖𝑖)|for at lower frequencies. However, these modes have smaller gains and will have smaller bandwidth. As a result, these differences will not be perceived within the mode bandwidth. For 𝜆𝜆 = 0, the mode is not controllable because the gain is very low.

As a conclusion, the system is quite complex. The standard matrix 𝑳𝑳 could be a good

Stability concern

To reveal the stability concern, the static error constraint must analyzed before the corrector synthesis.

IV.6.1. Static gain constraint

An integrator can be added to the controller 𝐶𝐶(𝑖𝑖) to cancel the error brought by the disturbance input 𝑫𝑫(𝑖𝑖). However, common mode deviation in the noise input 𝑵𝑵(𝑖𝑖) would saturate the VCO control voltage 𝑢𝑢. The common mode cannot be controlled because 𝑉𝑉 * 0 (𝑖𝑖) is 𝜠𝜠 𝚯𝚯 * (𝑖𝑖)

𝑫𝑫 * (𝑖𝑖) = 𝑖𝑖 0 𝑘𝑘 𝑛𝑛 ⁄ H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) 𝐶𝐶(𝑖𝑖) �𝑰𝑰 -𝒐𝒐𝑳𝑳 * (𝑖𝑖)� -1 𝒐𝒐𝑳𝑳 * (𝑖𝑖) , |𝑜𝑜𝑉𝑉 * 𝑖𝑖 (𝑖𝑖)| > 1 ⟹ 𝛦𝛦 Θ * 𝑖𝑖 (𝑖𝑖) 𝐷𝐷 * 𝑖𝑖 (𝑖𝑖) = 𝑖𝑖 0 𝑘𝑘 𝑛𝑛 ⁄ H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) 𝐶𝐶(𝑖𝑖) , 𝜆𝜆 = 1 … 𝑁𝑁 -1 (IV-35)
It can be noted that 𝐶𝐶(𝑖𝑖) can reduce the differential mode disturbances 𝐷𝐷 * 𝑖𝑖 (𝑖𝑖). In steady-state, the differential mode errors are reduced by a factor 𝐶𝐶(𝑗𝑗0), so the interest of having |𝐶𝐶(𝑗𝑗0)| → ∞, i.e. having at least an integrator in 𝐶𝐶(𝑖𝑖). As a conclusion, a controller with a high static gain is good to reduce the differential modes.

Nevertheless, a high static gain can cause side effects related to the common mode. To understand the issue, the signal 𝒖𝒖(𝑑𝑑) common mode final value 𝒖𝒖 0 𝑆𝑆𝑆𝑆 has to be revealed. To do so, the signals 𝑼𝑼(𝑖𝑖) is diagonalized as 𝑫𝑫(𝑖𝑖) and 𝑵𝑵(𝑖𝑖), as shown in Eq. (IV-36).

𝑼𝑼 * (𝑖𝑖) = 𝑾𝑾 -𝟏𝟏 𝑼𝑼(𝑖𝑖)

(IV-36)

The diagonal transfer functions from 𝑵𝑵 * (𝑖𝑖) to 𝑼𝑼 * (𝑖𝑖) is shown in Eq. (IV-37). As the common mode open-loop transfer function |𝑜𝑜𝑉𝑉 * 0 (𝑖𝑖)| ≪ 1 because 𝑉𝑉 * 0 (𝑖𝑖) ≅ 0 , the related common mode transfer function can be easily found, as shown in this equation.

𝑼𝑼 * (𝑖𝑖) 𝑵𝑵 * (𝑖𝑖) = �𝑰𝑰 -𝒐𝒐𝑳𝑳 * (𝑖𝑖)� -1 𝐶𝐶(𝑖𝑖) 𝑈𝑈 * 0 (𝑖𝑖) 𝑁𝑁 * 0 (𝑖𝑖) = 𝐶𝐶(𝑖𝑖) 1 -𝑜𝑜𝑉𝑉 * 0 (𝑖𝑖) = 𝐶𝐶(𝑖𝑖) (IV-37)
𝐷𝐷 * 0 (𝑖𝑖) is null by definition. Indeed, as 𝑓𝑓 0 is the average of all local free-running frequencies, the sum of 𝜃𝜃 𝑖𝑖 = 𝛿𝛿𝑓𝑓 𝑖𝑖 𝑘𝑘 𝑛𝑛 ⁄ is null. So, the final value of 𝑢𝑢 * 0 (𝑑𝑑), noted 𝑢𝑢 * 0 𝑆𝑆𝑆𝑆 , shown in Eq. (IV-38), is obtained by applying the final value theorem to Eq. (IV-37). The component 𝑢𝑢 * 0 𝑆𝑆𝑆𝑆 causes a second side effect, it causes a deviation of the average frequency Δ𝑓𝑓 0 in steady-state, noted Δ𝑓𝑓 0 𝑆𝑆𝑆𝑆 . Its expression is shown in Eq. (IV-39).

Δ𝑓𝑓 0 𝑆𝑆𝑆𝑆 = 𝑘𝑘 𝑛𝑛 √𝑁𝑁 𝑢𝑢 * 0 𝑆𝑆𝑆𝑆 |Δ𝑓𝑓 0 𝑆𝑆𝑆𝑆 | = 𝑘𝑘 𝑛𝑛 Δ𝑢𝑢 𝑠𝑠𝑑𝑑𝑡𝑡 (IV-39)
where Δ𝑢𝑢 𝑠𝑠𝑑𝑑𝑡𝑡 is the maximum 𝑢𝑢 deviation from its neutral value.

So, to limit the frequency deviation in a small range, |𝐶𝐶(𝑗𝑗0)| has to be limited and |𝑁𝑁 * 0 (0)| has to be as low as possible. A clear trade-off on |𝐶𝐶(𝑗𝑗0)| value has to be considered, impacting both the modal steady-state error and the frequency deviation.

IV.6.2. Corrector synthesis

As seen in the previous chapter, some trade-off have to be made because the modes present different gains, related to their eigenvalues, but all of them use the same corrector. The corrector is synthetized to provide the largest bandwidth with minimum phase margin of 55° combined with a phase-lag to increase the static gain. The matrix 𝑽𝑽(𝑖𝑖) is simplified and replaced by 𝑳𝑳.

In the use case considered here with 𝑁𝑁 = 8, the differential Mode 4 has the higher eigenvalue equals to 2, so the controller proportional gain must to be 0.50 to keep the same cutoff frequency. A zero is added to the controller to increase the static gain. The zero frequency is placed at 145 Hz, at least 8 times smaller than the cut-off frequency of Mode 1 to keep enough It can be noted that all modes' phase margins are greater than 55°, i.e. within the specifications. Also, the modes' rise times are different as expected, because they all depend on their associated cutoff frequency.

It can be noted that mode 1 has an important overshoot when compared to the expected value from its phase margin. This is because the phase-lag open-loop zero is close to the mode 1 cut-off frequency and disturbs its closed-loop response, similarly to a proportional-integral controller. The zero effect can be removed with a phase-lag controller based on an integralproportional equivalent topology.

These rise time responses are valid only when all modules are located in between their local neighbors. The response is slowed down if some LCs are not in between their neighbors because the perceived errors reach limited values (saturation). In that case, the stability criterion will not be analyzed because the number of cases to considered will be very high and the nonlinear system to be analyzed will become very complex.

IV.6.3. Diagonal response

The dynamic behavior of the overall system has been simulated and the observed settling times compared with the ones predicted. A MIMO transfer function based model is defined and simulated using MathWorks MATLAB ® . In the simulations performed hereafter, the system starts from its expected equilibrium state with all the carriers well interleaved. Each mode is excited individually, one after the other, from the common mode (mode 0) to the last one (mode 4) using the system eigenvectors (lines of the DFT matrix) as components of the disturbance signal 𝒅𝒅.

Fault hazards impact

Considering the implementation of the real system in an integrated circuit, the devices or wire links are always exposed to fault issues, such as short-circuits or disconnections (opencircuits). Most of the faults can be placed in two categories: short to ground and short to adjacent pin. The short to ground is a generic fault because causes a level freeze. The level freeze happens due a short to any level or pin disconnection, because most of the inputs have internal pull-up or pull-down.

When an inter-LC communication wire is stuck to a constant level, its input comparator with hysteresis will be provide a constant logical level. As a result, when comparing the constant input with the local clock, the UP or DN signal will have 50% duty cycle. The 50% duty cycle is equivalent to a detection of ±180° with its neighbor. It is equivalent to introducing an additional factor ±0.25 in the 𝝋𝝋 vector. The correctors will slowly saturate and cause consequently frequency deviation. During the time between the fault and the saturation, the PD will be in PD an unequal distribution because the others LCs will try to compensate an error that cannot be eliminated. After the saturation, the PD will be properly interleaved, but with a frequency deviation.

Let consider now a system with 𝑁𝑁 LCs in which the communication input of one LC is stuck to a constant level so that the LC detects a PD equal to -0. When a short-circuit occurs on adjacent communication wires, considering a AND operation by wire is obtained, both LC perceive the same rising and falling edges on its inputs.

It should be noted that one LC notes its own rising edges while the other notes its own falling edges. As only one of the edges is used for the PD measurement, one of the LC controllers perceives its neighbor as coincident because detects its own edge, while the other LCs can detect

properly the PD because it can detect the neighbor edge. This will cause some frequency deviation, and the impact on the interleaving error will be small because the PD error detected will be only equal to 0.5 𝑁𝑁 ⁄ . Because the sum of the errors has to be cancelled, the others LC errors, due to the compensations, would be approximately 0.5 𝑁𝑁 2 ⁄ . The LCs on the board are connected to their close neighbors. "Css2N" of the 𝜆𝜆 𝑡𝑡ℎ LC is connected to "CssP" of the 𝜆𝜆 + 1 𝑡𝑡ℎ LC and "Css2P" of the 𝜆𝜆 + 1 𝑡𝑡ℎ LC is connected to "CssN" of the 𝜆𝜆 𝑡𝑡ℎ LC. The circular chain of communications has to be closed with a cable using the connectors placed at the upper left and right sides of the board, connecting the LC6 to LC1.

Proof-of-concept development

Multiple boards can be connected together, connecting LC6 to LC7 and LC12 to LC1, where LC7 to LC12 are the LCs of the second board for instance.

IV.8.1. Triangular carrier generator and pre-positioning

The triangular carrier generator circuit is shown in The operational amplifier output is the triangular carrier called "Vtri".

To analyze the modal response, "Vtri" signal has to be set to a predefined value at the begging. The additional circuits required to pre-position the signal "Vtri" are also shown in

Shared LC1 LC2 LC3 LC4 LC5 LC6
Figure IV-17. The comparator (1) initial position is controlled at its non-inversing input with an analog switch "s0". The operational amplifier (2) output voltage is set to a predefined value thanks to the switch "s2" and the feedback resistors using the jumpers "Go" (open-loop gain)

and "Gx" (gain x), where x is equals to 1, 2 and 4. The switch "s1" is added to force the operational amplifier polarity and to avoid the output voltage dependence with the comparator output. So the voltages "V0" (initial voltage) and "V0ax" (auxiliary initial voltage) determine in which quadrant the phase-delay starts. An additional comparator generates the digital signal "Sync" (Sinc) aligned with the triangular signal peak used for SMP and RST synchronization. Figure IV-18 shows the 24 combinations of "V0", "V0ax" and "Gx" (Go always closed), required to pre-position "Vtri" phase-delays within 15° steps.

Figure IV-18 -24 combinations of "V0", "V0ax" and "Gx" to pre-position "Vtri" phase-delays.

IV.8.2. New interleaving local controllers

Table IV-3 shows the initial position chosen based on the initial modal error required. The new interleaving local controller is composed of a digital and an analog core.

The digital core, shown in

𝑣𝑣 𝑆𝑆 𝑢𝑢

The measure can be trimmed using "MesTrim" trimmer potentiometer to avoid static error.

IV.8.3. Fault introduction

The fault introduction module is located upstream LC1, i.e. between the LC1 and the circular-chain connector.

Three fault types can be applied individually or simultaneously (with separated control) on the lines "CssP" of LC1 and "CssN" of LC connected to LC1 though the cable. The faults are: open (disconnection), short-circuit to 5V and short-circuit to GND.

Additionally, a short-circuit fault can also be introduced to connect "CssN" to "CssP" though an impedance.

Experimental validation

The experimental validation will be done using two proof-of-concept boars, a Teledyne Table IV-4 shows the adapted experimental positions used during the measurements.

IV.9.3. Start-up response validation

The start-up transients are also verified. The start-up responses measurements support the behavior predicted with the model, showing that the start-up response by groups (4+4) converges faster than the start-up with one PD in phase opposition because the Mode 1 is not disturbed.

IV.9.4. Reconfiguration response validation

These reconfiguration simulations were meant to demonstrate the necessity of prepositioning a bypassed between their neighbors when inserted. Multiples unsuccessfully attempts were made to obtain a proper measurement where LC5 is coincident with 𝜃𝜃 1 at the begging, even using the pre-positioning. When bypassed, LC5

was always able to position itself between its neighbors. This is a good result, observed in the particular case 𝑁𝑁 = 7 (LC5 bypassed), but the cause and the extension to other values of 𝑁𝑁 has to be demonstrated.

IV.9.5. Short to ground fault response validation

The behavior in case of connection link failure were reveals theoretically using the final value theorem. However, the measurement is needed to observe if the system diverges, and in negative case, what happens when the fault is removed. When the fault is applied (0 ms), the second state starts. In this state, the LCs try to correct the error using the proportional corrector and a fast PD rearrangement can be observed.

The PDs are in a non-uniform arrangement and get closer, what indicates an increasing frequency. This goes until a LC saturates.

The third state starts when a LC saturates (at 82 ms). At this point, one of the loops is broken. As this specific LC stops correcting the accepts to have a non-null error, a new steadystate proper interleaving is obtained, but with a frequency deviation.

The fourth state starts when the fault is removed (120 ms). The controller memory (integral effect) is slowly being removed and converges to the initial condition with proper interleaving and with the correct frequency.

Conclusion

This chapter has presented the complete design and modeling of a new approach for the self-interleaving of carriers using digital signals for the inter-LC communications. A controller has been designed to meet the system stability criterion and obtain good transient performance.

A proof-of-concept has been built and experimental measurements have been performed. The experimental results support the developed theoretical study.

This innovative approach is robust and can work properly with many active local controllers. The controller is flexible and easy to design using classical control theory because the diagonal systems where revealed. The controller chosen guarantees a good transient performance with low static error. Reconfiguration events are operational. They do not disturbs the duty-cycle of the PWM signals because the method consists to sample the error at each period. The LC events are synchronized with the beginning of each clock period to avoid incorrect PD measurement.

The corrector designed was used in the proof-of-concept and the modal behavior has been measured and correlates with the theoretical one. The measurements during start-up transients with multiple disturbed modes also correlate with the theoretical, each individual mode had its expected transient without interactions with the other modes.

Thanks to the digital signals used, the communication links between devices are now robust and present no matching issues. It should be noted however, the inability to interleave between coincident neighbors makes start-up with numerous elements risky. But this issue can be solved using a different PD detector that extends the error detection to the region where the neighbors are coincident.

Nevertheless, no issues were observed during experimental measurements with the error detector used. The performance was even better than expected, where the insertion of a nonpre-positioned lead ways to a correct interleaving. This may be the result of the interaction with the others LCs, i.e. the group behavior surpass local flaws. No conclusion can be stated because these special cases with coincident neighbors are in limit of validity of the proposed model.

The introduction of a short to ground fault did not lead to a catastrophic failure in the tested used case. Only a frequency deviation and a temporary incorrect interleaving were observed. As soon as the fault was removed, the system recovered to the correct interleaving.

The frequency jitter measurement proved this approach has good noise immunity. An integrated circuit implementation will probably perform even better.

Conclusion

The theoretical procedure presented in this thesis where able to correlate with the circuit based simulations and the proof-of-concept experimental validation. This study provides the tools needed to design a robust distributed interleaving system, with good transient, static and noise immunity performances.

The study of the digital approach in chapter II brough basic understanding of the circular chain constraints, mainly about the fact that a trade-off is needed to select the closed loop performance because all modes share almost the same transfer function with only a different gain. A transient optimization method was proposed and applied. Important elements for simulation were also highlighted and verified. The necessity of the shared clock line was the major issue to discard this interleaving approach.

The study of the triangular carrier self-alignment in chapter III brough understanding to the modeling of non-synchronized systems by referring all of them to the same phase reference.

After modeling, the stability criteria was revealed and transient performance optimization performance. A cyclic delay appears in the interconnections and a rotation effect was seen in the transient responses. The usage of analog connections and mismatch issues were the major issue to discard this interleaving approach.

A new approach was proposed using digital signals self-interleaving in chapter IV. The conception was meant to avoid the issues on the two previous studied approaches. A basic structure was proposed, the modeling and corrector design performed. The modeling and theoretical study were validated with simulation and then a proof-of-concept was shown. The proof-of-concept validations present very good performance, being robust and easy to implement.

As perspective, the implementation this new approach in an integrated circuit and validation remains to be done, as well as use of the interleaved clocks to generate the interleaved PWM signals of a multiphase converter. A detailed study of this approach shows the current balance loop is non-linear because the multiplication of the corrected slope 𝛼𝛼 ′ 𝑖𝑖 with 𝐼𝐼 𝑖𝑖 , two state variables. Additionally, this system can diverges because current balance errors are applied to two cascaded integrators. As a result, this current balance approach has two drawbacks:

Figure I- 1 -

 1 Figure I-1 -NXP plan to improve safety. [1] ............................................................................ 6 Figure I-2 -Network architectures: centralized, decentralized and distributed. [2] .................. 7 Figure I-3 -AVS, power dissipation: a) before and b) after AVS adjustment. [3]. .................. 8 Figure I-4 -DVFS: a) power consumption vs. frequency, b) energy per instruction. ............... 8 Figure I-5 -Evolution of active and leakage power densities with node technology. Source: Intel. ............................................................................................................................................ 9 Figure I-6 -Clock modulation: a) 100% active-low, b) 50% active high + 50% idle. [4] ........ 9 Figure I-7 -DVFS and clock modulation. Best efficiency mapping for different workloads. 10 Figure I-8 -Load regulation, output voltage and current waveforms : a) without AVP, b) with AVP. [5] ................................................................................................................................... 10 Figure I-9 -Combined impact of AVS, DVFS and AVP techniques in the processor supply chart. ......................................................................................................................................... 10 Figure I-10 -Simplified scheme of VRM and processor control techniques. ......................... 11 Figure I-11 -Multiphase Buck converter (3 legs): a) topology, b) signal waveforms. ........... 11 Figure I-12 -FIVR: a) supply principle using either integrated LDO or IVR, b) supply scheme. [6, p.] ........................................................................................................................................ 12 Figure I-13 -Intel Core i7-4700MQ Processor: a) package, b) integrated inductors, c) converter topology, d) processor die, e) integrated inductors and capacitors view, f) converter specification. [7] ....................................................................................................................... 12 Figure I-14 -Increasing number of phases tendency............................................................... 13 Figure I-15 -Processor's die size comparison. [8] .................................................................. 13 Figure I-16 -a) Tesla's HW3 self-driving (level 2/3) car computer, b) Intel Nervana NNP .. 14 Figure I-17 -ST semiconductors 48V direct conversion approach: a) topology, b) multiphase operation. .................................................................................................................................. 14 Figure I-18 -Vicor a) Factorized Power Architecture block diagram, b) typical SAC specifications, c) SAC/VTM topology. Source: Vicor. ........................................................... 15 Figure I-19 -Nvidia GPU boards: a) A100 Tensor Core, b) Tesla P100. ............................... 15 Figure I-20 -Current balance distribution: a) Shared (single) wire [10], b) Circular chain [11]. .................................................................................................................................................. 17Figure I-21 -Zhang and Huang Modularized Voltage Regulator with shared wire average voltage reference [12]. .............................................................................................................. 18 Figure I-22 -Ericson BMR series POL regulators current balance strategy: a) no balance, b) with balance. ............................................................................................................................. 18 Figure I-23 -Cousineau droop slope adjustment technique to balance leg currents [13]: a) no balance, b) with balance. .......................................................................................................... 19 Figure I-24 -DLL circuit example. [14] .................................................................................. 20 Figure I-25 -Phase splitter: a) time diagram, b) scheme. [15] ................................................ 21 Figure I-26 -LTM4636-1 datasheet « Figure 4. Phase Selection Examples » extract. ........... 22 Figure I-27 -KOHAMA and all interleaving technique [18]: a) connections, b) delay calculation. ............................................................................................................................... 22

Figure I- 21 -

 21 Figure I-1 -NXP plan to improve safety. [1] ............................................................................ 6 Figure I-2 -Network architectures: centralized, decentralized and distributed. [2] .................. 7 Figure I-3 -AVS, power dissipation: a) before and b) after AVS adjustment. [3]. .................. 8 Figure I-4 -DVFS: a) power consumption vs. frequency, b) energy per instruction. ............... 8 Figure I-5 -Evolution of active and leakage power densities with node technology. Source: Intel. ............................................................................................................................................ 9 Figure I-6 -Clock modulation: a) 100% active-low, b) 50% active high + 50% idle. [4] ........ 9 Figure I-7 -DVFS and clock modulation. Best efficiency mapping for different workloads. 10 Figure I-8 -Load regulation, output voltage and current waveforms : a) without AVP, b) with AVP. [5] ................................................................................................................................... 10 Figure I-9 -Combined impact of AVS, DVFS and AVP techniques in the processor supply chart. ......................................................................................................................................... 10 Figure I-10 -Simplified scheme of VRM and processor control techniques. ......................... 11 Figure I-11 -Multiphase Buck converter (3 legs): a) topology, b) signal waveforms. ........... 11 Figure I-12 -FIVR: a) supply principle using either integrated LDO or IVR, b) supply scheme. [6, p.] ........................................................................................................................................ 12 Figure I-13 -Intel Core i7-4700MQ Processor: a) package, b) integrated inductors, c) converter topology, d) processor die, e) integrated inductors and capacitors view, f) converter specification. [7] ....................................................................................................................... 12 Figure I-14 -Increasing number of phases tendency............................................................... 13 Figure I-15 -Processor's die size comparison. [8] .................................................................. 13 Figure I-16 -a) Tesla's HW3 self-driving (level 2/3) car computer, b) Intel Nervana NNP .. 14 Figure I-17 -ST semiconductors 48V direct conversion approach: a) topology, b) multiphase operation. .................................................................................................................................. 14 Figure I-18 -Vicor a) Factorized Power Architecture block diagram, b) typical SAC specifications, c) SAC/VTM topology. Source: Vicor. ........................................................... 15 Figure I-19 -Nvidia GPU boards: a) A100 Tensor Core, b) Tesla P100. ............................... 15 Figure I-20 -Current balance distribution: a) Shared (single) wire [10], b) Circular chain [11]. .................................................................................................................................................. 17Figure I-21 -Zhang and Huang Modularized Voltage Regulator with shared wire average voltage reference [12]. .............................................................................................................. 18 Figure I-22 -Ericson BMR series POL regulators current balance strategy: a) no balance, b) with balance. ............................................................................................................................. 18 Figure I-23 -Cousineau droop slope adjustment technique to balance leg currents [13]: a) no balance, b) with balance. .......................................................................................................... 19 Figure I-24 -DLL circuit example. [14] .................................................................................. 20 Figure I-25 -Phase splitter: a) time diagram, b) scheme. [15] ................................................ 21 Figure I-26 -LTM4636-1 datasheet « Figure 4. Phase Selection Examples » extract. ........... 22 Figure I-27 -KOHAMA and all interleaving technique [18]: a) connections, b) delay calculation. ............................................................................................................................... 22

1 -

 1 Voltage regulation and balance techniques combinations. .................................... Table I-2 -Interleaving techniques mapping. ..........................................................................Table II-1 -Number of iterations for 5% response (𝑁𝑁 = 8). .................................................. Table II-2 -Number of iterations for 5% response using lead-lag corrector (𝑁𝑁 = 8). ........... Table II-3 -Iteration number for 5% response (𝑁𝑁 = 8) with one PD constant. ...................... Table II-4 -Number of iterations for 5% response (𝑁𝑁 = 9). .................................................. Table III-1 -Number of iterations for 5% convergence criterion (𝑁𝑁 = 8, 𝑀𝑀 = 5, 4 differential modes, 4 eigenvalues). ............................................................................................................. Table IV-1 -New interleaving system features/goals. ............................................................. Table IV-2 -Modal performances obtained with the model in the case study. ..................... Table IV-3 -Modal initial position and modal error. ............................................................ Table IV-4 -Experimental modal initial position and modal error. ...................................... Table IV-5 -Modal performances measured in the case study. ............................................

  work is part of the partnership between NXP Semiconductors and "Laboratoire Plasma et Conversion d'Energie" (LAPLACE) on the development of embedded systems for the autonomous mobility. This work treats specifically the study and development of a modular fail operational control for multiphase power converters needed to supply the autonomous driving embedded computers. The studied techniques can be applied in any type of series and/or parallel multicellular converter topologies. The fail tolerant control with reconfiguration ability is sought using modular distributed control without single point of failure. The distributed control of multicell converters requires the generation of interleaved PWM signals, the balance of current/voltages between cells and the output regulation. The ultimate objective of this thesis is the study and evaluation of the distributed control for future market introduction of a NXP product for core processor supply in automotive applications. This work focusses mostly on the interleaving approaches. Chapter I presents the context and state of the art. The context includes the NXP safety path and focuses the step to reach fail operational power supplies for processors. The approach developed is based on distributed control without single point of failure. A survey of requirements and techniques is developed to understand up-to-date processors power supply; trends of workload and power consumption increase are highlighted; and the adoption of multiphase converter topology is verified. The state of the art covers mainly the modular distributed techniques applied on voltage regulation and current balance, and then on interleaving techniques.

  AAA Foundation for Traffic Safety published in 2019 an article entitled "Think You're In Your Car More? You're Right. Americans Spend 70 Billion Hours Behind the Wheel" showing an increase of more than 6 percent on driving time from 2014-15 and 2016-17. Current technology, involving automation and robotics, pushes the development of autonomous driving vehicles and soon the mass deployment of robot taxis. It will allow people to do other activities while moving and improve mobility of non-enabled people. In the other hand, according with the World Health Organization 2018 report "Every year the lives of approximately 1.35 million people are cut short as a result of a road traffic crash. Between 20 and 50 million more people suffer non-fatal injuries, with many incurring a disability as a result of their injury. (…) Road traffic crashes cost most countries 3% of their gross domestic product." In most of the cases, the crashes are caused by human error and could be avoided.

Figure I- 1 -

 1 Figure I-1 -NXP plan to improve safety.[START_REF]Three things to know about functional safety[END_REF]

  decentralized and distributed. These different architectures are illustrated in Figure I-2.

Figure I- 2 -

 2 Figure I-2 -Network architectures: centralized, decentralized and distributed.[START_REF]Difference Between Centralized vs Decentralized vs Distributed network[END_REF]

Figure I- 3 -

 3 Figure I-3 -AVS, power dissipation: a) before and b) after AVS adjustment. [3]. When a different workload (clock) is required, the dependency between voltage supply and workload can be used to change the processor's performance. The processor supply voltage (and power dissipation) can be adjusted to ensure correct operation. This technique is called Dynamic Frequency Voltage Scaling (DVFS), where the supply voltage is adjusted on-the-fly to correspond to the clock frequency (workload) required.Figure I-4 (a) shows the power dissipation plot for different frequencies and (b) the energy required per instruction. A minimum can be seen in (b), being the optimal point for the processor operation, i.e. the lower energy per instruction rate. This point indicates where the processors work with optimal power consumption.

I- 5 .

 5

Figure I- 5 -Figure I- 6 -

 56 Figure I-5 -Evolution of active and leakage power densities with node technology. Source: Intel. As processor leakage power became an issue, fast cycles of "processing then rest" were introduced, thanks to clock modulation, to operate always at the more efficient point. During the rest time (idle), some processors regions are unsupplied to avoid leakage. Examples of power consumption as a function of active time can be seen in Figure I-6, where total energy consumption in case (b) is smaller than in case (a) for a same workload (not in scale).

Figure I- 6 .

 6 Figure I-6. This induces to the power supply very fast load transients, i.e. current transients. To handle this, a predictive technique called Adaptive Voltage Positioning (AVP) was introduced. Without AVP, the converter tries always to regulate the voltage in the middle of the voltage tolerance range to accommodate overshoots and undershoots, as shown in Figure I-8.

Figure I- 7 -Figure I- 8 -

 78 Figure I-7 -DVFS and clock modulation. Best efficiency mapping for different workloads.The AVP technique consists basically in adjusting the load voltage based on the current required. This dependency is also called Load Line (LL) because it is equivalent to a virtual resistance connecting an ideal voltage source (reference) with the load. The AVP allows to reduce both the output filter capacitor by a factor two and the power consumption.

Figure I- 9 -

 9 Figure I-9 -Combined impact of AVS, DVFS and AVP techniques in the processor supply chart. A simplified scheme with all these techniques is shown in Figure I-10. On the processors side, AVS takes into account the process variations, temperature and aging to choose the most adapted voltage reference level. Additionally, the clock modulation and DVFS will then adjust the processor voltage and operation to the workload. The Voltage Regulator Module (VRM) refers to the Point of Load (PoL) regulator used to supply processors. The VRM will apply AVP to improve transients and reduce even further processor power consumption.

Figure I- 10 -Figure I- 11 -

 1011 Figure I-10 -Simplified scheme of VRM and processor control techniques. Multiphase Buck converters are usually chosen due to the ability to deliver high current and being able to handle fast transients. The scheme of a Buck converter with 3 legs is shown in Figure I-11 (a). The converter control is composed of three main features: output voltage regulation, leg current balance and PWM leg control signal interleaving. The interleaving consists in equally spacing the switching commands on each leg (e.g. ON-time) to obtain a higher fundamental frequency in the combined inductor current at the output, as shown in the waveforms of Figure I-11 (b).

ForFigure I- 12 -Figure I- 13 -

 1213 Figure I-12 -FIVR: a) supply principle using either integrated LDO or IVR, b) supply scheme. [6, p.] These approach was introduced in the Intel Core i7-4700MQ Processor, shown in Figure I-13 (a), in a single die approach, called Fully Integrated Voltage Regulator (FIVR). Each domain highlighted in (d) is supplied by a dedicated converter. The converter topology used is a 3-level flying capacitor multiphase converter (c) with inductors integrated in the package (b).The inductors are very small, an astonishing 58 integrated inductor pattern can be count, operating as 2, 4, 6 or 8 multiphase converters can be observed in (e). The converter specification is shown in (f).

Figure I- 14

 14 Figure I-14 shows some striking points of the VRM evolution with the number of phases associated. The number of phases should remain at these level (around 12) in the processor market as more efficient processors are introduced and thermal management issues are solved.

Figure I- 14 -

 14 Figure I-14 -Increasing number of phases tendency.In the recent years, the artificial intelligence boom occurred. To improve performances, these applications prefer specialized circuits like GPUs and specialized Neural Network Processors (NNP). As a result, the processor's die sizes increased as well as their power consumption requirements. A die size comparison can be seen in FigureI-15.

Figure I- 15 -

 15 Figure I-15 -Processor's die size comparison. [8] Tesla's HW3 self-driving car computer deployed in Tesla Model 3, shown in Figure I-16 (a), is dedicated to autonomy level between 2 and 3. Its electronic board is composed by two processing units, each one supplied by a 2 phases Buck converter. The processors are very efficient, so only two standard power stages are sufficient. It should be noted a higher number of phases would increase redundancy and reduce the volume.

Figure I- 17

 17 Figure I-17 (a) shows one ST semiconductors solution based on a Full-Bridge commutation cell at the primary, a resonant circuit and a current doubler at the secondary, and (b) shows its scalability up to 6 phases.

Figure I- 17 -Figure I- 19 -

 1719 Figure I-17 -ST semiconductors 48V direct conversion approach: a) topology, b) multiphase operation. Vicor proposed a disruptive solution where multiple transformers, transistors and drivers are integrated together. Vicor solution is also unique because no feedback is present in the transformer unit, i.e. it works in open loop. The output voltage is regulated by varying the transformer's input voltage with a Buck-Boost converter. The two stages are called "PRMs (Pre

Figure I- 20 -

 20 Figure I-20 -Current balance distribution: a) Shared (single) wire [10], b) Circular chain[START_REF] Bolloch | New masterless modular current-sharing technique for DC/DC parallel converters[END_REF].

Figure I- 21 ,

 21 Figure I-21, where each leg's references Vref are tied together.

Figure I- 21 -

 21 Figure I-21 -Zhang and Huang Modularized Voltage Regulator with shared wire average voltage reference [12]. This technique solves only a part of the problem, as the droop gain and the load voltage measurement mismatches cannot be compensated. Ericson PoL regulators from BMR series (463 to 467) uses the droop technique and they can be associated together in parallel using a leader/followers approach. To balance the current, the leader broadcasts its output current in a digital communication link and the followers adjust their own reference voltages to match the leader current, as shown in Figure I-22 (a) without balance and (b) when balance is enabled. As a result, the leader imposes the converter voltage/current characteristics.

Figure I- 22 -

 22 Figure I-22 -Ericson BMR series POL regulators current balance strategy: a) no balance, b) with balance.

FigureFigure I- 23 -

 23 Figure I-23 -Cousineau droop slope adjustment technique to balance leg currents [13]: a) no balance, b) with balance.

  The ring oscillator is the simplest way to generate interleaved clocks. It is composed by inverter gates connected in a closed chain. This structure has two main weakness. First, the clock frequency depends on the number of elements and on its delay. Second, it only works with odd numbers of switching-cells and then clock signals. A Delay Locked Loop (DLL) is able to control the clock frequency through a feedback loop and generate the exact number of clocks required. It is composed by a Voltage Controlled Delay Loop (VCDL) and a phase/frequency feedback. The VCDL is an association of controlled delay cells. Each delay cell is associated with an interleaved clock signal. The phase/frequency feedback is composed by a Phase Detector (PD), a Charge Pump (CP) and a Loop Filter (capacitor). A DLL example is shown in Figure I-24.

Figure I- 24 -Figure I- 25 -

 2425 Figure I-24 -DLL circuit example.[START_REF] Pierre | End OF Column Circuits -Design Review -ppt download[END_REF] Interleaved clocks can also be obtained through a high frequency clock and a phase splitter, i.e. a state machine equivalent to a clock divider. The phase splitter has one clock input and several outputs. The input frequency is normally the product of the output clock frequency

Figure I- 26 Figure I- 27 -

 2627 Figure I-26 -LTM4636-1 datasheet « Figure 4. Phase Selection Examples » extract.

Figure I- 28 -

 28 Figure I-28 -Renesas ISL8018 interleaving technique.As a conclusion, these systems operate in open-loop, differently than a DLL, then all delays are not necessarily equal. As a result, the phases may not be precisely interleaved, also due to the cumulative errors.

Figure I- 29 -

 29 Figure I-29 -IR XPhase TM global reference technique [20]: a) Scheme, b) Reference ramp and synchronized PWM signals.

Figure I- 30 -

 30 Figure I-30 -Global reference digital approach with local controller: a) GRÉGOIRE shared ramp (Counter) and local controller [21], b) GATEAU shared clock and local controllers [22]. Phase Splitter To improve the phase-delay accuracy, International Rectifiers introduced the XPhase3 TM trend mark, including the control IC IR3500 and the phase IC IR3505. This partial decentralized interleaving technique is similar to a shift register, where each phase IC has a Dtype flip-flop element of the shift register. A clock signal at the apparent switching frequency is sent to all modules while a closed daisy chain communication line is used to transmit the High-Side turn-on enable from one phase IC to the next. The interleaving precision is improved because the time base is generated in a single element. The control IC identifies the number of phases during start-up, and it can verify the clock line and daisy chain connections integrity during operation. Reconfiguration is easy as a phase IC can be bypassed and the clock generator can adjust the apparent frequency.

  Figure I-32 (a). In this approach, each module injects a current pulse through the shared wire in phase with its clock. Each module uses a PLL to lock the local clock in between the combined signal from the others modules, as shown by the local scheme in

Figure I- 32 Figure I- 32 -

 3232 Figure I-32 (b).The PLL couples the different clock generators and the system converges to an interleaved state, independently of the start condition and on the number of elements. In steady state, the interleaving bus voltage should be as constant as possible without subharmonic oscillations. However, the analogue approach may be exposed to mismatch and noise sensitivity issues.

Figure I- 33 -

 33 Figure I-33 -Discrete levels interleaving bus [24]: a) Modules connection scheme, b) Bus voltage principle.

  Figure I-34 (a).

Figure I- 34 -

 34 Figure I-34 -Decentralized interleaving using local measurements: a) Series case[START_REF] Dutta | Decentralized Carrier Interleaving in Cascaded Multilevel DC-AC Converters[END_REF], b) Parallel case[START_REF] Sinha | Decentralized interleaving of paralleled dc-dc buck converters[END_REF].

Figure I- 35 .

 35 In each element, a local controller positions the local triangular carrier "tri" in between the neighbor's ones "trip" and "trin", for previous and next, respectively. This approach is modular, does not present SPOF and can reconfigure by bypassing its communications, achieving a new interleaved state for any number of active modules. More recently, this implementation gained more interest and was explored in different ways. Xiao simplified the implementation in[START_REF] Xiao | Modular interleaved carrier generator using a straightforward implementation method[END_REF] using some digital logic.

Figure I- 35 -Figure I- 37 -

 3537 Figure I-35 -Circular-chain based interleaving technique[START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF].BROADMEADOW and all used in[START_REF] Broadmeadow | Self-organising technique for carrier synchronisation and phase offset distribution in modular, fault-tolerant converters[END_REF] a high speed low latency digital communication link to interleave their converters. Once a period, each module receives a synchronization message from its neighbors, as shown in Figure I-36 with the dotted arrows. A local controller identifies the message time difference, i.e. the error, then position the local carrier in the middle. This technique can present issues during reconfiguration if fast bypass is not available due to the higher communication complexity. MURRAY introduced in [31] a different technique to interleave converters using a variable frequency hysteretic current-mode control. As shown in Figure I-37, each module receives the neighbors' gate signals, then compute the average switching period and phase-shift.

  based simulations are used to validate the proposed model. A new technique is proposed in chapter IV combining the advantages of the two approaches studied in the previous chapters. It can be summarized as the use of digital communication signals, as well as the decoupling between phase-delay control and carrier generation. The first part of the study describes the different elements involved and mainly the static relationships. The second part of the study focuses on the dynamic behavior of each building block. The third part include the overall modeling, system diagonalization and stability concern. Model simulations involving modal response is shown. Fault hazard impacts are described and the expected steady-state arrangement is revealed. A proof-of-concept is developed using a printed circuit board and standard SMDs to validate the results shown, including local controllers, the start-up modal pre-positioning and fault injection devices. Practical measurements are shown to correlate with the simulation results provide by the models previously proposed. The perspectives, developed in Annex F, show the ongoing and non-accomplished works, including the integrated device developed with NXP SmartMOS10HV technology. The device consist of a converter with fully distributed control designed for parallel operation. The interleaving approach is the same presented in chapter IV. The voltage regulation is based on parallelized voltage regulators with AVP and the current balance uses a circular chain of communications to adjust the voltage references. The current balance technique is exposed and modeled, the constraints are exposed to the corrector calculation.

  that describes a digital solution to decentralized interleaving system where the carrier generators are synchronized with a shared reference clock signal. The Phase-Delay Local Controllers (PDLCs) are connected in a circular chain configuration to adjust their local Phase-Delay (PD) in between their neighboring PDs, as shown in Figure II-1. This circular chain approach is theoretically extensible to an infinite number of elements. The non-active PDLCs are simply bypassed by making a direct link between their respective neighbors in order to keep the chain of communications closed. When a reconfiguration is required, by either inserting or removing an active cell of the converter, a local decision is made to bypass or not the communications of the cell, so that the PDLCs reconfigure automatically their respective PDs without a centralized/supervisor decision. Ignoring the shared signal, this approach provide a good answer to SPOF issues by removing the notion of master.

Figure II- 1 -

 1 Figure II-1 -Circular chain of inter-cell communications composed of four PDLCs (N = 4) associated with four carrier generators.

  implementation. As a result, the PDs signals 𝜃𝜃 𝑘𝑘 are causal discrete-time signals, i.e. null for k < 0, where k is the iteration number. The discrete-domain step function is denoted 𝑢𝑢 𝑘𝑘 . The values of 𝜃𝜃 𝑃𝑃 𝑘𝑘 and 𝜃𝜃 𝑆𝑆 𝑘𝑘 are the Previous and Next neighboring PDs of the considered PDLC.

Figure II- 2 .

 2

Figure II- 2 -

 2 Figure II-2 -Block diagram of the Phase-Delay Local Controller (PDLC) using digital feedback and a carrier generator.

1 to

 1 𝑁𝑁 going by the circular chain next neighbor direction, as shown in in Figure II-1. The PDs from 𝜃𝜃 1 to 𝜃𝜃 𝑆𝑆 are then represented by a column vector θ (in bold in the following equations). In regard to the schematic shown by Figure II-2, the several error computation involved by the circular chain connection architecture can be represented using the matrix 𝑳𝑳. It is similar to the Laplacian matrix in graph theory. The matrix 𝑳𝑳, for 𝑁𝑁 equal to 6 and 𝜽𝜽 the vector of the PDs sorted in ascending order (1 to 𝑵𝑵) is shown in Eq. (II-7). It is an N-order square matrix composed of a negative unitary diagonal surrounded by factors 0.5.

  𝜺𝜺 𝜽𝜽 𝑘𝑘 = 𝑳𝑳 𝜽𝜽 𝑘𝑘 + 𝝋𝝋 (II-8) From now on, all composing elements of the model are known, particularly the matrix 𝑳𝑳 for the communication links and the vector 𝝋𝝋 for the error calculation. Figure II-4 shows a block diagram using the matrix 𝑳𝑳 operator with 𝑁𝑁 = 6. This system is linear, and the stability study can be easily performed.

Figure II- 4 -

 4 Figure II-4 -Matrix representation of the complete system with 𝑁𝑁 = 6. It derives Eq.(II-9), the open-loop discrete transfer function in the Z-domain.

  It is N-by-M matrix and is composed of the 𝑀𝑀 first columns of 𝑾𝑾. The columns of 𝑽𝑽 are named 𝑣𝑣 𝑚𝑚 with 𝜆𝜆 = 0 … 𝑀𝑀 -1. The rows of 𝑽𝑽 * and their respective spectrum with 𝑁𝑁 = 8 (𝑀𝑀 = 5) are shown in Figure II-5.

Figure II- 5 -

 5 Figure II-5 -Rows of 𝑽𝑽 * and their Spectrum (𝑁𝑁 = 8). blue/red lines: real/imaginary coefficients.

Figure II- 6 illustrates

 6 Figure II-5. If 𝑁𝑁 is even, a last eigenvalue equal to 2 is found for 𝜆𝜆 equal to 𝑁𝑁/2. In both cases, the first eigenvalue λ 0 is null.

Figure II- 6 -

 6 Figure II-6 -Eigenvalues of L for a) N = 5 (M = 3), b) N = 6 (M = 4).

Figure II- 7 -

 7 Figure II-7 -Modal root locus analysis and pole-zero locations for 𝐶𝐶(𝐶𝐶): a) proportional, b) integral, c) proportional-integral, and d) lead-lag (with N = 8 the number of PDLCs and M = 5 the number of independent modes).

  Figure II-7 (a), α = 1 places mode 4 pole on the unit circle. The proportional-integral and lead-lag controllers present double poles for each mode.As they have more freedom degrees, better pole locations can be achieved, i.e. closer to the origin and providing higher damping. The lead-leg controller's three coefficients can potentially provide a very good trade-off concerning static gain, global transient response and modal transient response.

Figure II- 8 -

 8 Figure II-8 -Eigenvalue analysis with N = 8. a) Eigenvalue 𝜆𝜆 𝐴𝐴𝑖𝑖 vs. Convergence Coefficient α, b) Polezero plot for α equal to 1, 3/4 and 1/2.

  A second option is to improve the response globally such as minimizing either the quadratic sum of the λ Am or the number of iterations 𝑘𝑘 5% of each mode. The results of these three approaches are shown in Figure II-9 for 𝑁𝑁 = 8.

Figure II- 9 -

 9 Figure II-9 -Optimized Convergence Coefficient α. Minimising criterion: absolute maximum, least squares of 𝜆𝜆 𝐴𝐴𝑚𝑚 and least squares of 𝑘𝑘 5%_𝑚𝑚 .

Figure II- 10 -

 10 Figure II-10 -Eigenvalues vs. Convergence Coefficient α for different numbers of active PDLCs (N = 5…8)All differential modes are controllable because their eigenvalues depend on the parameter α. The differential modes are double and overlap themselves two-by-two (studied together), M going from 1 to (N-1)/2. If N is even, the last mode (m = N/2) is a single mode.

  Figure II-11 shows the pole locations for different values 𝑁𝑁 of active PDLCs with α equal to 3/4 and 1.

Figure II- 11 -

 11 Figure II-11 -Root locus for α equal to 3/4 and 1 and N ranging from 6 to 10

  proposed. One possibility is to use the least squares of 𝑘𝑘 5%_m as a fonction of the convergence coefficient α and the number 𝑁𝑁 of active PDLCs, as shown in Figure

Figure II- 12 -

 12 Figure II-12 -Optimized Convergence Coefficient α using least squares of k5%_m criterion. Sensibility to 𝑁𝑁.

Figure II- 14

 14 Figure II-14 shows the simulation results of a system with eight PDLCs (N = 8) and α equal to either 1 or 6/5. Each simulation result consists of the modal disturbance applied 𝒅𝒅 * = |𝑽𝑽 * 𝒅𝒅|, the PD 𝜽𝜽 behavior, the local error 𝜺𝜺 𝜽𝜽 , and its modal decomposition |𝜺𝜺 𝜽𝜽 * |, to observe the total mode disturbance.

Figure II- 14 -

 14 Figure II-14 -Dynamic modal response (N = 8) a) α = 1; b) α = 6/5. Using the modal disturbance 𝑫𝑫(𝐶𝐶) , it is possible to distinctly observe the modal excitations of each independent mode being applied successively. The PD values behave as expected. The deviations that appear are characterized by their eigenvectors' shape behavior (kind of sine wave) and their cycle number, as shown in Figure II-5. For the case illustrated in Figure II-14 (a), all modes are correctly damped. For the case in Figure II-14 (b), the mode 4 (𝜆𝜆 = 4) is at its stability limit as demonstrated by the stability criterion. So it oscillates without damping because one pole value is equal to -1. This simulation confirms the expected value of the number of iterations required for convergence forecasted in Table II-2. It can be seen with 𝛼𝛼 = 1 case, all modes have different oscillation frequencies (different damping), but almost the same settling time as a result of the harmonization obtained using least squares strategy.

Figure II- 3 .

 3 Thus, there is a discontinuity between the last and the first PD due to the trigonometric circle itself, and therefore the operator 𝑳𝑳 does not work for all PDLCs. Using normalized PD, the discontinuity appears when the PD approaches the value 1 from the negative side, as shown in the Figure, but also when the PD approaches 0 from the positive side.

Figure II- 15

 15 Figure shows a well-interleaved system with five carriers ( 𝑁𝑁 = 5 ) where the normalized PD differences are all equal to 0.2 (1/𝑁𝑁). The PD error has to be equal to zero.

Figure II- 15 Figure II- 15 -

 1515 Figure II-15 (c) shows the expected target position 𝜃𝜃 � 1 for the first carrier and the computed average value of the positions of its neighbors. These two values are different and in phase opposition.

  illustrate the phase-delay target operator necessity, the values of the PD column vectors 𝜽𝜽 and 𝑳𝑳 𝜽𝜽 are shown in Eq. (II-38) and Eq. (II-39) respectively, using the position values relative to the well-interleaved system shown in Figure II-15 (b). 𝜽𝜽 = [ 0.1 0.3 0.5 0.7 0.9 ] 𝑇𝑇 (II-38) 𝑳𝑳 𝜽𝜽 = [ 0.5 0.0 0.0 0.0 -0.5 ] 𝑇𝑇 (II-39)As anticipated, the 𝑳𝑳 𝜽𝜽 operation, required to compute the several local errors, does not give the null error vector expected for a well-interleaved system. As the error operator result is wrong, the PDLCs having a neighbor across the discontinuity (𝜃𝜃 1 and 𝜃𝜃 5 ) have a local error different from zero. This value can be compensated by an additive term 𝝋𝝋 introduced earlier, as shown in Eq. (II-8). In this particular case, the required 𝝋𝝋 value evaluated from a wellinterleaved system is given in Eq. (II-40).𝝋𝝋 = -𝑳𝑳 𝜽𝜽 = [ -0.5 0.0 0.0 0.0 0.5 ] 𝑇𝑇 (II-40)

Figure II- 16

 16 Figure shows another case where the system is well interleaved but all the PDs are shifted by -0.2 units. It uses the same 𝝋𝝋 vector described in Eq. (II-40). As shown, the discontinuity position is no longer around zero, and 𝜃𝜃 1 may be smaller than zero. Thus, some PDs values may be now outside the range from 0 to 1.

Figure II- 16 -

 16 Figure II-16 -Correct interleaving obtained using the 𝝋𝝋 vector (some PDs values are outside the range [0, 1]).

  Figure II-17. The first condition prevents undesired disturbances during start-up, when neighboring PD can be coincident. It can be seen in [22], during start-up, the PD in phase opposition is moving while it remains correctly in the middle of its neighbors. This condition makes PD in phase opposition constant only at the beginning, achieving better transient response and avoiding undesired disturbances. When neighboring PD are different, the target PD is corrected depending on the neighboring PD arrangement and on the local PD. The discontinuity handler adjusts the target value. It is trigged when the neighbors PDs are in a decreasing ordering, i.e. 𝜃𝜃 𝑃𝑃 > 𝜃𝜃 𝑆𝑆 . Then a correction is made based on the local PD value. It should be noted the target value can be outside the PD normal range. It happens when

Figure II- 17 -

 17 Figure II-17 -Phase-delay Local Controller Flowchart.

Figure II- 18

 18 Figure II-18 (a) and (b) show other cases where the phase differences are equal to 2/N.

Figure II- 18 - 1 𝜃𝜃 = 𝜃𝜃 - 1 𝜃𝜃 = 𝜃𝜃 + 1 𝜃𝜃 < 0

 181110 Figure II-18 -Interleaving issue when phase differences are equal to 2/N: a) N odd case (N = 5), b) N even case (N = 6).

𝜃𝜃 3 >

 3 arrangements on Figure II-15 (a) and Figure II-16 are PIA because only 𝜃𝜃 5 > 𝜃𝜃 1 and 𝜃𝜃 1 > 𝜃𝜃 2 , respectively. It can be noted that the arrangements on Figure II-18 are not PIA because in (a) 𝜃𝜃 4 and 𝜃𝜃 5 > 𝜃𝜃 1 and in (b) 𝜃𝜃 3 > 𝜃𝜃 4 and 𝜃𝜃 6 > 𝜃𝜃 1 . So the summation in (II-45) is higher than 1. Examples of these cases will be given in the next section.

Figure II- 19 Figure II- 19 -/ 5 . 3 *

 191953 Figure II-19 shows two reconfiguration simulations starting with nine well-interleaved PDLCs. The PDLC3 is disabled and bypassed at the first iteration, then the eight remaining active PDLCs reconfigure and reach another interleaving state. These eight PDLCs have the same dynamics revealed previously.Figure II-19 (a) shows the reconfiguration response with α = 1, and Figure II-19 (b) shows the reconfiguration response with α = 6/5.

Figure II- 20

 20 Figure II-20 shows two reconfiguration simulations with eight PDLCs. At the beginning, seven PDLCs are well interleaved, and PDLC5, pre-positioned or not, is inserted. These eight PDLCs have the same dynamics as those revealed previously with α = 1 to ensure stability.

Figure II- 20 Figure II- 20 -

 2020 Figure II-20 (a) shows the reconfiguration response where PD5 is pre-positioned in between its neighbors, and Figure II-20 (b) shows the case where its initial value is null.

Figure II- 21 -

 21 Figure II-21 -Start-up response (N = 8): a) one element in phase opposition (1+7), b) with two separated groups (4+4).

  time, e.g. chose case (b) if the mode 1 is the slower, choose (a) if mode 4

  For the proportional corrector, the modal poles, i.e. eigenvalues, can still be easily evaluated as a function of α by Eq. (II-28). The eigenvalues λ 𝐴𝐴𝑖𝑖 of the differential modes (𝜆𝜆 = 1 … 𝑁𝑁 -1) can be computed as previously and are shown in Figure II-22 for 𝑁𝑁 going from 5 to 8. The important major difference is the system is unconditional stable even if α is equal to 1.

Figure II- 22 -

 22 Figure II-22 -One constant PD: Eigenvalues vs. Convergence Coefficient for N from 5 to 8.

Figure II- 23 Figure II- 23 -

 2323 Figure II-23 shows two simulation results using the same conditions described previously, but 𝜃𝜃 1 is constant to 0. At the first iteration, PDLC3 is removed from the chain of communications. As PDLC1 provides a constant PD, its error is never corrected locally (blue line), and the other PDs have to change their value to cancel their own local error, and consequently PDLC1 error. In case (a), |𝜀𝜀 𝜃𝜃 * | 7 is quickly reduced to zero while |𝜀𝜀 𝜃𝜃 * | 1 dominates

6 *

 6 Figure II-24 -PDLC with multiple feedback and its representation with a common corrector 𝐶𝐶(𝐶𝐶).

𝑳𝑳 1 = 1 .

 11 𝑳𝑳 and 𝜦𝜦 1 = 𝜦𝜦. It can be shown the 𝜆𝜆 𝑡𝑡ℎ diagonal element of 𝜦𝜦 j noted λ 𝑖𝑖 𝑗𝑗 = cos 2 𝜋𝜋 𝑖𝑖 𝑗𝑗 𝑆𝑆 -The homogeneous system closed-loop discrete transfer function ( 𝝋𝝋(𝐶𝐶) = 0 ) is represented by Eq. (II-54).𝜽𝜽(𝐶𝐶) = �𝐶𝐶𝑰𝑰 -�𝑰𝑰 + 𝐶𝐶(𝐶𝐶) � 𝑘𝑘 𝑗𝑗 𝑳𝑳 𝑗𝑗

  𝜽𝜽 * (𝐶𝐶) = �𝐶𝐶𝑰𝑰 -�𝑰𝑰 + 𝐶𝐶(𝐶𝐶) � 𝑘𝑘 𝑗𝑗 𝜦𝜦 II-55) can be rewritten as 𝑁𝑁 independent transfer functions as shown in Eq. (II-56) because all matrices in Eq. (II-55) are diagonal.

Figure II- 25 -

 25 Figure II-25 -Start-up simulation (𝑁𝑁 = 9), (1+8): a) 𝑘𝑘 1 = 0.4, 𝑘𝑘 3 = 0.3, b) 𝑘𝑘 1 = 0.1, 𝑘𝑘 3 = 0.6.

  strategy has been developed. It highlights the existence of several modal responses whose number and dynamics depend on the number of carriers involved in the system. The stability criterion has been established for any number of active local controllers used. A convergence speed parameter has been defined to choose an appropriate convergence coefficient value for each application case. Examples have been given to show the resulting modal dynamics for different values of convergence coefficient.

  Figure III-1 shows a schematic view of the several TCGs connected with their neighbors forming a closed chain of inter-module communications. The TCG is composed by three elements, a bypass circuit, a Triangular Signal Generator (TSG) and an adjustable gain differential amplifier (𝛽𝛽) as a controller.

Figure III- 1 -

 1 Figure III-1 -Triangular Carrier Generators exchanging analog waveforms to interleave themselves.

  𝜆𝜆 𝑡𝑡ℎ TSG generates a triangular signal 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖_𝑖𝑖 . It should be noted that, in the following explanations, all signals 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖 generated are considered ideal. They are symmetrical, have constant slew-rate value ±𝑆𝑆 𝑅𝑅 and are bounded by two threshold voltages, a lower limit 𝑣𝑣𝑙𝑙 and an upper limit 𝑣𝑣ℎ, resulting in a signal with free running frequency 𝑓𝑓 0 , period 𝑖𝑖 0 . The 𝑓𝑓 0 expression is shown in Eq. (III-1) when the voltage thresholds are the constant values 𝑉𝑉 𝑚𝑚 and 𝑉𝑉 𝑂𝑂 . 𝑓𝑓 0 = 0.5 𝑆𝑆 𝑅𝑅 𝑉𝑉 𝑚𝑚 -𝑉𝑉 𝑂𝑂 (III-1) To obtain interleaved carriers, each module has to place the local triangular signal 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖 PD in between its Previous and Next neighboring TCGs triangular signals 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 and 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑆𝑆 phase delays, respectively. It can be obtained by superimposing 𝑉𝑉 𝑚𝑚 and 𝑉𝑉 𝑂𝑂 with an auxiliary signal 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 , where 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 is a factor 𝛽𝛽 of the difference of the neighboring triangular signals 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 and 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑆𝑆 , shown in Eq. (III-2), generated with the adjustable gain (𝛽𝛽) differential amplifier. 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 (𝑑𝑑) = 𝛽𝛽 �𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 (𝑑𝑑) -𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑆𝑆 (𝑑𝑑)� (III-2) Thus, the generated triangular signal 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖 amplitude is modulated, affecting its PD. By geometrical construction, 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖 is guided in phase to reach its steady-state position. The control input signal 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 turns the TSG into a Voltage Controlled Oscillator (VCO). This neighbor connections are effectively feedback-loops that lead each triangular signal to center itself in between its two neighbors. When a given number 𝑁𝑁 ≥ 3 of TCGs are connected together in a circular chain, all PDs are correct and the carriers tend to be located in the middle of its neighbors, resulting in a well interleaved system. Figure III-2 shows the principle of operation waveforms, where 𝑣𝑣ℎ(𝑑𝑑) = 𝑉𝑉 𝑚𝑚 + 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 (𝑑𝑑) and 𝑣𝑣𝑙𝑙(𝑑𝑑) = 𝑉𝑉 𝑂𝑂 + 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 (𝑑𝑑).

Figure III- 2 -III. 1 . 1 .

 211 Figure III-2 -Triangular Carrier Self-Alignment principle of operation, Phase-Advance case reaching a stable position [28].

Figure III- 3 -

 3 Figure III-3 -Triangular signal time delay measurement.When 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖 has a higher amplitude than 𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚 , going out of the 𝑉𝑉 𝑂𝑂 to 𝑉𝑉 𝑚𝑚 range, then ∆𝑑𝑑 𝑉𝑉 𝑡𝑡𝑡𝑡𝑡𝑡 𝑘𝑘

Figure III- 4

 4 Figure III-4 shows the time delay and phase delay plot for modeling with the values shown in Figure III-3.

Figure III- 4 -

 4 Figure III-4 -Time delay measurement plot for modeling.

Figure III- 5

 5 Figure III-5 shows details of the signal waveforms involved in a given TCG. 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 and 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑆𝑆 are the triangular signals of the Previous and Next neighboring TCGs. The values 𝜃𝜃 𝑃𝑃 and 𝜃𝜃 𝑆𝑆 are the related PDs. 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 is the local threshold voltage from Eq. (III-2) superimposed over 𝑉𝑉 𝑚𝑚 . The target position 𝜃𝜃 � 𝑘𝑘 is located at the crossing of 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 and 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑆𝑆 . The target local generated triangular signal is named 𝑉𝑉 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 .

Figure III- 5 -

 5 Figure III-5 -Target position shown based on of neighbor positions.

Figure III- 5

 5 Figure III-5 shows that at the iteration 𝑘𝑘, 𝑉𝑉 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 has already commutated, so its PD is already updated from 𝜃𝜃 𝑃𝑃 𝑘𝑘 to 𝜃𝜃 𝑃𝑃 𝑘𝑘+1 . This is natural due to the sequential nature of the commutations, i.e. the commutations are not simultaneous. Therefore, at a given iteration 𝑘𝑘, the target position 𝜃𝜃 � 𝑘𝑘 represents the average value of 𝜃𝜃 𝑃𝑃 𝑘𝑘+1 and 𝜃𝜃 𝑆𝑆 𝑘𝑘 values, as indicated in Eq.

Figure III- 6

 6 Figure III-6 shows a block diagram of all previously described PD operations. It reveals that the triangular carrier self-alignment system is similar to the one made up of discrete Local Controller (LC) previously presented. This model can be used for stability and convergence studies. As all PDs are measured regarding the same reference signal 𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚 , the iterations of all LCs happen at the same instant (𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚 peak/valley), simplifying the whole system modelling.

Figure III- 6 -

 6 Figure III-6 -PD local Controller block diagram. Eq. (III-9) gives the latest local PD obtained 𝜃𝜃 𝑘𝑘+1 by successive substitutions of all previous equations (III-5) to (III-8). The next local PD 𝜃𝜃 𝑘𝑘+1 depends on the next Previous neighbor PD 𝜃𝜃 𝑃𝑃 𝑘𝑘+1 , resulting in a non-causal system. 𝜃𝜃 𝑘𝑘+1 = (1 -𝛼𝛼) 𝜃𝜃 𝑘𝑘 + 0.5 𝛼𝛼 �𝜃𝜃 𝑃𝑃 𝑘𝑘+1 + 𝜃𝜃 𝑆𝑆 𝑘𝑘 � + 𝛼𝛼 𝜑𝜑 𝑘𝑘 + 𝜃𝜃 𝑘𝑘 (III-9)

  Figure III-7 shows the discrete time model block diagram based on Eq. (III-15). This system is linear, and the stability study can be easily performed.

Figure III- 7 -

 7 Figure III-7 -Triangular carrier self-alignment full system block diagram.Eq. (III-16) is the recurrence expression of 𝜽𝜽 𝑘𝑘+1 find from Eq. (III-15) as a function of 𝜽𝜽 𝑘𝑘 and the inputs 𝝋𝝋 𝑘𝑘 and 𝒅𝒅 𝑘𝑘 . The system is causal and depends on the actual PD values and on the actual inputs.

Figure III- 8 -

 8 Figure III-8 -Correction as a function of the local error 𝜀𝜀 𝜃𝜃 and the neighbor delays 𝛥𝛥𝜃𝜃 𝑃𝑃,𝑆𝑆 for 𝛼𝛼 = 1.0. Three regions can be distinguished in Figure III-8: 1) a linear region in green where the correction is proportional to the error, i.e. 𝛥𝛥𝜃𝜃 = 𝛼𝛼 𝜀𝜀 𝜃𝜃 ; 2) a saturation region in blue where 𝛥𝛥𝜃𝜃 is limited; 3) a dead-zone in red where the correction is null to any error value. The model is then only valid in the region 1 where the correction is proportional to the error.

  form. As all matrices involved in this system (𝑰𝑰, 𝑺𝑺 and 𝑺𝑺 * ) are circulanting, they are all diagonalizable with the Discrete Fourier Transform (DFT) matrix, shown in Section II.2.1. The diagonal expression of 𝑺𝑺 and 𝑺𝑺 * are provided in Eq. (III-18), where 𝑼𝑼 and 𝑼𝑼 * are the diagonal eigenvalue matrices of 𝑺𝑺 and 𝑺𝑺 * respectively. One can note that 𝑺𝑺 and 𝑼𝑼 are the matrices normally referred to as "shift and clock matrices" respectively, introduced by J. J. Sylvester in the 1880s. 𝑼𝑼 = 𝑾𝑾 * 𝑺𝑺𝑾𝑾 𝑼𝑼 * = 𝑾𝑾 * 𝑺𝑺 * 𝑾𝑾 (III-18) A change of basis expressed by the set of Eq. (III-19) is applied to the system. 𝜽𝜽 * = 𝑾𝑾 * 𝜽𝜽 𝝓𝝓 * = 𝑾𝑾 * 𝝓𝝓 𝜺𝜺 𝜽𝜽 * = 𝑾𝑾 * 𝜺𝜺 𝜽𝜽 𝜽𝜽 𝟎𝟎 * = 𝑾𝑾 * 𝜽𝜽 𝟎𝟎 (III-19)

Figure III- 9 -

 9 Figure III-9 -Root locus for 𝑁𝑁 = 8 with pole-zero mapping for tree particular cases: 𝛼𝛼 = 0.75, 𝛼𝛼 = 1.0 and 𝛼𝛼 = 1.5.

  Figure III-9 shows dotted lines as a function of the eigenvalue angle 𝜌𝜌, ranging between 0 and 2π, for several given α values. The lines λ 𝐴𝐴 (𝜌𝜌, α) are independent of 𝜆𝜆, showing the locations where the eigenvalues will land for any 𝑁𝑁 values. The non-plotted line λ 𝐴𝐴 (𝜌𝜌, α = 2.0) is coincident with the unit circle, as shown in Eq. (III-26).

  the response time, have to be reduced to speed-up the global response on any type of disturbance.As these values depend on α, a criterion has to be established to find a trade-off. Supposing all modes have the same importance, the criterion to choose the optimal configuration can be the quadratic sum. The quadratic sum can be applied on the eigenvalues or on the number of iterations k5% of each differential mode. Only the differential modal values (𝜆𝜆 = 1 … 𝑀𝑀 -1) are considered in order not to overweight the double modes. These two approach results are shown in the plot of Figure III-10 for 𝑁𝑁 = 8.

Figure III- 10 -

 10 Figure III-10 -Optimized Convergence Coefficient α. Minimising criterion: least squares of 𝜆𝜆 𝐴𝐴𝑚𝑚 and least squares of k5%_m.

  computed for several number of active LCs required in the application. The root locus analysis for the cases of 𝑁𝑁 = 4 … 9 are shown in Figure III-11 with the gain 𝛼𝛼 ranging from 0 to 2.

Figure III- 11 -

 11 Figure III-11 -Root locus for 𝑁𝑁 = 4 … 9 with 𝛼𝛼 ranging from 0 to 2.

  verified. A parametric plot of the least squares of 𝑘𝑘 5% as a function of the convergence coefficient 𝛼𝛼 and the value of 𝑁𝑁 is shown in Figure III-12.

Figure III- 12 -

 12 Figure III-12 -Optimized Convergence Coefficient α using least squares of 𝜆𝜆 𝐴𝐴 and k5% criterion. Sensibility to 𝑁𝑁.

Figure III- 13 Figure III- 13 -

 1313 Figure III-13 shows the simulation results of a system with eight LCs (𝑁𝑁 = 8) and α equal to either 0.8 or 1. Each simulation result is composed of the modal disturbance applied 𝒅𝒅 * = |𝑾𝑾 -1 𝒅𝒅| , the PD 𝜽𝜽 waveforms, and the local error 𝜺𝜺 𝜽𝜽 modal decomposition |𝜺𝜺 𝜽𝜽 * | toobserve the total mode disturbance. For simulation purposes, the target operator introduced in the digital case is required. Eq. (14) is taken to find the 𝝋𝝋 required considering 𝒅𝒅 = 𝟎𝟎 and

Figure III- 14

 14 Figure III-14 (a) shows a simulation starting with nine well-interleaved TCGs. The local controller TCG3 is disabled and bypassed at the first iteration, then the eight active TCGs reconfigure and reach another interleaving state with α = 1.0.

Figure III- 14 Figure III- 14 -

 1414 Figure III-14 (b) shows a reconfiguration simulation starting with seven wellinterleaved TCGs. The local controller TCG5 is disabled and positioned in between its neighbors. TCG5 becomes visible at the first iteration, then the eight active TCGs reconfigure and reach another interleaving state.

Figure III- 16 ,

 16 Figure III-16, Figure III-17 and Figure III-18 show two simulations each with 8 active TCGs to reveal the behavior of a system in (a) with limited positive gain 𝛽𝛽 (𝛼𝛼 = 1, 𝛽𝛽 = 0.5) and in (b) a system with comparators (𝛼𝛼 = 2, 𝛽𝛽 → +∞). The clock and triangular signals are shown on the top and bottom, respectively, with the following color code:

Figure III- 16 -Figure III- 17 -

 1617 Figure III-16 -Simulation Mode 2: a) 𝛼𝛼 = 1, 𝛽𝛽 = 0.5; b) 𝛼𝛼 = 2, 𝛽𝛽 → +∞.

Figure III- 18 -

 18 Figure III-18 -Simulation Mode 4: a) 𝛼𝛼 = 1, 𝛽𝛽 = 0.5; b) 𝛼𝛼 = 2, 𝛽𝛽 → +∞.As expected, based on the z-domain model, all modes are damped when 𝛽𝛽 is a limited positive gain (𝛼𝛼 = 1, 𝛽𝛽 = 0.5). According with the proposed model, the ideal system with comparators (𝛼𝛼 = 2, 𝛽𝛽 → +∞) and without delays results in non-damped oscillations. The model satisfactorily represents the transient performance, showing the stability limit when 𝛽𝛽 → +∞, resulting in all poles close to the unitary circle.

Figure III- 19 Figure

 19 Figure III-19 shows two simulations to reveal the start-up response of a system with α = 1. In (a) start-up by groups (4+4) and (b) start-up in phase opposition(1+7).

Figure III- 20

 20 Figure III-20 show a simulation of the particular case using comparators (α = 2, β → +∞) introduced by XIAO. In the simulation, only Mode 4 is disturbed at the beginning and triangular signals kept between 𝑉𝑉 𝑂𝑂 and 𝑉𝑉 𝑚𝑚 .

Figure III- 20 -

 20 Figure III-20 -Simulation Mode 4 using comparators (𝛼𝛼 = 2, 𝛽𝛽 → +∞) with triangular signals kept between 𝑉𝑉 𝑂𝑂 and 𝑉𝑉 𝑚𝑚 . It can be noted in Figure III-20 that the system converges slowly to the expected steadystate interleaving, even if α = 2, β → +∞.

  a. Matching issues: the control is based on arithmetical operations over analog signals; Each local controller and carrier generator has its own local references (voltages, currents). They can be slightly different from one to the other. On one hand, comparing two mismatched signals leads to make inevitable mistakes. On the other hand, comparing the time delay between two digital signals based on their rising and falling edges avoid all mismatch issues. b. Low noise immunity: the external analog signals are used to generate the local phase correction. The self-alignment principle is based on modifying the local Schmitt trigger thresholds using the difference of the neighbors' triangular carrier analog signals. In that case, any external electrical noise injection can alter the Schmitt trigger commutation instant and therefore the phase position accuracy. Filtering the control signal is not recommended because it would add an additional phase-delay on the commutation and generate a systematic error. c. Disturbance issues: PWM disturbance during reconfiguration due to transient on carrier amplitudes; The Schmitt trigger thresholds are strongly affected during the transient/reconfiguration event, leading to affect the several carrier amplitudes. Therefore, the duty-cycles of the PWM signals are also affected, resulting in transient on both output voltage regulation and leg current balance. To avoid this issues, the carrier amplitudes have to remain constant. Note that, to implement the self-interleaving function, the carrier slope may be changed instead of the Schmitt trigger thresholds, but the slope values should be kept constant during the whole period. d. Closed-loop issues: trade-off between settle time and static error;

a.

  Avoid comparing analog signals from different sources; b. Avoid using an external analog signal to control directly the local phase-delay; c. Avoid altering the carrier shape during a period; d. Use a more sophisticated controller transfer function; e. Use a local control structure made of several dissociated functions (local controller + VCO); f. Mutualize connections if possible.

FigureFigure IV- 1 -

 1 Figure IV-1 -Phase-Locked Loop: a) Classical, b) Expected self-interleaving block diagram.

  Figure IV-1(b) shows an example of the expected block diagram of the circular-chain interleaving module that dissociates clearly each function block of the structure.

(

  PD) is the same as the triangular signal PD. The triangular carrier generator based on operational amplifiers can be slightly modified to become a classic VCO, such as the one shown in Figure IV-2 from Texas Instruments® LM358 datasheet. The equivalent signals OUTPUT1, OUTPUT2 and +𝑉𝑉 𝑆𝑆 * will be called 𝑐𝑐𝑙𝑙𝑘𝑘, 𝑣𝑣 𝑡𝑡𝑡𝑡𝑖𝑖 and 𝑢𝑢, respectively, in this study. Here, the level of the signal 𝑢𝑢 imposes the clock frequency. The peak of the triangular signals is aligned with the clock rising-edge and its valley is aligned with the clock falling-edge.

Figure IV- 2 -

 2 Figure IV-2 -Texas Instruments LM358 datasheet: VCO and triangular carrier generator. Now, if the edges of the square clock signals involved in the system are equally spaced in time, so the square clock signals become interleaved. So the triangular signals will be interleaved accordingly.

Figure IV- 3 - 5 2 - 2 4 (IV- 3 )

 35243 Figure IV-3 -Phase detector operations on digital signals (outputs of the Schmitt triggers): a) carrier correctly positioned, b) carrier slightly late. Eq. (IV-1) develops the required phase detector expressions used in Figure IV-3.

Figure IV- 4 -

 4 Figure IV-4 -Perceived error with XOR phase detector.

Figure IV- 4

 4 Figure IV-4 shows that the response of DPD described in Eq. (IV-3) results in 4 distinct regions: a. Linear region (green): perceived error 𝜀𝜀 𝜃𝜃 ′ equals to 𝜀𝜀 𝜃𝜃 ; b. Saturation region (blue): perceived error 𝜀𝜀 𝜃𝜃 ′ non null and do not varies with 𝜀𝜀 𝜃𝜃 ; c. Reverse region (pink): perceived error 𝜀𝜀 𝜃𝜃 ′ decreases while 𝜀𝜀 𝜃𝜃 increases. d. Dead zone (red): perceived error 𝜀𝜀 𝜃𝜃 ′ null while 𝜀𝜀 𝜃𝜃 non null;It should be noted that all initial condition complying with a Proper Interleaving Arrangement (PIA) are in the DPD linear region and leads consequently to a correct interleaving if the system is stable and the disturbances are moderated.

  bounds of 𝜀𝜀 𝜃𝜃 ′ = 𝜀𝜀 𝜃𝜃 , such as the case of start-up by groups (∆𝜃𝜃 𝑃𝑃,𝑆𝑆 = 0.50, |𝜀𝜀 𝜃𝜃 | = 0.25) and the singular case of reconfiguration from 4 to 3 active carriers (𝜃𝜃 𝑃𝑃 -𝜃𝜃 𝑆𝑆 = 0.75, |𝜀𝜀 𝜃𝜃 | = 0.25).

  durations of the phase detector output signals 𝑈𝑈𝛥𝛥 and 𝐷𝐷𝑁𝑁 are converted into an equivalent amount of charges by the charge-pump circuit. It should be noted that the chargepump output is a current named 𝜆𝜆 𝑃𝑃 with high frequency content because the current sources are switched. As the name explains, the Loop Filter remove the high frequency content and sets the PLL closed-loop behavior. The system proposed here must have the VCO voltage constant in between periods, requiring them a very low cut-off frequency. However, it implies in a very limited transient response. To filter properly the CP current and have a good transient response, the loop filter will be divided in two: a periodic average circuit and a generic controller. Its simplified electrical diagram is shown in Figure IV-5.

Figure IV- 5 -

 5 Figure IV-5 -Simplified electrical diagram used to compute the periodic average of the charge-pump current.

  Figure IV-6 shows the current 𝜆𝜆 𝑆𝑆 waveform of the charge-pump circuit when the local carrier is constant and the neighbor's difference is kept constant ∆𝜃𝜃 𝑃𝑃,𝑆𝑆 = 0.5. At the same time, the neighbor's frequency changes so that the PDs change to produce a local error in a cosine shape with an amplitude of 0.25 and a period equal to 10 carrier periods. It is clearly shown that the current 𝜆𝜆 𝑆𝑆 is directly dependent of the interleaving error and consequently the amount of charges provided to (blue area) or removed from (pink area) the capacitor.

Figure IV- 6 -

 6 Figure IV-6 -Current of the charge-pump circuit 𝜆𝜆 𝑆𝑆 as a function of the neighbor's PD (with 𝜃𝜃 𝑆𝑆 -𝜃𝜃 𝑃𝑃 = 0.5), the fundamental 𝜆𝜆 𝑆𝑆 1/10 𝑚𝑚 0 and the periodical average 〈𝜆𝜆 𝑆𝑆 〉 𝑇𝑇 0 . The 𝜆𝜆 𝑆𝑆 fundamental harmonic waveform 𝜆𝜆 𝑆𝑆 1/10 𝑚𝑚 0 at 1/10 of the carrier frequency is shown. The curb 〈𝜆𝜆 𝑆𝑆 〉 𝑇𝑇 0 is the periodic average of 𝜆𝜆 𝑆𝑆 , i.e. a constant current applied within the period 𝑖𝑖 0 , between 𝑘𝑘 𝑖𝑖 0 and (𝑘𝑘 + 1) 𝑖𝑖 0 . Both signals 𝜆𝜆 𝑆𝑆 and 〈𝜆𝜆 𝑆𝑆 〉 𝑇𝑇 0 are representative of the error. It is confirmed by their Fast Fourier transform shown in Figure IV-7, where the frequency axis is normalized to the carrier frequency.

Figure IV- 7 -

 7 Figure IV-7 -Normalized Fast Fourier Transform (FFT) of 𝜆𝜆 𝑆𝑆 and 〈𝜆𝜆 𝑆𝑆 〉 𝑇𝑇 0 .

  Figure IV-8 shows a simplified block diagram representing the LC internal elements, where 𝐶𝐶(𝑖𝑖) and 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) are the controller and the VCO transfer functions respectively. As shown in the figure, it is assumed that an additional noise signal 𝑒𝑒(𝑑𝑑) appears at the corrector input and also an additional disturbance signal 𝜃𝜃(𝑑𝑑) appears at the VCO input.

Figure IV- 8 -

 8 Figure IV-8 -Small signal block diagram representing one LC elements.In our application, described later, the corrector 𝐶𝐶(𝑖𝑖) is composed by an operational amplifier with a feedback loop. Its transfer function, noted 𝐶𝐶(𝑖𝑖) = 𝑈𝑈(𝑖𝑖) 𝐸𝐸(𝑖𝑖) ⁄ , will be chosen later.

Figure IV- 9

 9 Figure IV-9 shows a simulation result involving the signals of Figure IV-5 and Figure IV-8. On top of the figure are shown three analog triangular carriers 𝑣𝑣 𝑡𝑡𝑡𝑡𝑖𝑖𝑃𝑃 , 𝑣𝑣 𝑡𝑡𝑡𝑡𝑖𝑖 and 𝑣𝑣 𝑡𝑡𝑡𝑡𝑖𝑖𝑆𝑆 , related to the previous, local and next PDLC respectively. For each of them, the associated digital clock signals 𝑐𝑐𝑙𝑙𝑘𝑘 𝑃𝑃 , 𝑐𝑐𝑙𝑙𝑘𝑘 and 𝑐𝑐𝑙𝑙𝑘𝑘 𝑆𝑆 are also shown, which are the Schmitt trigger output signals used by the local carrier generators of Figure IV-2. In one carrier generator, the carrier and the clock signals are always locked in the same phase and frequency because one is constructed based on the other. It should be noted that the clock edges are aligned with the peak and valley of the triangular signal.

Figure IV- 9 -

 9 Figure IV-9 -Simulation of the single edge error PD measurement method. The static relationship between the charge-pump current and the clock signal PDs has been shown in the last section. Now, the dynamic relationship existing between the three clock signals 𝑐𝑐𝑙𝑙𝑘𝑘 𝑃𝑃 (𝑑𝑑), 𝑐𝑐𝑙𝑙𝑘𝑘(𝑑𝑑), 𝑐𝑐𝑙𝑙𝑘𝑘 𝑆𝑆 (𝑑𝑑) and the sampled PD error 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) has to be revealed. The expression of the maintained voltage 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) , shown in Eq. (IV-5), is the convolution of 𝑣𝑣 𝑆𝑆 * (𝑑𝑑), the capacitor 𝐶𝐶 sampled voltage, ℎ ZOH (𝑑𝑑), the Zero-Order hold impulse response, and 𝑟𝑟𝑒𝑒𝑐𝑐𝑑𝑑(•) is the rectangular function. 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) = 𝑣𝑣 𝑆𝑆 * (𝑑𝑑) * ℎ ZOH (𝑑𝑑) where ℎ ZOH (𝑑𝑑) = 𝑟𝑟𝑒𝑒𝑐𝑐𝑑𝑑 � 𝑑𝑑 -𝑖𝑖 0 /2 𝑖𝑖 0 � (IV-5)

  ) = � 𝑣𝑣 C (𝑘𝑘 𝑖𝑖 0 )

IV. 3 . 3 .

 33 It can be observed that the block diagram inFigure IV-8 is not coherent with this transfer function because the delay transfer functions 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑃𝑃 (𝑖𝑖) and 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑆𝑆 (𝑖𝑖) are missing, being valid only in the case where 𝜃𝜃 𝑃𝑃 and 𝜃𝜃 𝑆𝑆 are constant. Plant transfer function It is proposed here to consider the plant transfer function noted 𝛥𝛥(𝑖𝑖) , i.e. the combination of process and actuator transfer functions, as the function composed of 𝑉𝑉 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) and 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖), where 𝑉𝑉 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) is composed by the three first terms of 𝑉𝑉 ε 𝜃𝜃 (𝑖𝑖), while the last two terms are equivalent to the loop subtractor and the error calculation. The plant transfer function is shown in Eq. (IV-17

Figure IV- 10

 10 Figure IV-10 shows bode diagram of 𝛥𝛥(𝑖𝑖) to the presented applicative case.

Figure IV- 10

 10 Figure IV-10 -P(s) bode diagram with phase and gain margins.

9 .

 9 74 dB (at 2.2e+04 Hz) , Pm = 57.8 deg (at 7.85e+03 Hz) Frequency (Hz) and then represented by a column vector 𝜽𝜽 (in bold in the following equations). The order of all matrices and vectors is 𝑁𝑁. The block diagram representing the all the elements of this interleaving system is shown in Figure IV-11.

Figure IV- 11 -

 11 Figure IV-11 -Overall system model block diagram.

  𝜽𝜽 � (𝑑𝑑) = 0.5 [𝜽𝜽 𝑃𝑃 (𝑑𝑑) + 𝜽𝜽 𝑆𝑆 (𝑑𝑑)] + 𝝋𝝋(𝑑𝑑)(IV-[START_REF] Zhang | A novel distributed interleaving scheme to achieve scalable phase design for microprocessor power management[END_REF] The PD error in the vector format, noted 𝜺𝜺 𝜃𝜃 (𝑑𝑑), is shown in Eq. (IV-20), where 𝑳𝑳 is a matrix representing the circular chain connections.𝜺𝜺 𝜃𝜃 (𝑑𝑑) = 𝜽𝜽 � (𝑑𝑑) -𝜽𝜽(𝑑𝑑) = 𝑳𝑳 𝜽𝜽(𝑑𝑑) + 𝝋𝝋(𝑑𝑑) (IV-20)The Laplace transform of the error 𝜺𝜺 𝜃𝜃 (𝑑𝑑) is noted 𝚬𝚬 𝚯𝚯 (𝑖𝑖) and shown in Eq. (IV-21). 𝜠𝜠 𝚯𝚯 (𝑖𝑖) = 𝑳𝑳 𝚯𝚯(𝑖𝑖) + 𝚽𝚽(𝑖𝑖) (IV-21) However, the error detector circuit of Figure IV-8 cannot detect directly 𝜀𝜀 𝜃𝜃 , only the voltage 𝑣𝑣 𝜀𝜀 𝜃𝜃 related to it. The 𝑉𝑉 ε 𝜃𝜃 (𝑖𝑖) expression in the single loop case shown by Eq. (IV-16) can be rewritten in the matrix format noted 𝑽𝑽 ε 𝜃𝜃 (𝑖𝑖) as detailed in Eq. (IV-22). 𝑽𝑽 ε 𝜃𝜃 (𝑖𝑖) = 2 𝐼𝐼 P 𝑖𝑖 0 𝐶𝐶 𝑉𝑉 𝑍𝑍𝑂𝑂𝑚𝑚 (𝑖𝑖) 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑 (𝑖𝑖) 𝜠𝜠 𝚯𝚯 ′(𝑖𝑖) (IV-22) where 𝜠𝜠 𝚯𝚯 ′(𝑖𝑖), shown in Eq. (IV-23), is the perceived error, 𝜠𝜠 𝚯𝚯 ′(𝑖𝑖) = 𝑳𝑳(𝑖𝑖) 𝚯𝚯(𝑖𝑖) + 𝚽𝚽(𝑖𝑖) (IV-23) and 𝑳𝑳(𝑖𝑖), shown in Eq. (IV-24), is a matrix representing the circular chain connections with the neighbors' delays 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑃𝑃 (𝑖𝑖) and 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑆𝑆 (𝑖𝑖). 𝑳𝑳(𝑖𝑖) = 0.5 �𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑃𝑃 (𝑖𝑖) 𝑺𝑺 + 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑆𝑆 (𝑖𝑖) 𝑺𝑺 * � -𝑰𝑰 (IV-24) This expression can be simplified by removing from the model the neighbors measurement delays 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑃𝑃 (𝑖𝑖) and 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑𝑆𝑆 (𝑖𝑖). Then, the error vector 𝜠𝜠 𝚯𝚯 (𝑖𝑖) can appear in the final expression, as shown in Eq. (IV-25), because 𝑳𝑳(𝑖𝑖) becomes 𝑳𝑳. It should be noted that 𝑳𝑳(𝑗𝑗0) = 𝑳𝑳. 𝑽𝑽 ε 𝜃𝜃 (𝑖𝑖) = 2 𝐼𝐼 P 𝑖𝑖 0 𝐶𝐶 𝑉𝑉 𝑍𝑍𝑂𝑂𝑚𝑚 (𝑖𝑖) 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑 (𝑖𝑖) 𝜠𝜠 𝚯𝚯 (𝑖𝑖) (IV-25)

  ) = 𝑽𝑽 ε 𝜃𝜃 (𝑖𝑖) 𝑼𝑼(𝑖𝑖) = -H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) 𝑳𝑳(𝑖𝑖) (IV-28) If all modules, including the controllers, are identical, the MIMO open-loop transfer function noted 𝒐𝒐𝑳𝑳(𝑖𝑖) and shown in Eq. (IV-29). 𝒐𝒐𝑳𝑳(𝑖𝑖) = 𝚯𝚯(𝑖𝑖) 𝚯𝚯′(𝑖𝑖) = -H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) 𝐶𝐶(𝑖𝑖) 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) 𝑳𝑳(𝑖𝑖) (IV-29) Change of basis and modal transfer functions All matrix transfer functions are diagonal and circulant, except 𝑳𝑳(𝑖𝑖), that is only circulant. To obtain the modal open-loop transfer function, 𝑳𝑳(𝑖𝑖) has to be diagonalized using the DFT matrix. The same DFT matrix as the one shown in Section II.2.1 will be used. A change of basis expressed by the set of equations developed in Eq. (IV-30) is applied to the system. 𝚯𝚯 * (𝑖𝑖) = 𝑾𝑾 * 𝚯𝚯(𝑖𝑖) 𝚯𝚯′ * (𝑖𝑖) = 𝑾𝑾 * 𝚯𝚯′(𝑖𝑖) (IV-30) Then, the diagonal formulation of Eq. (IV-29) can be written. Its expression is detailed in Eq. (IV-31). 𝒐𝒐𝑳𝑳 * (𝑖𝑖) = 𝚯𝚯 * (𝑖𝑖) 𝚯𝚯′ * (𝑖𝑖) = -H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) 𝐶𝐶(𝑖𝑖) 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) 𝑳𝑳 * (𝑖𝑖) (IV-31) where 𝑳𝑳 * (𝑖𝑖) = 𝑾𝑾 𝑳𝑳(𝑖𝑖) 𝑾𝑾 *

  𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) = 𝑉𝑉 * 𝑖𝑖 𝑅𝑅𝑖𝑖 (𝑖𝑖) + 𝑗𝑗 𝑉𝑉 * 𝑖𝑖 𝐼𝐼𝑚𝑚 (𝑖𝑖), 𝜆𝜆 = 0 … 𝑁𝑁 -1 (IV-33) where 𝑉𝑉 * 𝑖𝑖 𝑅𝑅𝑖𝑖 (𝑖𝑖) = cos(2𝜋𝜋 𝜆𝜆 𝑁𝑁 ⁄ ) cos(𝑗𝑗 𝑖𝑖 𝑖𝑖 0 ) -1 𝑉𝑉 * 𝑖𝑖 𝐼𝐼𝑚𝑚 (𝑖𝑖) = -𝑗𝑗 sin(2𝜋𝜋 𝜆𝜆 𝑁𝑁 ⁄ ) sin(𝑗𝑗 𝑖𝑖 𝑖𝑖 0 ) The values of |𝑉𝑉 * 𝑖𝑖 (𝑖𝑖)|, for 𝜆𝜆 = 0 … 𝑀𝑀 -1, are plotted in Figure IV-12 (a), showing the values for positive and negative frequencies.

1 𝜆𝜆 = 2 𝜆𝜆 = 3 𝜆𝜆 = 4 Figure

 1234 Figure IV-12 -𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) Transfer function: a) Positive and negative frequencies, b) Real and imaginary components.

  approximation of 𝑳𝑳(𝑖𝑖) to simplify the model and help to design the corrector. If the model is simplified replacing 𝑳𝑳(𝑖𝑖) by 𝑳𝑳, 𝑳𝑳 * (𝑖𝑖) becomes 𝜦𝜦 developed in Eq. (II-17) and each mode gets a different gain equal to 𝜆𝜆 𝑖𝑖 , i.e. the eigenvalues of 𝑳𝑳 detailed in Eq. (II-16).

  comparable to zero. This last point can become a real issue because it can generate frequency deviations an break the loop.In order to design the controller static gain to attenuate 𝑫𝑫(𝑖𝑖), the relationship between the disturbance 𝑫𝑫(𝑖𝑖) and the local error 𝜠𝜠 𝚯𝚯 (𝑖𝑖) has to be revealed. To do so, the signals 𝜠𝜠 𝚯𝚯 (𝑖𝑖) and 𝑫𝑫(𝑖𝑖) are diagonalized, as shown in Eq. (IV-34). 𝜠𝜠 𝚯𝚯 * (𝑖𝑖) = 𝑾𝑾 -𝟏𝟏 𝜠𝜠 𝚯𝚯 (𝑖𝑖) 𝑫𝑫 * (𝑖𝑖) = 𝑾𝑾 -𝟏𝟏 𝑫𝑫(𝑖𝑖) (IV-34) The diagonal transfer functions from 𝑫𝑫 * (𝑖𝑖) to 𝜠𝜠 𝚯𝚯 * (𝑖𝑖) is shown in Eq. (IV-35), where differential mode transfer functions are also shown, within the modal bandwidth, i.e. |𝑜𝑜𝑉𝑉 * 𝑖𝑖 (𝑖𝑖)| > 1.

  is assumed that |𝑁𝑁 * 0 (𝑗𝑗0)| has a limited value. 𝑢𝑢 * 0 𝑆𝑆𝑆𝑆 is also limited if |𝐶𝐶(𝑗𝑗0)| is limited as well, otherwise the signal 𝑢𝑢 would saturate in some of the local controllers and produce infinite value due to the controller integrator. A saturated local controller modify the transient response because it acts like if the loop was opened. As a consequence, 𝐶𝐶(𝑖𝑖) cannot implement an integrator, then |𝐶𝐶(𝑗𝑗0)| < ∞.

  Figure IV-13 shows the bode diagrams of the modal OLTF shown in Eq. ((IV-32)) for 𝑁𝑁 = 8 (𝑀𝑀 = 5), 𝐶𝐶(𝑖𝑖) = 0.5 and 𝑳𝑳(𝑖𝑖) = 𝑳𝑳, then 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) = 𝜆𝜆 𝑖𝑖 . As 𝜆𝜆 𝑖𝑖 = 𝜆𝜆 𝑆𝑆-𝑖𝑖 , only the values with 𝜆𝜆 = 0 … 𝑀𝑀 -1 are shown. Moreover, the common mode (mode 0) cannot be controlled because 𝜆𝜆 0 = 0, so only the differential modes are studied, then 𝜆𝜆 = 1 … 𝑀𝑀 -1.

Figure IV- 13 -

 13 Figure IV-13 -Modal open-loop transfer function plot for 𝑁𝑁 = 8 (𝑀𝑀 = 5) and 𝑳𝑳(𝑖𝑖) = 𝑳𝑳. A disturbance rejection simulation is made with each of the modal transfer functions as shown in Figure IV-14. This simulation result is similar to the expected responses of the components of |𝜺𝜺 𝜽𝜽 * |.

Figure IV- 14 -

 14 Figure IV-14 -Modal closed-loop disturbance rejection simulation for 𝑁𝑁 = 8 (𝑀𝑀 = 5) and 𝑳𝑳(𝑖𝑖) = 𝑳𝑳. The rise time 𝑖𝑖 𝑡𝑡𝑖𝑖𝑠𝑠𝑖𝑖 for these underdamped system is defined as the time from 0% to 100%. The rise time, overshoot and overshoot time 𝑖𝑖 𝑂𝑂𝑉𝑉 are obtained from the model simulation shown in Figure IV-14. Table IV-2 summarizes the modal performances obtained in this study: 𝑁𝑁 = 8 (𝑀𝑀 = 5) and 𝑳𝑳(𝑖𝑖) = 𝑳𝑳.

Figure IV- 15

 15 Figure IV-15 shows the simulation results of a system with eight LCs (𝑁𝑁 = 8) and the controller previously designed. Each simulation result consists of the applied modal disturbance 𝒅𝒅 * = |𝑾𝑾 -1 𝒅𝒅| , the waveforms of the PDs 𝜽𝜽 , the local errors 𝜺𝜺 𝜽𝜽 and the modal error decompositions |𝜺𝜺 𝜽𝜽 * | to observe the total mode disturbances. For simulation purposes, the target operator introduced in the previous chapter for the digital case is required.

Figure IV- 15 -

 15 Figure IV-15 -Dynamic modal responses with N = 8 and controller 𝐶𝐶(𝑖𝑖) of Figure IV-13. The PD values behave as expected. It is possible to distinctly observe the modal excitations being applied successively and their respective responses. All modes are stable and 𝑘𝑘 𝑖𝑖_5% observed on |𝜺𝜺 𝜽𝜽 * | corresponds to the simulated values from the modal transfer functions shown in Table IV-2.

5 .

 5 The resulting wrong error is approximately equal to -0.25. The other LCs compensate equally this interleaving issue, each local error been approximately equal to 0.25 𝑁𝑁 ⁄ . The PD steady-state values can be derived from Eq. (II-8) and solved with the Final Value Theorem on Eq. (II-47), and the result expressed in Eq. (IV-41). 𝜽𝜽 = 𝜆𝜆𝑜𝑜𝜃𝜃�𝑳𝑳 + (𝜺𝜺 𝜃𝜃 -𝝋𝝋)� = 𝜆𝜆𝑜𝑜𝜃𝜃�𝑳𝑳 + (0.25 𝑁𝑁 ⁄ 𝑰𝑰 -𝝋𝝋)� (IV-41) where 𝟏𝟏 = [1] 1×𝑆𝑆 , 𝑳𝑳 + is the pseudo-inverse of 𝑳𝑳, and 𝜆𝜆𝑜𝑜𝜃𝜃(•) is the module operator to correct the common-mode, i.e. keep the PDs between 0 and 1. The level freeze fault can be easily detected by analyzing the UP/DN signals or verifying directly the clk signals received from the neighbors, i.e. verify if a rising and a falling edge are detected in each period.

  This section is dedicated to the development of the new interleaving proof-of-concept for model validation. The data obtained will be analyzed and the comparisons with the proposed model predictions will be verified. The proof-of-concept is an electronic board where the interleaving LCs are implemented with basic functions, such as NAND gates, flip-flops, switches, comparators and operational amplifiers, in addition to resistors, capacitors and diodes. All these functions are of the type of commercial discrete Surface Mount Devices (SMD). The board shown in Figure IV-16 is composed by 6 identical carrier generators, each of them with a LCs and a bypass circuit. Additionally, shared functions are placed aside, composed of a start-up synchronization circuit (reset), a slope generator for phase-delay sampling and a fault introduction circuit composed by inter-connection analog switches.

Figure IV- 16 -

 16 Figure IV-16 -Proof-of -concept board with 6 LCs and shared functions.Each LC has two inputs, noted "CssP" and "CssN", to receive the previous and next LC signals. Each LC has also two outputs, noted "Css2P" and "Css2N", to send signals to the previous and next LCs. The nature of the signal sent to the neighbors depends if the LC is bypassed or not, i.e. deactivated or activated.

Figure IV- 17 .

 17 It consists of a Schmitt trigger made up of a comparator with hysteresis (1) and an operational amplifier in an integrator configuration[START_REF]Difference Between Centralized vs Decentralized vs Distributed network[END_REF]. The comparator output called "Vtrig" is equivalent to the clock signal "clk".

Figure IV- 17 -

 17 Figure IV-17 -Triangular carrier generator and its additional circuits required for "Vtri" preprepositioning.

  Figure IV-19 manages the start-up synchronization, generate the sample-and-hold control signals, and the "Up" and "Down" (UP/DN) signals that represents the phase-delay. The neighbors clock signals are applied on "VtrigP" and "VtrigN", while the local clock is applied on "Vtrtr". To avoid measurement errors, the D flip-flop at the left enables the measurement and corrections at start-up with the beginning of the carrier period, while the other on the right synchronizes the by-pass with the carrier period.

Figure IV- 19 -

 19 Figure IV-19 -New interleaving digital core. The analog core shown in Figure IV-20 is composed, from left to right, of an integrator with reset, a sampling circuit, a voltage follower, a proportional corrector with phase-lag, and an amplifier to manipulate the triangular carrier generator frequency. The last amplifier injects a current proportional to the correction "eV" at the inverting input of the amplifier (2) shown in Figure IV-17.

Figure IV- 20 -

 20 Figure IV-20 -New interleaving analog core.

LeCroy WaveRunner 8108HD 12 -

 12 bit oscilloscope with 8 analog and 16 digital channels, a Keysight Tektronix 5 SERIES MSO58 8 analog channels mixed signal oscilloscope. The boards are powered with an external 5V DC power supply. A Keysight Tektronix MDO3014 4 channels oscilloscope was used for debug purposes. The experimental validation bench is shown in Figure IV-21.

Figure IV- 21 -

 21 Figure IV-21 -Experimental validation bench, LeCroy oscilloscope in the middle and Tektronix oscilloscope on the right. The 8 analog channels of the LeCroy oscilloscope are used to observe the sampled PDs (top) and the digital channels are used to monitor the oscillators clock signals clk (bottom). The

Figure IV- 23

 23 Figure IV-23 -60 combinations of "V0", "V0ax" and "Gx" to pre-position "Vtri" phase-delays.

Figure IV- 24 ,

 24 Figure IV-25, Figure IV-26, and Figure IV-27. The LeCroy scope plots show in the top are the representation of the PDs 𝜽𝜽 from 𝜃𝜃 1 to 𝜃𝜃 8 upwards and the digital signals are the 𝑐𝑐𝑙𝑙𝑘𝑘𝑖𝑖 from 1 to 8; the Tektronix scope plots show on the top the local errors 𝜺𝜺 𝜃𝜃 and on the bottom the absolute value of the modal local errors |𝜺𝜺 𝜽𝜽 * | components 1 to 4. |𝜀𝜀 𝜃𝜃 * | 4 was scaled with a factor √2/2.

Figure IV- 24 -

 24 Figure IV-24 -Mode 1 diagonal response: a) PDs and clks; b) errors and modal errors.

Figure IV- 25 -

 25 Figure IV-25 -Mode 2 diagonal response: a) PDs and clks; b) errors and modal errors.

Figure IV- 26 -

 26 Figure IV-26 -Mode 3 diagonal response: a) PDs and clks; b) errors and modal errors.

Figure IV- 27 -

 27 Figure IV-27 -Mode 4 diagonal response: a) PDs and clks; b) errors and modal errors. The modal responses are stable and correspond to the expected values obtained with the model. The sampled modal error measurements are summarized on Table IV-5, where:

  Figure IV-28 shows the start-up response measurements with one PD in phase opposition (1+7).Figure IV-29 shows the start-up response measurements with by groups (4+4).

Figure IV- 28 -

 28 Figure IV-28 -Start-up response with one PD in phase opposition (1+7): a) PDs and clks; b) errors and modal errors.

Figure

  Figure IV-29 -Start-up response by groups (4+4): a) PDs and clks; b) errors and modal errors.

8 .

 8 Figure IV-30 (a) shows a well interleaved system where 𝜃𝜃 5 is pre-positioned between 𝜃𝜃 4 and 𝜃𝜃 6 and then inserted to complete 𝑁𝑁 = The transient is smooth, but takes time to achieve steady-state because Mode 1 is disturbed.

Figure IV- 30 Figure IV- 30 -

 3030 Figure IV-30 (b) shows a measurement where LC5 is bypassed at the beginning 𝑁𝑁 = 7 and the PD differences are 2/𝑁𝑁. It should be noted that 𝜃𝜃 5 is in between its neighbors, even if coincident with 𝜃𝜃 1 . When LC5 is inserted, the PDs arrange themselves by groups, as expected, such as shown in Figure II-18. The signals still interleaved, but not in a Proper InterleavedArrangement. As a result, the spectral content of the modulated signals is not optimal, considering optimal the highest as possible.

Figure IV- 31

 31 Figure IV-31 shows a use case where the connection from LC1 to LC8 is shorted to ground during operation, i.e. LC8 input "CssN" is connected to 0V using the fault introduction

Figure IV- 31 -IV. 9 . 6 .

 3196 Figure IV-31 -LC8 CssN short to ground fault transient measurement: a) PDs and clks; b) errors and modal errors.

Figure IV- 32 -

 32 Figure IV-32 -Noise immunity: frequency jitter measurement.

Figure I- 23 .

 23 Figure I-23. The current balance correctors with integrator can annul the error, but one current balance controller is disabled in order to avoid correction divergence. As no shared line is used, the focal point is always on the regulator characteristics where the balance regulator is disabled, and consequently the voltage precision improvement is lost.

1 - 2 - 3 )

 123 The loop gain and consequently transient response depends on 𝐼𝐼 𝑜𝑜𝑜𝑜𝑡𝑡 . 2-The closed loop line load characteristics 𝑅𝑅 𝑂𝑂𝑂𝑂 may change if all correctors are activated with non-limited gain;To remove the non-linearity, the voltage references should be adjusted to equalize the leg currents instead of changing the load line to balance the current. To have the voltage precision improvement when using current balance, all balance correctors must be active and have the same limited static gain.Voltage references adjustment: static behaviorThe output voltage and leg current tolerance analysis shall be written to reveal the advantages of using the voltage references adjustment with the circular chain. The static AVP relation is applied in each of the modular converter's legs, following the expression shown in Eq. (F-1).𝑉𝑉 𝑜𝑜𝑜𝑜𝑡𝑡 = 𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚𝑖𝑖 -𝑅𝑅 𝑂𝑂𝑂𝑂𝑖𝑖 × 𝐼𝐼 𝑖𝑖 + 𝑅𝑅 𝑆𝑆𝑖𝑖 × 𝜀𝜀 𝑖𝑖 , 𝜆𝜆 = 0 … 𝑁𝑁 -1 (F-1)where 𝜀𝜀 𝑖𝑖 is the current error in the ith leg given by 𝜀𝜀 𝑖𝑖 = 𝐼𝐼 𝑡𝑡-1 +𝐼𝐼 𝑡𝑡+1 𝐼𝐼 𝑖𝑖 and the current balance loop has static gain equals to 𝑅𝑅 𝑆𝑆𝑖𝑖 . The combined output voltage can be seen in Eq. (F-2). line 𝑅𝑅 𝑂𝑂𝑂𝑂 of the centralized case can be observed when each leg load line 𝑅𝑅 𝑂𝑂𝑂𝑂𝑖𝑖 is equal to 𝑅𝑅 𝑂𝑂𝑂𝑂𝑖𝑖 = 𝑁𝑁 × 𝑅𝑅 𝑂𝑂𝑂𝑂 . Considering the simplification where 𝑅𝑅 𝑂𝑂𝑂𝑂𝑖𝑖 = 𝑁𝑁 × 𝑅𝑅 𝑂𝑂𝑂𝑂 and 𝑅𝑅 𝑆𝑆𝑖𝑖 = 𝑅𝑅 𝑆𝑆 , the equivalent output voltage is shown in Eq. (F-3). It should be noted that the output voltage 𝑉𝑉 𝑜𝑜𝑜𝑜𝑡𝑡 tolerance benefits of the average of all voltage references 𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚𝑖𝑖 . Additionally, the sum of the current leg errors is null, ∑ 𝜀𝜀 𝑖𝑖 𝑆𝑆 𝑖𝑖=1 = 0, so the current balance loop do not impacts the output voltage if 𝑅𝑅 𝑆𝑆 is limited. As a result, this current balance structure with limited static gains allows to balance current keeping voltage reference tolerance improvement. By replacing 𝑉𝑉 𝑜𝑜𝑜𝑜𝑡𝑡 from Eq. (F-3) in Eq. (F-1) and considering ∑ 𝜀𝜀 𝑖𝑖 𝑆𝑆 𝑖𝑖=1 = 0, then the local current loop error can be expressed as shown in Eq. (F-4). × 𝐼𝐼 𝑜𝑜𝑜𝑜𝑡𝑡 -𝑅𝑅 𝑂𝑂𝑂𝑂𝑖𝑖 × 𝐼𝐼 𝑖𝑖 𝑅𝑅 𝑆𝑆𝑖𝑖 (F-4) This approach fulfill the two requirements. Eq. (F-3) shows the output voltage benefits of the voltage refence average and without impact of the current balance. Eq. (F-4) shows the current balance can mitigate local voltage reference and local load line deviations.

  Mannes-Hillesheim, M. Cousineau, G. Gateau, "Analyse Modale de l'Auto-Entrelacement de Porteuses par Approche Numérique Itérative," Symposium de Génie Electrique 2018, Nancy, France, juillet 2018.

	Journals: Patents:
	o Mannes Hillesheim, Miguel, Marc Cousineau, Miguel Vivert, Guillaume Aulagnier, and o "DISTRIBUTED INTERLEAVING CONTROL OF MULTIPHASE SMPCS", Application
	Guillaume Gateau. "Eigendecomposition of a Digital Iterative Decentralised Interleaving for Number 19306559.6 , NXP USA, Inc. and INSTITUT NATIONAL POLYTECHNIQUE
	Multicellular Converters." Mathematics and Computers in Simulation, July 2020, DE TOULOUSE, date de dépôt 12/02/2020, inventeurs : Miguel MANNES HILLESHEIM,
	S037847542030241X. https://doi.org/10.1016/j.matcom.2020.07.014. Marc Michel COUSINEAU, Eric Pierre ROLLAND, Philippe GOYHENETCHE and
	Guillaume Jacques Leon AULAGNIER.
								Applications
	(EPE	'19	ECCE	Europe),	P.1-P.8.	Genova,	Italy:	IEEE,	2019.
	https://doi.org/10.23919/EPE.2019.8915561.
								Dung, "High
	Dynamic Current Control Using Decentralized PWM Generation for Parallel Multiphase
	Converter," 2020 IEEE International Conference on Industrial Technology (ICIT), Buenos
	Aires, Argentina, 2020, pp. 480-486, doi: 10.1109/ICIT45562.2020.9067112

o Q. D. Phan, G.

Gateau

, P. C. Nguyen, M. Cousineau, H. P. To, B.A. Nguyen, L. Veit, R. De Milly, and M. Mannes Hillesheim. "A Fast, Decentralized, Self-Aligned Carrier Method for Multicellular Converters." Applied Sciences 11, no. 1, 2021. doi: 10.3390/app11010137 o M. Vivert, M. Cousineau, P. Ladoux, J. Fabre, M. Mannes-Hillesheim, R. Diez, D. Patino, « Decentralised Control for Balancing the Cell-Voltages of a High Conversion Ratio Flying Capacitor Multilevel Converter, » JESTIE 2021 (Accepted for publication the 15 of September 2021) International conferences: o Hillesheim, Miguel Mannes, Marc Cousineau, and Loic Hureau. "Reconfigurable Partial-Decentralized Control of a Multiphase Converter for Fail-Operational Automotive Processor Power Supply." In 2019 21st European Conference on Power Electronics and o Gateau, M. Cousineau, M. Mannes-Hillesheim and P. Q. Dung, "Digital Decentralized Current Control for Parallel Multiphase Converter," 2019 IEEE International Conference on Industrial Technology (ICIT), Melbourne, Australia, 2019, pp. 1761-1766, doi: 10.1109/ICIT.2019.8755049 o G. Gateau, M. Cousineau, M. Mannes-Hillesheim, T. Robert and P. Q. o Q. Phan, G. Gateau, M. Cousineau, L. Veit, R. De Milly and M. Mannes-Hillesheim, "Ultrafast Decentralized Self-Aligned Carrier Principle for Multiphase/Multilevel Converters," 2020 IEEE International Conference on Industrial Technology (ICIT), Buenos Aires, Argentina, 2020, pp. 517-522, doi: 10.1109/ICIT45562.2020.9067108 National conferences: o M. o "DISTRIBUTED CONTROL OF A VOLTAGE REGULATOR", Application Number 19306578.6, NXP USA, Inc. and INSTITUT NATIONAL POLYTECHNIQUE DE TOULOUSE, date de dépôt 12/02/2020, inventeurs : Guillaume Jacques Leon AULAGNIER, Miguel MANNES HILLESHEIM, Eric Pierre ROLLAND, Philippe GOYHENETCHE and Marc Michel COUSINEAU. o "MODULAR INTERLEAVING TECHNIQUES FOR SCALABLE POWER ELECTRONICS CONVERTER", Application Number 20305395.4, NXP USA, Inc. and INSTITUT NATIONAL POLYTECHNIQUE DE TOULOUSE, date de dépôt 12/02/2020, inventeurs : Miguel MANNES HILLESHEIM, Marc Michel COUSINEAU, Eric Pierre ROLLAND, Philippe GOYHENETCHE and Guillaume Jacques Leon AULAGNIER.

Table I -

 I 1 -Voltage regulation and balance techniques combinations.

			Voltage regulation
			Centralized	Distributed
	Current Balance	Shared wire Circular chain	Modular [9], [10] Modular [11]	Modular [12] Modular / No SPOF [13]

I.4.2. Interleaved clock generation

	Interleaved converters presented in the literature and available in the market can be
	classified in two groups.

  as the delay control voltage 𝑣𝑣 𝑅𝑅 is dependent on the number of connected slaves.Reconfiguration is very simple: the slave local resistor can be disconnected and the delay bypassed. Zhang introduced in [19] a similar VCDL system with improved delay computation.

	The
	interleaving technique is based on a clock signal being transmitted in an open daisy chain
	connections. The elements are cascaded and each one sends a clock signal to the next in the
	chain with a delay. The delay between input and output clocks is selected through an input
	"PHMODE" in each element. It is suitable for 2-, 3-, 4-, 6-and 12-phase interleaved operation.
	Some interleaved applications of the PolyPhase TM module LTM4636-1 datasheet is shown in
	Figure I-26. This implementation is not suitable to reconfiguration during operation because
	the delay value is chosen by hardware and only some phase-delay values are possible.
	KOHAMA and all introduced in [18] uses a similar scalable interleaving technique
	based on a Voltage Controlled Delay Loop (VCDL) as shown in Figure I-27. The delay value
	is shared through a shared wire and its value is automatically adjusted based on the number of
	active modules,

  Analog Device LTC3310S and Maxim MAX8686 uses a similar scalable interleaving technique up to four and eight phases, respectively, but the synchronization is made with a digital clock signal instead of the analogue triangular signal. Texas Instruments TPS543C20 requires only one resistor to set the phase-delay, but can only operate with two phases. These approaches are not suitable for reconfiguration because the phase-delay is chosen by hardware.

	The modules family BMR46x from Ericson, LGA80D series from ARTESYN, and
	ISL8272M from Renesas use a shared clock signal for synchronization. The phase-delay
	selection is made by software using a digital communication link. Reconfiguration can be made
	during operation by the master controller. A limited number of phase-delays are possible, e.g.
	BMR462-466 are limited to 16 possible values (22.5° steps), while BMR461 products support
	128 values (2.8° steps).
	GRÉGOIRE uses in [21] a circular-chain of communications and a local controllers to
	compute the local phase-delay, as shown in Figure I-30 (a). Each local controller has a feedback
	loop to position automatically the local phase-delay in between the neighbors' ones.

Table I -

 I

2 -Interleaving techniques mapping.

Table II -

 II

		𝑘𝑘 5%_4	𝑘𝑘 5%_3	𝑘𝑘 5%_2	𝑘𝑘 5%_1
	α = 6/5	+∞	6.4	4.0	6.8
	α = 1	5.3	3.0	4.5	7.2
	α = 3/4	3.4	3.9	5.2	7.9

2 -Number of iterations for 5% response using lead-lag corrector (𝑁𝑁 = 8).

Table II -

 II 𝑛𝑛𝑛𝑛 order problem, depending only on α and 𝑁𝑁. This system has an unknown number of active modules and all local controllers are identical. To simplify the design of the optimal 5% settling time, a parametric plot of the least squares of 𝑘𝑘 5% versus the convergence coefficient 𝛼𝛼 and 𝑁𝑁 is shown in Figure II-13 for 𝑁𝑁 = 8.

	Figure II-13 -Optimized Convergence Coefficient 𝛼𝛼 using least squares of 𝑘𝑘 5% criterion. Sensibility to
	𝑁𝑁.

[START_REF]Difference Between Centralized vs Decentralized vs Distributed network[END_REF]

shows explicitly the number of iterations required for each differential mode with a given α parameter. With different configurations observed, it is not easy to guess which would be the optimal one. So the normalized least squares of 𝑘𝑘 5% is used to provide a general criterion for each α value.

Chosen 𝐶𝐶 𝑂𝑂𝑂𝑂 and 𝑝𝑝 𝑂𝑂𝑂𝑂 values and the normalized least squares of 𝑘𝑘 5%_m , the problem is reduced to a 2

Table II -

 II

		k5%_7	k5%_6	k5%_5	k5%_4	k5%_3	k5%_2	k5%_1
	α = 1	39	9.4	4.1	1	4.1	9.4	39
	α = 3/4	3.7	2.4	0.9	2.2	4.8	12	51
	α = 1/2	1.9	2.6	3.5	5.3	9.1	20	78

3 -Iteration number for 5% response (𝑁𝑁 = 8) with one PD constant.

Table II -

 II 3 presents the same pattern seen in TableII-1, and all the previous observations are still valid, such as the convergence of the overall system depends on the type of modes that are excited.

Table II -

 II 4 -Number of iterations for 5% response (𝑁𝑁 = 9).

		k5%_4	k5%_3	k5%_2	k5%_1
	𝑘𝑘 1 = 0.6, 𝑘𝑘 3 = 0.1	2.6	1.3	2.9	8.7
	𝑘𝑘 1 = 0.4, 𝑘𝑘 3 = 0.3	2.0	3.3	2.0	3.2
	𝑘𝑘 1 = 0.1, 𝑘𝑘 3 = 0.6	1.3	18	0.7	1.2
	𝑘𝑘 1 = 0, 𝑘𝑘 3 = 2/3	0	+∞	0	0

  in Figure All poles start at 1 when gain 𝛼𝛼 is equal to 0 and go over the unit circle when the gain 𝛼𝛼 is equal to 2, being equivalent to 𝛽𝛽 going to infinity.

	α	0.75	1.0
	λ 𝐴𝐴1 0.74 ∠ -7.4° 0.68 ∠ -16°
	λ 𝐴𝐴2 0.42 ∠ -36° 0.45 ∠ -63°
	λ 𝐴𝐴3 0.21 ∠ -81° 0.36 ∠ -120°
	λ 𝐴𝐴4 0.09 ∠ -180° 0.33 ∠ -180°
	λ 𝐴𝐴5 0.21 ∠ 81° 0.36 ∠ 120°
	λ 𝐴𝐴6 0.42 ∠ 36° 0.45 ∠ 63°
	λ 𝐴𝐴7 0.74 ∠ 7.4° 0.68 ∠ 16°

Table III -

 III

		md1: k5%_1	md2: k5%_2	md3: k5%_3	md4: k5%_4
	α = 2	+∞	+∞	+∞	+∞
	α = 1.5	10	9.2	8.9	8.9
	α = 1	7.7	3.7	2.9	2.7
	α = 0.75	10	3.5	1.9	1.2

1 -Number of iterations for 5% convergence criterion (𝑁𝑁 = 8, 𝑀𝑀 = 5, 4 differential modes, 4 eigenvalues).

Table III -

 III [START_REF]Three things to know about functional safety[END_REF] shows explicitly the number of iterations required for each differential mode with a given α parameter. Observing the different configurations, it is not easy to guess which would be the optimal one. All differential mode eigenvalue absolute values, and consequently

  to T 0 . At the 𝑘𝑘 𝑡𝑡ℎ time period, the local clock rising edge instant is noted 𝑘𝑘, related to time instant 𝑘𝑘T 0 . The PD between 𝑐𝑐𝑙𝑙𝑘𝑘 𝑃𝑃 and 𝑐𝑐𝑙𝑙𝑘𝑘 falling edges at the previous half period is noted Δ𝜃𝜃 𝑃𝑃 𝑘𝑘 , and the PD between 𝑐𝑐𝑙𝑙𝑘𝑘 and 𝑐𝑐𝑙𝑙𝑘𝑘 𝑆𝑆 falling edges at the previous full period is noted Δ𝜃𝜃 𝑆𝑆 𝑘𝑘 .The signals 𝑣𝑣 𝑆𝑆 and 𝑣𝑣 𝜀𝜀 𝜃𝜃 related to the periodical average circuit are also shown with their iterations with control signal. A first signal called 𝑖𝑖𝜆𝜆𝑝𝑝 is generated by comparing the triangular carrier with a constant voltage level resulting in a digital signal centered with the triangle peak and showing a 10% duty-cycle. Then, the sample signal 𝑖𝑖𝜆𝜆𝑝𝑝 and reset signal 𝑟𝑟𝑖𝑖𝑑𝑑 are generated using logic gates with the clock signal, with 𝑖𝑖𝜆𝜆𝑝𝑝 = 𝑖𝑖𝑠𝑠𝑒𝑒𝑐𝑐 • 𝑐𝑐𝑙𝑙𝑘𝑘 ���� and 𝑟𝑟𝑖𝑖𝑑𝑑 = 𝑖𝑖𝑠𝑠𝑒𝑒𝑐𝑐 • 𝑐𝑐𝑙𝑙𝑘𝑘. One can observe that 𝑣𝑣 𝑆𝑆 increases with a constant rate when 𝑈𝑈𝛥𝛥 is high and decreases with the same constant rate when 𝐷𝐷𝑁𝑁 is high, 𝑣𝑣 𝜀𝜀 𝜃𝜃 assumes the same value as 𝑣𝑣 𝑆𝑆 when 𝑖𝑖𝜆𝜆𝑝𝑝 is high and 𝑣𝑣 𝑆𝑆 goes back to its initial positions when 𝑟𝑟𝑖𝑖𝑑𝑑 is high.

  There are two main ways to measure a phase-delay: either using instantaneous phasor values or using the time delay between the instants where the signals passes through the same level. It should be noted that the calculated charge in Eq. (IV-9) is equals to the definition using times delays, shown in Eq. (IV-10).The phasor delay approach generate an instantaneous value, where all PDs are sampled together, i.e. synchronized at the same instant. However, the clock signal reveals its PD only in the edge event, the PDs at the falling edge events are expressed in Eq. (IV-11).To obtain the equivalent phasor measurement, 𝜃𝜃 𝑃𝑃 and 𝜃𝜃 𝑆𝑆 values must be expressed at the instant t 𝑂𝑂 𝑘𝑘 . The previous and next sampled PDs can be rewritten as a function of the local sampling time, as shown in Eq. (IV-12).

	𝜃𝜃 𝑃𝑃 (t 𝑃𝑃	𝑘𝑘 ) =	t 𝑃𝑃 𝑖𝑖 0 𝑘𝑘	-𝑘𝑘					𝜃𝜃(t 𝑂𝑂	𝑘𝑘 ) =	t 𝑂𝑂 𝑖𝑖 0 𝑘𝑘	-𝑘𝑘	𝜃𝜃 𝑆𝑆 (t 𝑆𝑆	𝑘𝑘 ) =	𝑘𝑘 𝑖𝑖 0 t 𝑆𝑆	-𝑘𝑘	(IV-11)
			𝜃𝜃 𝑃𝑃 (t 𝑃𝑃	𝑘𝑘 ) = 𝜃𝜃 𝑃𝑃 �t 𝑂𝑂	𝑘𝑘 -Δ𝑑𝑑 𝑃𝑃	𝑘𝑘 �	𝜃𝜃 𝑆𝑆 (t 𝑆𝑆	𝑘𝑘 ) = 𝜃𝜃 𝑆𝑆 �t 𝑂𝑂	𝑘𝑘 + Δ𝑑𝑑 𝑆𝑆	𝑘𝑘 �	(IV-12)
														𝑘𝑘 𝑇𝑇 0 (𝑘𝑘-1) 𝑇𝑇 0	𝜃𝜃𝑑𝑑 = 𝐼𝐼 P 𝑖𝑖 0 �𝐷𝐷 𝑈𝑈𝑃𝑃	𝑘𝑘 -𝐷𝐷 𝐷𝐷𝑆𝑆	𝑘𝑘 �	(IV-9)
	with										𝐷𝐷 𝑈𝑈𝑃𝑃 𝐷𝐷 𝐷𝐷𝑆𝑆	𝑘𝑘 = 𝑘𝑘 =	1 𝑖𝑖 0 1 𝑖𝑖 0	� (𝑘𝑘-1) 𝑇𝑇 0 𝑘𝑘 𝑇𝑇 0 � 𝐷𝐷𝑁𝑁(𝑑𝑑) 𝑈𝑈𝛥𝛥(𝑑𝑑) 𝑘𝑘 𝑇𝑇 0 (𝑘𝑘-1) 𝑇𝑇 0	𝜃𝜃𝑑𝑑 = 𝜃𝜃𝑑𝑑 =	t 𝑂𝑂 t 𝑆𝑆 𝑘𝑘 -t 𝑃𝑃 𝑖𝑖 0 𝑘𝑘 -t 𝑂𝑂 𝑘𝑘 𝑘𝑘 𝑖𝑖 0
	where t 𝑃𝑃	𝑘𝑘 , t 𝑂𝑂	𝑘𝑘 and t 𝑆𝑆	𝑘𝑘 are the instant where each interleaved 𝑐𝑐𝑙𝑙𝑘𝑘 falling edge event
	happens, 𝐷𝐷 𝑈𝑈𝑃𝑃	𝑘𝑘 and 𝐷𝐷 𝐷𝐷𝑆𝑆	𝑘𝑘 are UP and DW signals duty cycles at period 𝑘𝑘.
								Δ𝜃𝜃 𝑃𝑃	𝑘𝑘 ≜		Δ𝑑𝑑 𝑃𝑃 𝑖𝑖 0	𝑘𝑘	Δ𝜃𝜃 𝑆𝑆	𝑘𝑘 ≜	Δ𝑑𝑑 𝑆𝑆 𝑖𝑖 0	𝑘𝑘	(IV-10)
	where				Δ𝑑𝑑 𝑃𝑃	𝑘𝑘 = t 𝑂𝑂	𝑘𝑘 -t 𝑃𝑃	𝑘𝑘	Δ𝑑𝑑 𝑆𝑆	𝑘𝑘 = t 𝑆𝑆	𝑘𝑘 -t 𝑂𝑂	𝑘𝑘
	It should be noted that equalizing the Δ𝑑𝑑 𝑃𝑃	𝑘𝑘 and Δ𝑑𝑑 𝑆𝑆	𝑘𝑘 , i.e. 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑) equals to zero, leads to
	a properly interleaved system. Nevertheless, the phasor delay approach is needed to determine
	the transient behavior.

Error detector Laplace transfer function

  Now, error detector Laplace transfer function noted 𝑉𝑉 ε 𝜃𝜃 (𝑖𝑖) has to be obtained from 𝑣𝑣 ε 𝜃𝜃 (𝑑𝑑). However, it cannot be done with the expression of Eq. (IV-13) because 𝜃𝜃 𝑃𝑃 and 𝜃𝜃 𝑆𝑆 𝜃𝜃 𝑆𝑆 �𝑘𝑘 𝑖𝑖 0 + Δ𝑑𝑑 𝑆𝑆 𝑘𝑘 � ≅ 𝜃𝜃 𝑆𝑆 (𝑘𝑘 𝑖𝑖 0 + 𝑖𝑖 0 𝑁𝑁 ⁄ ) = 𝛿𝛿(𝑑𝑑 + 𝑖𝑖 0 𝑁𝑁 ⁄ ) * 𝜃𝜃 𝑆𝑆 (𝑘𝑘 𝑖𝑖 0 )

				𝑘𝑘=-∞ ∞	5 -1 0.5 �	𝑇𝑇	�	𝜃𝜃 𝑃𝑃 �𝑘𝑘 𝑖𝑖 0 -Δ𝑑𝑑 𝑃𝑃 𝜃𝜃(𝑘𝑘 𝑖𝑖 0 ) 𝜃𝜃 𝑆𝑆 �𝑘𝑘 𝑖𝑖 0 + Δ𝑑𝑑 𝑆𝑆 𝑘𝑘 � 𝑘𝑘 �	� • 𝛿𝛿 �	𝑖𝑖 0 𝑑𝑑 -𝑘𝑘 𝑖𝑖 0	�	(IV-13)
	Eq. (IV-13) highlights that 𝜃𝜃 𝑃𝑃 and 𝜃𝜃 𝑆𝑆 are depend on themselves, Δ𝑑𝑑 𝑃𝑃	𝑘𝑘 and Δ𝑑𝑑 𝑆𝑆	𝑘𝑘 ,
	respectively, because the PD vary between periods and consequently Δ𝑑𝑑 𝑃𝑃	𝑘𝑘 and Δ𝑑𝑑 𝑆𝑆	𝑘𝑘 change. In
	chapter III the chain delay was constant (one sampling period to the previous) and the PD
	constant until next period.
	IV.3.2. expressions have delays (Δ𝑑𝑑 𝑃𝑃	𝑘𝑘 and Δ𝑑𝑑 𝑆𝑆	𝑘𝑘 ) dependent on themselves. To avoid this issue, Δ𝑑𝑑 𝑃𝑃	𝑘𝑘
	and Δ𝑑𝑑 𝑆𝑆	𝑘𝑘 can be approximated by their steady-state expected values, which is 𝑖𝑖 0 𝑁𝑁 ⁄ for a well
	interleaved system, under the assumption of small disturbances around the steady-state
	positions. This hypothesis is formulated on Eq. (IV-14).
		𝜃𝜃 𝑃𝑃 �𝑘𝑘 𝑖𝑖 0 -Δ𝑑𝑑 𝑃𝑃	𝑘𝑘 � ≅ 𝜃𝜃 𝑃𝑃 (𝑘𝑘 𝑖𝑖 0 -𝑖𝑖 0 𝑁𝑁 ⁄ ) = 𝛿𝛿(𝑑𝑑 -𝑖𝑖 0 𝑁𝑁 ⁄ ) * 𝜃𝜃 𝑃𝑃 (𝑘𝑘 𝑖𝑖 0 )	(IV-14)

  ). In the single loop case, the PDs inputs Θ 𝑃𝑃 (𝑖𝑖) and Θ 𝑆𝑆 (𝑖𝑖) are considered null and do not appears in 𝛥𝛥(𝑖𝑖).It should be noted that 𝛥𝛥(𝑖𝑖) is independent of the period 𝑖𝑖 0 because term 𝑖𝑖 0 in H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) simplify with the term 𝑖𝑖 0 -1 in 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖). The controller transfer function 𝐶𝐶(𝑖𝑖) is not present in 𝛥𝛥(𝑖𝑖) and is considered in series with it in the forward path. An applicative case with the following parameters is defined:

	𝑓𝑓 0 = 88 𝑘𝑘𝑉𝑉𝐶𝐶 𝑖𝑖 0 = 1 𝑓𝑓 0 ⁄ = 11.36 𝑢𝑢𝑖𝑖		𝐼𝐼 𝑃𝑃 = 2 x 2.5 𝑉𝑉 16 𝑘𝑘Ω ⁄ 𝐶𝐶 = 1 𝑒𝑒𝑛𝑛	𝑘𝑘 𝑛𝑛 =	1 2.5 𝑉𝑉	10 𝑘𝑘Ω 50 𝑘𝑘Ω
			𝛥𝛥(𝑖𝑖) =	𝑉𝑉 ε 𝜃𝜃𝜃𝜃 (𝑖𝑖) 𝑈𝑈(𝑖𝑖)	= H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖)	(IV-17)
	where:	H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) =	2 𝐼𝐼 𝑃𝑃 𝑖𝑖 0 𝐶𝐶	𝑉𝑉 𝑍𝑍𝑂𝑂𝑚𝑚 (𝑖𝑖) 𝑉𝑉 𝑛𝑛𝑖𝑖𝑙𝑙𝑑𝑑𝑑𝑑 (𝑖𝑖)	𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) =	𝑘𝑘 𝑛𝑛 𝑖𝑖 𝑖𝑖 0

   because 𝒐𝒐𝑳𝑳 * (𝑖𝑖) is diagonal. The 𝑁𝑁 diagonal elements 𝑉𝑉 * 𝑖𝑖𝑖𝑖 (𝑖𝑖) of 𝑳𝑳 * (𝑖𝑖) are named 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖), for 𝜆𝜆 = 0 … 𝑁𝑁 -1, and the same for 𝒐𝒐𝑳𝑳 * (𝑖𝑖) with diagonal elements renamed 𝑜𝑜𝑉𝑉 * 𝑖𝑖 (𝑖𝑖). Comparing the eigenvalues of 𝑳𝑳 with the eigenvalues of 𝑳𝑳(𝑖𝑖) , an additional term -𝑗𝑗 𝑖𝑖 𝑖𝑖 0 appears in the cosine. It should be noted that 𝑉𝑉 * 𝑆𝑆-𝑖𝑖 (𝑖𝑖) = 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) * in all double modes, for 𝜆𝜆 = 1 … 𝑀𝑀 -1, 𝑀𝑀 is defined in Eq. (II-15), but 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) * ≠ 𝑉𝑉 * 𝑖𝑖 (-𝑖𝑖), i.e. the conjugated of 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) is different of 𝑉𝑉 * 𝑖𝑖 (-𝑖𝑖), revealing that this is not a classical control system. 𝑉𝑉 * 𝑖𝑖 (𝑖𝑖) values are real, but it has a non-null complex component.

		𝑜𝑜𝑉𝑉 *	𝑖𝑖 (𝑖𝑖) =	Θ * Θ ′ * 𝑖𝑖 (𝑖𝑖) 𝑖𝑖 (𝑖𝑖)	= -H 𝑖𝑖𝑡𝑡𝑡𝑡𝑜𝑜𝑡𝑡 (𝑖𝑖) 𝐶𝐶(𝑖𝑖) 𝑉𝑉 𝑉𝑉𝑆𝑆𝑂𝑂 (𝑖𝑖) 𝑉𝑉 *	𝑖𝑖 (𝑖𝑖)	(IV-32)
	where:	𝑉𝑉 *	𝑖𝑖 (𝑖𝑖) = cos(2𝜋𝜋 𝜆𝜆 𝑁𝑁 ⁄ -𝑗𝑗 𝑖𝑖 𝑖𝑖 0 ) -1, 𝑗𝑗 is the complex variable √-1 𝜆𝜆 = 0 … 𝑁𝑁 -1

Table IV -

 IV 2 -Modal performances obtained with the model in the case study.

				Bode Diagram
		40
	Magnitude (dB)	-20 0 20							mode 1: Pm = 78.2 deg (at 1.17e+03 Hz) mode 2: Pm = 71.7 deg (at 3.95e+03 Hz) mode 3: Pm = 61.4 deg (at 6.70e+03 Hz)
		-90							mode 4: Pm = 56.9 deg (at 7.82e+03 Hz)
	Phase (deg)	-180 -150 -120
		10 2		10 3		10 4
			Frequency (Hz)
	100%
		90%
		80%
		70%									Mode 1
	disturbance	30% 40% 50% 60%									Mode 2 Mode 3 Mode 4
		20%
		10%
		0%
		0	0.1	0.2	0.3	0.4	0.5	0.6	0.7	0.8	0.9	1
							time [ms]
	Mode i	Cut-off freq 𝑓𝑓 𝑐𝑐 𝑖𝑖	Phase Margin	𝑖𝑖 𝑡𝑡𝑖𝑖𝑠𝑠𝑖𝑖		𝑘𝑘 𝑖𝑖_5%	Overshoot	𝑖𝑖 𝑂𝑂𝑉𝑉
		1	1.17 kHz		78.2°	323 us		28.4	8.87 %	652 us
		2	3.95 kHz		71.7°	105 us		9.24	3.38 %	232 us
		3	6.70 kHz		61.4°	44.3 us		3.90	5.41 %	59.1 us
		4	7.82 kHz		56.9°	36.1 us		3.18	10.5 %	49.2 us

Table IV -

 IV

	Mode 1	0	18	14	12	12	12	10	6 0.071 0.000 0.012 0.000
	Mode 2	0	18	18	18	12	6	6	6 0.000 0.177 0.000 0.000
	Mode 3	0	22	16	16	12	8	8	2 0.005 0.000 0.172 0.000
	Mode 4	0	18	18	12	12	6	6	0 0.000 0.000 0.000 0.354
	s0	Local controller pre-positioning LC1 LC2 LC3 LC4 LC5 LC6 LC7 LC8 |𝜀𝜀 𝜃𝜃 s1 (1)	Initial modal error s2 (2)

3 -Modal initial position and modal error.

* | 1 |𝜀𝜀 𝜃𝜃 * | 2 |𝜀𝜀 𝜃𝜃 * | 3 |𝜀𝜀 𝜃𝜃 * | 4

Table IV -

 IV The responses of a system with 8 local controllers are shown in the following

	Mode 1	59	44	33	29	29	29	24	14 0.074	0	0.005	0
	Mode 2	53	38	38	38	23	8	8	8 0.006 0.177 0.006	0
	Mode 3	59	48	48	33	28	23	8	8 0.002	0	0.172	0
	Mode 4	48	48	33	33	18	18	3	3 0.012	0	0.012 0.354

4 -Experimental modal initial position and modal error.

Local controller pre-positioning Initial modal error

LC1 LC2 LC3 LC4 LC5 LC6 LC7 LC8 |𝜀𝜀 𝜃𝜃 * | 1 |𝜀𝜀 𝜃𝜃 * | 2 |𝜀𝜀 𝜃𝜃 * | 3 |𝜀𝜀 𝜃𝜃 * | 4

  Table IV-5, where: 𝑖𝑖 𝑡𝑡𝑖𝑖𝑠𝑠𝑖𝑖 : rise time from initial value to the first minimum; 𝑉𝑉 𝑇𝑇 𝑡𝑡𝑡𝑡𝑟𝑟𝑟𝑟 : voltage at the first minimum; 𝑂𝑂𝑉𝑉 % : percentual overvoltage calculated as in Eq. (IV-36); 𝑖𝑖 𝑂𝑂𝑉𝑉 : over voltage time.

	𝑉𝑉 0 : 𝑉𝑉 𝑂𝑂𝑉𝑉 % = initial voltage;	𝑉𝑉 OV -𝑉𝑉 𝑇𝑇 𝑡𝑡𝑡𝑡𝑟𝑟𝑟𝑟 𝑉𝑉 0 -𝑉𝑉 𝑇𝑇 𝑡𝑡𝑡𝑡𝑟𝑟𝑟𝑟	(IV-42)

𝑂𝑂𝑉𝑉 : overvoltage after first minimum;

Table IV -

 IV 5 -Modal performances measured in the case study. The experimental modal errors were computed from the sampled local error, while the model modal error are based on the continuous time value. Despite this, the measured values are very close to the ones shown in TableIV-2, even the corrector zero impact on Mode 1 can be observed. This validate the proposed model ability to anticipate the system performance.

	Mode i	𝑖𝑖 𝑡𝑡𝑖𝑖𝑠𝑠𝑖𝑖	𝑉𝑉 𝑇𝑇 𝑡𝑡𝑡𝑡𝑟𝑟𝑟𝑟	𝑉𝑉 0	𝑉𝑉 𝑂𝑂𝑉𝑉	𝑂𝑂𝑉𝑉 %	𝑖𝑖 𝑂𝑂𝑉𝑉
	1	294.8 us	0.0866 V	1.08 V	0.156 V	6.94 %	576.3 us
	2	101.9 us	0.0185 V	3.32 V	0.183 V	5.00 %	212.2 us
	3	49.3 us	0.115 V	2.32 V	0.219 V	4.70 %	78.3 us
	4	44.0 us	0.0385 V	4.56 V	0.407 V	8.13 %	57.3 us

Remerciements Résumé

Availability

Fail-operational, no Single Point Of Failure (SPOF)

Disturbance estimation and error sensibility

Willing to limit the closed-loop steady-state error 𝜺𝜺 𝜃𝜃 𝐬𝐬𝐬𝐬 , the relation between the circuit parameters and the disturbance 𝒅𝒅 has to be revealed. This allows the system definer to specify the system building blocks tolerances to reach the expected performance, in this case 𝜺𝜺 𝜃𝜃 𝐬𝐬𝐬𝐬 .

Numerous parameters can cause disturbances in the PDs, but just some of them are discussed here. It is assumed each TCG is impacted by a disturbance 𝜃𝜃 𝑖𝑖 , 𝜆𝜆 = 0 … 𝑁𝑁 -1, independent of the others TCGs that compose the disturbance vector 𝒅𝒅. In an arbitrary TCG, the disturbance 𝜃𝜃 is related to 𝑉𝑉 𝑚𝑚 and 𝑉𝑉 𝑂𝑂 values. All the others parameters, such as slew rates and gains, are considered equal in all TCGs on purpose of this this study.

To find the expression of the equivalent disturbance 𝜃𝜃 , the voltages 𝑉𝑉 𝑚𝑚 and 𝑉𝑉 𝑂𝑂 are rewritten in two components, the differential mode Δ𝑉𝑉 0 (Δ𝑉𝑉 0 = 𝑉𝑉 H -𝑉𝑉 L ) and the common mode 𝑉𝑉 DC0 (𝑉𝑉 DC0 = (𝑉𝑉 H + 𝑉𝑉 L )/2). For modelling purpose, 𝛿𝛿𝑣𝑣 dm is the local voltage deviation to the average differential mode Δ𝑉𝑉 0 and 𝛿𝛿𝑣𝑣 cm is the local voltage deviation to the average common mode 𝑉𝑉 DC0 .

The PD expression can be evaluated using Eq. (III-8) (𝛥𝛥𝜃𝜃 𝑘𝑘 = 0). Then 𝜃𝜃 𝑘𝑘 expression of the disturbed triangular wave can be generically written as shown in Eq. (III-31). It can be noted 𝜃𝜃 𝑘𝑘 is composed of a common mode 𝜃𝜃 ̅ (cumulative) and an oscillating mode 𝜃𝜃 ̃ (noncumulative). It should be noted the triangular wave common mode does not modify the period, but it disturbs the PD measurement, i.e. there is no cumulative effect (𝜃𝜃 ̅ = 0). In the other hand, the triangular wave differential mode modifies systematically the period, but does not cause oscillation (𝜃𝜃 ̃= 0).

Performance

Communication noise immunity, mismatch sensitivity, settle time, static error, smooth transient (no duty-cycle discontinuity)

From now, the previous systems' accomplished goals will be summarized. Then, their limitations will be highlighted. A new auto-interleaving method will be proposed, providing appropriate improvements, followed by its detailed theoretical study and its implementation.

Finally, experimental results will be provided to demonstrate the validity of the proposed method.

IV.1.1. Advantages, features to keep

The advantages and features of the two interleaving techniques of chapter II and III to keep in the new approach are listed below.

Advantages shared by both implementations:

8 analog channels of the Tektronix oscilloscope are used to observe the LC errors (top), then 4

the math channels are programmed to show the modal content of the measured errors (bottom).

IV.9.1. Local controller validation

The

IV.9.2. Diagonal response validation

The diagonal/modal responses were be validated using the carrier pre-positioning shown in Figure IV-23. Due to the larger triangle signal amplitude and frequency trim (reduces the pre-positioning gain), an additional 0.5 step was added and the whole gain range (7.5) was

Proof 1: Lead-lag controller stability criterion

The stability criterion can be find by studding the system's modal closed loop poles 𝑝𝑝 1 and 𝑝𝑝 2 . The differential mode natural (homogeneous) transfer function response is shown in Eq.

(A-1).

Poles 𝑝𝑝 1 and 𝑝𝑝 2 can be found by applying the Bhaskara's formula to the denominator, as shown in Eq. (A-2).

Solve the Bhaskara's formula analytically without any considerations proves to be very hard. Looking at the root locus, it can be noticed in Figure II-7(d) that the blue root locus line is always inside the unit circle for α > 0. However, the green root locus line for α > 0 is equals to -1 when it passes through the unit circle. As both poles are real and different, 𝑎𝑎 𝑛𝑛 2 -4 𝑎𝑎 𝑛𝑛 𝑐𝑐 𝑛𝑛 > 0. As the sought pole is the smaller one and 𝑎𝑎 𝑛𝑛 > 0, it comes from the negative square root term. To stay in the unit circle, the simplified condition shown in Eq. (A-2) can be written as shown in Eq. (A-3) to define the stability criterion.

Eq. (A-4) shows the development of Eq. (A-3).

Eq. (A-5) by replacing 𝑎𝑎 𝑛𝑛 and 𝑐𝑐 𝑛𝑛 from Eq. (A-2) in Eq. (A-4) result.

The final condition is find combining this condition with the start one (α > 0).

Proof 2: Triangular carrier self-alignment C(z) corrector expression

The local triangular signal commutation instant is studied to determine the expression of the correction value ∆𝜃𝜃 𝑘𝑘 as a function of the error 𝜀𝜀 𝜃𝜃 and other implementation parameters. To ensure the result is a linear expression, two conditions have to be verified:

1. the PDs are in an ascending sequence as shown in Eq. (B-1);

2. Vtri commutation happens in an instant when 𝑉𝑉 𝑡𝑡ℎ𝑙𝑙𝑛𝑛 has a slope equal to -2 𝑆𝑆 𝑅𝑅 𝛽𝛽, with the constraints shown in Eq. (B-2).

Starting with two basic equations:

Solve ∆𝑥𝑥 2 to ∆𝑥𝑥 1 :

Solve 𝜀𝜀 𝜃𝜃 to ∆𝑥𝑥 1 :

Then:

It proves:

It should be noted that this expression is valid even beyond these limits.

Proof 3: Triangular carrier self-interleaving stability criterion.

The differential close loop eigenvalues formula and its validity conditions are given in Eq. (C-1).

The stability condition shown in Eq. (C-2) is derived from Eq. (C-1), where 𝛼𝛼 ∈ ℝ that respects the inequality has to be find.

Using absolute value properties, the inequality in Eq. (C-2) is rewritten such as in Eq.

(C-3):

There is no 𝛼𝛼 restriction solution if 𝜆𝜆 𝑖𝑖 is a complex number. The only pure real 𝜆𝜆 𝑖𝑖 value is -1 and it leads to a restriction 𝛼𝛼 ≠ -2.

The new inequality in Eq. (C-3) can be rewritten as in Eq. (C-4).

As this is a complex expression, the absolute value operator in Eq. (C-4) can be rewritten by its definition in Eq. (C-5).

where:

𝐼𝐼𝜆𝜆(𝐷𝐷𝑒𝑒𝑒𝑒) = -𝛼𝛼 0.5 𝐼𝐼𝜆𝜆(𝜆𝜆 𝑖𝑖 ) It can be noted that the complex parts in Eq. (C-5) are equal, then, the inequality to be true, it has to respect the condition in Eq. (C-6). 𝑅𝑅𝑒𝑒(𝑁𝑁𝑢𝑢𝜆𝜆) 2 < 𝑅𝑅𝑒𝑒(𝐷𝐷𝑒𝑒𝑒𝑒) 2 (C-6)

An term equal to 𝑅𝑅𝑒𝑒(𝐷𝐷𝑒𝑒𝑒𝑒) can be find in 𝑅𝑅𝑒𝑒(𝑁𝑁𝑢𝑢𝜆𝜆) by adding and removing one unity, i.e. (+1 -1), as shown in Eq. (C-7).

Eq. (C-8) shows the development of the first square of Eq. (C-6).

(

By putting (2 -𝛼𝛼) as a common factor, the expression in (C-8) expression can be rewritten as in Eq. (C-9).

Knowing Eq. (C-10),

Then Eq. (C-11) can be derived from (C-9).

(

The stability criterion in Eq.(C-11) in valid the whole interval shown because the restrictions in Eq. (C-1), Eq. (C-3) and Eq. (C-9) are valid.

Triangular carrier self-alignment simulation guidelines

The system state equations are shown in Eq. (D-1) and Eq. (D-2). This system can then be written in a discrete state space representation for simulation, such as in Eq. (D-3) and Eq. (D-4).

The PDs 𝜽𝜽 are the state variables 𝒙𝒙 are, the local errors 𝜺𝜺 𝜃𝜃 are placed as output variable 𝒚𝒚 for observation. The input signals 𝝋𝝋 and 𝒅𝒅 are placed in the input 𝒖𝒖, as shown in Eq. (D-5).

Any other connection is required because the system is already in the closed-loop form. Being thus, the natural response found is directly the closed-loop system behavior being sought. The local clock is connected in both feedback inputs (VAR). Two charge pumps are also necessary, so their outputs are connected together to feed the loop filter. Indeed, the start-up condition are not so accurate due to noise and mismatches, so the final reached stead-state may not be linked to the initial conditions because at least two stable equilibrium points exist. Additional logic could be added to try to avoid these discontinuities, however these studies will not be carried out in this work.

Combining both PFD outputs in a single charge pump (𝑈𝑈𝛥𝛥 𝑆𝑆𝑃𝑃 = 𝑈𝑈𝛥𝛥 1 + 𝑈𝑈𝛥𝛥 2 , 𝐷𝐷𝑁𝑁 𝑆𝑆𝑃𝑃 = 𝐷𝐷𝑁𝑁 1 + 𝐷𝐷𝑁𝑁 2 ) would result in a gain reduction of 50% outside the region 𝜃𝜃 𝑃𝑃 < 𝜃𝜃 𝑂𝑂 < 𝜃𝜃 𝑆𝑆 , i.e.

when the local is not between the neighbors.

Development of a modular distributed control monolithic fully integrated multiphase converter

This annex is dedicated to the description of an integrated circuit development using NXP SmatMOS10 technology. This approach is intended to mitigate the SPOF in the distributed control architecture. The architecture is the same as the system described in [START_REF] Hillesheim | Reconfigurable Partial-Decentralized Control of a Multiphase Converter for Fail-Operational Automotive Processor Power Supply[END_REF],

shown in Figure F-1, but with improvements in the current balance and interleaving approach, as shown in the previous chapter. With these changes, this device is more robust and goes a step closer to market requirements. The following sections will explain the changes proposed in the current balance architecture, and then describe in detail de implementation of each block.

Distributed voltage regulation and current balance

The AVP technique make the output voltage 𝑉𝑉 𝑜𝑜𝑜𝑜𝑡𝑡 dependent on the converter output current 𝐼𝐼 𝑜𝑜𝑜𝑜𝑡𝑡 . The converter output can be modelled as a voltage reference 𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚 in series with virtual output impedance called usually Load Line 𝑅𝑅 𝑂𝑂𝑂𝑂 . In a multiphase converter with centralized control architecture, the AVP control technique is applied following the static relation 𝑉𝑉 𝑜𝑜𝑜𝑜𝑡𝑡 = 𝑉𝑉 𝑡𝑡𝑖𝑖𝑚𝑚 -𝑅𝑅 𝑂𝑂𝑂𝑂 × 𝐼𝐼 𝑜𝑜𝑜𝑜𝑡𝑡 , where the 𝐼𝐼 𝑜𝑜𝑜𝑜𝑡𝑡 is the sum of all legs currents 𝐼𝐼 𝑖𝑖 .

The AVP can also be implemented to each leg and then combined in the same output, as shown in [START_REF] Zhang | MVRC and its tolerance analysis for microprocessor power management[END_REF], [START_REF] Cousineau | Fully masterless control of parallel converter[END_REF]. Zhang shows in [START_REF] Zhang | MVRC and its tolerance analysis for microprocessor power management[END_REF] that when independent references are used in each regulator, the combined output voltage tolerance is reduced (the shared voltage reference line is not mandatory). Using the shared voltage reference line reduces the leg current differences, but leg current 𝐼𝐼 𝑖𝑖 still dependent on the equivalent local load line characteristic 𝑅𝑅 𝑂𝑂𝑂𝑂𝑖𝑖 .

The circular chain current balance technique shown in [START_REF] Cousineau | Fully masterless control of parallel converter[END_REF] is distributed and has no single point of failure because it uses only module-to-module connections. The current balance is made by adjusting the load line to combine all in the currents in a focal point, as shown in

Circular chain of communication