Frédéric Rouger
email: rouger@laplace.univ-tlse.fr

Richardeau

Yazan Barazi
email: barazi@laplace.univ-tlse.fr

Nicolas Rouger

Frédéric Richardeau
email: frederic.richardeau@laplace.univ-tlse.fr

Comparison between ig Integration and vgs Derivation methods dedicated to fast Short-Circuit 2D-Diagnosis for Wide Band Gap Power Devices

Comparison between ig Integration and vgs Derivation methods dedicated to fast Short-Circuit 2D-Diagnosis for Wide Band Gap Power Devices

Barazi Yazan, Nicolas C.

Introduction

Wide band gap semiconductor materials, such as Silicon Carbide (SiC), have shown a tremendous evolution. However, power semiconductor devices such as Insulted Gate Bipolar Transistors (IGBT) and MOSFET Super Junction (SJ-MOSFET) silicon devices are limited, in terms of maximum switching speeds. Consequently, Silicon power devices have, higher switching losses, large and expensive thermal management systems. On the other hand, SiC MOSFETs are promising power semiconductor devices for high density converters, with low conduction and switching losses, high temperature stability [ 1 ]. However, the short circuit delay time capability for SiC MOSFETs is lower than silicon devices [ 2 ]. Power semiconductors devices are used in various industrial applications (Motor Drives, Battery Chargers, Switch Mode Power Supplies, Converters, …). They are exposed to several types of Short Circuit. HSF (SC type I) and FUL (SC type II) are the two main fault behaviors. Safety is necessary for those typical applications. Several ways of protecting circuits have been presented for either Silicon IGBT's or MOSFET's [ 3 ]. Most of the previous proposed techniques rely on the drain-source voltage or current. This is clearly a limiting approach due to the high voltage diode or additional current sensor used, such as MOSFET-sensecurrent in non-standard dies [ 4-5-6-7 ]. In SiC MOSFETs; the drain current ids is controlled by the gate voltage vgs. Since most Wide Band Gap (WBG) power FETs exhibit a low robustness and a typical fail-to-short behavior, they must be turned-off softly in a few hundreds of nanoseconds, after fault-detection. Good management of the gate voltage results in the best compromise between losses -EMI -safety. The reverse transfer capacitance "Crss = Cgd" of a SiC MOSFET also known as the Miller capacitance, is one of the most important parameters in switching performance for unipolar devices. This capacitance is a nonlinear function of voltages vgs and vds and it provides a feedback between the output voltage vds and the input vgs of the device. In this article, detailed analyses and comparisons between the SC detection methods are presented. LTspice™ simulated results are presented in the view of verifying the SC detection methods to further protect SiC MOSFETs.

ig Integration detection method

Normal Turn-On "NTO"

A useful parameter from the circuit design point of view is the gate charge Qg, in which the gate charge Qgd related to Cgd can be predominant.

𝑄 𝑔𝑇𝑜𝑡 = 𝑄 1 + 𝑄 2 + 𝑄 3 (4)
𝐶 𝑖𝑠𝑠 = 𝐶 𝑔𝑠 + 𝐶 𝑔𝑑 & vgsM= vgsplateau

(5) * In (2) the first integration is added to include the changes of Cgd from t0 to t2 Fig. 1; t2 the beginning of the Miller plateau, the non-included integral when vds starts to fall.

Hard switch Fault "HSF"

Contrary to fault condition type I, when vgs=vgsM at t2, vgs and ids continue to increase until vgs reaches vDrv+ and ids overcurrent, t3, ids=isat-channel. vds stays at the vbus value, which causes the transistor to operate in its saturation regime, as shown in Fig. 2(a). Such a regime can be sustainable only for a couple of µs, as presented in [ 11 ]. The amount of gate charge is QSC-HSF with a 1/Cissmin slope, exhibiting no change in the charging rate of the input capacitance. In this SC operation, there is no discharge of the Miller capacitance. As a consequence, a significant difference appears in the Qg characteristic between NTO and HSF, as shown in Fig. 2(b). An HSF can be detected by monitoring vgs and the amount of Qg, whereas the assessment of the time variable is not directly required. Then, a detection method based on the gate charge is proposed. As mentioned previously, a significant difference appears in the Qg amount, as shown in Qg characteristics, Fig. 2

(b). A detection selectivity criterion can be introduced by the ratio S=(QSC-HSF)/(QgTot).

Fault Under Load (FUL)

Fault condition type II on the other hand appears after the three normal time intervals are accomplished, namely after t4, where the MOSFET is in on-state ohmic mode vgs=vDrv+.

In this fault condition, ids increase to ids-sat (which can be calculated by the trans-conductance curve ids=f(vgs) at vbus), which in turn raises vds to the bus voltage vbus, due to the MOSFET entering the saturation regime Therefore, a reverse current flows into the gate ig<0 through Cgd, due to the Miller coupling; and the capacitance Cgd decreases. All these phenomena lead to the increase of vgs towards a larger value vgsov, see Fig. 3(a). The amount of gate charge is QSC-FUL, which also corresponds to a higher gate voltage vgsov,

Detection circuit based on gate charge monitoring

The proposed method is based on a gate charge characteristic as listed in this paper as the integration method also known as the gate charge method. In general, the charge transferred in time interval is obtained by integrating the current [START_REF] Kudoh | Current sensing IGBT for future intelligent power module[END_REF]. Since the charge needed in this work is the gate charge, the gate current ig under NTO, HSF or FUL is integrated and the gate charge is then calculated for each condition. Using the reference levels vref and Qref presented on the equations below (7-11), the detection of the SC is possible without setting a detection time window [ 14 ]. This principle will be more sensitive and robust for lower QSC-HSF/QgTot ratios. This constraint is far from assured for WBG devices where the Cgd/Cgs ratio is voluntarily minimized by designers to reduce the cross-talk phenomenon in inverter leg operation. As mentioned in Tab. 1, some commercially available SiC devices will be more suitable than others. Commercially available High Voltage GaN power transistors seem poorly adapted to this technique. Higher vref-HSF values lead to a more robust diagnosis, albeit with longer delay times. Nevertheless, it remains a general principle, also named "2D-adaptivedetection", only combining two low-voltage waveforms or signals without resorting directly to time measurement. One can note that this method can be easily integrated in a low voltage ASIC which would not be allowed with a classical high voltage detection Vdssat (Saturation Voltage). Moreover, the Qg method is an integral technique which will introduce less SNR.

𝑄 𝑔 = ∫ 𝑖 𝑔 𝑑𝑡 (
3 Derivation detection method

Behavior and characteristic

Fig. 5 dvgs/dt characteristics under "NTO" and "HSF". (a) Slope detection approach, (b) Dip detection approach. the stars represent the levels obtained for the same gate-voltage, vgs=vref=vstop, with vref > vgsM for the slope approach, and for the dip approach vgs=vstop is not a reference level for comparison.

Even with optimized detection thresholds, the previous method based on the gate-current integration over the gatevoltage range may not be fast enough for SC protection. The following methods provide a more direct quasiinstantaneous detection without the need for gate charge method. The impact of the capacitance Cgd in the switching behavior is demonstrated also on a new detection method based on monitoring the quasi-derivation of vgs. There are three important time intervals on the behavior of vgs as explained above. The first one has a slope of Cissmin, followed by the Miller plateau where Cgd is involved and the last one has a slope of Cissmax. Using this alteration of slopes, a significant impact appears on their time derivatives. Fig. 5 shows the dvgs/dt signal (slightly filtered) under NTO and a SC conditions, where two distinctive changes of slope can be observed. Time interval [t0, t2], in Fig. 5 dvgs/dt signal present, a high peak "Cissmin<Cissmax" followed by a decrease until reaching a dip presenting the plateau period [t2, t3]. A smaller peak occurs at t3 to present Cissmax. The dvgs/dt signal under SC is quite straight forward, where there is only Cissmin as a slope for vgs signal, from t0 to t4 dvgs/dt is the derivation of the slope Cissmin, the dip or the smaller peak is not present. Fig. 5(a) and Fig. 5(b) introduce two different ways to analyze the derivation signal. Other approaches [ 15 ]. From this analysis two detection approaches can be concluded; the first one is based on the changes of the dvgs/dt waveforms, where a threshold level dvref/dt is needed to be fixed for dv/dt signal, to distinguish between Cissmax for NTO and Cissmin for HSF at the threshold level vgs=vref. This threshold level vref is used to activate the lecture of the comparison, as well as, the SC detection, Tab. 4. Fig. 5(a) shows the importance of the vref level (represented by stars), while removing any direct dependence with time. Indeed, the vref detection is indirectly reflected in different times for NTO and HSF. Therefore, the difference between the slopes define the NTO or HSF detections. The second detection approach is based on the detection of the dip in the derivation signal, the presence of Miller plateau. A threshold level dvref/dt is needed as well. Under SC condition, the two approaches do not have any difference detecting at vref the presence of Cissmin or a non-presence of a dip. The approach is to detect the signal above dvref/dt before reaching vref, Tab. 4-5. On the other hand, under NTO condition, the two approaches are almost similar, both of them being based on the detection of the signal below dvref/dt. The only difference is to detect before vgs>vref when the dip is quickly detected or at vgs=vref detecting Cissmax slope changes. The second approach may be faster in NTO operation, where dip detection is before reaching vref. More importantly, the 2 nd approach may help the robustness of the detection by allowing a lower dvref/dt; consequently, a wider discrimination range for a SC detection is offered, avoiding the small critical zone whenever vgsNTO & vgsSC have similar values. The different threshold voltages must be defined from key parameters extracted from the datasheet, operating conditions and experimental results.

Detection circuit based on derivation monitoring and simulation behavior

The proposed method is based on the derivation method. As known, the current that runs through a capacitor is given by the voltage/current relationship [START_REF] Horiguchi | Short-Circuit Protection Method Based on a Gate Charge Characteristic[END_REF], where Cs is the sensing capacitor at the gate of the power device. Using this voltage/current relationship gives the derivative of vgs.

𝑑𝑣 𝑔𝑠 𝑑𝑡 = 𝑖 𝐶𝑠 𝑐 𝑠 [START_REF] Horiguchi | Short-Circuit Protection Method Based on a Gate Charge Characteristic[END_REF] Fig. 6 presents the detection circuit for a constant Rg. The capacitor Cs connected in parallel with the gate is a sense capacitor, sensing the derivation of the voltage vgs. This sense capacitor must be much smaller than the minimum input capacitor of the power transistor (Cs << Cissmin). The ics current passing through Cs is further amplified and converted in a voltage, which is then compared with dvref/dt. Two others comparators with vgs signal are used to create a monitoring window for the readout and detection. Flip-Flops are added for both approaches, the purple parts being the dip detection circuit, and the green ones are the slope detection circuits. Simulations using LT-Spice are performed to verify the validity of the proposed detection circuits. The parameters used in the simulations are a power device C2M0025120D, vbus=600 V, iload=50 A, vDrv= ±5/20 V and Rg=50 Ω. Gate loop and power loop parasitic inductances were included to better reproduce experimental waveforms. The value of Rg is deliberately chosen high for representation purposes. For lower values of Rg, the detection must be faster. Fig. 8 introduces the robustness [ 17-18-19 ], highlighting the effect of different integration windows. Fig. 8 (a) presents the ratio of QSC-HSF/QgTot for different vds and ids. The integration window can be calculated between vgs=-5/+20V or +3/+15.5V. This latter setting offers a smaller QSC-HSF/QgTot ratio, which reduces the stress on Qg detection threshold. The lower the ratio, the easier the detection. As shown in Fig. 10, both methods are independent of time.

Detection and protection circuit simulation based on 2D gate charge monitoring

Detection and protection circuit simulation based on 2D derivation monitoring

The detection time for both methods is below 300ns due to the same reference gate voltage vref 15.5V. Fig. 11 presents how important vref should be early for the detection of SC. With an early vref, an early detection will take place and probably vref interfering with the second peak in NTO mode, causing a false detection. To overcome this interference, the dip method will not take into consideration the second peak, even if there are interferences.

Conclusions and Comparison

This paper introduces two 2D detection method circuits, both of them being time independent. Both methods protect the power circuit in the event of a SC. The gate charge method exhibited a fast detection and protection capability and introduces less SNR under NTO and HSF. The reference levels are the critical values for both methods. The derivation method was presented with two approaches. With the slope approach, oscillation can slightly distort the detection, if the detection is at a critical vref (dvref/dt interfering with dvgs/dt). On the other hand, the dip approach is better due to the dip presence, under NTO condition, even with dvref/dt interfering with dvgs/dt, the detection of a dip occurs before the interference of the second peak. Under HSF, no oscillations are present for both approaches.

For robustness and a fast detection, the highest dvref/dt and the lowest vref the better. In other words, setting dvref/dt higher, will prevent interferences. Defining a low vref, allows an early detection. These techniques will be implemented experimentally and compared with the simulations. Several limitations must be particularly addressed, such as the precise assessment of the threshold voltages with the dip method, the effects of parasitic elements and non-ideal circuits.

Fig. 1

 1 presents the qualitative typical switching waveforms and the different contributions to the total gate charge during Normal Turn On NTO. The first gate charge amount Q1 is defined where 1/Cissmin is its slope (1), in the first time interval [t0 -t2]. Q2 is the second gate charge amount, between [t2 -t3] during the Miller plateau where vds drops from vbus to approximately (vgs-vth) slightly lower than Rdson.Iload while vgs stays constant and Cgd or CMiller starts to discharge, allowing the fast voltage change across the Drain-Source terminals. In the presence of a SiC transistor, a short inversion channel is generally used to reduce the losses in the on-state. This property causes a dependence of vgsplateau to variations in drain voltage than it can be in vertical silicon device (ex. SJ-VDMOS, IGBT…); a slight slope appears instead of the plateau [ 8 ] (2). The third time interval began at t3 with vgs increasing back, until it reaches vDrv+, and gate charge amount Qg reaches QgTot (4), with 1/Cissmax as a slope of the third amount of gate charge Q3 (3). At the end of this time interval, the two capacitance Cgd and Cgs fully charged [ 9 -10 ].

Fig. 1

 1 Fig. 1 (a). Turn-on switching characteristics of SiC MOSFET under NTO condition. (b). Gate Charge characteristics "NTO". (c). Equivalent circuit of the half bridge. *Note (Fig. 1-3): For the purposes of a simple graphical representation, Cgs and Cgd capacitors are taken here as constant values. The voltage drops in on-state of the components (diode and transistor) are also not taken into account for the switching study. A constant Miller plateau is also assumed in the figures. Neither the reverse recovery nor the parasitic inductances are taken into account.

Fig. 2 (

 2 Fig. 2 (a). Turn-on switching characteristics of SiC MOSFET under HSF. (b). 2D representation of the Gate Charge characteristics "HSF" and detection zone with vgs.

Table 1

 1 Ratio detection, the threshold level of vref and Qref need to be in the hatched trapezoid {(Q1, vgsM); (Q2, vgsM); (QSC, vDrv+); (Q3, vDrv+)} of the Fig. 2(b). Hence, this detection method is a two-dimension diagnosis. Most of the time, this Qg characteristic figure is given in the data-sheet under NTO. The choice of the threshold detection levels vref and Qref can then be assessed from the data-sheet. The method is naturally robust against variation in switching delay time due to variation in threshold voltage or current operating point of the load. With a constant threshold level and sense resistor Rs, the detection will simply be a matter of blocks design to obtain the gate charge Qg [ 12 -13 ].

Fig. 3 (

 3 b). A FUL can be detected by monitoring vgs and the amount of Qg, but for different threshold levels of vref and Qref, whose value need to be in the hatched triangle of Fig. 3(b).

Fig. 3 (

 3 Fig. 3 (a). Turn-on switching characteristics of SiC MOSFET under FUL. (b). 2D representation of the Gate Charge characteristics "FUL" and detection zone with vgs above vDrv+.

6 )

 6 𝑣 𝑟𝑒𝑓-𝑆𝑡𝑎𝑟𝑡 = 𝑝. 𝑣 𝐷𝑟𝑣+ (7) 𝑣 𝑟𝑒𝑓-𝐻𝑆𝐹 = 𝑘. 𝑣 𝐷𝑟𝑣+ (8) 𝑄 𝑟𝑒𝑓-𝐻𝑆𝐹 = 𝑘′. 𝑄 𝑇𝑜𝑡 (9) 𝑣 ref-FUL = (1 + r). 𝑣 Drv+ (10) 𝑄 𝑟𝑒𝑓-𝐹𝑈𝐿 = 𝑟′. 𝑄 𝑇𝑜𝑡 (11)With p, k, k', r, r' ponderation multipliers needed for the appropriate position of the reference levels.

Tabs. 2 -

 2 3 simplify the aforementioned figures about the gate charge characteristics and also bring guidance to the detection circuit below[ 7 ], gathering all the data to design the detection circuit. A comparator with vref-Start[START_REF] Oberdieck | Short circuit detection using the gate charge characteristic for Trench/Fieldstop-IGBTs[END_REF] activates the detection circuit. A Differential amplifier at the RS terminals (sensing resistance integrated on the gate driver, Rs<<Rg+Rint) is needed, to create the image of the current ig from the voltage across the sense resistor Rs and then amplify it for a better integration. With those two main blocks (Diff. Amp. Followed by Integrator) we obtain the gate charge Qg, which is then further compared with the threshold Qref-HSF and Qref-FUL levels. Before that, to make sure that the detection is at the right moment, two additional comparators with vref-HSF and vref-FUL are used to activate the monitoring -see Fig.4. For HSF, Tab. 2, when the output of the vref-HSF comparator reaches a logic state '1' (non-priority value of the AND gate), this signal goes through the first input of the AND-HSF gate. The second input will decide the state of the detection circuit: if the calculated Qg is below the Qref-HSF, then the second input (the output of the Qref-HSF) of the AND-HSF gate goes high '1' logic state. The output of the AND-HSF gate goes high as well, which generates a flag for further SC protection. On the other hand, if one of those two inputs; the two outputs of the vref-HSF and Qref-HSF comparators; is in a '0' logic state there is no flag, and no detected SC. For FUL, the same method is applied where both vref-FUL and Qref-FUL comparators outputs need to have a '1' logic state.

Fig. 4

 4 Fig. 4 Fast 2D-diagnosis and protection circuit based on gate charge. Note: Rs=1Ω, R1=R2=20KΩ, other blocks are considered ideals.

Fig. 6 Fig. 7

 67 Fig. 6 Detection and protection circuit based on slope and dip approaches (input Smith triggered gate are not represented). Note: Cs=100pF, Rs=100Ω, other blocks are considered ideals.

Fig. 8 (

 8 Fig. 8 (a). Variation of the Amount of charge for different vds, ids, and vgs. (b) vgs, ig characteristic to present integration period.

Fig. 9

 9 Fig. 9 presents the simulation voltage signal vgs and its derivative under NTO and HSF conditions. Fig. 11 takes further the NTO condition into different ids and vds values.

Fig. 9

 9 Fig. 9 Simulation Waveforms under NTO and HSF condition without the protection circuit.

  Fig. 11 represents a variation of iload and vbus in the circuit, under HSF. Where we can see the oscillation reaches dvref/dt, for low ids & vds. Under SC, dv/dt does not show any oscillation.

Fig. 10

 10 Fig. 10 Simulation Waveforms under HSF condition with the protection circuit. (a) Derivation method, (b) Gate charge method.

Fig. 11

 11 Fig. 11 Simulation Waveforms under NTO condition for different ids and vds without the protection circuit.

Table 2 2D

 2

diagnosis algorithm for HSF Comparator Output Diagnosis If Qg>Qref-HSF AND vgs>vref-HSF then NTO If Qg<Qref-HSF AND vgs>vref-HSF then HSF

Table 3

 3 Diagnosis algorithm for FUL Comparator Output Diagnosis If Qg>Qref-FUL AND vgs<vref-FUL then NTO If Qg<Qref-FUL AND vgs>vref-FUL then FUL

Table 4 2D

 4

diagnosis for HSF, vgs Slope approach Comparator Output If vgs=vref AND dvg/dt<dvref /dt then NTO If vgs=vref AND dvg/dt>dvref /dt then HSF Table 5 2D diagnosis for HSF, Dip approach Comparator Output If dvg/dt<dvref /dt AND vgs<vref then NTO If dvgs/dt>dvref/dt AND vgs<vref then HSF Both approaches can be accurate and robust because they are based on 2D-detection dvgs/dt  iCiss combined with vgs.