Kepa Odriozola

Thierry A Meynard

Alain Lacarnoy

Full-Silicon 98.7% Efficient Three-Phase Five-Level 3-port UPS Architecture with Wide Voltage Range Battery based on Multiplexed Topology

Keywords: Multilevel converters, Emerging topology, Efficiency, Uninterruptible Power Supply, Energy Storage, Batteries, Modulation strategy

This paper proposes a new three-phase Multilevel 3-port converter topology based on Multiplexed topology concept which is especially intended for high-power Uninterruptible Power Supplies (UPS) applications with wide battery voltage range and well adapted for high step-down voltage conversion ratio. Compared to other high-voltage conversion ratio Multi-Cell converters, the Multiplexed concept allows cascading power conversion stages without any intermediate filter and optimizing power density. In the studied case it will be used to transfer power between a 1200V DC source and 400V/480V AC load and grid. The proposed converter topology achieves very high efficiency, up to 98,7% in direct ACto-AC power conversion mode using reduced number of silicon low blocking voltage semiconductor devices. The Hardware In the Loop (HIL) assessment has enabled the development of the modulation strategy and validated the performance of the converter. To validate the feasibility of the Multiplexed concept, both at the topological level and the modulation strategy, of the 5-Level Multiplexed 3-port topology for UPS applications a 100-kW hardware demonstrator featuring a volumetric power density of 3.68 kW/dm 3 (60.3 W/in 3 ) has been built.

Introduction

The growing penetration of renewable energies at worldwide scale is playing a leading role in the evolution of power electronics systems. Therefore, new high efficient power-electronic systems and associated control strategies are needed to make this transition possible. From the introduction of the first well known multi-level topologies [START_REF] Nabae | A New Neutral-Point-Clamped PWM Inverter[END_REF][START_REF] Meynard | Multi-level conversion: High voltage choppers and voltage-source inverters[END_REF][START_REF] Marchesoni | Non-conventional power converter for plasma stabilization[END_REF] to their industrial maturity, many applications have taken advantage of their improved performances [START_REF] Franquelo | The age of multilevel converters arrives[END_REF].

Regarding the already consolidated 1500V technology, several studies [START_REF] Xue | Towards next generation photovoltaic inverters[END_REF][START_REF] Gkoutioudi | Comparison of PV systems with maximum DC voltage[END_REF][START_REF] Serban | DC-Bus Voltage Range Extension in 1500 v Photovoltaic Inverters[END_REF][START_REF] Corba | Future of high power PV´ plants -1500V inverters[END_REF] have shown in the past decade the economic benefits in the PV sector. Many manufacturers have already developed and installed photovoltaic inverters throughout the world and several devices (converters, contactors, combiner boxes, etc.) are already approved by global safety certification companies [START_REF] Abb | Contactors for DC switching -Motor protection and control -ABB[END_REF][START_REF] Mersen | Mersen is fully 1500VDC Ready -Mersen[END_REF]. Along with this, it should be noted that the grid integration of distributed energy sources such as Photovoltaic (PV) systems accompanied by Battery Energy Storage Systems (BESS), both at utility-scale and Behind-the-Meter (BTM) or residential-industrial level [START_REF] Hesse | Lithium-Ion Battery Storage for the GridA Review of Stationary Battery Storage System Design Tailored for Applications in Modern Power Grids[END_REF] is becoming more important. Proof of this are the products that are already available on the market [START_REF] Ingeteam | INGECON SUN STORAGE Power B Series[END_REF][START_REF] Electric | GE Energy Storage Unit[END_REF][START_REF] Sungrow | [END_REF]. This trend, today well established for system-oriented UPSs is now observed for the next generation Giant Data Centers. The installed power capacity in Data-Centers Fig. 1: General schematic of the proposed 3-port DC-AC-AC Multiplexed Power Converter. DC port side is connected to the battery pack system of the UPS. Each AC port is connected either to the grid and the load respectively. is increasing exponentially with the never ending expansion of the global data sphere [START_REF] Reinsel | The Digitization of the World -From Edge to Core[END_REF] and therefore battery-based UPS systems are becoming a key factor for today's Original Equipment Manufacturers (OEMs) and technology firms in this area.

Among the wide variety of industrial applications, UPS systems [START_REF] Dong | Design of hybrid AC-DC-AC topology for Uninterruptible Power Supply[END_REF][START_REF] Lu | Multi-mode operations for on-line uninterruptible power supply[END_REF] as well as other applications such as Medium-Voltage (MV) drives, energy storage systems (ESS), grid-tied systems for distributed generation sources such as PV, wind turbines and microturbines and HVDC (High-Voltage DC) transmission systems [START_REF] Kouro | Powering the future of industry: High-power adjustable speed drive topologies[END_REF][START_REF] Kouro | Recent advances and industrial applications of multilevel converters[END_REF][START_REF] Manuel Carrasco | Powerelectronic systems for the grid integration of renewable energy sources: A survey[END_REF][START_REF] Rodriguez | A survey on neutral-point-clamped inverters[END_REF][START_REF] Rodr´ ´ıguez | Multilevel voltagesourceconverter topologies for industrial medium-voltage drives[END_REF][START_REF] Abu-Rub | Medium-voltage multilevel converters State of the art, challenges, and requirements in Industrial applications[END_REF][START_REF] Yaramasu | High-power wind energy conversion systems: State-of-the-art and emerging technologies[END_REF][START_REF] Rodr´ | PWM regenerative´ rectifiers: State of the art[END_REF] which make use of back-to-back configuration. Typical back to back configuration systems use mainly both identical topologies for inverter and AFE (Active Front End) converter for decoupling the grid from the loads. Therefore, the total cost of this type of conversion systems is double that of a single inverter stage. Therefore, obtaining high efficiency and high power density in this type of conversion architecture, whatever the application, with current semiconductor and magnetics technologies at low cost is still a big challenge. This paper proposes a new three-phase multilevel 3-port converter topology based on multiplexed topology concept [START_REF] Odriozola | Multi-Level Multiplexed Power Converter Topology for 1500V Applications[END_REF] and which is especially intended for high-power UPS applications with wide battery voltage range, which achieves very high efficiency, up to 98,7% in direct AC-to-AC power conversion mode using reduced number of silicon low blocking voltage semiconductor devices. The structure and conversion stage topologies of this Multi-Level Multiplexed topology will be described in Section II -3-Port DC-AC-AC Multiplexed Converter. The modulation strategy for the proposed

3-Port DC-AC-AC Multiplexed Converter

The proposed power conversion architecture (see Fig. 1) is based on multiplexed converter topology presented in [START_REF] Odriozola | Multi-Level Multiplexed Power Converter Topology for 1500V Applications[END_REF][START_REF] Odriozola | Multi-Level Inverter Topologies for Mediumand High-Voltage Applications[END_REF]. As explained above, the most typical configuration in UPS systems is back-toback. Therefore, the most conventional would be to serialize two 5-Level Multiplexed DC-AC Converter stages that share the same DC-link.

However, the concept of control associated with multiplexed converters allows in this case, to mutualize the chopper stages. Thus, the inverter output stage and the rectifier input stage share the same chopper stage. In this way, it is possible to reduce the number of switches drastically and obtain better efficiency with respect to the back-to-back configuration.

The proposed power conversion topology is shown in Fig. 2. In principle, the DC-DC chopper and DCAC inverter can be any converter with two or more voltage levels, under the condition of adapting the modulation scheme according to the selected topological variant. In the studied case, for a maximum voltage of 1200V at the DC-link, different combinations of multi-level topology can be derived. Going from 3 to n levels, where n is the number of voltage levels at the output of each converter. Fig. 2 shows the power circuit of the three-phase 5-Level 3-port DC-AC-AC Multiplexed Power Converter with 3level Flying Capacitor chopper and 3L-T-NPC inverter and rectifier configuration. In this paper only this configuration will be analyzed.

Semiconductor Selection

One of the main features being efficiency and low cost, the selection of semiconductors becomes essential. Only silicon components are used in order to reduce the total cost but of course wide band gap components could be used to reduce losses and improve efficiency and power density.

The first originality of this topology is that the choppers deliver square voltage waveforms with steps of one fourth of the DC-bus; assuming that an appropriate control pattern is used, the voltage applied to the inverter switches may thus be limited to 3/4 or even 1/2 the DC-bus voltage in order to ensure high immunity to cosmic rays [START_REF] Felgemacher | Cosmic radiation ruggedness of Si and SiC power semiconductors[END_REF] and obtain a high reliability, which of course helps maintaining a high efficiency. In our case, the inverter and rectifier stages are realized with 1200V, 75A High Speed IGBTs IKY75N120CS6 from Infineon. The typical voltage across the semiconductors of the flying capacitor chopper is 1/4 of the DC-bus voltage, and 650V, 75A Low-VCEsat IGBTs IKZ75N65ES5 from Infineon have been selected here. In order to handle the high current of the load and to reduce the conduction losses, each switch consists of four TO-247 package devices in parallel.

Voltage Balance on Flying Capacitors

In order to limit the overvoltage on the inverter and rectifier we must guarantee a correct balancing of the flying capacitors. In the offline power conversion mode and in the battery recharge mode, the power flow circulates through the choppers flying capacitors. In this way, under normal circumstances, it is possible to obtain a natural balance of the capacitors [START_REF] Richardt | Natural balance of multicell converters: The two-cell case[END_REF]. However, in the AC-AC direct energy conversion mode, the power flow circulates from the grid directly to the load via the variable DC-bus. Therefore, the current circulating through the flying capacitors is negligible even though the choppers continue to operate to generate in the variable DC-bus (VDC(Aux)) the maximum and minimum part of the voltage of the two three-phase systems (grid and load). Due to imperfections of the control there will also be small unwanted current components; the inherent self-balancing property of these converters might be lost which is not acceptable because unbalanced voltages could destroy the semiconductors.

To guarantee balancing of the flying capacitors there are various techniques and we can distinguish active and passive methods. In order to avoid introducing additional distortions on the differential voltage pattern of the choppers by means of the duty cycle correction [START_REF] Amer | Voltage-balancing method using phase-shifted PWM for the flying capacitor multilevel converter[END_REF] the passive methods will be preferred here. Among the passive methods there are different circuits described in the literature like [START_REF] Meynard | Analysis and design of multicell DC/DC converters using vectorized models[END_REF][START_REF] Fang | Harmonic sources and filtering approaches-series/parallel, active/passive, and their combined power filters[END_REF]. However, these linear circuits as well as the non-linear variants are designed considering several assumptions, one of these being a constant supply voltage of the converter. A balance-booster design [START_REF] Papamanolis | Behavior of the Flying Capacitor Converter Under Critical Operating Conditions[END_REF], be it internal or external, that follows the input voltage variations becomes complicated, mainly due to its limitations from the implementation point of view.

For this reason, it has been decided to use an RLC circuit [START_REF] Meynard | Modeling of multilevel converters[END_REF]. This shunt passive filter essentially acts as a notch filter connected in parallel to the output of each chopper offering a very low impedance at the switching frequency of these choppers. When the voltage of the flying capacitor is unbalanced, each chopper generates at the output, voltage harmonics at the switching frequency. Since the RLC filter is tuned to the switching frequency (i.e. 8kHz) it presents very low impedance, ZLC (2•π• fChop), forcing the circulation of harmonics of current at the same frequency that favor the rebalancing of the capacitors. The inductance and capacitance values used in simulation for the RLC circuit are given in Table I and the design values in Table II.

Modulation Strategy

Unlike conventional three-phase topologies, the multiplexed topology does not have independent phase legs. Therefore, each conversion stage module must be controlled separately. As a basic principle of modulation, sinusoidal PWM modulation can be used to make it simple.

Similar to the modulation strategy described in [START_REF] Odriozola | Multi-Level Multiplexed Power Converter Topology for 1500V Applications[END_REF] the main concept is to generate respectively the highest and the lowest part of the 6 voltages (3 of the grid and 3 of the load) by respectively Top and Bot choppers. Doing so, 2 of the 6 inverter legs can be saturated and stop switching. The 4 other inverter/rectifier legs need to switch to generate the appropriate grid side and load side three-phase voltage systems.

Chopper Modulation

Regarding the control of DC-DC choppers, the main objective is to generate the highest and lowest side of the both grid side and load side three-phase voltage systems. The chopper section involving capacitors has a strong requirement to ensure that the average current is zero and that the voltage of this capacitor can be regulated. Another objective will be to minimize the static voltage seen by the inverter stage in order to respect the voltage rating of the inverter switches. As a first approach, self-balancing mechanism can be tried by applying a carrier based PWM modulation scheme such as Phase Shifted (PS) [START_REF] Thierry | Multicell converters: Basic concepts and industry applications[END_REF]. Another possibility is to use Phase Disposition (PD) by means of state machines like in [START_REF] Cougo | PD modulation scheme for three-phase parallel multilevel inverters[END_REF] and [START_REF] Peter Mcgrath | Optimal modulation of flying capacitor and stacked multicell converters using a state machine decoder[END_REF], but in this kind of schemes extra commutations are needed and the balancing of flying capacitor could become complex. We therefore use PS sawtooth carriers at 8kHz switching frequency are used for having the absolute control of turn-on and turn off moments or rising-up and falling-down instants of the voltage created by each chopper.

Rising sawtooth carriers for the Top chopper and falling sawtooth carriers for the BOT chopper have been selected. In order to minimize the static voltage, VDC,Aux (cf., Fig. 2) seen by the inverter and rectifier stages over the majority operating points, there will be a relative phase shift of some switching periods between the Top and Bot choppers carrier signals. In this way when high modulation index is required, consecutive steps of voltage levels on the differential voltage of the chopper outputs can be avoided. The feature of the Flying Capacitor converter to double the apparent frequency at the output leads to a chopper switching frequency equal to half that of the inverter. Consequently, the switching losses are reduced too. This switching frequency ratio between chopper and inverter must be respected if the calculation of the inverter and rectifier duty cycle (introduced in the next section) is to be accurate.

Inverter Modulation

The voltage generated at the output of the inverter and rectifier must be synthetized by means of the voltage already switched by choppers. Hence, the duty cycle for inverter and rectifier is defined in function of choppers duty cycles and inverter and rectifier voltage reference. For that, duty cycles of each output inverter and rectifier arm are determined separately by means of two-dimensional look-uptables using a pre-calculated PWM method. Contrary to the disadvantages of this type of techniques [START_REF] Leon | The Essential Role and the Continuous Evolution of Modulation Techniques for Voltage-Source Inverters in the Past, Present, and Future Power Electronics[END_REF][START_REF] Mohamed | A Review of Multilevel Selective Harmonic Elimination PWM: Formulations, Solving Algorithms, Implementation and Applications[END_REF], in this case, the computational cost of the algorithm is not high and duty cycles can be calculated with a high accuracy. The calculation of duty cycles is made off-line throughout two piecewise interpolations and explained more in depth in [START_REF] Odriozola | Multi-Level Multiplexed Power Converter Topology for 1500V Applications[END_REF]. The applied modulation scheme has the intrinsic property of freezing the inverter phase legs when necessary. Once the duty cycle is computed, a dedicated scheme of modulation must be applied for the inverter and rectifier output stages. Gate signals must be generated in function of selected topology. For our configuration, three-phase three-level T-type NPC has been chosen. For being compatible with the chopper modulation and mainly with the inverter duty cycle offline calculation we must choose carriers at 16kHz switching frequency such that they are in counterposition to the chopper carriers. In this case, the upper switch cell of the inverter must depend on the carriers of the Top chopper and vice versa. Therefore, having selected rising sawtooth carriers for the Top chopper then the carrier modulating the upper cell of the inverter must be of type falling sawtooth carrier. In this way, we ensure that the interpolation equations with which the duty cycle table is constructed to control the inverter stage are fair. Moreover, each switch cell will guarantee ZVS (Zero Voltage Switching) operation for inverter and rectifier arms (at least one turn-on or turn-off per switching period in function of the selected rising or falling front carrier configuration) thanks to the extra slight phase shift introduced between Top and Bot choppers and inverter stage carriers. Consequently, the desired switching pattern is obtained for the inverter and rectifier, thus only two phase legs are swiching at a time when both three-phase voltage systems have same amplitude, one on the grid-side, the other on the load-side.

Control Strategy

New regulations (i.e. IEC, IEEE 1547, etc.) impose more functionalities on electrical energy conversion devices in order to interact with the different types of current networks. These devices must be able, for example, to provide a certain amount of reactive power during a certain period of time in order to cope with eventual accidents or instabilities that may occur.

In practice, to fulfill the requirements imposed on today's new UPS equipment, different types of control laws can be applied to the proposed topology. Depending on the mode of operation, the management of the direction of the active (PLoad, PGrid) or reactive power (QLoad, QGrid) flow will be different. Thus, we can distinguish mainly the inverter mode of operation, the battery charging mode in rectifier operation (cf., Fig. 4a), the grid following or grid forming mode of operation, and the AC-to-AC direct energy conversion mode (cf., Fig. 4b) which is enabled thanks to the mutualization of the chopper stage. In the AC-to-AC direct power conversion mode, unlike conventional back-to-back configurations in which all energy passes through the DC-link, the proposed topology partially bypasses the DC-link: power may be transferred from grid to load via only the inverter and rectifier.

It is necessary to emphasize that for all the above-mentioned operating modes, it is necessary to apply a preload strategy of DC-bus capacitors voltage as well as chopper flying capacitors, in order to guarantee a balanced distribution of the total DC link voltage [START_REF] Sepahvand | Start-up procedure and switching loss reduction for a single-phase flying capacitor active rectifier[END_REF][START_REF] Amer | Initial capacitor charging in grid-connected flying capacitor multilevel converters[END_REF]. At any moment of the preload, it is necessary to ensure that the flying capacitor is charged to its nominal voltage. This is achieved by combining a classic preload method via a resistance that is later bypassed and a DC-bus voltage control loop that takes care of charging the DC link to the battery voltage in boost power conversion. The RLC filters connected in parallel to the output of each chopper will ensure that in case of unbalance the distribution of the voltage is compensated.

Simulation Results

The performance of the three-phase 5-Level DC-AC-AC Multiplexed Converter has been simulated in the PLECS R software using specifications described in Table I. All operating modes have been tested in simulation as well as the thermal performance of the converter using semiconductors described in Subsection -Semiconductor Selection. the illustrated scenario, the DC-bus (battery voltage) is 1200V, the inverter works in open loop with a reference voltage between phases equal to 400V/50Hz while the rectifier works in PFC mode with closed loop control of the grid currents. In this mode, power is transmitted directly (AC-AC power conversion mode, Fig. 4b) from the mains to the load without passing through the DC-bus, i.e. the battery, thus reducing overall losses and increasing efficiency. The grid voltage is 440V/50Hz with a relative phase shift of 60 with respect to the load voltage. It can be observed that at all times the choppers are responsible for synthesizing the maximum and minimum of the two three-phase systems (grid and load). It can also be seen that the voltage ripple of the flying capacitors is kept below 5% of the nominal voltage thanks to the RLC filters.

Fig. 5 shows the efficiency map of the converter in single DC-AC power conversion mode (cf., Fig. 4a) for different values of load DC-bus (battery) voltage. The same efficiency is expected for the converter in grid-forming mode when rectifier stage is working as inverter. Loss distribution per each conversion stage (2x 3-Level Flying Capacitor Chopper Stage and Inverter Stage) of the theoretical design is shown in Fig. 6. Fig. 7 shows the efficiency map of the converter operating the system in AC-AC power conversion mode (cf., Fig. 4b

Experimental Results

To validate the proposed strategy and the suitability of the 5-Level Multiplexed 3-port topology for UPS applications, the HIL test system and hardware implementation of the three-phase 5-Level 3port Multiplexed topology will be presented in the following.

Hardware-In-the-Loop (HIL)

The digital implementation of the proposed modulation and control strategy and all operating modes, including start-up precharge strategy of flying capacitors and DC-bus, has been validated via HIL. The control is implemented by coding two Real-Time Imperix B-Box RCP 3.0 that interfaces with the TyphoonHIL 602+ system. Fig. 9 shows the HIL waveforms of the proposed converter during inverter operating mode.

L(V) i L(W) i L(U) V U 0

Hardware Implementation

To validate the feasibility of the multiplexed concept of the 5-Level Multiplexed 3-port topology for UPS applications, a 100-kW hardware demonstrator shown in Fig. 10 has been built using components described in the Table II.

Experimental Waveforms

The main measured waveforms taken with a resistive load and operating the system in inverter mode are presented in Fig. 11 for 15.7 kW operation. The five output voltage levels are shown for phase U together with the Top chopper output voltage (VTOP), as well as the load phase voltage and currents. We can deduce from the shape of the 5-Level voltage of the phase U (VU0) that the voltage of the flying capacitors is kept balanced thanks to the RLC filters.

Conclusions

In this paper, a 98.7% 3,68kW/dm 3 three-phase 3-port multilevel converter topology based on Multiplexed structure was proposed. This topology has the ability to achieve a high step-down voltage con- Cascading inverter and choppers without intermediate filtering elements leads to a reduction of the voltage applied to the switches of the inverter and rectifier stages (in some cases ZVS operation is possible), thus reducing the switching losses and indirectly the conduction losses (since switches with a lower voltage rating can be used). The switching losses in the inverter are also reduced because the Max and Min voltage waveforms of both grid and load three-phase systems are synthesized by the choppers, so at any time two of the inverter legs are not switching. These features enables switching at relatively high frequency and helps in the end to obtain a high power density. Moreover, compared to conventional single three-phase multilevel topologies it reduces the number of modules needed because of the mutualization of the chopper stage. It should also be noted that it only uses only silicon low blocking voltage semiconductors devices reducing the overall cost of converter.

Furthermore, a higher efficiency can be obtained in AC-to-AC power conversion mode by allowing the main power transfer via the inverter stages only, with a very small portion of currents flowing via the chopper stages. In this paper an appropriate control strategy for the novel topology is presented.

Simulations have been conducted on the PLECS software environment with good results especially in terms of efficiency. Real time feasibility of the control strategy has been checked using two Imperix B-Box RCP 3.0 and Typhoon HIL 602+ devices and a scale 1 prototype has been built and is now ready for testing. The first experimental results (up to 55 kW) have globally demonstrated a good behaviour of the converter, being able to validate at the same time the feasibility of the topological architecture of the converter based on the "Multiplexed" concept as well as the modulation strategy proposed for it.

We can already identify improvement margins for the final prototype. Due to the high efficiency of the topology, the size of thermal cooling system could be significantly reduced. It would also be possible to replace the power modules by paralleled 4-pin TO-247 package switches (as proposed at the theoretical study) which would greatly simplify the PCB design and reduced parasitic stray inductances between the chopper and inverter stages. The RLC Shunt filters could also be embedded on the PCB. These, improvements could lead to optimize overall power density of the converter and better fit to the standard rack-size of the Data-Center oriented UPS systems.

Fig. 2 :

 2 Fig. 2: Detailed schematic of the 5-Level three-phase 3-port DC-AC-AC Multiplexed Power Converter. The chopper stage consists of two 3L-Flying Capacitor converters. Both inverter and rectifier stage consists of three-phase 3L-T type NPC converters.

Fig. 3 :

 3 Fig. 3: Main simulation waveforms of the 5-Level three-phase 3-port DC-AC-AC Multiplexed Power Converter (see Fig. 2) operating with a DC-link (Battery) voltage of 1200V during direct AC-AC power conversion mode (cf., Fig. 4a) and a load output power of 50kW. (a): Grid reference voltages; (b): Load reference voltages; (c): Chopper output voltages, VTOP in green, average value of VTOP in blue, VBOT in red, average value of VBOT in yellow; (d): Multi-level voltage of the node A at the input of the Rectifier stage referenced to the DC-link midpoint (cf. Fig. 2); (e): Grid phase currents; (f): Multi-level voltage of the node U at the output of the Inverter stage; (g): Inverter filter inductor voltage of phase U; (h): Load phase currents; (i): Flying Capacitor voltages. Please note that the grid and load voltages are phaseshifted by 60• making the choppers generate the maximum of the 6-voltage system.

  (a) DC-AC power conversion mode. (b) AC-AC power conversion mode.

Fig. 4 :

 4 Fig. 4: Power transfer flow in the proposed three-phase 3-port Multiplexed Converter for different modes of power conversion.

Fig. 5 :Fig. 6 :

 56 Fig. 5: Efficiency map of the 5-L three-phase 3-port DC-AC-AC Multiplexed Power Converter in single DC-AC power conversion mode (cf., Fig. 4a) feeding a 50 kW resistive load for different line-toline load voltage and DC-bus voltage values

Fig. 7 :Fig. 8 :

 78 Fig. 7: Efficiency map of the 5-L three-phase 3-port DC-AC-AC Multiplexed Power Converter in direct AC-AC power conversion mode (cf., Fig. 4b) feeding a 50 kW resistive load for different line-to-line grid and load voltage values and identical phases and for VDC= 900V and VDC=1200V.(a) VDC = 900V (b) VDC = 1200V

Fig. 3

 3 Fig.3shows the multilevel performance of the three-phase 5-Level Multiplexed Converter (illustrated in Fig.2) over two periods of fundamental output frequency. Regarding the simulation conditions for

Fig. 9 :

 9 Fig. 9: Hardware In the Loop (HIL) waveforms of the five-level output voltage of the phase U of the 5-Level three-phase 3-port DC-AC-AC Multiplexed Power Converter shown in Fig. 2 (300 V/div, referenced to the DC-link midpoint, 5 ms/div) and the three-phase (u,v,w) load currents (120 A/div) during inverter operating mode at 50 kW. The HIL real-time waveforms are in accordance with the simulation results shown in Fig. 3.

  i

Fig. 10 :

 10 Fig. 10: Hardware prototype of the 100kW three-phase 5-Level DC-AC-AC Multiplexed Converter, measuring 420mm 880mm 110mm (16.53 in 34.64 in 4.33 in). The final volumetric power density (without considering RLC Shunt filters, output and input LC filters of each AC port and auxiliary power) is 3.68 kW/dm 3 (60.3 W/in 3 ).

Fig. 11 :

 11 Fig. 11: Experimental waveforms of the five-level 5-Level three-phase 3-port DC-AC-AC Multiplexed Power Converter shown in Fig. 2 operating the system in inverter mode for 15.7 kW operation (VDC=600V, Vu=150V, iL(U)=35A). (a): V(u,v,w) (100 V/div), Load phase voltages; (b): VTOP (100 V/div), output voltage of the Top 3-Level Flying Capacitor Chopper; (c): iL(U,V,W) (20 A/div), output filter inductance currents; (d): VU0 (100 V/div), five level output voltage of the phase U referenced to the DClink midpoint.

Table I :

 I Specifications of the 5-Level three-phase 3-port DC-AC-AC Multiplexed Power Converter.

	Grid filter capacitance
	Parameter	Symbol Value
	Nominal Power	Pnominal 50kW
	DC bus voltage	VDC	900V-
			1200V
	Grid voltage	U(a,b,c)	400V-480V
	Grid frequency	fGrid	50-60 Hz
	Load voltage	U(u,v,w)	400V-480V
	Load frequency	fLoad	50-60 Hz
	Chopper switching frequency	fChop	8 kHz
	Inverter/Rectifier switching frequency fSw	16 kHz
	Flying Capacitor	CF1,CF2 150 μF
	RLC circuit inductance	LS1,LS2	200 μH
	RLC circuit capacitance	CS1,CS2	2 μF
	Grid filter inductance	Lf(a,b,c)	200 μH

Cf(a,b,c) 50 μF Load filter inductance Lf(u,v,w) 200 μH Load filter capacitance Cf(u,v,w) 50 μF

  ) for different values of load and mains voltage and two constant values of battery voltage. Loss distribution per each conversion stage (2x 3-Level Flying Capacitor Chopper Stage, Inverter Stage and Rectifier Stage) of the theoretical design is shown in Fig.8. We can observe this time how the losses within the Flying Capacitor choppers have been drastically reduced with respect to the inverter mode of operation. Most of the losses, around 90%, are located in the inverter and rectifier stages.

Table II :

 II Main components of the hardware prototype.

	Inverter/Rectifier Stage Switches		Infineon 1200V 300A
	(3L-T-NPC Switches)		FF300R12KE4
			Infineon 1200V 300A
			FF300R12KE4 E (Common Emitter)
	Gate Driver		Custom PCB Schneider Electric
	CDC1, CDC2	4800 μF Epcos TDK B43643
	CF1, CF2	280 μF	Kemet C4AEGBW5350A3JJ
			75 turns, 100 strand x 200 μm Litz
	LS1, LS2	200 μH	wire
			Core: Micrometals T300-8/90 T300
	CS1, CS2	1,88 μF Kemet R75UR34704040J
	Lf(a,b,c), Lf(u,v,w)	150 μH Traftor T10125-M09
	Cf(a,b,c), Cf(u,v,w)	132 μF	Epcos TDK B32354S
	Component	Value	Part Number
	Chopper Stage Switches		Mitsubishi 1200 400A
	(3L-FC Switches)		FMF400BX-24A

version ratio which makes it suitable for new low-medium voltage applications with wide range of input voltage such as UPS systems.


Andre Furlan

Alvaro Morentin

Guillaume Fontes

Guillaume Delamare

Marcelo L Heldwein

Thierry Meynard

Andre Furlan´

Homothetic Method to Compute Winding Losses in the Design of Power Inductors

Keywords: Winding resistance, finite element analysis, magnetic components, air gap

ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

I. INTRODUCTION

Dowell's equations [START_REF] Dowell | Effects of eddy currents in transformer windings[END_REF] are often used to calculate the equivalent ac resistance (RAC) of inductor windings, taking skin and proximity effects into account. These equations are derived through a 1D approximation to calculate the window magnetic field under certain simplifying hypotheses. However, inductors are generally gapped, and this 1D approximation is not applicable since the fringing field of the air gap cannot be described in a 1D manner [START_REF] Muehlethaler | Modeling and multi-objective optimization of inductive power components[END_REF]. Gapped inductors can be accurately analyzed using the finite element method (FEM) with the computation efforts and CPU time that this represents. When a fast computation of the RAC is needed, to avoid a computationally intensive finite element simulation, some works applied tuned equations based in Dowell's methods [START_REF] Holgun | Simple analytical approach for the calculation of winding resistance in gapped magnetic components[END_REF] [START_REF] Xi | An improved calculation of proximityeffect loss in high-frequency windings of round conductors[END_REF]. In such works, additional coefficients are introduced through a data fitting process against FEM results. The derived relation coefficients depend on the inductor geometrical parameters. Consequently, this approach can be used only for specific geometries. Some analytical methods for gapped inductors are presented in [START_REF] Muehlethaler | Modeling and multi-objective optimization of inductive power components[END_REF] [5] [START_REF] Wallmeier | Improved analytical modeling of conductive losses in gapped high-frequency inductors[END_REF]. Nevertheless, a final validation with a FEM simulation is indispensable.Fig. 1 describes a typical power inductor design procedure. After a fast design, using the area product approach (AwAc) [START_REF] Meynard | Analysis and Design of Multicell DC/DC Converters Using Vectorized Models[END_REF], with the geometric parameters, the winding loss can be evaluated through different methods. Following this evaluation, the calculated and projected power losses are compared. If the error is greater than the tolerance, the design process is repeated once again, using a correction loss factor.

In this work, a general approach based on the interpolation of a surface that is pre-computed using 2D FEM is proposed to obtain the RAC of a generic E-core inductor in a reduced CPU time. Thus, generating a process that is adequate for use in iterative and optimization design tools. The homothetic properties of these structures as well as relations between different conductivities are explored to reduce the number of variables. Generating this surface requires a high computational effort. Nevertheless, it can be used in the design of an arbitrary number of inductors after being computed offline.

First, the topology of the studied inductor is presented, and Dowell's equations are derived with two different approaches: neglecting the gap in the calculation of the orthogonal magnetic field (HE) and considering the gap in the evaluation of HE.

After describing the formulation, the homothetic and conductivity relations are studied to reduce the number of variables of the problem. Different values of inductor geometric parameters are combined, and many FEM simulations have been run to establish a reduced multidimensional FEM surface. RAC is then evaluated through direct multivariate linear interpolation from the FEM results. The resulting values are shown to match FEM simulations more closely than analytical formulations.

II. CHARACTERISTICS OF THE FOIL INDUCTOR

Fig. 2 describes the cross section of the right-side corewinding window of an E-core inductor that is built with foil conductors using air gaps in the center and outer legs. The following parameters are defined: • µcr: core relative permeability;

L core dx h i h i/2 ω W l gap b F h c L leg dx h i/2
• kw: winding fill factor. Ratio between the winding section area and the winding window area without spacing (kw = N • hc/w).

III. CLASSICAL ANALYTICAL FORMULATION

Two different approaches for Dowell's equations are analyzed in this section. The first approach is widely used in previous works: it was developed for ungapped cores, resulting in the classical Dowell's equation. The second approach considers the gap in the expression of the orthogonal field (HE). Usually, little details are given about the formulation and its application.

Classical methods to compute RAC are based in the orthogonality existing between skin effect and proximity effect in conductors. This makes possible to decouple the two effects and simplifies the analysis [START_REF] Ferreira | Improved analytical modeling of conductive losses in magnetic components[END_REF]. In the next subsections, these effects will be described in terms of losses for a sinusoidal excitation at frequency f in order to calculate RAC.

A. Skin Effect

The skin-effect losses for a single winding layer (including DC losses) per unit length is calculated as [START_REF] Muehlethaler | Modeling and multi-objective optimization of inductive power components[END_REF] (1

)
where Ib is the peak current flowing through the coil, ∆ is the foil conductor thickness normalized to the skin depth (√ hc/δ), δ is the skin depth (1/ πµ0σf), µ0 is the vacuum permeability, rDC is the single layer DC resistance (1/(σbFhc)), and FSkin is the factor that describes the rise of the conductor resistance due to the skin effect (2).

(2)

B. Proximity Effect

The losses due to the proximity effect for a single winding layer are described as [START_REF] Muehlethaler | Modeling and multi-objective optimization of inductive power components[END_REF]

PProx = FProx • rDC • HEavg 2 (3)
where FProx is a factor that describes the amount of winding losses due to the proximity effect [START_REF] Xi | An improved calculation of proximityeffect loss in high-frequency windings of round conductors[END_REF] and HEavg is the average value of the two magnetic fields of the two sides of the coil, illustrated in Fig. 3 and described by the following equation [START_REF] Van Den Bossche | Eddy current losses and inductance of gapped foil inductors[END_REF] where m is the number of the layer, and [START_REF] Wallmeier | Improved analytical modeling of conductive losses in gapped high-frequency inductors[END_REF] where hcg is the magnetic field at the center gap. Usually, this variable is not included in the Dowell's method demonstration, which would lead to a better understanding of Dowell's equations.

With ( 5) and ( 6), HEavg 2 becomes

h c H Eavg b F H m H m+1

C. Total Losses

The total proximity losses per unit length for N turns is

N PProxTot = FProx • rDC • X HEavg2 ( 8
)
m=1
where For an ungapped core lg = 0. Thus,

for The total losses per unit length including proximity and skin effects can be found with

N PTot = X(PProx + PSkin) (12) m=1
1) Ungapped Core: For ungapped cores [START_REF]Soft Ferrites and Accessories -Data Handbook[END_REF] becomes where RDC = NrDC. Thus, it follows that, Equation ( 14) presented in [START_REF] Muehlethaler | Modeling and multi-objective optimization of inductive power components[END_REF] is equivalent to classic Dowell's formulation presented in several works, in particular [START_REF] Shen | An AC resistance optimization method applicable for inductor and transformer windings with full layers and partial layers[END_REF]. Indeed, by applying ( 15) into ( 14), the classic Dowell's equation ( 16) is obtained.

2) Gapped Core: For the gapped core shown in Fig. 2, (12) becomes the above expression gives, Equation (18) differs from the classical approach (16), and it is found in the literature much less frequently, in particular (18) is found in [START_REF] Holgun | Simple analytical approach for the calculation of winding resistance in gapped magnetic components[END_REF].

IV. MULTI-DIMENSIONAL SURFACE DESIGN

The construction of a regular homothetic multi-dimensional surface is proposed in this study. This surface can be used in the Fitting Approaches described in Fig. 1, allowing a simple multivariate interpolation to evaluate RAC for generic gapped E-core inductors. In the multivariate problem, linear multidimensional interpolation is an attractive choice due to its computation speed and simplicity.

Throughout this section, the homothetic properties of the proposed surface, as well as relations between different conductivities, are explored to reduce the number of variables. Finally, the surface construction is described.

A. Homothetic

A possible approach to reduce the number of variables is to consider fixed shapes of magnetic cores with dimensions that vary according to a homothetic law [START_REF] Forest | Analytic Design Method Based on Homothetic Shape of Magnetic Cores for HighFrequency Transformers[END_REF].

According to Dowell's equations, for two inductors with foil conductor thicknesses hc1 and hc2, to have the same RAC/RDC, we need to have ∆1 = ∆2, i.e. hc1/δ1 = hc2/δ2. For homothetic inductors, N1 = N2 and kw1 = kw2, thus, w1/δ1 = w2/δ2 (19) Therefore, instead of working directly with the frequency in our design of experiments, we can use the foil conductor thickness normalized to the skin depth (w/δ). The geometric compensation is contained inside this relation. For the same foil materials (σ1 = σ2) applying the relation (19) and the skin depth equation leads to (20) where Kg12 = w1/w2 is the geometric factor of two homothetic inductors.

All geometric variables must follow the geometric factor to take advantage of the homothetic property, except the w/δ ratio, where the geometric factor is already implicit. To have a homothetic surface, we can set a geometric parameter and change the other parameters in function of their relations with it.

B. Conductivity Relations

Another important advantage of working with the w/δ ratio is that the same surface, constructed by fixing a winding material, can be used for different coil conductivities. The conductive factor is also implicit in the thickness of the foil conductor normalized to the skin depth. For two identical inductors with only different winding material, the relation (19) becomes:

δ2 = δ1 =⇒ f2 = f1Kσ12 (21)
where Kσ12 = σ1/σ2 is the conductivity factor of two identical inductors with different foil conductivities, σ1 and σ2, respectively.

C. Surface Construction

The multivariate regular grid surface implies that all possible combinations between the different variables are covered. To generate this surface, the value of the fixed parameter needs to be chosen. Upper and lower limits for the remaining variables are defined. The discretization of the resulting intervals and a FEM simulation for each of the possible combinations are done in the sequence. The resulting total number of points on the surface depends on the number of different discrete values of each variable.

The flowchart illustrated in Fig. 4 describes the construction of the proposed homothetic surface. Subsequently, each item of this flowchart will be discussed.

1) Variables of the Problem :

In order to construct a regular grid surface, the relative permeability of the core is fixed to 2100, and aluminum foil conductors are used for the inductor winding. Eight variables result, namely: f, N, W, w, Lcore, Lleg, lgap, and kw.

2) Fixed-value Parameter : The variable W was chosen to be fixed. Then the following function represents the multidimensional surface It can be noted that all variables of (22) are dimensionless, which is a typical characteristic of a homothetic problem. In terms of simulation, W was fixed to a small value (0.05 m). Although the surface is constructed with a fixed W, due to the homothetic property, as we are working with geometric normalized variables, this surface can be used to interpolate any value of W. A reduced maximum frequency for larger topologies is identified by considering (20), which is not a problem for the design since higher frequencies tend to reduce magnetics size.

3) Discretization of Parameters: The next step is to determine the range of the ratios between the remaining geometric variables and the fixed-value parameter (w/W, Lcore/W, Lleg/W and lgap/W). To define upper and lower limits for the core variables Lcore/W and Lleg/W, the E cores present in [START_REF]Soft Ferrites and Accessories -Data Handbook[END_REF] were taken as reference. The minimum and the maximum air gap normalized by the core window select for our test surface were W/200, and W/2, respectively. The winding window (w) was set between 50% and 99.8% of W. Finally, the winding fill factor was set between 0.2 and 0.8, and the number of turns was limited to 10, to reduce the calculation time to construct the surface test. The discretization of the variables intervals is described below: The total number of FEM simulations to construct a regular grid surface with the above variables intervals is:

range(N)• L l 4)
FEM Design: The 2D FEM simulations have been carried out with the FEMM software [START_REF] Meeker | Finite Element Method Magnetics[END_REF]. The harmonic magnetodynamic formulation is used to calculate the equivalent Fig. 5. Reduced FEM Domain resistance of the windings. Details of its formulation are found in [START_REF] Ida | Electromagnetics and Calculation of Fields[END_REF].

Due to the symmetry of the problem, only one-quarter of the domain is modeled as shown in Fig. 5. The application of Asymptotic Boundary Conditions (ABC) is proposed for the FEMM model, which is a way to approximate an open boundary, other than truncation, as described in [START_REF] Meeker | Finite element method magnetics[END_REF]. Classical Neumann and Dirichlet boundary conditions are applied for the symmetric axes of the model, x and y, respectively.

Mesh refinement is essential to increase the accuracy of finite element calculations. The mesh refinement must be compatible with the skin depth (δ) of the winding. Usually, 1.5 to 2 elements per skin depth are required for a correct solution [START_REF] Ida | Electromagnetics and Calculation of Fields[END_REF]. In this work, the conductors were divided into layers of δ-thickness from the surface layer up to a depth of 3δ. Assuming the maximum size of each triangular element is equal to δ/2 in these layers, and outside of these layers the finite element mesh automatically generated by FEMM, as shown in Fig. 6, a sufficient level of refinement is achieved leading to consistent results. In order to test the accuracy of the new method, the RAC/RDC values of 1000 randomly-chosen design points are obtained from the constructed surface by direct multivariate linear interpolation.

The interpolation is implemented using the SciPy library, an open source scientific library for Python used for scientific and technical computing [11]. Particularly, the interpolation is done with the scipy.interpolate.RegularGridInterpolator class, an interpolation method on a regular grid in arbitrary dimensions. A linear interpolation method has been chosen and will be called to interpolate each required design.

The random points are created between the upper and lower limits of the variables of the problem described in (23). For the width of the core window (W), fixed in our FEM simulation, we explore the homothetic property with random values between 0.005 and 1 m, spanning a very wide range of applications. The random variables are described in (24). NRand = int(random [START_REF] Dowell | Effects of eddy currents in transformer windings[END_REF][START_REF] Forest | Analytic Design Method Based on Homothetic Shape of Magnetic Cores for HighFrequency Transformers[END_REF]) Lcore/WRand = random(0.4,1.2) w/WRand = random(0.5,0.998) Lleg/WRand = random [START_REF] Dowell | Effects of eddy currents in transformer windings[END_REF][START_REF] Holgun | Simple analytical approach for the calculation of winding resistance in gapped magnetic components[END_REF] (24) lgap/WRand = random(0.005,0.5) kwRand = random(0.2,0.8) w/δRand = random(1,500) WRand = random(0.005,1) Formulations ( 18), ( 16) and the proposed interpolation method are compared in Fig. 7 relative to FEM simulations. The errors are respectively defined as where RACtest can be the RAC calculated with (16), (18) or by the interpolation method. The results with the proposed method are more accurate than analytical calculations as shown in Fig. 7. The mean absolute error applying ( 16) is lower than the mean absolute error of (18). Otherwise, with (16), the data values are more spread out As shown in Tab. I, the estimated absolute error (Mean ± Std) in this application of the proposed method is 6.7 ± 7.0, a lower value comparing to 37.3 ± 25.8 (16) and 73.7 ± 10.6 (18). Although the estimated absolute error is lower with the Dowell classic formulation than with the air gap formulation, its variance is much higher when compared to the other approaches. What was expected by looking at the Fig. 7, where the Dowell (16) distribution is more spread out than the Dowell (18) distribution. Therefore, a correction factor would be more easily applied to (18) than to (16).

Err[%]

VI. CONCLUSIONS

This work proposed an improvement for taking into account ac winding losses in the inductor design process, where the geometrical parameters are not defined before starting the design.

First, special attention was paid to Dowell's formulations. Several works use the Dowell's method applying (18) or ( 16) to calculate inductors the equivalent resistance of the windings, but, usually, no more details are given about the equations. However, it was shown that these equations give different results. Generally, both formulations can have significant errors compared to FEM simulation.

A new homothetic method was proposed for E-core inductors, improving RAC calculations. The presented method consists of the construction of a homothetic multivariate regular grid FEM surface, from which RAC is obtained through direct multivariate linear interpolation. In the surface construction, the geometric variable W (width of the core window) was set, but due to the homothetic properties, the proposed surface can be used to interpolate any value of W. The same surface can also be used for winding materials with different conductivities.

The results with the proposed method typically are more accurate than analytical calculations. The accuracy of the new approach could be further improved by increasing the discretization of the problem variables, at the cost of more computational effort. However, this computation can be performed offline once and used a posteriori for designing an arbitrary number of different inductors.

Fig. 1 .

 1 Fig. 1. Inductor design procedure.

Fig. 2 .

 2 Fig. 2. Cross section of the right-side core-winding window of an E-core inductor.

•

  f : excitation frequency [Hz]; • N: number of turns; • Lcore: core leg width [m]; • W: core window width [m]; • w: winding window width [m]; • Lleg: core leg height [m]; • bF: core window total height [m]; • hc: foil conductor thickness [m]; • hi: insulation thickness [m]; • lgap: air gap length [m]; • dx: distance between coil insulation and vertical core legs (dx = (W -w)/2) [m]; • σ: foil conductivity [S/m];

Fig. 3 .

 3 Fig. 3. Cross section of a foil conductor that is influenced by an external magnetic field (HE)

Fig. 4 .

 4 Fig. 4. Proposed Homothetic Surface.

[

  N] = [1,5,10] [Lcore/W] = [0.4,0.8,1.2] [w/W] = [0.5,0.7,0.8,0.98,0.99,0.998] [Lleg/W] = [1.0,1.5,2.0,2.5,3.0] (23) [lgap/W] = [0.005,0.05,0.5] [kw] = [0.2,0.4,0.6,0.8] [w/δ] = [0.1,10,25,100,250,500]

Fig. 6 .

 6 Fig. 6. Mesh Refinement Criteria V. RESULTS

Fig. 7 .

 7 Fig. 7. RAC errors: Dowell (16), Dowell (18) and Interpolation.

  the mean. The comparison is more evident in Tab. I, with the evaluation of the mean and the standard deviation (Std) of |ERRACtest%|, maximum and minimum values of ERRACtest% and variance of ERRACtest%.

TABLE I MEAN

 I , STANDARD DEVIATION (STD), MIN AND MAX OF ERRORS AND VARIANCE


Cristian Verdugo
email: cristian.andres.verdugo@upc.edu

Samir Kouro
email: samir.kouro@usm.cl

Christian A Rojas

Marcelo A Perez
email: marcelo.perez@usm.cl

Thierry Meynard
email: thierry.meynard@laplace.univ-tlse.fr

Mariusz Malinowski

Five-Level T-type Cascade Converter for Rooftop Grid-Connected Photovoltaic Systems

Keywords: grid-connected photovoltaic systems, cascade multilevel converters, multistring converters, Ttype converters

Multilevel converters are widely considered to be the most suitable configurations for renewable energy sources. Their high-power quality, efficiency and performance make them interesting for PV applications. In low-power applications such as rooftop grid-connected PV systems, power converters with high efficiency and reliability are required. For this reason, multilevel converters based on parallel and cascaded configurations have been proposed and commercialized in the industry. Motivated by the features of multilevel converters based on cascaded configurations, this work presents the modulation and control of a rooftop single-phase grid-connected photovoltaic multilevel system. The configuration has a symmetrical cascade connection of two three-level T-type neutral point clamped power legs, which creates a five-level converter with two independent string connections. The proposed topology merges the benefits of multistring PV and symmetrical cascade multilevel inverters. The switching operation principle, modulation technique and control scheme under an unbalanced power operation among the cell are addressed. Simulation and experimental validation results in a reduced-scale power single-phase converter prototype under variable conditions at different set points for both PV strings are presented. Finally, a comparative numerical analysis between other T-type configurations to highlight the advantages of the studied configuration is included.

Introduction

Rooftop photovoltaic (PV) energy conversion systems (less than 20 kW), have become a well-established technology in the industry. The most common configurations for single-phase grid-connected PV systems commercially found are the string, multistring and ac-module integrated topologies. Central and string inverters have been widely applied to manage and control PV energy systems [START_REF] Kouro | Grid-Connected Photovoltaic Systems: An Overview of Recent Research and Emerging PV Converter Technology[END_REF]. Among the string topologies, the transformerless H5, H6, HERIC, neutral point clamped (NPC) and T-type NPC converters have been successfully commercialized [START_REF] Jedtberg | Analysis of the Robustness of Transformerless PV Inverter Topologies to the Choice of Power Devices[END_REF]. In fact, multilevel inverters (MLI) are designed to produce a stepped voltage waveform by reducing the Total Harmonic Distortion (THD) and the voltage stress across semiconductor devices. Secondly, reduction of the output filter size and power footprint also permit an important improvement in terms of costs, weight and efficiency [START_REF] Kouro | Recent Advances and Industrial Applications of Multilevel Converters[END_REF]. These technical features have led to the massive adoption of MLI over the last thirty years for high-power medium voltage (MV) motor drive applications. In the last years, three-level neutral point clamped (3L-NPC) converters have been used for interfacing PV systems into the grid, where a higher PV incorporation has brought substantial concerns on power efficiency, power quality and grid code compliance [START_REF] Kouro | Grid-Connected Photovoltaic Systems: An Overview of Recent Research and Emerging PV Converter Technology[END_REF] as well as power grid services [START_REF] Muñoz-Cruzado-Alba | Power production losses study by frequency regulation in weak-grid-connected utility-scale photovoltaic plants[END_REF].

T-type neutral point clamped inverters (3L-TNPC), also known as neutral point piloted converters (3L-NPP), [START_REF] Wang | Diode-Free T-Type Three-Level Neutral-Point-Clamped Inverter for Low-Voltage Renewable Energy System[END_REF] have gained a wide presence in the industry sector due to several advantages as symmetrical loss distribution, higher overall efficiency, small footprints [START_REF] Shi | A 60-kW 3-kW/kg Five-Level T-Type SiC PV Inverter With 99.2% Peak Efficiency[END_REF] and low harmonic injection in relation to the conventional 3L-NPC [START_REF] Schweizer | Design and Implementation of a Highly Efficient Three-Level T-Type Converter for Low-Voltage Applications[END_REF]. In fact, many manufactures such as Fuji, On Semiconductor, Mitsubishi and Semikron have commercial T-type legs used in central PV inverters and motor drive applications [START_REF]Semikron: 3L NPC and TNPC Topology[END_REF][START_REF]Infineon: 3-Level configurations[END_REF][START_REF]OnSemiconductor: Q0PACK Modules[END_REF]. For the threelevel inverter, based on the T-type leg, was presented thirty-five years ago for motor drives, with the bidirectional medium switch being realized with thyristors and improved with GTO-thyristors [START_REF] Joetten | AC drive with three level voltage source inverter and high dynamic performance micropocessor control[END_REF]. After some years, many configurations based on the well-known three-level T-type NPC leg can be found in the literature [START_REF] Salem | T-Type Multilevel Converter Topologies: A Comprehensive Review[END_REF]. In [START_REF] Xue | A new class of single-phase multilevel inverters[END_REF] a five-level TNPC (5L-TNPC) was introduced, which corresponds to the parallel connection of two 3L-TNPC legs [START_REF] Almeida Cacau | Five-Level T-Type Inverter Based on Multistate Switching Cell[END_REF][START_REF] Aly | Modulation Method for Improving Reliability of Multilevel T-type Inverter in PV Systems[END_REF]. Furthermore, a variation of this configuration with reduced switches, also known as fivelevel hybrid T-type NPC (5L-HTNPC), was presented in the recent literature [START_REF] Valderrama | A Single-Phase Asymmetrical T-Type Five-Level Transformerless PV Inverter[END_REF]. This topological variation is built with a 3L-TNPC leg and a two-level leg inverter, forming a five-stepped voltage waveform in the AC terminals.

In the literature there are two main possibilities for increasing the number of levels in the power converter field, which is by increasing the internal DC capacitors connected to a single DC source or by connecting several converters in the series at the AC side, in which each converter has an independent DC source. Focusing on the second alternative, cascade MLI can be developed by using symmetrical or asymmetrical voltage levels and by using different type of topologies such as: Full H-Bridge, 3L-TNPC converters or by performing a hybrid configuration [START_REF] Limones-Pozos | Design and analysis of a single-phase transformerless multilevel 7L-TT-HB cascade inverter for renewable energy applications[END_REF]. Note that symmetrical cascade configurations have had a more industrial presence as the case of Cascade H-Bridge (CHB) converters [START_REF] Kouro | Recent Advances and Industrial Applications of Multilevel Converters[END_REF] due to modulation and control simplicity compared with asymmetrical configurations [START_REF] Chang | Design and of a STATCOM Based on a Multilevel FHB Converter with Delta-Connected Configuration for Unbalanced Load Compensation[END_REF]. In fact, in [START_REF] Yoo | Multi-Ievel Medium-Voltage Inverter[END_REF] a symmetrical nine-level Ttype converter (9L-TNPC) is presented for motor drive applications, which is based on the cascade connection of two 5L-TNPC converters. The same number of levels can be generated with advanced hybrid topologies as presented in [START_REF] Shi | A 60-kW 3-kW/kg Five-Level T-Type SiC PV Inverter With 99.2% Peak Efficiency[END_REF][START_REF] Salem | T-Type Multilevel Converter Topologies: A Comprehensive Review[END_REF].

Considering the advantages and features previously presented regarding the 3L-TNPC and symmetrical cascaded configurations, this paper described and validated the 5L-CTNPC topology for rooftop PV applications by using a cascaded connection of two 3L-TNPC legs which was firstly introduced in [START_REF] Verdugo | Series-connected T-type Inverters for single-phase grid-connected Photovoltaic Energy System[END_REF] as a cascade 3L-TNPC converter. Thus, the advantages of symmetrical cascade configurations with multistring inputs are merged. Each 3L-TNPC converter can interface a dedicated DC bus, and consequently two separate maximum power point tracking (MPPT) algorithms are allowed to obtain the maximum power of each PV string. Note that the PV string of each module can be sized to handle half the entire PV string in the conventional 3L-TNPC converter, providing better MPPT efficiency since less modules are combined in a series per string. The main contribution of this paper is the experimental validation of a simplified control scheme to alleviate the power unbalancing mismatch between 3L-TNPC modules and to compensate capacitor voltage variations per each converter, which was presented earlier in [START_REF] Verdugo | Series-connected T-type Inverters for single-phase grid-connected Photovoltaic Energy System[END_REF]. Furthermore, a brief comparison between five-level voltage waveform converters based on the conventional 3L-TNPC is performed as a second contribution in terms of the main electrical features.

The rest of the document is organized as follows. In Section 2, a hardware description of the proposed converter, switching states and implemented modulation is presented. In Section 3, a simple stationary reference-frame voltage-oriented control and a voltage control loop to compensate a possible power unbalance operation are included. Then, in Section 4, simulation results and experimental verification of the proposed multilevel converter and its control system behavior are added. Furthermore, a brief comparison with the 5L-TNPC and 5L-HTNPC is performed to highlight the main advantages of the proposed configuration. Finally, in Section 5, the conclusions of the paper summarize the work done.

The 5L-CTNPC Converter Topology

The power topology of the analyzed cascade 5L-CTNPC for a rooftop grid-connected PV system is depicted in Figure 1. The configuration is composed of a series connection of two 3L-TNPC legs, where each of them is built with two conventional IGBTs and one bidirectional switch. This bidirectional switch could be formed either by two conventional IGBTs in common-emitter or by a common-collector and reverse blocking IGBT connection. Actually, a classical IGBT semiconductor structure could be replaced by a reverse blocking MOSFETs for a high-voltage [START_REF] Mori | Demonstration of 3 kV 4H-SiC reverse blocking MOSFET[END_REF] and high-switching frequency operation [START_REF] Gurpinar | Single-Phase T-Type Inverter Performance Benchmark Using Si IGBTs, SiC MOSFETs, and GaN HEMTs[END_REF]. Although more than two cells in a series connection are conceptually feasible, for the sake of simplicity, two-cell 3L-TNPC converters have been introduced as a proof-of-concept applied to conventional string rooftop PV applications. Each 3L-TNPC leg operates as a string inverter connected to a single potential-induced degradation converter which is fed by one PV string. This potential-induced degradation stage can be designed to boost the DC voltage and perform the MPPT. Furthermore, it could be isolated [START_REF] Chub | A Review of Galvanically Isolated Impedance-Source DC-DC Converters[END_REF] to avoid leakage currents due to the PV aluminium metallic frame grounded [START_REF] Kouro | Grid-Connected Photovoltaic Systems: An Overview of Recent Research and Emerging PV Converter Technology[END_REF]. To reduce leakage currents paths and avoid high-frequency transformers there are three successful options well-documented in the literature: Changing the modulation stage to avoid switched common mode [START_REF] Valderrama | A Single-Phase Asymmetrical T-Type Five-Level Transformerless PV Inverter[END_REF], by reducing surface conductivity of PV modules to avoid potential-induced degradation (PID) and by including extra switches between the PV array and the inverter, also well-known as transformerless inverters [START_REF] Dargahi | Fundamental Circuit Topology of Duo-Active-Neutral-Point-Clamped, Duo-Neutral-Point-Clamped, and Duo-Neutral-Point-Piloted Multilevel Converters[END_REF]. Although, a potential-induced degradation stage is desired to provide an independent DC voltage control, in this work, the validation of the proposed configuration does not integrate a potential-induced degradation stage, giving place to the worst case scenario under study where the MPPT control is fulfilled directly from each 3L-TNPC power cell, instead of using a high frequency galvanic isolated converter with its appropriate MPPT control. Thus, the overall control loops are more challenging since the voltage fluctuations in the PV panel is directly presented in the DC-side of each 3L-TNPC module, i.e., vdck = vpvk, where k = {1, 2} is given by the number of cell. Furthermore, in order to extract the maximum power from the PV panels, an integration of an external MPPT algorithm is required so as to define the appropriate DC voltage reference in each cell. Note that the proposed topology is modeled without affecting the basic control objectives.

Fundamental Principle of the 5L-CTNPC

The 3L-TNPC provides three-output voltage levels: vdck/2, 0 and -vdck/2, where k is the cell or module number. These voltage steps are generated by connecting the AC terminals to the positive, neutral and negative pole of the DC-link terminals. Although, the 3L-TNPC configuration gives rise to four switching states, in order to avoid a short-circuit to the DC side there are only three of them possible. The cascade connection of two 3L-TNPC cells permits the generation of five voltage steps, where the zero level is combined into just one at the AC converter output voltage vc. According to the switching states presented in Table 1, the output voltage in the 5L-CTNPC can be modeled as:

vc = (S11 + S12 -1)vdc1 +(S21 + S22 -1)vdc2 , (1) 2 2 | {z } | {z } vc1 vc2
where vc is the addition of the converter voltages of both modules, S1k and S2k are the switching states of the k-th 3L-TNPC unit and vdck/2 is the total DC-link voltage of each cell. Furthermore, the dynamic model of the AC current in terms of the output voltage is governed by the next expression:

di s vc = isRs + Ls + vs,
(2) dt with vs as the grid voltage measured at the point of common coupling (PCC), is as the grid current, Ls the grid filter inductance and Rs is the filter resistance included for modeling purposes. According to Table 1, the switching states are able to generate nine voltage levels in the output voltage vc where each state has an associated voltage level in function to the DC-link vdc1 and vdc2. Note that in this rooftop PV application both strings will be considered to work with similar DC-link voltages, i.e., vdc1 ≈ vdc2 = vdc. By doing this, the output voltage vc can be reduced just to ±vdc, ±vdc/2 and 0. This assumption leads to five switching states with similar output voltage steps between two consecutive levels [START_REF] Verdugo | Series-connected T-type Inverters for single-phase grid-connected Photovoltaic Energy System[END_REF]. The redundant switching states will be used to balance the voltage in the DC-link capacitors by adjusting the power mismatch between the converter cells.

The computed peak amplitude of the converter output voltage vˆc is equal to vpv1/2 + vpv2/2, i.e., each power cell has a DC-link equal to the maximum level of the converter voltage. Therefore, for a proper grid current regulation, each PV string must be designed to satisfy vpv1 ≈ vpv2 > vs. In fact, this aspect is a practical advantage of cascaded configurations, since the overall DC-link voltage of the central configuration is split among power cells, thus reducing the string size.

Table 1. Switching states and output voltage in the AC terminals.

State S11 S12 S21 S22 vc

1 1 1 1 1 vdc1/2 + vdc2/2 2 1 1 0 1 1 3 0 1 1 1 2 7 0 1 0 0 -vdc1 8 0 0 0 1 -vdc2 9 0 0 0 0 -vdc1/2 - vdc2/2 2.

Proposed Hybrid LS-PWM and PS-PWM Modulation Scheme for 5L-CTNPC Converter

The proposed modulation scheme for the 5L-CTNPC is based on two well-known carriers based on the sinusoidal PWM methods. The first is the Sinusoidal Level-Shifted Pulse Width Modulator (LS-PWM), used in 3L-NPC three-phase converters [START_REF] Serbane | Modulation Effects on Power-Loss and Leakage Current in Three-Phase Solar Inverters[END_REF] and the single 3L-TNPC legs [START_REF] Verdugo | Series-connected T-type Inverters for single-phase grid-connected Photovoltaic Energy System[END_REF]. This modulation strategy requires two carrier signals in phase, to generate the three voltage levels in the output terminals of each cell. One carrier signal has a positive polarity (0 to 1) and the other has a negative polarity (-1 to 0). Furthermore, the LS-PWM is merged with the Sinusoidal Phase-Shifted PWM (PS-PWM) conventionally used in cascaded H-bridge power converters [START_REF] Leon | The Essential Role and the Continuous Evolution of Modulation Techniques for Voltage-Source Inverters in the Past, Present, and Future Power Electronics[END_REF]. In the PS-PWM modulation, a phase shift between the carrier signals of each series connected to a power cell is introduced to increase the number of voltage levels, giving rise to a five-level stepped voltage waveform. The operation principle of this hybrid modulation technique is illustrated in Figure 2, where m * ck and vck are the modulation signal and the output voltage in the k-th cell, respectively. Note that each cell uses two carrier signals defined as vcr1 and vcr2. Thus, the stacked connection of both cells creates the converter voltage vc, which is commanded by its reference v * c. The combination of both methods is simpler in respect to the space vector modulation (SVM) [START_REF] Lee | Hybrid PWM Strategy for Power Efficiency Improvement of 5-Level TNPC Inverter and Current Distortion Compensation Method[END_REF]. Finally, the implementation of this modulation technique is depicted in the block diagram of Figure 3, where simple comparators and two carrier signals are required to implement the proposed technique.

Overall Control Strategy

In this work three decoupled control stages are programmed to regulate the current injected into the grid, the power generated by each PV string and the power mismatch between cells. The first one is the MPPT, which set the DC-link voltage reference for both cells and is optionally included to extract the maximum power from the PV panels in case of direct connection to the 3L-TNPC modules. This control stage is complemented with the total DC-link control loop based on the energy interchange between the power cells. The second control stage is the single-phase voltage-oriented control loop, which has an embedded stationary current control loop implemented with Proportional Multi-Resonant (PMR) controllers. The last control loop is in charge of attenuating the DC-link voltage differences to compensate power mismatch issues among each cell of the converter. The overall control scheme is presented in Figure 4, where vpvk, ipvk, vdck and sok are the PV voltage, PV current, DC-link voltage measurement and gating pulses of each k-th module.

MPPT and Outer DC-Link Controller

The well-known Perturb and Observe (P&O) MPPT routine has been implemented for simplicity in this application. As the analyzed power configuration features two separate DC-links or PV string connections, two independent MPPT algorithms are required to obtain its full power operation. The MPPT routines compute the voltage reference for each DC-link v and v , as illustrated in Figure 4. Then, the DC-link control loop is designed to manage the total energy of the system through the difference between the voltage reference and the voltage measured, i.e., eT = e1 + e2. This total energy is governed by using a proportional-integral (PI) controller, which generates the amplitude of the injected grid current iˆs. Note that the DC-link voltage measurements are acquired and processed with a notch filter Gf to eliminate the second harmonic ripple 2ωs presented in the DC-link capacitors by the rectification of a single-phase grid voltage. In fact, not filtering this harmonic voltage component will generate an undesired third harmonic 3ωs component in the grid current reference. The MPPT parameters such as voltage step ∆vpv and time period Tk are designed according with conventional commercial values. In experimental results, the voltage step ∆vpv = 6 V and the time period Tk = 2 s, whereas in simulation results, ∆vpv = 6 V and the time period is ten times smaller than the experimental results. Furthermore, the DC-link compensator has been designed by using a DC-link control bandwidth of 14Hz. Major details about the outer control design can be found in [START_REF] Verdugo | Series-connected T-type Inverters for single-phase grid-connected Photovoltaic Energy System[END_REF].

PMR Current Control Scheme

The grid current reference is generated by multiplying the amplitude of the injected grid current iˆs with a unitary sinusoidal signal synchronized to the grid voltage. To avoid voltage measurement noise and low frequency harmonic components, a second order generalized integrator (SOGI) with a synchronous reference frame phase lock loop (SRF-PLL) is implemented to set the synchronous angle. Then, the grid current reference is * is compared with the current measured value is, giving rise to a current error which is regulated by using a PMR control scheme. The structure of the implemented controller is included in Figure 5 and expressed as following:

Ci(s) = kp + h=∑1,3,5 s2 +2kihh2sωs2 ( 3
)
where kp is the proportional gain and kih is the resonant gain at each selected h-th harmonic. Note that the above resonant controllers have been considered to achieve selective harmonic impedance enhancement at 3st and 5th components. The resonant frequency at ωs is equal to the grid frequency, hence the compensator Ci(s) has infinite gain at ωs, providing perfect sinusoidal tracking with zero steady-state error. The PMR compensator in Figure 5 has been designed by a simple pole placement with a crossover frequency of 270 Hz, which corresponds to a rate twenty times faster than the outer control loop. This control scheme is currently adopted for grid-connected PV systems where the grid voltage has important low-frequency harmonics [START_REF] Teodorescu | Grid Converters for Photovoltaic and Wind Power Systems[END_REF].

Voltage Balancing Control and Power Balance Scheme

As mentioned, correct power distribution between both cells and a control strategy to avoid voltage unbalancing in the DC-link capacitors is required to provide full operation in the 5L-CTNPC. The compensation block shown in Figure 6 is separated into two parts. The first one is the DC-link balancing control between cells, whose purpose is to regulate the power mismatch by increasing or decreasing the general modulation index amplitude, also referred to as the normalized inverter voltage vc delivered from the current controller. In this control loop, the DC voltage error is regulated by using a PI controller and then the voltage compensator ∆mc is multiplied by the normalized inverter voltage reference vc [START_REF] Kouro | Control of a cascaded H-bridge multilevel converter for grid connection of photovoltaic systems[END_REF]. Therefore, the cell with higher power will increase its modulation amplitude, as the cell with lower power reduces its modulation amplitude. The second part of the control loop is given by the voltage balancing between the internal capacitors in the DC-link, where the voltage error is controlled using another PI controller. The output signal of this compensator ∆md is added to the modulation index provided by the cell voltage control by moving in the vertical axis the modulation index for capacitor balancing purposes. Both PI controllers have been designed by a pole placement strategy, using a bandwidth of 5 Hz. This dynamic has been imposed to avoid fast disturbances into the modulation signal. Note that the proposed balancing control scheme does not need extra measurements, since they are previously accessible from the outer control stage.

Results

Simulation and experimental results of the proposed configuration are presented in this section. The simulation analysis has been performed through MatLab/Simulink for control purposes, while PLECS were used for modelling the modulation stage, power converter, grid voltage and PV strings. The analysis was completed by using the same scenarios of the experimental set-up just to improve the concept verification.

The key simulation and experimental parameters are identified in Table 2. It is important to highlight that simulation parameters have been selected according to the reduced power experimental prototype.

Simulation Results

The first simulation result presented the injected grid current is with reference is * and both capacitor voltages for each power cell under steady-state operation. In Figure 7, it is possible to appreciate the good regulation and synchronization in respect to the grid voltage vs performed by the grid current control and the synchronization control loop. Furthermore, in Figure 8, the voltage balancing control is demonstrated, where the upper vdcu,k and lower vdcl,k voltage capacitors for each k-th power cell are well balanced. The second simulation results present a dynamic operation under two different scenarios. An irradiation step from 1 kW/m 2 to 0.8 kW/m 2 was applied to the lower cell, maintaining 1 kW/m 2 of irradiation in the PV string connected to the upper cell. After the irradiation step took place, a temperature step changes was performed from 25 • C to 18 • C to the upper cell, generating an increase in the power. The irradiation and temperature changes were introduced in a simplified PV model provided by PLECS. Figure 9 shows the dynamic operation of the DC-link voltage vdck and the power at DC-side Pck = vdck •ipvk for each k-th cell. It is possible to appreciate how the irradiation step at t = 3.5 s only affected to the lower module, producing a voltage perturbation and a power reduction in Pc2. Since the reference voltage is provided by the P&O algorithm, the stepped voltage was required to maintain the maximum power operation. In the second scenario, the temperature decreased at t = 8 s and the DC voltage as well as the power in the upper module increased. The three-level voltage vck of each converter cell, and the overall five-level voltage vc are depicted in Figure 10 under unbalance operation. Additionally, it is possible to appreciate how the power reduction in the lower arm affects the modulation indexes mck, creating signals with different magnitudes.

Time(s)

Experimental Results

The experimental PV system comprises of two 3L-TNPC power cells without isolation and were fed directly by one PV string. Each string was composed by two PV modules emulated with the Agilent E4360 solar array simulator, which enabled a total control of the temperature and irradiation parameters. Each simulator has two output channels connected in series to emulate the PV string generator. The parameters such as maximum power Pm, current at maximum power imp, short-circuit current isc, voltage at maximum power vmp and open-circuit voltage voc are listed in Table 2. The simplified layout of the experimental small-scale setup is depicted in Figure 11. The control algorithm is fully programmed in C code by using a dSPACE 1103 digital control platform running at 15 µs. The modulation stage and dead-time generation is implemented by using a FPGA Spartan3. To experimentally validate the proposed control scheme, three different operation points are evaluated. A steady-state operation, and two dynamic operation under an irradiation and a temperature step.

The first experimental results shown in Figures 12 and13 are analyzed during steady-state operation. The grid-side variables i.e., grid current and voltage waveforms are presented in Figure 12, where the unitary power factor operation is achieved. Furthermore, Figure 13 captures the output voltage of each cell and the total voltage composed by a five-level waveform. Similar to the simulation results, the steadystate performance of the capacitor voltage balancing in Figure 14 The second set of experimental results during dynamic operation is shown in Figures 15 and16. Firstly, an irradiation step from 1 kW/m 2 to 0.8 kW/m 2 was applied to the second PV cell (lower cell operating at reduced power), while the first array irradiation level was retained. After this irradiance step variation, a temperature step change was tested from 25 • C to 18 • C and applied to the first PV cell (upper cell operating at increased power). Under the above conditions, the input voltages generate a three-level waveform signal due to the use of the conventional P&O MPPT method. Note that under both scenarios, the coupling effects from one cell to each other is fully avoided, ensuring a decoupled operation between power cells.

Brief Comparison with Other Five-Level T-type Converters

A comprehensive comparison between three different five-level T-type converters have been presented in Table 3. The studied topologies are the proposed 5L-CTNPC, the hybrid version 5L-HTNPC and the conventional 5L-TNPC. Each topology presents the same features of the one described in simulation and experimental results. To evaluate the power efficiency of each converter, switching and conduction losses is required in respect to the power operation point for each cell. Semiconductor device losses are included with a thermal model library developed in PLECS, based on the manufacturer datasheet [START_REF]IGBT Model IXXK100N60C3H1 Datasheet[END_REF]. The resulting efficiency evaluation is depicted in Figure 17, where the obtained efficiency of the proposed configuration 5L-CTNPC is equal to the conventional 5L-TNPC. Due to the fact that there is a reduced number of switches at the second parallel leg in the 5L-HTNPC a slightly higher efficiency was achieved. This analysis is corroborated by counting the number of semiconductor devices used for each evaluated topology, which is summarized in Table 3.

The symmetrical topology configuration and the multiple MPPT possibilities are the main advantages of the studied topology in respect to the rest power converters. Finally, in Figure 18 the current spectrum for each evaluated converter topology is computed. The current THD obtained with the proposed topology is similar to the conventional 5L-TNPC power topology, while the worst value (over 4.9%) was reached in the 5L-HTNPC configuration. In fact, the apparent switching frequency of this topology was equal to the carrier frequency, while in the proposed 5L-CTNPC and 5L-TNPC the apparent switching frequency was twice the switching frequency.

Conclusions

In this work a grid-tied PV system configuration based on a series connection of three-level T-type inverter cells was described and validated. The proposed power topology merged the benefits of multistring configurations with more than one independent MPPT capability and the benefits of cascade Hbridge converters, generating a five-level output voltage waveform in the AC terminals. The proposed topology, modulation and control scheme were validated experimentally in a reduced scale power prototype with a straightforward implementation. Additionally, the proposed control strategy was evaluated under steady-state and unbalanced power conditions, ensuring a decoupled operation between both power cells. Finally, a brief comparison for key merit figures was included, where the main advantages of the proposed topology among other T configurations were highlighted, giving rise to the possibility of enhancing the power extraction from the PV side due to the multi-string configuration.

Author Contributions: C.V. conceived, designed and performed the experimental evaluations; S.K. provided insight on the power topology and conceptual solution, and was responsible of supervision throughout the work; C.A.R. wrote the manuscript and was part of the development team of the experimental test-bench, M.A.P. was responsible for the guidance during the prototype design stage, T.M. and M.M. provided relevant key theoretical and technical suggestions.

Conflicts of Interest:

The authors declare no conflict of interest.

Abbreviations

The

3L-TNPC 1 Figure 1 .

 11 Figure 1. Proposed 5L-CTNPC power topology.

Figure 2 .Figure 3 .

 23 Figure 2. Proposed modulation scheme for 5L-CTNPC based on the hybrid LS-PWM and PS-PWM.

Figure 4 .

 4 Figure 4. Single-phase voltage-oriented control strategy for the proposed 5L-CTNPC converter.

Figure 5 .

 5 Figure 5. Stationary current control loop implemented with PMR controllers.

Figure 6 .

 6 Figure 6. Implemented voltage balancing control strategy per 3L-TNPC cell.

Figure 7 .

 7 Figure 7. Steady-state operation of the grid current PMR control.

Figure 8 .

 8 Figure 8. Steady-state operation of capacitor voltages for each power cell.

Figure 9 .

 9 Figure 9. Dynamic operation of DC-link and power on the DC-side under unbalanced power per string.

Figure 10 .

 10 Figure 10. Steady-state converter output voltage performance under unbalanced power per string.

  is included.

Figure 11 .

 11 Figure 11. Simplified diagram of implemented experimental setup.

Figure 12 .

 12 Figure 12. Steady-state experimental results at grid-side variables: Grid current and voltage waveforms.

Figure 13 .

 13 Figure 13. Steady-state experimental results at converter-side variables: Output voltage for each cell and total output voltage.

Figure 14 .

 14 Figure 14. Steady-state experimental results of capacitor voltage across each 3L-TNPC cell.

Figure 15 .

 15 Figure 15. Experimental dynamic operation of DC-link voltage under unbalanced power per string due to solar irradiation and temperature changes.

Figure 16 .

 16 Figure 16. Experimental dynamic operation of DC power under unbalanced power per string due to solar irradiation and temperature changes.

Figure 17 .

 17 Figure 17. Efficiency comparison between 5L-CTNPC, 5L-HTNPC and 5L-TNPC inverter topologies respect to the power operation.

Figure 18 .

 18 Figure 18. Grid current FFT comparison between 5L-CTNPC, 5L-HTNPC and 5L-TNPC inverter topologies.

Funding:

  The authors gratefully acknowledge the financial support provided by CONICYT REDES 170217, AC3E (CONICYT/BASAL/FB0008), SERC Chile (CONICYT/FONDAP/15110019), CONICYT + PAI CONVOCATORIA NACIONAL SUBVENCION A INSTALACION EN LA ACADEMIA CONVOCATORIA 2018 + PAI77180032.

Table 2 .

 2 Simulation and experimental parameters.

	DC voltage drift control
	, dcui v	PI	d m	c m
		, dcli v
		c v
	* dci , v	PI	c m
		, dci v	1
	Cell voltage control
	Symbol	Parameter	Simulation Value	Experimental Value
	Grid Parameters
	vˆs	Peak grid voltage	80 (V)	80 (V)
	fs	Grid frequency	50 (Hz)	50 (Hz)
	Converter Parameters
	Cdc	DC-link capacitors	1950 (µF)	1950 (µF)
	fcr	Carrier frequency	2000 (kHz)	2083 (kHz)
	Ls	Grid inductance	5 (mH)	5 (mH)
	Rs	Grid resistance	0.01 (Ω)	1 (Ω)

Table 3 .

 3 Brief comparison between five-level T-type topologies.

	Parameter	5L-CTNPC	5L-HTNPC	5L-TNPC
	DC-link voltage	vdc	vdc	vdc
	IGBT blocking voltage	4 × vdc, 4 × vdc/2	4 × vdc, 2 × vdc/2	4 × vdc, 4 × vdc/2
	IGBT switching freq.	8 × 2 (kHz)	4 × 2 (kHz), 2 × 50 (Hz)	8 × 2 [kHz]
	Apparent output voltage Ffreq.	4 (kHz)	2 (kHz)	4 [kHz]
	Grid current THD	2.83%	4.91%	2.53%
	Switching losses	0.087%	0.078%	0.087%

  following abbreviations are used in this manuscript:

	vpv,k			PV voltage per cell
	ipv,k			PV current per cell
	mck			Modulation reference signal per cell
	vcr1, vcr2		Carrier signals
	v * c			Per-unit converter voltage reference
	ek			Energy error per cell
	eT			Total error energy
	iˆs			Reference current magnitude
	ωs			Angular grid frequency
	θ			Grid angle
	fs			Grid frequency
	Gf		Notch filter
	∆vpv		MPPT voltage step
	Tk		MPPT time step
	is *		Current reference
	Ci(s)		Current controller
	kp		Proportional gain of the PMR controller
	kih		Integral gain of the PMR controller for each h-th frequency component
	AC h		Alternating Current Grid harmonic
	DC vL		Direct Current Inductor voltage
	PV v * L		Photovoltaic Inductor voltage reference
	NPC fcr		Neutral Point Clamped Carrier frequency
	MLI Ts		Multi Level Inverter Sampling period
	THD BWvdc DC-link control bandwidth Total Harmonic Distortion
	MV BWis		Medium-Voltage Current control bandwidth
	3L-NPC BWdv Balancing control bandwidth Three-Level Neutral Point Clamped
	3L-TNPC Pmp	Three-Level T-type Neutral Point Clamped Maximum power
	3L-NPP vmp	Three-Level Neutral Point Piloted Voltage at maximum power
	5L-TNPC voc	Five-Level T-type Neutral Point Clamped Open-circuit voltage
	5L-HTNPC imp Current at maximum power Five-Level Hybrid T-type Neutral Point Clamped
	CHB isc		Cascade H-Bridge Short-circuit current
	9L-TNPC ∆md	Nine-Level T-type Neutral Point Clamped Voltage drift modulation component
	5L-CTNPC ∆mc Cell voltage control Five-Level Cascade T-type Neutral Point Clamped
	IGBT Pck		Isolated Gate Bipolar Transistor Power per cell
	MOSFET		Metal Oxide Semiconductor Field Effect Transistor
	MPPT			Maximum Power Point Tracking
	PID			Potential-Induced Degradation
	PWM			Pulse Width Modulation
	LS-PWM		Level-Shifted Pulse Width Modulation
	PS-PWM	Phase-Shifted Pulse Width Modulation
	SVM			Space Vector Modulation
	PMR			Proportional Multiresonant
	P&O			Perturb and Observe
	PI			Proportional-Integral
	SOGI			Second Order Generalized Integrator
	SRF-PLL		Synchronous Reference Frame Phase Lock Loop
	Nomenclature
	The following variable nomenclature is used along figures and tables of this manuscript:
	vs			Grid voltage
	is			Grid current
	Ls			Filter inductor
	Rs			Filter resistor for modelling purposes
	vc			Total converter voltage
	vck			Converter voltage per cell
	Cdc			Capacitance per cell
	Sk1, Sk2		Switching signals per cell
	vdcu,k,	v dcl,k	Upper and lower capacitor voltages per cell
	vdc,k			DC-link voltage per cell
	vdck *			DC-link voltage reference per cell