Jaime W Zapata

Thierry A Meynard

Optimal Design of Inductors Based on Homothetic Shape and using Geometric Programming

The efficiency and power density of a converter are two major characteristics but they are antagonists so the designer has to find a tadeoff between them. This is generally formulated as a multi-objective optimization problem giving a pareto front, and it can be encoutered at the system level, at subsystem level or even at the component level. In general the formulation needs to be different at each level because optimization algorithms are not robust enough and cannot guarantee convergence on large scale problems. This paper proposes a design method for inductors, using a mathematical formalism known as Geometric Programming (GP) that gives strong guarantees of convergence whatever the size of the problem. The design model describes objective and constraint functions using monomials and posynomials to comply with GP rules and works with homothetic shapes. A first formulation using continuous parameters allows selecting the region of operation and provides a good estimate of attainable size and losses, then a second formulation shows how to truncate parameters that need to be discrete values to obtain feasible objects (integer number of turns, discrete core size,) and account for non linear permeability. An evaluation case is presented to test the performance of the proposed algorithm. Last, a finite element analysis is included to account for some non linearities such as fringing and proximity effects, and improve the design accuracy. Because of the GP formulation, it should be possible in future work to use such an inductor model for sub-system level optimization (for example 2nd or 4th order filter) and still guarantee convergence towards a global optimum.

I. INTRODUCTION

The inherent trade-off, between efficiency and power density, represents a challenge for the design of power electronics systems due to the multi-objective optimization problem [START_REF] Badstuebner | An optimized, 99phase-shift pwm dc-dc converter for data centers and telecom applications[END_REF]. Several works found in the literature focus the optimization mostly on analytic models of the power converter, then following with experimental or simulation verification [START_REF] Badstuebner | Sensitivity of telecom dc-dc converter optimization to the level of detail of the system model[END_REF], [START_REF] Kolar | Exploring the pareto front of multi-objective single-phase pfc rectifier design optimization -99.2efficiency vs. 7kw/din3power density[END_REF]. The performance of the optimization algorithm, the most computationally efficient way to tackle the problem and cost or the sub-problems to be optimized, are not deeply considered.

The magnetic components, such as inductors and transformers, are very significant part of the volume and weight of power electronic converters, and can also contribute to reduce the system efficiency [START_REF] Badstuebner | An optimized, 99phase-shift pwm dc-dc converter for data centers and telecom applications[END_REF]. Therefore, their design must be carefully addressed as a sub-optimization problem. Among the challenges to consider during the modeling of inductors are the accurate calculation of the core and winding losses, and of the value of the inductance (air-gap fringing effect and non linear permeability). In terms of design, added difficulty comes from the fact that some parameters cannot vary continuously (number of turns, core and conductor size, air-gap) so that once the mathematical optimum is found it is not so obvious to determine the best feasible design.

In the literature it is possible to find several methods for the optimization of the inductors, most of them focusing on analytic models, measurements and finite elements models [START_REF] Badstuebner | An optimized, 99phase-shift pwm dc-dc converter for data centers and telecom applications[END_REF], [START_REF] Morentin | Opencomp3d: An opensource framework dedicated to design in power electronics[END_REF], with fixed or variable geometry [START_REF] Sato | 3-d optimization of ferrite inductor considering hysteresis loss[END_REF], [START_REF] Stupar | Multi-objective optimization and comparison of multi-level dc-dc converters using convex optimization methods[END_REF]. Our aim here is to develop a method that is sufficiently fast to be later used at subsystem or system level with up to hundreds of variables, and still accurate enough to be a very good starting point of a component optimization process. As we will show here, the Geometric Programming (GP) [START_REF] Boyd | A tutorial on geometric programming[END_REF], has been identified as the appropriate optimization method to achieve both these goals because of the following properties: • Assembleability: Alike most optimization methods, several design models can be easily assembled (e.g. by adding the individual objective functions and grouping the individual constraint functions) to formulate a wider optimization problem. • Buildability: Unlike other optimization methods, higher-level problems resulting of the assembly of several lower-level GP-valid formulations inherit from the guarantees of convergence. It is therefore possible to develop and test design models at componentlevel, to include these models in subsystem or even system-level efficient design tools.

• Clear-sightedness: Unlike most optimization methods, GP gives guarantees finding the absolute minima, if any; therefore, it does not need initial guess, nor scaling. That indirectly guarantees reproducibility of results, requires less user inputs, and might find an optimum in an unexpected design region which is especially needed in large scale problems where human intuition might fail. These properties are obtained at the expense of strict rules to be obeyed when describing the problem, but the methods and tools to solve efficiently these problems are available in [START_REF]Ggplab: A simple matlab toolbox for geometric programming[END_REF]: • The validity of the formulation is checked before launching the optimization itself. If a rule is not obeyed, it is pointed out right from the start.

• Solvers for valid GP-form problems are fast and efficient, little knowledge is needed to use them.

II. GEOMETRIC PROGRAMMING

Geometric Programming (GP) is a mathematical optimization problem [START_REF] Boyd | A tutorial on geometric programming[END_REF]. It has the following form: minimize:

(1) subject to:

(2) where x = (x1,x2,...,xn) is a vector of the design positive variables, hj(x) are the GP-monomials constraints, the coefficients aj are positive coefficients, and the exponents kj are any real number. However, in this standard formulation the posynomials and monomials are not convex function [START_REF] Stupar | Posynomial models of inductors for optimization of power electronic systems by geometric programming[END_REF], and can be difficult to solve. However, translating them to the log domain makes them convex and easy to solve. Posynomial Functions:

log(h(x)) = log(ax k 1 1 ...x k n n ) (3) = log(a)+ k1log(x1)+ ... + knlog(xn)
After such a transformation, the function presents a linear and convex behavior, which guarantees the existence of only one global optimized point. In the next sections we will show that the multi-objective optimization of an inductor aiming at finding the trade-off between power losses and volume, can be quickly solved as long as the formulation is a GP-valid problem [START_REF] Stupar | Efficiency optimization of a 7-switch flying capacitor buck converter power stage ic using simulation and geometric programming[END_REF].

III. INDUCTOR DESIGN BASED ON HOMOTHETIC SHAPE

An homothetic shape, as shown in Fig. 1 (a) has the advantage of being a linear transformation, which preserves not only the colinearity of points but also the vector addition and scalar multiplication. It means that the distances between points are proportional by a factor λ, areas by λ 2 , volumes to λ 3 , etc...

Parameter

Rectangular Shape Toroidal Shape power P, which allows to scale the converter volume depending on the operating point. However, it is not easy to express all the core and winding parameters as function of the area product. Therefore, the approach of considering fixed shapes, with dimensions following an homothetic law, simplifies the modeling problem. This homothetic approach is mainly dedicated to standard magnetic cores (E, planar, ETD, toroidal, etc.). Even though the core dimension in a given family are not always homothetic, this approach allows finding the closest possible core.

A. Core Shape Specifications

In order to apply the methodology, the geometrical parameters must be expressed in terms of the area product. As a beginning step, three ratios are obtained to describe all the geometric parameters no matter the core geometry. A rectangular shape, as shown in Fig. [START_REF] Forest | Analytic design method based on homothetic shape of magnetic cores for high-frequency transformers[END_REF] , or a toroidal shape, as shown in Fig. 1 (c) [START_REF] Forest | Design and comparison of inductors and intercell transformers for filtering of pwm inverter output[END_REF].

aw = Lw/lw ac1 = Lc/lw (4) ac2 = lc/lw
where, Lw and lw are related to the winding distances, and Lc and lc with the core distances. These geometrical ratios allow defining the desired inductor characteristic in terms of the area product AwAc, but it is necessary to previously define some geometrical factors, for the rectangular and toroidal shape, as described in the Table I.

With these factors it is possible to express the inductor characteristic as follows:

• Core and winding areas:

Aw = Lwlw = awwc(AwAc)1/2 (5) Ac = Lclc = acwc(AwAc)1/2 •
Effective inductor volume:

V olE = (Y + Z/Kw)(AwAc) 3/4 Kw > 1
where, Kw represents a winding factor. [START_REF] Stupar | Multi-objective optimization and comparison of multi-level dc-dc converters using convex optimization methods[END_REF] • Total exchange surface: 1/2 ATH = S(AwAc)

• Allowed losses:

(7)

Pwc = ATHHΔT (8)
where, ΔT represents the thermal elevation above ambient temperature, and H is the thermal exchange coefficient.

As can be seen, the volume and thermal losses have been described in terms of the area product AwAc.

IV. OPTIMIZATION PROBLEM USING GP FORMULATION

The main rules governing the design of inductors are the following:

• A magnetic component stores energy through the interaction of a magnetic flux and a current (φ • I > Ltarget • I 2 ).

• The flux density cannot exceed a certain value (φ • Ac < Bsat).

• The current generates losses in the conductor, and the AC flux generates losses in the core; these losses must be dissipated through an exchange surface.

In order to address the optimization problem, the proposed procedure is presented in Fig. 2. At the beginning the user selects from a data base set, some standard parameters found in the commercial datasheets (e.g. the material of the core and winding, geometrical proportions based on the type of core, etc.). Then, the user defines the operating points under which the inductor will work (e.g. nominal power, input/output voltage, switching frequency, etc). After that, the program will calculate some operation parameters based on the user selections, with these parameters all the geometrical and electrical characteristics are defined.

At first instance, the geometric programming formulation is constructed defining the target variables to be optimized gpvar. The selected variables regard the construction limitations AwAc, inductance requirement jDC and core saturation Bdc. The advantage of the GP is that there is not a theoretical limitation on the number of variables to be optimized, as long as the GP formalism is respected. Besides, all the constraints are imposed in this step. Where all the maximum allowed values can be also defined as a function of the variables to optimize NRJ or, physical limitations of the material Bsat. For concluding the first GP formulation, the objective is defined. The GP does not limit the number of objectives to be optimized at same time, but in this work the objectives are evaluated independently and consecutively. This will be justified in the following sections.

V. EVALUATION CASE

As an evaluation case the selected core is: a EI -Planar type, with a magnetic material MagneticsMPP300, and conductor

Copper, for a Chopper application. Moreover, the design parameters are presented in the Table II.

A. GP Formulation in a Continuous Domain

At first instance, the GP formulation selects the area product as the optimization objective AwAc. Beside, the first assumption made is that rac/rdc = 1. It is made in order to know the volume/loss Pareto front under ideal conditions. The result depicted in Fig. 3 (a), allows the designer to chose a desired operating condition on this design space. This selected target can be made based on the technique for the thermal dissipation (liquid cooling, forced convection or natural convection). In this case, the selected point is: Htherm = 13W/ 0 C/m 2 , AwAc = 1.02623e 6 mm 4 , nTurns = 50.4397. However, as can be noted, the variables are continuous (e.g. nTurns), and it must to be an integer value in order to construct the inductor.

B. GP Formulation for Feasible Variables

1) Feasible Core Design: Once the algorithm generates the Pareto front for continuous variables, the designer will be able to find an existing core and an integer number of turns close to the prescribed solution. In the evaluation case, as depicted in Fig. 3 (b), the designer was able to chose an available core. In this case, the selected point is: Htherm = 13W/ 0 C/m 2 , AwAc = 1.12e 6 mm 4 , nTurns = 52.1402

It means that the geometry proportion AwAc, is not a variable anymore, but it is an imposed parameter to be set on the GP formulation as follows:

• gpvar: jDC, Bdc ( AwAc now imposed to AwAcDisc )

• constraints: Inductance requirement NRJreq ≤ NRJ(AwAcDisc) Avoid saturation Bmax≤Bsat(AwAcDisc) Respect thermal constraint totalLosses(AwAcDisc)≤ allowedLosses(AwAcDisc)

• objective: totalLosses(AwAcDisc)

2) Feasible Turns Ratio: After the optimization, the core is now slightly bigger than strictly required but it still has to truncate the turns ratio nTurns. There are different ways to do this:

• nTurnsDisc=floor(nTurns): It increases Bmax, the core losses and wire section. But it decreases dc winding losses.

• nTurnsDisc=ceil(nTurns): It decreases the core losses and wire section. But it increases dc winding losses.

It means that the turns ratio nTurns, is not a variable anymore, but it is an imposed parameter to be set on the GP formulation as similar to the explained above, with the difference that:

• gpvar: Bdc ( jDC is now imposed)

• constraints: Inductance requirement NRJreq ≤ NRJ(AwAcDisc, nTurnsDisc)

Avoid saturation Bmax≤Bsat(AwAcDisc, nTurnsDisc)

Respect thermal constraint totalLosses(AwAcDisc, nTurnsDisc)≤ allowedLosses(AwAcDisc)

• objective: totalLosses(AwAcDisc, nTurnsDisc)

In that evaluation, the selected operating points are depicted in Fig. 4. The are: Htherm = 13W/ 0 C/m 2 , AwAc = 1.12e 6 mm 4 , nTurns = 53. In case no acceptable design is found, the next bigger core must be selected.

C. Design using Finite Elements Analysis

The jDC/Bdc formulation does not involve the B(H) characteristic of the material; in this approach, the air gap is adjusted at the end of the design to obtain the appropriate induction level and inductance value. Therefore a non-linear B(H) characteristic can be easily taken into account since B and H are already known, as shown in Fig. 5 (a).

The air gap reluctance is found by subtracting the core reluctance (with μ(Bdc)) to the targeted total reluctance, as shown in Fig. 5

(b).

There are some motivations for using Finite Elements: • Relation from airgap to airgap reluctance is complex and involves details of the geometry (e.g. distance to the winding).

• AC losses are difficult to take into account (skin, proximity and air gap induced losses) and each formulation is geometry dependent.

Therefore, FEMM simulations are run to have a good estimate of rac/rdc and inductance L. The whole process is repeated until the correction coefficients become as close to 1 as specified. From the results, it was realized that 5% tolerance generally needs less than 4 iterations. Calculation time is around 1 minute, with roughly 99% for FEMM and 1% for GP formulation execution. The results of the FEMM analysis for the selected geometry, is depicted in Fig. 6 (a). In this figure it is possible to see the Flux Density B on the core.

Moreover, after 3 iterations, the results of the optimization process is depicted in Fig. 6 (b). In this figure, the desired operating points are highlighted, and from the results it is possible to see that for an inductor of 477.2cm 3 , a total power dissipation of 47.56W is achieved. The result assumes the designer will be able:

• To find an existing core and an integer number of turns close to the prescribed solution.

• To find the air gap that gives targeted L, accounting for fringing effect and for material non linearity.

• To find a winding topology (round/litz, horizontal/vertical foil,) that gives the assumed rAC/rDC.

VI. CONCLUSIONS

This work presents a methodology for the optimal design of inductors, based on the homothetic shapes. Due to this criteria of designing, it is possible to represent all the geometrical and electrical characteristics of the inductor in terms of the area product.

Besides, the geometrical programming formalism is used as a powerful tool for the multi-objective convex optimization. Giving as result a volume/loss Pareto front, which allows to the to select the available core and turns ratio close to the prescribed solution.

Moreover, other advantage of the geometric programming formalism, is that this design is extremely fast (< 20ms). And it can be used, to explore the design space (weight/losses pareto, iteration on materials or shapes, variation of frequency,), at system level to get good estimates of weight and losses of magnetic components (e.g. in a full conversion chain).

Fig. 1 .

 1 Fig. 1. (a) Homothetic Shape. (b) Charactersitics of a rectangular shape. (c) Charactersitics of a toroidal shape.

  Fig. 1 (b)

Fig. 3 .

 3 Fig. 3. (a) Volume/Losses Pareto Front, for continuous variables design. (b) Volume/Losses Pareto Front, selecting a feasible core design.

Fig. 6 .

 6 Fig. 6. (a) Flux density results using Finite Elements. (b) Optimization procedure of an inductor under user specifications.


Fellow, IEEE Thierry A Meynard

Sa Tiago

Guilherme Monteiro Ferreira

Lenin Rezende

Ferreira Martins

Victor Flores Morais

Didier Mendes

Jérémi Flumian

Regnier

Member, IEEE Tiago S Ferreira

Guilherme M Rezende

Member, IEEE Lenin M F Morais

Victor F Mendes

Didier Flumian

Member, IEEE Jérémi Regnier

Novel Multirate Modulator for High Bandwidth Multicell Converters

come

I. INTRODUCTION

n recent years, several topologies of converters have been reported in the literature to improve their performances, especially efficiency and power density. Among them, there are multilevel converters with some characteristic features [START_REF] Rodriguez | Multilevel Converters: An Enabling Technology for High-Power Applications[END_REF], [START_REF] Marquardt | Modular Multilevel Converters: State of the Art and Future Progress[END_REF]: 1) they include several commutation cells, which are the building blocks of the converters; 2) the two-level chopped voltage and/or current waveforms of the different cells are added in the circuit to form voltage and/or current waveforms with more levels; 3) the control pattern can be interleaved to optimize the output total waveform; 4) the filters take advantage of these improved waveforms; storing less energy, they can be smaller than those of classical twolevel converters. Such multilevel converters are employed in a myriad of applications such as HVDC transmission and distribution, energy storage systems and electric vehicles as well as in the naval and aerospace industries [START_REF] Rodriguez | Multilevel Converters: An Enabling Technology for High-Power Applications[END_REF], [START_REF] Kim | The High-Efficiency Isolated AC-DC Converter Using the Three-Phase Interleaved LLC Resonant Converter Employing the Y-Connected Rectifier[END_REF]- [START_REF] Nademi | Power Quality Characteristics of a Multilevel Current Source With Optimal Predictive Scheme From More-Electric-Aircraft Perspective[END_REF]. This wide range of end-uses imply in different requirements for each deployment of the technology. Thus, numerous converter configurations exist [START_REF] Kouro | Recent Advances and Industrial Applications of Multilevel Converters[END_REF]- [START_REF] Tardelli | Series Chain-Link Modular Multilevel AC-DC Converter (SCC) for HVDC Applications[END_REF], as the wellknown neutral point clamped (NPC) [START_REF] Nabae | A New Neutral-Point-Clamped PWM Inverter[END_REF], the flying capacitor (FC) [START_REF] Meynard | Multi-level conversion: high voltage choppers and voltage-source inverters[END_REF] and the cascaded H-bridge [START_REF] Peng | A multilevel voltage-source inverter with separate DC sources for static VAr generation[END_REF] topologies and others as the clamp-double [START_REF] Xue | Self-Start Control With Grouping Sequentially Precharge for the C-MMC-Based HVDC System[END_REF] and double-zero [START_REF] Dahmen | Analytical investigation of efficiency and operating range of different Modular Multilevel Converters[END_REF] converters, each with its particularities.

Furthermore, many applications of multilevel converters may demand or benefit from a faster transient response and a broader stability margin [START_REF] Niklaus | Ultra-High Bandwidth GaN-Based Class-D Power Amplifier for Testing of Three-Phase Mains Interfaces of Renewable Energy Systems[END_REF]. There are many techniques to achieve fast transient response depending on the application and converter topology. A fast control can be obtained, for example, with analog control without microcontrollers if the electronic circuits are designed to include all structures (converter and control system) [START_REF] Hsu | A Transient Enhancement DC-DC Buck Converter With Dual Operating Modes Control Technique[END_REF], [START_REF] Zhou | Multiloop Control for Fast Transient DC-DC Converter[END_REF]. This is better suited for simpler topologies such as buck converters or low power applications [START_REF] Wu | Full-Range Soft-Switching-Isolated Buck-Boost Converters With Integrated Interleaved Boost Converter and Phase-Shifted Control[END_REF].

In [START_REF] Katayama | Application of Multi-Level Converter for Fast Current Control in Small-Scale DC Power Network[END_REF] it is shown that, for the same perceived switched frequency, a multilevel converter can be faster and more stable than its two-level counterpart due to a reduced output filter. Another way to reach better transient response in the control of power converters is to use non-linear techniques instead of the classical linear approach, such as: predictive control [START_REF] Dragicevic | Model Predictive Control of Power Converters for Robust and Fast Operation of AC Microgrids[END_REF]- [START_REF] Defay | A Predictive Control With Flying Capacitor Balancing of a Multicell Active Power Filter[END_REF], geometric control [START_REF] Mohammadi | Fast Transient Response of Series Resonant Converters Using Average Geometric Control[END_REF], adaptive control [START_REF] Bellinaso | Cascade Control With Adaptive Voltage Controller Applied to Photovoltaic Boost Converters[END_REF], [START_REF] Eren | An Adaptive Droop DC-Bus Voltage Controller for a Grid-Connected Voltage Source Inverter With LCL Filter[END_REF], etc. These techniques however come at the expense of increased computational burden, which is still a limitation especially for high frequency applications. Therefore, classical controls are still widely used since they are simple and easy to implement.

Other important aspect of control systems in multilevel converters is the use of distributed control. In applications with high number of switches, the distributed structure is usually adopted due to the impossibility to control all converters cells using a single processor. Thus, a multirate sampling approach is beneficial to implement all control strategies [START_REF] Huang | A new method to implement resampled uniform PWM suitable for distributed control of modular multilevel converters[END_REF]- [START_REF] Yang | Carrier-Based Digital PWM and Multirate Technique of a Cascaded H-Bridge Converter for Power Electronic Traction Transformers[END_REF].

Another important subject related to dynamics in multilevel converters is the modulation technique, since decreasing the modulator delay is one way to enhance the control performance [START_REF] Yang | Carrier-Based Digital PWM and Multirate Technique of a Cascaded H-Bridge Converter for Power Electronic Traction Transformers[END_REF], [START_REF] Zhang | Study of Multisampled Multilevel Inverters to Improve Control Performance[END_REF]. Two classical carrier-based modulation techniques are the Symmetrically Sampled PWM (SS-PWM) and the Asymmetrically Sampled PWM (AS-PWM). These are based in sampling the control quantities and updating the duty cycle of each individual cell in specific moments of the carrier wave. This is done once per cycle for the SS-PWM and twice per cycle for the AS-PWM. However, this sampling and updating limitation deteriorates modulator performance [START_REF] Yang | Carrier-Based Digital PWM and Multirate Technique of a Cascaded H-Bridge Converter for Power Electronic Traction Transformers[END_REF]- [START_REF] Walker | Bandwidth considerations for multilevel converters[END_REF].

To prevent this, the Naturally Sampled PWM (NS-PWM) can be used [START_REF] Walker | Digitally-implemented naturally sampled PWM suitable for multilevel converter control[END_REF]. This modulator updates the duty cycles of all cells at the same time whenever sampling occurs. Moreover, it is shown in [START_REF] Yang | Carrier-Based Digital PWM and Multirate Technique of a Cascaded H-Bridge Converter for Power Electronic Traction Transformers[END_REF] that this modulator is suitable for decentralized control structures, since using it allows the separation of switching, sampling and control frequencies, minimizing control and sampling time and allowing for an overall better control performance in low frequency multilevel converters. I Nevertheless, overswitching (multiple switching pulses per carrier cycle) may incur while using the NS-PWM since each cell can change its duty cycle at any moment. These extra pulses must be avoided since they generate extra losses and EMI problems. Although there are ways to eliminate this via hardware, the Multirate Symmetrically Sampled and Multirate Asymmetrically Sampled modulators (which will be referred to as MSS-PWM and MAS-PWM, respectively) proposed in this paper present a software implemented solution that select which cell can change its state without provoking overswitching. This novel multirate modulator is not dependent of the control strategy nor the multicell converter configuration, i.e., it is generalized for any number of cells in series and/or in parallel. This paper will focus on multicell series and parallel converters for three reasons: 1) they can be used to build DC/DC or DC/AC (as depicted in Fig. 1(a) and Fig. 1(b) and, respectively) converters with any number of cells; 2) they can be combined to form series-parallel converters (in Fig. 1(a), 𝑆 𝐻𝑖 and 𝑆 𝐿𝑖 form cell 𝐼, with 𝑖 = 1, ⋯ ,6; cells 1 to 3 form a series three-cell inverter leg and cells 1 to 6 form a 3x2 series-parallel multicell inverter leg); 3) they are convenient to illustrate how some principles are common to series and parallel types and also to point out some differences. The aim of this paper is to better understand the dynamic performance of series and parallel multicell converters by identifying their physical limits, showing how they can be maximized and comparing results obtained with different numbers of cells. In order to ensure fair comparison between the converters, three rules discussed along the text are followed:

1) no overswitching is allowed (a switching cell must never undergo more than one ON-OFF in a switching period); 2) the output filters of converters with different numbers of cells are designed according to the same criteria, since the filter values obviously affect dynamic performances; 3) the control is adjusted in such way that the fastest response is reached without control saturation. The two main contributions of this paper are:

1) firstly and mainly, the introduction of a multirate modulation strategy that allows fast duty cycles changes while avoiding overswitching via software and that is more resilient to filter parameter deviation;

2) secondly, a better understanding of the influence of the number and configuration of cells in the filter design and control dynamic behavior. The superior performance of the proposed multirate method is demonstrated in simulations using the PLECS platform, and the impact of the number of cells on the system response is evaluated for parallel converters. The results are validated using an experimental prototype of a DC/DC three-cell converter.

The paper is organized as follows: Section II describes the filter design principles for series and parallel converters, Section III draws the physical performance limit of such converters, Section IV presents the control strategy employed, Section V describe the classical modulation and the proposed method, Section VI shows the simulation and experimental results, and finally in Section VII the conclusions are presented.

II. FILTER DESIGN FOR MULTICELL CONVERTERS

Filter design is not an easy task and it is not the main aim of this paper, so the development carried out here will be kept as simple as possible. Still, it is necessary to identify simple design rules and always apply them in such way that direct comparison can be done to identify the inherent differences of using different numbers of cells in series and/or in parallel.

Firstly, equations that govern the inductor current ripple and the capacitor voltage ripple in DC-DC converter structures as the one in Fig. 1(a) are derived, then it is discussed how these ripples influences the design of the filter. Finally, it is shown how the filter obeying chosen rules evolves with the number of cells in series and in parallel.

A. Inductor Current Ripple

The voltage delivered at the output of a series (𝑠) multicell converter with 𝑛 𝑠 cells in series and interleaved control (control patterns of the different cells identical but phase-shifted by 2𝜋/𝑛 𝑠 ) is a square voltage waveform with an amplitude 𝑉 𝐻𝑉 /𝑛 𝑠 and an apparent frequency 𝑛 𝑠 • 𝑓 𝑆𝑤 (where 𝑓 𝑆𝑤 is the switching frequency). In consequence, the inductor current ripple is given by [START_REF] Meynard | Analysis and design of multicell DC/DC converters using vectorized models[END_REF] ∆𝐼 𝑝𝑘𝑝𝑘 = 𝑉 𝐻𝑉 /(4

• 𝐿 𝑓 • 𝑓 𝑆𝑤 • 𝑛 𝑠 2 ), (1)
where ∆𝐼 𝑝𝑘𝑝𝑘 is the current ripple peak-to-peak value, 𝑉 𝐻𝑉 is the voltage in the high voltage side of the converter (input) and 𝐿 𝑓 is the equivalent filter inductor (low voltage side).

In a parallel (𝑝) multicell converter with 𝑛 𝑝 cells in parallel, each inductor sees only a fraction of the current, but the voltage applied is the same as for a two-level converter. To maintain the normalized ripple in each 𝐿 𝐿𝑉 inductor (∆𝐼 𝑝𝑘𝑝𝑘 𝑐𝑒𝑙𝑙_𝑁 ), it is needed

∆𝐼 𝑝𝑘𝑝𝑘 𝑐𝑒𝑙𝑙_𝑁 (𝐼 𝐿𝑉 /𝑛 𝑝 ) = 𝑉 𝐻𝑉 /(4 • 𝐿 𝐿𝑉 • 𝑓 𝑆𝑤 ), (2)
where 𝐿 𝐿𝑉 is the cell filter inductor. Using an interleaved modulation, the current ripple will be partially compensated [START_REF] Laboure | A Theoretical Approach to InterCell Transformers, Application to Interleaved Converters[END_REF], resulting in a ripple of the total current divided by np

∆𝐼 𝑝𝑘𝑝𝑘 𝑡𝑜𝑡𝑎𝑙 = ∆𝐼 𝑝𝑘𝑝𝑘 𝑐𝑒𝑙𝑙_𝑁 (𝐼 𝐿𝑉 /𝑛 𝑝 )/𝑛 𝑝 = 𝑉 𝐻𝑉 /(4 • 𝐿 𝐿𝑉 • 𝑓 𝑆𝑤 )/𝑛 𝑝 , (3)
which can be rewritten as

∆𝐼 𝑝𝑘𝑝𝑘 𝑡𝑜𝑡𝑎𝑙 = 𝑉 𝐻𝑉 /[4 • (𝐿 𝐿𝑉 /𝑛 𝑝 ) • 𝑓 𝑆𝑤 • 𝑛 𝑝 2 ], (4)
where 𝐿 𝐿𝑉 /𝑛 𝑝 is the inductance equivalent to the cell inductances in parallel. Comparing Eq. 1 and Eq. 4, it is seen that the total current ripple of the series and parallel multicell converters can be described with a unified equation involving the equivalent output inductance and the total number of cells, no matter if they are in series, parallel or even in series-parallel

∆𝐼 𝑝𝑘𝑝𝑘 𝑡𝑜𝑡𝑎𝑙 = 𝑉 𝐻𝑉 /(4 • 𝐿 𝑓 • 𝑓 𝑆𝑤 • 𝑛 𝑐𝑒𝑙𝑙 2 ), (5)
𝐿 𝑓 = 𝐿 𝐿𝑉 /𝑛 𝑝 , (6)
𝑛 𝑐𝑒𝑙𝑙 = 𝑛 𝑠 • 𝑛 𝑝 . (7)

B. Capacitor Voltage Ripple

The inductor ripple current is assumed to flow into the capacitor and it provokes the voltage ripple. Keeping in mind that the frequency of the current ripple in the series, the parallel and the series-parallel multicell converter is always 𝑛 𝑐𝑒𝑙𝑙 . 𝑓 𝑆𝑤 when the control signals are appropriately interleaved, for all three cases the voltage ripple is [START_REF] Meynard | Analysis and design of multicell DC/DC converters using vectorized models[END_REF] ∆𝑉 𝑝𝑘𝑝𝑘 = ∆𝐼 𝑝𝑘𝑝𝑘 𝑡𝑜𝑡𝑎𝑙 / (8

• 𝐶 𝐿𝑉 • 𝑛 𝑐𝑒𝑙𝑙 • 𝑓 𝑆𝑤 ), (8)
where 𝐶 𝐿𝑉 is the filter capacitor.

C. Filter Design

The inductor of a 2 nd order low voltage side filter is generally bigger and more expensive than the capacitor and it also generates more losses. All these reasons push the designer to try to minimize the inductor size and this process may result of various complicated tradeoffs. However, as a first approach, it can be considered that 𝐿 • 𝐼 𝑝𝑘 • 𝐼 𝑟𝑚𝑠 is an acceptable indication of the size of the inductor [START_REF] Kazimierczuk | Design of AC resonant inductors using area product method[END_REF], [START_REF] Nijende | Optimized size design of integrated magnetic components using area product approach[END_REF]. Very high inductance values result in almost no ripple, but also very big inductors (high energy, 𝐿 • 𝐼 𝑑𝑐 2 ). However, very low inductance values would also result in very big inductors, because of high peak and RMS currents. This means that, in practice, the filter inductors are neither chosen based on filtering criteria nor on dynamic performances; their value is chosen to try to minimize their weight, cost and/or losses. A first rule of thumb is to choose the maximum normalized current ripple ∆𝐼 𝑝𝑘𝑝𝑘 𝑁 and, for the case of a series-parallel converter, through Eq. 5 yields

𝐿 𝐿𝑉 = 𝑉 𝐻𝑉 /(4 • ∆𝐼 𝑝𝑘𝑝𝑘 𝑁 • 𝐼 𝐿𝑉 /𝑛 𝑝 • 𝑓 𝑆𝑤 )/𝑛 𝑠 2 , (9)
which combined to Eq. 6, 7 and 8 gives

𝐶 𝐿𝑉 = ( 𝐼 𝐿𝑉 𝑉 𝐻𝑉 ) • (∆𝐼 𝑝𝑘𝑝𝑘 𝑁 /∆𝑉 𝑝𝑘𝑝𝑘 𝑁 )/(8 • 𝑓 𝑆𝑤 • 𝑛 𝑠 • 𝑛 𝑝 3 ), (10)
where ∆𝑉 𝑝𝑘𝑝𝑘 𝑁 is the normalized voltage ripple. In this work, these equations are used to design the filters and impose current and voltage ripples of ∆𝐼 𝑝𝑘𝑝𝑘 𝑁 = 30% and ∆𝑉 𝑝𝑘𝑝𝑘 𝑁 = 0.5%. Notably, the constraint in the parallel converter is the current ripple in each leg (cell). Designing the maximum ripple in the cell, the output current ripple will be smaller, and the capacitor will be designed for this ripple. For the series converter, the constraint is directly the output current ripple thus the capacitor will be bigger to keep the maximum voltage ripple.

D. Filter Calculation with the Number of Cells

By these rules, filters for multicell converters are easily designed, and the similarities/differences of series/parallel converters can be better understood. Table I gives the 2 nd order filter characteristic values for both topologies using the value of ripple previously mentioned, and considering a converter input voltage 𝑉 𝐻𝑉 = 100𝑉, maximum output current 𝐼 𝐿𝑉 = 20𝐴 and switching frequency 𝑓 𝑆𝑤 = 20kHz. These parameters are used throughout this work for simulation and experimental results.

III. DYNAMIC PERFORMANCES AND PHYSICAL LIMITS FOR MULTICELL CONVERTERS

The general trend is that increasing the number of cells allows increasing the cutoff frequency of the filter, so it must be possible to increase the dynamic performances. Before getting into more details about the control strategy that respects all the requirements of a feasible power converter with as fast as possible time response, a study of the physical limits of large-scale response time resulting of the fixed DC voltage is first developed. This limit is in fact relative and it will be used later to compare with the result of the proposed modulation strategy.

State plane analysis is a convenient tool to study the evolution of second order filters, and it will be first analyzed the simplest case, i.e., a step of the reference from 0% to 100% without any load. It is easy to understand that the voltage to be applied for fastest response is 100% for a first time interval 𝑇 1 , to deliver as much energy as possible to the filter, then 0% for second time interval 𝑇 2 , to avoid voltage overshoot and allow current to reach zero at the time that the voltage reaches 100%; at this time the applied voltage must become 100% again to maintain the output voltage at the targeted value.

This process requires perfect timing, but in this specific undamped case, the trajectories are perfect circles and, since the angles in the state plane translate to fractions of the natural frequency, it can be seen from Fig. 2 that the minimal time response is 1/3 of the natural frequency. This principle can be generalized to a more realistic case, i.e., a loaded converter. The centers of the circles are now along a line with a slope imposed by the value of the load, and the trajectories are now logarithmic spirals that makes analytic calculation much more difficult (see Fig. 3).

It is however possible to find numerically the values of 𝑇 1 and 𝑇 2 corresponding to this case, using the following process: 1) write the model equations as functions of applied voltage, filter parameters and load;

2) impose initial conditions of point 𝐴 and find first trajectory with full applied voltage;

3) impose final conditions of point 𝐵 and find second trajectory by reverse simulation with zero applied voltage (reverse means a negative step at each iteration); 4) find intersection of the two trajectories, times 𝑇 1 and 𝑇 2 . Using this method and considering the previously calculated filter parameters, Table II presents the optimal time responses as a function of the switching period (𝑡 𝑠𝑊 ) of the loaded series and parallel converters for 𝑟 𝐿𝑜𝑎𝑑 = 5 Ω (rated load resistance). It is seen that the response varies with the number of cells and with the series and parallel structures.

The simulation results for a parallel converter as the one from Fig. 4 with 𝑛 𝑐𝑒𝑙𝑙 = 3 and 𝑟 𝐿𝑜𝑎𝑑 = 5 Ω are shown in Fig. 5. From Fig. 5, the response time is 1.55 • 𝑡 𝑠𝑊 = 77.54µs for a voltage output step on the loaded converter, value that is in close agreement with the one shown in Table II. Despite giving the "optimal response", calculating 𝑇 1 and 𝑇 2 is not trivial and, thus, it is hard to implement in a microprocessor for the control of multicell converters.

These trajectories and minimum response times are ideal optima that do not respect most limitations of practical setups (i. e. they represent theoretical physical limits). These will be used as comparison references, since they cannot be achieved by practical converters with sampling, delays, etc.

IV. CLOSED LOOP CONTROL OF OUTPUT VOLTAGE IN MULTICELL CONVERTERS

A. Inductor Current Ripple

As demonstrated previously, an appropriate filter design allows taking advantage of the multicell topologies to reduce the output filter size. In the same way, increasing the number of cells favor higher filter cutoff frequencies, implying that faster dynamics could be expected. In contrast, seeking high bandwidth for the output voltage requires a system modeling with focus on specific points related to the control performances, including the modulator.

The equivalent filter model on Fig. 6 can be used for modeling the filter in series or parallel multicell converters. The output voltage 𝑉 𝑂𝑈𝑇 depends on the filter parameters and on the common mode voltage 𝑉 𝐶𝑀 provided by the converter. The filter includes the equivalent inductor 𝐿 𝑓 (and its equivalent winding resistance 𝑟 𝐿 𝑓 ), the capacitor 𝐶 𝐿𝑉 and the load 𝑟 𝐿𝑜𝑎𝑑 .

Whatever the converter topology, 𝑉 𝐶𝑀 (𝑡) could be expressed as a composition of the single cell voltage contributions

𝑉 𝐶𝑀 (𝑡) = 𝑉 𝐻𝑉 𝑛 𝑐𝑒𝑙𝑙 ∑ 𝛼 𝑐𝑒𝑙𝑙 𝑖 (𝑡) 𝑛 𝑐𝑒𝑙𝑙 𝑖 , (11)
with 𝛼 𝑐𝑒𝑙𝑙 𝑖 (𝑡) the instantaneous cell duty cycle of the 𝑖 𝑡ℎ cell. To be suitable for the control design, Eq. 11 must be transformed into its mean value formulation. The mean value 𝑉 𝐶𝑀 of the converter voltage is written with Eq. 12 by introducing an equivalent mean common mode duty cycle 𝛼 𝐶𝑀 .

𝑉 𝐶𝑀 = 𝑉 𝐻𝑉 𝑛 𝑐𝑒𝑙𝑙 ∑ 𝛼 𝑐𝑒𝑙𝑙 𝑖 (𝑡) 𝑛 𝑐𝑒𝑙𝑙 𝑖 = 𝑉 𝐻𝑉 • 𝛼 𝐶𝑀 (12)
Using the previous formulation, a generalized state space system of the converter-filter can be established:

[ 𝐼 𝐿 V𝑂𝑈𝑇 ̇] = [ - 𝑟 𝐿 𝑓 𝐿 𝑓 - 1 𝐿 𝑓 1 𝐶 𝐿𝑉 1 𝑟 𝑙𝑜𝑎𝑑 𝐶 𝐿𝑉 ] [ 𝐼 𝐿 𝑉 𝑂𝑈𝑇 ] + [ 𝑉 𝐻𝑉 𝐿 𝑓 0 ] 𝛼 𝐶𝑀 . (13)

B. Closed loop control of the output voltage

To be suitable for a closed loop control, the state space model in Eq. 13 must be discretized at the sampling time 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 [START_REF] Franklin | Digital control of dynamic systems[END_REF]. In a classical approach, the closed loop operation can be performed using discrete state space feedback with an integral action as in Fig. 7. A pole placement design allows calculating the feedback gains by choosing the desired closed loop performances required to generate the duty cycle 𝛼 𝐶𝑀𝑘 [START_REF] Kuo | Automatic control systems[END_REF]

𝛼 𝐶𝑀 𝑘 = -[𝐾 𝐿 𝐾 𝑓 ] [ 𝐼 𝐿 𝑘 𝑉 𝑂𝑈𝑇 𝑘 ] -𝐾 𝑖 ∫(𝑉 𝑟𝑒𝑓 𝑘 -𝑉 𝑂𝑈𝑇 𝑘 ), (14)
where 𝛼 𝐶𝑀 𝑘 is the mean duty cycle in the discretized 𝑘 instant and 𝐾 𝐿 , 𝐾 𝑓 , 𝐾 𝑖 are the gains of the state space feedback control. The poles' frequencies are chosen according to the desired time of first peak during the system's step response. This time value is chosen as the minimum peak time in a 10% to 90% voltage step without duty cycle saturation. The peak time is selected using an iterative simulation which changes this set of gains to achieve the best time response with these restrictions. For the same control restrictions, improving the modulator yields better gains and better overall performance. Thus, Section V details the proposed multirate modulator and Section VI shows its superior performance when compared to the classical ones.

V. MODULATION IN HIGH BANDWIDTH CONTROL OF MULTICELL CONVERTERS

A. Classical Modulator

The final objective of the control strategy is to generate the appropriated cell duty cycles 𝛼 𝑐𝑒𝑙𝑙 𝑖 (𝑡) from 𝛼 𝐶𝑀 𝑘 . To generate these duty cycles, a PWM strategy is commonly implemented.

In the classical SS-PWM and AS-PWM, the discrete duty cycle 𝛼 𝐶𝑀 𝑘 is compared to 𝑛 𝑐𝑒𝑙𝑙 triangular carrier signals with a phase shift of 2𝜋/𝑛 𝑐𝑒𝑙𝑙 [START_REF] Meynard | Parallel multicell converters for high current: Design of intercell transformers[END_REF]. To get the mean value of the common current and to avoid overswitching, 𝛼 𝐶𝑀 𝑘 is updated on specific events related to the minimum or/and maximum values of the carrier signals. The duty cycle is then sampled with a period of 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 = 𝑡 𝑠𝑊 /𝑛 𝑐𝑒𝑙𝑙 /𝑠 𝑟𝑎𝑡𝑒 , with the sampling rate 𝑠 𝑟𝑎𝑡𝑒 = 1 for symmetrical and 𝑠 𝑟𝑎𝑡𝑒 = 2 for asymmetrical samplings. An example is shown on Fig. 8 for 𝑛 𝑐𝑒𝑙𝑙 = 3 and an update related to the minimum value of each carrier (SS-PWM).

When a change occurs on the duty cycle command 𝛼 𝐶𝑀 𝑘 , each cell duty cycle 𝛼 𝑐𝑒𝑙𝑙 𝑖 is transformed through a sampling process with a cascaded delay, as depicted in Fig. 8. The real resulting duty cycle 𝛼 𝐶𝑀_𝐸𝑄 𝑘 is then different from the required 𝛼 𝐶𝑀 𝑘 in the middle of the period, and the real mean output voltage 𝑉 𝐶𝑀 is not rigorously equal to 𝑉 𝐻𝑉 • 𝛼 𝐶𝑀 . This implies that the state space model of Eq. 13 using 𝛼 𝐶𝑀 is not strictly representative of the real behavior of the whole controlled system. The same observations can be done if the duty cycle 𝛼 𝐶𝑀 𝑘 is updated both on minimum and on maximum of the carrier signal (AS-PWM).

This sampling process strongly penalizes the control performances. Often omitted for slow bandwidth control by assuming that the duty cycle sampling process is perfect (𝛼 𝐶𝑀_𝐸𝑄 𝑘 = 𝛼 𝐶𝑀 𝑘 ), it will be shown in the following that this behavior matters when high bandwidth control is requested.

B. Proposed Multirate Modulator

To reduce the influence of the sampling process on the output voltage control, a novel strategy is proposed to improve the generation of the cell duty cycles. The goal of such approach is to allow changes in all cell's duty cycles for each event on the carrier signals, not only for the event related to a specific cell. For this purpose, the mean voltage provided by the converter is studied over a subcycle period defined by 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 .

Table III defines the notations used in this paper.

Depending on the number of cells and the sampling rate, a time window with duration 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 starting from the sampling event is used to extract the shape of the carrier signals. As an example, Fig. 9(a) depicts the shape of the carrier signals in a subcycle for a three-cell converter in which the duty cycle update occurs only when the carrier passes through a minimum. At each instant 𝑡 𝑘 , regardless of which one is the active cell, the contribution of each cell to the global mean output voltage is defined for a three-cell converter as

𝑉 𝑂𝑈𝑇 𝑡 𝑘 = (𝑉 𝑐𝑒𝑙𝑙 𝑘 𝑡 𝑘 + 𝑉 𝑐𝑒𝑙𝑙 𝑘-1 𝑡 𝑘 + 𝑉 𝑐𝑒𝑙𝑙 𝑘-2 𝑡 𝑘 ) 3 ⁄ . ( 15
)
The comparison of the carrier signal with each duty cycle cell allows computing the mean voltage value of each of these cells over 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 . Hence, from Fig. 9(b), the mean voltage of each cell during one sample period is not a linear function of the cell duty cycle as to a classical two-level converter.

This observation is a main point of the proposed approach. Usually neglected, this non-linearity constitutes a key point to improve the ability of the converter to provide a required voltage. With this, the objective is to find, at each 𝑡 𝑘 , the duty cycles [𝛼 𝑘 𝑡 𝑘 , 𝛼 𝑘-1 𝑡 𝑘 , 𝛼 𝑘-2 𝑡 𝑘 ] to apply during the next period 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 to guarantee, if possible, the required output voltage 𝑉 𝑂𝑈𝑇 𝑡 𝑘 . While knowing that every cell can change its state twice (at any time, once for the positive carrier slope and once for the negative), the first task is to verify which cell has already switched during its own PWM cycle. With this, considering that the converter mean voltage output is given by Eq. 15, it is possible to calculate using Eq. 16 the required voltage (𝑉 𝑜 ) to be synthesized by the cells that are still able to switch. Since overswitching is not allowed, the state of the cells that already switched cannot be changed and their contributions (𝑉 𝑘 𝑠𝑤𝑖𝑡𝑐ℎ𝑒𝑑 ) to the desired converter output voltage 𝑉 𝑂𝑈𝑇 𝑡 𝑘 is already defined.

𝑉 𝑂𝑈𝑇 𝑡 𝑘 = 1 𝑛 𝑐𝑒𝑙𝑙 • (𝑉 𝑜 + ∑ 𝑉 𝑘 𝑠𝑤𝑖𝑡𝑐ℎ𝑒𝑑 ) (16)
Thus, an additional "watchdog" must be included to avoid the overswitching. For this purpose, it is defined new variables 𝑒𝑛 𝑘-1 and 𝑒𝑛 𝑘-2 respecting the rules presented in Table IV. With these rules, four different cases can be distinguished:

1) Case 0: if [𝑒𝑛 𝑘-1 , 𝑒𝑛 𝑘-2 ] = [0,0], 𝑐𝑒𝑙𝑙 𝑘-1 and 𝑐𝑒𝑙𝑙 𝑘-2 already switched. Only 𝛼 𝑘 𝑡𝑘 is free to be chosen as

𝛼 𝑘 𝑡𝑘 = 2 • 𝑉 𝑡 𝑘 𝑂𝑈𝑇 - 2 3 (𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘-1 + 𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘-2 ). (17)
2) Case 1: if [𝑒𝑛 𝑘-1 , 𝑒𝑛 𝑘-2 ] = [0,1], 𝑐𝑒𝑙𝑙 𝑘-1 already switched. 𝛼 𝑘 𝑡𝑘 and 𝛼 𝑘-2 𝑡𝑘 are free to be chosen as

𝛼 𝑘 𝑡𝑘 = 𝛼 𝑘-2 𝑡𝑘 = 𝑉 𝑡 𝑘 𝑂𝑈𝑇 - 1 3 𝑉 𝑡 𝑘-1 𝑐𝑒𝑙𝑙 𝑘-1 . (18)
3) Case 2: if [𝑒𝑛 𝑘-1 , 𝑒𝑛 𝑘-2 ] = [1,0], 𝑐𝑒𝑙𝑙 𝑘-2 already switched 𝛼 𝑘 𝑡𝑘 and 𝛼 𝑘-1 𝑡𝑘 are free to be chosen as

𝛼 𝑘 𝑡𝑘 = 𝛼 𝑘-1 𝑡𝑘 = 2 • 𝑉 𝑡 𝑘 𝑂𝑈𝑇 - 2 3 𝑉 𝑡 𝑘-1 𝑐𝑒𝑙𝑙 𝑘-2 , (19)
for 𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘 + 𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘-1 < 1, and

𝛼 𝑘 𝑡𝑘 = 𝛼 𝑘-1 𝑡𝑘 = 𝑉 𝑡 𝑘 𝑂𝑈𝑇 - 1 3 𝑉 𝑡 𝑘-1 𝑐𝑒𝑙𝑙 𝑘-2 + 1 3 , (20)
for 𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘 + 𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘-1 > 1.

4) Case 3: if [𝑒𝑛 𝑘-1 , 𝑒𝑛 𝑘-2 ] = [1,1], 𝛼 𝑘

𝑡𝑘 , 𝛼 𝑘-1 𝑡𝑘 and 𝛼 𝑘-2 𝑡𝑘 are free to be chosen. An infinity of solutions is possible under respect of Eq. 16. It can be chosen for example as

𝛼 𝑘 𝑡𝑘 = 𝛼 𝑘-1 𝑡𝑘 = 𝛼 𝑘-2 𝑡𝑘 = 𝑉 𝑡 𝑘 𝑂𝑈𝑇 , (21)
where [𝛼 1 𝑡𝑘 , 𝛼 2 𝑡𝑘 , 𝛼 3 𝑡𝑘 ] can finally be defined by arranging the duty cycles [𝛼 𝑘 𝑡𝑘 , 𝛼 𝑘-1 𝑡𝑘 , 𝛼 𝑘-2 𝑡𝑘 ] by choosing the index 𝑘 equal to the cell from which the carrier signal event comes from (1, 2 or 3). This is summarized in Table V, where "𝑝𝑜𝑠" corresponds to the cell number related to the considered carrier signal event.

For the sake of simplicity and easier understanding, the proposed approach is detailed for a three-cell parallel converter and symmetrical sampling. It must be underlined that one advantage of the proposed strategy is to be extendable to whatever the number of cells and the sampling rate by building a generic algorithm parametrized by 𝑛 𝑐𝑒𝑙𝑙 and the sampling rate 𝑠 𝑟𝑎𝑡𝑒 . Furthermore, since the output voltage expression is the same for parallel and series topologies, such proposed multirate strategy is suitable for any of these converter topologies. From a practical point of view, the proposed strategy is implemented in C-language to be suitable for real-time running. If 𝛼 𝑘-1 𝑡 𝑘-1 > 2/3, the cell 𝑐𝑒𝑙𝑙 𝑘-1 has not switched during the last increasing phase of the carrier signal: 𝑒𝑛 𝑘-1 = 1 (change allowed on the duty cycle).

𝑒𝑛 𝑘-2

If 𝛼 𝑘-2 𝑡 𝑘-1 < 2/3, the cell 𝑐𝑒𝑙𝑙 𝑘-2 has not switched during the last decreasing phase of the carrier signal: 𝑒𝑛 𝑘-2 = 1 (change allowed on the duty cycle).

If 𝛼 𝑘-2 𝑡 𝑘-1 > 2/3, the cell 𝑐𝑒𝑙𝑙 𝑘-2 has already switched during the last decreasing phase of the carrier signal: 𝑒𝑛 𝑘-2 = 0 (no change allowed on the duty cycle).

TABLE V MULTIRATE ALGORITHM RULES TO AVOID OVER-SWITCHING

Step 1 -Determination of

[𝛼 𝑘-1 𝑡 𝑘-1 , 𝛼 𝑘-2 𝑡 𝑘-1 ] = 𝑓(𝑝𝑜𝑠, 𝛼 1 𝑡 𝑘-1 , 𝛼 3 𝑡 𝑘-1 , 𝛼 2 𝑡 𝑘-1 )
Step 2 -Determination of

[𝑒𝑛 𝑘-1 , 𝑒𝑛 𝑘-2 ]= 𝑓(𝑝𝑜𝑠, 𝛼 𝑘-1 𝑡 𝑘-1 , 𝛼 𝑘-2 𝑡 𝑘-1 )
Step 3 -Determination of

[𝑉 𝑐𝑒𝑙𝑙 𝑘-1 𝑡 𝑘-1 , 𝑉 𝑐𝑒𝑙𝑙 𝑘-2 𝑡 𝑘-1 ]=f (𝛼 𝑘-1 𝑡 𝑘-1 , 𝛼 𝑘-2 𝑡 𝑘-1 )
Step 4 -Determination of

[𝛼 𝑘 𝑡𝑘 , 𝛼 𝑘-1 𝑡𝑘 , 𝛼 𝑘-2 𝑡𝑘 ]=f (𝑉 𝑐𝑒𝑙𝑙 𝑘-𝑖 𝑡 𝑘-1 , 𝑉 𝑂𝑈𝑇 𝑡 𝑘 , 𝑒𝑛 𝑘-1 , 𝑒𝑛 𝑘-2 )
Step 5 -Determination of [𝛼

𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘-1 𝛼 𝑘-1 𝑡𝑘 1 0 𝛼 𝑘-2 𝑡𝑘 2 3 ⁄ 1 2 3 ⁄ 1 1 3 ⁄ 2 3 ⁄ 1 1 3 ⁄ 𝑉 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘-2 1 3 ⁄

A. Considerations

The goal of this study is to determine the fastest response obtainable in closed loop operations using the classical SS-PWM and AS-PWM and comparing them with the proposed MSS-PWM and MAS-PWM. Only parallel converters will be assigned in the following. As already mentioned, the multirate modulator is directly transposable to series converters.

The definition of the "fastest response" implies taking into account the duty cycle saturation. In contrast to the classical small signal approach, the simulations are focused on a large-scale reference voltage step (from 10% to 90% of the DC bus voltage). In these conditions, the best reachable performance of a topology is defined as the fastest step response while respecting the duty cycles' physical limits, i.e. 𝛼 𝐶𝑀 ∈ [0,1].

The state space feedback gains are computed by choosing a specified time instant for the first peak value 𝑡 𝑝𝑒𝑎𝑘 of the closed loop output voltage with a damping ratio 𝜉 = 0.7 to ensure a corresponding voltage overshoot less than 5%. An iterative approach using numerical simulations is performed to find the fastest response according to the duty cycle limitations. Starting from a specified closed loop time response involving the duty cycle saturation (typically 𝑡 𝑝𝑒𝑎𝑘 < 𝑡 𝑜𝑝𝑡𝑖𝑚𝑎𝑙 ), 𝑡 𝑝𝑒𝑎𝑘 is increased step by step until it is find the first step response for which the duty cycle 𝛼 𝐶𝑀 is less than one, meaning that the control does not saturate. This response is then considered as the best for the situation under analysis and, thus, these control gains are used.

Moreover, the following premises will be assumed in the simulations and for the experimental results: 1) 𝑉 𝐻𝑉 = 100𝑉 and 𝑓 𝑆𝑤 = 20kHz;

2) The filter is designed for each parallel converter, as the procedure described in Section II, i.e. the filter parameters of Table I are employed; 3) The controller gains are always calculated for each specific case in order to have the fastest possible response, changing with 𝑛 𝑐𝑒𝑙𝑙 , the filter parameters, the load and also with the modulation strategy.

B. Simulation Results -Parallel Multicell Converters

To illustrate the use of the previous algorithm, closed loop simulations are performed using parallel converters, as depicted in Fig. 4, for 𝑛 𝑐𝑒𝑙𝑙 ∈ [START_REF] Rodriguez | Multilevel Converters: An Enabling Technology for High-Power Applications[END_REF][START_REF] Nademi | Power Quality Characteristics of a Multilevel Current Source With Optimal Predictive Scheme From More-Electric-Aircraft Perspective[END_REF] with filter parameters of Table I and rated load resistance (𝑟 𝐿𝑜𝑎𝑑 = 5Ω). This allows comparing the performances of the proposed multirate modulator with regard to the classical strategies of updating the cells duty cycles.

The step response performance changing the reference from 10% to 90% is evaluated using the first peak time 𝑡 𝑝𝑒𝑎𝑘 expressed as a function of the switching period 𝑡 𝑠𝑤 and the overshoot for the different number of cells and different sampling rate, as depicted in Fig. 10. In the same figure is also plotted the optimal time response of the output filter calculated as demonstrated in Section III and shown in Table II. This reference allows evaluating the distance between the control performances and the best obtainable physical responses.

The sampling process clearly reduces the bandwidth and the use of an asymmetrical sampling enhances the response for two and three cells. From Fig. 10, the time response with the proposed multirate modulation is improved in relation to the classical symmetrically and asymmetrically sampled ones no matter the number of cells, providing a closer-to-optimal response than the latter. As the classical approach does not accounts for the non-linearity of the system, the overshoot tends to be higher when compared to the proposed multirate.

Through Fig. 10, it is also observed that the fastest response can be achieved with a three-cell converter. This is a particular case for the chosen filter design that keeps the equivalent inductance (𝐿 𝐿𝑉 /𝑛 𝑝 ) constant independently of the number of cells (see Table I), while the capacitance drops with 𝑛 𝑝 3 . The dynamics is more affected for smaller number of cells and tends to be constant increasing the number of cells. The 𝑠 𝑟𝑎𝑡𝑒 also has higher influence on converters with a smaller number of cells.

As the three-cell parallel converter has the fastest response in this case, it is the one chosen for study in the following sections.

C. Simulation Results -Three-Cell Parallel Converter

First, the effect of the variation of filter parameters on the three-cell parallel converter is investigated. The inductance and capacitance values presented in Table I are considered as a base and they are varied from -20% to +20%. Fig. 11(a) and(b) show the time of the first voltage peak as a function of 𝑡 𝑠𝑊 for both classical SS-PWM and proposed MS-PWM, respectively.

It can be seen that, when the classical modulator is employed, the system is more prone to variations in the time response. In this case, the higher the inductance, the slower is the response. However, the most important factor is the capacitance: the higher it is the faster is the response.

When the multirate modulator is employed, the capacitance has almost no effect on the time response when evaluated individually, whereas the inductance has a small influence. One can notice that the multirate modulator reduces the effect of the parameters variation and always leads to a better response compared to the classical one.

Since the results from Fig. 11 consider a fixed load (rated current), Table VI shows the comparison of the time to reach the first voltage peak between both modulators for different load resistances. Furthermore, the optimal time is presented for sake of comparison. The system response is more affected when the classical modulator is employed and the proposed method has superior performance regardless of the load resistance.

D. Experimental Setup -Three-Cell Parallel Converter

The experimental setup is constituted of a three-cell parallel converter. Its structure is the same as the one presented in Fig. 4 with 𝑛 𝑐𝑒𝑙𝑙 = 3. In fact, there is a small difference in the prototype values (𝐿 𝐿𝑉 = 650µ𝐻, 𝐶 𝐿𝑉 = 2.5µ𝐹), that influences the system response mainly in the SS-PWM, as demonstrated in the points signaled in Fig. 11. The workbench used on all tests is depicted in Fig. 12.

E. Experimental Results -Open Loop

First, an open loop study is made. For this, it is important to check the mean value of all individual 𝛼 𝑐𝑒𝑙𝑙 𝑖 , which is the mean equivalent duty cycle (𝛼 𝑒𝑞 ) perceived by the converter. Fig. 13 shows 𝛼 𝑒𝑞 for the classical SS-PWM, the proposed MSS-PWM and also for the NS-PWM. When updating duty cycles in multicell converters without overswitching, there is a time delay between calculated and synthetized equivalent duty cycles. This is due to the restriction that each cell can switch only in a certain proper time. As shown in Fig. 13, during the given step change, the multirate algorithm reaches the final desired reference level a whole sampling time earlier (twice as fast) than the classical SS-PWM approach, which reduces the aforementioned modulator delay. When the system is submitted to a change in the reference output voltage, the NS-PWM allows for a fast response by immediately updating the duty cycle of every single cell in the converter regardless of the occurrence of overswitching. Given that overswitching is a problem because it increases losses and causes EMI problems, it is desired that this behavior is avoided.

The classical SS-PWM and AS-PWM prevent the occurrence of overswitching by allowing the update of each cell duty cycle only once per carrier period. The proposed multirate PWM is a middle ground between the natural and classical PWMs: by determining which cell has already switched during its own PWM cycle and preventing their duty cycle from changing at a software (code) level, it allows the immediate update of all of the other cells' duty cycles while avoiding overswitching. Thus, the proposed multirate is able to present faster responses than the classical SS-PWM and AS-PWM as observed from the curves presented in Fig. 14.

F. Experimental Results -Closed Loop

The load voltages from Fig. 14 present steady state error for all of the tested PWM methods. Therefore, even though the advantages of the proposed modulator can be seen in open loop, an enhancement of the response can be better in closed loop. Table VII shows the closed loop gains calculated for rated load resistance load for the tested modulation methods. Only the strategies without overswitching will be compared. Trying to make the control extremely fast is a challenge in the prototype due to the inherent time delays between duty cycle computations and analog to digital conversions (ADC) of measurement samples. Using the measured quantities in the control leads to an unstable behavior since it has not been designed to compensate these delays. This particular point is out of the present paper scope.

To overcome this problem and validate the proposed method, a state space estimator [START_REF] Kuo | Automatic control systems[END_REF] based on Eq. 13 is implemented to estimate the voltage and current used in the control instead of the measurements. In this configuration, it is possible to highlight the performances of the modulator regardless of the constraints related to the measurement delays. Nevertheless, it is important to highlight that the experimental results presented are from direct measurements of the output voltage.

The converter duty cycles are computed by the control, using the estimator and the modulator. The RT Box's processor does this within the available calculation period of 16.6µ𝑠 for symmetrical sampling and 8.3µ𝑠 for asymmetrical sampling. To complete a computation cycle, it takes a total time of 1.1µ𝑠 for the multirate strategy (MSS-PWM and MAS-PWM) and 0.62µ𝑠 for the classical one (SS-PWM and AS-PWM). For the worst scenario of asymmetrical sampling, this means 13.3% and 7.5% of processor usage, respectively. Fig. 15(a) shows the comparison of the SS-PWM, AS-PWM, MSS-PWM and MAS-PWM for rated load resistance (𝑟 𝐿𝑜𝑎𝑑 = 5 Ω) in closed loop operation. For the sake of validation, the simulation results are also plotted using the filter parameters of the experimental setup. In fact, the measurements have a delay of one sampling time in comparison with the simulation, because the digital control platform has an inherent calculation time and the command signal is only made available in its output in the next sampling period. For a more direct comparison, the simulation data is delayed by its modulator respective 𝑡 𝑑𝑒𝑙𝑎𝑦 in the presented graph. From Fig. 15, for the symmetrical sampling cases, the proposed method makes the response much faster and it also reduces the overshoot. This happens because the multirate modulator can effectively control the average value of the chopped voltage over each 𝑡 𝑠𝑊 /3 interval (instead of 𝑡 𝑠𝑊 for the standard modulator). For the asymmetrical sampling cases, the response is faster with the multirate modulator, but the improvement is marginal for this specific test. As already mentioned while discussing the simulation results and it will be reinforced by the experimental results, such improvement depends on the load and the filter.

It is also important to highlight that, in both cases, the control output (duty cycle) peaks at (but does not exceed) 100%, as in Fig. 15(b). This proves that both controllers were efficiently designed to maximize speed without distortion in this 10% to 90% voltage reference (𝑉 𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 ) step. Thus, the enhancement in the system performance is due to the proposed method, not because of the different control tuning for each load.

As shown in Fig. 15(c), the average current values of each cell converge to values that are very close to each other, with the differences between them being due to deviations inherent to the manufacturing process of the used inductors. This small unbalance in steady state exists for all the modulation strategies and it can be eliminated by using differential control techniques as the one presented in [START_REF] Chen | Decoupled Master-Slave Current Balancing Control for Three-Phase Interleaved Boost Converters[END_REF]. To disturb the common mode current as little as possible and have a fast response, the single constraint is to design the differential control with a low bandwidth with regard to the common mode dynamic.

Furthermore, it can be seen from Fig. 15(a) that the measured load voltage overshoot and first peak time for all tested modulators (specially for the multirate ones due to their resilience to parametric deviation) is in agreement with the information disclosed in Fig. 10 and Fig. 11 for 𝑛 𝑐𝑒𝑙𝑙 = 3 and the previously discussed filter analysis is validated.

Fig. 16 shows results for the symmetrical and asymmetrical sampling strategies with different 𝑟 𝐿𝑜𝑎𝑑 . From it, the higher the resistance (smaller current), the faster the response in all cases. The multirate modulator has faster responses than the classical strategy while keeping the overshoot within design constraints.

G. Experimental Results -Steady State Analysis

To deepen the study of the proposed multirate modulator, it is fitting to carry out an analysis of its performance in steady state through zoom-ins on Fig. 14 and Fig. 15. Thus, Fig. 17 allow the comparison between the steady state load voltages' waveforms with rated load for both the classical and multirate modulators. From all the curves shown in these figures, it is noted that the multirate modulator not only allows for faster responses with smaller overshoot, but it also does not provoke any degradation of the system's performance in steady state.

VII. CONCLUSIONS

In this paper, a novel multirate modulator is proposed to improve the closed loop performances of the output voltage control of parallel and series converters. This modulator takes into account the non-linearity between the subcycle duty cycle and the subcycle average output voltage of multicell converters. A generic multirate modulator has been developed to be adaptable for any cell number and for the two different sampling strategies (symmetrical and asymmetrical). One of its advantages is that both the MSS-PWM and MAS-PWM are fully software implemented and overswitching is avoided. The reduction of the modulator delay will affect the overall control performance and it is one way to achieve a better global response. The open loop step responses demonstrate that the multirate modulator allow the converter's mean equivalent duty cycle to reach steady state faster than the classical SS-PWM and AS-PWM. This improved performance also lead to better results for the closed loop tests. Thus, by using the multirate modulator, it is possible to obtain faster responses (without degrading the system's steady state performance) and this can be a significant improvement when high bandwidth is required.

It was shown through simulations and experimental results that this proposed multirate strategy (the MSS-PWM and MAS-PWM) always surpasses the classical SS-PWM and AS-PWM regarding the reachable time response no matter the load and even considering a variation in the filter parameters. This concept is also immediately applicable to series converters since there is a duality between them.

Lastly, the effects of decreasing the modulator's time might not be noticeable if the filter design is not proper. If this happens, the effects of the modulator's delay reduction may be overshadowed by the slower dynamics imposed by the filter itself. In light of this, a study of the influence of the number and configuration of cells in the filter design and control dynamic behavior was presented. By optimizing the filter and having a quick multirate modulator, it is possible to design even faster controllers to have fast global responses.

Fig. 1 a

 1 Fig. 1 a) DC/DC series-parallel multicell converter (2 parallel, 3 series) and (b) DC/AC series-parallel multicell converter (2 parallel, 3 series).

Fig. 2

 2 Fig. 2 Optimal response at no-load.

Fig. 3

 3 Fig. 3 Optimal response of loaded converter.

Fig. 4 Fig. 5

 45 Fig. 4 Generic 𝑛 𝑐𝑒𝑙𝑙 parallel converter.

Fig. 6

 6 Fig. 6 Filter equivalent circuit for parallel and series topologies.

Fig. 7 Fig. 8

 78 Fig. 7 State space feedback control.

Fig. 9

 9 Hypothetical three-cell converter: (a) PWM carriers during one subcycle sampling period and (b) possible voltage contributions of each cell. TABLE IV RULES FOR 𝑒𝑛 𝑘-1 AND 𝑒𝑛 𝑘-2 TO AVOID OVER-SWITCHING 𝑒𝑛 𝑘-1 If 𝛼 𝑘-1 𝑡 𝑘-1 < 2/3, the cell 𝑐𝑒𝑙𝑙 𝑘-1 has already switched during the last increasing phase of the carrier signal: 𝑒𝑛 𝑘-1 = 0 (no change allowed on the duty cycle).

Fig. 10

 10 Fig. 10 Closed loop system response of 𝑛 𝑐𝑒𝑙𝑙 parallel converters using the SS-PWM, AS-PWM, MSS-PWM and MAS-PWM for rated resistance.

Fig. 11

 11 Fig. 11 Time response of three-cell parallel converter with closed loop control for 𝑟 𝐿𝑜𝑎𝑑 = 5 Ω: (a) SS-PWM and (b) proposed MSS-PWM. Fuji Electric 2MBI300VB060 IGBT are used and the system is controlled by a PLECS RTBox with a deadtime of 1𝜇𝑠. Each individual carrier has a frequency of 𝑓 𝑆𝑤 = 20kHz, thus the sampling period is 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 ′ = 16.6𝜇𝑠 for the symmetrically sampled cases and 𝑡 𝑠𝑎𝑚𝑝𝑙𝑒 ′′ = 8.3𝜇𝑠 for the asymmetrically sampled ones. The employed filter has similar parameters to the previous design.In fact, there is a small difference in the prototype values (𝐿 𝐿𝑉 = 650µ𝐻, 𝐶 𝐿𝑉 = 2.5µ𝐹), that influences the system response mainly in the SS-PWM, as demonstrated in the points signaled in Fig.11. The workbench used on all tests is depicted in Fig.12.

Fig. 12 Fig. 13

 1213 Fig. 12 Experimental setup: DC/DC three-cell parallel converter.

Fig. 14

 14 shows the load voltage comparison of the NS-PWM, SS-PWM, AS-PWM, MSS-PWM and MAS-PWM for the rated load resistance (𝑟 𝐿𝑜𝑎𝑑 = 5 Ω) in open loop operation. The inherent time delays (𝑡 𝑑𝑒𝑙𝑎𝑦 ) between computing the duty cycle and outputting the commands are highlighted in the graph for each sampling strategy.

Fig. 14

 14 Fig. 14 Experimental results (time response) of the three-cell parallel converter in open loop with rated load: measured load voltages with (a) the SS-PWM, NS-PWM and MSS-PWM and (b) the AS-PWM, NS-PWM and MAS-PWM.

Fig. 15

 15 Fig. 15 Experimental results (time response) of the three-cell parallel converter with closed loop control using the classical SS-PWM and AS-PWM and the proposed MSS-PWM and MAS-PWM: (a) load voltage, (b) duty cycle (control command) and (c) cells, common mode and load currents with MSS-PWM.

Fig. 16

 16 Fig. 16 Experimental results obtained by changing the load resistance (rated values): a) SS-PWM and MSS-PWM and b) AS-PWM and MAS-PWM.

Fig. 17

 17 Fig. 17 Experimental results of the three-cell parallel converter with rated load for both a 10𝑉 and a 90𝑉 voltage reference: steady state load voltages with the classical and multirate modulators in (a) open loop and (b) closed loop.

TABLE I FILTER

 I

		𝑛 𝑐𝑒𝑙𝑙	1	2	3	4	5	6	7
	𝐶 𝐿𝑉	𝑝	75	9.3	2.8	1.17	0.6	0.35	0.2
	(µF)	𝑠	75	37.5	25	18.75	15	12.5	10.7
	𝐿 𝐿𝑉	𝑝	208	416	625	833	1041	1250	1458
	(µH)	𝑠	208	52	23.1	13	8.3	5.8	4.2

PARAMETERS: 𝑉 𝐻𝑉 = 100V, 𝐼 𝐿𝑉 = 20A, 𝑓 𝑆𝑤 = 20kHz (SERIES "𝑠" AND PARALLEL "𝑝" CONVERTER CONFIGURATIONS)

TABLE II OPTIMAL

 II

	𝑛 𝑐𝑒𝑙𝑙	1	2	3	4	5	6	7
	𝑝	5.0	1.98	1.55	1.6	1.76	1.79	1.80
	𝑠	5.0	1.75	0.95	0.61	0.44	0.33	0.26

TIME RESPONSE (MULTIPLES OF 𝑡 𝑠𝑊 ): 𝑉 𝐻𝑉 = 100V, 𝐼 𝐿𝑉 = 20A, 𝑓 𝑆𝑤 = 20kHz AND RATED 𝑟 𝐿𝑜𝑎𝑑 = 5Ω (SERIES "𝑠" AND PARALLEL "𝑝" CONVERTER CONFIGURATIONS)

TABLE III DEFINITION

 III

OF USED VARIABLES

𝑐𝑒𝑙𝑙 𝑘

: cell of which associated carrier signal equals 0 at 𝑡 𝑘 𝑐𝑒𝑙𝑙 𝑘-1 : cell of which associated carrier signal was equal to 0 at 𝑡 𝑘-1 𝑐𝑒𝑙𝑙 𝑘-2 : cell of which associated carrier signal was equal to 0 at 𝑡 𝑘-2 𝑉 𝑐𝑒𝑙𝑙 𝑘 𝑡 𝑘 : average normalized voltage on [𝑡 𝑘 , 𝑡 𝑘+1 ] generated by 𝑐𝑒𝑙𝑙 𝑘 𝑉 𝑐𝑒𝑙𝑙 𝑘-1 𝑡 𝑘 : average normalized voltage on [𝑡 𝑘 , 𝑡 𝑘+1 ] generated by 𝑐𝑒𝑙𝑙 𝑘-1 𝑉 𝑐𝑒𝑙𝑙 𝑘-2 𝑡 𝑘 : average normalized voltage on [𝑡 𝑘 , 𝑡 𝑘+1 ] generated by 𝑐𝑒𝑙𝑙 𝑘-2 𝛼 𝑘 𝑡 𝑘 : signal sent to the non-inverting input of comparator 𝑘 during [𝑡 𝑘 , 𝑡 𝑘+1 ] 𝛼 𝑘-1 𝑡 𝑘 : signal sent to the non-inverting input of comparator 𝑘 -1 during [𝑡 𝑘 , 𝑡 𝑘+1 ] 𝛼 𝑘-2 𝑡 𝑘 : signal sent to the non-inverting input of comparator 𝑘 -2 during [𝑡 𝑘 , 𝑡 𝑘+1 ]

TABLE VI TIME

 VI TO FIRST PEAK FOR A THREE-CELL PARALLEL CONVERTER (MULTIPLE OF 𝑡 𝑠𝑊 ): 𝑉 𝐻𝑉 = 100𝑉, 𝐼 𝐿𝑉 = 20𝐴, 𝑓 𝑆𝑤 = 20kHz, 𝑠 𝑟𝑎𝑡𝑒 = 1 𝑟 𝑙𝑜𝑎𝑑 (𝛺)

		3.5	5	6.5	8	9.5	11	20
	SS-PWM	7.83	3.81	3.80	3.83	3.83	3.83	5.81
	MSS-PWM	4.17	2.83	2.50	2.17	1.83	1.83	1.83
	Optimal	2.37	1.55	1.25	1.13	1.07	1.03	0.97

TABLE VII DESIGNED

 VII CLOSED LOOP GAINS FOR EACH TESTED MODULATOR

	Modulator	𝐾 𝐿	𝐾 𝑓	𝐾 𝑖
	SS-PWM	0.0527	-0.0080	-123.4379
	AS-PWM	0.1778	-0.0114	-619.7231
	MSS-PWM	0.1049	-0.0039	-469.0183
	MAS-PWM	0.2033	-0.0074	-924.3017