Eduardo Aldrete-Vidrio

Diego Mateo
email: mateo@eel.upc.edu

Josep Altet
email: pepaltet@eel.upc.edu

DIFFERENTIAL TEMPERATURE SENSORS IN 0.35µm CMOS TECHNOLOGY

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INTRODUCTION

Temperature at the surface of a silicon IC is a physical magnitude whose evolution depends on the activity of the circuits embedded in the semiconductor die. There is a direct relation between the power dissipated by devices and the IC surface thermal map. Therefore, as the power dissipated by each device depends on its specific working conditions (e.g., operating point, input values, topology figures of merit of circuits as gain and non-linearities, etc.), it is possible to perform the circuit test through temperature measurements. For instance, in [START_REF] Kölzer | Electrical characterization of megabit DRAMs-Part 2: Internal testing[END_REF][START_REF] Altet | Thermal coupling in Integrated Circuits; Application to Thermal Testing[END_REF] abnormal hot spots appearing on the silicon surface are related to changes in the topology of analog and digital circuits due to the presence of structural defects, and the temperature is being used as a test observable of ICs (thermal testing).

Temperature sensors can be used to track the power dissipated by devices placed in the silicon die. They precise a very selective sensitivity: they need high sensitivity to small changes in temperature provoked by a change of the power dissipated by the circuit under measure, but they require a very low sensitivity to changes in temperature provoked by external elements, such as ambient temperature. This is achieved with a differential sensing strategy [START_REF] Altet | Differential Sensing Strategy for Dynamic Thermal Testing of ICs[END_REF]: differential sensors are sensitive to changes of the difference in temperature at two points of the silicon surface.

Besides built-in thermal testing presented in [START_REF] Altet | Thermal coupling in Integrated Circuits; Application to Thermal Testing[END_REF] and [START_REF] Altet | Differential Sensing Strategy for Dynamic Thermal Testing of ICs[END_REF], some applications of build-in differential temperature sensors involve defect localization, and electrical characterization. For instance, in [START_REF] Altet | Thermal Testing: Fault Location Strategies[END_REF] the distance between monitoring point and the defect has been determined with amplitude thermal measurements. To obtain the exact location of the defect, three different monitoring points are needed. In an early work [START_REF] Mateo | An approach to the electrical characterization of analog blocks through thermal measurements[END_REF], the possibility to characterize the electrical performance of high frequency analogue blocks into a system on chip (SoC) by thermal measurements has been proposed.

Prior realizations of active differential temperature sensors can be found in [START_REF] Altet | Thermal coupling in Integrated Circuits; Application to Thermal Testing[END_REF], where two sensors manufactured in a 1.2µm BiCMOS technology are experimentally reported. Simulated analysis of active CMOS temperature sensors can be found in [START_REF] Syal | CMOS Differential and Absolute Thermal Sensor[END_REF][START_REF] Altet | Sensing temperature in CMOS circuits for thermal testing[END_REF]. A passive differential temperature sensor based on thermopiles can be found in [START_REF] Charlot | Fault modeling of suspended thermal MEMS[END_REF]. Thermocouples were made with poly-metal couples in a 0.6µm AMS bulk micromachining process. Embedded transducers fabricated whit silicon CMOS compatible technologies offer the possibility of providing low cost applications. Fabrication of such devices can avoid semiconductor foundries integrating new material layers and processes in their standard microelectronics flow, where the circuits to be tested and/or characterized are implemented.

The objective of this paper is to present two (active and passive) fully CMOS compatible differential sensing strategies fabricated in a 0.35µm CMOS process. Active sensors are based on differential amplifiers, using lateral parasitic bipolar transistors acting as transducer devices. To the best of our knowledge, this paper reports the first experimental data of pure active CMOS differential temperature sensors. Passive differential sensors are thermopile-based, made of poly1-poly2 (both n-type) and poly1-P+ implant thermocouples connected in series. Thermopile senses the temperature gradient in the substrate surface and generates an output voltage by Seebeck effect. Thus it is possible to characterize the Seebeck coefficient of couple materials used from the 0.35µm standard CMOS technology.

E. Aldrete-Vidrio, D. Mateo, J. Altet Differential Temperature Sensors in 0.35µm CMOS Technology

The paper is organized as follows: section 2 summarizes the main figures of merit of active differential temperature sensors and presents the different topologies reported in this paper. Sections 3 and 4 report the measurements of the active differential temperature sensors. Section 5 deals with the thermopile-based temperature sensors. Finally, section 6 concludes the paper.

TOPOLOGIES AND FIGURES OF MERIT OF ACTIVE SENSORS

Figure 1 shows two different topologies of a differential temperature sensor. Depending on the nature of its output voltage, the sensor can be classified in: a) monopolar or b) differential. In Figure 1, the square represents the location of the temperature transducer devices, S 1 an S 2 , i.e., the points of the IC layout where temperatures T 1 and T 2 are measured. Ideally, the output voltage of the sensor circuit is only sensitive to the temperature difference (T 1 -T 2 ). However, the output voltage of differential sensors can be shown to be:

2 ) ( 2 1 2 1 T T S T T S V cT dT out + + - = ∆ (1)
where S dT is the sensor's differential sensitivity and S cT is the sensor's common sensitivity. Ideally, the common sensitivity should be 0. The experimental setup for the sensor sensitivity measurements is as follows. As indicated in Figure 1, a heat dissipating device is placed at a distance D 1 from S 1 , and a distance D 2 from S 2 .

The temperature difference generated at the temperature sensing points is provoked by the device power dissipation. Therefore, the sensor sensitivity can be expressed as a variation of the sensor output voltage versus the power dissipated by the heating device, its means [V/W]. In such a case, the distance between sensor transducers and heat dissipating devices is a very important data.

DIFFERENTIAL TEMPERATURE SENSOR WITH MONOPOLAR OUTPUT

The schematic of the implemented differential thermal sensor circuit (DTSC) with monopolar output is shown in Figure 2. It consists of a symmetrical CMOS transconductance amplifier (OTA) structure [START_REF] Laker | Design of Analog Integrated Circuits and Systems[END_REF]. In this case, the temperature transducers devices (TTDs) are two lateral bipolar transistors Q 1 and Q 2 that are inherent in the existing CMOS digital technology, since they have the same temperature behaviour with respect to standard bipolar technologies [START_REF] Vittoz | MOS transistors operated in the lateral bipolar mode and their application in CMOS technology[END_REF][START_REF] Merino | Smart temperature sensor for on-line monitoring in automotive applications[END_REF]. Their operating temperatures are T 1 and T 2 , respectively. The emitter area (2x2µm 2 ) of the CMOS-compatible lateral bipolar transistor is a fixed constant and predefined by the process technology. Two calibration transistors, M p and M n , acting as current sources have been added. They are capable of compensating by externally adjusting the DC operating point for both random and systematic thermal offset, and the possible mismatching between transistors. The biasing and output circuitry is setting by the other transistors in the circuit.

V DD V OUT V SS M 1 M p M 5 M 6 M 4 M 3 Q 1 T 2 V DD V G V Offp V Offn Q 2 Q B M n M 2 M F T 1
The operation principle and analysis of the DTSC is the same as that proposed in [START_REF] Altet | Differential Sensing Strategy for Dynamic Thermal Testing of ICs[END_REF]: when no change in temperature is present between transistors Q 1 and Q 2 , half of the current level determined by transistor M F , flows trough Q 1 and M 1 , with the other half flowing through Q 2 and M 2 . Therefore, the output voltage variation, ∆V out , is zero. A differential of temperature between Q 1 and Q 2 will cause currents imbalance in the input branches. The output stage converts this currents imbalance into output voltage. As a result, an output voltage variation with a significant gain is produced. The DTSC and four identical heat sources (HSs) consisting of a MOS transistor connected in diode configuration have been fabricated in a 0.35µm CMOS standard process technology from AMS. Figure 4 shows a photograph of the sensor and heat sources. The layout was done such that the TTDs are placed at a relative large distance from each other, e.g. 400µm. Three of the heat sources are located at 20µm, 100µm and 220µm from Q 1 , or at 420µm, 500µm, and 620µm from Q 2 (right side of Figure 4) and the fourth one is located at 20µm from Q 2 , or at 420µm from Q 1 (left side of Figure 4).

DC power dissipated by each hest source as a function of its bias voltage can be externally set up. Their power dissipation range goes from 0 to 11mW. Once an individual heat source is activated, the temperature at the silicon surface around the device increases; this temperature increase is measured by the DTSC. Figure 5 shows the measured values of the static output voltage variation of the sensor as a function of the power dissipated by each activated heat source. Curves A have been obtained when only the heat source located at 20µm from Q 1 is activated. When only the heat source located at the same distance from Q 2 is activated, Curves B can be generated. Once the thermal steady state is reached, the output voltage measurement is taken. In Figure 6, the voltage/power gains for different distances between the active heat source and Q 1 for V G = 2.5V are plotted. The heat source located at 100µm produces a gain of 210 V/W in the sensor, whereas the most distant heat source produces a gain of 105 V/W. This fact illustrates the high sensitivity of this sensor to detect an active heat source in the same silicon substrate.

V G [V] Q 1 [V/W] Q 2 [V/W]
In Figure 7, the two equidistant heat sources (at 20µm) from Q 1 and Q 2 have been simultaneously activated. The voltage/power gains as a function of the bias voltage V G are plotted. The measurements show that a lower biasing (means lower current and therefore higher output impedance of transistor current source M F ) cause a lower common sensitivity.

Figure 8 shows comparisons between measured and simulated values of the total bias current and the output voltage as a function of V G . Good agreement between the simulated and measured bias current values has been showed. However, this is not the case for the output voltage where there is a major difference between values, which indicates the present of a thermal offset as a result of the distance between both TTDs in the sensor circuit (mismatching). E. Aldrete-Vidrio, D. Mateo, J. Altet Differential Temperature Sensors in 0.35µm CMOS Technology

V DD V O1 V SS M 1 M p M 5 M 6 M 4b M 3 Q 1 T 2 V DD V G V Offp V Offn Q 2 Q B M n M 2 M F T 1 M 6b M 4 M 5b M 3b V O2
Figure 9: Schematic of the built-in fully DTS.

FULLY DIFFERENTIAL TEMPERATURE SENSOR

The first active fully differential temperature sensor (F-DTS) circuit to be reported in a fully CMOS technology is presented in this section. Figure 9 shows the schematic of the F-DTS. Operating principles are the same as the previous sensor. The F-DTS is based on a fully symmetric fully balanced OTA proposed in [START_REF] Cooper | A fully Balanced Pseudo-Differential OTA With Common-Mode Feedforward and Inherent Common-Mode Feedback Detector[END_REF]. It can be described as a conventional three-current-mirrors singleended OTA (see Figure 2), plus the additional branches formed by transistors M3b, M4b, M5b, and M6b. Thus, the OTA becomes fully differential, which has an improved dynamic range over its monopolar-ended counterpart. This is due to the properties of any differential structure, namely, better common-mode noise rejection, better distortion performance, an increased output voltage swing. Figure 9.a shows the HSPICE simulation, where the differential output voltage variation as the temperature of sensing devices is increased by 1ºC is plotted. Figure 9.b shows the voltage sensitivity of the F-DTS compared with its monopolar-ended counterpart. It can be seen that the F-DTS has almost the same sensitivity of the DTS (≈ 8 V/ºC). However the F-DTS presents a larger linear region at the same operation conditions:

V DD = 3.3V, V SS = 0V, I MF ≅ 3µA and V G = 2.4V.
The F-DTS has been fabricated using the same technology and following the same DTS circuit criteria. The set of heat sources is shared (see Figure . 4).

Figure 10 shows measured static differential output voltage variation of the F-DTS as a function of the power dissipated by each heat source individually activated: at 20µm, 100µm and 220µm from Q 1 , or at 420µm, 500µm, and 620µm from Q 2 , and one located at 20µm from Q 2 , or at 420µm from Q 1 (see Figure 4). The voltage/power gains are given in Table II. The reduction in voltage/power gain is due to the operating point which cannot be correctly adjusted, since the calibration transistors (M p and M n ) have been only added in one branch of the differential pair, and due to the loading effect. The non-symmetry between the gains when the heat sources located to the same distance of Q 1 and Q 2 are activated is due to the sensor asymmetry: introduced by auto polarization scheme (transistor Q B ) and the compensation circuit.

Q 1 [V/W] Q 2 [V/W]

THERMOPILES

The thermopile is a temperature sensor based on Seebeck effect. This effect results in the generation of a voltage between the ends of two joint materials (thermocouples) that have different Seebeck coefficients and are placed on a temperature gradient (see Figure 11). In order to be able to characterize the Seebeck coefficients of the 0.35µm CMOS technology, two thermopiles have been implemented and measured. Both thermopiles have the same structure but different materials.

The first one is made of a total of 16 stripes, 8 of Poly1 (n doped) and 8 of Poly2 (n doped), connected alternatively (8 thermocouples serially connected. See Figure 10, where the left part of both thermocouples is shown; the connections of the cold end are visible at the left of the photograph). The second thermocouple is made of 8 stripes of Poly1 and 8 of stripes of P+ implantation. All stripes are 500µm long (which is the distance between the hot and cold ends), and their width is the minimum allowed by the technology in each case (that is 0.65µm for Poly layers and 0.3µm for p+ implantation).

The temperature gradient is generated by a MOS transistor sized W/L = 20µm/0.35µm, connected in diode configuration and placed in what we call hot end of the thermopiles, which can dissipate up to 48 mW. From the plots shown in Figure 12 and 13, it can be observed that the sensitivity of the Poly1-Poly2 thermopile is 0.1 V/W, whereas it is 0.26 V/W of the Poly1-P+ one.

CONCLUSIONS

In this paper we have presented two differential temperature sensing strategies manufactured in a 0.35µm CMOS technology. Two active temperature sensors use CMOS compatible lateral PNP bipolar transistors as E. Aldrete-Vidrio, D. Mateo, J. Altet Differential Temperature Sensors in 0.35µm CMOS Technology temperature transducers. The first one has a monopolar output, whereas the second one has a differential output. Static simulation and experimental results have been reported. Simulation analysis gives differential sensitivities of 8 V/ºC the monopolar and the differential sensors. When a heat source placed at 20 µm from one of the temperature transducers and 420 µm from the other, measurements have given differential sensitivities of 627.5 V/W and 398.2 V/W respectively, proving that CMOS differential temperature sensors can be used to track the power dissipated by devices placed in the same silicon substrate. In addition, sensitivities of two integrated thermopiles (passive differential sensors) made with standard CMOS materials have been reported. 0.1 V/W for Poly1-Poly2 and 0.26 V/W for Poly1-p+ materials.

Figure 1 :

 1 Figure 1: Symbol of two Differential Temperature Sensors (DTS): a) monopolar output, and b) differential output.

Figure 2 :

 2 Figure 2: Schematic of the monopolar output differential temperature sensor.

Figure 3 :

 3 Figure 3: Output voltage variation ∆V out as a function of temperature increase in Q 1 (Q 2 ) while Q 2 (Q 1 ) remains at nominal temperature (27 o C).

Figure 4 :

 4 Figure 4: Photograph of built-in temperature sensors and 3 of the 4 heat sources ( , and ).

Figure 3 .

 3 Figure 3.a shows HSPICE simulated results of the static output voltage variation when the temperature of transistor Q 1 is increased by 1ºC with respect to the nominal temperature (27ºC), while Q 2 remains at room temperature, and vice versa. Different values of biasing voltage V G have been analyzed. Figure 3.b shows a zoomin over the temperature range before the output voltage saturates. If the nominal parameters of the devices are used throughout the analysis a voltage sensitivity of approximately -8 V/ºC can be reached when V G = 2.4V, corresponding to a common mode gain of 1.88 mV/ºC (V DD = 3.3V, V SS = 0V, I MF ≅ 3µA).The DTSC and four identical heat sources (HSs) consisting of a MOS transistor connected in diode configuration have been fabricated in a 0.35µm CMOS standard process technology from AMS. Figure4shows a photograph of the sensor and heat sources. The layout was done such that the TTDs are placed at a relative large distance from each other, e.g. 400µm. Three of the heat sources are located at 20µm, 100µm and 220µm from Q 1 ,

Figure 6 :

 6 Figure 6: Voltage/Power gain plot for different distances between the active heat source and Q 1 . V G = 2.5V.

Figure 7 :Figure 8 :

 78 Figure 7: Output voltage as a function of the power dissipated at the same time by the equidistant HS's from Q 1 and Q2 as a function of the bias voltage V G .

Figure 9 :Figure 10 :Figure 11 :

 91011 Figure 9: Differential output voltage as a function of temperature increase in Q 1 (Q 2 ) while Q 2 (Q 1 ) remains at nominal temperature (27 o C). V G = 2.4V.

Figure 12 :

 12 Figure 12: Output voltage of thermocouple Poly1-Poly2 as a function of the power dissipated by the MOS transistor.

Figure 13 :

 13 Figure 13: Output voltage of thermocouple Poly1-P+ as a function of the power dissipated by the MOS transistor.

  Table I summarizes the voltage/power [V/W] gain for different values of the bias voltage V G .

					E. Aldrete-Vidrio, D. Mateo, J. Altet
			Differential Temperature Sensors in 0.35µm CMOS Technology
		1
						VG=2.5V
		0.8	HS 20µm from Q1
		0.6				VG=2.4V
			A
		0.4				VG=2.3V
	∆VOUT [V]	-0.2 0 0.2
		-0.4
		-0.6	B			VG=2.4V VG=2.3V
		-0.8	HS 20µm from Q2			VG=2.5V
		-1
		0	1	2	3	4
			Power of HS [mW]
	Figure 5: Measurements of ∆V out vs. power dissipated by
		heat sources located at 20µm from Q 1 and Q 2 ,
		respectively. V G = 2.3V, 2.4V and 2.5V.
		TABLE I: Voltage/Power gain for different V G
		bias voltages and active HS located at 20 µm
			from each TTDs.

TABLE II :

 II Voltage/Power gain for V G = 2.4V. HS located at 20 µm, 100 µm, and 220 µm from TTDs.

	HS Distance
	[µm]

 TIMA EDITIONS / THERMINIC 2005 ISBN 2-916187-01-4

ACKNOWLEDGEMENTS

This work has been partially supported by the project TEC2004-03289 and the Research Grants 2005FIR 00080 (AGAUR).


E B Rudnyi
email: rudnyi@imtek.de

L H Feng
email: lhfeng@fudan.edu.cn

M Salleras
email: msallera@el.ub.es

S Marco

J G Korvink
email: korvink@imtek.de

ERROR INDICATOR TO AUTOMATICALLY GENERATE DYNAMIC COMPACT PARAMETRIC THERMAL MODELS

During recent years, several groups have shown that parametric model reduction is possible in general. In particular, it has been shown that it allows us to generate compact thermal models while preserving film coefficients as parameters. Unfortunately, in order to run algorithms, a user should specify how many moments and what type to generate in advance and there were no formal rules to this end but a "trial and error" approach. We present an approach based on a local error in the transfer function and show that it can automate the process to build a dynamic compact parametric thermal model in much greater extent. We demonstrate that our algorithm can preserve three film coefficients for the first thermal model and material properties such as heat conductivity and heat capacity for the second model.

INTRODUCTION

Model reduction is a rapidly developing area of mathematics [START_REF] Antoulas | Approximation of large-scale dynamical systems: An overview[END_REF]. It allows us to take a high-dimensional finite element model developed at device level simulation and convert it efficiently into a low-dimensional approximation for system level simulation [START_REF] Rudnyi | Review: Automatic Model Reduction for Transient Simulation of MEMS-based Devices[END_REF]. Model reduction approaches have been successfully applied to a thermal problem to automatically generate a dynamics compact thermal model [START_REF] Bechtold | Automatic generation of compact electro-thermal models for semiconductor devices[END_REF][4] [START_REF] Codecasa | An Arnoldi based thermal network reduction method for electro-thermal analysis[END_REF][6] [START_REF] Palacín | Evolutionary algorithms for compact thermal modelling of microsystems: application to a micro-pyrotechnic actuator[END_REF].

However, in its original form model reduction does not allow us to preserve parameters in the system matrices that naturally arise in many applications. Fortunately, a new development, that is, parametric model reduction, allows us to overcome this limit.

In our knowledge, the first work on parametric model reduction has been presented by Weile et al [START_REF] Weile | A method for generating rational interpolant reduced order models of two-parameter linear systems[END_REF] in 1999 and applied to describe frequency depended surfaces in [START_REF] Weile | Analysis of frequency selective surfaces using two-parameter generalized rational Krylov modelorder reduction[END_REF]. This approach has been generalized from two to many parameters in [START_REF] Daniel | A Multiparameter Moment-Matching Model-Reduction Approach for Generating Geometrically Parameterized Interconnect Performance Models[END_REF] and in parallel re-discovered in [START_REF] Gunupudi | Analysis of transmission line circuits using multidimensional model reduction techniques[END_REF] [START_REF] Gunupudi | Passive parameterized time-domain macromodels for high-speed transmission-line networks[END_REF] [START_REF] Codecasa | A novel approach for generating boundary condition independent compact dynamic thermal networks of packages[END_REF]. We have suggested an empirical solution to a similar problem in [START_REF] Feng | Parametric Model Reduction to Generate Boundary Condition Independent Compact Thermal Model[END_REF] and an alternative algorithm in [START_REF] Feng | Preserving the film coefficient as a parameter in the compact thermal model for fast electro-thermal simulation[END_REF]. Note that different authors use different names for the same method: multiparameter model reduction in [START_REF] Daniel | A Multiparameter Moment-Matching Model-Reduction Approach for Generating Geometrically Parameterized Interconnect Performance Models[END_REF], multidimensional model reduction in [START_REF] Gunupudi | Analysis of transmission line circuits using multidimensional model reduction techniques[END_REF] [START_REF] Gunupudi | Passive parameterized time-domain macromodels for high-speed transmission-line networks[END_REF] and multivariate model reduction in [START_REF] Codecasa | A novel approach for generating boundary condition independent compact dynamic thermal networks of packages[END_REF]. Our choice in this respect is parametric model reduction as it allows us to preserve parameters in system matrices in the symbolic form.

In [START_REF] Codecasa | A novel approach for generating boundary condition independent compact dynamic thermal networks of packages[END_REF][14] [START_REF] Celo | Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Distributions in Electronic Components Using Multidimensional Model Reduction[END_REF], this approach has been successfully applied to a thermal problem when film coefficients have been preserved as symbols in a reduced model. Although these works have demonstrated that this is the right way to go, an important practical question remains unanswered. That is, how to choose moments to include into the reduced model. A straightforward approach to choose some order and then generate all the moments up to this order does not scale well with the number of parameters [START_REF] Daniel | A Multiparameter Moment-Matching Model-Reduction Approach for Generating Geometrically Parameterized Interconnect Performance Models[END_REF]. For example, if we choose to preserve four film coefficients then a reduced model made from all first derivatives has the dimension of 6, a reduced model made from all second derivatives has the dimension of 21, and a reduced model from all third derivatives already has the dimension of 56 (see Appendix F in [START_REF] Daniel | A Multiparameter Moment-Matching Model-Reduction Approach for Generating Geometrically Parameterized Interconnect Performance Models[END_REF]). At the same time, we may need derivatives of higher order than three to describe accurately transient behavior of the original model.

The explosion in the dimension of a reduced model is due to mixed moments (mixed derivatives). In [START_REF] Celo | Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Distributions in Electronic Components Using Multidimensional Model Reduction[END_REF] the authors have observed that one can actually ignore mixed moments in the case of a thermal problem and proved this by numerical simulation. However, even in this case it is unclear how to choose the number of moments along each parameter automatically. Although time in the form of the Laplace variable formally looks like the film coefficient in the transfer function, we may need more moments along the time axis. In [START_REF] Celo | Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Distributions in Electronic Components Using Multidimensional Model Reduction[END_REF] the authors have limited themselves The use of local error estimators has been researched in [START_REF] Bai | Error Estimation of The Pade Approximation of Transfer Functions via the Lanczos Process[END_REF] [START_REF] Bai | Error bound for reduced system model by Pade approximation via the Lanczos process[END_REF] (see also discussion in [START_REF] Rudnyi | Review: Automatic Model Reduction for Transient Simulation of MEMS-based Devices[END_REF]). Error indicators for Arnoldi-based model reduction have been suggested in [START_REF] Bechtold | Error indicators for fully automatic extraction of heat-transfer macromodels for MEMS[END_REF]. In the present paper, we use these results as inspiration for a heuristic procedure suited for parametric model reduction. We suggest an approach that controls the dimension of the reduced model automatically based on local error control. We apply the approach to two thermal models and report our numerical observations. First is a thermal model of a microthruster unit [START_REF] Rudnyi | Boundary Condition Independent Thermal Model[END_REF] (see also [START_REF] Feng | Parametric Model Reduction to Generate Boundary Condition Independent Compact Thermal Model[END_REF] [START_REF] Feng | Preserving the film coefficient as a parameter in the compact thermal model for fast electro-thermal simulation[END_REF]) where the goal is to preserve three film coefficients. Second is a thermopile based IR detector [START_REF] Salleras | A methodology to extract dynamic thermal compact models under time-varying boundary conditions: Application to a thermopile based IR sensor[END_REF] when a compact thermal model should preserves material properties of the gas in the symbolic form.

OVERVIEW OF PARAMETRIC MODEL REDUCTION

Let us briefly review the application of parametric model reduction to a thermal problem. The discretization in space by the finite element/volume/difference method of the heat transfer equation leads to a system of ordinary differential equations as follows

€ E + q i E i i ∑ ( ) dT (t) dt + K + p i K i i ∑ ( ) T (t) = Bu(t) y(t) = CT (t) , (1)
where € T (t) is the vector of unknown temperatures at the nodes.

€ E and

€

K are the heat capacity and heat conductivity system matrices, € B is the input matrix, and € C is the output matrix. The vector € u comprises input functions such as heat sources. The output matrix specifies particular linear combinations of temperatures that of interest to an engineer. Our goal is to preserve the parameters € q i and € p i in the symbolic form in the reduced model (a film coefficient or material property). A parameter contributes to the global system matrix by means of the matrix

€ E i or € K i .
The transfer function of (1) can be expressed as follows

€ H (s) = C{s(E + q i E i i ∑ ) + K + p i K i i ∑ )} -1 B , (2)
and in addition to the Laplace variable s it contains the parameters € q i and € p i . Model reduction is based on an assumption that there exists a low-dimensional subspace € V that accurately enough captures the dynamics of the state vector

€ T (t) : € T ≈ Vz .
(3) In order to find such a subspace € V that does not depend on parameters to preserve, the transfer function (2) can be treated as a function in many variables ( € s , € q i and € p i ) and one can perform its multivariate expansion. Then € V is taken as a subspace that spans multivariate moments of (2) (see [START_REF] Daniel | A Multiparameter Moment-Matching Model-Reduction Approach for Generating Geometrically Parameterized Interconnect Performance Models[END_REF]- [START_REF] Celo | Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Distributions in Electronic Components Using Multidimensional Model Reduction[END_REF]). This way, € V does not depend on parameters in (1) and [START_REF] Rudnyi | Review: Automatic Model Reduction for Transient Simulation of MEMS-based Devices[END_REF].

Provided € V is known, one obtain a low-dimensional model by projecting (2) on € V as follows € {V T EV + q i V T E i V i ∑ } dz(t) dt + {V T KV + p i V T K i V i ∑ }z(t) = V T Bu(t) . (4)
Eq (4) preserves the original parameters in the symbolic form and as a result we refer to this approach as parametric model reduction.

LOCAL ERROR CONTROL

We have limited ourselves to the Single-Input-Single-Output case when the transfer function ( 2) is a scalar, the input matrix € B is a vector and the output matrix € C is a single row. Another simplification is that we ignore mixed moments following the observation in [START_REF] Celo | Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Distributions in Electronic Components Using Multidimensional Model Reduction[END_REF]. As a result, the model reduction algorithm is practically equivalent to that described in [START_REF] Celo | Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Distributions in Electronic Components Using Multidimensional Model Reduction[END_REF] except that we take into consideration the Laplace variable as well.

We assume that a user specifies the range of interest for the frequency and parameters:

€ s min < s < s max q i,min < q i < q i,max p i,min < p i < p i,max , (5)
Additionally a user chooses expansion points for the Laplace variable and parameters. In our work, we take the expansion point for the Laplace variable as zero because this allows us to preserve the stationary state. Finally, a user also specifies the error

€ ε for the maximum frequency of interest € f max ( € s max = i2πf max ).
In our experience, 1% error for 100 Hz corresponds to reasonably accurate approximation in the time domain although this may depend on the frequency spectrum of the input function.

Our main idea is to choose the number of vectors in the Krylov subspaces in such a way that the difference between the transfer functions of the original and reduced models at the maximum frequency is below of the specified level for the allowable range of parameters as follows

€ H (s max ,q i , p i ) -H reduced (s max ,q i , p i ) < ε , (6)
We present numerical results in the next two sections.

CASE STUDY I: PRESERVING FILM COEFFICIENTS

We have used the thermal problem from [13][14]. It is described in [START_REF] Rudnyi | Boundary Condition Independent Thermal Model[END_REF] and available on-line in the Matrix Market format [START_REF] Boisvert | The matrix market exchange formats: Initial design[END_REF] at http://www.imtek.uni-freiburg.de/simulation/benchmark. Fig. 1 shows the device. The heat is generated by a heater and propagates through the device to three boundaries (top, side, bottom). Each boundary has its own film coefficient and the goal is to preserve them in the symbolic form. As a result, Eq (1) is written as )

) ( ) ( ) ( ) ( ) ( t CT t y t Bu t T K h K h K h K dt t dT E b b s s t t = = + + + + , ( 7
)
where t h , s h and b h are the film coefficients at the top, side and bottom respectively (they replace i p in Eq 1). The dimension of the full model is 4257.

We have chosen the same expansion point for all film coefficients as 10 0 , = i h and the same maximum value of 6 10 . The maximum frequency was chosen as 100 Hz and required accuracy at this frequency is 1%. It is worthy of noting that when we have changed the order to generate subspaces to s , b h , s h and t h , the final result was the same although the convergence history became different (see Fig. 3). In this case, it happened that generated along the Laplace variable reached the convergence limit not only in Simulation results for the reduced model of dimension 41 and the original model of dimension 4257 are shown in Table 1. For 27 cases of different values of film coefficients, we present the stationary temperature at the heater, the error in the stationary state made by the reduced model and the error in the transient step response as compared with the original model. The error for transient response was estimated as follows:

€ error = [ (T i -ˆ T i ) 2 ] 1/ 2 i=1 n ∑ /[ T i 2 ] i=1 n ∑ (8)
where ) , , ( 1. The difference is very small and comparable to the line thickness.

CASE STUDY II: PRESERVING MATERIAL PROPERTIES

A thermopile based IR detector can be fabricated with CMOS compatible micromachining processes [START_REF] Salleras | A methodology to extract dynamic thermal compact models under time-varying boundary conditions: Application to a thermopile based IR sensor[END_REF] (see Fig. 7). The sensor is formed by a silicon wafer with a thermally isolated membrane that contains the thermocouples hot junction. The cold junctions are placed in the opposite side of the membrane, over the silicon bulk, to assure a maximum thermal isolation with respect to the hot junctions. A silicon absorber is located in the center of the membrane with the thermocouples hot junctions. When the absorber is heated up, a temperature difference appears between the hot and cold junctions. Due to the Seebeck effect this temperature difference produces a voltage difference that is the output signal of the sensor. For calibration or test purposes, is also placed above the absorber with the corresponding electrical contacts. Due to the thermal isolation the main thermal flux from the hot junctions is to the surrounding gas. Moreover, the output signal of the device is quite sensitive to the thermal properties of this gas. This opens new opportunities for its use to detect different gases.

The sensor operation can be modeled by a thermal model however the gas material properties change and they should be preserved in the symbolic form. In other words, Eq (1) becomes

( ) ( ) ) ( ) ( ) ( ) ( ) ( t CT t y t Bu t T K K dt t dT cE E c = = + + + κ κ , (9)
where there are two gas-specific parameters: the heat conductivity κ and the heat capacity per unit volume c . The thermal sensor model in the form of Eq (9) has been made in ANSYS and it had dimension of 2870. The goal of model reduction was to find a low-dimensional approximation and at the same time to preserve κ and c . We have chosen required range of the heat conductivity and heat capacity to cover air, nitrogen, neon, argon, krypton, and xenon. Parametric model reduction in this case happened to be easier as the range of parameter values is much more narrow than in the previous case. We needed to generate 10 vectors along the Laplace variable and then only one vector along each parameter. Thus, the dimension of the reduced system was equal 12.

Simulation results for the reduced model of dimension 12 and the original model of dimension 2870 are shown in Table 2. For six gases, we present the stationary temperature at the hot and cold junction, the error in the stationary state made by the reduced model and the error in the transient step response as compared with the original model. Fig. 8 and9 show the step response of the full scale (red) and reduced models (green) for the nitrogen: the difference is close to the line thickness.

CONCLUSION

In our view, there are two main results of our study. 1) Mixed moments seem to be unnecessary indeed in agreement with [START_REF] Gunupudi | Analysis of transmission line circuits using multidimensional model reduction techniques[END_REF][11] [START_REF] Celo | Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Distributions in Electronic Components Using Multidimensional Model Reduction[END_REF]. 2) The local error control allows us to choose the right number of moments in order to give good approximation properties of the reduced model.

Unfortunately, at present it is hard to say how general these results are. No doubts, it is necessary to try more different thermal models to gain more experience.

  E. B. Rudnyi, L. H. Feng, M. Salleras, S. Marco, J. G. Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models

(

Fig. 1 .Fig. 2 .

 12 Fig. 1. A 2D-axisymmetrical model of the micro-thruster unit (not scaled). The axis of the symmetry on the left side. A heater is shown by a red spot. As the mixed moments have been neglected, it was necessary to generate four subspaces along the Laplace variable and the three film coefficients. The first subspace has been made along the Laplace variable. We have used the value o f t h e transfer function at ] 10 , 10 , 10 , 100 [ 0 , 0 , 0 , max = = = = b s t h h h s H to keep the local error below It was necessary to generate 28 vectors to reach desired accuracy. The next subspace has been generated along t h and the value of the transfer function at ] 10 , 10 , 10 , 100 [ 0 , 0 , 6 max = = = = b s t h h h s H has been used for the local error control. It took 13 vectors to reach the convergence. At this point, it happened that the two next subspaces along s h and b h were unnecessary as t h e c o n v e r g e n c e i n r e s p e c t t o ] 10 , 10 , 10 , 100 [ 0 , 6 6 max = = = = b s t h h h s H a n d 10 , 10 , 10 , 100 [ 6 6 6 max = = = = b s t h h h s H has been reached simultaneously while generating vectors for the

  along t h only and the final dimension of the reduced model was again 41.

Fig. 3 .

 3 Fig. 3. Convergence history when the order to generate subspaces was s , b h , s h and t h . Different markers show the error at different values of the transfer function ] , , , 100 [ max b s t h h h s H = , where the values of the film coefficients shown near to the marker.

  solution of the reduced model[START_REF] Codecasa | Compact modeling of electrical devices for electrothermal analysis[END_REF]. Fig. 4 to 6 show the transient response of the original model (red) and reduced model (green) for the three different cases from Table

Fig. 4 .Fig. 5 .

 45 Fig. 4. The transient response for the step input function: temperature vs. log10[time] for the case when 1 = t h , 1 = s h and 1 = b h.

Fig. 6 .

 6 Fig. 6. The transient response for the step input function: temperature vs. log10[time] for the case when 10000 = t h , 10000 = s h 10000 b h .

Fig. 7 .

 7 Fig. 7. Micromachined thermopile based IR detector.

Fig. 8 .

 8 Fig. 8. The transient response for the step input function: temperature vs. log10[time] for the hot junction in the case of nitrogen.

Fig. 9 .

 9 Fig. 9. The transient response for the step input function: temperature vs. log10[time] for the cold junction in the case of nitrogen.

  E. B. Rudnyi, L. H. Feng, M. Salleras, S. Marco, J. G. Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models to a stationary problem and have not researched this problem further.

Table 1 .

 1 E. B. Rudnyi, L. H. Feng, M. Salleras, S. Marco, J. G. Korvink Error Indicator to Automatically Generate Dynamic Compact Parametric Thermal Models Simulation results for the reduced model as compared with the original model.

	top h	side h	bottom h	Station-ary solution	Error (%) in stationary	Error (%) in transient
	1	1	1 832.	0.11	0.47
	1	1	100 85.8	0.0033	0.21
		1 10000 39.2	0.21	0.24
	1	100	1 50.0	0.044	0.15
	1	100	100 47.8	0.031	0.15
	1	100 10000 39.1	0.19	0.22
	1 10000	1 38.3	0.066	0.17
	1 10000	100 38.3	0.066	0.17
	1 10000 10000 38.3	0.068	0.17
	100	1	1 73.4	0.0031	0.20
	100	1	100 55.4 0.00089	0.17
	100	1 10000 36.8	0.17	0.21
	100	100	1 43.6	0.027	0.15
	100	100	100 42.4	0.020	0.15
	100	100 10000 36.7	0.16	0.21
	100 10000	1 36.0	0.056	0.17
	100 10000	100 36.0	0.056	0.17
	100 10000 10000 36.0	0.058	0.17
	10000	1	1 7.56 0.000008	0.18
	10000	1	100 7.56 0.000011	0.18
	10000	1 10000 7.56 0.00016	0.18
	10000	100		7.56 0.000007	0.18
	10000	100	100 7.56 0.000003	0.18
	10000	100 10000 7.56 0.00016	0.18
	10000 10000	1 7.56 0.00068	0.18
	10000 10000	100 7.56 0.00068	0.18
	10000 10000 10000 7.56 0.00067	0.18

Table 1 .

 1 Simulation results for the reduced model as compared with the original model. . B. Rudnyi, L. H. Feng, M. Salleras, S. Marco, J. G. Korvink Error Indicator to Generate Dynamic Compact Parametric Thermal Models

	Gas Junction Stationary solution	Error (%) in stationary	Error (%) in transient
	air	hot 0.00925	0.016	0.82
		cold 0.000014	0.52	1.23
	nittrogen	hot 0.00933	0.015	0.83
		cold 0.000014	0.49	1.19
	neon	hot 0.00706	0.083	0.78
		cold 0.000012	2.56	3.69
	argon	hot 0.0105	0.0038	0.84
		cold 0.000015	0.12	0.88
	krypton	hot 0.0122	0.000021	0.86
		cold 0.000017	0.00068	0.74
	xenon	hot 0.0131	0.0013	0.87
		cold 0.000017	0.040	0.79

E

 TIMA EDITIONS / THERMINIC 2005 ISBN 2-916187-01-4

ACKNOWLEDGEMENTS

IMTEK acknowledges partial support by the German ministry for science and education (BMBF) for funding in the framework of the project SIMOD and an operating grant of the Freiburg University. LHF's research is supported partly by NSFC research project 90307017, 60176017, 90207002 of China, partly by Synopsys Inc., partly by Cross-Century Outstanding Schoolar's fund of Ministry of Education of China, partly by National 863 plan projects 2004AA1Z1050 of China, Science & Technology key project of Ministry of Education of China 02095, partly by NSF grants CCR-0098275 and CCR-0306298 of China and partly by fund of Alfried Krupp von Bohlen und Halbach-Stiftung of Germany.


Ryusuke Egawa
email: egawa@archi.is.tohoku.ac.jp

Mutsuo Ito

Naoyuki Hasegawa

Ken-Ichi Suzuki
email: suzuki@archi.is.tohoku.ac.jp

Tadao Nakamura
email: nakamura@archi.is.tohoku.ac.jp

TEMPERATURE GRADIENT ALLEVIATING METHODS FOR ARITHMETIC UNITS

Recently, thermal-aware digital circuit design in advanced technologies is great challenges to realize high-speed and robust microprocessors. In this paper, we explore temperature gradient alleviating method for arithmetic units. Aiming at alleviating temperature gradients at logical circuit design level, we try to flatten out a power density by applying delay-balancing technique for equaldelay circuits. Our proposal is evaluated in fine grain thermal simulation. Simulation results show the strong dependency between placement and temperature gradients on arithmetic units. .

INTRODUCTION

Computer architects and circuit designers are continually pushing the envelope in the race to design faster, powerful microprocessors. Technology scaling to advanced technologies brings higher performance and higher levels of on-chip functional integration. However, this scaling has brought with it a variety of exacerbated issues, such as higher current and power densities, increased leakage current, low-k dielectrics with poorer heat conductivity, and package and heat sink design challenges. In other words, the rapid increase in speed and complexity of recent microprocessors is outstripping the benefit of feature size scaling and supply voltage reduction. Furthermore the power density has doubled every three years in recent microprocessors. As a result, the temperature of the microprocessor increases rapidly, and high temperature causes speed degradation of transistors and increase in cooling cost. Consequently, thermal aware design will play the key role in future VLSI design as well as power conscious design [START_REF] Banerjee | Analysis of Optimization of Thermal Issues in High-Performance VLSI[END_REF]. The "hot spot", the area where a temperature is locally high, generates a large temperature gradient as for not only microprocessors but also functional blocks, and deteriorates the robustness or reliability of the microprocessors in DSM (Deep Sub-Micron era) [START_REF] Stan | HotSpot: A Dynamic Compact Thermal Model at the Processor-Architecture Level[END_REF]. [START_REF] Cheng | ILLIADS-T, An Electrothermal Timing Simulator for Temperature-Sensitive Reliability Diagnosis of CMOS VLSI Chips[END_REF] reported that there is about nine degree temperature difference even in a 10-bit negative adder. Based on the above facts, in advanced CMOS technologies, an early accurate design estimation including deep submicron effects is strongly required.

Aiming to clarify the thermal behavior on VLSI, and to design thermal robust microprocessors in DSM, many researchers have studied thermal simulation methods by various approaches. The simulator proposed in [START_REF] Stan | HotSpot: A Dynamic Compact Thermal Model at the Processor-Architecture Level[END_REF], "hotspot", is based on instruction level and functional unit analysis. On the other hand, simulators, "ILLIADS-T" [START_REF] Cheng | ILLIADS-T, An Electrothermal Timing Simulator for Temperature-Sensitive Reliability Diagnosis of CMOS VLSI Chips[END_REF] and "THERMAN" [START_REF] Szekely | Electro-Thermal and Logi-Thermal Simulations of VLSI Designs[END_REF], proposed finer grain thermal simulations based on the switching of transistors and logic gates.

However, they employ steady-state temperature analysis in temporal granularity for the reason that the time required for the on chip temperature to reach its steady-state is several order of magnitude longer the clock signal period in digital circuits. These approaches are fine enough for evaluating rough thermal behavior of large-scale integrated circuits. But, to examine temperature behavior in a functional unit, more detailed or fine temporal granularity is needed. [START_REF] Ito | Simulating Fine-Grain Thermal Behaviors on VLSIs[END_REF] proposed finer grain thermal simulation to evaluate detailed inside thermal behavior of functional units. it use a logic cell as a heat source, and evaluate the temperature at every clock cycle level.

As mentioned above, thermal simulation methods are studied well in late years.

However, thermal aware digital circuit design methodologies have not been so studied well compared with thermal simulation methodologies. Recently the temperature-aware design flow has been proposed [START_REF] Huang | Compact Thermal Modeling for Temperature-Aware Design[END_REF]. It insists on the ability of estimating temperature at different granularities and at different design stages, especially early in the design flow.

The estimated temperature at each granularity and each stage can help to design high speed and thermal robust circuit. All the decisions should use temperature as a guideline and the design should be intrinsically thermally optimized and free from thermal limitations. They have a high potential to contribute to shorten the turn-around time of circuit design in deep submicron technologies.

Based on the fact, we study a technique to make a temperature gradient smaller in high-speed arithmetic units for the purpose of designing thermal robust high speed circuits. As mentioned above, a thermal gradient deteriorates reliability of arithmetic units. We concentrate to alleviate temperature gradients inside of an arithmetic unit, because a local temperature gradient influences the performance of an arithmetic unit rather than global high temperature due to the improvement of recent cooling techniques [1][4]. Thus, we focus on the adverse effect of temperature gradient in a functional block, and try to flatten out it to realize thermally robust and reliable arithmetic units in DSM.

The rest of the paper is organized as follows. In section 2, we show our basic strategies of alleviating temperature gradient method. Section 3 describes the details of our proposal method, especially we logic depth alleviating technique and logical effort theory. In section , we show some experimental results and discussion of the possibility of temperature-aware design at logical circuit design level. Finally, Section 5 concludes this paper.

BASIC STRATEGIES

Thermal behavior (or profile) strongly depends on the power density profiles. Correspondingly, power density correlates closely with switching activity and the total number of switchings in a whole circuit. Thus, a simple way to alleviate the temperature gradient in a circuit is alleviating the power density. Also, alleviating the power density can be achieved by flattening out switching activities or the number of switchings [START_REF] Marculescu | Logic level power estimation considering spatiotemporal correlations[END_REF][14]. Our approach is basically based on this way. However, controlling switching activities for alleviating temperature gradient are difficult due to its strong dependency on Figure1. Number of switching on paths. applications, or sequences of input vectors. Therefore, it is difficult to design a logic circuit with alleviating the temperature gradient and power density with universal status. And also, usually arithmetic unit design for microprocessors does not carry on with in the light of its applications.

Under these situations, to achieve temperature gradients alleviating at logic circuit design level, we focus on the number of switchings on a path. Upper portion of Figure1 shows number of switchings on all paths in a combinational logic circuit. In this figure, vertical axis indicates the number of switchings on a path, and horizontal axis indicates the paths. In this case, we assume the combinational logic circuits have n paths. As like this figure, respective paths have diverse number of switchings and this can be a trigger of generating thermal gradient in a combinational logic circuit. Thus, as the first step of our strategy, we try to alleviate the number of switchings of all paths of arithmetic units.

To alleviate the number of switchings we employ delay-balancing technique. Delay-balancing techniques are popular techniques to design equal delay circuits for wave pipeline, asynchronous circuit and data-flow architecture [START_REF] Burleson | Wave-Pipelining: A Tutorial and Research Survey[END_REF], [START_REF] Klass | Balancing Circuits for Wave Pipelining[END_REF], [START_REF] Nowka | System design using wavepipelining: CMOS VLSI vector unit[END_REF]. As implied by the name, the delay from all inputs to all outputs of a combinational logic circuit are designed nearly the same [START_REF] Sutherland | Logical Effort: Designing Fast CMOS Circuit[END_REF]. In addition, though it depends on input datum, the paths of an equal delay circuit designed by delay element insertion (which is a kind of delay balancing technique) have almost same numbers of switchings, because the all signals go through almost the same number of logic gates. Accordingly, the number of switchings on each path for any input pattern can be made smooth by designing equal delay circuit. Lower portion of Figure1 shows numbers of switching on paths after delay balancing. Shaded cuboids denote the number of switching by inserted delay element.

As a result of delay balancing by delay elements insertion, we assume the power density profile will be improved as Figure 2 This figure shows basic concepts of our strategy. Though, we can look delay elements with high numbers of switching in Figure 2 (b) and they contribute to alleviate power density of the circuit. Thus, from the viewpoint of power density and temperature gradients, equal delay circuits are very effective in and suitable for temperature-aware circuit design.

It is well known that the placement of the cells has a strong influence on the thermal profile. [START_REF] Tsai | Cell-Level Placement for Improving Substrate Thermal Distribution[END_REF] has clarified the strong relationship between thermal profile and cell placement and proposed thermal aware cell placement to minimize the temperature. However, we are aiming at finding chances of temperature aware design at logic circuit design phase, not in physical design phase (cell placement). Thus, we just concentrate in logical circuit design level.

Also, increasing cells causes an increase of the total power consumption of circuit. However, we just pay attention most in the high-speed microprocessors design that uses CMOS technology in the near future is in a local temperature gradient in a minute area. The detail of these topics is discussed in section 4 with experimental results.

DELAY BALANCING FOR TEMPERATURE ALLEVIATING

Proposed Delay Balancing Methods

So far, many researchers have been proposed delay balancing techniques to design equal delay circuits aiming at realizing asynchronous circuits, data flow systems and wave-pipelined circuits [START_REF] Burleson | Wave-Pipelining: A Tutorial and Research Survey[END_REF], [START_REF] Klass | Balancing Circuits for Wave Pipelining[END_REF], [START_REF] Nowka | System design using wavepipelining: CMOS VLSI vector unit[END_REF]. However, almost all the delay-balancing techniques are time-consuming due to its heuristic approach, and can't fill up the gap between the logical design phase and physical design phase of VLSI design. To overcome these problems, we propose delay-balancing algorithms with delay elements insertion and modified "Logical Effort" theory that based on gain based delay model. Figure 3 shows a whole flow of delay balancing.

Figure 3. Delay balancing methods.

In delay balancing flow, firstly we select an appropriate arithmetic algorithm for equal delay circuits considering the trade off between delay and area, and then we apply delay elements insertion. Gate sizing for all elements are carried on after delay elements insertion. The details of delay elements insertion and gate sizing technique are described in the following subsections.

Delay Elements Insertion

Delay elements insertion methods described in Figure 3 are shown in Figure 4. In this procedure, 'level' means logic length of the circuit. The 1st step of this procedure is searching for a critical path of the circuit. In the 2nd step, we levelize the logic gates in the circuit [START_REF] Klass | Balancing Circuits for Wave Pipelining[END_REF]. After the 2nd step, we can find out traverse nets. A net is defined as wire form the output of a logic gate to the input of the next logic gate. Each traverse net is defined as a net traversing level of one or more. Figure 5 shows an example of traverse nets. Then we insert delay elements onto traverse nets to equalize the all paths' delays. This process makes logic depth and delay almost been same. When inserting delay elements, we refer to the critical path delay.

Gate Sizing

In gate sizing procedure, we employ Logical Effort (LE) based gain-based delay model due to its simplicity and accurate delay estimation [START_REF] Vojin | Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders[END_REF]. LE refers to the inherent effort of computation in logic gates, and is a characterization of the complexity of a logic gate. It provides a method to estimate delay of a CMOS circuit, and develops a scheme for sizing the transistors by back of the envelope calculations. LE employs gain-based delay model that has higher accuracy to estimate delay time than commonly use wire load model. We will briefly describe some of the main features of LE in this subsection. The detail of LE can be obtained from [START_REF] Sutherland | Logical Effort: Designing Fast CMOS Circuit[END_REF].

LE takes into account the fact that the speed of a digital circuit block is dependent on its fan-out (C out ) and fan-in (C in ). Further, LE introduces technology independence by normalizing the speed by that of a minimal size inverter:

d abs = d ( 1 )
. where d abs = absolute delay, d = unitless delay, = delay of an inverter driving an identical inverter with no parasitics. The delay expression of a logic block in LE is given as:

d = f + p ( 2 )
. Where p = parasitic delay, f = effort or stage delay. Further f = gh where g is defined as logical effort and h is electrical effort. Electrical effort h is equal to the ratio of input capacitance and output capacitance : h = C in /C out . Thus: d = gh + p (3). The most important feature of LE is that it provides a way of determining appropriate transistor sizing of the critical path to minimize the delay. Optimizing the design of an N-stage logic network proceeds from a very simple principle: The path delay is least when each stage in the path bears the same stage effort. In this case, each stage bears equal effort given as:

ˆ f = g i h i = F 1 N ( 4
). In such a case, delay of the path will be equal to:

D = N ˆ f + P ( 5 ) .
where, D = the path delay, F=the path effort, P = the path parasitic delay. In order to obtain optimal transistor sizes to realize minimal delay, gate sizing process should be started from the output and calculate C in for each stage, which is determined by each stage effort. Some modification of LE is required to achieve equal delay circuit design, since the optimization of LE theory aims at achieving minimum delay for fast circuits. In order to achieve delay balancing, not the equal effort per stage but the equal delay time is set at each logic stage (or level). The delay time per stage is decided referring to the largest stage delay of all stages. Gate sizing procedure is shown in Figure 6.

Actually, this approach causes an increase in critical path delay and circuit area. However, as mentioned before, our proposal is designing equal delay circuit for alleviating temperature gradient. And an equal delay circuit potentially operated extremely high clock frequency as a wave-pipelined circuit. And also, while hold time restriction of registers becomes severe in recent years, equal delay circuits contribute to robust circuit operation. Figure 6. Gate sizing.

SIMULATION AND EXEPERIMENTAL RESULTS

Simulation Conditions

To evaluate our proposal, we designed three kinds of 4-bit adder: Ripple Carry Adder(RCA), Carry Lookahead Adder(CLA), Binary tree adder(BTA). Each adder is consisted of only 2-input NAND gates and designed in ROHM 0.35μmCMOS technology. Also we use Synopsys Design Compiler and Scirocco for logic circuit design and its simulation, Apollo and Milkyway for physical design. Continuously, we apply delay-balancing method for each circuit. Actually we insert delay elements by using Synopsys Design Compiler, after finding out traverse nets. Then we give timing constraints for all traverse nets to insert buffers for logic synthesis. We also take care not to change original circuit organization by using "don't touch constraint" on all gates in the original circuit. Pairs of inverters are used as delay elements, because a pair of inverters has wider delay flexibility than that of buffers in EXD cell library. To reenact the gate sizing under the restriction of cell based design that uses cell library given by vendors, we take a similar approach to [START_REF]Gain-based Synthsis: Speeding RTL to Silicon[END_REF], which selects a similar size logic gate to be sized logic gate, from cell library. We simulate these circuits using the thermal simulator described in the next subsection. Simulations are carried out on 100MHz operation, using all 256 pattern input vectors with random sequences and under the same physical condition with [START_REF] Ito | Simulating Fine-Grain Thermal Behaviors on VLSIs[END_REF].

Fine Grain Thermal Simulator

Here we describe fine grain thermal simulator [START_REF] Ito | Simulating Fine-Grain Thermal Behaviors on VLSIs[END_REF] that we have used in this experiment. Figure 7 shows an outline of our thermal simulator. In this simulation, we use standard cell design method for target chips. Therefore we can simply regard cells, which are provided as standard cells by CAD vendors, as logic gates. Then switching information is obtained in the phase of logical simulation, and geometrical information in the phase of placement & routing(P&R) respectively during implementing the target chip. During the logical simulation, we make the toggle counting file for given input vectors. And the switching information file has the power of each cell obtained by the CAD tool. After the placement and routing phase, we obtain the places and surface areas of the heat sources.

Experimental Results

This section shows experimental results of our proposed method. Table .1 shows specification of simulated circuit. The number of cells of each adder increases by 2.6-3.1 times. The delay adjustment reduces the delay variation in 10%. Figure 8 shows power density profiles of CLA. We can see the increase of power density by delay elements. Figure 9 shows a temperature profile of CLAs. The area of this figure is normalized by computational area.

Discussions

Though average switchings of the paths increased and the delay balancing worked well, temperature gradients enlarged by our proposal. From these results, we can say temperature profile strongly depends on cell placement.

In our experiments, we employ an automatic cell placement tool. However, in order to flatten out the temperature gradient, we should explore how the proposal can contribute to temperature aware cell placement. we can say, large number of redundant switchings by delay element expands the way to select of temperature aware placement. Also, more detailed evaluations of our proposal are needed. First, it is necessary to examine the comparison condition. The original circuit and the balanced circuit have different area, though we simulate them with same computational area and boundary condition.

The difference of circuit areas will influence temperature gradient. Thus after the relation between the space and temperature gradient is clarified. Second, equal delay circuit have a potential to operate high clock frequency, as a wave pipelined circuit. A simulation under pipeline operation with high clock frequency will show different results, especially in terms of performance base evaluations. Finally, we should consider the trade off between power consumption increase and temperature gradient reduction.

CONCLUSIONS

In this paper, aiming at alleviating the temperature gradient in arithmetic units, we have proposed a delay balancing method with logical effort methodology. And also we have explored temperature aware design at logic circuit design level. We have simulated our proposal by using fine grain thermal simulator and the simulation results indicated the strong dependency between placement and temperature gradients on arithmetic units, which also shows us their potential for temperature aware design at logical circuit design level.

Figure 2 .

 2 Figure 2. Power density profiles: (a) original circuit, (b) delay balanced circuit.

  Figure 2 shows power density aspects of an arithmetic unit designed by cell-based design. In this figure, Figure 2 (a) shows power density of the original circuit and Figure 2 (b) shows power density of the delay balanced circuit. White cuboids denote the number of switchings of original cells (given circuit), and shaded cuboids denote the number of switchings of inserted delay elements. Actually, the circuit size or the number of cells is increased by delay element insertion in Figure 2 (b).

Figure 4 .

 4 Figure 4. Delay elements insertion.

Figure 5 .

 5 Figure 5. Traverse net.

Figure 7 .

 7 Figure 7. Thermal Simulator.

Figure 9 .

 9 Figure 9. Temperature profiles of CLA.

Table 1 .

 1 Specifications of evaluated adders.

 TIMA EDITIONS / THERMINIC 2005 ISBN 2-916187-01-4

ACKNOWLEDGEMENTS

This work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Grant-in-Aid for Scientific Research(KAKENHI)(B) #17700044.