Matthew A Hawkins

Researching and marketing to consumption collectives

Consumer researchers have identified a handful of consumption collectives, such as consumption tribes, brand communities, and communities of practice. A consumption collective is a group of consumers who share consumption characteristics. Despite the use of participant screens in other research domains, published consumption collective research rarely reports on participant screens demonstrating their participants are actual members of the specific collective under investigation. Without participant screens researchers may mistakenly attribute conflicts over heterogeneous resources to intra-collective competition when the source may be inter-collective competition. This research demonstrates that consumer researchers can implement a short survey during field interviews as a participant screen. The article concludes by suggesting that marketing strategies and branding messages should be adjusted according to the individual consumer's consumption collective membership status.

Introduction

Consumer researchers have identified a handful of consumption collectives, such as consumption tribes [START_REF] Cova | Community and consumption: towards a definition of the "linking value" of product or services[END_REF], brand communities [START_REF] Muñiz | Brand community[END_REF], and communities of practice [START_REF] Leigh | The consumer quest for authenticity: the multiplicity of meanings within the MG subculture of consumption[END_REF]. A consumption collective is an umbrella term applied to a group of consumers "who share a commitment to a product class, brand, activity, or consumption ideology" [START_REF] Thomas | When differences unite: resource dependence in heterogeneous consumption communities[END_REF](Thomas et al. : 1012)). Extant studies typically focus on understanding how specific collectives form [START_REF] Mcalexander | Building brand community[END_REF] and how being a member of a collective impacts consumers' meaning-making processes [START_REF] Kates | The protean quality of subcultural consumption: an ethnographic account of gay consumers[END_REF]. While understanding that multiple consumption collectives exist researchers rarely conduct and report participant screens demonstrating their participants are actual members of the specific collective under investigation. This is surprising as participant screens are commonly implemented in other research domains and in the consulting and private realms. Participant screens are questions directed to the interviewee to ensure they meet the requirements to be included in the study. The lack of participant screens is problematic as researchers are beginning to argue that despite sharing consumption patterns, consumers' divergent goals and use of heterogeneous resources create tensions that impact intra-collective relationships [START_REF] Leigh | The consumer quest for authenticity: the multiplicity of meanings within the MG subculture of consumption[END_REF][START_REF] Thomas | When differences unite: resource dependence in heterogeneous consumption communities[END_REF].

Without participant screens researchers may mistakenly attribute conflicts over heterogeneous resources to intra-collective competition when the source may be inter-collective competition.

For marketers, understanding whether a group of consumers are a consumption collective can help in determining what type of marketing strategy to implement. This is because members of a consumption collective are interested in the meaning-making process surrounding the brand and the activities it is used within. Conversely, non-members tend to have transactional relationships with the brand. Thus, implementing community marketing strategies with nonmembers may waste resources and instead community strategies should target collective members.

Accordingly, this research has two goals (1) to demonstrate that consumption collective researchers can implement a short field survey as a participant screen and (2) to propose that marketers adjust their marketing strategies and branding messages according to the consumer's consumption collective membership status. A motorcycle rally serves as the empirical setting for discussing the practicality of implementing participant screens. This four-day event is an ideal setting as it routinely attracts over a quarter-million visitors [START_REF] Stigar | Fayetteville braces for Bikes, Blues & BBQ: more than 250,000 visitors expected at festival[END_REF] or potential consumption collectives members. This research makes multiple contributions. Methodologically, it affirms that consumer researchers can implement participant screens in the field to demonstrate participants are part of the specific collective under investigation. Future research can take advantage of implementing participant screens longitudinally to explore how membership status transforms through time.

Managerially, it is argued that marketers should implement transactional marketing strategies to consumers not involved in a collective while community marketing strategies are more appropriate for consumers who are members of a collective.

Site: Bikes, Blues & BBQ

The Bikes, Blues & BBQ (BBB) motorcycle rally held in Fayetteville, Arkansas served as the empirical setting. This geo-temporal event was purposely selected because this event is not supported by a brand, such as in brand fests [START_REF] Mcalexander | Building brand community[END_REF]. In fact, substantial diversity in the types of businesses and brands participating in the event was evident. Ample space was dedicated to motorcycle manufacturers, customizers, part suppliers, and even a test riding course; and, there were numerous food and craft vendors, local community organizations, beer gardens, and a music stage. Additionally, the event is embraced by both the city and the community and is free of charge. Because BBB attracts a wide range of consumers interested in motorcycles more generally it is an ideal site to interact with potential members of brand communities, consumption tribes, and communities of practice.

In fact, some attendees had limited interest in motorcycles rather they attended the event to execute transactions in the temporary marketplace. For example, one young couple interviewed on Saturday night came to purchase pulled-pork sandwiches from an award winning vendor they heard about on the internet and to look at the bikes. Accordingly, a portion of the attendees never became community members as they lacked a "sense of duty or obligation to the community as a whole, and to its members" (Muñiz & O'Guinn 2001: 413). In essence, some consumers interacted with the event as a stable entity and were unaware of or uninterested in the social status games being played by the various consumption collectives present at the event.

Methods: field research

The field research included conducting formal (n = 12) and informal (n = 15) interviews with BBB attendees. The formal interviews involved following a semi-structured interview protocol and providing a short self-administered survey which served as the participant screen (see Appendix). The formal interviews focused on understanding the consumer's experience at BBB as well capturing descriptions of their motorcycle, riding preferences, riding attire, and their overall motorcycle consumption habits. Interviews that followed the protocol but did not result in the screen being administered are classified as an informal interview. Additionally, the normal social interactions and discussions that occur at an event were classified as informal interviews.

The field research utilized a wide-range of data collection methods: pocket audio recorder (15hrs, 39mins), wearable ear-mounted video camera (7hrs, 00mins), handheld video camera (1hr, 52mins) and a digital still camera (281 photos) to capture the majority of the interviews and event participation. Multiple special events were attended, such as portions of the Battle of the Bikes, a bike judging contest, and the Parade of Power (Figure 1), a multi-hour stream of bikers riding down Dickson, the city's main street. I also rode my moped up and down the main street a few times each day to visually capture and experience this conspicuous display ritual.

Insert Figure 1 about here All recorded formal and informal interviews were transcribed. Drawing on extant research and using the consumption collective typologies developed by [START_REF] Canniford | A typology of consumption communities[END_REF], Goulding and colleagues (2013) and Thomas and colleagues (2013) participants were categorized into their appropriate consumption collective based on the interview transcript. A few participants were not placed into a pre-existing consumption collective category and instead they were classified as market participants. This is because their interviews suggest their attendance was motivated by the opportunity to take advantage of BBB for traditional market reasons, such as purchasing food, enjoying the music, or otherwise engaging in transactional relationships with BBB vendors and organizations. After each participant was categorized the participant screens were visually inspected to determine if their survey results correspond with their discourse.

Participant screen

Participant screens are questions administered to interviewees to ensure they fit the characteristics of the study's desired participants and/or demonstrate they possess certain characteristics. They tend to be categorical (sex, party affiliation) when tied to study participant requirements. The failure to report and even collect evidence supporting membership claims can be problematic as screens help ensure the study is researching what it intends to research. [START_REF] Thomas | When differences unite: resource dependence in heterogeneous consumption communities[END_REF], for instance, explore community tensions, arguing that "heterogeneity and resource dependence co-occur and are intertwined such that the community sustains itself by building a network of dependent social and economic resource exchanges between heterogeneous actors" (p. 1017). Thus, the competition within a community creates the social structure allowing for differing levels of social capital to be distributed. Social capital is akin to economic capital with one major distinction: social capital functions within social relations while economic capital functions with economic or monetary relations [START_REF] Bourdieu | The logic of practice[END_REF]).

Thus, social capital is only a resource within specific social arrangements, groups or collectives.

Demonstrating or displaying one's social capital helps position the individual within the collective and, ultimately, determines their identity (Arsel & Thompson 2011;[START_REF] Bourdieu | Distinction: A social critique of the judgement of taste[END_REF].

Accordingly, understanding the social rules or structuralized behaviour patterns regrading what body movements to (not) make, what objects (not) to possess and what words to (not) say have important ramifications on an individual's ability to accrue social capital as well as constructing their identity. This competitive social game provides meaning to members by offering them something to be engaged in and helping them develop a sense of belonging. However, while Thomas and colleagues (2013) assert "belonging refers to the degree to which communities embrace solidarity and togetherness (communitas) as a part of their collective identity" (p. 1012), Thomas and colleagues do not provide any evidence that their informants possess solidarity or a collective identity with other members. In fact, the presented data demonstrate the opposite. An informant named Ryan stated "If you are going to run or walk a marathon, just go walk [26 miles] yourself. Don't waste everyone else's time, getting in front of everyone and slowing down...elite runners" (p. 1020). Ryan's other passage is just as disparaging. While [START_REF] Thomas | When differences unite: resource dependence in heterogeneous consumption communities[END_REF] interpret this statement as a source of intra-community tension it may have been inter-collective or inter-group tension as Ryan appears to be placing himself in the elite runner community thereby distancing himself from the running tribe. This example demonstrates that reporting on why each participant was classified as a community member can bolster claims that intra-community tension is not actually inter-collective tension.

Individuals are members of multiple collectives, groups and communities. They may feel connected to others who engage in the same profession, share interest in a particular clothing or motorcycle brand or enjoy a certain leisure activity, for instance. An individual's behaviors, discourse and mindset are motivated not just by their social relations but also their social setting [START_REF] Allen | Toward a theory of consumer choice as sociohistorically shaped practical experience: the fits-like-a-glove (FLAG) framework[END_REF]. While individuals may spend more time within one community over another, multimembership is not hierarchical, like a pyramid but, instead, interconnected, like a web [START_REF] Warde | After taste: culture, consumption and theories of practice[END_REF]). Accordingly, it is necessary to triangulate not just the research phenomena but also informant's membership or identity. Implementing participant screens within the field can help justify informant status because they were interviewed within the social setting where the specific membership is activated and their corresponding mindset is surveyed.

The next section reviews three main consumption collectives and presents representative participant screens collected in the field. The purpose of this section is to demonstrate that consumption collective research can implement a simple participant screen in the field.

Types of consumption collectives

Brand community

Brand communities arise when social relationships develop among brand admirers to enhance consumption experiences [START_REF] Mcalexander | Building brand community[END_REF]. The resulting strong consumer-brand relationship encourages members to expend substantial personal resources or "go the extra mile" to show their support for the brand. This involves more than just higher rates of spreading positive word-of-mouth or repeat purchasing to include traveling great distances to attend corporate sponsored events and wearing branded clothing [START_REF] Bhattacharya | Consumer-company identification: a framework for understanding consumers' relationships with companies[END_REF][START_REF] Marzocchi | Brand communities: loyal to the community or the brand[END_REF]. What distinguishes brand community members from brand loyal consumers is they have not only have a deep connection with the brand but also with other brand users and have a desire to protect and support community members. Accordingly, research participants must possess the three markers of community "shared consciousness, rituals and traditions, and a sense of moral responsibility" (Muñiz & O'Guinn 2001: 412) to be classified as brand community members. Otherwise they are brand loyal consumers or even a brand champions but they are not brand community members.

As an example, consider Jim a CPA from Utah, who first flew with his motorcycle to Harley-Davidson's headquarters in Milwaukee, Wisconsin for their 110 th Year anniversary before riding over 700 miles with his brother to BBB. Unlike his brother, Jim wasn't wearing a Harley-Davidson branded t-shirt and bandana; rather, he was smart looking in jeans, yellow baseball cap, and a long sleeve t-shirt-a quintessential RUB (Rich Urban Biker). In fact he was practically called out as such on this trip:

Jim -We pulled into Milwaukee and my brother, John, was standing there and there was a guy on an old, you know, kind of original Harley, and…I mean the hard-core and he sees me pull in next to John. And he turns to John and…well he turns next to him and says to himself…What did he say? John -"They will sell these damn things to anybody". Meaning he recognized he was not like him. The guys like him are the only ones that really should be riding these bikes.

Jim's experience exemplifies both the positives and negatives of brand communities. He is definitely a Harley-Davidson brand champion who encourages others to purchase the brand and travels great distances to support the brand and to meet other brand enthusiasts. However, conflicts over authentic performances appear to deter some brand users from developing a shared moral responsibility with other brand users. Without a participant screen researchers may have mistaken Jim for a brand community member.

Participant screens for brand community members need to take into consideration the three markers of community membership as well as a desire to support the brand. Therefore, this study expected to see high ratings for participants' consumer-brand connection as well as their communal-brand connection, customer commitment, and intentions to spread positive word-ofmouth. The latter scales serve as a proxy for a shared sense of moral responsibility and consciousness. However, Figure 2 provides Jim's raw participant screen data which finds that he has a reduced connection with fellow brand users and he doesn't fully believe other users are like him. Thus, he may not be brand community member or there may be multiple Harley-Davidson brand communities.

Insert Figure 2 about here

Consumption tribes

Consumption tribes are groups of consumers engaged in similar activities and characterized by their focus on social interaction and play [START_REF] Cova | Community and consumption: towards a definition of the "linking value" of product or services[END_REF]). Tribal membership is often multiple, resulting in a liquid boundary that emerges, adjusts, and dissipates sometimes as fast as it arrives [START_REF] Canniford | A typology of consumption communities[END_REF]. Tribes negotiate and share meaning as other collectives but often change, combine, and create new meanings in innovative ways to meet their specific interests. Therefore, the presence of legitimacy markers stemming from structuralized behavior patterns, such as wearing appropriate clothing are reduced, if present at all. Further, hierarchical structures are less common in tribes as they are organic in growth and tend to spontaneously arise due to a collective emotional state [START_REF] Cova | Tribes, inc.: the new world of tribalism[END_REF][START_REF] Goulding | Learning to be tribal: facilitating the formation of consumer tribes[END_REF]. Thus, to consumption tribes, brands are valued for the social-linking value over functional value because using a brand facilitates social interaction which is different than brand community members who value a brand and then form relationships with others because they use the brand. Participant screens for consumption tribe members do not require high intentions to spread positive word-of-mouth or high levels of brand commitment. This is because the consumer's consumption experience revolves around social interaction and not maintaining a relationship with the brand, as is the case with brand community members. While some consumers may have elevated relationships with the brand, if a participant evidences high commitments or attachments to other brand users this may suggest they are a brand community member and extra attention should be given to their interview transcripts. Bob -"I like them all really. I am not a hard-core Harley man like some around here. I will still ride. I will ride anything. I enjoy being with people who will ride anything. I checked out the new Indians over there, at the University. They are beautiful."

Insert Figure 3 about here Accordingly, consumption tribe members' consumption experiences are characterized by a preference for social interactions and the brands enrolled into consumption experiences tend to have lower prominence than in brand community members. Resource play and creative arrangements may then be mischaracterized as conflict over authentic performance or a social status game when in fact tribes lack the social structure necessary for resource competition. There is no legitimate or correct way to perform for consumption tribe members while brand communities have a social structure coming from their shared history and way of doing things.

Understanding whether a consumer is playing or competing with their resource configurations is, therefore, key in identifying whether a consumer is a consumption tribe member or brand community member.

Communities of practice

The identifiable consumption patterns of a community of practice are not a direct result of an intention to consume a specific product or brand, as in brand communities or engage in social interaction, as in consumption tribes. Rather, communities of practice predominately focus their attention towards practice enactment, improvement, and preservation [START_REF] Lave | Situated learning: Legitimate peripheral participation[END_REF][START_REF] Wenger | Communities of practice and social learning systems[END_REF]. Communities of practice develop through a shared understanding of how an activity should be done [START_REF] Bourdieu | The logic of practice[END_REF]). Communities of practice do not need to possess hierarchical structures but formal communities of practice, commonly referred to as a trade or professional association often have structured hierarchies. Communities of practice possess a sense of mutuality: the belief that involvement in a community helps them do an activity better than not self-organizing. Organization researchers have predominately explored how communities of practice share knowledge and how they coordinate with outsiders [START_REF] Carlile | A pragmatic view of knowledge and boundaries: boundary objects in new product development[END_REF].

Similarly, consumer researchers often look at how meanings or values are managed within communities of practice [START_REF] Leigh | The consumer quest for authenticity: the multiplicity of meanings within the MG subculture of consumption[END_REF].

In terms of participant screening, both the interview script and survey included questions to capture if motorcycles are a component of the interviewee's profession. A prominent community of practice evident in the data was the mechanical community. The following introduces Tommy who hand-builds one-of-a-kind bikes that are products of his imagination and creative process (Figure 4). He values the construction process because it allows him to test his skills and improve his competency, as he often builds things because "I just wanted to see if I could do it".

Insert Figure 4 about here

It is quite evident that Tommy is not deeply concerned with promoting his self-selected favorite motorcycle brand, Harley-Davidson (See Figure 5); rather, he is focused on enacting the mechanical practice. He has built bikes for all of his six boys and is currently working on a couple of their girlfriends' bikes. Moreover, on Saturday he spent the day sitting next to James who had the only hand-built Rat Bike at the rally. They met the preceding year at BBB when they were interviewed for the news. While both Tommy and James are very friendly and open they didn't initiate social interaction with event attendees or wear Harley-Davidson attire.

Accordingly, consumption patterns emerging from communities of practice place prominence on enacting and preserving the practice, in this case the mechanical practice over the brands they may use in the practice.

Insert Figure 5 about here

Summary

This section demonstrated that qualitative researchers can implement a brief self-administered survey as a participant screen. This study used existing scales but researchers should construct a participant screen that meets their needs. Without a participant screen researchers may mistakenly classify participants as members of a particular consumption collective or misinterpret tensions and conflicts over object authenticity, for instance, as an intra-collective conflict when the tensions over what counts as an authentic object may be better explained as an inter-collective conflict.

Marketing to consumption collective members

While this study focuses on consumption collective members, it is important to address consumers who are not collective members. First, collective-like practices are evident in members of a collective who engage in social status games by contesting, negotiating and altering the meanings of resources within the collective [START_REF] Levina | Turning a community into a market: a practice perspective on information technology use in boundary spanning[END_REF]. In essence, these individuals are attempting to accrue social capital by demonstrating an understanding of the collective's rules [START_REF] Bourdieu | Distinction: A social critique of the judgement of taste[END_REF]. Collective-like practices not only include behaviors that place themselves within the collective's hierarchy but also behaviors that attempt to change what counts as a legitimate community behavior. Leigh and colleagues' (2006) work on what counts as an authentic MG highlights some of the intra-collective conflicts that can arise when members challenge the meanings attributed to objects. [START_REF] Kates | The protean quality of subcultural consumption: an ethnographic account of gay consumers[END_REF] work on joining the gay community, illustrates the process of joining a community. His work shows that individuals, when entering a community, tend to mimic others. Then, as they gain knowledge and confidence in their ability to work within the social structure they begin to challenge accepted symbolic meanings and behaviors in an effort to carve out a unique identity within the community.

Consumers interested in joining the collective have legitimate peripheral membership [START_REF] Lave | Situated learning: Legitimate peripheral participation[END_REF][START_REF] Wenger | Communities of practice and social learning systems[END_REF], until they have the ability to fully participate in the collective. Accordingly, legitimate peripheral practices are reserved for consumers who are legitimately able to participate in the collective's activities but have low social capital and are developing their understanding of the collective's norms and shared history. Accordingly, peripheral collective members do not have the social capital to fully engage in meaning altering games but are interested in these intra-collective conflicts nonetheless [START_REF] Bourdieu | The logic of practice[END_REF]). Thus, peripheral members enact a mix of collective-like practices and market-like practices. Marketlike practices are evident in consumers who accept the meaning of a resource as objectively established [START_REF] Levina | Turning a community into a market: a practice perspective on information technology use in boundary spanning[END_REF]. This is different from legitimate peripheral practices, where a consumer is attempting to enter a collective through gradually learning the required behaviors and discourse and is actively engaging in intra-collective meaning making. In essence, consumers enact market-like practice when they are uninterested in the social games or resource conflicts occurring around them and are, therefore, not members of the collective under investigation.

Insert Figure 6 about here

Classifying consumer by collective membership status suggests that differing marketing strategies might be more appropriate depending on the membership status of the consumer being targeted (see Figure 6). Consumers engaging in market-like practices are interested in taking the values embedded into the brand and incorporating them into their life projects. They are not interested in actively participating in its meaning creation system. Therefore, transactional marketing could be a particularly efficient strategy to implement when targeting consumers not part of a consumption collective. However, brand managers should still develop a clear brand image within the market so consumers can integrate the branded resource into their lives. Even though consumers do not collaborate with a brand this does not negate the fact that the brand is being integrated into their social system [START_REF] Vargo | Service-dominant logic: continuing the evolution[END_REF], has symbolic meaning in their life and should be managed accordingly.

As peripheral participants are actively engaging with a collective and are trying to acquire the capital and knowledge necessary to become a legitimate member of the collective offering them support could be advantageous. Moreover, they are becoming familiar with a brand's functional quality and values presenting an opportune time to strength the consumer-brand link by implementing relationship marketing strategies. This is important for brand managers as brand community members have higher repurchase tendencies compared to consumption tribe members who are more prone to switch brands in order to maintain social relations as they have lower brand commitment levels. Additionally, strengthening the consumer-brand relationship in this stage may motivate these consumers to join a brand community over a community of practice, for instance.

Members of a collective are actively involved in the meaning management process and are characterized by their desire to preserve the collective's prominent resource, whether it is a practice or a brand. Accordingly, brand managers should consider implementing community marketing strategies to collective members. First, creating opportunities for consumers to meet and share knowledge can help facilitate the formation of a community [START_REF] Mcalexander | Building brand community[END_REF][START_REF] Wenger | Communities of practice: the organizational frontier[END_REF]. Besides supporting social relation development, meeting others enables consumers to enhance their self-esteem through demonstrating their competency in using the brand and brand knowledge, more generally [START_REF] Schau | How brand community practices create value[END_REF]). Thus, brand focused social events can subtly direct a collective's interest towards brand preservation in an effort to form a brand community. Additionally, developing a connection with these consumers can help identify trends and new products as they tend to be generated by heavy end-users interested in personalizing and modifying products [START_REF] Roberts | Consumer co-creation: an opportunity to humanise the new product development process[END_REF][START_REF] Von Hippel | Democratizing innovation[END_REF]. Schau and colleagues (2009) further suggest that vibrant communities display a series of practices that can be classified into four main categories. Accordingly, brand managers interested in implementing a community marketing strategy should ensure that their consumers have sufficient social networking opportunities. Interested members need to be welcomed, they need to feel as if they are supported and cared about, have a set of rules to follow and be provided with opportunities to transition from a peripheral member into a full member. The community also needs to possess impression management practices. These practices or activities evangelize, promote or otherwise encourage others to join and these practices also justify the community's existence by defending it and other members from negative images or discourse. Successful communities are also composed of members who evidence community engagement practices. Specifically, members often strive for and highlight the achievement of significant events. For example, Schau and colleagues (2009) note that concert-goers often celebrate their 100 th show or, as this study's informant Jim mentioned, visiting the brand's headquarters. Members also stake claims to or become experts in specific domains within the community. This feature enables members to develop a unique identity based on community-valued knowledge while still fitting in or maintaining a sense of belonging. The last set of practices a vibrant brand community possesses is brand use. In particular, communities share and promote a specific usage or consumption pattern. They also modify and customize the brand to meet their needs. Lastly, communities generate or produce innovative brand related objects and material. Brand managers are urged to identity which practices are underdeveloped within a collective and then develop a strategy to develop this practice, such as sending welcome letters, suggesting milestones, and supporting product modifications.

Summary

This research demonstrates that researchers focused on consumption collective membership should consider implementing short participant screens to ensure participants are part of the group or collective under investigation. Currently, while common in private practice and in other research domains, research on consumption collectives rarely justify their informants' membership status. In fact, the author is unaware of any published study in which researchers explicitly state how each informant met the requirements to be classified as a brand community member, for instance. This is potentially problematic as research interest is moving away from justifying the presence of various consumption collectives to understanding how intra-collective conflicts impact the meaning making process and develop various forms of social capital using heterogeneous resources. Therefore, it is suggested that consumption collective researchers should implement and report on participant screens, especially when membership issues are intertwined with research objectives.

Additionally, developing a participant screen could be advantageous for investigating how and why consumption collective membership transform over time. Research on consumption tribes suggest that tribe members sometimes fall into a routine, using the same brand during multiple social interactions, potentially facilitating their transformation into a brand community member. Additionally, brand community research suggests that members form social relations with other members that center on other activities, potentially weakening brand community membership. Longitudinal research is needed to fully understand how consumers transform through time. Is there a standard progression of moving from a consumption tribe to brand community member, for instance? Does the transformation process differ for consumption behaviors that allow for competency improvements? For example, personally restoring a motorcycle provides a consumer with opportunities to not only improve brand knowledge but also their mechanical competency. Thus, the consumer may transform into a community of practice member and not a brand community member if they find more satisfaction or social capital gains in the mechanical community than the brand community. It is recommended to implement relationship marketing and then community marketing to encourage consumers to form a relationship with the brand over the practice or usage activity. Moreover, a multitude of scales exist that measure consumers' resource-identity strength, such as consumer-brand [START_REF] Escalas | Self-construal, reference groups, and brand meaning[END_REF], consumer-possession [START_REF] Ferraro | Our possessions, our selves: domains of selfworth and the possession-self link[END_REF], and consumer-organization [START_REF] Mael | Alumni and their alma mater: a partial test of the reformulated model of organizational identification[END_REF]. Consumers can, potentially, form a relationship with any of these resources and researchers should select the scales that are appropriate for their research question.

Accordingly, integrating participant screens into longitudinal studies opens the door for tracing membership transformation through time.

Conclusion

Consumer researchers have identified and investigated a handful of consumption collectives, such as consumption tribes, brand communities, and communities of practice. This research demonstrates that consumption collective researchers can implement a short survey during field interviews as a participant screen in order to substantiate membership classifications claims.

Lastly, marketers are encouraged to adjust marketing strategies and messages based on the individual consumer's consumption collective membership status.

Figure 3

 3 Figure 3 presents Bob's participant screen. Bob rode to BBB with his wife to reunite with another couple he met earlier in Indiana while working as a pig hauler. Prior to administering the participant screen, his response to what bikes he likes suggests he is not a Harley-Davison brand community member, even though Harley is his favorite motorcycle brand and he owns one.

Figure 3

 3 Figure 3 Consumption tribe member participant screen

Figure 4 Figure 5 Figure 6

 456 Figure 4 Community of practice motorcycle

Matthew A. Hawkins, matthew.hawkins@icn-artem.com, ICN Business School, University of Lorraine -CEREFIGE

Appendix

Scales and sources included in participant screen. All scales where measured using a 7-point, labeled, likert-scale: 1=Totally Disagree; 2=Disagree; 3=Somewhat Disagree; 4=Neither Agree or Disagree; 5=Somewhat Agree; 6=Agree; 7=Totally Agree

List of Figures


Yoonjin Kim
email: ykim@poppy.snu.ac.kr

Mary Kiemb
email: ‡kiemb@marykiemb.net

Chulsoo Park

Jinyong Jung
email: jyjung@poppy.snu.ac.kr

Kiyoung Choi
email: kchoi@azalea.snu.ac.kr

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

published or not. The documents may come   L'archive ouverte pluridisciplinaire

Introduction

As the market pressure of embedded systems compels the designer to meet tighter constraints on cost, performance and power, the application specific optimization of a system becomes inevitable. On the other hand, the flexibility of a system is also important to accommodate rapidly changing consumer needs. To compromise these incompatible demands, domain-specific design is focused on as a suitable solution for recent embedded systems. Coarse-grained reconfigurable architecture is the very domain-specific design in that it can boost the performance by adopting specific hardware engines but it can be reconfigured as well to adapt the different characteristics of each application.

In this reason, many delicate coarse-grained reconfigurable designs are proposed [START_REF] Hartenstein | A decade of reconfigurable computing: a visionary retrospective[END_REF]. Most of them comprise of a fixed set of specialized processing elements (PEs) and interconnection fabrics between them and the run-time control of the operation of each PE and the interconnection provides the reconfigurability. However, such fixed architectures have limitations in optimizing the cost and performance for various domains of application. Some researchers suggest a reconfigurable architecture in the form of a template to find an optimal design for a specific application domain [START_REF] Mei | Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study[END_REF] [START_REF] Reiner Hartenstein | KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures[END_REF]. Most design space exploration techniques previously suggested are limited to the configuration of the internal structure of a PE and the interconnection scheme. Such configuration techniques are in general good at obtaining high performance but require high hardware cost. This is mainly because even a primitive PE design should be equipped with basic functional resources to gain reasonable performance. Moreover, adding a small functional block to a primitive PE design increases the total cost of the aggregate architecture increases a lot. To alleviate this problem, some templates permit heterogeneous PEs [START_REF] Reiner Hartenstein | KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures[END_REF] [START_REF] Bansal | Analysis of the performance of coarse-grain reconfigurable architectures with different processing element Configurations[END_REF]. However, such heterogeneity bears strict constraints in the mapping of applications to PEs, resulting in negative effect on the performance.

In this paper, we suggest a reconfigurable architecture template which has two key features. One is hardware cost reduction by sharing critical functional resources that occupy large area in the PEs and the other is critical path reduction by pipelining the critical resources. To implant these features into our template, we assume that the template is based not on SIMD like execution [START_REF] Singh | MorphoSys: an integrated reconfigurable system for dataparallel and computation-intensive applications[END_REF] but on loop pipelining execution [7][8]. Although SIMD like execution is efficient for data parallel computation in that it saves configuration and data storage by regular execution, it is inflexible in that each PE cannot operate independently. In contrast, loop pipelining requires more storage to control each pipeline stage but it has more flexibility in selecting the operation of a PE. In addition, it can enhance the performance because it reduces the synchronization overhead to perform identical operations simultaneously.

This paper is organized as follows. After mentioning the related work in Section 2, we describe our reconfigurable architecture template in Section 3. In Section 4, we propose a design flow to optimize the reconfigurable architecture to a specific application domain. We also describe the details of design space exploration for optimal resource sharing. We show the experimental results in Section 5 and conclude with future work in the last section.

Related Work

Many coarse-grained reconfigurable architectures are suggested as summarized in [START_REF] Hartenstein | A decade of reconfigurable computing: a visionary retrospective[END_REF]. Among them, two dimensional mesh architectures have the advantage of rich communication resources for parallelism. Morphosys [START_REF] Singh | MorphoSys: an integrated reconfigurable system for dataparallel and computation-intensive applications[END_REF] consists of 8 x 8 array of Reconfigurable Cell coupled with Tiny_RISC processor. The array performs 16-bits operations including multiplication in SIMD style. It shows good performance for regular code segments in computation intensive domains but requires high hardware cost. XPP configurable system-on-chip architecture [START_REF] Becker | Architecture, memory and interface technology integration of an industrial/academic configurable system-on-chip (CSoC)[END_REF] is another example. XPP has 4 x 4 or 8 x 8 reconfigurable array and LEON processor with AMBA bus architecture. A processing element of XPP is composed of an ALU and some registers. Since the processing elements do not include heavy resources, the total hardware cost is not high but the range of applicable domains is restricted.

For more aggressive domain-specific optimization, template based architectures are suggested. In ADRES template [START_REF] Mei | Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study[END_REF], an XML-based architecture description language is used to define the overall topology, supported operation set, resource allocation, timing, and even internal organization of each processing element. KressArray [START_REF] Reiner Hartenstein | KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures[END_REF] also defines the exploration properties such as array size, interconnections, and functionality of certain processing elements. However, both templates do not support common resources shared among processing elements, thus some critical functional resources may have low utilization while occupying large area.

3

Architecture Template

Resource sharing

We illustrate resource sharing between processing elements with matrix multiplication. We assume a general mesh-based coarse-grained reconfigurable array of PEs, where a PE is a basic reconfigurable element composed of an ALU, an array multiplier, etc. and the configuration is controlled by configuration cache. Each row of the array shares read/write-buses. Figure 1 shows the case of 4x4 array with two read buses and one write-bus. Consider two square matrices X and Y of order N. The output matrix Z is represented by:

1 0 )} , ( ) , ( { ) , ( N k j k Y k i X C j i Z (1)
where i, j = 0,1,…,N and C is a constant specified in the configuration cache. Assuming that equation (1) with N=4 is executed on the array shown Figure 1, the loop pipelining [START_REF] Lee | Mapping loops on coarse-grain reconfigurable architectures using memory operation sharing[END_REF] schedules the operations as shown in Figure 2. The first row of Figure 2 represents the schedule time in cycle from the start of the loop and the first column represents the column number of the array. At the first cycle, all the PEs in the first column are loaded with the operands then perform multiplication at the second cycle. In the next two cycles, the PEs in the first column perform addition to obtain the sum of products, while the PEs in the next columns perform multiplication. Then multiplication is performed in the first column at the 5 th cycle while the first multiplication is performed in the fourth column. Because loop pipelining distributes the same operations over several cycles, there is no need for all PEs to have the same functional resources at the same time. This allows the PEs in the same column or in the same row to share area-critical resources. For the 4x4 matrix multiplication example, since multipliers take much more area and delay compared to other resources, we classify them as critical resources and other resources as primitive resources. The reconfigurable structure in our template can be one dimensional array, two-dimensional mesh, or other rectangular structure, where each PE has its own Bus switch to control the resource sharing.

Figure 4 depicts the detailed connections about multiplier sharing. The two n-bit operands of a PE are connected to the Bus switch. The dynamic mapping of a mul-tiplier to a PE is determined in compile time and the information is annotated to the configuration instructions. In run-time, the mapping control signal from the configuration cache is fed to the Bus switch and the Bus switch decides where to route the operands. After the multiplication, the 2n-bit output is transferred from the multiplier to the original issuing PE via the Bus switch.

Resource pipelining

If there is a critical functional resource which has very long latency in a PE, the functional resource can be pipelined to curtail the critical path. Resource pipelining has clear advantage in loop pipelining execution because heterogeneous functional units can run at the same time. Figure 5 shows this. In a general PE design, the latency is fixed by the critical path but in a pipelined PE design, the critical path is curtailed by the register insertion, so the latency can vary depending on the operation. Since heterogeneous operations are executed simultaneously in loop pipelining, some short latency operations can terminate early and the total latency of the system may be reduced. If a critical functional resource has both large area and long latency, the resource sharing and resource pipelining can be applied at the same time in such a way that the shared resource executes operation in several pipeline stages. If these two techniques are merged, the conditions for resource sharing are relaxed and so the critical resources are utilized more efficiently. Figure 6

Critical Resource

Design Space Exploration

Since our Resource Sharing and Pipelining (RSP) technique assumes any rectangular pipelining structure, our RSP design flow for domain-specific optimization is applicable to a generic array architecture template including many existing coarse-grained reconfigurable arrays. The RSP technique can be integrated into the refinement stage of the base design space exploration flow. The steps in the upper half of Figure 7 represent the generic design space exploration flow and those in the lower half represent our RSP flow. The upper half can be slightly different depending on the specific base architecture. To extract critical loops which are to be executed on the reconfigurable architecture, profiling is performed over a set of applications in the target domain. When the critical loops are selected, the design space is explored to obtain an optimal base architecture. After the base architecture is determined, the selected critical loops are mapped on the configuration contexts. With the base architecture and the initial configuration contexts, RSP parameters are determined through the RSP design space exploration step. Our RSP template has the following principal parameters for design space exploration:

The types of shared functional resources The types of pipelined resources The number of pipeline stages of the pipelined resources The number of rows of the shared resources The number of columns of the shared resources

For an easy mapping of operations, we need to form a regular structure of shared resources. So the shared resources are placed in line with the rows and/or columns of the reconfigurable structure. Thereby, the structure of the shared resources is represented by the number of rows and/or columns. The RSP design space exploration is based on the estimation of the hardware cost and performance with the RSP parameters. If the hardware cost is too high or the performance is too low, such RSP design is rejected. Among the designs that satisfy the condition, only Pareto points are evaluated and then an optimal solution is selected. Although accurate hardware cost of entire architecture is evaluated after RSP exploration, we can estimate the hardware cost of an RSP design with presynthesized architecture components during RSP exploration. This is as follows : Once the final RSP configuration context is obtained, we can evaluated the exact performance since the configuration context has the information of the exact number of cycles required to execute the given kernel loop. However, the mapping and evaluation of all the candidate RSP designs are time-consuming. Therefore, in the RSP exploration stage, we use the upper bound for the performance estimation. The upper bound is computed with the RSP parameters and the initial configuration contexts. In the case of RS, the number of operations that are to be executed on the critical resources is counted and compared with the number of shared resources in every cycle. If the number of critical operations in a cycle is larger than the number of shared resources, it means that the shared resources are lacking in the cycle. Therefore, some stall cycles should be inserted to avoid the resource conflict -we call it RS stall. In addition, in the case of RP, the operations that are to be executed on the pipelined resources take multiple cycles so the operations dependent on pipelined resources should be stalled together -we call it RP stall. So we approximate the entire number of stall cycles by RS stall and RP stall cycles. In reality, more cycles may stall depending on the characteristics of the RSP structure, thus this approximation is an upper bound of the performance. The initial RSP configuration contexts are rearranged according to the RS and RP. We have two rules for the rearrangement. First, in the case of RS, shared resources are assigned to PEs in the order of loop iteration. Therefore, if it lacks shared resources, the operations in later loop iterations are moved to the next cycle. Second, in the case of RP, since the operations on pipelined resources take multiple cycles, other operations dependent on the output of pipelined resources have to be stalled together. Furthermore, in the case of consecutive pipelined operations, overlapped cycles between the operations should be removed. In the case of RSP, the two rules are applied to the initial configuration contexts.

5

Experimental Results

Architecture specification

We have determined the internal PE design as well as the array structure by analyzing the kernels and implemented the base architecture with VHDL. The base architecture used in this experiment is similar to Morphosys, which has a two dimensional 8 x 8 mesh of PEs. Each of the PEs contains one ALU and one array multiplier. Our base architecture is different from Morphosys in that data memory have multiple read/write data buses and a configuration cache is allocated to each PE. This is because our template assumes loop pipelining style execution while Morphosys assumes SIMD style execution. In addition, the bit-width of the data bus is extended to 16 and some interconnections between PEs are added to reduce data arrangement cycles. We evaluated area and delay cost of each component of a PE by RTL synthesis and the result is shown in Table 1. The array multiplier is a critical resource in both area and delay and thus we extract the multiplier from the PE design and arrange it to be the shared and pipelined resource. To make a two stage pipelined version of the multiplier, we inserted a pipeline register into the multiplier.

5.2

Architecture evaluation

For quantitative evaluation of RTL model from RSP exploration, we have used Synplify Pro TM [9] as the RTL synthesis tool and Xilinx Virtex II 8M gates FPGA[10] as the target hardware. To demonstrate the effectiveness of our approach, we have compared three cases: base architecture, RS architecture, and RSP architecture. Figure 8 shows four cases of resource sharing:

Performance evaluation

We have applied several kernels of Livermore loops benchmark and representative loops in DSP applications to RS and RSP architectures. Table 3 shows the operation set and maximum multiplication number in a cycle of selected kernels. Table 4 shows that RSP Arch#2 supports all of the selected kernels of Livermore loops without stall and gives the best performance. Table 5 shows performance evaluation of specific applications including 2D-FDCT, SAD, MVM, and FFT, and RSP Arch#2 again supports all of the selected kernels. The performance evaluation results of Table 4 and5 show that the best performance for individual kernels can be obtained with RSP#1 or RSP#2. Therefore we conclude that RSP architecture is more efficient than the base architecture in the aspect of area and delay. Furthermore, the shared resources of RSP architectures are more utilized than RS architectures under same resource sharing condition -in the case of 2D-FDCT in H.263, RSP#2 has no stall but RS#2 has stall cycles of 6. The amount of performance improvement depends on the application. For example, compared to 2D-FDCT which has multiplications, we have achieved much more performance improvement with RSP architectures for SAD which has no multiplication. This is because the clock frequency has been increased by pipelining the multipliers. We cannot have that much speedup for kernels with many multiplications since multiplications take multiple cycles in the RSP architectures.

Conclusion

Coarse-grained reconfigurable architectures are considered to be appropriate for embedded systems because it can satisfy both flexibility and high performance. Most reconfigurable architectures use regular structures composed of computational primitives for parallel execution of multiple operations and flexible operation scheduling but such regular designs require many hardware resources without regard to the characteristics of the application domain. To overcome the limitation, we suggest a novel reconfigurable architecture template which splits the computational resources into two groups: primitive resources and critical resources. Critical resources can be area-critical and/or delay-critical. Primitive resources compose the base reconfigurable array. Area-critical resources are shared among the basic PEs. The number of shared resources is configurable according to the application domain. Delay-critical resources can be pipelined to curtail the overall critical path so as to increase the system clock frequency. In this way, our architecture template can be used to achieve the goal of domain-specific optimization while keeping the regularity of the reconfigurable array.

In the experiments, the RTL synthesis results show that our sharing and pipelining can reduce the area and the critical path delay by up to 42.8% and 34.69% respectively compared to the base architecture and the benchmark evaluation reveals the performance enhancement up to 35.7%. In this paper, we consider only hardware cost and performance but the domain-specific optimization may also be effective for reducing power consumption. To verify the practicality of the proposed approach more seriously, we are currently working on implementing H.264 encoder on our architecture template.

Figure 1 .

 1 Figure 1. 4x4 reconfigurable Array.

  operation, St: store operation

Figure 2 .

 2 Figure 2. The loop pipelining of a matrix multiplication of order 4.

Figure 3 . 8

 38 Figure 3. 8 multipliers sharing among 16 PEs.

Figure 4 .

 4 Figure 4. The connections between a PE and shared multipliers.

Figure 5 .

 5 Figure 5. The critical path comparison between a general PE and a pipelined PE.

Figure 6 .

 6 Figure 6. The loop pipelining of a matrix multiplication when the multiplier is pipelined.

Figure 7 .

 7 Figure 7. Design space exploration flow for RSP architecture template.

  HW cost = {n×m×(Sh_PE area +Reg area +SW area ) + Sh_Res area ×(n×shr+m×shc)} < n×m×PE area (2) where n, m : number of row, column PE area : area of a PE with shared resource Sh_PE area : area of a PE without shared resource Reg area : area of registers in a PE for pipelined operation SW area : area of a bus switch Sh_Res area : area of a shared resource shr/shc : number of rows/columns of the shared resources

Table 1 . Synthesis result of a PE

 1

	Component	Area No. of slices	Ratio	Critical path delay Time(ns) Ratio
	PE	910	100	25.6	100
	Multiplexer	58	6.37	1.3	12.89
	ALU	253	27.80	11.5	44.92
	Array multiplier	416	45.71	19.7	76.95
	Shift logic	156	17.14	2.5	17.58

bold number : the largest ratio among the components

Table 2 .

 2 Compared to the base architecture, we have reduced the area and delay by up to 42.8% and 34.69%, respectively.

	1. one multiplier shared by 8 PEs in each row,
	2. two multipliers shared by 8 PEs in each row,
	3. two multipliers shared by 8 PEs in each row and
	one multiplier shared by 8 PEs in each column,
	4. two multipliers shared by 8 PEs in each row and
	two multipliers shared by 8 PEs in each column.
	The RTL synthesis results of these designs are shown in
	RS/RSP Architecture #1		RS/RSP Architecture #2
			MUL MUL	MUL MUL		MUL MUL
		8x8			8x8
	PE array	MUL MUL	MUL MUL	PE array	MUL MUL
			MUL MUL	MUL MUL		MUL MUL
	RS/RSP Architecture #3		RS/RSP Architecture #4
	MUL MUL	MUL MUL	MUL MUL	MUL MUL	MUL MUL	MUL MUL
	MUL MUL		MUL MUL	MUL MUL		MUL MUL
		8x8			8x8
	MUL MUL	PE array	MUL MUL	MUL MUL	PE array	MUL MUL
	MUL MUL		MUL MUL	MUL MUL		MUL MUL
				MUL MUL	MUL MUL	MUL MUL

Figure 8. Four designs of RS/RSP architectures.Table 2 . Synthesis result of various architec- tures Area (No. of slices) Critical path delay(ns) Arch' PE SW Array R(%) PE SW Array R(%)

 2

	Base 910 -	55739	0	25.6 -	26	0
	RS#1		10 32446	42.8		0.7 26.85 -4.88
	RS#2		34 36816 34.05		1.2 27.97 -9.25
	RS#3		55 40577 27.02		1.8 28.89 -11.11
	RS#4	489	68 44768 19.69	15.3	2.0 30.23 -16.27
	RSP#1		10 33249 40.35		0.7 16.72 34.69
	RSP#2		34 38422 31.07		1.2 17.26 32.58
	RSP#3		55 42987 22.88		1.8 18.21 29.97
	RSP#4		68 47981 13.92		2.0 18.83 27.58

R(%): Reduction ratio compared with Base architecture SW: Bus switch

Table 3 . Kernels in the experiments

 3

	Kernels	Operation set	Mult No.
	*Hydro	mult, add	6
	*ICCG	mult, sub	4
	*Tri-diagonal	mult, sub	4
	*Inner product	mult, add	8
	*State	mult, add	7
	2D-FDCT in H.263 enc mult, shift, add, sub	16
	SAD in H.263 enc	abs, add	0
	Matrix-vector Multiplication	mult, add	8
	Multiplication Loop in FFT	add, sub, mult	8
	*kernel : Livermore loop benchmark suite
	Mult No : maximum of multiplications mapped to array in a cycle
	mult : multiplication, add : addition, sub : subtraction,
	abs : absolute value, shift : bit shift operation

Table 4 . Performance evaluation of the kernels in Livermore loop benchmark suite Hydro(32 † ) ICCG(32 † ) Tri-diagonal(64 † ) Inner product(128 † ) State(16 † ) Arch' cycle ET(ns) DR(%) stall cycle ET(ns) DR(%) stall cycle ET(ns) DR(%) stall cycle ET(ns) DR(%) stall cycle ET(ns) DR(%) stall

 4 ) : iteration number of the kernel, ET(ns) : Execution Time = cycle Critical path delay(ns), DR(%) : Delay Reduction percentage, stall : stall number of resource lack, bold number : the largest amount of delay reduction %

	Base	15	390	0	-	18	468	0	-	17	442	0	-	21	546	0	-	20	520	0	-
	RS#1 19 510.15 -30.80 4	18 483.3 -3.26	0	17 456.45 -3.26	0	21 563.85 -3.26	0	35 939.75 -80.72 15
	RS#2 15 419.55 -1.07	0	18 503.46 -7.58	0	17 475.49 -7.58	0	21 587.37 -7.58	0	20 559.4 -7.58	0
	RS#3 15 433.35 -11.11 0	18 520.02 -11.11 0	17 491.13 -11.11 0	21 606.69 -11.11 0	20 577.8 -11.11 0
	RS#4 15 453.45 -16.27 0	18 544.14 16.27	0	17 513.91 -16.27 0	21 634.83 -16.27 0	20 604.6 -16.27 0
	RSP#1 21 351.12	10	2	19 317.68 32.12	0	18 300.96 31.91	0	22 367.84 32.64	0	37 618.64 -18.96 14
	RSP#2 19 327.94 15.92	0	19 327.94 29.93	0	18 310.68 29.71	0	22 379.72 30.45	0	23 396.68 23.65	0
	RSP#3 19 345.99 11.28	0	19 345.99 26.07	0	18 327.78 25.84	0	22 400.62 26.62	0	23 418.83 19.45	0
	RSP#4 19 357.77 8.26	0	19 357.77 23.55	0	18 338.94 23.31	0	22 414.26 24.12	0	23 433.09 16.71	0
	Kernel(No.

†

Table 5 . Performance evaluation of 2D-FDCT, SAD, MVM and FFT function 2D-FDCT in H.263 enc SAD in H.263 enc *MVM(64 † ) Multiplication Loop in FFT(32 † ) Arch' cycle ET(ns) DR(%) stall cycle ET(ns) DR(%) stall cycle ET(ns) DR(%) stall cycle

 5

	ET(ns)	DR(%)	stall

*MVM : Matrix Vector Multiplication

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE

Acknowledgements

This work was supported by grant No. R01-2004-000-10268-0 from the Basic Research Program of the Korea Science & Engineering Foundation.


Roman Lysecky
email: rlysecky@cs.ucr.edu

Frank Vahid
email: vahid@cs.ucr.edu

A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning

Keywords: Hardware/software partitioning, warp processing, FPGA, dynamic optimization, soft cores, MicroBlaze

Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their FPGA products. While FPGAs with soft processor cores provide designers with increased flexibility, such processors typically have degraded performance and energy consumption compared to hard-core processors. Previously, we proposed warp processing, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic. In this paper, we study the potential of a MicroBlaze soft-core based warp processing system to eliminate the performance and energy overhead of a soft-core processor compared to a hard-core processor. We demonstrate that the soft-core based warp processor achieves average speedups of 5.8 and energy reductions of 57% compared to the soft core alone. Our data shows that a soft-core based warp processor yields performance and energy consumption competitive with existing hard-core processors, thus expanding the usefulness of soft processor cores on FPGAs to a broader range of applications.

Introduction

Field programmable gate arrays (FPGAs) provide great flexibility to hardware designers. While past designers primarily used FPGAs for prototyping and debugging purposes, many commercial end-products now incorporate FPGAs. Designers using FPGAs can quickly build entire systems or hardware components while still leveraging the prototyping and debugging advantages that FPGAs have over ASIC (application-specific integrated circuit) designs. Continuing increases in FPGA capacity, performance, and architectural features are enabling more designs to be implemented using FPGAs. Additionally, FPGAs costs are decreasing, allowing designers to incorporate FPGAs with one million equivalent gates for less than $12 [27].

While designers can use FPGAs to quickly create efficient hardware designs, many systems require a combination of both software and hardware. In the late 1990s, FPGA vendors began introducing single-chip microprocessor/FPGA devices. Such devices include one or more hard-core (implemented directly using IC transistors/gates) microprocessors and an FPGA fabric on a single IC, and provide efficient mechanisms for communication between the microprocessor and FPGA. Atmel [2] and Triscend [23] were the first to make these devices available, both incorporating low-end microprocessors and FPGAs supporting tens of thousands of gates. More recently, Altera developed the Excalibur devices having an ARM9 processor and a one million gate FPGA [1]. Xilinx offers the VirtexII Pro devices incorporating two or more PowerPC processors and an FPGA fabric with tens of millions of gates [26].

While single-chip hard-core microprocessor/FPGA platforms offer excellent packaging and communication advantages, a softcore approach offers the advantage of flexibility and lower part costs. Many FPGA vendors are now offering such soft processor cores that designers can implement using a standard FPGA. Altera offers both the NIOS and more recently the NIOS II soft processor cores [1]. The NIOS II processor is a 32-bit configurable processor supporting clock frequencies as high as 135 MHz. Xilinx offers the PicoBlaze and MicroBlaze soft processor cores [26]. The MicroBlaze processor is 32-bit configurable processor core capable of supporting clock frequencies as high 150 MHz. These soft processor cores offer designers tremendous flexibility during the design process, allowing the designers to configure the processor to meets the needs of their systems (e.g., adding custom instructions or including/excluding particular datapath coprocessors) and to quickly integrate the processor within any FPGA. Unlike singlechip microprocessor/FPGA systems using hard-core processors, soft processor cores allow designers to incorporate varying numbers of processors within a single FPGA design depending on an application's needs. While some embedded system designs may require a few processors, other designs can include 64 processors [START_REF] Halfhill | MIPS embraces configurable technology[END_REF] or more. Furthermore, as reported in [START_REF] Halfhill | MIPS embraces configurable technology[END_REF], customers of Tensilica [START_REF] Tensilica | [END_REF], who provide customizable soft processor core solutions, are creating chip designs that incorporate over five processors on average.

Unfortunately, soft processor cores implemented using FPGAs typically have higher power consumption and decreased performance compared with hard-core processors. To alleviate the performance and power overhead, a designer can potentially use hardware/software partitioning to increase software performance while decreasing energy. Hardware/software partitioning is the process of dividing an application among software (running on a microprocessor) and hardware co-processors. By identifying the critical kernels within the software application, one can reimplement those software kernels as a hardware coprocessor on the FPGA. Extensive research has shown that hardware/software partitioning can result in overall software speedups of 200%-1000% [3][7][8] [START_REF] Gajski | SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design[END_REF][14] [START_REF] Venkataramani | A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture[END_REF], as well as reducing system energy by up to 99% [START_REF] Henkel | A low power hardware/software partitioning approach for core-based embedded systems[END_REF][13][20] [START_REF] Wan | An Energy Conscious Methodology for Early Design Space Exploration of Heterogeneous DSPs[END_REF].

However, hardware/software partitioning requires a special compiler that profiles, estimates hardware size, and generates an application binary that communicates with a hardware description that implements the software kernels. Thus, partitioning imposes a significant increase in tool complexity, and results in nonstandard output having greatly reduced portability compared to a standard binary. Recently, we showed [START_REF] Stitt | Hardware/Software Partitioning of Software Binaries[END_REF] that designers could perform desktop hardware/software partitioning starting from binaries rather than from high-level code, with competitive resulting performance and energy. Binary-level partitioning approaches can produce excellent results by using decompilation techniques to retrieve most of the high-level information typically lost at the binary level [START_REF] Cifuentes | Preliminary Experiences with the Use of the UQBT Binary Translation Framework[END_REF].

Binary-level partitioning opens the door to dynamic hardware/software partitioning, in which an executing binary is dynamically optimized by moving software kernels to configurable logic, a process we call warp processing [START_REF] Lysecky | A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning[END_REF][16] [START_REF] Stitt | Dynamic Hardware/Software Partitioning: A First Approach[END_REF]. However, warp processors previously only targeted single-chip multiprocessor/FPGA devices incorporating a hardcore processor. Extensive details of warp processing are beyond the scope of this paper and appear in other publications. Our purpose in this paper is to study whether warp processing methods could potentially make a soft processor core competitive with a hard-core processor with respect to performance and energy. Because warp processing occurs dynamically and transparently, soft-core warp processing could open the door to a much wider use of FPGA soft-cores.

In this paper, we investigate the benefits of warp processing for soft processor cores. We present a warp processing system consisting of a soft processor core that a designer can implement using any FPGA. While we could potentially target any soft processor core, we focus our efforts on the MicroBlaze processor. By utilizing a warp processor based on a soft processor core, a designer can quickly implement a software system using a low cost FPGA, potentially incorporating several processors, with increased performance and lower energy consumption compared with the soft processor core alone, and comparable with hard-core processors.

MicroBlaze Soft Processor Core

The MicroBlaze soft processor core provided by Xilinx is a 32-bit configurable processor core. A designer can create a system incorporating a MicroBlaze using the Xilinx Platform Studio in which a designer can quickly build a MicroBlaze processor system by instantiating and configuring cores from the provided libraries. Figure 1 presents a simple MicroBlaze system incorporating the MicroBlaze processor along with several components to create a complete system. The MicroBlaze processor utilizes a three-stage pipeline with variable length instruction latencies typically ranging from one to three cycles. The MicroBlaze has a Harvard memory architecture and utilizes two Local Memory Busses (LMB) for instruction and data memory. The system shown in Figure 1 includes two Block RAMs (BRAM), one for instruction memory and one for data memory, whose sizes are user defined. A local memory bus to BRAM interface connects the MicroBlaze with the instruction and data memories. The system also includes two peripherals connected via the On-Chip Peripheral Bus (OPB). After specifying the system architecture and configuring the MicroBlaze processor, the Xilinx Platform Studio tools synthesize the design and create a bitstream for the system as well a generate a set of software libraries that a design can use to interface with the various components in the system. Finally, a designer can compile their application and combine the application's binary with the bitstream to produce the final system bitstream.

Key features of the MicroBlaze processor, as well as other soft processor cores, include the user configurable options that allow a designer to tailor the processor's functionality to their specific design. The MicroBlaze's user-configurable options include configurable instruction and data caches, incorporating a hardware multiplier to enable the mul instruction, incorporating a hardware divider to enable the idiv instruction, and incorporating a barrel shifter to enable the bs and bsi instructions.

Many of the MicroBlaze processor's configurable options can have a significant impact on performance. While the impacts on performance of incorporating or excluding caches is well known and widely understood, the impact of other configurable options such as the inclusion of a hardware barrel shifter is also extremely important, especially in embedded systems in which bit manipulation is often used.

We therefore analyzed two embedded system benchmark applications, brev and matmul, from the Powerstone benchmark suite (which we obtained from Motorola). The critical kernel of the benchmark brev performs an efficient bit reversal but heavily relies on shift operations. If the MicroBlaze processor is configured without the hardware barrel shifter or hardware multiplier, the resulting application binary will perform an n-bit shift by using n successive add operations each of which doubles the values of the variable being shifted. Compared with a MicroBlaze processor including a barrel shifter and multiplier, the absence of these configurable options results in a 2.1X longer execution time for the application brev. For the application matmul, the critical region is a matrix multiplication. Without a hardware multiplier, the compiler will use a software function to perform every multiplication, thereby increasing the execution time for matmul by 1.3X. However, with knowledge of the final software application, a designer can reduce the amount of configurable logic used within the FPGA if they do not require a hardware barrel shifter, multiplier, or divider.

Another potential drawback of the MicroBlaze processor is the lack of floating point instructions, requiring software routines to perform these operations. However, as FPGAs continues to increase in complexity, soft processor cores will likely begin to incorporate more functionality possibly allowing designers to configure the processor with a hardware floating point unit. The most significant drawbacks to using a soft core processor are the performance and energy overhead. Although the MicroBlaze processor has a three-stage pipeline, during the execute phase of the pipeline, instructions have different latencies. For example, an addition operation has a latency of only one cycle, whereas a multiply operation requires three cycles. Other instructions such as branch instructions have latencies anywhere from one cycle to three cycles depending on the instruction and whether or not the branch is taken. However, of the applications we analyzed, most branch instructions had a latency of two cycles, as the compiler often did not utilize the branch delay slot. While the performance overhead can significantly impact the overall energy consumption, FPGAs also consume more power than ASICs or custom designs. This increased power consumption and performance overhead results in a system that consumes more energy than a similar hard-core processor.

MicroBlaze-based Warp Processor

Figure 2 presents a single processor MicroBlaze-based warp processor. The warp processor consists of a main processor with instruction and data caches, an efficient on-chip profiler, a warp configurable logic architecture (WCLA), and a dynamic partitioning module (DPM). Initially, the software application executing on the warp processor will execute only on the MicroBlaze processor. During execution of the application, the profiler monitors the execution behavior to determine the critical kernels within the application. After identifying the critical regions, the dynamic partitioning module re-implements the critical software regions as a custom hardware component within the WCLA using our Riverside On-Chip Partitioning Tools (ROCPART). Extensive discussion of the ROCPART tools is beyond the scope of this paper and has been published in [START_REF] Lysecky | A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning[END_REF][16] [START_REF] Stitt | Dynamic Hardware/Software Partitioning: A First Approach[END_REF]. We highlight the key features in this section enough to better understand the experimental study that we performed.

The MicroBlaze warp processor includes a profiler within the warp processor to determine the critical kernels within the executing application that the warp processor could implement as hardware. Based on the profiler presented in [START_REF] Gordon-Ross | Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware[END_REF], the profiler incorporated in our warp processor design is a non-intrusive profiler that monitors the instruction addresses seen on the local instruction memory bus. Whenever a backward branch occurs, the profiler updates a small cache that stores the branch frequencies.

The dynamic partitioning module executes the ROCPART partitioning and synthesis algorithms. ROCPART first analyzes the profiling results for the executing application and determines which critical region the warp processor should implement in hardware. After selecting the software region to implement in hardware, the DPM accesses the application's software binary by interfacing with the dual ported instruction BRAM. The partitioning tool then decompiles the critical region into a controldataflow graph and synthesizes the graph to create the hardware circuit [START_REF] Stitt | Dynamic Hardware/Software Partitioning: A First Approach[END_REF]. The hardware circuit is then optimized and mapped onto the WCLA by performing technology mapping, placement, and routing to produce the final hardware bitstream [START_REF] Lysecky | Dynamic FPGA Routing for Just-in-Time FPGA Compilation[END_REF] [START_REF] Lysecky | On-chip Logic Minimization[END_REF]. Finally, the DPM configures the configurable logic and updates the executing application's binary code to utilize the hardware within the configurable logic fabric.

Currently, we implement the dynamic partitioning module as another embedded MicroBlaze processor core including separate instruction and data memories, which can either be located onchip or off-chip depending on what is acceptable for a given warp processor implementation. Alternatively, one could eliminate the need for the DPM by executing the partitioning tools as a software task on the main processor sharing computation and memory resources with the main application.

Figure 3 shows the overall organization of our warp configurable logic architecture. The WCLA consists of a data address generator (DADG) with loop control hardware (LCH), three input and output registers, a 32-bit multiplier-accumulator (MAC), and utilizes the unused configurable logic within the FPGA to implement the partitioned critical regions. The configurable logic architecture handles all memory accesses to and from the configurable logic using the data address generator. Furthermore, the data retrieved and stored to and from each array is located within one of the three registers Reg0, Reg1, and Reg2.

32-bit MAC

These three registers also act as the inputs to the configurable logic fabric and can be mapped as inputs to the 32-bit (MAC) or directly mapped to the configurable logic fabric. Finally, the WCLA connect the outputs from the configurable logic fabric as inputs to the three registers using a dedicated bus.

Since warp processing targets critical loops that typically iterate many times before completion, the WCLA must be able to access memory and to control the execution of the loop. Therefore, the WCLA includes a DADG with LCH to handle all memory accesses as well as to control the execution of the loop. The DADG within the WCLA can handle memory accesses that follow a regular access patterns. The DADG and LCH interface with the MicroBlaze system by accessing the dual ported data BRAM to read and write data during the hardware execution. The WCLA also communicates with the MicroBlaze processor using the on-chip peripheral bus.

Ideally, our proposed MicroBlaze-based warp processor would utilize the FPGA's unused configurable logic to reimplement the application's critical regions. However, developing computer aided design tools for existing FPGAs capable of executing on-chip using very limited memory resources is a difficult task [START_REF] Lysecky | Dynamic FPGA Routing for Just-in-Time FPGA Compilation[END_REF] [START_REF] Lysecky | On-chip Logic Minimization[END_REF]. Instead, our MicroBlaze warp processor utilized a simple configurable logic fabric for re-implementing the critical kernels in hardware that we developed simultaneously with a set of lean synthesis, technology mapping, placement, and routing algorithms [START_REF] Lysecky | A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning[END_REF]. By targeting a simplified configurable logic fabric, our ROCPART tools can execute on a small, embedded processor requiring very little memory and execution time while producing good results. Alternatively, we could create a virtual configurable logic fabric by superimposing our custom configurable logic fabric on top of the underlying physical FPGA fabric, which we are currently investigating.

As mentioned earlier, one the benefits of using a soft processor core is the ability for designers to build systems with multiple processors using the same FPGA. The number of processors a designer can incorporate within any given FPGA is only limited by the size of the FPGA itself. However, in building a multi-processor warp processor device, simply instantiating multiple warp processors as shown in Figure 2 would results in a very large overhead as multiple DPMs and WCLAs are not needed to support a multi-processor system. Instead, a single DPM is sufficient for performing partitioning and synthesis for each of the processors in a round robin or similar fashion. Furthermore, one could again implement the partitioning tools as a software task executing on any of the multiple processors.

Figure 4 presents a multi-processor MicroBlaze warp processor. For each individual MicroBlaze processor we include a profiler. While we could create a profiler capable of monitoring all processors simultaneous, the profiler is very small compared with the processor and should not have significant impact on area or energy consumption. The dynamic partitioning module in a multiprocessor system needs to be able to interface to all processors individually. Therefore, we include a simple BRAM Interface that allows the DPM to select which processor's memory to access. Finally, we need to modify our original WCLA to include separate data address generators, loop control hardware, registers, and MAC for each of the processors. However, as the requirements for the applications executing on each of the processors are likely to differ, the critical regions implemented in hardware for the various processors can share the available configurable logic.

Experiments

In determining the performance and energy benefits of warp processing for the MicroBlaze soft processor core, we analyzed the execution time and power consumption of several embedded systems applications from the Powerstone and EEMBC benchmark suites. Our experimental setup considers a MicroBlaze processor system implemented using the Spartan3 FPGA. When implemented on a Spartan3 FPGA, the MicroBlaze processor core has a maximum clock frequency of 85 MHz. However, the remaining FPGA circuits can operate at up 250 MHz. We configured the processor to include a barrel shifter and multiplier, as the applications we considered required both operations.

Figure 6 and Figure 7 present the speedup and energy reduction of the MicroBlaze-based warp processor compared with a standard MicroBlaze processor. We simulated the software application execution on the MicroBlaze using the Xilinx Microprocessor Debug Engine and obtained an instruction trace for each application. We used the instruction trace to simulate the behavior of the on-chip profiler to determine the single most critical region within each application. Using the profiling results, we executed our ROCPART partitioning tools for each application to create the hardware circuit implementations targeting our simple configurable logic fabric. To determine the performance and power consumption of the WCLA, we implemented our configurable logic architecture in VHDL and synthesized the design using Synopsys Design Compiler targeting the UMC 0.18 µm technology library. Then, using the execution traces, we simulated the hardware circuits for each partitioned critical region using the VHDL model of the WCLA to determine the final application performance with warp processing. Finally, we calculated the energy consumption of each of the applications using the equations in Figure 5. With the exception of the configurable logic fabric, we determined the power consumption of the MicroBlaze processor and system components using the Xilinx XPower power estimation tool to determine the dynamic and static power consumption. We also compared the performance and energy consumption of the MicroBlaze processor and MicroBlaze warp processor to several ARM processors. For each application, we determined the execution for the ARM processors using the SimpleScalar simulator ported for the ARM processor [START_REF] Burger | The SimpleScalar Tool Set, version 2.0[END_REF]. Figure 6 presents the speedups of a MicroBlaze-based warp processor and several ARM hard-core processors compared with a MicroBlaze soft processor core. The MicroBlaze warp processor is able to improve the performance of a MicroBlaze system, achieving an average of speedup of 5.8. The largest speedup is for the application brev, achieving a speedup 16.9. As we described earlier, brev's critical kernel is a bit reversal implemented using shift operations and other bit manipulations. However, after partitioning the kernel to hardware, the hardware circuit is much more efficient, requiring only wires to implement the bit reversal. Excluding the application brev, which is a special situation in which a hardware implementation is much more efficient than software, the MicroBlaze warp processor achieves an average speedup of 3.6 over a MicroBlaze processor alone. We note that the MicroBlaze warp processor achieves these performance results using the simple configurable logic fabric and not the more robust native configurable logic of the Spartan3 FPGA. Instead, if we could target the native Spartan3 fabric, we would expect to see additional performance improvements.

Figure 7 presents the normalized energy consumption of the MicroBlaze-based warp processor and several ARM hard-core processors compared with a MicroBlaze soft processor core. While having the lowest clock frequency, the MicroBlaze processor has the highest energy consumption, requiring 48% more energy than the ARM11, which has the second highest overall energy consumption. However, the MicroBlaze warp processor is able reduce the energy consumption by an average of 57%, with a maximum energy reduction of 94% for the application brev. Excluding brev, the MicroBlaze warp processor achieves an average energy reduction of 49%.

While the MicroBlaze warp processor provides increased performance and lower energy consumption compared to the MicroBlaze processor, we also need to compare the MicroBlaze warp processor with readily available hard-core processors. Overall, the MicroBlaze warp processor has better performance than the ARM7, ARM9, and ARM10 processors and requires less energy than the ARM10 and ARM11 processors. The ARM11 processor executing at 550 MHz is on average 2.6X faster than the MicroBlaze warp processor but requires 80% more energy. Furthermore, compared with the ARM10 executing at 325 MHz, the MicroBlaze warp processor is on average 1.3X faster while requiring 26% less energy. Therefore, while the MicroBlaze warp processor is not the fastest nor the lowest energy alternative, the MicroBlaze warp processor is comparable and competitive with existing hard-core processors, while having all the flexibility advantages associated with soft-core processors.

Of course, one could also consider applying warp processing to a single-chip hard-core microprocessor/FPGA device, and in fact that was the original focus our warp processing technique. What we have shown in this paper is that warp processing can make a soft-core FPGA processor competitive with a standalone hard-core processor, which simply expands the usefulness of softcores on FPGAs to cover a broader range of applications with tighter performance and power constraints, providing a competitive alternative to a hard-core processor.

Conclusions

Soft-core processors provided by FPGA vendors give designers the flexibility to configure the processors and enable those designers to quickly build FPGA systems incorporating one or more processors. However, these soft processor cores, such as the MicroBlaze, typically require longer execution times with higher energy consumption compared with hard-core processors, limiting the number of potential applications in which a designer would choose to use a soft processor core. We studied a MicroBlazebased warp processor that dynamically and transparently optimizes the executing application by re-implementing critical software kernels in hardware using the configurable logic available within the FPGA. The MicroBlaze warp processor eliminates the performance and energy overhead by improving performance on average by 5.8X and reducing energy consumption on average by 57%, making them competitive with current hard-core processors. Designers using MicroBlaze warp processors can quickly build FPGA systems incorporating a MicroBlaze or similar soft processor core with performance and energy consumption comparable to standard hard-core processors such as an ARM processor. With warp processing, soft processors cores can be used in a wider range of application in which using a soft-core processor would not have been previously feasible due to performance and/or energy requirements.

Our current future work includes creating physical implementations of warp processing, improving warp processing's tools to provide speedups for a wider range of applications, and making use of advanced on-chip configurable structures for further improvements [START_REF] Stitt | Techniques for Synthesizing Binaries to an Advanced Register/Memory Structure[END_REF].

Figure 1 :

 1 Figure 1: Simple MicroBlaze processor system.

Figure 2 :

 2 Figure 2: MicroBlaze single-processor warp processing system.

Figure 3 :

 3 Figure 3: Warp configurable logic architecture (WCLA) for dynamic hardware/software partitioning.

Figure 4 :

 4 Figure 4: MicroBlaze multi-processor warp processing system.

Figure 5 :

 5 Figure 5: Equation for determining energy consumption after hardware/software partitioning.

Figure 6 :

 6 Figure 6: Speedups of MicroBlaze-based warp processor and ARM7, ARM9, ARM10, and ARM11 (MHz in parentheses) processors compared to MicroBlaze processor alone for various Powerstone and EEMBC benchmark applications.

Figure 7 :

 7 Figure 7: Normalized energy consumption of MicroBlaze-based warp processor and ARM7, ARM9, ARM10, and ARM11 (MHz in parenthesis) processors compared to MicroBlaze processor alone for various Powerstone and EEMBC benchmark applications.

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05)

Acknowledgements

This research was supported in part by the National Science Foundation (CCR-0203829), the Semiconductor Research Corporation (2003-HJ-1046G), and Xilinx Corp.