Zhi Guo
email: zguo@cs.ucr.edu

Betul Buyukkurt
email: abuyukku@cs.ucr.edu

Walid Najjar
email: najjar@cs.ucr.edu

Kees Vissers

Optimized Generation of Data-path from C Codes for FPGAs

FPGAs, as computing devices, offer significant speedup over microprocessors. Furthermore, their configurability offers an advantage over traditional ASICs. However, they do not yet enjoy high-level language programmability, as microprocessors do. This has become the main obstacle for their wider acceptance by application designers.

ROCCC is a compiler designed to generate circuits from C source code to execute on FPGAs, more specifically on CSoCs. It generates RTL level HDLs from frequently executing kernels in an application. In this paper, we describe ROCCC's system overview and focus on its data path generation. We compare the performance of ROCCCgenerated VHDL code with that of Xilinx IPs. The synthesis result shows that ROCCC-generated circuit takes around 2x ~3x area and runs at comparable clock rate.

Introduction

Continued increases in integrated circuit chip capacity have led to the recent introduction of Configurable Systemon-a-Chip (CSoC), which has one or more microprocessors integrated with a field-programmable gate array (FPGA) as well as memory blocks on a single chip. In these platforms both the FPGA fabric, as well as the embedded microprocessors are essentially programmed using software. The earliest example is the Triscend E5 followed by the Triscend A7 [START_REF]Triscend A7 Configurable System on a Chip Family[END_REF], the Altera Excalibur [START_REF] Corp | Excalibur: System-on-a-Programmable[END_REF], and Xilinx Virtex II Pro [START_REF]IBM and Xilinx Team[END_REF]. The capabilities of these platforms span a wide range with the Triscend A7 at the low end and the Xilinx Virtex II Pro 2VP125 at the high-end. These amazing computing devices have the flexibility of software and have been shown to achieve very large speedups, ranging from 10x to 100x, over microprocessors for a variety of applications including image and signal processing [START_REF] Chen | An FPGA Implementation of the Two-Dimensional Finite-Difference Time-Domain (FDTD) Algorithm[END_REF] [5][6]. Such speedups come from large-scale parallelism made possible by high-capacity FPGAs, as well as from customized circuit design. The main problem standing in the way of wider acceptance of CSoC platforms is their programmability. Application developers must have an extensive hardware expertise, in addition to their application area expertise, to develop efficient designs. Presently, most CSoCs are programmed manually. The main drawback of this approach is that it is very labor intensive and requires large design times. Some commercial effort in programming FPGAs have been proposed by companies such as Synopsys [7] and Tensillica [8]. Their focus is on moving simple loops to hardware or on instruction-set extension.

Optimizing compilers for traditional processors have benefited from several decades of extensive research that has led to extremely powerful tools. Similarly, electronic design automation (EDA) tools have also benefited from several decades of research and development leading to powerful tools that can translate VHDL and Verilog code, and recently SystemC [START_REF]SystemC Consortium[END_REF] code, into relatively efficient circuits. However, little work has been done to combine these two approaches. In other words, work is still needed to compile a high-level language program, based on C/C++/Java, with software level optimizations with the intent of generating a hardware circuit. Obviously, it is neither practical nor desirable to translate the whole program into hardware. It is therefore imperative to provide the programmer with tools that would help in identifying which code segments ought to be mapped to hardware as well as the cost and benefit tradeoffs implied.

Compiling to CSoCs and FPGAs in general is challenging. Traditional CPUs, including VLIW, have a fixed hardware platform. Their architectural features may or may not be exposed to the compiler. FPGAs, on the other hand, are completely amorphous. The task of an FPGA compiler is to generate both the hardware (data path) and the sequence of operations (control flow). This lack of architectural structure, however, presents a number of advantages. (1) The parallelism is very high and limited only by the size of the FPGA device or by the data memory bandwidth. (2) On-chip storage can be configured at will: registers are created by the compiler and distributed throughout the data path where needed, thereby increasing data reuse and reducing re-computations or accesses to memory. (3) Circuit customization: the data path and sequence controller are tailored to the specific computation being mapped to hardware. Examples include customized data bit-width and pipelining.

The objective of the ROCCC (Riverside Optimizing Configurable Computing Compiler) project is to design a high-level language compiler targeting CSoC. It takes high-level code, such as C or FORTRAN as input and generates RTL VHDL code for the FPGA and C code for the CPU. In this paper we describe the overall structure of the compiler and emphasize the data path generation component. We compare the clock speed and area of automatically generated circuits to a number of IP codes available on the Xilinx web site. The results show that the speed is within 10% while the area is larger by a factor of 2 to 3. The work in [START_REF] Frigo | Evaluation of the Streams-C C-to-FPGA Compiler: An Applications Perspective[END_REF][26] has compared generated code with hand written VHDL. Both have shown a factor of 2 on the performance decrease of the generated code in area and clock rate. ROCCC is built upon the knowledge acquired from SA-C and Streams-C. We experimentally show that the resultant VHDL is much closer to the handwritten one.

The rest of this paper is organized as follows. The ROCCC compiler is introduced in section 2. Related work is discussed in section 3. Section 4 presents ROCCC compiler RTL code generation for the controller, the buffer and the data path. Experimental results are reported in section 5. Section 6 concludes the paper.

ROCCC System Overview

Figure 1 shows the overview of the ROCCC compiler. The profiling tool set has been described in a prior publication [START_REF] Suresh | Profiling Tools for Hardware/Software Partitioning of Embedded Applications[END_REF]. It identifies the frequently executing code kernels in a given application. ROCCC's objective is to compile these kernels to HDL code, which is synthesized using commercial tools.

The ROCCC system is built using SUIF [START_REF]SUIF Compiler System[END_REF] and Machine-SUIF [START_REF]Machine-SUIF[END_REF] platforms. SUIF IRs (intermediate representations) provide abundant information about loop statements and array accesses. ROCCC performs loop level optimizations on SUIF IRs. Loop unrolling for FPGAs requires compile time area estimation. The work reported in [START_REF] Kulkarni | Fast Area Estimation to Support Compiler Optimizations in FPGAbased Reconfigurable Systems[END_REF] shows that in less than one millisecond and within 5% accuracy compile time area estimation can be achieved. Information to generate high-level units, such as controllers and buffers, is also extracted from SUIF IRs.

Machine-SUIF analysis and optimization passes, such as Control Flow Graph (CFG) library [START_REF] Holloway | Machine SUIF Control Flow Graph Library[END_REF], Data Flow Analysis library [START_REF] Holloway | The Machine SUIF Bit-Vector Data-Flow-Analysis Library[END_REF] and Static Single Assignment library [START_REF] Holloway | The Machine-SUIF Static Single Assignment Library[END_REF], are used to generate the data path.

ROCCC's conventional optimizations include constant folding, loop unrolling, etc. Full loop unrolling converts a for-loop with constant bounds into a non-iterative block of code and therefore eliminates the loop controller. In addition to these conventional optimizations, at loop level ROCCC performs FPGA-specific optimizations, such as loop strip-mining, loop fusion, etc. At storage level and circuit level, ROCCC's optimizations are closely related with HDL code generation and are discussed in section 4.

The restrictions on the C code that can be accepted by the ROCCC compiler, for mapping on an FPGA fabric, include no recursion, no usage of pointers that cannot be statically unaliased. Function calls will either be inlined or whenever feasible made into a lookup table.

Related Works

Many projects, employing various approaches, have worked on translating high-level languages into hardware. SystemC [START_REF]SystemC Consortium[END_REF] is designed to provide roughly the same expressive functionality of VHDL or Verilog and is suitable to designing software-hardware synchronized systems. Handle-C [START_REF]Handel-C Language Overview[END_REF], as a low level hardware/software construction language with C syntax, supports behavioral descriptions and uses CSP-style (Communicating Sequential Processes) communication model. SA-C [START_REF] Najjar | From Algorithms to Hardware -A High-Level Language Abstraction for Reconfigurable Computing[END_REF] is a single-assignment high-level synthesizable language. Because of special constructs specific to SA-C (such as window constructs) and its functional nature, its compiler can easily exploit data reuse for window operations. SA-C uses pre-existing parameterized VHDL library routines to perform code generation in a way that requires a number of control signals between components, and thereby involves extra clock cycles and delay. Our compiler avoids spending clock cycles on handshaking by focusing more on the compile-time analysis. It takes a subset of C as input and does not involve any non-C syntax.

Streams-C [START_REF] Gokhale | Stream-oriented FPGA computing in the Streams-C high level language[END_REF] relies on the CSP model for communication between processes, both hardware and software. Streams-C can meet relatively high-density control requirements. However, it does not support accesses to two-dimension arrays and therefore image processing applications, including video processing, must be mapped manually. This makes it very awkward to efficiently support algorithms that rely on sliding windows. For one-dimension input data vector, such as a onedimension FIR filter, Streams-C programmers need to manually write data reuse in the input C code in order to make sure that a data value is retrieved only once from external memory.

SPARK [START_REF]SPARK project[END_REF] is another C to VHDL compiler. Its transformations include loop unrolling, common subexpression elimination, copy propagation, dead code elimination, loop-invariant code motion etc. SPARK does not support multi-dimension array accesses.

The ROCCC Compiler

ROCCC targets high computational density, low control density applications. Figure 2 shows the execution model. An engine moves the data from off-chip to a BRAM storage. The compiler-generated circuit accesses the arrays in BRAM and stores the output data into another BRAM, from which an engine retrieves data into the off-chip memory. Inside the compiler-generated circuit, the data path is fully pipelined. The controllers and buffers are in charge of feeding input data and retrieving output data to and from the data path.

Controller and Buffers

ROCCC's scalar replacement transformation converts, for instance, the segment in Figure 3 (a) into the segment in Figure 3 (b). We can see that scalar replacement isolates memory access from calculation.

The highlighted region of code is exported in the form of Figure 3 (c) and goes to the data path generator. At the same time, the loop statement and memory load/store code are used to generate the controllers and buffers. The controllers include address generators, which export a series of memory addresses according to the memory access pattern, and a higher-level controller, which controls the address generators. They are all implemented as pre-existing parameterized FSMs (finite state machine) in a VHDL library.

One of the major reasons that account for FPGA's speedup over general-purpose processor is that FPGA is capable of providing optimized I/O interface between data path and memory units [START_REF] Guo | A Quantitative Analysis of the Speedup Factors of FPGAs over Processors[END_REF]. For example, each iteration of the for-loop in Figure 3 (a) is essentially an operator on a window of five consecutive array elements. The window slides on the array. Two adjacent windows have four input data in common and only one new input data per window/iteration. ROCCC, as a high-level synthesis compiler, uses the knowledge of memory access pattern from the input code, such as the code shown in Figure 3 (b), to automatically generates an intelligent buffer, called smart buffer, based on the bus size, window size, data size and sliding-window stride. This buffer unit is able to reuse live input data, clean unused data and export the present valid input data set (the 5-data window in Figure 3 (b)) to the data path [START_REF] Guo | Input Data Reuse In Compiling Window Operations Onto Reconfigurable Hardware[END_REF].

Data Path Generation

Before building the data path, a few preparation passes are done both at the front-end and back-end. Then, ROCCC's back-end passes perform the analysis, optimization and data path generation.

Preparation Passes

ROCCC uses Machine-SUIF virtual machine (SUIFvm) [START_REF] Holloway | Machine-SUIF SUIFvm Library[END_REF] intermediate representation as the back-end IR. The original SUIFvm assembly-like instructions, by themselves, cannot completely cover HDLs' hardware description functionality. On the other side, the front-end analysis may assist and simplify the data path generation at back-end. Besides back-end data flow analysis, ROCCC performs high-level data flow analysis at front-end and the analysis information is transferred through pre-defined macros to assists back-end hardware generation.

Figure 4 (b) shows an accumulator after applying scalar replacement in C. The variable sum is detected as a feedback signal. Figure 4 (c) shows the resultant segment in C, in which macro ROCCC_load_prev() and macro ROCCC_store2next() annotate the signal feedback.

After applying scalar replacement and front-end dataflow analysis, the function that describes the scalar computing, like the codes shown in Figure 3 (c) or Figure 4 (c), is fed into Machine-SUIF. ROCCC performs circuit level optimizations and eventually generates data path on a modified version of the Machine-SUIF virtual machine (SUIFvm) [START_REF] Holloway | Machine-SUIF SUIFvm Library[END_REF] intermediate representation.

Before fed to ROCCC's passes, the virtual machine IR first undergoes Machine-SUIF Static Single Assignment and Control Flow Graph transformations. At this point, control flow graph information is visible and every virtual register is assigned only once.

The preserved macros are converted into ROCCCspecific opcodes. For example, ROCCC_load_prev() and ROCCC_store2next() in Figure 4

Data Path Building

Each instruction that goes to hardware is assigned a location in the data path. We add new fields into Machine-SUIF IR to record the location of each arithmetic, logic or register copying instruction's location. For example, Figure 6 shows the data path for the C code list in Figure 5. We maximize instruction level parallelism. All the input and output operands are copied to the entry or exit of the data flow, respectively. A virtual register's definition and reference should be adjoining in the data flow. If not, extra register copying instructions are added to satisfy so.

The compiler first builds data path for each non-null node in the CFG, as node 1 through node 4 shown in Figure 6. To parallelize alternative branches, the compiler adds a new mux node between alternative branch nodes and their common successor node, for instance, node 7 in Figure 6. A new pipe node (node 6 in Figure 6, for instance) is added to copy live variables from alternative branches' parent node to their common successor node.

In Figure 6, node 6 and 7 are called hard nodes since they only appear in hardware and have no equivalence in software. Nodes 1 through 4 are thereby called soft nodes. Notice that if we only consider soft node, vr11 in node 4 is vr11 in node 1, the same case as of vr13. Therefore, the soft nodes, by themselves, will have the same behavior on a CPU compared with the whole data path on a FPGA.

Data Path Pipeline

ROCCC automatically places latches in a data path to pipeline it. The latch location in a node is decided based on the delay estimation of instructions, which is beyond this paper's scope.

The latch location also satisfies special opcodes' requirements. For example, SNX instruction must have a latch to store the feedback signal to the corresponding LPR instruction. Figure 7 shows the data path of Figure 4 (c).

After data path pipelining, each pipeline stage is an instance of single iteration in the forloop body.

VHDL Code Generation

Experimental Results

We compare the hardware performance generated from Xilinx IP cores and ROCCC-generated VHDL code. We use Xilinx ISE 5.1i and IP core 5.1i. All the Xilinx IP cores and ROCCC-generated VHDL code are synthesized targeting a Xilinx Virtex-II xc2v2000-5 FPGA.

All the benchmarks in Table 1 are picked from Xilinx IP core except the wavelet engine. The input and output variables of ROCCC equivalents have the same bit sizes as that of the IP cores.

Bit_correlator counts the number of bits of an 8-bit input data that are the same as of a constant mask. Mul_acc is a multiplier-accumulator, whose input variables are a pair of 12-bit data. Udiv is an 8-bit unsigned divider. Square_root calculates a 24-bit data's square root. Cos's input is 10-bit, output, 16-bit. The arbitrary LUT has the same port size as that of cos. FIR is two 5-tap 8-bit constant coefficient finite impulse response filters, whose bus sizes are 16-bit. DCT is a one-dimension 8-data discrete cosine transform. The input data size and output data size are 8-bit and 19-bit, respectively. For Xilinx IP FIR and DCT, the multiplications with constants are implemented using distributed arithmetic technique, which performs multiplication with lookup-table based schemes. Therefore, we set the synthesis option 'multiplier style' as 'LUT' for the ROCCC-generated DCT and FIR.

The second and the third column of Table 1 show Xilinx IP cores' clock rate and device utilization and the forth and the fifth column show ROCCC's corresponding performance. %Clock is the percentage difference in clock rate of ROCCC-generated VHDL compared to Xilinx IP. %Area is the percentage difference in area of ROCCCgenerated VHDL compared to Xilinx IP. Bit-correlator, udiv and square root consist of a number of bit manipulations. The C input, as a high-level code, is not good at describing bit operations and therefore is one of the major causes of the performance difference. Xilinx mul_acc IP has a control input signal nd (new data) whose Boolean value true indicates the present data is valid. In C code, we describe the equivalent behavior using if-else statement whose condition evaluates Boolean input nd. Thus, extra nodes and latches are added to support the alternative branch and take extra area. We used to convert this C code by multiplying nd with the new input data instead of using if-else statement. Though one more multiplier was used, the overall area and clock rate performance was better than the one listed in Table 1. Obviously, this is not compile level optimization. But at the same time, it shows one of high-level synthesis's advantages: ease to do algorithm level optimizations. In terms of lookup tables, ROCCC-generated VHDL code instantiates Xilinx IP cores. Therefore, they have exactly the same performance. In Xilinx Virtex-II, 10-bit-input-16bit-output cos/sin lookup table stores only half wave, which is one of the reasons that this cos/sin lookup table utilizes less area compared with the arbitrary ROM lookup table with the same port size. Fir operates on an array. Basically, a 5-data window slides on the one-dimension array. ROCCC generates smart buffer to reuse the previous input data. The FIR's data path consists of multipliers, adders/subtracters and no branch. ROCCC fits this type of algorithms and gets comparable performance with IP cores. Like FIR, DCT has high computational density and no branch. The throughput of Xilinx DCT IP is one output data per clock cycle, while ROCCC's throughput is eight output data per clock cycle. Therefore, though ROCCCgenerated DCT runs at a lower speed (73.5%), the overall throughput of ROCCC-generated circuit is higher. Both ROCCC DCT and Xilinx IP DCT explore the symmetry within the cosine coefficients. The last row in Table 1 shows an implementation of a two-dimension (5, 3) wavelet transform engine, which is the standard lossless JPEG2000 compression transform. This wavelet transform engine includes the address generator, smart buffer and data path. The ROCCC-generated circuit is compared with a handwritten one. We derive bit width only based on port size and opcodes. More aggressive bit narrowing, performed by users or/and the compiler, may reduce device utilization.

Conclusion

The reconfigurable computing paradigm is a powerful computing model that has a lot of potential for longrunning or streaming applications that are somehow regular in nature. The main obstacle to its use is its programmability. Handwritten HDL code for large scale applications is not the most desirable approach. Automatic compiler generation of HDL code from high-level languages is very challenging.

The ROCCC compiler generates VHDL for reconfigurable computing from high-level languages, such as C or Fortran. ROCCC performs loop level, storage level and circuit level optimizations. In this paper we have mainly presented its data path generation. At front-end, the compiler performs high-level data flow analysis and transfers the analysis information through preserved macros. At back-end, the compiler explores low-level parallelism, pipelines data path and narrows inner signals' bit sizes. ROCCC supports lookup tables through automatically instantiating pre-existing lookup table IPs or ROM IPs.

We compared the performance of ROCCC-generated VHDL code with that of Xilinx IPs. The synthesis result shows that ROCCC-generated circuit takes around 2x ~3x area and runs at comparable clock rate. ROCCC performs better on high computational density examples than on high control density ones.

Figure 2 -

 2 Figure 2 -The Execution Model

Figure 3 -

 3 Figure 3 -A 5-tap FIR in C

  ROCCC generates one VHDL component for each CFG node that goes to hardware. In a node, every virtual register is single assigned and is converted into wires in hardware. All arithmetic opcodes in SUIFvm have corresponding functionality in IEEE 1076.3 VHDL with the exception of division. Arithmetic, logic and copying instructions become combinational or sequential VHDL statement according to int sum = 0; for ( i = 0; i < 32; i++) { sum = sum + A[i]; } (a) int sum = 0; for ( i = 0; i < 32; i++) { main_Tmp0 = A[i]; sum = sum + main_Tmp0; } (b) int sum = 0; void main_dp(int main_Tmp0, int* main_Tmp1) { int main_dp_Tmp2; main_dp_Tmp2 = ROCCC_load_prev(sum) + main_Tmp0; ROCCC_store2next(sum, main_dp_Tmp2); *main_Tmp1 = sum; } (c) (a) -An accumulator in original C code (b) -The accumulator after scalar replacement (c) -The C code fed into data path generator after detecting feedback variable and adding preserved macros

Figure 4 -Figure 5 -

 45 Figure 4 -An Accumulator in C

Figure

  Figure 6 -The Alternative Branch Data Path

  whether the instruction needs latched or not. A LUT instruction invokes an instantiation of a lookup table component. If the lookup table is a pre-existing one, such as a cos lookup table, the compiler automatically includes the existing component. Otherwise, for example, if a user wants to have a probability distribution function lookup table, the compiler instantiates the lookup table as a regular ROM IP core unit in the VHDL code. The only thing the user needs to do is to edit a pure text initialization file, which defines the lookup table's content. By adding more data type in Machine-SUIF, ROCCC supports any signed and unsigned integer type up to 32 bit. The compiler infers the inner signals' bit size automatically.

Table 1 :

 1 A comparison of hardware performance from Xilinx IPs and ROCCC-generated VHDL code. (*The wavelet engine is not from the Xilinx IP, it is written in VHDL)

		Xilinx IP		ROCCC
	Example	Clock (MHz) Area (slice) Clock (MHz) Area (slice) %Clock %Area
	bit_correlator	212	9	144	19	0.679	2.11
	mul_acc	238	18	238	59	1.00	3.28
	udiv	216	144	272	495	1.26	3.44
	square root	167	585	220	1199	1.32	2.05
	cos	170	150	170	150	1.00	1.00
	Arbitrary LUT	170	549	170	549	1.00	1.00
	FIR	185	270	194	293	1.05	1.09
	DCT	181	412	133	724	0.735	1.76
	Wavelet*	104	1464	101	2415	0.971	1.65

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE


E Echevarria-Bonet

D P Rojas
email: d.rojas@upm.es

E Espeso

Rodríguez Fernández

E Bauer

Sébastien Burdin

S Magalhaes

L Fernandez Barquín

C Echevarria-Bonet

J I Espes

J Rodrígue Fernández

L Rodríguez Fernández

E Baue

S G Magalhães

L Fernández Barquín

Breakdown of the coherence effects and Fermi liquid behavior in YbAl 3 nanoparticles

Keywords: Yb nanometric alloys, Kondo lattice, single impurity, electrical resistivity, quantum interference effects

niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

1

In the framework of this model, a large number of SCES can be classified as Kondo lattice systems, and these are viewed as a dense periodic array of magnetic ions, as opposed to single impurity systems, in which the impurities are assumed to be well separated, with no mutual coherence. The possibility that long range Fermi liquid coherence may break down in a Kondo alloy has opened new perspectives, since it may lead to the formation of non-trivial new quantum states [6][7][8]. Until now, this issue has mainly been experimentally explored in bulk materials by diluting the active Kondo ion with a nonmagnetic one (in Ce alloys), paying an special attention to the crossover from Kondo lattice to single impurity regime detected by electrical resistivity measurements [9][10][11][12][13]. Less attention has been focused on Yb alloys than Ce systems, with only a few reports (see, for instance, [14][15][16]), where even this crossover has hardly been explored [17].

Introduction

The behavior of magnetic impurities in a metallic host encapsulated by the well-known Kondo effect has been one of the most challenging problems in condensed matter physics [START_REF] Hewson | The Kondo Problem to Heavy Fermions[END_REF]. This phenomenon is a fine e xample o f d evelopment of electronic correlations in a solid, and in recent years it has witnessed a resurgence with the development of nanoelectronic devices and novel nanostructured materials [START_REF] Goldhaber-Gordon | [END_REF]3]. However, there is probably no other area where the presence of the Kondo effect is so fundamental as in strongly correlated electron systems (SCES) (Ce-, U-, and Yb-based compounds) [START_REF] Coleman | Handbook of Magnetism and Advanced Magnetic Materials ed H Kronmüller and S Parkin[END_REF]. Within the existing theories, the Kondo lattice model [START_REF] Doniach | [END_REF] has been successfully applied to explain the influence of the Kondo effect on the physical properties of this kind of material.

It is also remarkable that most of the reports in SCES have been constrained to macroscopically well-crystallized bulk materials. However, it appears evident that the development of molecular beam epitaxy techniques has-very recently allowed the production of two dimensional structures based on Ce Kondo lattice systems, known as 'Kondo superlattices' [18]. The reduction of the dimensionality results in new types of electronic state, as observed in CeIn 3 -LaIn 3 superlattices, where an enhancement of the effective electron mass and non-Fermi liquid behavior were underlined [19]. Another example is the fabrication of multi-scale microstructures spanning from atomic to nanometer and mesoscopic scales in YbAl 3 alloy, showing a simultaneous enhancement of the electron and phonon transport properties [20].

Following this alternative route, novel phenomena appear when reducing the size of these materials to the nanometer scale. In particular, it is appealing to investigate more deeply the eventual variations in the relation to the role of Kondo interaction, especially in Kondo lattice compounds [21]. There are only a few examples of experimental results on Ce alloys ( [22,23] and references therein), and also some theoretical approaches (see, for instance, [24][25][26]). In Yb systems, a significant example is that of nanosized YbAl 3 particles, which exhibit a decrease of Yb valence with the size reduction. This decrease has been attributed to the bonding loss of the surface atoms [27]. More recently, changes in valence with size reduction in REPb 3 (RE = Eu, Yb) alloys have also been observed [28]. For nanosized YbAl 3 , the bulk counterpart of this alloy is an archetypal intermediate valence system, which has been thoroughly studied in the past. The existence of energy scales related to coherence and Kondo effects allows the classification of this alloy as a Kondo lattice system [14]. Electrical resistivity results indicate a decrease in scattering around 100 K [29]. There are also broad maxima around 100 K in the magnetic susceptibility and the magnetic contribution to the specific heat related to an energy scale (Kondo temperature (T K = 500-670 K)) [14,30,31], as also found in nanosized YbAl 3 alloys [27]. In this kind of material, with a Kondo temper ature higher than 500 K, crystalline field effects are found to play a secondary role [START_REF] Hewson | The Kondo Problem to Heavy Fermions[END_REF]14,30,32]. Moreover, studies on the Yb 1-x Lu x Al 3 series of alloys have shown that according to magnetic susceptibility and specific heat measurements, the appearance of a second energy scale at 40 K in the intermediate valence Kondo lattice YbAl 3 is a true coherence effect [14]. In addition, a reduction of Kondo lattice effects in Yb 1-x Lu x Al 3 has been observed by soft x-ray photoelectron spectroscopy, with behavior in good agreement with the single impurity Anderson model [15]. However, it is interesting to note that details of these changes in the Kondo lattice behavior have not so far been explored by means of electrical resistivity (ρ(T)) measurements in this Yb-substituted series, despite its representing a valuable source of evidence to disclose the evolution of the coherence effects and the Kondo regime in strongly correlated Yb and Ce compounds. The Fermi liquid regime (∝T 2 ) at low temperatures and coherence effects-hallmarks of Kondo lattice behavior-can easily be identified by measuring electronic transport properties.

In considering the electronic properties of nanosized YbAl 3 [27], and those of the bulk alloy noted above, it is relevant to scrutinize the influence of the size reduction on the electronic transport properties (electrical resistivity), and how the Kondo lattice behavior and the Fermi liquid ground state (T 2 dependence at low temperatures) are affected; these together constitute the main aims of this work. This will represent a definite step forward within SCES systems (Ce, Yb, U alloys). Additionally, the results are compared with that obtained for the non-magnetic reference LuAl 3 nanometric alloy, and with the effect of dilution by non-magnetic Lu in bulk YbAl 3 alloy, also using the electrical resistivity.

Experimental

Nanocrystalline LuAl 3 alloy was prepared by high-energy mechanical milling of a starting bulk alloy. The alloy was then crushed and milled in a planetary high-energy ball system (Retsch PM 400/2) at a rotation speed of 200 rpm, using a container and balls made of tungsten carbide-a similar procedure to that already used in the study of YbAl 3 and other Rare Earth nanoalloys [27,33]. The bulk Yb 0.2 Lu 0.8 Al 3 alloy was prepared in an arc furnace from constituent elements Yb (Alfa-4N), Lu (Alfa-4N) and Al (Alfa-5N). Transmission electron microscopy (TEM) was performed in a JEOL JEM 2100 microscope. X-ray diffraction measurements were performed at room temperature with a Bruker D8 Advance diffractometer using Cu-Kα radiation. Electronic transport properties were measured by the four probe method in a Quantum Design PPMS device. For the electrical resistivity measurements, the milled powder was first pressed in a press pellet die. A disk was then obtained, which had to be cut into a parallelepiped shape. The sample bar was of a typical length (10 mm) and area (2 × 2.5 mm 2 ). Our in-house holder consisted of four spring-loaded pins. The pin holder was screwed on top of the sample until a certain deformation was observed in the springs. The spring-loaded pins were rounded to ensure excellent contact.

Results

Figure 1 shows the x-ray diffraction patterns and results of Rietveld refinement of 70 h milled YbAl 3 (a) and LuAl 3 (b) alloys. The Rietveld analysis of x-ray data for 70 h milled YbAl 3 alloy (Bragg factor: R B = 10%) provided the unit-cell parameter a = 4.2037 (7) Å, mean grain size D XRD = 12 (2) nm and lattice strain η = 0.37(3)%, in agreement with the previously reported results [27]. For the sample LuAl 3 milled for 70 h, with a Bragg factor ( R B = 7%), values of a = 4.1918(4) Å, D XRD = 10(2) nm and η = 0.64(3)% are calculated. The structural characterization was completed, collecting TEM images. Figures 1(c) and (d) show representative high resolution transmission electron microscopy images of the 70 h milled YbAl 3 and LuAl 3 nanoparticles. The figures show a single YbAl 3 particle with a mean diameter of 14 nm (figure 1(c)) and of 11 nm for LuAl 3 nanoparticle (figure 1(d)). The lattice planes can be clearly observed, which indicates that the nanoparticles are crystalline at the core. These values of the mean size of the nanoparticles are near to those obtained by the analysis of the x-ray diffraction data. with the milling process. For 70 h milled YbAl 3 alloy, there are two important features that indicate a remarkable difference from the bulk sample: the high temperature slope; and a minimum around 15 K, as indicated by the marker-visible in more detail in figure 2(b). There is also a broad hump in the 70 h milled YbAl 3 alloy. The appearance of this hump is typical in the magnetic contribution to ρ(T) of intermediate valence Kondo lattice systems-as observed, for instance, in intermediate-valence YbCuAl [34]. When coming down from high temperatures in 70 h milled YbAl 3 , the ρ(T) increase can be attributed to the incoherent Kondo scattering (high temperature scale-T K = 670 K [14]) until the decrease below T max = 125 K. Thus, the contribution to the electrical resistivity in 70 h milled YbAl 3 (see figure 2(b)) basically comes from the magnetic scattering and the residual resistivity terms. This suggests that the disorder provoked by the milling process induces an increase of scattering by defects in the crystal lattice, starting to play a more significant role that electron-phonon scattering. This fact has been observed in other milled Rare Earth-based alloys, where the electrical resistivity has shown a significant reduction of the high temperature slope with the increase of the milling time, with values of residual resistivity ratio (RRR) = ρ 300 K/ρ 4 K changing from 1.6 to 1.1 [35].

On the other hand, a drastic change (although relatively reduced) in the behavior is observed at low temperatures in such a milled sample with respect to the bulk alloy, with a marked upturn and the presence of a minimum around 15 K, as shown in figures 2(a) and (b). Specifically, there is a small upturn in YbAl 3 20 h ( D XRD ≈ 19 nm [27]), which demonstrates that the appearance of the minimum at 70 h alloy is not casual but the result of a definite tendency (see figure 2(c)). The consequence of this minimum is a deviation from standard Fermi liquid behavior, as shown in figure 3, when comparing the bulk and 70 h milled YbAl 3 alloy samples.

To analyze the origin of such a minimum in ρ(T), it is pertinent to check ρ(T) in LuAl 3 milled for 70 h. This will make it possible to test whether the minimum is observed in a conventional metallic alloy of a similar nanometric structure. In this case (see figure 4(a)), the shape of the resistivity curve is that of a typical metal. Curiously, it also displays a minimummuch shallower than that in 70 h milled YbAl 3 -as shown in detail in the inset of figure 4(a). This last feature could be intuitively interpreted as being due to additional contributions around the minimum in the Yb-based alloy, which conjecture we will address below.

The analysis of the different contributions to ρ(T) in disordered (amorphous) metals and nanocrystalline alloys is not a simple task. Several mechanisms exist that could provide a reasonable interpretation for the increase of the electrical resistivity at low temperatures for the nanometric 70 h milled YbAl 3 and LuAl 3 alloys. To facilitate the interpretation, we will describe our rationale step-by-step. Firstly, it could be expected the low temperature upturn be due to eventual changes in the density of carriers, which are commonly found in semiconducting materials and hopping conductivity. In the second step, we will discuss quantum interference effects (QIE) usually observed in compounds of amorphous nature [36,37]. Finally, a third plausible approach to quantify is the role of an eventual Kondo effect in the Yb sample; this will be discussed as another extra scattering source frequently present in SCES Yb alloys.

Regarding the first mechanism, our ρ(T) measurements indicated an ohmic dependence (see figure 4(b)), thus providing reasonable evidence for metallic conductivity. This rules out the influence of oxides such as Yb 2 O 3 on ρ(T). The presence of this oxide (less than 3%) of the sample) has been previously detected in bulk and milled YbAl 3 alloys [27]. Consequently, this ohmic dependence of ρ(T) also eliminates the possibility of hopping conductivity, based on Mott metalinsulator transition, at least with an exponential dependence [START_REF] Kittel | Introduction to Solid State Physics[END_REF]. Secondly, an electrical resistivity minimum has been been widely observed in amorphous materials of high ρ 0 ( 80 µΩ cm). The high-energy milling process usually leads to sizeable lattice strains and deformations, thus giving rise to a poorly crystallized environment at the very local scale [START_REF] Echevarria-Bonet | [END_REF]. Therefore, it would not be surprising to detect some influence of these effects on ρ(T). Quantum electron interaction effects [36] entail two corrections, namely the electronelectron interaction (EEI) and the weak localization (WL). In the following, we will briefly comment on both effects. Although EEI and WL introduce temperature dependent corrections to resistivity, in three-dimensional disordered metals at low temperatures, the contribution to resistivity from the EEI effects dominates over that due to WL effects [36,40]. Assuming the existence of EEI, the correction to conductivity (σ) is derived as

∆σ ee = 1.3 √ 2 e 2 2πh F 0 2πk B T hD , (1)
where

D = v 2 F τ
3 is the diffusion constant, in terms of the Fermi velocity v F and the relaxation time τ. F 0 is a screening term which equals 4/3 in the absence of any applied magnetic field. Experimental reports revealing the ρ ∝ - √ T dependence have been extensively published for disordered metals [37]. On the other hand, electron wave propagation-away from a classical interpretation-allows a variety of paths, with the existence of loops of interference between the electron waves, giving rise to an effective localization. If all particles returned back to the origin, then ρ → ∞, and full localization would be achieved.

An ideal approach to determine the influence of EEI effects is thus to include ρ ∝ - √ T. As shown in figure 5(a), it is possible to fit a linear variation ( √ T dependence) for 70 h milled LuAl 3 alloy. This supports, experimentally, the former assumption: the mechanism related to the electrical resistivity minimum in LuAl 3 is that due to quantum corrections.

Regarding the YbAl 3 nano (70 h milled alloy), the contribution below the minimum shows an extra contribution. Let us first consider that for T < T min there is a major contribution from QIE effects, as occurs in LuAl 3 . The fit considering only the - √ T term is not satisfactory (see figure 5(b)), thus suggesting the presence of (an)other, more important, scattering mechanism(s). In the SCES Yb systems we presented above, there could exist a contribution stemming from the Kondo effect (ρ ∝ -ln(T)) [START_REF] Hewson | The Kondo Problem to Heavy Fermions[END_REF]. In this sense, we have found that the low temperature data (T < 7 K), is well described according to the -lnT dependence; the results are displayed in figure 5(c). This could indicate the presence of an additional temperature scale (T * = 7 K) related to the onset of an eventual Kondo contribution at low temperatures, different from the high T K temperature scale.

Discussion

The outcome of the foregoing analysis is that the experimental evidence is explained by both QIE and Kondo interaction, which are responsible for the low temperature upturn below T min . The milling of the bulk YbAl 3 results in an ensemble of nanoparticles randomly dispersed and in contact, forming a granular alloy. It is commonly accepted that nanoparticles can be generally described as a two-component system, consisting of core nanocrystallites and grain or interphase boundary components [41]. The thickness of the grain boundary is commonly assumed around 1 nm. At grain boundaries, more disorder is expected, as compared to the core of nanoparticles.

On the one hand, the nanometric size of the particles favors the presence of surface shells in which the atomic coordination is reduced whereas the microstrain is enhanced. In this situation the nanostructure becomes more and more disordered, affecting the electrical resistivity. Therefore, such considerable disorder is the basic element supporting the QIE.

In bulk YbAl 3 , the f-electron atoms form periodic arrays which lie in the so-called Kondo lattice systems [START_REF] Doniach | [END_REF]. Every spin in the lattice is screened by the conduction electrons. In real space, the screening takes place on a length scale of mesoscopic size (ξ K = v F /k B T K , where v F is the Fermi velocity), denoted as the Kondo screening cloud [42]. The values of Fermi velocity may range from 10 6 m s -1 for normal metals to 10 3 -10 4 m s -1 in heavy fermion systems [START_REF] Mourachkine | Room-Temperature Superconductivity[END_REF]. Consequently, the Fermi velocity is directly proportional to the electronic contribution to the specific heat (Sommerfeld coefficient (γ)). The value of γ = 45 mJ mol -1 K -2 estimated from the specific heat data in bulk YbAl 3 is found to decrease down to 36 mJ mol -1 K -2 for the 70 h milled YbAl 3 alloy [27]. Since a Fermi velocity value v F = 4 • 10 4 m s -1 is observed for bulk YbAl 3 [START_REF] Demsar | [END_REF], a simple scaling with the variation of the coefficient γ leads to an appraisal of 5 • 10 4 m s -1 for the Fermi velocity in the milled sample. On the other hand, from the maximum in the magnetic susceptibility and magnetic contribution to the specific heat in bulk and milled YbAl 3 alloys [27], the T K values do not change significantly, being around 500 K-670 K, as estimated for the bulk sample [14,30,32]. Thus, following the above reasoning, it is possible to estimate a value of ξ K around 0.7 nm for the 70 h milled YbAl 3 alloy. The length scale ξ K would be less than the mean size of our samples (12 nm), and consequently the Kondo screening cloud is restricted within nanoparticles, at least in the core, with variations at the nanoparticle surface. The size effect would not be essential for the disruption of the Kondo lattice behavior, as the characteristic length is one order of magnitude lower than the mean grain size, whereas the increase in lattice strain and disorder at the surface of the particles with the size reduction Kondo ions (as a consequence of the size reduction process) and QIE (favored by the presence of a disordered collection of nanoparticles).

process will play a significant role. Our measurements of electrical resistivity of nanosized YbAl 3 indicate that the nanoparticle ensemble provokes breakdown of the Kondo lattice coherence, with an upturn at low temperatures. It has been shown that the reduction of particle size in nano-YbAl 3 results in Yb valence reduction as a consequence of increasing numbers of non-magnetic Yb 2+ atoms at the surface of nanoparticles [27]. Irrespective of this qualitative interpretation, what is clear is that by reducing the size, a ρ(T) minimum appears with the low temperature upturn. As a matter of fact, this situation resembles the cases of bulk alloys under chemical substitution, in which by adding non-magnetic rareearth atoms (Y and La for Ce-based and La or Lu for Yb-based compounds) a transition from Kondo lattice to single impurity regime is observed (see for instance [12,17]. In bulk YbAl 3 the coherence scattering is maintained throughout the alloy as a result of Kondo lattice behavior. This is greatly modified whenever there is a reduction of size and a concomitant increase of surface strain and disorder in the nanoparticle shell. For comparison purposes, the possibility of a change of regime on dilution with Lu was explored in the bulk YbAl 3 . The bulk sample Yb 0.2 Lu 0.8 Al 3 is found to crystallize in the same type of structure and space group Pm-3m as YbAl 3 and LuAl 3 alloys but with a lattice parameter a = 4.1932 (2) ˚A. The results show the presence of a low temperature minimum in ρ(T) of the bulk Yb 0.2 Lu 0.8 Al 3 alloy, with an upturn following a -lnT dependence (see figure 6). Curiously, the position of this minimum, around 7 K, coincides with the onset of -lnT term below the temperature scale T * , associated with the low temperature upturn in the 70 h milled YbAl 3 alloy. Consequently, it is possible to find some similarities between the processes of size reduction and chemical substitution by Lu in bulk YbAl 3 alloy. In both cases, there is an increase in the fraction of non-magnetic atoms (Yb 2+ or Lu) and the disorder, leading to a limit situation where the periodicity of the Kondo ions is broken. Consequently, a deviation from the Fermi liquid regime is observed.

Concerning the observed -lnT dependence of the low temper ature upturn in the 70 h milled YbAl 3 alloy, it is obvious that the electronic transport in an ensemble of nanoparticles is complex. It will require further study in order to ascribe it to Kondo behavior.

Conclusions

It is concluded that the size-in intimate combination with the increasing strain-is a significant d riving p arameter f or intrinsic electronic scattering changes. In this contextextending the universality of the former assertion-it is widely known that particles of noble metals in nanocrystalline state can undergo serious changes in the density of states, as has been reported recently [45]. Thus, our finding is naturally connected with a more general physical situation.

To summarize, the scrutiny of the electrical resistivity in nano-YbAl 3 particles has revealed a deviation from the Fermi liquid behavior at low temperatures. This deviation is due to the combined effect of the disruption of the periodicity of the

Figure 2 (

 2 Figure 2(a) shows the temperature dependence of the total electrical resistivity (ρ(T)) in bulk, 20 h and 70 h milled YbAl 3 alloys. It is observed a gradual change in the high temperature slope in the milled samples with respect to the bulk alloy, with a decrease of the relative variation in all temperature ranges

Figure 1 .

 1 Figure 1. X-ray diffraction patterns and results of Rietveld refinement of 70 h milled YbAl 3 (a) and LuAl 3 (b) alloys. The vertical markers are the expected Bragg positions according to Pm-3m space group. High resolution TEM image of a nanoparticle of 70 h milled YbAl 3 (c) and LuAl 3 (d) alloys.

Figure 2 .

 2 Figure 2. (a) Normalized electrical resistivity versus temperature for bulk, 20 h and 70 h milled YbAl 3 alloys. In the milled sample, there is a minimum followed by an increase of the resistivity, up to a broad maximum, as indicated by the markers. (b) Details of normalized electrical resistivity curve for 70 h milled YbAl 3 alloy, highlighting the existence of a temperature minimum and maximum. (c) Details of the low temperature region of 20 h milled YbAl 3 alloy, showing a minimum in ρ(T) around 4 K.

2 )Figure 3 .Figure 4 .

 234 Figure 3. Details of the low temperature region of bulk and 70 h milled YbAl 3 alloys, showing a deviation from the Fermi liquid dependence below T min in the nanometric alloy.

Figure 5 .

 5 Figure 5. (a) Low temperature region of electrical resistivity described by a - √ T term in 70 h milled LuAl 3 . Fitting of the electrical resistivity data in 70 h milled YbAl 3 alloy in logarithmic scale, according to - √ T term (b) and a -lnT dependence (c).In the Yb alloy, the data is better described by -lnT behavior below T * = 7 K.

Figure 6 .

 6 Figure 6. Normalized electrical resistivity curve of Yb 0.2 Lu 0.8 Al 3 bulk alloy. Details of the low temperature region showing the presence of a minimum around 7 K (left inset), with an upturn according to -lnT dependence (right inset).

Acknowledgments

This work was supported by the Spanish MINECO under project MAT2014-55049-C2-R.


Marcelo Negreiros
email: negreiro@inf.ufrgs.br

Luigi Carro
email: carro@inf.ufrgs.br

Altamiro A Susin
email: susin@inf.ufrgs.br

Noise Figure Evaluation Using Low Cost BIST

A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of noise figure in several test points of the analog circuit. The method is also able to benefit from SoC resources, like memory and processing power. Theoretical background and experimental results are presented in order to demonstrate the feasibility of the approach.

Introduction

With the increasing capacity of development achieved by the electronic industry nowadays, mainly in the consumer market, the design of new devices is a great challenge. A fast, flexible and reliable methodology must be used in order to cope with ever shrinking product development time, as a shorter time-to-market is crucial to the commercial success of such devices. The SoC approach [START_REF] Zorian | System Chip Test -How Will It Impact Your Design[END_REF] has been used in order to solve this issue.

Testing of such devices is another challenge, as test costs must be kept lower for the device to be competitive in the market. Unfortunately, analog testers are expensive devices and extra difficulties arise when trying to test analog circuits in a SoC environment. The limited access to the input and output of the analog circuit under test is an example.

In order to reduce the cost of the analog test, built-in test strategies may be used in order to reduce the requirements of external analog testers, or replace them completely. In the SoC environment, as plenty of processing and memory resources are available, it is possible to perform test analysis by reusing these resources [START_REF] Zorian | Test resource partitioning strategies for systems on chip[END_REF].

In this paper a low cost method for evaluating the noise figure of analog circuits is presented. Noise figure is an important parameter in the specification and design of low noise systems, such as communications systems and biomedical instrumentation. It is used to characterize the noise behavior, from single analog components to entire systems.

The test method is based on digital signal processing and may be implemented in the SoC environment by reusing processing and memory resources already available in the SoC. A one-bit digitizer that is permanently connected to the desired analog test point is used, thus minimally disturbing the circuit under test. Thanks to the simplicity of the converter, low analog area overhead is obtained, and no impact is made on the noise figure of the circuit being tested, that is, the proposed BIST does not increase the noise level to be measured.

The ultimate goal of this work is to show that, by using a simple BIST cell [START_REF] Negreiros | A Statistical Sampler for a New On-Line Analog Test Method[END_REF], one can measure not only frequency related parameters of the circuit under test, but rather one can obtain information of other important characteristics like noise figure.

The paper is organized as follows: in section 2 a brief review of other approaches to measure the Noise Figure is presented. In section 3, noise parameters are reviewed and two common noise figure measurement methods are presented. An analysis of a possible implementation of the methods here proposed in the SoC environment is provided in section 4, together with the test method. In section 5 results regarding the digitizer are presented, followed by experimental noise figure evaluations. Analysis is provided in section 6 and the paper finishes with conclusions in section 7.

Related work

The use of embedded noise sources for noise figure measurements has already been reported. In [START_REF] Beland | An enhanced on-wafer millimeter-wave noise parameter measurement system[END_REF] a thinfilm resistor has been used as an on-wafer noise source. Diode noise sources have been investigated in [START_REF] Randa | On-Wafer Measurements of Noise Temperature[END_REF]. A production test scheme based on signature testing has been proposed in [START_REF] Voorakaranam | A signature test framework for rapid production testing of RF circuits[END_REF], where noise figure measurements have been indirectly made. To the authors' knowledge, a first approach showing that it is possible to have a BIST circuit to measure noise figure has been proposed in [START_REF] Negreiros | Towards a BIST Technique for Noise Figure Evaluation[END_REF].

In the present work we address the issue of using a low cost BIST to measure the noise figure.

Noise in analog circuits

In this section some background information regarding noise characterization in analog circuits is provided. First noise figure is defined, and then two usual measurement methods are presented.

Definitions

A common parameter used to characterize the noise behavior of an analog electric signal (such as the output of a sensor or amplifier) is the signal-to-noise ratio (SNR). It is a ratio of the signal power to the noise power, expressed in dB. The noise factor (F) of a two-port device is the ratio of the available output noise power per unit bandwidth to the noise caused by the actual source connected to the input terminals of the device, measured at the standard temperature of 290K [START_REF]Fundamentals of RF and microwave noise figure measurements[END_REF]. The IEEE standard definition of the noise factor (F) is given by equation 4, where N a is the noise added by system, T 0 is 290K (standard temperature), B is the system bandwidth, k is the Boltzmann constant and G is the gain of the system.

G B T k G B T k N F a ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + = 0 0 (4)
The definition of noise figure is based on the assumption of a linear system. Some extensions for nonlinear systems have been proposed, like in [START_REF] Geens | Noise figure measurements on nonlinear devices[END_REF], but are not going to be analyzed in this work. Some usual noise figure values are illustrated in table 1, together with the corresponding noise factor. Note that the typical value of noise figure for an RF low noise amplifier is 3dB. For an RF mixer, the value is about 10 dB [START_REF] Razavi | RF Microelectronics[END_REF]. A circuit that does not add noise to its input would have a noise figure of 0 dB.

Measurement methods

In the direct measurement method, equation 4 is used. A load is connected to the input of the system, at a temperature of 290K, like in figure 1. The output noise power of the system is measured (the numerator of equation 4). If one knows the measurement bandwidth (B) and the gain of the system (G), equation 4 can be used directly.

In the y-factor method, noise figure evaluation is based on the use of a calibrated noise source [START_REF]Fundamentals of RF and microwave noise figure measurements[END_REF][START_REF] Collantes | Effects of DUT mismatch on the noise figure characterization: a comparative analysis of two Y-factor techniques[END_REF]. The method is a two-step process (see figure 2): with the noise source turned off (at a temperature of 290K, or cold temperature), the DUT output power (N c ) is measured. Then the noise generator is turned on, and the noise output power (N h ) for the hot temperature is recorded. The Y factor is the ratio of these powers:

c h N N Y = (5)

Figure 2. Noise characterization setup

Knowing that the noise power at the output of the DUT is simply the noise added by the system (N a ) plus the amplified input noise, one can write

a h h N G B T k N + ⋅ ⋅ ⋅ = (6) a c c N G B T k N + ⋅ ⋅ ⋅ = (7)
After applying equations 6 and 7 to 5, and developing using equation 4, one obtains the equation of the Y-Factor technique [START_REF] Collantes | Effects of DUT mismatch on the noise figure characterization: a comparative analysis of two Y-factor techniques[END_REF], that allows the evaluation of the noise factor ( ) ( ) ( )

1 1 / 1 / 0 0 - - - - = Y T T Y T T F c h (8)
T 0 is the reference temperature of 290K. If the noise source cold temperature is not 290K, this provides a correction term. This equation can be rewritten in order to take into account noise powers, instead of temperatures [START_REF] Geens | Noise figure measurements on nonlinear devices[END_REF], as shown in equation 9.

(

) ( ) ( )

1 1 / 1 / 0 0 - - - - = Y N N Y N N F c h (9)

A NF BIST in the SoC environment

In this section the implementation of methods for estimating noise figure suitable for BIST in a SoC environment are discussed. The proposed method is also presented.

Direct method

An implementation of the direct method would be as shown in figure 3. A nominal load R s must be applied at the input at a temperature of T 0 =290K. The output of the DUT must be amplified and routed to the ADC of the system for further processing.

DUT AD G a G du R S T o Figure 3. Direct method setup

One practical disadvantage of this setup is related to variations in the gain of the amplifier (G a ). This gain multiplies both terms in equation 10, but only the numerator is measured. This way, any deviation in the amplifier gain (from G a to G a ') will cause an error in the noise factor estimation. This issue is expected to occur because of process variations that may affect the gain of the amplifier.

a DUT o a DUT o a G G B T k G G B T k N F ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + = ' ) ( (10)

Y-factor method

If one could embed a suitable noise generator, being able to provide two known noise levels, it would be feasible to implement a noise figure measuring system based on the Y-factor technique. The system level setup is presented in figure 4. A programmable attenuator provides the noise levels needed for the NF measurement. The generator noise level can be measured through an auxiliary analog path to the ADC. This setup does not possess the same sensitivity to changes in the amplifier gain as the direct method. Both numerator and denominator in equation 11 are measured, so any deviations in the amplifier gain (from G a to G a ') are corrected.

' ) ( ' ) ( a DUT c a a DUT h a G G B T k N G G B T k N Y ⋅ ⋅ ⋅ + ⋅ ⋅ ⋅ + = (11)
In [START_REF] Negreiros | Towards a BIST Technique for Noise Figure Evaluation[END_REF] an analysis of uncertainty in commercial noise sources is provided, and it is shown that even large errors like 5% in the hot temperature can still provide useful measurements for noise figure estimation, if an error of ±0.3dB is acceptable (for noise figures of 3dB and 10dB). These errors could be used as guidelines in the design of the noise generator and attennuator.

Proposed method for NF measurement

Some problems are not addressed in the strategy presented in figure 4: the AD converter of the system is used, so simultaneous acquisition is not possible. Also, routing of analog signals to the ADC may be difficult. There is a need for a multiplexing device at the input of the ADC, which introduces non-linearity and distortion in the signal.

If the ADC is replaced by a simple digitizer, like in figure 5, some advantages like the possibility of simultaneous observability and no need for multiplexing devices is achieved. Also, because of the simplicity of the digitizer, it can be permanently connected to the analog test point, thus avoiding switches which degrade the performance of the analog circuit under test. As the Y-factor method requires the evaluation of a ratio of signal power, the digitizer must be able to provide noise power levels.

In this work the digitizer [START_REF] Negreiros | A Statistical Sampler for a New On-Line Analog Test Method[END_REF] uses a voltage comparator and a reference signal in order to perform the data acquisition. The requirements of the reference signal are modest (in the sense that only a small frequency band is used in the calibration process), allowing a simple and low-cost signal generator to be used.

Results

In this section the digitizer and a strategy to evaluate power levels using a reference waveform are presented. Noise and reference levels are also discussed. The section finishes with results from a prototyped setup.

Digitizer

The digitizer (figure 6) is composed by a voltage comparator with a noise reference [START_REF] Negreiros | A Statistical Sampler for a New On-Line Analog Test Method[END_REF]. The input signal is connected directly to the input of the comparator. The digitized input signal is obtained at the output of the comparator and is a digital output. Sampling may be controlled by adding a flip-flop at the output of the comparator. This structure is common in high speed voltage comparators. The noise amplitude should be greater than or equal to the signal amplitude, and both signals should be zero mean (or have the same dc level). The autocorrelation at the output of the sampler, considering that the combined signal and noise is a normal stationary process with zero mean, is given by the arcsine law:

        = ) 0 ( ) ( arcsin 2 ) ( x x y R R R τ π τ (12)
Equation 12 allows one to state that the statistics of the input signal will be at the output of the sampler, affected by a gain factor and by the arcsine function, which is approximately linear for small values of the input argument.

As the Fourier transform of the autocorrelation is the power spectrum density, one is able to observe the spectral characteristics of the signal, but with an increased noise level because of the addition of the noise at the comparator input [START_REF] Negreiros | A Statistical Sampler for a New On-Line Analog Test Method[END_REF].

Evaluating power levels

In the following, a Matlab simulation illustrates the idea of measuring noise levels using a reference waveform. In a real application, noise and reference waveforms should be amplified in order to enable the use of a voltage comparator.

If one applies a constant-amplitude square wave signal to the digitizer of figure 6 as a reference signal, noise levels can be determined if a simple strategy is followed. Two noise levels were applied to the digitizer using the same square wave as reference. Signals are as shown in figure 7. One should notice that noise levels should be always greater than the reference levels. The power spectrum density evaluation of the bitstream at the output of the digitizer is shown in figure 8. One can notice that the noise levels remains similar, while amplitude levels of the reference square wave are larger.

As the reference level is constant, a simple normalization procedure can be used. One can evaluate the maximum amplitude of both spectra and apply a correction factor to one of the power spectral density plots.

Figure 9. Power spectrum density after normalization (zoom at 60 Hz)

Figure 9 shows different noise levels, obtained before and after the normalization procedure. One can observe that the noise levels were very close before the normalization procedure. In order to make a numeric comparison, noise power ratio was evaluated using three different methods: ratio of mean square values (evaluated in time domain), ratio of PSD data and ratio of PSD data from the 1-bit digitizer. The values obtained are presented in table 2. For the 1-bit data, the reference waveform must be excluded from the power ratio evaluation (the reference is not part of the signal being measured). If this is accomplished, about 2.5% error in the power ratio was observed in the simulation, as presented by the last line in table 2.

Table 2. Noise power ratio evaluation and derived parameters for T h =10000K and T c =1000K

Noise and reference levels

Simulations were carried out in order to evaluate the accuracy of noise power ratio estimates as a function of the amplitude of the reference waveform. Figure 10 shows the error in power ratio estimates for gaussian noise. The reference waveform amplitude level is related to the overall accuracy of the method: for very small amplitude references, a large error is expected because of noise levels disturbing the reference amplitude. Very large references may lead to non-linear distortion of the digitizer. Amplitudes in the range of 10% to 40% of the noise level should give reasonable results (figure 10).

Experimental results

In order to verify the approach a test setup was implemented in order to measure the noise figure of a non-inverting amplifier. The general setup is shown in figure 11. In order to change the value of the noise figure of the circuit, a different operational amplifier was used. As the equivalent noise voltages are provided by the datasheets of the components, one is able to calculate the expected nominal value of the noise figure of the circuit, according to the opamp used [START_REF] Steffes | Noise Analysis for High Speed Op Amps[END_REF]. The opamps used were the OP27, OP07, TL081 and CA3140. The corresponding expected noise figures where in the range of 3.7dB to 16.2dB. In order to avoid interference pickup, the circuit was assembled in an aluminum case, being battery powered (figure 12).

Figure 12. Prototyped circuit

External noise generator and sine wave generator (both HP33120A) were used. The reference waveform was at 3kHz, while the noise measurement bandwidth was at 1kHz, as indicated in figure 13. The output of the digitizer was acquired using a digital scope (HP54645D). Data was processed using Matlab. Total acquisition length was 1e6 samples and the FFT size was 1e4 samples. The results obtained after processing are presented in table 3, including the expected noise figure values from noise circuit analysis [START_REF] Steffes | Noise Analysis for High Speed Op Amps[END_REF].

Analysis

The experimental results presented in section 5 have indicated the feasibility of implementing the approach for practical circuits. Noise figure measurements were carried out with a 2 dB maximum absolute error.

The proposed strategy makes use of a reference signal in order to perform the normalization process. Even a low-cost generator could be used, as the normalization process would track the main frequency component (disregarding harmonics, for example). This would enable the use of low quality reference waveforms, as the harmonics are not used in the normalization process. The amplitude of the main component, however, should be constant.

The need for analog signal conditioning, as a high gain amplifier, is related to the signal levels that should be measured. In general, an amplifier will be required for noise measurements [START_REF] Motchenbacher | Low-Noise Electronic System Design[END_REF]. This overhead could be minimized by observing that the noise figure of a cascade of stages is mainly the noise figure of the first stage [START_REF] Motchenbacher | Low-Noise Electronic System Design[END_REF].

Conclusions

In this paper a technique for the evaluation of noise figure in a BIST environment was presented. As the technique is based on DSP, it is able to benefit from resources already available in the SoC environment.

A simple voltage comparator and a reference signal were used as digitizers, thus discarding the need for an ADC. The technique also extends the capabilities of a simple BIST cell [START_REF] Negreiros | A Statistical Sampler for a New On-Line Analog Test Method[END_REF], allowing one to perform frequency and noise measurements.

Figure 1 .

 1 Figure 1. Noise characterization of a 2-port device

  figure (NF) is defined as the noise factor (F) expressed in dB[START_REF]Fundamentals of RF and microwave noise figure measurements[END_REF][START_REF] Motchenbacher | Low-Noise Electronic System Design[END_REF]

  Figure 5. Proposed setup

Figure 6 .

 6 Figure 6. Diagram of 1-bit digitizer

Figure 7 .Figure 8 .

 78 Figure 7. Noise and reference waveforms for hot (left) and cold (right) noise temperatures

  Vref/Vnoise*100%] error in power ratio[%]

Figure 10 .

 10 Figure 10. Error in power ratio estimates versus reference amplitude

Figure 11 .

 11 Figure 11. Diagram of the experimental setup

Figure 13 .

 13 Figure 13. PSD plot for noise levels after normalization

Table 1 . Some reference values for noise figure and

 1

			noise factor
	NF(dB)	F	Example
	0	1	noiseless analog circuit
	3	2	RF low noise amplifier
	10	10	RF mixer

Table 3 . Noise figure results for T 0 =290K and T h =2900K

 3

	Opamp	Expected	Measured
	OP27	3.7	3.69
	OP07	6.5	4.841
	TL081	10.1	9.698
	CA3140	16.2	14.02

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05)