Tony

Victor, Andréa, Julien, Loic, Martin Mathias

Maxime Dimitri Et Bastien

Mathieu Anna Georges

Energy Dispersive X-ray Spectroscopy EELS Electron Energy Loss Spectroscopy FIB Focused Ion Beam HAADF High Angular Annuler Dark Field HRS High Resistance State LRS Low Resistance State PCRAM Phase Change Resistive Memory pFIB plasma Focused Ion Beam PCM Phase Change Material

Keywords:

Je souhaiterais commencer par remercier les deux directeurs

General Introduction

After the invention of the magnetic tape in the late 1920s, data storage technologies have kept evolving from optical CDs to the most recent transistor based Solid State Discs. Nowadays, electronic devices have become a core part of our daily lives and the need for long term data storage is expected to increase exponentially.

For the past decades, the main focus of the research activity aimed at reducing the size of transistors in order to increase their density in electronic devices. Transistor based technologies however have reached a tipping point. The laws of quantum physics have greatly slow down the development of transistors below the 7 nm node. Moreover, the data retention time of transistor based technology is shown to be insucient regarding our current needs. For example, Solid State Discs using the Flash technology can preserve digital information for less than 2 years when the power is turned o. It is then required to build backup and redundancies which increase the cost of long term data storage. Today, new emerging technologies are studied in order to address these issues. Resistive Random Access Memories are now considered as promising candidates for the future of long term data storage. They show great potential in performances, stability, density and power consumption.

For example, it is projected that Conductive Bridge Resistive Memories technologies can reach an integration size below 5 nm and preserve information for more than 10 years. These technologies also come with their challenges. Mainly, their functioning mechanisms at the atomic scale remain unclear.

The development in the eld of semiconductors has always been limited by the ability of imaging and characterization tools to obtain information on newly created devices. In the past few years, an increasing number of studies have been conducted using in situ Transmission Electron Microscopy to observe functioning resistive memories at the atomic scale. In situ TEM allows to link physical, chemical and electrical characterization in order to obtain a new understanding on these technologies. This technique is consequently a promising solution for the development of resistive memory technologies but it remains a dicult technique to implement, and most of the studies published are not reproducible.

During this PhD, two types of resistive memory technologies have been studied using in situ Transmission Electron Microscopy. First, the physical, chemical and electrical characterization tools used in this PhD are described, and the current limitations of in situ TEM characterization for resistive memories are emphasized. Then, in order to facilitate the in situ TEM characterization process, improvements are performed on the hardware and new methods are developed and calibrated.

Finally, in situ heating and biasing of resistive memories are performed during TEM observation. In this work, a close link is made between the material science and the electrical characterizations, in order to obtain new information that could help the development of emerging data storage technologies.

Chapter 1

The needs of data storage technologies Contents

Expanding needs of data storage

There are two major technological applications driving the memory market :

processing power and data storage. For the past decade, the amount of digital data has followed an exponential growth [START_REF]Digital data storage is undergoing mind-boggling growth[END_REF]. Companies generate every day an increasing amount of data. Even individual people create large amount of information by taking photos and making videos. The Digital Universe study projects performed by IDC shows that the total amount of data created and copied annually in 2013 reached 4.4 zettabytes, and this value is expected to increase to 44 zettabytes by 2020 [START_REF]The digital universe of opportunities: Rich data and the increasing value of the internet of things[END_REF].

New solutions must therefore be found as the storage and processing requirements for such data are particularly important.

Currently, the demand for digital information storage already exceeds the production capabilities as shown on Figure 1.1. These big data then require powerful calculation tools to be handled. In the Information Age, entire businesses are based on digitized information. Even in the public sector, it has been suggested that government administrators in Europe could save more than 100 billion euros in operational eciency alone by using big data [START_REF]Big data: The next frontier for innovation, competition, and productivity[END_REF]. Consequently, the demand for data storage is expected to increase much more rapidly than the ability to produce it as illustrated in Figure 1.1. The main objective of the big data market is to provide storage, security, as well as backups for a minimal cost. In the big data market, the main actors are large companies such as Amazon Web Service, Google Inc, or International Business Machines Corporation. [4]. The data market represented 9 billion dollars in 2015 and it is expected to grow by 20% by the year 2022, as shown on Figure 1.2. In addition to the amount of data to be stored, there is an increasing need for the data storage to remain stable over time. From personal les to private companies data centers, it has become necessary to secure data over vast periods of time.

Data retention is currently limited by technological concerns and long term stor- mances. An active HDD does not last forever and they usually need replacement every 3 to 5 years. In addition, when the power is turned o, the information will be lost over time due to thermal instabilities. For example, the specication of the Solid State Disk (SSD) JESD218A from JEDEC states that when turned o, the retention time at 25 • C is below 2 years [5,4]. To compensate for this such short data retention time, it is necessary to build redundancies, and backup data regularly which increases the cost of data storage.

These issues come from the technology on which current data storage is based.

The singular unit used to store a bit of information in FLASH memories is a transistor. A scheme of a transistor is presented in Figure 1.3. To write the information, a voltage is applied to the word line to produce a relatively high current between the source and drain. Electrons then cross the insulating layer and get trapped in the oating gate. When the power is turned o, the charges trapped in the oating gate allow to maintain the transistor in a conductive state. In order to force electrons to the oating gate, a strong voltage is necessary. In addition, the electrons trapped in the oating gate are evacuated over time due to thermodynamics. This technology then involves a high power consumption and a limited data retention over time. It is also important to point out that miniaturization of transistors will no longer be economically viable in 2021 according to the the last ITRS report published in 2015[6]. This technology then cannot sustain the increasing need in storage capacity in the near future.

Emerging technologies

There are a variety of emerging technologies using dierent physical properties as vectors for digital information storage. The most promising technologies for Random Access Memory (RAM), which are currently intensively studied, are for example ferroelelectric RAM (FeRAM), Magnetic RAM (MRAM), Oxide based memories (oxRAM), Phase Change RAM and Conductive Bridge RAM (CBRAM) [START_REF] Singh Meena | Overview of emerging nonvolatile memory technologies[END_REF].

This work focuses on two of these technologies : CBRAM which are based on controlled metal diusion, and PCRAM which are based on the reversible transition between crystalline and amorphous phase. Their functioning mechanism are described in this section and their performances are compared to those of current ash memories.

Denitions

Conventionally, the active area of a resistive memory device is composed of a simple Metal-Insulator-Metal stack. The goal is to change the resistance of the insulator layer in a controlled and reversible way by applying a voltage between the two electrodes. In such conditions, digital information can be stored by associating a bit of information (0 or 1) to two dierent resistance values of the memory device.

This technology is qualied as "non-volatile" as no energy is necessary to maintain the memory layer in a specic physical state (conducive and non conductive). Each state will remain stable for more than 10 years given the proper external conditions such as temperature or humidity [8,6].

Three main states can be identied to describe the electrical properties of a resistive memory : a High Resistance State (HRS), a Low Resistance State (LRS) and a Pristine State (PS). The Pristine State is associated with a device following fabrication, and prior to any polarization, leading to a particularly high resistance.

Resistive memories are operated as follow :

Switching from a Pristine state to a LRS is called a FORMING operation.

Switching from LRS to HRS is called a RESET operation Switching from HRS to LRS is called a SET operation

Emerging technologies 7

Measuring the resistance of the device in order to retrieve its current state is called a READ operation

To assess their performances for data storage, resistive memories can be cycled between SET and RESET operation multiple times while monitoring their physical properties. Device failure is reached when it is no longer possible to dierentiate the resistance values between LRS and HRS. This results in a loss of the information.

The endurance of the resistive memory device is therefore dened by the number of cycles that can be performed before the device failure.

Non volatile resistive memories working principles 1.2.2.1 Conductive Bridge Resistive Memories

It is widely accepted that resistive switching of CBRAMs is based on the formation and dissolution of a Conductive Filament (CF) across the resistive layer. The resistive layer then not only needs good insulating properties, but also needs to be compatible with ionic and atomic diusion in order to form local conductive paths.

Several materials have been studied for the resistive layer, from chalcogenides to oxide based materials (GeS, HfO 2 , Al 2 O 3 ...). It has been reported that oxide based CBRAM show better endurance and data retention properties [START_REF] Jana | Conductive-bridging random access memory: challenges and opportunity for 3d architecture[END_REF].

Despite extensive studies performed over recent years, the physical mechanisms responsible for lament forming at the atomistic level remain unclear. One of the most accepted theory for the formation mechanism of the CF involves a Joule heating assisted electrochemical reaction, coupled with atomic and ionic diusion in the resistive layer. In the case of copper based electrodes (CuTe or CuTeGe for example), Kinetic Monte Carlo modeling suggests that copper is the species most likely to react and diuse to form the lament in CBRAMs [START_REF] Sankaran | Modeling of copper diusion in amorphous aluminum oxide in cbram memory stack[END_REF]. However, other metal based electrodes can be used, involving for example silver ions for the lament formation [START_REF] Lin | Electrochemical simulation of lament growth and dissolution in conductive-bridging RAM (CBRAM) with cylindrical coordinates[END_REF]. Figure 1.4 summarizes the corresponding forming mechanism of the CF.

The most widely accepted theory suggests that the CF starts growing at the cathode [START_REF] Guy | Investigation of forming, set, and data retention of conductive-bridge randomaccess memory for stack optimization[END_REF][START_REF] Pengxiao | Simulation study of conductive lament growth dynamics in oxide-electrolyte-based ReRAM[END_REF][START_REF] Lin | Electrochemical simulation of lament growth and dissolution in conductive-bridging RAM (CBRAM) with cylindrical coordinates[END_REF]. When applying a positive voltage to the top electrode, metal atoms located near the interface with the oxide layer are oxidized by transferring an electron to the anode. The applied voltage then participates in overcoming the energy barrier for hopping mechanisms of positively charged metal ions thus promoting diusion mechanisms across the memory layer. A reduction reaction then occurs at the cathode leading to an accumulation of Cu atoms. When the metal aggregate bridges the two electrodes, a strong current starts owing between the electrodes. This enables a stabilization of the CF, leaving the memory in LRS even after the biasing is stopped. This theory over CBRAM functioning is still being discussed. For example, a recent study suggested that the lament growth might not be limited by the electrochemical reaction, but rather by the low mobility of positive metal ions in the resistive layer [START_REF] Celano | Three-dimensional observation of the conductive lament in nanoscaled resistive memory devices[END_REF]. This would lead to a lament growth ductive lament occurs leading to a HRS. Schematic adapted from reference [START_REF] Chao | Fully roomtemperature-fabricated nonvolatile resistive memory for ultrafast and highdensity memory application[END_REF] starting at the anode instead of the cathode.

It is widely accepted that the width of the CF formed is directly proportional to the amount of current owing through the memory layer during the FORMING or SET operations [START_REF] Celano | Three-dimensional observation of the conductive lament in nanoscaled resistive memory devices[END_REF][START_REF] Jameson | Quantized conductance in Ag/GeS 2 /W conductivebridge memory cells[END_REF]. A small current will require less power but will produce an unstable LRS with low conductance. Strong currents however will produce wider and more stable laments associated with a very high conductance. This will however lead to a stronger Joule eect and reduce the device endurance.

After the CF is formed during the FORMING operation, the pristine state of the resistive memory is never recovered. Only a small part of the lament will be modied by SET and RESET operations as shown on Figure 1.4. Those operations will therefore need less power than the FORMING step.

The RESET operation is performed by applying a reverse biasing to the device.

When the current increases above the SET or FORMING current, the lament is destabilized because of the Joule eect. The increased temperature coupled with the applied electric eld will allow to retract the lament and RESET the device. A CF formed with a strong current will therefore require a higher power for the RESET operations. Likewise, when a small forming current is used, an equivalently small current will be sucient to destabilize the lament under reverse biasing [START_REF] Kinoshita | Reduction in the reset current in a resistive random access memory consisting of niox brought about by reducing a parasitic capacitance[END_REF][START_REF] Chen | Impact of compliance current overshoot on high resistance state, memory performance, and device yield of hfox based resistive memory and its solution[END_REF]. The phase change memory working principle is very similar to the one of CBRAM.

The main dierence lies in the structure of the device, as well as the nature of the conductive path between the electrodes. A schematic of a PCRAM device is presented in Figure 1.5(a). A PCRAM memory layer is composed of a Phase Change Material (PCM), which is usually a chalcogenide material. In PCRAM devices, one of the two electrodes act as a heater.

The phase change is obtained by applying an electrical pulse between the electrodes. The Joule eect occurring in the heater produces a local increase of the temperature in the PCM. The transition between the amorphous state and the crystalline state is possible depending on the temperature used. The functioning mechanism of PCRAM is represented in Figure 1.5(b). The two dierent resistance states of a PCRAM device are based on the reversible change between the amorphous and crystalline phases of the PCM.

In order to switch from the amorphous state to the crystalline state during the SET operation, the chalcogenide material is heated above its crystallization temperature point (around 180 • C for GeTe). Only a small volume of the PCM located above the heater reaches this temperature. This enables the formation of a crystalline lament between the heater and the top electrode. As the crystalline phase has a high conductivity, the device is then in LRS.

For the RESET operation, a stronger current pulse is applied in order to reach the melting temperature of the PCM (around 725 • C for GeTe). It is then necessary to quench the PCRAM to maintain it in an amorphous state. Since the temperature increase is very local, the heat can be evacuated in the order of a few tenths of nanoseconds following the current pulse [START_REF] Suh | Critical quenching speed determining phase of Ge 2 Sb 2 Te 5 in phasechange memory[END_REF]. The PCM volume on top of the heater is then amorphized, thus switching the device in HRS.

The SET and RESET operation of PCRAM devices then involves two dierent mechanism and the shapes and amplitudes of the applied voltage pulses are dierent as shown on Figure 1.5(c,d). As a result, SET and RESET operations require dierent times and dierent energies.

Current limits of resistive memory technologies

The performance of PCRAM, CBRAM and ash technologies obtained from the 2013 IRTS report are summarized in Table 1.1. Global characteristics of both CBRAM and PCRAM are expected to largely overcome ash current technologies.

The rst key advantages of these technologies is the integration size. The CBRAM structure is simple which allows to stack them very eciently. Even though PCRAM require a more complex structure, their integration size is also expected to decrease. In addition, both CBRAM and PCRAM already demonstrate high endurance, and data retention capabilities. They are therefore extremely promising solutions for massive data storage over vast periods of time. Graphs are adapted from Reference [START_REF] Hubert | Optimisation de mémoires PCRAM pour générations sub-40 nm: intégration de matériaux alternatifs et structures innovantes[END_REF] Several challenges still need to be overcome for both technologies. First, CBRAM devices present a low thermal stability. Manufacturing those devices becomes problematic as standard processes involve high temperatures. In addition, the increasing temperature involved during extensive operation of integrated CBRAM can also lead to a quick degradation of the device. Secondly, CBRAM devices present a strong resistance variability, especially in the HRS. The reliability of the device is then [START_REF] Guy | Evaluation of the performances of scaled CBRAM devices to optimize technological solutions and integration ows[END_REF]8] limited as HRS and LRS values can sometimes overlap during cycling.

In the case of PCRAM devices, the main challenges are the power consumption, the writing speed, and the HRS stability. As shown in Figure 1.5(c,d), PCRAM resistive switching uses dierent pulse durations. The device then requires a long writing time to allow the material to form a crystalline phase. Secondly, in order to reach the phase change temperature of PCM, a high current is required. For example, GeTe based PCRAM devices can require a programming current up to 1.5 mA [START_REF] Navarro | Reliability analysis of embedded Phase-Change Memories based on innovative materials[END_REF]. This leads to a high power consumption during PCRAM device operation.

Finally, it has been observed that the resistance of the device changes over time, especially in the case of the HRS [START_REF] Ielmini | Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells;part I: Experimental study[END_REF]. This eect called "drift" is caused by the structural relaxation of the amorphous state. In order to minimize its energy, spontaneous crystal nucleation and growth occur over time within the amorphous phase.

This consequently reduces the reliability of PCRAM devices for long duration data storage.

1.3

In situ characterization research motivation

It is dicult to improve something one cannot see. The development and manufacture of new semiconductor devices is then partially limited by the performances of the characterization tools. The Transmission Electron Microscope is a powerful instrument which allows nanoscale imaging, along with physical and chemical analysis using a wide range of dierent characterization techniques. It has consequently been a major actor for the development of the semiconductor industry. Over the past decades, TEM has been an invaluable tool driving the reduction of the size of transistor in microelectronic devices. The development of aberration correction Chapter 1. The needs of data storage technologies in the early 2000 have greatly increased the performances of TEMs [START_REF] Ol Krivanek | Aberration correction in the STEM[END_REF]. In the present day, atomic scale imaging has become a routine characterization technique.

However, TEM characterization is still considered as a destructive technique as the specimens are no longer functional and can no longer be modied.

In order to overcome the current challenges in the development of semiconductor devices, it is necessary to better understand their functioning mechanisms at the atomic scale. To do so, it is necessary to be able to apply external stimuli on the specimen during TEM observation. This has become possible thanks to the recent development of in situ TEM holder. In situ TEM holders now have the ability to heat and bias a sample inside the TEM column while preserving the imaging capabilities of the instrument. This new technology provides innovative research opportunities for the semiconductor industry. Both imaging and spectroscopy techniques available in the TEM can be used to obtain new information on the physical and chemical mechanisms responsible for semiconductor devices functioning. In situ TEM is therefore a promising solution for the development of new technologies such as resistive memories.

However, the ability to change a specimen in situ -during live TEM observations comes with new challenges. While the imaging part of the characterization process is now well established, the sample preparation necessary to allow heating and biasing of the sample is particularly complex. Extensive work is therefore necessary to make in situ TEM characterization possible. This PhD aims to develop a new characterization process to allow electrical operation of a resistive memory device during TEM observation.

PhD outlines

The present chapter described the context of this work through a quick overview of the data storage market. Existing technologies for non volatile data storage are described and the emerging technologies are presented. This work focuses on Conductive Bridge Resistive Memories (CBRAM) and Phase Change Memories (PCRAM). The currently considered functioning mechanisms of these technologies are presented and the current challenges limiting their development are discussed and in situ Transmission Electron Microscopy is proposed as a promising solution to address these challenges.

The main goal of this PhD is to understand the functioning mechanisms of resistive memories technologies at the atomic scale. Chapter 2 describes the current tools used for resistive memory characterization. First, ex situ electrical characterization is presented and the main properties of resistive memories are described. Then, the Focused Ion Beam tools used for TEM sample preparation is described, and a quick overview of the Transmission Electron Microscope is presented. The current state of the art of in situ TEM holders is shown and the current limits of this technology 1.4. PhD outlines 13 are discussed.

The next three chapters present the main results obtained during this PhD.

Chapter 3 describes a new sample preparation method for in situ heating of a specimen in the TEM. The performances of the in situ annealing experiment when using this method are studied through modeling and calibration experiments. These results are then implemented to obtain new information on the properties of Phase Change Materials (PCM) used in resistive memory devices.

Chapter 4 describes the development of TEM in situ biasing characterization.

First, the performance of the FIB tool are studied. Secondly, customized components for in situ TEM biasing are development to facilitate the characterization process. A new sample preparation method specically dedicated to the new in situ biasing setup is shown. The capabilities of this new method for TEM in situ biasing are then demonstrated though quantitative analysis of a reference sample.

Finally, the developments performed on the TEM in situ biasing technique are applied on CBRAM devices. The performances of CBRAM devices are studied by ex situ electrical characterization. These results are used as a basis for comparison to better understand the eect of in situ biasing on resistive memory devices. Finally, live operation of a CBRAM device in the TEM is presented and the changes observed in the CBRAM device after in situ biasing are discussed. In order to evaluate the properties of the resistive memory devices, a dedicated high performance electrical measurement tool is used. This tool is composed of an Agilient 4156C semiconductor analyzer power supply connected to a Cascade Microtech wafer probing system. This setup uses fully patterned wafers dedicated to electrical measurements. These wafers are composed of arrays of memory devices connected to contact pads on the surface. Figure 2.1 shows an optical image of the probe system connected to a device contact pad on the wafer. Using a map of the fully patterned wafer, this instrument can move between devices and operate them automatically to gather statistical information on their electrical properties and characteristics. By linking the electrical properties to the device structure, the fabrication processes can be improved in order to obtain better performances. This manufacture and characterization process is repeated illiterately to progressively improve the performances of resistive memories.

Each probe is connected to a Source/Measure Unit (SMU) which is conventionally set to apply a control voltage while measuring current. Figure 2.1 presents the electrical circuit and operation logic of a Source/Measure Unit (SMU). A maximum current limit called current compliance can be applied to protect the device during polarization. If the measured current goes above the compliance current, the power supply adjusts the voltage output to respect current limitations. The current compliance performance is consequently limited by the response time of the power supply. The longer it takes for the feedback loop to adjust the voltage output, the more unwanted current will ow in the system, which can damage the device. Upon forming, this capacitance is discharged in the system and the device undergoes a current surge called an overshoot, as presented in Figure 2.2. The overshoot can reach 70mA during the tenth of nanoseconds following forming [START_REF] Shima | Voltage polarity dependent low-power and high-speed resistance switching in CoO resistance random access memory with Ta electrode[END_REF] and cause extensive damage to the device. This eect is still intensively studied in the resistive memory eld, as it directly impact devices performances [START_REF] Tirano | Accurate analysis of parasitic current overshoot during forming operation in rrams[END_REF].

To solve this issue, 1T1R systems add a transistor in series of the resistor to act as a current selector. By adjusting the grid voltage on the transistor, it becomes possible to limit the amount of current owing in the device. 1T1R present better performances and high endurance but need an additional contact for the transistor.

Resistive memories programming methods

To operate the device, the simplest programming method is called quasi-static programming. This method simply consists in applying a voltage ramp while measuring the current owing through the device until the resistive switching occurs.

READ operations are performed by applying a small voltage ramp in the range of 100mV. By measuring the current, it is possible to retrieve the device resistance, hence its current state (HRS, LRS, pristine). READ operations are performed at low voltage to prevent unwanted switching caused by the polarization.

Higher voltage ramps (usually within the range of a few volts) are necessary to perform FORMING, SET and RESET operations. In quasi static programming, current measurements allow to monitor in real time the resistive memory operation.

The current-voltage curve obtained provides information on the proper functioning of the device, such as the switching voltage, or the occurrence of overshoots.

However, switching mechanisms are extremely fast, and quasi static programming implies a lack of control over high speed phenomena. For example, when the device switches toward the LRS, the voltage ramp does not stop. The current ow is then maintained until the voltage ramp reaches the programmed value. The device is then submitted to an unnecessary current and the associated Joule eect for a prolonged period of time.

The second programming method is called pulsed-programming and requires a pulse generator in addition to the power supply. This method consists in applying precise voltage pulses with high temporal resolution on the device. Multiple pulse and complex voltage pattern can be applied during very short duration (in the order of nanoseconds). The duration, height and shape of the pulse have a strong impact on the device operation and they can be adapted in order to improve the device performances [START_REF] Li | Eect of the programming pulse width on resistive memory switching behavior[END_REF]. Pulsed programming is considerably less stressful for the device compared to a continuous biasing during a quasi static approach. Its temporal resolution is no longer limited by the power supply feedback loop, but by the pulse generator. Even though it provides less information than the quasi static programming, its temporal control and operation speed are much better, making it more adapted to statistical studies. In addition, the better control over the current limits the stress applied on the device, leading to an improved lifetime compared to quasi static programming. reference [START_REF] Pan Feng | Nonvolatile resistive switching memories-characteristics, mechanisms and challenges[END_REF]. The applied voltage is in a linear scale in the order of a few volt.

Resistive memories electrical properties

Current is in logarithmic scale with I C the current compliance used.

Thousands of SET and RESET operation can be performed to cycle the resistive memory between HRS and LRS in order to evaluate the device endurance. The average dierence between the HRS resistances and LRS resistances is dened as the Window Margin (WM). The wider the WM, the easier it is to identify the resistance state of the device during a READ operation. Consequently, the WM is directly linked to the reliability of the device to store and retrieve the information. of temperature on the retention capabilities. Graphs were obtained from [START_REF] Nail | Understanding RRAM endurance, retention and window margin trade-o using experimental results and simulations[END_REF] and [START_REF] Guy | Investigation of forming, set, and data retention of conductive-bridge randomaccess memory for stack optimization[END_REF] When left in a particular state, external conditions can lead to a degradation of the memory device. Data retention is usually evaluated by measuring the stability of the resistance states relative to high temperatures. To evaluate the retention temperature, devices are programmed and left in a specic resistance state (HRS or LRS). Then, devices are progressively heated up while monitoring their resistance. the stochastic nature of the formation and dissolution of the lament. For example, cycling a device between HRS and LRS states will lead to an accumulation of defects in the resistive layer. Such defects will participate in current conduction leading to a drift of the HRS toward low resistance values [START_REF] Nail | Understanding RRAM endurance, retention and window margin trade-o using experimental results and simulations[END_REF].

Failure can also occur because the device no longer switches between the two resistance states. This is usually the consequence of either oxide breakdown or Optimizing the physical and electrical properties of resistive memories is then a matter of trade-o. The size of the window margin, the endurance, the power consumption and even the thermal stability are closely linked to each other. Improving a specic property often results in a degradation of another. The aim is then to nd a optimal balance between the dierent properties depending on the application eld using the variety of materials and stacking existing in the literature. However, it remains particularly dicult to recreate proper operating conditions while performing an observation at the atomic scale. For example, in such conditions, the endurance of a device is not an issue as only a few cycles are performed.

The characterization needs for resistive memories

Failure from extensive operation of a device is then dicult to observe. However, failure from unsuitable operation are more likely to occur, since atomic scale observation requires specic conditions such as high vacuum, and reduced dimensions.

This work attempts to develop new methods to perform in situ biasing of resistive memories during live observation of their chemical and physical properties. This requires basic assessments of the electrical properties of a device through ex situ electrical measurements as discussed in this section. Then, sample preparation methods are developed to enable atomic scale observation, while preserving the electrical properties of the device. Care is then taken to progressively get closer to real operation in order to observe the underlying mechanism of resistive memory switching.

Chapter 2. Characterization methods for resistive memories

Focused Ion Beam

A Focused Ion Beam (FIB) or Dual-FIB is a scanning electron microscope (SEM) coupled with a scanning ion microscope. The SEM column can perform high quality imaging from topography to elemental mapping while the FIB column enables to remove or deposit material on the sample with nanoscale precision. The use of FIB tools is widespread and concerns numbers of dierent problematics, but it is particularly used for cross sectional TEM foil preparation [START_REF] Reyntjens | A review of focused ion beam applications in microsystem technology[END_REF].

In this work, we aim to bias in situ semi-conductor device which are a few hundred of nanometers in size. Site specicity and circuit edit capabilities are then necessary to locate a specic device, extract it, and create electrical connections.

The SEM imaging enable to locate a specic device, while the FIB column can be used to extract the device and transport it on the in situ sample holder. In addition with precise etching, FIB tools can deposit conductive materials and create electrical connections between the sample and the holder. Consequently, Focused Ion Beam sample preparation is an essential tool to perform TEM in situ biasing experiments. A gas injection system (GIS) can be inserted in the chamber and positioned about 200 µm above the sample's surface. They can contain various organometallic gaseous precursors which can be heated up and sputtered on the sample to perform Ion Induced and Electron Induced Beam Deposition (IBID,EBID) [START_REF] Utke | Gas-assisted focused electron beam and ion beam processing and fabrication[END_REF]. Dierent precursors can deposit either metallic or insulating materials. This enables to perform circuit edit in fully patterned devices by cutting or adding conductive paths, insulate or short-circuit samples.

A tungsten needle called the Omniprobe with a tip diameter of about 500nm can 2.3. Focused Ion Beam 23 be inserted in the chamber. It uses piezo electric actuator to approach the sample with a high precision and perform micro manipulations either for mechanical tests or precision displacements of micron size features.

The stage possesses 5 degrees of freedom : x,y,z, rotation and tilt which enable the user to navigate easily around the sample. Coupled with the Omniprobe, this system grants considerable versatility for complex manipulation of extremely small samples. To prevent drift caused by charging eects during FIB processing, the stage is connected to the ground to evacuate the excess charges. Finally, a transfer lock is usually added to FIB tools to facilitate insertion and removal of the sample, and avoid repetitive venting of the chamber.

Two dierent FIBs were used in the current work. First, a Strata 400s dual beam from FEI was used for all TEM and in situ TEM sample preparation. Secondly, a single column V-ion Plasma FIB (pFIB) was used for micro manipulation and circuit editing during in situ sample preparation. This equipment diers from conventional FIB by replacing the Gallium Liquid Metal Ion Source (LMIS) with a radio frequency plasma source which extracts Xenon ions. Such system can create considerably brighter beam, and reach currents 100 times higher than liquid gallium sources. [START_REF] Giannuzzi | TEM Specimen Preparation with Plasma FIB Xe+ Ions[END_REF] It becomes then possible to etch or deposit much bigger structures at the cost of lower precision. The absence of an SEM column in our case also limits the imaging capabilities and makes micro manipulation more problematic. Despite these dierences, FIB and pFIB have a very similar functioning. The pFIB has been extensively used during the early development work performed during this PhD but the nal results were limited as the process became too complex. For those reasons, the current discussion is focused on regular gallium FIB.

Focused Ion Beam column

The LMIS gallium source is composed of a tungsten needle connected to a liquid metal reservoir. Gallium is heated to its fusion point (about 30 • C) and comes to wet the needle. By applying an electric eld, the liquid gallium adopts a conic shape. When the applied energy reaches the ionization potential, ions are extracted and sent in the column. [START_REF] Swanson | High Resolution Focused Ion Beams: FIB and its Applications[END_REF] Once gallium ions are accelerated to an energy usually ranging from 1 keV to 30 keV a series of magnetic lens (condenser and objective) are used to focus the beam on the sample. During FIB processing, it is necessary to switch between various currents to operate coarse or ne etching, deposition, and imaging. For this purpose, mechanical apertures are calibrated to select dierent probe current according to the user need. The beam then scans the sample using magnetic coils (deection plates) while octupoles adjust beam astigmatism. A detailed schematic of the FIB columns is presented on Figure 2.6.

The resulting gallium beam presents a Gaussian-Holtsmarkian distribution [START_REF] Callegari | Spontaneous growth of uniformly distributed in nanodots and InI3 nanowires on InP induced by a focused ion beam[END_REF]. The low intensity tail can extends up to 70 nm from the beam center even for high volt-Chapter 2. Characterization methods for resistive memories In the SEM column, electrons are extracted using a Shottky Field Emission Gun (FEG). The cathode composed of a tungsten needle with a 100 nm diameter tip is exposed to a potential between 3 and 5 keV. The Shottky eect describes the drop in the potential barrier created by the sharp shape of the electric eld at the end of the tungsten tip. The lowered potential barrier enable to extract electrons from the material. In the Dual-FIB, electrons can be accelerated to reach an energy between 1 keV and 30 keV.

To form an image, a secondary electron detector is positioned behind a positively polarized grid. The grid will attract electrons with low kinetic energy to the detectors during beam scanning. As discussed in section 2.3.2, both ion and electron exposure can create low energy electrons making both secondary ion and electron imaging possible.

Particle-matter interaction 2.3.2.1 Electron matter interaction

Incident electron collision with the sample will result in two types of interactions.

First, elastic scattering will lead to electron deviation without any signicant loss of Secondly, incident electrons can undergo inelastic scattering involving partial transfer their kinetic energy to the sample. Those interactions results in a variety of emissions such as X-ray, Auger electron, and secondary electron emission. Inelastic interaction can produce electrons with an energy loss. The energy distribution of exiting electrons is presented in reference [START_REF] Goldstein | Scanning Electron Microscopy and X-ray Microanalysis: Third Edition[END_REF]. By convention, secondary electrons are dened by having an energy inferior to 50 eV [START_REF] Nickles | Applications of secondary electron energy-and-angular-distributions to spacecraft charging[END_REF]. While BSE have an escape depth in the order of 500 nm to a micron, secondary electrons will only emerge from the top 5 nm to 10 nm of the sample. They consequently provide good information on the sample topography. The size of the interaction volume, and therefore the depth probed by the beam are directly proportional to incident electron energy. For electron beam imaging, beam conditions are usually set to 5 keV and 0.4 nA but beam energy can be increased to 15 keV in order to locate deeper structure in fully patterned devices.

There are two types of secondary electrons. True secondary electrons also called SE1 are created directly by incident electrons while SE2 secondary electrons are formed by back-scattered electrons, as shown on Figure 2.7. Considering the escape depth of backscattered electrons, their lateral spatial distribution, and therefore the potential SE2 lateral distribution must be considered. [START_REF] Murata | Spatial distribution of backscattered electrons in the scanning electron microscope and electron microprobe[END_REF] Chapter 2. Characterization methods for resistive memories

Ion matter interaction

The aim of this work is to perform in situ operation of a semi-conductor device inside the TEM. The sample must still be electrically functional after the FIB sample preparation. It is then important to evaluate how ion-sample interactions can degrade the sample quality or electrical properties of the device. impacts on a silicon substrate for dierent beam energies obtained using the SRIM software [START_REF]The stopping and range of ions in matter software[END_REF] After reaching the sample surface, the incident ion progressively loses energy through consecutive elastic and inelastic interactions. This is called a collision cascade which leads to a variety of phenomena, from physical sputtering to secondary electron emission, amorphization, defects formation and ion implantation.

Physical sputtering occurs when the energy received by the target atom reaches its surface binding energy (around a few eV which is approximately the sublimation energy of an atom). The target atom is then ejected as sputtered particle, either neutral or ionized. As the surface binding energy is dierent for each material, the milling speed can vary consequently depending on the material composition and density. Sputtering yields of gallium ion at dierent energies for various materials are presented in reference [START_REF] Utke | Gas-assisted focused electron beam and ion beam processing and fabrication[END_REF] . Sputtered material is partly evacuated by the pumping system, but a considerable part will land back on the sample creating redeposited material in the surrounding area [START_REF] Rubanov | FIB-induced damage in silicon[END_REF].

Along the collision cascade, the incident ion can knock-on atoms from the sample, creating vacancies, and causing atoms to move in interstitial positions. This can lead to defect nucleation, dislocation loops and amorphization in crystalline samples.

The size of the collision cascade, and consequently of the area damaged by FIB exposure is directly proportional to incident beam angle and energy. SRIM modeling of 1000 collisions of gallium ions with a normal incidence is presented in Figure 2.8 for dierent incident energies. Only a small part of incident ion energy is used for physical sputtering, to emit radiations (secondary electrons, sputtered ions, sputtered atoms...) or to induce defect in the sample. As such an interaction only requires a few eV, most of the energy from incident gallium ions is dissipated through heat [START_REF] Volkert | Focused ion beam microscopy and micromachining[END_REF]. A local increase in temperature can be described as a thermal spike conned in the collision cascade region. According to Monte-Carlo modeling, bombardment of a Ga + ions with an energy in the order of a few keV on a silicon substrate can already lead to a temperature higher than the melting point of silicon around the impact point (≈ 1 nm diameter ). However, as cooling occurs within the order of picoseconds, (before actual melting have time to happen) the true temperature is hard to dene [START_REF] Michael | Multi-scale modeling of localized heating caused by ion bombardment[END_REF][START_REF] Volkert | Focused ion beam microscopy and micromachining[END_REF].

Using dierent models, the average temperature rise upon Ga + bombardment of a silicon sample has been estimated in the literature to a few degrees even in extreme beam conditions [START_REF] Ishitani | Calculation of local temperature rise in focused-ion-beam sample preparation[END_REF][START_REF] Volkert | Focused ion beam microscopy and micromachining[END_REF][START_REF] Michael | Multi-scale modeling of localized heating caused by ion bombardment[END_REF].

Consequently, careful sample preparation using the FIB should allow the preparation of TEM sample while preserving the resistive memory device electrical properties. Amorphization and Gallium implantation can be limited using low energy ion beam, and the temperature increase under beam exposure is acceptable.

FIB Induced material deposition

The second main feature of the Dual-FIB after physical sputtering is beam induced material deposition. This feature is particularly important as it enables to perform electrical connection during sample preparation for in situ biasing.

Gas assisted deposition is achieved by decomposition of adsorbed precursors molecules on the sample surface. The dierent molecules sputtered by each GIS will produce a dierent material. We can for example deposit SiO 2 (with a Si(OCH 3 ) 3 or C 6 H 24 O 6 Si 6 precursor), Tungsten (W CO 6 ) or Platinum ((CH 3 )3P t(C p CH 3 )).

Electron and ion beam exposure along with several emissions resulting from particle-matter interaction have then the possibility to break atomic bonds in the precursor molecules. Lets consider tungsten deposition using (W CO 6 ) as an example, it has been reported that the loss of a CO ligand requires an energy ranging from Chapter 2. Characterization methods for resistive memories around 1 eV to 40 eV depending on the reaction involved [START_REF] Thorman | The role of low-energy electrons in focused electron beam induced deposition: four case studies of representative precursors[END_REF]. Consequently, precursor decomposition is mainly attributed to secondary electrons (E kinetic < 50eV )

both for IBID and EBID. However, in the case of IBID, both heat and excited surface atoms can also be involved.

Beam induced deposition is a dynamic process. Under continuous gas sputtering, precursor molecules are adsorbed on a wide area. During one beam scanning loop on the area of interest, adsorbed molecules are decomposed and surface density of the precursor decreases. Simultaneously, surrounding gas molecules will diuse on the surface and replenish the area of interest, to carry on deposition during the next scanning loop. Beam conditions during deposition are critical. Increasing beam current and energy will produce additional secondary electron and increase deposition speed. However, diusion rate of the precursor is limited. A point can be reached where the adsorbed molecules surface density becomes negligible, and precursors are instantaneously consumed when diusing in the area of interest. This is called the precursor limited regime corresponding to the maximum ion beam assisted deposition rate.

In the case of IBID, physical sputtering occurs simultaneously with the deposition mechanism. Net deposition yield is then dened by subtracting the sputtering yield to the deposition yield. Physical sputtering yield is directly proportional to the incident ion beam current and energy. However, sputtering is not limited by the surface density of adsorbed molecules. As beam current is more critical, 3 deposition regimes can be considered at constant beam energy to express net deposition yield.

At low current, physical sputtering is limited, and deposition rate increase with current. The maximum deposition rate is achieved when reaching the precursor limited regime. If beam current keeps increasing, the sputtering yield keeps increasing until it completely compensates the beam induced deposition, resulting in zero net yield.

Finally, at higher current, sputtering yield becomes superior to the deposition yield, resulting in overall etching of the sample.

Optimized beam settings for material deposition can vary depending on the sample. The topography surrounding the area of interest will strongly impact adsorbed molecules diusion capabilities. If gas molecules diuse at lower rate, the precursor limited deposition rate will be much lower. It is therefore necessary to adapt beam condition and closely monitor the process to prevent etching of the area of interest.

For example, reducing dwell time, or increasing dead time in between scanning loop can provide additional time for the adsorbed molecules to diuse.

For both EBID and IBID, material deposition is not strictly limited to the scanned area [START_REF] Gopal | Metal delocalization and surface decoration in direct-write nanolithography by electron beam induced deposition[END_REF]. As discussed in section 2.3.1, the focused gallium beam presents a low intensity tails. Incident Gallium beam can therefore reach sample's surface far from the beam center. Moreover, secondary electron lateral distribution can be important, especially for SE2 electrons. In addition to secondary electron emissions, heat diusion following ion impact can also result in precursor decomposition. Those mechanisms will therefore lead to a halo eect around the scanned area composed of thin layer of FIB deposited material. As shown on Figure 2.9 this halo eect, can extend, in certain beam conditions, up to 20 microns in diameter. This can have important implication for electrical connections in the specimen. This limited precision during deposition of conductive material can then lead to short circuits during sample preparation.

FIB deposited material properties

The tungsten deposited in the FIB using W CO 6 precursor can have good electrical and physical properties. For example, the conductivity of FIB deposited tungsten nanowire has been reported to be of 4.6 * 10 3 Ω -1 cm -1 [START_REF] Horváth | Electrical characterization of tungsten nanowires deposited by focused ion beam (b)[END_REF]. As its deposition rate is also important, it is widely used both for circuit edit, or for conventional TEM sample preparation as a protection layer.

As mentioned before, SiO 2 is deposited using tetraethoxysilane (TEOS) precursor. However, the chemical reaction involved is particularly complex. Electron induced deposition using TEOS is extremely slow, and ion induced deposition resulted in most cases in sample etching during this work. Another precursor available in the pFIB was therefore used. Instead of Si(OCH 3 ) 3 , the GIS uses C 6 H 24 O 6 Si 6 to deposit insulating material. Not only could this material be deposited in much larger quantity due to the high current available in this equipment, but the insulating properties given by the manufacturer are excellent (σ < 10 -10 Ω -1 cm -1 ).

The thermal conductivity of FIB deposited materials is however hard to evaluate.

Ion beam deposited materials are amorphous, and contains in variable quantities gallium, carbon and oxygen depending on the precursor and beam conditions used during the process. Very few studies address this issue. In the case of FIB deposited platinum, it was found that its thermal conductivity was of one order of magnitude Chapter 2. Characterization methods for resistive memories inferior to its pure, crystalline equivalent [START_REF] Alaie | Thermal conductivity and nanocrystalline structure of platinum deposited by focused ion beam[END_REF]. FIB deposited tungsten presents the same issues in structure and composition. It is fair to assume that its thermal conductivity is also much lower than the bulk equivalent. the bulk. The chunk of material is then transferred on a copper grid and ion beam deposition is used to solder the chunk to the copper grid. The Omniprobe is then detached using the ion beam. Once on the copper grid, the sample can be thinned down to electron transparency by progressive etching using the ion beam.

Conventional TEM foil preparation

During milling and thinning, the tail of the ion beam will create a rounding eect by etching the top surface of the sample. Top deposit thickness must be sucient to absorb this phenomenon and leave the sample itself intact. This deposit must also be homogeneous, as dierence in density would lead to an uneven etching of the ion beam, creating thickness variations called a curtaining eect. This eect can also emerge on patterned devices where high density and low density material are adjacent. It is possible to limit this eect by increasing beam dose, and slightly tilt the foil.

Brief history

The maximum resolution of an optical microscope is given by the Rayleigh criterion. This equation shows that the smallest resolvable distance d is linked to the wavelength λ of the incoming photon, the medium refractive index n and the semi angle α induced by the magnifying lens :

d = 0.61λ nsin(α)
The maximum resolution achievable in a light microscope is therefore limited by the visible light wavelength (from about 400nm to 800nm). The idea to use electrons to overcome this resolution limit emerged at the beginning of the twentieth century after De Broglie suggested the wave-particle duality of electrons [START_REF] De | Recherches sur la theorie des quantas[END_REF]. This hypothesis on the wave nature of electrons enabled to link their wavelength to their momentum (if relativistic eects are ignored) following the equation :

λ = mv
where λ is the electron wavelength, is the Planck constant, m is the mass of the electron and v its speed.

The rst prototype of an electron microscope was created in 1932 by Knoll and Ruska [START_REF] Knoll | Das elektronenmikroskop[END_REF]. By 1938, the rst commercial electron microscope was produced by Siemens. Since then, TEM technology has been developed relentlessly. The principle of aberration correction to reach atomic resolution was proposed in 1939 by Scherzer [START_REF] Scherzer | Das theoretisch erreichbare auösungsvermögen des elektronenmikroskops[END_REF]. Atomic columns were rst resolved in 1956 by Menter [START_REF] Menter | The direct study by electron microscopy of crystal lattices and their imperfections[END_REF].

At the time the most eective way to increase TEM resolution was considered to be a reduction of the electron wavelength. This led to the creation of High Voltage Transmission Electron Microscopes during the 1960s with accelerating voltage in the range of 1 to 3 MeV. Despite the gain in resolution, HVTEM could cause extensive damage to the sample. It could for example lead to defect formation, high temperature and exposure damage during imaging and therefore drastically limit the accuracy, veracity and the possibilities of the information obtained.

The progress made with multipole technologies led to another solution to increase resolution. Without any aberrations (such as spherical, coma or chromatic), a resolution of around 0.1 nm could theoretically be achieved with a 100 keV electron 2.4. Transmission Electron Microscopy 33 beam, considering the limitation of magnetic lenses. The rst aberration corrector was demonstrated in Cambridge in 1997 [START_REF] Ol Krivanek | Aberration correction in the STEM[END_REF]. The combination of intermediary voltage TEM (with a beam energy up to 200 keV) and aberration correction enabled to improve the resolution well below this 0.1 nm limit.

Since the breakthrough of aberration correction, TEM kept improving mainly by developing new techniques and exploiting all the untapped potential of information provided by scattered electrons. TEM are now vastly used both in the research and the industrial elds for a variety of dierent techniques, such as advanced crystallography, chemical analysis, spectroscopy, electromagnetic eld and strain mapping. Figure 2.12 shows a schematic view of the the TEM column. For the microscopes used in this work, electrons are extracted using a eld emission gun. A rst anode is used to extract the electrons from the tungsten tip, and a second is used to accelerate them to the desired energy (ranging from 80 keV to 300 keV in conventional TEM).

The TEM column

The condenser system then controls the intensity and convergence angle of the electron beam enabling for example to switch between parallel or convergent illumination modes. The rst lens creates a reduced image of the source which is then projected onto the specimen by the second lens. Then the condenser aperture is used to block part of the electron beam. This has two consequences. First it impacts the amount of current reaching the specimen. Secondly, this aperture removes high angle electrons, which are the origin of strong spherical and chromatic aberrations.

Chapter 2. Characterization methods for resistive memories

The most critical part for proper imaging is the objective lens, as it controls the beam focus on the specimen. Any defects or aberrations present in the electron beam at this point will be directly transmitted in the specimen image. The objective lens then needs to be properly aligned to produce a high quality image. The objective aperture is then used to select the electrons which will participate to the image formation of the specimen and improve nal image contrast. It can be used for example to switch between Bright Field (by selecting the transmitted beam) or Dark Field (by selecting a diracted beam). Finally, the projector system projects either the image or diraction pattern of the specimen onto the uorescent screen and the CCD camera for observation. X-ray after electron-sample interaction. Following an inelastic interaction with incident electron, a core electron is excited and ejected from the target atom. A valence electron is then relaxed to ll the core hole and emits an X-ray photon corresponding to the energy transition involved. This relaxation and the associated photon energy are characteristic of the energy levels available. They are therefore directly linked to the nucleus nature. It is then possible to obtain elemental composition information from the measured X-ray photon energy.

EDS : Cli Lorimer quantication

Calculations are then necessary to obtain quantitative information from EDS analysis. After the intensity background is removed, characteristic intensity peaks undergo a Gaussian t. Superimposed signals are deconvoluted in order to isolate each element participation to the overall intensity.

The Cli Lorimer method is a simple quantication procedure which does not involve any reference sample. In a binary system, the weight percent C A / C B of each element present in the sample can be retrieved by comparing the intensity ratio of the two peaks :

C A C B = k AB I A I B
Where k AB is a sensitivity correction factor taking into account the dierence between generated and measured X-ray for both signals intensity I A and I B . By applying the thin foil approximation which considers that no absorption phenomenon occurs, the k factor is only linked to the atomic number Z. This factor is characteristic of a pair of elements. If three or more elements are present, k factors are related to each other following : As the sum of the weight percents of all present elements is equal to 1, it is possible to retrieve an absolute value of weight percent for each element and obtain quantitative data on the sample composition. Further details on EDS acquisition and quantication methods can be found in [START_REF] Shindo | Energy Dispersive X-ray Spectroscopy[END_REF]. From the DPC images obtained, it is possible to retrieve a quantitative value of the electric eld in the sample from the angular displacement of the beam. The inuence of the electric eld component perpendicular to the beam direction can be calculated, with the approximation that no scattering or energy loss occurs. If the electric eld in the sample is uniform, and in the absence of diraction contrast, the value of the electric eld is given by [START_REF] Shibata | Imaging of built-in electric eld at a pn junction by scanning transmission electron microscopy[END_REF]:

k AB = k AC k BC
γ = t 2K 2 2me h 2 E
with γ the angular displacement (in µrad), t the sample thickness (in cm), K the wavevector, m the mass of the electron, e the charge of the electron, and E the magnitude of the electric eld (in MV/cm).

Chapter 2. Characterization methods for resistive memories resolution is now routinely obtained on a state of the art TEM, while an advanced user can access a vast panel of information, as previously discussed. A limit has however been reached as a TEM remains incapable of reproducing real world environment, since the sample stays trapped within the high vacuum column. Years of development in this eld enabled to create new ways to provide control over the sample, from Environmental TEM (ETEM) using local gas ow in the column to cryo and mechanical TEM holder.

Great progress have been made regarding in situ TEM holders technologies, especially in the case of liquid or gaseous environment [START_REF] Damiano | Electron microscope sample holder for forming a gas or liquid cell with two semiconductor devices[END_REF]. Finally, most recent in situ TEM holders have become capable of performing low drift in situ heating and electrical biasing within the TEM column during live observation [START_REF] Damiano | Sample holder providing interface to semiconductor device with high density connections[END_REF][START_REF] Lawrence F Allard | A new mems-based system for ultra-high-resolution imaging at elevated temperatures[END_REF]. This created new opportunities, especially in the eld of microelectronics. It allows for example to perform live observation of a device during its operation. This technique could then provide information on the intrinsic physical and chemical mechanisms responsible for a device operation at the atomic scale.

The aim of this work is to perform in situ biasing during live observation of a resistive memory device. An important aspect of this work is to get as close as possible to real resistive memory devices operation conditions. One of the main goals would be to create a method allowing to perform TEM in situ biasing on samples which are compatible with ex situ electrical characterization (fully patterend wafer). This implies to use real devices and avoid samples specically manufactured for TEM observation. This section will rst describe previous design for in situ biasing TEM holder, before describing the more recent technology used in this work.

Early in situ TEM holder technologies 2.5.1.1 Furnace in situ heating holder

The original in situ heating holders are dened as furnace type holders. A schematic of a furnace type holder is presented in Figure 2.15. Identically to conventional TEM holders, a furnace holder uses a copper grid. The grid is attached to the furnace using a spacer and a screw. The sample can then be heated by applying a current on the furnace. This technology presents several issues. Because of the size of the heater, strong drift is observed. In addition, the heater is located several millimeters away from the sample. Consequently, there is a strong temperature gradient between the heater target temperature and the actual sample temperature. Such holder is compatible with copper grid thus allowing to use conventional sample preparation technique. The copper grid is inserted between the furnace and the spacer.

Probe-based in situ biasing holders

The Probe-based in situ biasing holder from Nanofactory is presented on Figure 2.16. This holder is based on a movable probe controlled by piezo-electric motors.

The TEM foil is positioned on a conventional TEM grid connected to the ground.

The probe is manually controlled and put in contact with the surface of the sample.

Once the contact is achieved, the probe can be polarized to produce a current ow in the sample. One of the key advantages of this system is that it uses TEM grid and is therefore compatible with conventional FIB sample preparation. Probe-based TEM holders however present several critical drawbacks, especially when characterizing resistive memories. Landing the probe on the sample can be dicult and presents the risk of breaking the sample. The contact area between the sample and the probe is unknown, and possibly very small. Moreover, a thin oxide layer of a few nanometers is usually formed on the probe when the holder is outside the TEM, leading to a strong contact resistance during the experiment. The resulting Joule heating can either permanently damage the sample. For example, while no I(V) curve characteristic of resistive switching (neither SET nor RESET) are shown in reference [START_REF] Kwon | Oxygen vacancy creation, drift, and aggregation in TiO 2based resistive switches at low temperature and voltage[END_REF], clear signs of extreme temperatures are visible around the contact point of the movable probe after in situ biasing. The increased Joule eect can then strongly participate in the resistive switching which is not representative of the device real operating conditions.

Increasing the pressure from the probe on the sample surface can slightly improve contact quality but this will also generate mechanical stress. Not only this increases the risk of breaking the sample, but it has also been reported that mechanical stress inuences the switching mechanism of resistive memories [START_REF] Ambrogio | Impact of the mechanical stress on switching characteristics of electrochemical resistive memory[END_REF]. The purpose of in situ TEM is to get close to real operating conditions of the device, but those observations show that probe based holders strongly modify the sample condition.

Another major issue concerns quantitative measurements during in situ TEM analysis. A strong eld eect will appear when applying a potential on the probe.

During an experiment such as DPC or electron holography, this electric eld will strongly interfere with data acquisition and prevent quantitative measurements.

Several studies attempted to couple reference measurement with modeling, in order to overcome this issue. However, isolating the eld information coming from the sample remains particularly dicult in the presence of such a strong ambient electric eld [START_REF] Beleggia | Towards quantitative o-axis electron holographic mapping of the electric eld around the tip of a sharp biased metallic needle[END_REF][START_REF] Migunov | Prospects for quantitative and time-resolved double and continuous exposure o-axis electron holography[END_REF].

Despite the high diculty of in situ biasing of resistive memory devices, many studies have been published using probe based holders [START_REF] Arita | Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ TEM[END_REF][START_REF] Choi | In Situ Observation of Voltage-Induced Multilevel Resistive Switching in Solid Electrolyte Memory[END_REF][START_REF] Cooper | Anomalous resistance hysteresis in oxide reram: Oxygen evolution and reincorporation revealed by in situ tem[END_REF][START_REF] Kwon | In situ biasing TEM investigation of resistive switching events in TiO 2 -based RRAM[END_REF][START_REF] Yang | Observation of conducting lament growth in nanoscale resistive memories[END_REF][START_REF] Yao | Direct observation of oxygen vacancy-driven structural and resistive phase transitions in La 2/3 Sr 1/3 M nO 3[END_REF]. However, most of these studies are not reproducible, and it remains dicult to dierentiate genuine device functioning from artifacts when using probe based holder.

Recent advances in in situ TEM sample holders

New generation MEMS-based in situ holders have been developed to try and solve critical issues coming from using a probe. Figure 2.17 shows the Protochips Fusion holder. Instead of a copper grid, this system uses a MEMS chip to support and connect the sample. The chip is composed of a 4 mm by 5.8 mm silicon chip with a thickness of 2.5. In situ TEM 41 300 µm. In the center of the chip, a 300 µm by 300 µm hole is chemically etched. This enable the electron beam to go through the chip during TEM observation. A suspended membrane remains on top of this observation window as shown on Figure 2.17 (b). This membrane composed of silicon nitride for in situ biasing chip. For an in situ heating chip, the membrane is composed of silicon nitride, coupled with a silicon carbide heater. The holder presents at its end 4 gold clamps. They are used to takes contact on 4 dierent 475 µm wide metal pads located on the MEMS chip as shown of Figure 2.17.

While presenting a challenge to place a clean sample onto a thin membrane, this technology provide several major advantages. The heater is smaller compared to furnace type holder. As a result, very low drift is observed during in situ heating experiments. Then, each heating chip is individually calibrated by infrared imaging during manufacturing. The temperature control is consequently quicker and much more precise. Finally, for in situ biasing experiment, chip based systems do not require to perform the electrical contacting inside the TEM in opposite to probe based systems.

MEMS based holders require however a much more complicated sample preparation. After conventional FIB sample preparation, once the sample has been thinned down and cleaned at low voltage, it must be transported and laid at on the membrane. This step involves a lift-out, a 90

• rotation, and a transfer of the TEM foil onto the membrane.

Performing FIB in situ lift-out on a thinned and cleaned TEM foil leads to two issues, as discussed in Section 2.3. First, metal deposition close to the area of interest will contaminate the sample. Secondly, FIB milling will leave redeposited material on the TEM foil.

The thin foil must then be ipped by 90 • usually by rotating the Omniprobe. Figure 2.18 shows a TEM foil after the rotation and ready to be transferred on the membrane. In this conguration, the sample must rst be soldered on the membrane. And then the thin foil is exposed to metal contamination from the halo eect. Then, the soldering between the omniprobe and the sample must be cut o.

In addition to material redeposition, the sample will be exposed to the gallium beam with a normal incident angle. This will result in an important amorphization and gallium implantation. On the other hand, if the soldering is mechanically broken, this will generate important mechanical stress in the sample and there is an strong probability to either break the sample, the membrane or simply lose the sample because of the mechanical and electrostatic forces. It is extremely dicult if not impossible to maintain the sample in a working condition using this method. Consequently, a new method must be developed. This PhD work will attempt to develop new methods to perform in situ biasing of a resistive memory in a TEM.

Conclusion

In this chapter, the state of the art of electrical and material science characterization in the eld of resistive memories has been presented. The electrical properties of resistive memory devices are studied to serve as a basis for comparison during in situ TEM characterization. The focused ion beam technique is also presented. It is shown that the FIB presents the site specicity, micro manipulation, and circuit edit capabilities necessary for in situ TEM sample preparation. Using high energy ion beam presents however several challenges such as beam induced damage and artifacts. In addition, it is shown that parasitic deposition as well as redeposited material generated during FIB sample preparation can be a major issue for in situ biasing experiments. A quick summary of the TEM imaging technique is presented

Introduction

This chapter describes the in situ study of phase change memories. As discussed in Section 2.5.2, a new MEMS based chip based in situ heating technology presents major advantages compared to previous furnace type holders. The sample preparation for chip based in situ holder is however more complicated. To perform in situ annealing of phase change memories, a new sample preparation method dedicated to in situ experiment using chip based sample holders has been developed.

First, the new FIB sample preparation is described and compared to the current one. Secondly, modeling and calibration experiments are performed to understand how the new sample preparation impacts in situ annealing. Finally, as example of the working method, STEM in situ annealing on cross sections of GeTe lms is presented. The aim is to compare the crystallization mechanisms in a GeTe lm capped by SiN and a GeTe lm left uncapped after deposition and hence submitted to natural oxidation. In situ annealing results on TEM foils are compared with in situ annealing on bulk samples reported on the same material [START_REF] Noé | Impact of interfaces on scenario of crystallization of phase change materials[END_REF]. This previous work performed on this material provides a strong basis for the development of in situ annealing methods on resistive memories in the TEM.

Current limits of in situ TEM sample preparation

In order to perform in situ annealing, the sample must be placed on a heating chip described in Section 2.5.2. Sample preparation is performed using a FIB. As shown on Figure 2.18 in Section 2.5.2, a thin foil laid at on a membrane will have redeposited material and metal contamination on its surface which cannot be removed. Transporting a thinned and cleaned TEM foil is the main issue to address in order to improve sample preparation for chip based in situ TEM holders. To do so, it is necessary to transfer the sample on the membrane before thinning it.

Two major issues emerge from such a situation as shown on Figure 3.1. First, the sample, once on the membrane, must be in a position which allows further FIB thinning in order to reach electron transparency. Then, the thin foil must be positioned perpendicular to the electron beam to allow imaging in the TEM after the sample preparation.

The FIB stage allows rotation over 360

• and tilting from -10 • to 52 • . In addition, pre-tilted slots are available on the FIB stage which allows even very high angle to be reached. Bringing the sample parallel to the FIB for ion thinning and cleaning is then easily achieved. The only limitation concerns milling at grazing angle. The sample must be positioned at an angle of at least 5

• relative to a at surface to enable proper imaging, and therefore precision milling. It is important to point out that higher the angle between the foil and the at surface, the higher the imaging and milling quality, as shown in Figure 3.1.

For TEM observation, the alpha tilt rotation axis of a conventional TEM holder often covers a range from -30

• to 30 • angle, depending on the TEM model. This wide range of available angle can be used to bring a tilted TEM foil along the zone axis in the TEM. If a sample is initially positioned at the limit of the holder capabilities (i.e, ±25 to ±30 • ), it can be problematic for the TEM user to reach certain zone axis. Consequently, one can consider that a TEM foil can initially be positioned at an angle up to ±15 • without limiting the TEM observation capabilities. Once in the TEM, the alpha rotation axis can be used to compensate for the TEM foil tilt.

Then, a minimum of 15 • rotation is still available in both direction in order to nd the sample zone axis.

A thick chunk of material can consequently be soldered onto the heating membrane at an angle of 15 • . It can then be positioned parallel to the ion beam during the preparation, and perpendicular to the electron beam during TEM observation.

In order to perform the rotation of the chunk during FIB sample preparation, a rotation needle is used. This rotation needle simply consist of a used omniprobe mounted on an FIB stub as shown in Figure 3.2.

Development of a new FIB sample preparation method

A SEM image of the sample preparation as well as a schematic view of the sample manipulation are presented in Figure 3.3. Once the targeted device is located on the bulk sample, it can lifted out following the rst steps of conventional TEM foil For TEM observation, the sample must be located on top of a hole in the membrane as shown on Figure 3.4a. However, as the thinning is after performed at grazing angle, it is necessary to increase the size of the hole in the membrane to guarantee better ion beam image quality. Figure 3.4b shows the transfer of the 15

• tilted chunk on top of the newly etched hole in the membrane. In Figure 3.4c, one can distinguish that when the FIB chunk is in line with the newly etched hole.

During FIB thinning, image quality is improved thanks to a better contrast between the sample and the hole in the background.

As the sample is yet to be thinned, thick tungsten pads can be deposited by IBID to solder the sample to the chip. Extensive tungsten deposition provide increased stability, while improving the heat conduction between the heating membrane and the sample. The chunk is then ready to be thinned down to electron transparency, and cleaned at low voltage to remove amorphous material, redeposition and metal contamination. Figure 3.4d presents an STEM HAADF image of the nal sample.

Upon heating, the membrane will extend and mechanical stress in the sample can emerge. To avoid this, the sample is cut in half during thinning. An interesting aspect of this is that it provides an additional foil in case a problem emerges during thinning. However, this aspect is not mandatory. If tungsten is only deposited on one side of the chunk, no stress will emerge in the sample from membrane extension.

Advantages and drawbacks

This preparation method presents several major advantages compared to conventional previous preparation method on MEMS chips for in situ TEM. While it does not involve transport of a thinned and cleaned foil, it also avoids metal contamination and guarantees higher sample quality. The success rate is also much higher as each transfer can be secured by metal deposition.

However, a few drawbacks also emerge from this method. Local etching of the membrane is necessary to help through the preparation process. It is then possible that such modication can interfere with the membrane ability to heat.

Then, even though increased metal deposition provides great advantages, it can be considered that the increased halo eect might participate in current conduction in the membrane. Consequently, part of the current ow originally intended for Joule heating in the membrane can pass through the tungsten halo, thus slightly lowering the membrane temperature. Knowing this, it is also important to point out that this modication are extremely local relative to the size of the heating membrane.

The membrane covers a 300µm x 300µ area. The entire membranes is heated up by the Joule eect, but only an area of around 20 microns in diameter is modied during sample preparation.

At the same time as this PhD work, a dierent method was proposed to perform the rotation on the sample. By using a 45

• tilted stub in the FIB, it is possible to reproduce the rotation of the sample without taking the sample out of the FIB [START_REF] Zintler | FIB based fabrication of an operative Pt/HfO 2 /TiN device for resistive switching inside a transmission electron microscope[END_REF]. This can reduce the preparation time by a factor 1.5. However, using a rotation needle still presents an important advantage. When preparing sample with local variation in density (for example fully patterned devices), performing backside sample preparation might be necessary to avoid curtaining eect on the area of interest. The presented sample preparation can be adapted extremely easily to bring the sample in backside milling position. The new sample preparation method was implemented many times and every chip tested had their resistance falling within the acceptable range relative to their calibration. Even though the membrane resistance is still within the acceptable range, local temperature variations can emerge. This section presents two other methods used to evaluate the impact of sample preparation on the heating behavior of the chip. First, a COMSOL model of an intact heating membrane is compared with a model of a membrane modied by the sample preparation. This enables to estimate local temperature variations caused by the sample preparation. Secondly, an in situ calibration experiment is performed with a well know sample. A sample of BaTiO 3 is prepared following the previously presented protocol. BaTiO 3 ferro- electric properties have been extensively studied [START_REF] Kyoung | Enhancement of ferroelectricity in strained BaTiO 3 thin lms[END_REF][START_REF] Comes | The chain structure of BaTiO 3 and KNbO 3[END_REF]. In situ annealing of this sample can then be compared to the literature to estimate the actual temperature of the TEM foil as well as the heat conduction properties of the sample in this conguration.

COMSOL modeling

Protochips heating membrane

In order to measure the local heating on the surface of the chip, infrared mapping of the center of the heating membrane has been performed and shown in Figure

Modeling build for the heating membrane

In order to be able to correctly model the heat transfer in such system, it is necessary to accurately know the parameters. A heating chip is 4 mm wide by 5.8 mm long with a thickness of 300 µm. The heating membrane is located in the center over an area of 300 µm by 300 µm. A backside chemical etching is then performed to remove the silicon underneath the heating membrane location. The suspended membrane is composed of silicon carbide and silicon nitride with a total thickness of 150 nm. The silicon nitride is a protection layer and the silicon carbide is the heater. Finally, 100 nm gold tracks with a thickness of 100 nm enable a contact to the silicon carbide with the contact pads as shown in Figure 2.17 in Section 2.5.2.

To simplify the calculation, only the center of the chip is modeled. The model consists of a 800 µm by 800 µm frame with a thickness of 300 µm. In the center of the frame, a 300 µm by 300 µm area is removed to simulate the chemical back etching. A slab with a thickness of 150 nm remains to simulate the suspended membrane. Finally, an array of 9 holes each having a diameter of 5 µm and each separated by 5 µm is added to reproduce the viewing area of the membrane. This model is used to mimic a membrane prior to sample preparation and is dened as "intact membrane". A variation of the model is then created to mimic the membrane after sample preparation, and is dened as "modied membrane".

For both models, a 30 µm in diameter disc is drawn in the center of the viewing area. In the case of the modied membrane, this disc is extruded with a thickness of 100 nm to simulate the tungsten halo eect. Then, a trench in the membrane as shown in Figure 3.4 is removed according to the sample preparation method presented in Section 3.1. Electrical boundaries are set on the two gold layers on each side of the silicon carbide heater as shown in Figure 3.7(c). The outer edge of the gold layer is set on one side as a grounding point, and on the other side as a current source.

It is important to take into account that a solid at high temperature will emit a non negligible amount of energy as radiation. The net power emitted by a blackbody per surface area can be obtained using the Stefan-Boltzmann law. In order to properly reproduce the heat loss emerging from radiation, an outward heat ux boundary is added to each surface of the model following Stephan-Boltzmann equation :

P = eσA(T 4 -T 4 i )
With :

P : the net radiated power e = 0.96 : the emissivity of SiC σ = 5.6703 * 10 -8 Stefan's constant T membrane temperature calculated T i = 293.15 K Microscope temperature A = Area of the surface on which the outward heat ux is applied SiC emissivity reported in the literature can cover a range from 0.83 to 0.96 depending on the SiC composition. As the exact SiC composition remains unknown, the maximal value reported is used. This enables to observe the worst case scenario when the heat loss from radiations is maximized. At a set temperature of 100

COMSOL model results

Current

• C, the temperatures obtained over the viewing area for both intact and modied membranes are almost identical as shown in Figure In the condition of the model, the modied membrane presents a temperature gradient over the viewing are similar to the unmodied membrane (within the range of 3

• C to 6 • C). The temperature distribution is however dierent, and the temper- ature on the area where the sample is located is slightly lower in the case of the modied membrane. Below a temperature of 300

• C, the impact of sample prepara- tion seems very limited.

Even though such modeling results remain a strong approximation of the mechanisms that can inuence an experiment, it provides a good insight on what could potentially result from extended modication of the heating membrane, as well as the real heating process. The goal of this model is to observe the maximum impact that could have the sample preparation on the membrane ability to heat. To do so, the hole size in the membrane, the tungsten halo thickness and the SiC emissivity are increased. Finally, the geometry of the heating chip is simplied to increase calculation speed. Another source of error concerns the exact properties of the silicon carbide used by Protochips as well as the exact thickness of the heater. This

Calibration experiment using BaTiO 3

Several questions remain regarding the actual temperature of the TEM foil during in situ annealing experiment. First, the temperature measurements of the heating membrane are performed indirectly through the calibration le. Consequently, the real temperature of the TEM foil can be questioned since the membrane has been modied. Then, considering the extremely small dimensions involved, heat transfer between the membrane and the TEM foil can be limited. FIB deposited tungsten thermal conductivity remains unknown, and the heat conduction mechanisms within the TEM foil can involve nano scale eect and have unexpected behavior [START_REF] Volz | Transferts de chaleur á l'echelle du nanometre[END_REF].

To try an answer those questions, calibration experiments are performed on BaTiO 3 which properties are well known.

Experimental conditions

The observation of the domain walls by Transmission Electron Microscopy has been previously reported [START_REF] Bradt | Transmission electron microscopy of ferroelectric domain boundaries in barium titanate[END_REF][START_REF] Prashant | A review of domain modelling and domain imaging techniques in ferroelectric crystals[END_REF]. It is commonly accepted that a diraction con- [77] trast is created by the lattice distortion and ionic displacements at the domains boundaries. STEM imaging then directly allows the observation of the domain walls. The disappearance of this contrast during in situ annealing then gives a direct information on the ferroelectric to paraelectric transition in the BaTiO 3 .

As described in Section 3.1 the new sample preparation method might change the heating capabilities of the chip. The aim of this experiment is to provide information regarding the actual foil temperature and compare it to the heating membrane set temperature. In addition, heat transfer is particularly complex at the scale of a TEM foil. This experiment can then help determining if a temperature gradient exists between the foil and the membrane leads.

In situ annealing of BaTiO 3

For TEM in situ annealing of BaTiO 3 , the sample preparation was performed following the protocol described in Section 3.1. In situ annealing experiments were performed on an FEI Titan Themis using the Fusion holder from Protochips. In order to conrm this result, heating and cooling cycles are repeated.

Heat transfer study

The heat conduction in the sample is studied by performing consecutive heating and cooling of the TEM foil at dierent rates. Live HAADF imaging is performed with an acquisition time of 0.4 s to ensure rapid detection upon disappearance and reappearance of the domain wall.

Heating and cooling cycles are performed at temperature ramps of 5,10,20,40 and 80

• C per minute. First, the BaTiO 3 TEM foil is heated until complete disap- pearance of the domain wall demonstrating the paraelectric transition. The sample is then cooled down with an identical temperature ramps until reappearance of the domain wall. For all the dierent temperature ramps used during this experiment, paraelectric transition is observed at 180.3±1.3

• C during heating. Then, the ferro- electric transition is observed at 146.2±1.1

• C during cooling.

In order to observe the paraelectric transition using an increased temperature ramp, heat pulses are applied to the sample. The temperature rate provided by the manufacturer is estimated to 10 6• C/s when applying a heat pulse for both heating and cooling [START_REF] Lawrence F Allard | A new mems-based system for ultra-high-resolution imaging at elevated temperatures[END_REF]. The heat pulses are set for a duration of 1 s between the reference temperature of 25

Discussion

Three main hypothesis can explain the temperature dierences observed in this experiment compared to the reported Curie temperature for BaTiO 3 . First, as dis- cussed in Section 3.2.1, modication performed on the membrane might create a dierence between the calibrated set temperature and the real membrane temperature. COMSOL modeling presented however suggests that this eect is limited below 300

• C. Secondly, the heat transfer between the membrane and the TEM foil can be limited. FIB deposited tungsten is dierent from the pure metallic material, and its thermal conductivity is unknown. Moreover, the 20 • angle between the foil and the membrane leads to a small contact area. Finally, nanoscale eect can be considered regarding the ferroelectric properties of the BaTiO 3 , and the impact of the electron beam on the sample can also be taken into account. BaTiO 3 is a well known material and the impact of scale on the Curie temper- ature have been extensively studied [START_REF] Li | Signicant increase of curie temperature in nano-scale BaTiO 3[END_REF]. This article demonstrate that the Curie temperature can drastically increase when the size of BaTiO 3 particles decreases.

In the present work, in situ annealing is performed on a 200 nm thick TEM foil. The paraelectric transition is observed at 180.3±1.3

• C. This result is in agreement with the Curie temperature-particle size phase diagram presented in Figure 3.14. A new sample preparation method has been developed for in situ annealing experiments and is presented in Section 3.1. COMSOL modeling as well as calibration experiment have been performed to evaluate the actual sample temperature during in situ annealing. The modeling results suggest that the modications performed on the heating membrane have little impact for temperatures below 300 • C. Then, the calibration experiment on BaTiO 3 have shown a rapid heat transfer between the membrane and the TEM foil. This section presents result obtained during TEM in situ annealing of a Phase Change resistive memory sample using this method.

Introduction

Chalcogenide Phase-Change Materials (PCM) such as Ge-Sb-Te alloys are currently being developed for use in Phase-Change Random Access Memories (PCRAM).

These materials are considered as a promising technology for new generations of non-volatile memories and as such they are the focus of an intense research activity.

Prototypical chalcogenide phase-change compounds, such as GeTe and Ge 2 Sb 2 Te 5 (GST), exhibit the ability to switch quickly and reversibly between their crystalline and amorphous phases with dierent optical and electrical properties. PCMs oer a unique set of features such as fast programming, good cyclability, high scalability, multi-level storage capability and good data retention. [START_REF] Raoux | Phase change materials[END_REF][START_REF] Volker L Deringer | Microscopic complexity in phase-change materials and its role for applications[END_REF][START_REF] Franceschini | Microelectronics and nanometer structures[END_REF][START_REF] Navarro | Material engineering of Ge x Te 100-x compounds to improve phasechange memory performances[END_REF][START_REF] Bruns | Nanosecond switching in GeTe phase change memory cells[END_REF][START_REF] Raoux | Phase transitions in Ge-Te phase change materials studied by time-resolved x-ray diraction[END_REF] Controlling their crystallization is a challenge and numerous studies have been conducted to probe interface and size eects on PCM crystallization, mostly on thin lms (in the sub-30 nm thickness range) capped with various materials [START_REF] Ohshima | Crystallization of germanium-antimony-tellurium amorphous thin lm sandwiched between various dielectric protective lms[END_REF][START_REF] Pandian | Inuence of capping layers on the crystallization of doped Sb x Te fastgrowth phase-change lms[END_REF][START_REF] Simpson | Toward the ultimate limit of phase change in Ge 2 Sb 2 Te 5[END_REF][START_REF] Raoux | Crystallization properties of ultrathin phase change lms[END_REF]. However the impact of oxidation was not considered in these studies and the surface of GeTe and GST samples is known to be quickly oxidized when exposed to air. [START_REF] Gourvest | Impact of oxidation on Ge 2 Sb 2 Te 5 and GeTe phase-change properties[END_REF][START_REF] Yashina | X-ray photoelectron studies of clean and oxidized α-GeTe(111) surfaces[END_REF] Recently, it was shown that impeding surface oxidation by deposition of a suitable capping layer strongly increases the crystallization temperature in the case of 100 nm thick GeTe and GST lms. [START_REF] Noé | Impact of interfaces on scenario of crystallization of phase change materials[END_REF] As a result, the stability of the amorphous phase of these PCMs can be increased by avoiding surface oxidation. From Scanning Transmission Electron Microscopy (STEM) images obtained at room temperature after various annealing treatments, it was shown that in oxidized lms the crystallization starts at the oxidized surface, while in non-oxidized lms nucleation starts inside the PCM lm. [START_REF] Noé | Impact of interfaces on scenario of crystallization of phase change materials[END_REF] The conclusion was that surface engineering can be used to control the crystallization temperature and mechanisms of PCMs. Nevertheless, acquiring STEM images in situ during annealing is required to get a full understanding of the crystallization process. Particularly, the rst steps leading to the formation of the crystalline phase at the atomic scale remains unclear. In situ transmission electron microscopy studies have already been conducted to study for instance the phase transition of GST nano-bridges in electric eld [START_REF] Meister | In situ transmission electron microscopy observation of nanostructural changes in phase-change memory[END_REF], the sublimation of GeTe nanowires at high temperature [START_REF] Yim | Sublimation of gete nanowires and evidence of its size eect studied by in situ tem[END_REF] and the crystallization rate of GST under laser pulse irradiation [START_REF] Santala | Nanosecond in situ transmission electron microscope studies of the reversible Ge 2 Sb 2 Te 5 crystallineamorphous phase transformation[END_REF]. Nevertheless, no detailed study of the crystallization steps in PCMs at a nanometer scale has been provided yet.

STEM in situ annealing of GeTe thin foil

The amorphous 100 nm thick GeTe lms were deposited by magnetron sputtering in an industrial cluster tool on a SiO 2 layer (500 nm thick) obtained by thermal oxidation of the Si substrate. GeTe layers were either protected by in situ deposition of a 10 nm thick SiN capping layer or left uncapped and then exposed to air for 1 month before measurements. The composition of the lms was measured by Rutherford back-scattering and found equal to Ge 52.4±0.6 Te 47.6±.6 . Temperature-resolved optical reectivity (wavelength equal to 670 nm) and resistivity measurements were performed while annealing both capped and uncapped samples at a heating rate of 10

• C/min. The transition of a PCM from amorphous to crystalline states is accompanied by a reectivity increase and a resistivity decrease. [START_REF] Raoux | Phase change materials[END_REF] FIB sample preparation is performed using the method presented in Section 3.1.

The freshly prepared sample is immediately transferred into the microscope in order to limit material oxidation or possible contamination. Experiments were performed using a FEI Titan Themis transmission electron microscope operated at 200 keV.

A low probe current and a minimal beam exposure time were used during the in situ experiments in order to limit the inuence of the electron beam on the crystallization process. [START_REF] Pandian | Inuence of electron beam exposure on crystallization of phase-change materials[END_REF] Prior to all in situ experiments, the GeTe foil was irradiated by the electron beam for 15 minutes. No change was observed showing that there is little impact of the electron beam at room temperature. Experiments were performed using a Protochips Fusion heating holder. As described in Section 2.5.2, this holder uses a ceramic heating membrane. The relative dierence between the set temperature and the membrane temperature is estimated to be about 1.3% [START_REF] Lawrence F Allard | A new mems-based system for ultra-high-resolution imaging at elevated temperatures[END_REF].

In the condition of this experiment, the heating membrane has been modied by the sample preparation. Results presented in Section 3.2 suggest that such modication has little impact on the membrane for the temperature range used in this experiment.

The dual tilt sample holder used in the STEM experiments allows for observation along the <110> Si zone axis of the substrate. In situ annealing was performed using • C. These results show that the crystallization temperature of 100 nm thick GeTe lms changes signicantly depending whether a capping layer is present or not [START_REF] Noé | Impact of interfaces on scenario of crystallization of phase change materials[END_REF]. However, while the capped GeTe lm exhibits a single resistivity drop upon heating, at the same temperature ( 234• C) as the reectivity increases, the uncapped GeTe lm shows two consecutive changes in resistivity labelled A and B in the gure. The rst one (A) at 183

• C coincides with the reectivity increase.

One can conclude that it concerns the upper part of the GeTe lm since reectivity only probes about the top 40 nm of the GeTe layer [START_REF] Noé | Impact of interfaces on scenario of crystallization of phase change materials[END_REF]. Any change occurring deeper in the GeTe lm cannot be detected by reectivity. The heating ramp used for in situ STEM experiments is 5 • C/min instead of 10 • C/min in the reectivity and resistivity measurements. This dierence has only minor consequences. For instance, for an uncapped GeTe sample, the reectivity increase and resistivity drop measured when heating at 5 • C/min occur only 3 • C below those measured when heating at 10 • C /min (see Reference [START_REF] Navarro | Material engineering of Ge x Te 100-x compounds to improve phasechange memory performances[END_REF] and Figure 3.16 in the supplementary in- formation of Reference [START_REF] Berthier | In situ observation of the impact of surface oxidation on the crystallization mechanism of GeTe phase-change thin lms by scanning transmission electron microscopy[END_REF]).

The set temperature at which crystallization starts during the in situ STEM studies is systematically higher than expected from reectivity or resistivity measurements. For each kind of GeTe lm, capped or uncapped, three STEM samples were prepared. The onset of crystallization upon heating in the microscope occurs at the same set temperature (within ± 2 • C) for the three samples. Besides, the temperature oset between the onset of crystallization in the microscope and during reectivity or resistivity measurements is the same for the capped and uncapped GeTe samples, of the order of 36 ± 2 • C. The origin of this temperature dierence remains unclear. First, this dierence might originate from a dierence between the set temperature and the real membrane temperature. It could also be caused by a temperature gradient between the membrane and the sample. Finally, the sample size, as well as the annealing conditions are dierent. For the GeTe annealing experiment, only the top 600 nm of the TEM foil are composed of materials with low thermal conduction (100 nm GeTe layer on top of 500 nm SiO 2 layer). The TEM foil is mainly composed of crystalline silicon with high thermal conductivity. For in situ annealing of the GeTe, a 5 • C/min heating ramp is used. In addition, this sample as a higher thermal conductivity compared to the BaTiO 3 sample. This suggests that the GeTe sample is at thermal equilibrium with the heating membrane during this experiment.

Reectivity and resistivity measurements have been performed on a bulk sample under a nitrogen atmosphere. However, in situ annealing is performed in vacuum on a 250 nm thick TEM foil. Consequently, the dierent sample size, as well as the dierent annealing conditions are most likely leading to the dierence in the transition temperatures observed during those experiments. layer but exposed to an Ar/O 2 reactive plasma during Ta deposition [72]. These observations are consistent with previously reported XPS measurements showing that the GeTe thin lm surface composition depends on the surface oxidation state [START_REF] Gourvest | Impact of oxidation on Ge 2 Sb 2 Te 5 and GeTe phase-change properties[END_REF][START_REF] Yashina | X-ray photoelectron studies of clean and oxidized α-GeTe(111) surfaces[END_REF]. In this previous work it was demonstrated that GeTe surface oxidation begins with germanium oxidation, Ge atoms migrating outside the initial layer to form a Germanium oxide layer. Note that below the upper 15 nm, the Ge/Te weight ratio obtained from EDS analysis in the uncapped GeTe sample is about 40/60, as in the capped sample.

EDS analysis of capped and uncapped GeTe

In situ observation of GeTe crystalisation

Variations of crystallization temperatures observed by reectometry and resistivity measurements between oxidized and protected GeTe lms have been ascribed

to the composition changes induced by oxidation at the lm surface. To get more insight on this issue and study the crystallization mechanism at the nanometer scale, the samples were annealed in situ in the transmission electron microscope

Discussion

Note that a partial crystallization of the upper part of an amorphous lm requires that the crystal growth velocity in the lm plane at the upper surface is much higher than in the perpendicular direction. This statement could be quantied in with the fact that the nucleation probability is high in GST, which is reported in literature as a nucleation-dominated material. [START_REF] Raoux | Phase change materials[END_REF] Besides, crystal growth in the direction perpendicular to the lm surface is certainly low at 170 • C (temperature at which volume nucleation occurs in GST).

In the case of GeTe, the perpendicular growth velocity in oxidized lms, as well as the growth velocity after volume nucleation in non-oxidized lms (not determined here), probably depend on the exact composition of the amorphous phase. The composition of the crystalline phase is xed (within an extremely narrow composition window around Ge 49.5 Te 50.5 ) [106]. As soon as the composition of the amorphous phase diers from this value, crystal growth must be accompanied by rejection of the excess species (Ge or Te) and thus implies diusion. This is illustrated by optical transmission measurements in Ref. [START_REF] Guy | Evaluation of the performances of scaled CBRAM devices to optimize technological solutions and integration ows[END_REF] in which an oxidized Ge 54 Te 46 lm exhibits a two-step crystallization process, as observed in our Ge 52.4±0.6 Te 47.6±0.6 lm, while an almost stoichiometric oxidized GeTe lm (composition Ge 48 Te 52 ) crystallizes in only one step, which suggests a much more rapid perpendicular crystal growth.

Conclusion

In conclusion, by using an innovative STEM sample preparation method which is adapted to a new generation of chip-based specimen holders, the present in situ

Conclusion

In In situ biasing of a resistive memory inside the TEM involves many dierent steps and each of them is critical to successfully perform the experiment. The device extracted using the FIB must be preserved to produce a high quality sample for TEM observation. In addition, its electrical properties must remain intact to produce an electrically functional sample. The FIB deposited contact must be of high quality with a high conductivity. FIB deposited metal does not have the same conductivity as their bulk equivalent. If their conductivity is too low, it would result in the formation of a resistance in series which could prevent proper operation of the device. Also, preparing a sample on a suspended membrane is dicult. A sample preparation have been previously presented for in situ experiments using a heating membrane. In the case of in situ biasing however, the membrane is not necessary.

The chip on which the sample is positioned can then be improved in order to simplify the sample preparation.

This chapter addresses those questions by analyzing the dierent steps involved during the preparation in situ biasing experiments. First, the dierent types of samples used are observed through STEM imaging to understand their electrical layout. Secondly, FIB deposited material are studied. The composition of ion beam deposited tungsten is compared to the electron beam deposited equivalent using STEM EDS. Then, electrical measurement are performed on dierent material deposited using both the FIB and the plasma FIB with various beam conditions and chemical precursors. FIB deposited contact conductivity can then be optimized to have the smallest impact possible on the device operation. Finally, a new design for the chip supporting the TEM foil is developed, and an new FIB sample preparation is proposed.

Characterization of FIB deposited materials

The ion beam deposition of metals are a key part for TEM in situ biasing.

FIB deposits are used not only to solder the TEM foil to the chip, but also to provide the electrical contact between the sample and the rest of the circuit. It is therefore necessary to evaluate how the FIB deposited contact can aect the electrical properties of a device during an in situ biasing experiment. Composition of ion beam and electron beam deposited tungsten is studied by EDS. Then, 4 point probe measurements are performed to evaluate the conductivity of dierent FIB deposited materials.

EDS analysis of FIB deposited material

Composition variations between ion and electron beam induced deposition were measured by EDS. STEM EDS analysis were done using an FEI Titan Osiris 200 keV using the Super EDS system comprising 4 large detectors close to the specimen (collection solid angle up to 0.8 sr). Intensity processing was done using Since each precursor reacts dierently, the beam condition used for optimal 4.2. Characterization of FIB deposited materials 79 deposition varies consequently for each material. To ensure data coherence, the ion beam energy is set to 30 keV for all ion beam induced deposition. The set dimensions for each deposit are identical, and beam current is adjusted in each case to remain in an acceptable time frame relative to deposition speed calibrations.

Real dimensions of the depositions are measured in the FIB, and conductivity was calculated accordingly. In the case of EBID, the beam energy is set to 2 keV and the beam current is set to the maximum value of 24 nA to have the highest deposition rate possible.

Successive four point probe measurements are performed using the same chip. In order to do so, the four gold lines are cut by performing a cleaning cross section using a 16 keV gallium beam at 6.5 nA after the electrical measurements are performed on a FIB deposit. The image quality and etching precision at 16 keV and 30 keV are almost identical. However, using a 16 keV beam reduces the depth of amorphization and implantation by a factor of 1.6 as shown in Figure 2.8 in Section 2.3.2.2. Four point probe measurements are performed to measure the conductivity of the S2 segments after the FIB cut is performed. The measured resistance is above the instrument detection limit. Intact chips are also tested prior to usage and produced the same result. This conrms that many measurement can be performed in series using the same chip as previously deposited material do not participate in current conduction after an FIB cut of the metal lines is performed.

The conductivity measurements presented here are used to identify global trends in the FIB deposited material quality. The properties of FIB deposit material varies over time. Parameters such as vacuum quality, Gas Injection System lifetime, and beam alignment settings can have a strong impact on the nal material properties.

Secondly, it is important to discuss the error in conductivity measurement. The conductivity σ is calculated using the following equation :

σ = L (l * h) * R (4.1)
Where R is the measured resistance, L corresponds to the length of the S2 segment, l is the width of the deposit and h the deposited thickness.

The resistance R is measured with a high precision. Then, the length L of the segment S2 can also be considered as a precise measurement considering that its dimensions are dened by the lithography procedure. However, the deposited thickness as well as the actual width of the deposit are measured in the SEM. The size of the deposit is small, and the conductivity is inversely proportional to the deposit cross section. Consequently, the error in the measurement performed in the SEM can drastically change the obtained conductivity value. FIB induced deposition is calibrated for 16 keV and 30 keV ion beams. These beam energies provide the highest deposition rate. In addition, high beam energies enable to reduce the beam spot size, and limit image shift caused by charging eect during deposition. It is then easier to measure the deposit exact dimensions, and less unwanted deposition is 80 Chapter 4. Development of quantitative TEM in situ biasing techniques observed. When using 5 keV and 8 keV ion beams, more important drift is observed during deposition. It is then necessary to adjust the location of the deposited area in real time. In addition, reducing the beam energy also reduces the focusing eciency of the system. This often leads to a blurring deposit. It becomes then dicult to properly dene the edge of the deposit. As the deposition rate is also much slower, and not calibrated, overall thinner deposits are obtained. The measurement error becomes more important relatively to the deposited thickness. Consequently, the error on the calculated conductivity value is more important.

It is then important to estimate the error width and thickness measurement of the FIB deposits. The measurement is done using SEM with a resolution of around 50 nm. The main source of error however comes from human interpretation when deciding the edge location on a poorly resolved FIB deposit. A representation of the potential error measurement is presented in Annex in Figure 5.28. A measurement error in nanometer is then dened arbitrarily when measuring the FIB deposit dimensions. The calculated conductivity as well as the estimated error originating from the dimensions measurement are presented in Figure4.3(b), and summarized in Table 4.1.

Results on conductive materials

First, ion beam and electron beam deposited tungsten conductivity are compared. Then, conductivity measurements are performed for ion beam deposited platinum and tungsten. Finally, to evaluate the inuence of beam energy on the FIB deposited metals, electrical measurements are performed on ion beam deposited tungsten with dierent beam energy.

EBID is compared to IBID in the case of tungsten deposition using WCO 6

precursor. Results show that electron deposited tungsten presents a conductivity of 2.34 * 10 4 Ω -1 .m -1 while the ion beam deposited tungsten at 30 keV has a measured conductivity of 2.66 * 10 5 Ω -1 .m -1 . As shown in Figure 4.1, the EBID deposited material is rich in carbon and oxygen from the incomplete decomposition of the precursor molecules. This can explain the much lower conductivity measured for this material.

The platinum deposited with a 30 keV ion beam showed a conductivity of 1.25 * 10 5 Ω -1 .m -1 . Then, tungsten deposited in the same conditions presents a conductivity of 2.66 * 10 5 Ω -1 m )-1 . Tungsten and platinium conductivities obtained in the literature are respectively 8.9 * 10 6 Ω -1 .m -1 and 9.3 * 10 6 Ω -1 .m -1 . This represent a dierence of about one order of magnitude between FIB deposited materials and their pure crystalline equivalent. This dierence can be easily explained. As described in Figure 4.1, FIB deposited material is rich in gallium. In addition, due to the deposition mechanism, its structure is completely amorphous. The material quality is then naturally inferior to a pure, crystalline equivalent. Still, FIB deposited tungsten seems to have a better conductivity than FIB deposited platinum. Finally, the conductivity of tungsten is compared for dierent beam energies. An increase in conductivity is observed when decreasing the beam energy. A conductivity of 2.66 * 10 5 Ω is measured at 30 keV while an 8 keV beam deposits tungsten with a conductivity of 8.90 * 10 5 Ω. This trend however appears to change at 5 keV where a conductivity of 3.27 * 10 5 Ω is measured. However, tungsten deposition at 5 keV is found particularly inecient. A very slow deposition rate, as well as a strong drift are observed. It is consequently dicult to determine the edges of the deposited area. Secondly, the measured thickness of the deposit is in the same order of magnitude than the dened error in the measurement. This explains an estimated error of about one order of magnitude for the calculated conductivity.

Results on insulating materials

Insulating materials can also be deposited using both electron and ion beams.

It is shown that electron beam deposited SiO 2 using the Tetraethoxysilane (TEOS) precursor produces a highly insulating material. Its conductivity is below the measurement capabilities of the instrument. However, gallium ion beam deposition using the same precursor could not be performed as every attempt resulted in sample etching.

The deposition of insulating material is found particularly ecient using the pFIB. First, the pFIB deposition rate is much faster compared to that in a regular FIB. Then, the xenon beam deposited SiO 2 conductivity is below the measurement capabilities of the instrument.

Electron beam induced deposition of TEOS produces a highly resistive material. The electron beam induced deposition rate is however particularly slow. The Gallium beam deposition of insulating material could not be performed. This is due to the fact that, even when using an increased gas ow, and a reduced beam current and beam energy, only sample etching was observed. Moreover, gallium ion beam deposition of insulating material is not advised. It has been reported

that implanted gallium can create leakage current in the insulator and increase its conductivity [START_REF] Sànchez | Ion and electron beam assisted growth of nanometric simon structures for near-eld microscopy[END_REF].

A very good insulator could be deposited in large quantities using the Xenon beam. Two reasons could explain the observed insulating properties. First, Xenon ions are supposedly inert and therefore less likely to cause leakage current. As a consequence, xenon implantation should have less impact compared to gallium implantation [START_REF] Sànchez | Ion and electron beam assisted growth of nanometric simon structures for near-eld microscopy[END_REF]. Secondly, an organic precursor (C 6 H 24 O 6 Si 6 ) is used instead 4.2. Characterization of FIB deposited materials 83 of an inorganic compound (Si(OC H 3 ) 3 ). It is then possible to suggest that the precursor decomposition is more ecient in the conguration of a pFIB.

Discussion

The deposition rate observed during electron beam induced deposition is much lower compared to ion beam deposition. In addition, the conductivity of the resulting material is also much lower. Electron beam induced deposition is consequently not suited for contact deposition during in situ biasing sample preparation.

The material deposited with the pFIB is also studied. Present results show that the pFIB can deposit highly insulating material in large quantities. However, the conductivity of metals deposited with a xenon beam is particularly low. Secondly, the increased beam size limits the resolution during imaging and deposition. This tool is well suited for large scale circuit edit. In the context of contact deposition during sample preparation for in situ TEM biasing experiment, the use of the pFIB is limited.

Conductivity measurements performed on tungsten deposited at dierent beam energies suggest that the conductivity decreases when the beam energy increases. A decrease of a factor 3.3 is observed in the conductivity between 8 keV and 30 keV.

However, the deposition rate observed experimentally between 8 keV and 30 keV increases by a factor of 12. In addition, 16 keV and 30 keV beam leads to better imaging quality and lower drift during the deposition. FIB deposited contact resistance can then be decrease more eciently by depositing an increased amount of material using a 16 keV ion beam.

In situ biasing dedicated sample preparation

The goal is to operate a resistive memory device in situ during TEM observation. Its complex structure involves several interconnected metal lines underneath a specic device in fully patterned wafers. The metallic interconnections surrounding the sample, in addition to small device thicknesses make such sample prone to short circuit. It is therefore complicated to prepare fully patterned sample for in situ biasing experiments. To facilitate the experiment, samples are manufactured specically for in situ experiment. They present the exact same composition as fully patterned devices, but the layout is made simpler to facilitate sample preparation.

In this section, samples are prepared using conventional FIB sample preparation with a nal cleaning performed at 5 keV. STEM observation is performed on a FEI Titan Themis at 200 keV. The Layout of in situ biasing dedicated sample is presented. It is then compared to fully patterned devices. Then, a new chip design for in situ biasing experiment is presented. Finally, a sample preparation procedure is described to perform in situ biasing TEM experiment on the two dierent sample congurations.

STEM imaging of in situ dedicated CBRAM Stacking

Here, the conguration of a dedicated sample has been studied. A STEM HAADF image of the sample is shown in Figure 4.4. This sample presents a 2D structure where the top and bottom electrode as well as the memory layer are deposited over the entire wafer. The top and bottom electrode are separated by a SiN layer. Then, tungsten via are used to locally connect the resistive memory to the electrodes. This ensures that resistive switching occurs on a limited eld of view, in the vicinity of the via, making changes in the sample easier to locate. Tungsten via have a density much higher than the rest of the sample. Consequently, a small curtaining eect is visible following sample preparation. The memory layer is located on top of the via. Consequently, it is not impacted by the curtaining eect.

The sample is manufactured using a conductive doped silicon wafer. This enables an increase in thickness of the bottom electrode. This provides more versatility during sample manipulation and sample contacting. The detailed composition of this sample is presented in Chapter 5. The deposition conditions of each material, as well as their nal composition are identical to a fully patterned samples. The only dierence comes from the electrical layout. This enables sample preparation and TEM observation to be easier during in situ biasing experiments. Secondly, this enables similar electrical properties to be compared to fully patterned sample.

STEM imaging of fully patterned CBRAM Stacking

Devices used for ex situ electrical characterization have a more complicated layout. Top view and cross section images of the fully patterned sample is shown The presence of metal interconnects are problematic when it comes to in situ sample preparation. Large metal lines present across the TEM foil can easily lead to a short circuit. The shape and layout of those interconnections can be completely dierent depending on which part of the wafer is observed. It is therefore complicated to locate a single device with no interconnection around it. Finally, many dierent structures are present in the TEM foil such as metal lines, dummies, or aluminum bridges. Since each material has a dierent density, a strong curtaining eect is observed during FIB preparation.

One of the key advantages of this sample conguration is the size of the electrical contacts. Left and right metal lines are 1 µm thick, and they are located on opposite sides of the sample. The sample can therfore be connected to a chip by simply depositing metal on each side of the chunk. However, considering this geometry, the protection layer used for FIB sample preparation needs to be electrically insulating.

If a conductive tungsten layer is used as a protection layer, it would create a short circuit between the left and right electrode. Consequently, pFIB deposited SiO 2 is used. As described in Section 4.2.2, this material is highly insulating and can be deposited in large quantities. techniques

Improvments of in situ biasing chip design

The sample geometry as well as the electrical layout of each sample is established.

The location of the electrical contact is known, and the FIB contact deposition is optimized. The sample then needs to be deposited onto a chip and thinned down to electron transparency.

The chips used for electrical biasing in the TEM are very similar to the in situ heating chips. Both chip design are described in Section 2.5. Two main dierences can be identied. First, the membrane of a biasing chip is entirely composed of silicon Nitride. Then, 100 nm thick gold line are present to provide electrical connection. They extend from the central part of the viewing area and reach contact pad on the silicon chip.

Customized chip design and manufacturing

Preparing a TEM foil on a suspended membrane using the method described in Section 3.1 becomes more complex as electrical contacts are necessary. Then, only one side of the TEM foil can be observed during thinning. This can be an issue when trying to locate a device in the TEM foil during thinning. As the sample is only soldered to the membrane at its base, contacting the sample to the chip becomes more dicult. Connecting the top electrode to the chip metal tracks is more likely to result in a short circuit. During this PhD, extensive work has been performed 4.3. In situ biasing dedicated sample preparation 87 coupling the FIB and the pFIB for in situ biasing dedicated sample preparation on suspended membranes. However, this work yielded limited results due to its over complication. It is therefore not described here. A more simple and more reliable method was therefore necessary. For in situ biasing, the use of a suspended membrane is not necessary. Removing the membrane can then simplify the entire process. A new design for the chip is then developed and manufactured. Secondly, due to hardware malfunction, mask alignment between the dierent steps could be achieved with limited precision. The gold patterns in the top surface of the chip were often misaligned with the backside chemical etching pattern. In addition, access to precise chemical etching equipment was not possible in the time of the PhD.

As they did not require chemical etching, chips dedicated to 4 points probe measurement have been produced. Even with a low success rate, enough chips were manufactured correctly and provided the results presented in Section 4.2.2.

Improving the designs and manufacturing conditions

It was then necessary to improve the quality of the chips dedicated to in situ biasing. Developing a clean room process requires time, and the production of the rst generation of chips did not reach expectations. To improve the quality of the chip, and to decrease the production time, a second generation of chip is produced in collaboration with the manufacturer Protochips. The designs are adapted using masks already existing in their conventional procedures. Thanks to dedicated facilities, the rapid production of the second generation of chips was made possible. The second generation of chips is presented in Figure 4.9. The quality of the lithography procedure as well as the metal deposition are increased. However, implementing a clean room process is complicated. The chemical etching is a particularly sensitive step and it often requires calibration before reaching the expected precision. Despite using dedicated facilities, the trench is slightly over etched. The width of the trench ranges from 35 µm to 45 µm instead of the targeted width of 10 µm.

As the sample is supposed to bridge the trench, wide chunk of material needs to be extracted during FIB preparation. Such dimensions remains within the capabilities of the FIB. This however increases the duration of sample preparation as larger sample need to be prepared to bridge the gap.

Dicing the wafer into several chips is also a complicated step. In order to have the trench on the edge of the chip, it is necessary to dice the silicon through a chemically etched hole. As shown in Figure 4.9(c), small damage are present on the diced face. However, as shown in Figure 4.9(b) the area where the sample should be located is intact even after dicing.

Due to the development done at CEA in collaboration with Protochips, this new design has reached production and is now a new solution proposed by Protochips for in situ biasing experiments using FIB sample preparation.

Implementing new chip designs for FIB sample preparation

The second generation of chip can then be used for in situ biasing experiments. The congurations of the in situ dedicated stacking as well as the fully patterned devices are presented. Due to the new chip design, a new sample preparation method techniques

Sample preparation for in situ dedicated CBRAM stacking

First, the sample preparation is done using in situ dedicated samples. tilt. No rotation is needed and transfer can be done directly after lift out. As the sample is positioned on the edge of the chip, the tungsten GIS can be inserted easily without risking touching the sample. Tungsten is deposited to solder the sample on each side of the trench as shown in Figure 4.10(c). The Omniprobe is then detached using the ion beam. Additional tungsten can then be deposited. This can improve the contact quality and ensure better stability. Finally, the sample is thinned down progressively to obtain a foil with a thickness of around 400 nm as shown in Figure 4. 10(d).

Identically to conventional sample preparation with a copper grid, the chip can be rotated during thinning. As both sides can be observed during thinning, the tungsten VIA inside the sample can be easily located in the foil.

The sample is however not electrically functional at this stage. Both top and bottom electrode are connected to each side of the trench, thus creating a short circuit. During sample preparation, this brings a major advantage. FIB exposure can charge the sample. As the sample is shorted during the majority of the preparation, charges can be easily evacuated. This prevents electrostatic discharge (ESD) that could destroy the device during the preparation. techniques In order to be able to operate the sample in situ, each electrode must be electrically connected to a single side of the trench. Both top and bottom electrode then need to be cut. As shown in Figure 4.11, two successive FIB cuts are performed using the ion beam. This step is critical, and each cut must be precisely performed. When cutting the bottom electrode on the left side of the sample, there is a high risk of cutting the top electrode as well. The thicker tungsten deposition used during the rst step of the preparation is therefore important. It provides the additional thickness on the top electrode necessary to safely cut the bottom electrode. On the right side, the conductive doped silicon wafer guarantees an electrical connection even if the bottom electrode is removed during this step. This cuts are performed using at 5 keV beam energy to prevent gallium implantation below 30 nm from the foil surface as shown in Figure 2.8 in Section 2.3.2.2. Once both cuts are done, sample is thinned down to the desired thickness of 250 nm, thus removing the damaged layer formed when cutting the electrodes. Finally, a cleaning step is performed at 2 keV to further remove the amorphous material on the foil surface. A thickness of 250 nm is chosen during in situ experiments for several reasons. First, it improves This sample preparation method enables the production of high quality TEM foil containing a functional device. High quality TEM foil can be obtained thanks to a better monitoring during thinning coupled with a low voltage nal cleaning step. This new method for sample preparation using the new chips is very similar to conventional TEM sample preparation. It is much safer and more reliable than previously presented sample preparation for in situ heating and biasing experiments.

It involves no transport of a fragile thinned TEM foil. Without the suspended membrane, there is no need to tilt the sample during the transfer. It is consequently much quicker as this method does not require to take the sample out of the FIB.

Each step from lift out to thinning can be performed consecutively.

Sample preparation for fully patterned CBRAM stacking

Fully patterned samples can also be prepared using a similar procedure. As previously described, this conguration requires to use an insulating protection layer.

First, a 2 µm thick SiO 2 layer is deposited using a 16 keV Xenon ion beam with a current of 59 nA. Figure 4.12(a) shows the surface of the wafer after deposition of the protection layer. The sample then needs to be taken out of the xenon plasma FIB and transferred to a gallium FIB to carry on with the preparation. The device is lifted out in the FIB as shown in Figure 4.12(b). Identically to the previously presented method, the chunk is lifted out and directly transferred onto the chip as shown in Figure 4.12(c). Then, contacts are deposited using the ion beam. The sample is then thinned down to electron transparency and nal cleaning step can be performed at low voltage.

The nal sample is presented in Figure 4.13. The pFIB deposited protection layer is found perfectly suitable for FIB preparation. The entire device is preserved and can be observed during the TEM experiment. As shown in Figure 4.13(b), interconnections and metal dummies are properly isolated and do not create short circuits.

Preparing a fully patterned device for in situ biasing requires two dierent pieces of equipment. This consequently leads to an increase in preparation time. In opposite to what was expected, contacting the sample to the chip is however much simpler compared to in situ dedicated devices. Due to its conguration, no short techniques In situ biasing of a reference pn junction

In order to verify that the presented sample preparation method is viable, a simple pn junction is examined in situ. pn junctions present well known characteristics and have been extensively studied over the years [START_REF] Gupta | P-N Junctions and Their Breakdown Mechanisms[END_REF][START_REF] Simon | Physics of semiconductor devices[END_REF][START_REF] Shibata | Imaging of built-in electric eld at a pn junction by scanning transmission electron microscopy[END_REF][START_REF] Cooper | Experimental o-axis electron holography of focused ion beam-prepared si p-n junctions with dierent dopant concentrations[END_REF]. This makes them a perfect candidate for reference measurements during in situ biasing experiments. The theoretical behavior of this material can be compared to quantitative measurements obtained during an in situ biasing experiment.

Experimental setup description

The sample that was used is composed of a 1 µm thick boron doped silicon layer on top of a phosphorous doped silicon wafer. The pn junction is symmetrically doped with a concentration of 1 * 10 19 cm -3 . The sample is prepared following the method presented in Section 4.4.1 for in situ dedicated samples. The chip containing the pn junction sample is then mounted on the in situ TEM holder. The experiment is performed using a FEI Titan Themis microscope at 200 keV. In situ biasing of the sample is performed using a Keithley 2636B power supply. Finally, in order to make sure that the sample is electrically functional before the experiment, a voltage is applied to the pn junction while measuring the current.

The resulting I(V) prole is presented in Figure 4.17 and compared to a conventional pn junction prole. A voltage from -10 V to 10 V is applied on the sample. The resistance of a pn junction is not linear and depends on the applied voltage. Ohm's law can then only be used to obtain the resistance of the junction at a single point.

During forward biasing, a resistance of 82.6 kΩ is measured at 10 V. On the opposite, a resistance of 571.4 kΩ is measured when applying a reverse bias of -10 V. As shown in Figure 4.17, the current voltage curve obtained during in situ biasing is in agreement with typical pn junction characteristics.

An important leakage current is observed. As shown in Figure 4.17 Those results suggest that the electrical properties of the pn junction are in agreement with the literature. This demonstrates the viability of the sample preparation previously presented. The pn junction has been electrically connected to the chip and thinned down to electron transparency, and its electrical properties have been preserved. The next step is then to perform quantitative measurements in the TEM during in situ biasing of the pn junction.

Dierential Phase Contrast measurements

The electric eld in a specimen can be measured using techniques such as electron holography or Dierential Phase Contrast (DPC) [START_REF] Williams | Transmission electron microscopy: a textbook for materials science[END_REF]. In the present work, DPC measurements are performed on the pn junction for dierent applied voltages. It is important to understand the signal that will be expected, and as such, the correct experimental conditions can be selected so that the required sensitivity is obtained.

For a symmetrical pn junction doped with a concentration of 10 19 cm -3 , calculations show that at equilibrium, the depletion region is 16.6 nm wide and the expected electric eld is 1.26 MV/cm or 0.126 V/nm. As discussed in Section 2.4.5, the beam deection caused by an electric eld in the sample can be obtained from the equation :

γ = t 2K 2 2me h 2 E (4.2)
With γ the angular displacement (in µrad), t the sample thickness (in cm), K the wavevector, m the mass of the electron, e the charge of the electron, and E the magnitude of the electric eld (in V/cm). When measuring a beam deection, equation 4.2 can be used to calculate the magnitude of the electric eld in the direction orthogonal to the beam :

E ≈ γ 0.3438 t (4.
3)

The beam deection in a DPC measurement is obtained from the shift of the transmitted beam on a segmented detector. Consequently, increasing the camera length enables an increase in the beam deection at the detector plane and therefore improves the sensitivity of the measurement. Increasing the camera length while maintaining a constant convergence angle results in an illuminated area much larger than the detector surface. Consequently, the convergence angle needs to be reduced. Abbe's law states that the convergence angle is directly linked to the beam diameter as shown in Figure 4.18. Consequently, a tradeo needs to be made for DPC measurements between spatial resolution and eld sensitivity.

The experiment is performed in Low Magnication (LM) mode at a 8500x magnication. In LM mode, the objective lens is turned o to obtained a large eld of view. This allows a camera length of 9.1 m to be used, thus increasing the sensitivity when measuring the beam deection. A semi convergence angle of 0.27 mrad is obtained and a probe current of 50 pA is measured. As shown in Figure 4.18, the spatial resolution obtained according to Abbe's criterion is around 6 nm, which is sucient to resolve the depleted region in the specimen. A low beam current of 4.5. In situ biasing of a reference pn junction 101 50 pA is selected as it provides a good compromise between an improved sensitivity and a reduction of charging. Dynamical diraction contrast will also contribute to the measured signal. Consequently, the TEM foil is tilted to remove this contrast from the area of interest.

The beam is then shifted to obtain an even illumination over the 4 dierent segments of the detector. The software Velox from FEI is used to perform the measurements. The camera gain is optimized to image the region of interest composed of regions 3 to 5 as shown in

Dierential Phase Contrast calibration and quantication

The intensity dierence in each pixel caused by the beam deection can be calibrated. This calibration is valid for the set of parameters used, such as magnication, acceleration voltage, camera length, convergence angle and detector settings.

The equation 4.3 can then be adapted to describe the electric eld obtained in each pixel :

E i,j ≈ I i,j ζ i,j 0.3438 t (4.4)
Where ζ i,j is the coecient linking a beam deection to a change in intensity on the four segments images. In order to calculate ζ i,j , a reference measurement is necessary. induced beam shift. The image of the beam both before and after the manual shift are also acquired. First, the beam deection S created by the induced beam shift is calculated. Then, the intensity dierence δ i,j caused by the induced beam shift is retrieved. The coecient ζ i,j is calculated following :

ζ i,j = S δ i,j (4.5)
First, the beam deection induced by the manual shifting of the beam must be measured. A simple cross correlation between the two beam images enables to obtain the value of the beam shift, expressed in a number of pixels p for both x and y directions. The convergence angle used during this experiment is noted α.

The beam diameter noted D beam and expressed in pixels is measured on the CCD camera. The induced deection of the beam can then be linked to the measured shift on the CCD camera following the equation :

S = ( 2 * α D beam * p x ) 2 + ( 2 * α D beam * p y ) 2 (4.6)
The beam diameter is 136 pixel for a convergence angle of 0.27 mrad. An induced shift of 42 pixels and 17 pixels is measured in the x and y directions respectively.

The dierence between these two beam images is shown in Figure 4.20. In the conditions of this experiment, this leads to a value for S of 179.9 µrad obtained as followed :

S = ( 2 *
δ i,j = (∆I s AC -∆I 0 AC ) 2 + (∆I s BD -∆I 0 BD ) 2 (4.8)
The calibration factor ζ i,j is obtained by dividing the calculated shift S by the change in intensity δ i,j . This factor then translates the change in intensity measured in each pixel into a deection of the beam in microradian.

Alignment of the segmented images with the camera plane

The goal is then to obtain the image showing the electric eld measured in two orthogonal directions x and y. The sample is not aligned with the detectors segments and the segments images then need to be rotated. The rotation to be applied to the segments images can be calculated using the shift measured in each direction as followed :

ω = arctan (∆I s AC -∆I 0 AC ) * py-(∆I s BD -∆I 0 BD ) * px (∆I s AC -∆I 0 AC ) * px-(∆I s BD -∆I 0 BD ) * py (4.9)
The angle between the camera plane and the detectors segments is known. In addition, the intensity change in the segments images can be linked directly to a beam deection. The Equation 4.9 is then combined with Equation 4.4 to obtain the electric eld information. This information can be obtained for each direction of the plane orthogonal to the electron beam.

Application of the calibration on the pn junction measurements

The calibration is then applied on the 4 raw segments images of the pn junction shown in Figure 4.19. For each segments image, the intensity I i,j is normalized, and the normalized intensity I 0 i,j of the segments images obtained over vacuum is subtracted. The equation 4.4 is applied on the four segments images to convert the measured intensity into a eld value. As the angle ω is known, the image showing the electric eld in x and y directions can be calculated using the equation :

E max = 2q ε N D N A N D + N A V bi (4.11)
Where the silicon relative permittivity ε is expressed as :

ε = ε Si * ε 0 (4.12)
And where the built in voltage V bi can be expressed as : The increased width for the electric eld as well as decreased eld value in regard to the simulation results can be explained by multiple factors. First, the simulation considers that the pn junction is abrupt, which is not the case in a real sample. This is an approximation made for calculation purposes. As shown in Figure 4.23 (a), the SIMS prole obtained on the same sample shows that both sides of the junction present a gradual change in dopant concentration between the highly doped region, and the background concentration [START_REF] Cooper | Experimental o-axis electron holography of focused ion beam-prepared si p-n junctions with dierent dopant concentrations[END_REF].

V bi = kT q ln( N D N A n 2 i ) (4.
Secondly, it is necessary to take into account the artifacts caused by sample preparation. As described in Section 2.3.2.2, FIB exposure during sample preparation creates amorphous sidewalls. Such regions cannot participate in the formation of an electric eld. Secondly, it has been reported that FIB exposure also impacts the dopant activity in crystalline silicon [START_REF] Cooper | Experimental o-axis electron holography of focused ion beam-prepared si p-n junctions with dierent dopant concentrations[END_REF][START_REF] Cooper | O-axis electron holography for the measurement of active dopants in silicon semiconductor devices[END_REF][START_REF] Cooper | Experimental o-axis electron holography of focused ion beam-prepared si p-n junctions with dierent dopant concentrations[END_REF]. As shown in Equation 4.4, the measured value of the electric eld is inversely proportional to the thickness.

The thickness value used for the calculation is the thickness of the entire TEM foil. As only part of the sample can be dened as electrically active, the calculated electric eld values are naturally underestimated.

Moreover, it has been shown that the emission of secondary electron during TEM observation can lead to surface charging on the TEM foil [START_REF] Fazzini | Eects of beam-specimen interaction on the observation of reverse-biased p-n junctions by electron interferometry[END_REF][START_REF] Beleggia | Inuence of charged oxide layers on TEM imaging of reverse-biased p-n junctions[END_REF]. This surface charging also impacts the dopant activity in the sample [START_REF] Twitchett-Harrison | High-resolution threedimensional mapping of semiconductor dopant potentials[END_REF]. The width of the depletion region between the specimen surface and the bulk region increases as the active dopant concentration decreases. Consequently, the pn junction and the depletion region can be represented as shown in Figure 4. 23(b).

The eld information obtained by DPC is a 2D information. However, the sample is a 3D object with a thickness of 265 nm. The 2D information produced during the DPC acquisition is a projection of the eld present over the whole thickness of the sample. In addition, every measurement is convoluted by the size of the beam.

The beam diameter in the condition of this experiment is around 6 nm. The eect of the 2D projection of the electric eld becomes more pronounced as the sample is tilted in order to remove the diraction contrast. These artifacts, in addition to the electrically active thickness in the sample, lead to a decrease of the maximum electric eld measured compared to simulations.

Multiple DPC acquisitions were performed in the same conditions for applied voltage from -10 V to +10 V. The voltage step size is set to 1 V in reverse biasing, and 2 V in forward biasing. The maximum eld value measured for dierent applied voltages is shown in Figure 4.24. The theoretical electric eld values are calculated using the simulation tool described in reference [START_REF] Klimeck | Nanohub.org tutorial: Education simulation tools[END_REF] and compared to experimental results.

Between 0 V and -1 V, the measured electric eld remains constant at -0.8 MV/cm.

Then, for reverse bias ranging from -1 V to -5 V, a similar trend is observed between experimental and simulation results. For reverse biasing between -5 V and -9 V, the measured electric eld remains constant. Finally, a decrease of the measured electric eld is observed for a reverse bias of -10 V. During in situ forward biasing of the pn junction, both experimental and simulation results show a decrease of the electric eld. However, the measured electric eld values remain much higher than the ones provided by the simulation.

An interesting phenomenon is the constant electric eld measured between 0 V and -1 V. It has been demonstrated that the pn junction is properly biased, and that its electrical properties seem in agreement with simulation results. However, at -1 V, the electric eld in the junction does not increase.

One of the most likely explanation is that an additional resistor is present in series with the pn junction. When applying a low voltage, part of the voltage drop occurs across the resistor. Its resistance is linear and obey to Ohm's law. When increasing the applied voltage, a point is then reached where the voltage drop across the resistance is constant. However, the pn junction resistance is not linear but During forward biasing, this additional resistance adds up to the pn junction resistance. It is then possible that, during forward biasing, this supplementary resistance is higher than the pn junction's resistance. Consequently, the voltage drop across the pn junction is small. The electric eld present is then insucient to overcome the depletion region. A more important forward bias is then necessary to overcome the resistance and put the pn junction in forward biasing mode.

Finally, the measured electric eld is constant from -6 V to -9 V, and decreases at -10 V. This result suggests that the pn junction is in breakdown conditions. The breakdown voltage is usually measured experimentally as it depends on a number of dierent factors, such as the dopant concentration, the temperature or the junction cross section.

As shown in Figure 4.17 The pn junction used in this experiment has dopant concentration is at 10 19 cm -3 which is considered as heavy doping. However, it has been shown that the width of the depletion region in the sample is larger compared to the information provided by the simulation. This then reduces the probability of tunneling current across the junction. It is also important to note that a non negligible leakage current is measured as shown in Figure 4.17. The temperature is likely to increase due to Joule heating. Considering to the size of the sample, and the limited contact area with the chip, heat dissipation can be limited. Such conditions then favor an Avalanche breakdown [START_REF] Simon | Physics of semiconductor devices[END_REF].

The junction breakdown during in situ biasing occurs progressively between -6 V and -10 V. The high voltage involved as well as the gradual change of the junction properties suggest an avalanche breakdown. This gradual change could also explain why no change in current is observed in Figure 4.17. Finally, under Zener breakdown conditions, the voltage drop across the junction should remain constant. In avalanche breakdown conditions, there is an hysteresis eect. The material remains conductive even if the applied voltage is decreased below the breakdown voltage [START_REF] Gupta | P-N Junctions and Their Breakdown Mechanisms[END_REF]. This means that under avalanche breakdown, the electric eld across the junction decreased. Considering the present results, the most likely phenomenon observed during in situ biasing of the pn junction is an avalanche breakdown.

Conclusion

In this chapter, the sample preparation is improved in order to to perform in situ biasing on semiconductor devices during TEM observation. First, the composition and electrical conductivity of FIB deposited material is studied. For the electrical contact deposition, the 16 keV ion beam deposited tungsten is selected relatively to its deposition rate and its electrical conductivity. To establish the micro manipulation necessary to connect samples with the in situ sample holder chips, dierent sample congurations are analyzed. Then, in order to simplify the sample preparation and ensure successful biasing of the sample, new chips have been developed. In collaboration with the manufacturer, new designs are produced which enable to reduce the sample preparation time and increase the reliability of the technique. This method is applied to a reference sample to evaluate its eciency. A pn junction sample is biased in situ and quantitative electric eld measurements are performed for dierent applied voltages using Dierential Phase Contrast technique.

The experimental results are then compared with simulations. First, the dierences observed are linked to the impact of the gallium ion beam on the dopant activity.

Conclusion 111

Secondly, due to the nature of TEM observation, 3D information are lost during the acquisition. This results demonstrate that the FIB sample preparation for in situ biasing in the TEM works in the case of a simple device. Several discrepancies have been observed compared to simulation. These artifacts are known from previously reported work on pn junctions by o-axis electron holography and the results presented here are in agreement with the literature. Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices

Introduction

A progressive and systematic analysis of each step necessary to enable live TEM observation during in situ biasing of resistive memories has been made. To perform live observation during in situ biasing of CBRAM devices, the sample needs to be thinned down to electron transparency. The impact of the FIB ion beam or the TEM electron beam on the electrical operation of the device are still unknown. Before performing in situ biasing experiment on CBRAM, a detailed characterization of the device must be done. First, the detailed composition of the CBRAM device is analyzed using conventional STEM characterization. Secondly, ex situ electrical characterization is performed. The detailed information obtained during conventional electrical operation are then used as a basis for comparison for in situ biasing experiments.

Characterization of CBRAM device

A variety of dierent materials with dierent stoichiometries can be used during the fabrication process of resistive memories. The memory layer used in this work is a CuTe 2 Ge/HfO 2 stack. The rst objective is then to gather information on the material stacking and geometry as well as the elemental distribution within the memory layer.

EDS analysis of in situ dedicated CBRAM stacking

For Energy Dispersive X-ray Spectroscopy (EDS) analysis, we used the Super EDS system with 4 large detectors close to the specimen (collection solid angle up to 0.8 sr). Analysis was performed using Cli-Lorimer factors (at 200 kV available in the Esprit 1.9 Bruker software) for peak deconvolution based on Gaussian functions.

The resulting EDS map is presented in Figure 5.1.

The in situ biasing dedicated CBRAM sample presents a simple 2D structure.

The top and bottom electrodes are composed of titanium, titanium nitride, and silicon doped aluminum layers. The memory layer is composed of a 20 nm thick CuTe 2 Ge on top of a 5 nm thick HfO 2 layer. Between the memory layer and the bottom electrode, silicon nitride is used to provide electrical insulation. Finally, as shown in Figure 5.1, the tungsten via is used to bridge the silicon nitride layer and connect the bottom electrode to memory layer.

During in situ operation of the CBRAM sample, changes in composition are expected in the CuTe 2 Ge/HfO 2 stack. Consequently, an EDS linescan is performed on the memory layer to have more precise information on local composition variations.

Linescans are acquired over a 20 nm wide area on map shown in vertical direction. While Te tends to accumulate on upper part of the layer, the bottom part of the layer is richer in copper and germanium. While the nominal thicknesses are 20 nm for the CuTe 2 Ge and 5 nm for the HfO 2 , the actual measured thicknesses are respectively 26 nm and 7 nm. This gure also shows that the tail of the copper signal from the CuTe 2 Ge layer and from the copper doped tungsten over- lap. As described in Section 1.2.1, resistive switching occurs through the formation of a conductive copper lament across the HfO 2 layer. The HfO 2 layer is only 5 nm thick and is positioned in between two materials containing copper. Because of the sample thickness, and the size of the beam, it becomes dicult to resolve properly the copper distribution in the around the oxide layer. The overlapping of the copper signal from each side of the HfO 2 layer then causes a major issue. Identifying subtle changes in copper distribution will be particularly dicult in such conditions. This gure also shows traces of oxygen between the titanium and titanium nitride layer located on top of the resistive layer. These traces come from exposition to the atmosphere during the manufacturing process. It is however unlikely for such small traces to form a resistance during biasing. Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices

Ex situ electrical characterization of CBRAM devices

TEM in situ biasing of resistive memories aims at identifying the physical mechanism occurring at the atomic level during the device operation. As presented in Section 2.2, resistive switching involves four dierent operations dened as READ, FORMING, SET and RESET. Ex situ electrical measurements are performed in conventional operation conditions on fully patterned devices in order to provide a source of comparison for in situ electrical characterization.

Current voltage measurement of CBRAM operation

Electrical characterization was performed using an Agilent 4156C semiconductor analyzer connected to a Cascade Microtech wafer probing system. limitation in the measurement when using the current setup. An overshoot lasts for a few tenth of nanoseconds, and the SMU cannot perform the current measurement quickly enough to detect it [START_REF] Shima | Voltage polarity dependent low-power and high-speed resistance switching in CoO resistance random access memory with Ta electrode[END_REF][START_REF] Tirano | Accurate analysis of parasitic current overshoot during forming operation in rrams[END_REF]. Moreover, as the resistance is decreased, the current applied by the power supplies is increased. It then takes time for the power supply to adjust the output current according to the new resistance value of the device.

In order to evaluate the overshoot, one must look at the RESET curve. As that the amplitude and duration of the overshoot can be linked to the FORMING or SET voltage [START_REF] Tirano | Accurate analysis of parasitic current overshoot during forming operation in rrams[END_REF]. The smaller overshoot is then observed because the SET voltage is inferior to the FORMING voltage. Finally, the 1T1R device still shows no sign of overshoot.

In situ biasing of a device inside the TEM is complex. In addition, the three contacts required for 1T1R devices are extremely dicult to implement. For that reason, only 1R devices are used to perform in situ biasing of CBRAM devices.

Consequently, overshoots are expected to happen. This can become an issue as current surge involves strong Joule heating. This eect should then be monitored since it could damage devices during in situ operation.

Endurance and resistance variability in CBRAM devices

Biasing a single device in situ during TEM observation requires extensive preparation. Only one device is available at a time, meaning that no statistics are available. As resistive switching and the formation of a CF is based on stochastic mechanisms, HRS and LRS resistances can cover a wide range of values. Ex situ measurements are used to determine the acceptable resistance range that dene each resistive state. As we can see in Figure 5.4, both ON and OFF resistances present a variability of several orders of magnitude. The main factor for this variability is the stochastic nature of the switching mechanism. Chemical reactions and diusion at the atomic scale are completely random events, especially under the inuence of an electric eld, and of the temperature increase from the Joule eect [START_REF] Guy | Evaluation of the performances of scaled CBRAM devices to optimize technological solutions and integration ows[END_REF]. In some cases, resistance variability can also come from the formation of multiple laments simultaneously [START_REF] Xu | Superior retention of low-resistance state in conductive bridge random access memory with single lament formation[END_REF].

The CBRAM devices examined here have an endurance greater than 100 cycles 5.3. Electrical characterization of CBRAM devices using the in situ TEM holder 119 During the rst operation performed in situ, a strong variability in the resistance states is expected. As previously discussed, a low resistance is usually measured after the FORMING operation due to the overshoot. In addition, when the surface over volume ratio decreases, the participation of surface states increases, leading to a non negligible surface current (cf. Annexe, Figure 5.29) [START_REF] Hasegawa | Electronic transport at semiconductor surfaces, from point contact transistor to micro four point probes[END_REF]. Finally, the defects created by the FIB preparation can also lead to a leakage current. Those factors are then expected to decrease both LRS and HRS resistances during in situ operation.

Electrical characterization of CBRAM devices using the in situ TEM holder

The electrical properties of the CBRAM devices have been measured using high precision equipment. However, electrical characterization in the TEM is performed using the sample holder directly connected a Keithley 2636B power supply. Resistive memories are particularly fragile and improper electrical operation can rapidly damage a device. Before performing in situ biasing on CBRAM devices during TEM observation, it is rst important to evaluate the impact of the lift out and FIB contacting on the electrical properties of a device. This also provides information on the ability of the TEM in situ biasing system to perform electrical characterization Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices CBRAM.

Electrical characterization using the Keithley 2636B

In order to compare the results with ex situ characterization, the CBRAM device is extracted from the fully patterned wafer. It is then transferred on a chip using the FIB sample preparation method presented in Section 4.3. However, the sample is not thinned down to electron transparency.

As described in Section 4.4.2 curtaining eects and short circuits are likely to occur when thinning fully patterned devices to electron transparency. As the goal here is not TEM observation, the sample thickness is maintained at 1 µm and a low voltage cleaning is performed. This removes the amorphous sidewall on the sample which can be the source of leakage current and short circuits. As the sensitive area is not exposed to the ion beam, the device remains supposedly intact. The TEM holder is then inserted in a turbo pumping station. The sample is operated using the The RESET operation is performed successfully and an HRS resistance of 4.95 * 10 5 Ω is measured. The overshoot occurring during the FORMING operation is visible during the RESET operation and shows a current of 500 µA.

During the next SET operation, a leakage current of 9.8 µA is measured at 1 V.

Even though this value is 10 times superior compared to the FORMING leakage current, it is within the range of normal SET leakage current as shown in Figure 5.3.

The measured resistance for the following LRS is 8.12 * 10 3 Ω. One major dierence between in situ and ex situ measurement concerns the applied voltage after FORMING and SET operation. In both cases, when resistive switching occurs, the resistance of the device is greatly reduced. Consequently, the current reaches the set compliance. During in situ operation, the applied voltage is reduced in order to reduce the current owing in the sample as shown in Figure 5.5. In the case of ex situ characterization, the applied voltage keeps increasing, but the measured current remains constant as presented in Figure 5.3. This observation demonstrates that the two power supplies act dierently relatively to the current compliance.

Two hypotheses can explain the reduced device lifetime observed during this experiment. First, it is possible that the sample preparation modied the sample.

Secondly, electrical characterizations are performed in dierent conditions. The in situ TEM holder uses a Keithley 2636B power supply controlled by the Clarity software. However, ex situ characterization is performed using an Agilent 4156C connected to a probing station. As previously described, the two systems seem to act dierently when reaching current compliance. It is then possible to suggest that the in situ electrical operation of the device is not properly executed thus causing damage to the device and reducing its lifetime. To answer this question, the performances of both power supplies are studied.

Impact of the power supply and the operation conditions

In order to understand the impact of the power supply in the conditions of an in situ experiment, the electrical response of both system during resistive switching is analyzed using an oscilloscope.

An important thing to keep in mind is that power supply specications varies depending on the range of current used. For high currents, measurement is quicker and less precise. When using smaller currents, the measurement takes more time in order to obtain a better precision. It is therefore necessary to perform the measurements on a current range similar to the one used during in situ operation.

A resistance of 26 kΩ is connected to the power supply and a current compliance of 100 µA is set. Then an oscilloscope is plugged in parallel with the resistance to measure the applied voltage. In order to mimic a resistive switching, the power supply is set to apply a voltage pulse. Finally, two dierent target voltages are used. First, a voltage pulse of 2.5 V is applied in order to reach a current of 96 µA thus remaining below the set compliance. Then, a voltage pulse of 5 V is set in order 5.3. Electrical characterization of CBRAM devices using the in situ TEM holder 123 to produce a current which is higher than the set compliance. This enable to observe the output voltage of the power supply when reaching the current compliance. First, an important noise is observed in the Keithley 2636B voltage output.

Keithley 2636B voltage output measurements

Voltage spikes of ±150 mV are observed with a frequency of around 130 kHz. Then, results show that the settling time for both pulses is around 100 µs. This rapid settling time is made possible because the power supply uses mechanical switches to instantaneously apply the target voltage. This allows the observation of the behavior of the power supply when suddenly reaching the current compliance.

Figure 5.7 shows that the voltage keeps increasing for 15 µs after the current compliance is reached. Then, it takes 50 µs for the power supply to adjust its output and decrease the current down to the set compliance.

The Keithley 2636B electrical conguration of the current source and voltage source mode obtained from the manufacturer are shown in Annexe Figure 5.24.

The compliance system is a numerical feedback loop. The method used by the compliance system is to act like a clamp. If the measured output current exceeds the set compliance, the systems switches its source logic. When reaching a current compliance in a voltage source mode, the power supply switches towards a current source mode. This long process can then explain the measured response time in the order of 65 µs. Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices

According to the Keithley 2636B specication, the maximum settling time in the conditions of this experiments is 150µs. The maximum voltage that can source this power supply is 55 V. Present results are then in agreement with the Keithley 2636B specication considering the small voltage involved.

This long response time can be critical for resistive memories. When the resistive memory switches toward LRS, its resistance decreases by several order of magnitude. Consequently, for a constant applied voltage, the current owing in the device increases by several order of magnitude. Maintaining such a high current during the 65 µs necessary for the power supply to adjust its output will damage the device. The 5V pulse in Figure 5.8 shows a settling time of about 300 µs to reach 2.5 V. For a 5 V pulse, the settling time is 400 µs and the actual output voltage reached is 2.6 V. Both curves seem identical and the only dierence is the time necessary to increase the voltage by 100 mV. Finally, a noise of ± 10mV is measured and the applied voltage never leads to a current higher than the set compliance.

Agilent 4156C voltage output measurements

There is no pulse generator in the Agilent analyzer. Consequently, a long time is required to reach the target voltage. According to specication of the power supply, the measurement time is 60 µs. The measurement time is then much shorter compared to the time necessary to reach the target voltage. The power supply then has enough time to adjust its output voltage before the current goes above the set 5.3. Electrical characterization of CBRAM devices using the in situ TEM holder 125 compliance. However, the resistance change caused by resistive switching is much quicker than the settling time of the Agilent analyzer. Present results suggest that similarly to the Keithley 2636B, a long response time is expected to adjust the power supply output after resistive switching.

However, the sourcing logic of the Agilent analyzer is completely dierent compared to the Keithley 2636B. The conguration of each SMU in the power supply is shown in Figure 2.1. When an SMU in voltage source reaches the current compliance, it acts as a constant voltage source. In order to limit the current ow in such conditions, the power supply uses a current limiter based on a transistor. The exact electrical layout of the current limiters used in the Agilent power supply is unknown.

However, a similar system is presented in the Annex in Figure 5.25. Current limiters are analogical systems which physically prevent a current above the set compliance.

The response time of such system is then much quicker compared to a numerical feedback loop.

Uncontrolled voltage spikes

Another issue is identied when observing the entire pulse applied by the Kei- This gure shows that during the voltage pulse at 2.6 V (i.e. at the compliance current), a voltage spike of -4 V occurs. In about 12 µs, the applied voltage decreases from 2.6 V to -1.6 V. The power supply takes about 100 µs to increase the applied the forming operation in Figure 5.5 can therefore be a direct consequence of this observation.

The compliance system of the Keithley 2636B is not suited for resistive switching. A reverse current is observed which can cause pseudo RESET operation when reaching the compliance current. In addition, the strong oscillation of the voltage output can inuence the formation of the CF. Finally, present result demonstrate that a strong current is forced in the device during FORMING and SET operations.

The reduced lifetime of the device observed in Figure 5.5 can therefore be linked to an improper electrical operation. Even though resistive switching occurs, the physical and chemical mechanisms occurring at the atomic scale are not representative of normal functioning conditions. It is therefore not instructive to perform in situ biasing on resistive memories using the Keithley 2636B power supply.

Semiconductor analyzers are conventionally used for resistive memory electrical characterization. They naturally show better performances compared to a simple Keithley 2636B power supply. It is possible to connect a semiconductor analyzer, and even other modules such as a pulse generator, to the in situ TEM holder.

Similarly to ex situ characterization, control boards can be added to control the power supply and pulse generator with a software.

In the present work, for simplicity, only the semiconductor analyzer is used for in situ TEM characterization. It is then easy to implement, but already improves the in situ operation of CBRAM device. In this conguration, it becomes necessary to control the power supply manually using the front panel. As only a few operation are performed during in situ biasing experiment, the increase time necessary for manual programming is not an issue.

Electrical characterization using 4156C semiconductor analyzer

It is demonstrated that in situ operation of CBRAM device cannot be performed using the Keithley 2636B. In order to improve the electrical characterization during in situ TEM experiment, the Agilent power supply is used with the in situ TEM The results obtained from electrical characterization of a device prepared with the FIB are in perfect agreement with the values obtained during ex situ electrical characterization. This conrms that the lift out, transfer, and electrical connection performed in the FIB have a limited impact on the electrical properties of the CBRAM device. This also demonstrates that resistive memory devices can be properly operated using the in situ TEM holder when using high precision power supply conventionally used for ex situ characterization. Programming each operation manually is time consuming. Extensive cycling of the device is therefore not performed.

It is however possible, in the future, to implement computer control.

5.4

In situ operation of CBRAM devices

Impact of the environment on resistive switching

As discussed in Section 1.2.2.1, the formation mechanism of a CF in CBRAM involves copper migration as well as oxygen vacancies. During ex situ characterization of CBRAM, devices are buried within the fully patterned wafer. However, during in situ biasing, the memory layer is exposed to the environment. Even though the thin foil is operated within the high vacuum of the TEM column, it is then interesting to evaluate the impact of the environment on the CBRAM electrical properties.

A new sample was prepared using the method described in Section 4.

In situ operation of CBRAM devices 129

The measured Pristine resistance is 1.26 * 10 5 Ω. As shown in Figure 5.11, resistive switching is not achieved during forward biasing. When increasing the applied voltage to 6.8 V, the resistance of the sample increases to 2.60 * 10 5 Ω.

A negative voltage is then applied on the sample. The same result is observed at -8 V where the resistance increases to 9.46. * 10 5 Ω. Finally, another increase in sample resistance up to 9.65 * 10 6 Ω is observed at an applied voltage of 8 V. This last operation caused extensive damage to the sample, thus preventing TEM observation.

The impact of the atmosphere on the electrical properties of HfO 2 based re- sistive memories have been previously investigated [START_REF] Bertaud | Resistive switching of Ti/HfO 2 -based memory devices: impact of the atmosphere and the oxygen partial pressure[END_REF]. It has been shown that the conductance of the resistive memory increases when the total pressure decreases, especially for Pristine State and Low Resistance States. This can be linked to an decrease of the concentration of oxygen vacancies in the HFO 2 when the oxygen partial pressure increases. Biasing the sample at ambient pressure then could participate in injecting oxygen in the sample. This could explain the increasing resistivity during biasing showed in Figure 5.11.

Oxygen therefore seems to prevent proper resistive switching in the CBRAM device. This phenomenon is also supposedly limited once in TEM where the vacuum reaches 1 * 10 -6 mbar. The measurements shown in reference [START_REF] Bertaud | Resistive switching of Ti/HfO 2 -based memory devices: impact of the atmosphere and the oxygen partial pressure[END_REF] on the Pristine state are done after a 1 hour exposure to oxygen rich atmospheres. It is reported that the sample needs a certain time to reach equilibrium. The transfer of the TEM foil between the FIB and TEM is much shorter. It is however important to limit such exposure to the atmosphere as it can temper with the device.

In situ operation of CBRAM devices in the TEM

A new sample preparation is developed for in situ biasing of resistive memories.

Then, electrical characterization is improved by using high precision power supply. Finally, the impact of the environment on the CBRAM device is established. The next step is then to perform in situ biasing of a CBRAM device during TEM observation. A new sample is prepared in the same conditions and transferred immediately inside the TEM to prevent damage linked to oxygen exposure of the TEM foil. The in situ biasing experiment is performed using a FEI Titan Themis with an acceleration voltage of 200 keV. EDS maps were acquired using the super EDS system with 4 large detectors close to the specimen. In situ biasing was performed using the Agilent 4156C analyzer. A HAADF image of the sample is presented in Figure 5.12 along with the electrical layout of the device.

The aim of an in situ biasing experiment in the TEM is to measure subtle changes in element distribution within the HFO 2 layer caused by the resistive switching.

Prior to in situ biasing, an EDS map is obtained on the area above the tungsten via. To limit the impact of the electron beam on the sample, the gun lens is more strongly excited in order to lower the beam current to 100 nA. In order to improve the signal to noise ratio, EDS acquisition was optimized.

During an acquisition, the information is averaged using all active detectors. In Between 0 V and 2 V, the current measured during the FORMING operation on the TEM foil is unstable, and negative values are even measured. It is possible to suggest that insulating materials in the sample are charged due to TEM observation and EDS acquisition Applying a voltage on the sample could then help evacuate those charges. Then, as discussed previously, the wiring between the TEM holder and the sample is simple and prone to leakage currents. In addition, the sample is now located inside the TEM column, and exposed to strong magnetic and electric elds. Measuring extremely low current in such circumstances is dicult, as the metal tracks on the chip as well as the cables inside the TEM holder are not shielded.

Identically to the measurements performed on the thick sample, the signal improves when reaching a current in the order of the nanoamp.

The measured resistance before and after the resistive switching for the dierent experiments are summarized in A major issues is then established as TEM imaging is shown to damage the resistive memory device. Then, it is observed that EDS mapping is insucient to resolve the CF. Finally, it appears that any attempt to increase the resolution or signal to noise ration during EDS acquisition increases the damage done to the device. Electron Energy Loss Spectroscopy (EELS) mapping could provide the resolution necessary to image the CF. Sadly, this technique was not yet available on the TEM at this stage of the PhD due to a major microscope upgrade.

The limits of EDS characterization

Before doing further electrical operation on the device, it is important to identify how the electron beam changed the properties of the CBRAM device. It is then necessary to have an estimation of the size of the CF created during in situ biasing.

The physical dierence between LRS and HRS is dened by the quantum point contact (QPC). When the CF is formed, the QPC is obtained when a singular Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices atom at the apex of the CF connects the bottom electrode [START_REF] Long | Quantum-size eects in hafnium-oxide resistive switching[END_REF]. The quantum conductance corresponding to a contact point made of a singular atom is given by G 0 = 2e 2 /h and is equal to 7.75 * 10 -5 Ω -1 m -1 . This corresponds to a resistance created by a quantum point contact of 12.9 kΩ [START_REF] Su Né | Electrical evidence of atomic-size eects in the conduction lament of rram[END_REF].

Moreover, it has been reported that the formation of the CF in CBRAM can be described as a discrete quantized conductance state [START_REF] Fekadu Gochole Aga | Controllable quantized conductance for multilevel data storage applications using conductive bridge random access memory[END_REF]. The contact area between the CF and the electrode can then be approximate as its conductance is linked to a discrete number of atomic contacts. The resistance measured after the FORMING operation during in situ biasing of the CBRAM device is equal to 1.82 * 10 3 Ω, which corresponds to a conductance of 5.49 * 10 -4 Ω -1 m -1 . By approximating that the CF is exclusively responsible for the current conduction through the sample, this corresponds to a value of 7G 0 . This approximation implies that no electric path but the CF exists in the sample. This consequently means that no surface current or leakage current is present, and that the other resistance in series in the circuit (such as metal tracks, cable, contact pads) can be neglected. This approximation is clearly inaccurate. However, it can provide an insight on the maximum size possible for the CF following in situ resistive switching.

The CF could not be located on the EDS measurements. During EDS acquisition, the information obtained is a projection of the chemical distribution over the entire thickness of the sample. In order to improve current conduction and heat dissipation during in situ biasing, the TEM foil thickness is kept at 250 nm. Identifying a structure of a few atoms in size is therefore problematic in this sample as the local change in composition represents a small volume relatively to the foil thickness. In addition, it is shown in Figure 5.2 that copper is present on each side of the HfO 2 layer. This leads to an overlap of the tail of the copper signal on top of the HfO 2 layer. Consequently, isolating a subtle change in copper distribution from the formation of a CF of a few atoms in size is even more challenging.

Impact of the electron beam on the lament

Another major issue preventing to image the CF during in situ biasing is the increased resistance caused by electron beam scanning. This result suggests that the CF is partially dissolved during the EDS acquisition. It is commonly established that the electron beam exposure during EDS mapping can sometime damage the sample, either by electron induced damage or beam induced heating. As reported in reference [START_REF] Guy | Investigation of forming, set, and data retention of conductive-bridge randomaccess memory for stack optimization[END_REF], exposing a resistive memory in LRS to high temperatures promotes metal diusion and electrochemical reactions leading to a dissolution of the CF. Considering the acquisition times involved during EDS mapping of the sample after in situ resistive switching, an increase in temperature of 100 • C is sucient to dissolve the lament as shown in Figure 2.4. However, calculations show that the temperature increase in inorganic specimen during STEM observation is insignicant, even at high current and small probe size [START_REF] Rf Egerton | Radiation damage in the TEM and SEM[END_REF]. It is therefore unlikely that 5.5. Impact of TEM observation on functioning CBRAM devices 135 the dissolution of the CF occurs solely from beam induced heating.

Dissolution of the CF normally occurs by a combination of temperature and electrochemical reactions [START_REF] Lin | Electrochemical simulation of lament growth and dissolution in conductive-bridging RAM (CBRAM) with cylindrical coordinates[END_REF]. It is well established that radiation damage are generated during electron beam exposure in the TEM. The emission of the high energy photon used for EDS measurement are the result of inelastic interactions between the 200 keV electron beam and the sample. X-ray emissions follow the ionization of an atom. An important amount of energy is transferred to the sample through these interactions, and ionized elements are particularly reactive. In addition, the various emissions of charged particles created by the electron beam can lead to a build up in potential in the sample [START_REF] Mildner | Environmental TEM study of electron beam induced electrochemistry of P r 0.64 Ca 0.36 M nO 3 catalysts for oxygen evolution[END_REF]. Such potential can then directly lead to a modication of the resistive memory by helping element migration.

Preventing beam induced damage during in situ biasing

Results obtained from electrical characterization demonstrate that resistive switching is performed successfully in the TEM foil. Moreover, in situ electrical measurements are in perfect agreement with ex situ characterization results. This suggests that the resistive switching mechanism observed in situ corresponds to normal operation conditions. However, it is not possible to locate the CF through EDS measurements. In addition, it is shown that beam exposure causes damage to the CF.

During an acquisition, it can be possible to limit the damage caused by the electron beam scanning by reducing the beam current or the dwell time. However, it would be necessary to increase the acquisition time to compensate for the loss in signal to noise ratio necessary to image the CF. Beam induced damage would then be generated over time, still leading to a failure in the device.

Another possibility can be considered to successfully image the CF. If a voltage is applied during the acquisition, the CF could be maintained by the current ow.

As discussed in section 1.2.1, the amount of current used during FORMING and SET operation can be directly linked to the size of the lament. Maintaining a high current during the acquisition could help maintaining the lament stable.

Instead of reinforcing the lament, applying voltage to the sample can reduce beam induced damage. It has been shown that the amount of energy transferred to the sample by inelastic interaction can be drastically reduced by applying a negative voltage on the stage [START_REF] Rf Egerton | Radiation damage in the TEM and SEM[END_REF]. As the sample itself is electrically connected during in situ biasing experiment, grounding, or applying a small negative voltage could help reducing radiation damage.

Those methods present a high risk of damaging the equipment. The EDS de- In order to understand the origin of the failure observed during in situ biasing, it is necessary to describe conventional failure mechanisms. The most common mechanism for device failure is caused by the accumulation of defects in the oxide layer after extensive cycling. A schematic of the mechanism is shown in Figure 5.17.

When performing a RESET operation, the lament is not perfectly removed and defects can remain. Mainly, copper atoms are left in the oxide layer thus creating a leakage current. The progressive accumulation of defects leads to an increasing leakage current. Consequently, a progressive decrease of the HRS resistance is observed.

The device failure then occurs either when the window margin becomes too small to determine the device resistance state, or when the defect accumulation bridges the oxide layer, leading to a permanent LRS [START_REF] Lv | A probe of reliability issues of oxide electrolyte based cbram[END_REF].

In the present work, few operations are performed on the sample during in situ 138 Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices from reference [START_REF] Nail | Understanding RRAM endurance, retention and window margin trade-o using experimental results and simulations[END_REF] biasing in the TEM in order to understand its functioning mechanism. This failure mechanism is characteristic of extensive cycling of a device. It is therefore not suited to describe the device failure observed in the present experiment.

The second well established failure mechanism can be dene as a negative SET (n-SET) and is presented in Figure 5.18 [START_REF] Ielmini | Resistive switching memories based on metal oxides: mechanisms, reliability and scaling[END_REF][START_REF] Balatti | Voltage-controlled cycling endurance of HfO x -based resistiveswitching memory[END_REF]. During a RESET operation, a negative voltage is applied to retract the CF. During a negative SET, the CF is retracted, but the sample is then quickly damaged by an increasing current ow.

A negative set can then be describe as a RESET followed by an rapid decrease of the resistance leading to a current above the SET compliance. Negative SET are associated with large CF leading to a strong leakage currents. High leakage current are associated with a high defect density and low conductivity. As there are no current compliance during the RESET operation, this conguration leads to strong Joule heating. This results in the critical injection of defects during reverse biasing dened as a negative-SET.

The goal is then to understand the failure mechanism observed during in situ biasing. First, it is necessary to evaluate the properties of the CF created during the FORMING operation.

The sample is a simple 1R device, meaning that an overshoot necessarily occurred. As described previously, the current surge is particularly high during the FORMING operation. The increased current used during programming then leads to a larger lament. Then, as discussed in reference [START_REF] Guy | Evaluation of the performances of scaled CBRAM devices to optimize technological solutions and integration ows[END_REF], quasi static programming is associated with a slow formation and a larger CF. The present results are in agreement with this observation as a low resistance of 1.82 * 10 3 Ω is measured after the FORMING operation. The formation of a thick CF is usually associated with an increased data retention capability at high temperature [START_REF] Barci | Impact of SET and RESET conditions on CBRAM high temperature data retention[END_REF][START_REF] Fekadu Gochole Aga | Controllable quantized conductance for multilevel data storage applications using conductive bridge random access memory[END_REF]. However, it as also been reported that resistive switching performed at high temperature produces a lament with poor thermal stability [START_REF] Cabout | Eect of SET temperature on data retention performances of HfO 2 -based rram cells[END_REF]. The measured ON resistance remains identical compared to normal programming condition, but the data retention of the LRS is reduced.

During in situ biasing, heat diusion is limited due to the reduced dimensions of the TEM foil. In addition, the size of the device is reduced. This leads to an increased current density in the memory layer during resistive switching. The Joule heating then increases the temperature during in situ operation. It is then possible to consider that in situ FORMING of the CBRAM device can be described as a high temperature programming It is possible to suggest that the CF formed during in situ presents poor thermal stability. In addition, it has been previously shown that radiation damage is generated during the EDS acquisition. Electron beam scanning triggers oxidation reactions and defect diusion which destabilize the CF. This results in a measured ON resistance of 1.62 * 10 4 Ω.

The degradation of the LRS caused by radiation damage can be compared to temperature induced damage in CBRAM devices. High temperatures lead to a changes in morphology of the CF. Secondly, titanium migration is observed. Titanium is know to be active in resistive memories and several devices are based on titanium diusion. The impact of the chemical nature of the electrode for HfO 2 based resistive memories has been previously investigated [START_REF] Cabout | Role of Ti and Pt electrodes on resistance switching variability of HfO 2 -based resistive random access memory[END_REF]. This study shows that using a titanium buer layer instead of inert metal such as platinum can improve the device performances. In the present work, it is interesting to point out that titanium diusion is strictly limited to the CuTe 2 Ge layer and did not extend to the HfO 2 layer. This suggests that the titanium is not a direct component of the CF. It is possible however that titanium diusion in the CuTe 2 Ge layer impacts the copper migration toward the HfO 2 layer.

It has been also demonstrated that using a titanium buer layer between the copper based active layer and the oxide layer improves the uniformity and reliability of CBRAM devices [START_REF] Attarimashalkoubeh | Eects of Ti buer layer on retention and electrical characteristics of Cu-based conductive-bridge random access memory (CBRAM)[END_REF]. This is attributed to the lower standard potential of titanium compared to copper leading to a preferential reduction of the titanium. Titanium oxidation then enables to limit overall copper diusion in the oxide layer. Then, the electrons injected by titanium reduction help on stabilizing the CF.

As shown in Figure 5.2, titanium already naturally diuses with the CuTe 2 Ge layer. Then, a clear migration of titanium in the CuTe 2 Ge layer observed after the failure. This shows that titanium can easily migrate in the CuTe 2 Ge. It is possible to suggest that similarly to the results presented in reference [START_REF] Attarimashalkoubeh | Eects of Ti buer layer on retention and electrical characteristics of Cu-based conductive-bridge random access memory (CBRAM)[END_REF], titanium strongly participate on the CBRAM functioning mechanism. A possible hypothesis would be that the formation of the copper CF is not only promoted by the injection of oxygen vacancies in the oxide layer, but also by titanium diusion is the initial copper based layer.

Conclusion

In this chapter, Condutive Bridge Resistives Memories based on CuTe 2 Ge and HfO 2 have been studied by both ex situ and in situ characterization techniques. First, ex situ characterization is performed to precisely dene the electrical properties of a CBRAM device operated in normal conditions. The same devices are then prepared for in situ observation using the previously presented FIB preparation technique.

The power suppy used for in situ and ex situ electrical characterization are compared. It is shown that the power supply normally used for in situ biasing is not suited for resistive memories operation. It is therefore replaced by high precision tools used for ex situ characterization. This work conrms that in situ TEM is today a powerful tool which can help to understand the underlying functioning mechanisms of semiconductor devices. In addition to atomic scale imaging, TEM provides a vast number of dierent methods that can be used to obtain quantitative physical and chemical information at the sub nanometer scale during live operation of a device. It can be used for a variety of elds such as microelectronics, catalysis, photo-voltaics, batteries, and many others.

This work aims at facilitating in situ TEM characterization through a thorough study of the entire process. The sample preparation method is modied to become nearly straightforward as conventional FIB specimen preparation. Finally, the reliability of the process is improved and the overall preparation time is reduced by a factor of two compared to the previous method. The goals, samples and techniques used for each research projects are dierent. However, we demonstrate that each step can be adapted to answer ones needs thus helping new users to undertake the challenge of in situ TEM characterization.

Micro chips are a versatile tool and we presented through this PhD that extensive modication can be done on micro chips to directly address a targeted issue.

Manufacturing entire wafers of in situ biasing dedicated samples is expensive and time consuming. In the eld of ex situ electrical characterization, a single wafer design is used, and only material compositions are modied between the dierent samples. In this PhD, we showed that customized micro chips can be manufactured to specically address a targeted sample conguration using the capabilities of Focused Ion Beam tools. In situ biasing micro chips have been adapted to be compatible with fully patterned devices used for conventional ex situ characterization. In situ TEM biasing experiments are then not limited to a specic material system. With a single innovative chip design, it is possible to study a wide range of materials without having to modify the preparation method.

Adapting in situ TEM to fully patterned wafers also allows direct observation of a real device during its operation. A direct link can then be made between the ex situ electrical and material science characterization. New information then become available by correlating ex situ electrical measurement to in situ TEM observations. This makes the characterization process more ecient by bringing electrical characterization and TEM imaging closer together. Both TEM imaging and electrical measurements obtained in situ and ex situ can be directly transferred to development and manufacturing teams to speed up technological development.

This work also points out the need for the use of advanced Transmission Electron Microscopy techniques. While it is shown that EDS does not have the sensitivity for in situ characterization of our CBRAM devices, other techniques such as Electron Energy Loss Spectroscopy might overcome the current issues. However, the electron beam will always have an impact on the sample. This impact must be better understood for the user to be able to dierentiate a controlled change applied on the sample from the eect of the electron beam. In addition, improving the sensitivity of the TEM techniques using low electron dose could also greatly help for the diusion of in situ TEM characterization.

Finally, a collaboration can be made in the future between sample manufacturing and characterization. In situ TEM characterization throughput is small compared to ex situ electrical characterization. In order to take advantage of the recent improvements, the future design could dedicate a region of the fully patterned wafer to suit the needs of in situ characterization. This way, in situ TEM characterization could be performed more rapidly to provide valuable information for new devices and materials developments. The value of the sense resistor is chosen so that at when the maximum allowable current ows from the power supply, a voltage equal to the turn on voltage of the current sense transistor is developed across it. When the current sense transistor starts to turn on, the voltage at the base of the main power supply pass transistor is pulled down, thereby preventing any increase in the output current of the power supply" https://tex.stackexchange.com/questions/35977/ how-to-add-a-url-to-a-latex-bibtex-file. (Cited in page 149.)

Figure 1 . 1 :

 11 Figure 1.1: Projected growth of supply and demand in the data storage market by the year 2020 [1]

1. 1 . 5 Figure 1 . 2 :

 1512 Figure 1.2: Evolution of the data storage market size expected by the year 2022[4]

Figure 1 . 3 :Chapter 1 .

 131 Figure 1.3: Scheme of a oating gate eld eect transistor used in ash data storage technologies

Figure 1 . 4 :

 14 Figure 1.4: Schematic diagram of the switching mechanism of Conductive Bridge Resistives Memories.(a) Oxidation of the active metal atoms at the anode (b) migration of the active metal ions through the oxide layer (c) formation of the conductive lament leading to a LRS (d) upon reverse biasing, partial dissolution of the con-

Figure 1 . 5 :

 15 Figure 1.5: (a) Schematic showing the conguration of a PCRAM device. (b) Schematic diagram showing the switching mechanism of Phase Change Resistive Memories adapted from [19]. Graph showing the dierence in (c) voltage versus time, and (d) temperature versus time of the SET and RESET operation of PCRAM devices. Graphs are adapted from Reference[START_REF] Hubert | Optimisation de mémoires PCRAM pour générations sub-40 nm: intégration de matériaux alternatifs et structures innovantes[END_REF]

Figure 2

 2 Figure 2.1: (a) Optical image of a fully patterned wafer connected to the biasing probes during characterization (b) Electrical schematic of a Source/Measurement Unit (SMU)

Figure 2 . 2 :

 22 Figure 2.2: Electrical schematics of (a) one resistor (1R) and (b) one transistor one resistor (1T1R) systems, together with current surge occurring during switching

Figure 2 .

 2 Figure 2.3 shows typical Current-Voltage curve obtained during quasi static operation of a typical resistive memory device. The device is initially in a HRS. Upon forward biasing, a very small current is measured. When reaching the SET voltage, the memory switches toward a LRS and the current reaches the compliance current. The memory then remains in LRS even without biasing. When reverse biasing a memory in a Low Resistance State, a strong current is measured. When the reverse biasing reaches the RESET voltage, the device switches back into a HRS and a low current is measured.

Figure 2 . 3 :

 23 Figure 2.3: Typical I-V curve of bipolar resistive memory switching adapted from

Figure 2 . 20 Chapter 2 .

 2202 Figure 2.4 (a) shows the size of the window margin as a function of endurancefor dierent resistive memory devices reported in the literature[START_REF] Nail | Understanding RRAM endurance, retention and window margin trade-o using experimental results and simulations[END_REF]. As previously discussed, the resistance value of the LRS (and therefore the size of the Window

Figure 2

 2 Figure 2.4: (a) Window Margin (mean value) as the function of the maximum achieved cycle for resistive memories reported in the literature. (b) LRS data retention experimental results and Kinetic Monte Carlo simulation showing the impact

Figure 2 .

 2 Figure 2.4 (b) presents the evolution of the LRS resistance of a device over time when annealed at dierent temperatures. This image shows that exposing a resistive memory device in LRS to temperatures of 100 • C and higher leads to an increase in resistance over time. This occurs because high temperatures promote metal diusion and electrochemical reactions leading to a dissolution of the conductive lament. This gure also shows that higher temperatures will cause a much quicker degradation of the lament. Device failure during cycling usually occurs through closing of the window margin (either by HRS or LRS drift). This type of failure is a good indicator of the technologies real endurance. Resistance drift between LRS and HRS comes from

Figure 2 . 5 :

 25 Figure 2.5: Schematic representation of a Focused Ion Beam

Figure 2 . 6 :

 26 Figure 2.6: Detailed schematic of electron and ion column in a Focus Ion Beam

Figure 2 . 7 :

 27 Figure 2.7: Summary of the dierent mechanism involved in (a) electron-matter interactions and (b)ion-matter interaction.

Figure 2 .

 2 Figure 2.8: Stopping Range of Ion in Matter (SRIM) simulation of gallium ion

Figure 2 . 9 :

 29 Figure 2.9: 1 keV SEM image of an tungsten pad deposited in the FIB using a 30 keV and 0.46 nA gallium beam showing unwanted tungsten deposition around the area of interest.

Figure 2 .

 2 Figure 2.10: 5 keV SEM image of conventional FIB sample preparation. (a) deposition of a tungsten protection layer (b) FIB milling on each side of the protection layer (c) undercut leaving a freestanding chunk (d) liftout using the micromanipulator (e) transfer onto a TEM copper grid and (f ) chunk soldered to the TEM copper grid prior to FIB thinning

Figure 2 .

 2 Figure 2.10 shows SEM images of FIB sample preparation for TEM observation. Conventionally, a few hundred nanometer thick metal layer is deposited via EBID to protect the top surface of the sample. Then, IBID is performed to deposit a few microns of metal. Ion implantation and ion induced damage are consequently limited to the rst deposit, thus preserving the sample surface. The second deposit will then protect more eciently the sample along preparation. It also allows to avoid curtaining eects during the sample thinning. Trenches are then etched on each side of the deposit. The bottom part of the sample is then removed to leave a standing wall only attached by one side. As shown on Figure 2.10(c), the chunk is attached to the omniprobe via ion beam deposition before being separated form

Figure 2 .

 2 Figure 2.11: (a) Schematic of a Transmission Electron Microscope column. Schematic was adapted from [54]. (b) Photograph of a TEM.

Figure 2 .

 2 Figure 2.13 shows the energy diagram describing the formation of characteristic

Figure 2 .

 2 Figure 2.12: (a) schematic of a TEM column in STEM mode and (b) schematic of the dierent STEM detectors with various ranges of collection angles : Bright Field detector θ 1 = 10 mrad ; Dark Field detector θ 2 = 15 -50 mrad and High Angle Annular Dark Field detector θ 3 = 50 -200 mrad. Schematic adapted from [55].

Figure 2 . 13 :

 213 Figure 2.13: Representation of the mechanism involved in the formation of characteristic X-ray following inelastic interaction with high energy electron.(a) The incident electron excites an inner shell electron on the target atom creating an electron hole (b) An outer shell electrons relaxes to ll the hole by emitting an X-ray characteristic of this energy transition

2. 4 . 5

 45 Dierential Phase Contrast Dierential Phase Contrast (DPC) is a TEM technique that can image electric elds in a sample. This method requires the use of a segmented detector. As shown in Figure 2.14, scanning the electron beam over an electric eld results in Coulomb deection of the beam. This produces a change in the intensity distribution over the dierent segments of the detectors. Initially, the intensity measured on each segment of the detector is normalized. DPC images are obtained by comparing the measured intensity on the dierent parts of a segmented detector when the beam is deected.

Figure 2 . 14 :

 214 Figure 2.14: Schematic showing the principle of a Dierential Phase Contrast measurement on a simple pn junction. (a) When no electric eld is present, each segments on the detector is evenly illuminated. (b) When scanning the beam over an electric eld, the beam is deected leading to a change in the intensity distribution on the segmented detector.

2 . 5

 25 In situ TEM Since the aberration correction revolution during the 2000-2010 decade, TEM performances kept improving to become what is today one of the most ecient imaging and characterization tool both for research and industrial purposes. Atomic

Figure 2 . 15 :

 215 Figure 2.15: Schematic of the furnace type in situ heating TEM holder from Gatan.

Figure 2 . 16 :

 216 Figure 2.16: Schematic representation of the probe based in situ biasing TEM sample holder from Nanofactory. Such holder is compatible with copper grid thus allowing to use conventional sample preparation technique.

Figure 2 .

 2 Figure 2.17: (a) rendered schematic of the chip based in-situ Fusion holder from protochips. (b) schematic of the MEMS chip supporting TEM samples.

Figure 2 .

 2 Figure 2.18, taken from reference[START_REF] Chen | Dynamic Evolution of Conducting Nanolament in Resistive Switching Memories[END_REF] supplementary information, shows the result of such sample preparation for an in situ biasing experiment. Even though the article suggests that this method can provide a device in working conditions, the image clearly show a halo eect around deposited metal covering a wide area including the area of interest. As the entire area is covered in conductive material, it is fair to assume a non negligible fraction of the input current will ow around

Figure 2 .

 2 Figure 2.18: (a) SEM image of a TEM foil solder to an omniporbe and laying at on the chip membrane (c) SEM image of a TEM foil electrically connected to the metal lines on the chip from reference[START_REF] Chen | Dynamic Evolution of Conducting Nanolament in Resistive Switching Memories[END_REF]

Figure 3 . 1 :

 31 Figure 3.1: (a) Schematic showing a TEM foil laying at on the membrane of the chip. Due to its position, the contamination on the foil surface cannot be cleaned using the FIB. (b) Schematic of a thin foil in a position which allows both FIB cleaning and TEM observation.

Figure 3 . 2 : 15 •

 3215 Figure 3.2: Top view of the rotation needle used for rotation of chunks and foils of material in the FIB. It consist of a used FIB micromanipulator mounted on a FIB stub. It can perform a 180 • rotation with 45 • step by using reference positions as shown the in the image insert.

Figure 3 . 3 :

 33 Figure 3.3: 5 keV SEM image of the FIB sample preparation. (a) conventional lift out with a stage tilt of 52 • (b) transfer on the rotation needle with a stage tilt of 37 • (c) lift out of the chunk from the rotation needle after ex situ rotation with a stage tilt of 52 • (d) resulting rotated chunk with an angle of 15 • relative to a at surface on the stage. (e) schematic representation of the front view (top) and side view (bottom) of the sample manipulation

Figure 3 . 4 : 50 Chapter 3 .

 34503 Figure 3.4: 5 keV SEM image of (a) the heating membrane before additional hole etching, (b) transfer of the 15 • tilted chunk on the newly etched hole in the heating membrane, (c) soldered chunk following extensive IBID tungsten deposition and (d) STEM HAADF image of the nal TEM foil with a 15• alpha rotation tilt.

3. 5 .

 5

Figure 3 .

 3 5(a) shows good temperature homogeneity over the viewing area and in the center hole where the sample would be located.

Figure 3 .

 3 5(b) shows the temperature gradient existing in the heating membrane. This gure shows that at a set temperature of 1000• C, the edge of the viewing area is at 987 • C. Finally, these measurements have shown that the heating and cooling rate achievable in this system is 10 6 • C/s[START_REF] Lawrence F Allard | A new mems-based system for ultra-high-resolution imaging at elevated temperatures[END_REF].

Figure 3 . 5 :

 35 Figure 3.5: (a) Temperature gradient existing over the entire membrane at a set temperature of 1000 • C (b) Infrared mapping of the temperature of the viewing area of the heating membrane at a temperature of approximately 825 • C.

  Figures 3.6

52 Chapter 3 .

 523 (a),(b) and (c) show the resulting geometrical cutting of the model of both intact and modied membrane.In order to be able to calculate the heat transfer it is necessary to mesh the model. The mesh enables to divide the current model into smaller domains over TEM in situ annealing of Phase Change Memories which equations are solved. Meshing is then a critical step, as it is a trade o between calculation speed and accuracy. The simplied geometry used in this model then allows more ecient meshing and therefore a drastic reduction of the calculation time.

  Figure 3.6(b),(c) and (d) present the meshing of both intact and modied membrane model. First, the silicon frame is divided using a large squared meshing as shown in Figure 3.6d. Then, the membrane is divided using a ne triangular mesh, with an increased precision over the viewing area as shown in Figure 3.6(e) and (f ) The additional disc for the modied membrane model is meshed with a ne triangular shape.

Figure 3 .

 3 Figure 3.6: (a) Geometry used for (b) the intact membrane and (c) the modied membrane. (d) Meshing for (e) intact membrane and (f ) the modied membrane

Figure 3 .

 3 7 presents the material distribution in the modeled heating chip. The frame is composed of silicon. The heating membrane is divided into a 120 nm thick silicon nitride layer on top of a 30 nm thick silicon carbide layer. Gold layers are added on each side of the silicon carbide layer to provide electrical connections. The simple geometry used then requires the gold layer to be 30 nm thick. Gold has a high conductivity, and small currents are used during this simulation. Even though real thicknesses should be 100 nm, using a thinner gold layer has little impact on the nal results. Silicon carbide and gold layers are covered by the same 120 nm silicon nitride layer as the membrane. For the modied membrane model, the additional 100 nm thick disc in the center of the viewing area is composed of tungsten to mimic the halo eect from FIB deposition.The physical properties of the elements used in the model were obtained from

Figure 3 . 7 :

 37 Figure 3.7: Material distribution in the model showing (a) Silicon(b) Silicon Carbide (c) Gold, (e) Silicon Nitride and (f ) Tungsten. Physical boundaries of the model are represented in red showing in (a) the 20 • C xed temperature on the frame edge and in (c) the electrical contact on the gold tracks

Figure 3 .

 3 Figure 3.8 shows the conductivity obtained depending on the temperature. To facilitate the calculation, interpolation of the function describing the conductivity of the SiC depending on the temperature is set to the nearest value. The value of the tungsten conductivity is also replaced in the model by values obtained from 4 point probe measurements on FIB deposited tungsten presented in Section 4.2.2. The physical boundaries are then set to dene the starting conditions of the model. Figure 3.10 shows the dierent boundaries applied. The entire model is set with a starting temperature of 20 • C. Each side of the silicon frame is set to have

Figure 3 . 9 .

 39 Figure 3.9. The temperature obtained in the intact membrane model for dierent currents are very close to experimental temperature obtained during infrared calibration. As shown in Figure 3.9 the temperature output of the modied membrane model is almost identical to the one of the intact membrane model.

Figure 3 .

 3 Figure 3.10 presents the temperature gradient existing over the viewing area of the heating chip of both intact and modied membrane at dierent temperatures.

Figure 3 . 3 •

 33 Figure 3.10c show the temperature gradient at a temperature of approximately 800 • C. Over the viewing area, a temperature gradient of 6 • C is visible (from 796 • C to 802 • C). For a temperature of approximately 825 • C, experimental infrared map from the manufacturer presented in Figure 3.5b shows a temperature gradient of 3 • C (from 822 • C to 825 • C).

Figure 3 . 9 :

 39 Figure 3.9: Current-temperature response of the heating chip from calibration le compared to the max temperature obtained in the intact and modied membrane models

3. 2 . 57 Figure 3 .

 2573 Figure 3.10: COMSOL modeling of the impact of a tungsten short circuit around the sample area

Figure 3 . 11 :

 311 Figure 3.11: Schematic of the (a) ferroelectric tetragonal cubic and (b) paraelectric cubic lattive of BaTiO 3 adapted from reference[77]

  Figure 3.12 shows an HAADF STEM image of the BaTiO 3 foil. In situ heating is performed using a Keithley 2636B power supply controlled by the Clarity software from Protochips. In order to observe the paraelectric transition, the temperature is increased progressively with 10 • C steps. The temperature ramp used for each step is 10 • C/s. Images are acquired every 10 • C steps. The ferroelectric to paraelectric transition is observed at a set temperature of 180 • C.

Figure 3 .

 3 Figure 3.12: STEM HAADF image of the BaTiO 3 foil at 25 • C. The specimen is prepared using the method presented in Section 3.1

•

  C and a target temperature. The target temperature are set every 5 • C between 100 • C and 200 • C. The paraelectric transition is observed at a set temperature of 185 • C. Then, the temperature step size is decreased to 1 • C to

Figure 3 .

 3 Figure 3.13: STEM HAADF images of the BaTiO 3 sample at (a) 170 • C showing two domain walls labeled (1) and (2). (b) STEM HAADF imaged obtained at 180 • C

Figure 3 .

 3 Figure 3.14: Temperature-particle size phase diagram for BaTiO3 particle created by reference [80]. The phase diagrams clearly show various behaviors (e.g., Tc, the uppermost phase boundary) of BaTiO 3 at various size scale compared to bulk BaTiO 3 phase diagram. Phases are labeled as : the paraelectric phase (C) cubic and ferroelectric phases (T) tetragonal (O) orthorhombic (R) rhombohedral. The phase change temperature for to a 200 nm particle is shown in light green.

  a temperature ramp of 5 • C/min to limit sample drift and maintain a sucient image quality to observe the rst steps of crystallization. Live recording of crystallization events was obtained by acquiring a series of 100 1024 2 pixel STEM images (4 s scan time per image). Bright Field, (BF) Dark Field (DF) and High Angle Annular Dark Field (HAADF) STEM detectors were used simultaneously. For Energy Dispersive 64 Chapter 3. TEM in situ annealing of Phase Change Memoriesx-ray Spectroscopy (EDS) analysis, we used the Super EDS system with 4 large detectors close to the specimen. Analysis was performed using Cli-Lorimer factors (at 200 kV available in the Esprit 1.9 Bruker software) for the oxygen K, germanium K and tellurium L peaks. Other elements appearing in the EDS spectra (Mo, Al, Cu) have been used for the peak deconvolution based on Gaussian functions.

Figure 3 .

 3 Figure 3.15: (a) Temperature-resolved resistance and (b) temperature-resolved reectivity of GeTe lms left uncapped and capped in situ by a 10 nm thick SiN protective layer. Measurements were performed at a 10 • C/min heating ramp. The reectivity curves are normalized by setting the minimum value of the reectivity to 0 and its maximum to 1. The crystallization temperatures, dened as the maximum of the curve derivative, are ≈ 183 • C for the uncapped sample and ≈234 • C for the capped sample. The uncapped sample shows two successive resistance drops, labeled A and B, suggesting two dierent crystallization events.

  The membrane temperature is calibrated by the manufacturer by infrared measurements. Then the modeling results presented in Section 3.2 suggest that the modication performed on the membrane have little impact for temperature below 300 • C. Then, calibration experiment have shown that the BaTiO 3 thin foil and the membrane are at thermal equilibrium even for temperature ramps of 10 6 • C/s. As shown in Table3.1, the thermal conductivity of BaTiO 3 and GeTe are similar over the range of temperature covered by this experiment. In addition, the uncapped GeTe crystallization temperature (180 • C) and BaTiO 3 curie temperature (130 • C) are close.

Figure 3 .

 3 Figure 3.16 shows STEM Energy Dispersive x-ray Spectroscopy (EDS) maps that were obtained from a 250 nm thick STEM foil for both capped (a and b) and uncapped (d and e) as-deposited amorphous GeTe. The composition line scans shown in Figure 3.16(c) and (f ) were obtained by integrating the information in the EDS maps across a 30 nm wide area. Deconvolution was done using conventional Cli-Lorimer method using K rays. The STEM EDS map obtained on the GeTe layer protected by the 10 nm SiN layer shows no sign of composition change and a homogeneous distribution of germanium and telluride is observed throughout the sample. The Ge/Te weight ratio obtained from EDS analysis is about 39/61. This corresponds to an atomic ratio of 53/47 to be compared to 52.4/47.6 obtained from Rutherford Backscattering. This map also suggests that the interface between GeTe and SiN is sharp with no detectable interdiusion. However, for the uncapped GeTe sample, a germanium oxide layer is formed at approximately 10 nm above the initial GeTe layer surface. Composition changes induced by oxidation are detected in the upper 15 nanometers of the GeTe lm. Similar conclusions were reached from Electron Energy Loss Spectroscopy (EELS) maps for a GeTe lm capped with a Ta 2 O 5

Figure 3 . 16 :

 316 Figure 3.16: Energy Dispersive X-ray Spectroscopy composition maps on SiN capped (a, b) and uncapped (d, e) GeTe samples. Composition line scans have been extracted along the white arrow from top to bottom over a 30 nm wide area and are shown in (c) for the SiN capped GeTe sample and (f ) for the uncapped sample. The interface between SiN and GeTe is abrupt (c) while clear changes in composition on the top surface of the uncapped GeTe sample are evidenced in (f ).

Figure 3 .

 3 Figure 3.17: HAADF STEM snapshots of the crystallization of the SiN capped GeTe lm recorded at a set temperature equal to 270 • C reached after heating at 5 • C/min. Time was set to 0 at the rst sign of the phase change and the time is displayed in the format (minutes : seconds)s. The crystallization does not start from the interface. The right part of the STEM foil crystallizes rst. The reason is that the tungsten soldering connecting the STEM to the heating membrane is located on the right of the eld of view.

Figure 3 .• C (heating rate of 5 • 5 • 20 • 70 Chapter 3 .

 35520703 Figure 3.18: (a) Room temperature bright eld STEM images of the SiN capped GeTe lm after rapid cooling immediately after the crystallization onset occurring at a set temperature of 270 • C in the in situ STEM experiment. (b) High resolution image of an individual crystal and (c) the associated Fourier Transform.

Figure 3 .

 3 Figure 3.19: (a, b, c) HAADF STEM snapshots of the crystallization of the uncapped GeTe lm recorded at a set temperature equal to 220 • C reached after heat- ing at 5 • C/min. Time was set to 0 at the rst sign of phase transformation, and the time is displayed in the format (minutes : seconds). After surface crystallization, set temperature was increased to 240 • C at a 5 • C/min ramp. (d) Image were acquired after waiting 7 minutes at 24 • C. The insert in image (d) is a diraction pattern acquired in the region pointed by the black arrow showing that this region is crystalline.

  the present in situ STEM studies. Crystallization speeds were obtained by measuring the growth of the crystalline phase over time at a xed temperature. At a temperature ≈184 • C (set temperature equal to 220 • C), after heterogeneous crystallization at the oxidized surface, the lateral crystallization speed was estimated to be 4.4 ± 0.1 nm.s -1 . The in depth growth velocity could be estimated at ≈ 204 • C (set temperature equal to 240 • C) and found to be less than 0.1 nm.s -1 . Pre- vious studies of the lateral growth velocity in GeTe by either in plane transmission electron microscope views or optical microscopy lead to extremely widely dispersed values[START_REF] Santala | Irreversible reactions studied with nanosecond transmission electron microscopy movies: Laser crystallization of phase change materials[END_REF]. At 180• C, extrapolated values from the literature extend from 1 nm.s -1 to 1 µm.s -1 . These results suggest that sample oxidation could contribute to such discrepancies. All previous studies were performed on uncapped, and hence oxidized, samples. Nevertheless, the degree of oxidation is unknown in these studies and is probably dierent from one study to the other since it depends on the duration of the exposure to air after fabrication. Such a variability certainly contributes to the dispersion of measured lateral velocities. No information was available in literature on the perpendicular growth velocity. When heating an oxidized GeTe lm above 184• C, the crystallization of the entire lm is obtained through the growth of the crystallized part in the direction perpendicular to the lm plane. The STEM images explain the two-step decrease of the resistivity (Figure3.15) measured in an oxidized GeTe lm at a heating rate of 10 • C/min. Note that the occurrence of a two-step crystallization, with crystallization starting at the upper lm surface, had been previously proposed from optical transmission, reectivity and in plane transmission electron microscope views in a lm with a similar composition (Ge 54 Te 46 )[106] but Chapter 3. TEM in situ annealing of Phase Change Memories in this work the role of oxidation remained unnoticed and no cross section STEM images were provided.It is instructive to compare the behavior of GeTe to that of Ge 2 Sb 2 Te 5 (GST)[START_REF] Noé | Impact of interfaces on scenario of crystallization of phase change materials[END_REF]. In both phase-change materials, crystallization in non-oxidized lms results from nucleation in the lm volume followed by crystal growth, which leads to a one step change in resistivity. In oxidized GST, like in oxidized GeTe, a two-step crystallization is observed in 100 nm thick lms, the rst step (at ≈150 • C) being the formation of an upper crystallized layer above an amorphous layer. In the case of GST, the second step consists in nucleation and crystal growth inside the volume of the remaining amorphous phase. It occurs at 170 • C, i.e. at the same temperature as the crystallization of a non-oxidized GST lm. In GeTe, when the heating rate is of the order of 5 • C/min, the second step is due to growth of the initially crys- tallized upper layer in the direction perpendicular to the lm plane. This occurs at a temperature close to 204 • C (set temperature equal to 240 • C), lower than the crystallization temperature of the capped lm. These observations are consistent

  STEM investigations have shown how oxidation deeply aects the crystallization process of GeTe phase-change materials. These results must be considered in the development of PCRAM since the current trend is to introduce phase-change materials into more conned structures aiming at improving thermal connement of the active material in order to reduce the programming current. In conned mem-3.4. Conclusion 73 ory cells, the active phase-change material is located between thermal and electrical insulator materials and metallic contacts. First, the thickness of the zone aected by oxidation could be not negligible with respect to the active volume. Secondly, data retention in the amorphous state is reduced by the presence of oxide since oxidation promotes crystallization. When oxidation is prevented, the crystallization temperature increases by 50 • C for GeTe (230 • C instead of 180 • C) and 20 • C for GST (170 • C instead of 150 • C) leading to a substantial improvement of their performance for phase change memories applications.

15 •

 15 this chapter, a new sample preparation dedicated to TEM in situ heating experiment is presented using MEMS-based heating holder. The reduced size of the heater on the MEMS chip leads to a much lower thermal drift compared to furnace type holder. This then allow direct observation at the atomic scale of one time event such as PCM crystallization. Using the Focused Ion Beam, it is possible to extract a sample from a region of interest with high specicity. Using the micro manipulation tools available in the FIB, the thick chunk of material is positioned on the suspended heating membrane of the heating chip at an angle of relative to the membrane surface. This helps preventing beam induced damage by enabling the thinning of the sample as a last step of the sample preparation. However, this method requires to locally modify the heating membrane. A COMSOL model is presented in order to asses the impact of such modications on the heating membrane. Then, a calibration experiment is performed using a reference sample. Results suggest that the modications performed on the membrane have little impact on the chip heating properties. Finally, live observation of the crystallization of GeTe phase change material is observed during in situ annealing in the TEM. The results demonstrate the impact of surface oxidation on the crystallization temperature and mechanism of this material. This provided valuable information which can help the current development of PCRAM devices. Chapter 4. Development of quantitative TEM in situ biasing techniques 4.1 Introduction

Cli-

  Lorimer factors (at 200 kV available in the Esprit 2.0 Bruker software) for the gallium K, oxygen K, carbon K and gallium L peaks. Other elements appearing in the EDX spectra (Zr, Mg, Al, Cu) have been used for the peak deconvolution based on Gaussian functions.Figure 4.1 shows the relative composition variation of the FIB deposited tungsten depending on the deposition condition. EDS measurements presented in Figure 4.1 are obtained on the dierent tungsten protection layers used during conventional FIB sample preparation of an aluminum sample. The electron Beam Induced Deposition was performed at 2 keV and 13 nA to cover a 12 x 3 µm area during ve minute exposition. This deposition was performed as a rst surface protection prior to ion beam induced deposition. The second protection layer was obtained by ion beam induced deposition using a 16 keV gallium beam with a current of 0.46 nA on a 10 x 3 µm area with a targeted thickness of 4 µm.

Figure 4 . 1 : 4 . 2 . 2 . 1

 414221 Figure 4.1: Relative composition of electron beam and ion beam deposited tungsten obtained by EDS measurements

Figure 4 . 2 :

 42 Figure 4.2: Schematic showing the 4 point probe measurement principle using chip based in situ TEM holders.

Figure 4 . 3 :

 43 Figure 4.3: (a) 5 keV SEM image showing a tungsten pad deposited with a 16 keV gallium ion beam. The four parallel metal tracks on the chip are labeled 1 to 4 are used to measure the conductivity of the deposited tungsten. (b) Four points probe conductivity measurement of material deposited in the FIB using electron beam and ion beam at dierent incident energy. The dotted blue line corresponds to the conductivity of metallic tungsten

Chapter 4 .

 4 Development of quantitative TEM in situ biasing techniques 4.3

Figure 4 . 4 :

 44 Figure 4.4: Stacking and composition of an in situ biasing dedicated Conductive Bridge Resistive Memory device

Figure 4 . 5 :

 45 Figure 4.5: (a) Top view image of a fully patterned CBRAM device obtained with a 30 keV Xenon ion beam (b) HAADF STEM cross section image of the fully patterned CBRAM image. Structured are labeled as follow : (1) left metal line (2) right metal line (3) aluminum bridge and (4) location of the CuTe 2 Ge resistive memory layer.

Figure 4 .Figure 4 . 7 :

 447 Figure 4.6: Schematic (a) top view and (b) side view of the new chip design.

Figure 4 .

 4 Figure 4.8: 5 keV SEM image of the gold line obtained on the customized chips design (c). Metal lines are discontinuous due to delamination during the lithography process.

Figure 4 . 9 :

 49 Figure 4.9: 5 keV SEM image of the second generation of customized chips. (a) overview of the top side of the chip with (b) close up view of the chemically etched trench on the edge of the chip.(c) Back view of the chemically etched trench.

Figure

4 . 91 Figure 4 .

 4914 Figure 4.10: 5 keV SEM image of the FIB sample preparation. (a) lift out of the chunk (b) transfer of the chunk on top of the chip trench (c) detachment of the Omniprobe and (d) close up view of the VIA observed during FIB thinning.

Figure 4 .

 4 Figure 4.11: HAADF STEM image of the in situ biasing dedicated CBRAM sample (a) after cutting the top electrode and (b) after cutting the bottom electrode. (c) schematic of the nal electrical layout of the CBRAM sample during in situ biasing experiment.

4. 4 .

 4 Implementing new chip designs for FIB sample preparation 93 the mechanical stability of the TEM foil. It also facilitates the heat transfer from Joule eect during biasing. Finally, this allows to increases the signal during EDS acquisitions. However, thinner sample would be required for EELS or high resolution imaging. Ion beam exposure on the sample after removing the short circuit is then limited. This reduces the risk of ESD in the sample. The layout of the nal TEM foil is presented in Figure 4.11(c). The top electrode is only connected to the left side of the chip. The bottom electrode is only connected to the right part of the chip. The sample is therefore properly connected and no short circuits remain.

Figure 4 .

 4 Figure 4.12: 5 keV SEM image of the FIB sample preparation. (a) surface of the fully patterned wafer after depositing the SiO 2 protection layer in the pFIB. (b) lift out of the chunk (c) transfer of the chunk on top of the chip trench (c) chunk soldered to the chip after tungsten deposition.

Figure 4

 4 Figure 4.13: (a) HAADF STEM image of the fully patterned CBRAM sample connected to the chip. (b) schematic of the nal electrical layout of the CBRAM sample during the in situ biasing experiment.

Figure 4 . 96 Chapter 4 .

 4964 Figure 4.14: STEM HAADF image of the memory layer of a fully patterned CBRAM device prepared using the Focused Ion Beam. The red arrow shows the result of an electrostatic discharge occurring during sample preparation.

Figure 4 . 15 :

 415 Figure 4.15: Summary showing the dierent sample preparation discussed in this work. (1) Initially proposed method. Other methods are described in (2) Section 3.1 (3) Section 4.4.1 (4) Section 4.4.2.

Figure 4 .

 4 Figure 4.16: (a) HAADF STEM image of the pn junction sample connected to the biasing chip. The sample presents ve regions of dierent thicknesses labeled 1 to 5. (b) Close up view of the region used for DPC measurements showing three sections, of 3 µm in width, with thicknesses of 408 nm, 265 nm and 180 nm.

Chapter 4 .

 4 Development of quantitative TEM in situ biasing techniquesAs previously presented, two consecutive cuts are performed using the 5 keV ion beam. This allows to connect the top electrode on the left part of the chip, and the bottom electrode on the right part of the chip shown in Figure4.16(c). Finally, the sample is thinned down to produce three sections with dierent thicknesses. The thickness of each section is measured using Convergent Beam Electron Diraction (CBED). Results show that the dierent sections are respectively 408 nm, 265 nm and 180 nm thick as shown in Figure4.16(b).

  (b), a current of 17.5 µA is measured at -10 V during reverse biasing of the pn junction. This represents about 15% of the current obtained during forward biasing at 10 V. This leakage current is most likely caused by surface currents on the damaged surfaces of the TEM foil as shown in Annex in Figure 5.29, as well as amorphous silicon and gallium implanted regions created by the FIB preparation.

Figure 4 . 100 Chapter 4 .

 41004 Figure 4.17: (a) Typical current-voltage response of a pn junction. Electrical breakdown is dened by a rapid increase of current under reverse biasing. Avalanche breakdown occurs at high reverse bias (typically above 5 V) and concerns low doped materials (below 10 18 cm -3 ). Zener breakdown occurs at lower reverse voltages (typically below 5 V ) and concerns highly doped materials (above 10 18 cm -3 ) [113] (b) Current-voltage response of the TEM foil containing the pn junction.

Figure 4 .

 4 16(b). The measured signal increases with the sample thickness. The section 4 shown in Figure 4.16 is consequently chosen for the data analysis as it has the best compromise between the reduction in dynamical diraction contrast, and the measurable signal. Measurements are performed with an acquisition time of 100 s. The DPC measurement principle as well as the 4 raw images obtained by each detectors are shown in Figure 4.19. This gure shows the raw images obtained on the 4 detectors when performing the DPC measurement on the pn junction at equilibrium (i.e. unbiased). It is already possible to observe contrast caused by the beam deection when scanning the pn junction. When scanning area (a), the beam is centered and all four segments of the detector are evenly illuminated. As the beam is scanned over the pn junction in the area (b), the electric eld deects the beam. The area (b) is brighter on segments B and C and darker on segments A and D. The beam is deected from the center position in the direction of detectors B and C as represented in Figure 4.19. When scanning the area (c), the electric eld is no longer present and the beam goes back in the centered position. DPC is an indirect measurement of the eld. The information obtained is just a measured intensity change at this point. Calibrations are therefore necessary to link the intensity change on the detectors to the beam deection. The beam deection is then used to calculate the electric eld value. This remains however a projection of the electric eld inuencing the beam when going through the sample.

102 Chapter 4 .Figure 4 . 19 :

 1024419 Figure 4.19: Working principle of the DPC measurement on a pn junction sample. The beam is centered on the 4 detectors in (a). Then, the electric eld present at the junction in (b) deects the beam. Finally, in the absence of an electric eld, the beam goes back in a centered position in (c). The image provided by detectors A,B,C and D are presented. Due to the beam deection, the junction in area (b) appears brighter on detectors B and C, and darker on detector A and B compared to p-doped and n-doped silicon part of the sample.

4. 5 . 103 Figure 4 . 20 :

 5103420 Figure 4.20: Image showing the dierence between the image of the electron beam before and after the manually induced shift.

(4.7) 104 Chapter 4 .

 1044 Development of quantitative TEM in situ biasing techniquesSecondly, the change in intensity caused by the induced shift is retrieved. The intensity of each segment is normalized by dividing each image by the sum of the 4 segments images. For each diagonal segment (i.e. AC and BD), the intensity dierence of the segments images obtained at the initial beam position I 0 is subtracted to the intensity value on the segments images obtained after the induced shift I s . The relative intensity change in each pixel caused by the induced beam shift is therefore calculated according to :

  measurement is performed on the pn junction at equilibrium. The images showing the electric eld measured in x and y directions after performing the calibration are shown in Figure 4.21.

4. 5 . 105 Figure 4 .

 51054 Figure 4.21: (a) overview of the section 4 of the TEM foil. The doted white rectangle shows the region of interest. (b) Electric eld z component (c) electric eld x component obtained after calibration of the DPC measurements

  [START_REF] Guy | Investigation of forming, set, and data retention of conductive-bridge randomaccess memory for stack optimization[END_REF] With Dopant concentration N D = N A = 10 19 cm -3 , Silicon intrinsic carrier concentration n i = 9.65 * 10 9 cm -3 Free space permittivity ε 0 = 8.85 * 10 -12 F cm -1 Silicon dielectric constant ε Si = 11.9.

Chapter 4 .

 4 Development of quantitative TEM in situ biasing techniquesFor a symmetrical silicon pn junction doped at 1 * 10 19 cm -3 , the calculated electric eld at the junction is 1.26 MV/cm. The present results then show a difference of about 36 % compared to the theoretical value. In order to fully test the biasing geometry of the sample, DPC measurements are performed for dierent applied voltages. 4.5.4 Quantitative eld measurements during in situ biasing of a pn junction DPC measurements are performed on the same area during reverse biasing of the pn junction between -10 V and 10 V. The calibration method previously presented is applied on each measurement. First, results obtained with an applied voltage of 0 V and -3 V are compared to simulated values obtained using reference [116]. The electric eld proles are retrieved across the pn junction by averaging over a width of 2.5 µm and results are shown in Figure 4.22.

Figure 4 .

 4 Figure 4.22: (a) Prole of the measured electric led in the z direction obtained on the pn junction during in situ reverse biasing a 0 V and -3 V. Results are compared to the electric eld prole obtained from simulation.

108 Chapter 4 .

 1084 Figure 4.23: (a) SIMS prole performed on the same sample showing the dopant concentration around the junction. The SIMS prole is obtained from Reference [117]. (b) Schematic representing the active dopant distribution, amorphous sidewall and electrically inactive regions.

Figure 4 . 24 :

 424 Figure 4.24: Maximum electric eld value measured on the pn junction during in situ biasing compared to simulation results. The built-in voltage and the associated electric eld at equilibrium are shown.

110 Chapter 4 .

 1104 , two mechanisms exist for pn junction breakdown. Zener breakdown is usually associated with heavily doped material and occurs at low voltage. Zener breakdown is caused by tunneling current and is made possible because of the reduced size of the depletion region. Avalanche breakdown on the opposite concerns lightly doped materials and occurs at high voltage. Avalanche breakdown is caused by collision between the charge carriers and atoms. The prob-Development of quantitative TEM in situ biasing techniques ability of avalanche breakdown therefore increases with the leakage current, as well as the temperature [112]. Due to their dierent functioning mechanisms, the change in current-voltage characteristics is very sharp during Zener breakdown, and more gradual during Avalanche breakdown.

Figure 5 .

 5 1(b). The resulting weight percentage distribution is presented in Figure 5.2.

Figure 5 .

 5 Figure 5.2(a) clearly shows that the CuTe 2 Ge layer is not homogeneous in the

Figure 5 . 1 :

 51 Figure 5.1: (a) Energy Dispersive X-ray Spectroscopy map of the in situ biasing dedicated CBRAM sample. The sample presents a 2D structure where the top electrode, the memory layer, and the bottom electrode are deposited over the entire wafer. To separate both electrodes, a silicon nitride layer is used. Finally, tungsten via are used to provide localized electrical connections. (b) a close up map of the memory layer showing the heterogeneity of the CuTe 2 Ge where the upper part of the layer is rich in tellurium and has a low content of germanium and copper.

Figure 5 . 2

 52 Figure 5.2(b) shows the distribution of the other elements surrounding the CuTe 2 Ge layer. The hafnium and oxygen signals are properly conned to the HfO 2 layer. It appears however that traces of titanium diused into the CuTe 2 Ge layer.

Figure 5 . 2 :

 52 Figure 5.2: EDS linescan obtained on the resistive memory layer showing weight percentage distribution of (a) Cu, Te and Ge and (b) Hf,W,Ti,N,O. Linescan is obtained over a 20 nm wide area in the middle of the tungsten via from top to bottom. Zero position is set on the top surface of the memory layer.

  Figure 5.3: I(V) proles of one resistor (1R) and one transistor / one resistor (1T1R) devices. Operations were performed in the following order : 1-FORMING (red) ; 2-RESET (blue) ; 3-SET (green) ; 4-RESET (orange).

shown in Figure 5 . 3 ,Figure 5 . 3 ,

 5353 Figure 5.3, an overshoot current of 200 µA can be estimated. It has been reported

Figure 5 .

 5 Figure 5.4 presents the evolution of ON and OFF resistance values during cycling of a 1R CBRAM device. After the FORMING operation and during the following few cycles, the resistance window is particularly wide. Two reasons can explain this window margin. First, a strong overshoot occurs following the FORMING operation. The current surge then creates a wider lament leading to particularly low ON resistance compared to a normal SET operation. Secondly, the very low defect density present in the rst cycles also participates in a HRS with a particularly high resistance, but this only concerns about 5 cycles after the rst activation.

Figure 5 . 4 :

 54 Figure 5.4: Evolution of the resistance values (R ON and R OF F ) measured on a 1R device during 100 cycles. This result shows a window margin of about one order of magnitude between LRS and HRS. Both R ON and R OF F also present an important variability.

  Clarity software from Protochips with the Keithley 2636B power supply connected to the TEM holder. The current compliance is set to 100 µA for the FORMING and SET operations. The current-voltage curves obtained after the rst 4 characteristic operations are presented in Figure 5.5(a).

Figure 5 . 5 :

 55 Figure 5.5: I(V) curves of the FIB prepared 1 µm thick, 1R, CBRAM sample using the Keithley 2636B power supply. Operations were performed in vacuum in the following order : 1-FORMING (red) ; 2-RESET (blue) ; 3-SET (green) ; 4-RESET (orange)

  The current voltage curve obtained during nal RESET operation presented in Figure5.5 shows almost no sign of resistive switching. The following READ operation however measures an HRS resistance of 6.36 * 10 4 Ω.The current voltage curve of the FORMING operation, as well as the overshoot observed on the following RESET operation demonstrate that resistive switching occurred successfully. However, the high resistance measured after the FORMING operation suggests that the CF is not properly formed. The rst LRS aside, the resistances measured after the 4 operations are in agreement with results obtained during ex situ measurements as shown in Figure5.5. This suggest that the CF is formed and retracted successfully after each operations. Several SET/RESET cycles are performed on the CBRAM device and resistance is measured after each step. The resistance values measured after each operation are summarized in Figure 5.6. This gure shows that the window margin of the device progressively closes. On the 4 th cycle, ON and OFF resistance values become extremely close and it becomes dicult to separate the LRS from the HRS. On the 9 th cycle, sample failed and resistive switching could no longer be performed.

Figure 5 . 6 :

 56 Figure 5.6: Resistance measured after each operation performed on the CBRAM device. Cross-Hatched areas corresponds to normal window margin obtained during ex situ characterization shown in Figure 5.4.

Figure 5 .

 5 Figure 5.7 shows the measured voltage across the resistance when triggering voltage pulses using the Keithley 2636B power supply.

Figure 5 . 7 :

 57 Figure 5.7: Voltage measured on each side of a 26 kΩ resistance when triggering a 2.5 V (blue) and 5 V (red) voltage pulse with a 100 µA compliance current using the Keithley 2636B power supply.

Figure 5 .

 5 Figure 5.8 shows the the measured voltage across the resistance when triggering voltage pulses using the Agilent power supply.

Figure 5 . 8 :

 58 Figure 5.8: Voltage measured on each side of a 26 kΩ resistance when triggering a 2.5 V (blue) and 5 V (red) voltage pulse with a 100 µA compliance current using the Agilent 4156C power supply.

  they. The full voltage pulse are presented in Annexe in Figure 5.22 for the Keithley 2636B and Figure 5.23 for the Agilent power supply. A negative voltage pulse is observed systematically with a variable amplitude when reaching the current compliance with the Keithley 2636B and is presented in Figure 5.9.

Figure 5 . 9 :

 59 Figure 5.9: Sudden voltage change measured during a 5 V pulse performed with the Keithley 2636B power supply.

5. 3 .

 3 Electrical characterization of CBRAM devices using the in situ TEM holder 127 holder. A new CBRAM sample is prepared identically to the one from Section 5.3.1. Electrical operation of the thick FIB prepared sample is done in the same condition, but using the Agilent 4156C power supply. The current-voltage curves obtained after the rst 4 characteristic operations are presented in Figure 5.10 and compared to the results obtained during ex situ characterization.

Figure 5 . 10 :

 510 Figure 5.10:

  4.1 for in situ dedicated sample. The sample was thinned down to electron transparency and cleaned at 2 keV. The chip containing the sample is connected to the in situ TEM holder and left in atmosphere. Finally, the device is operated using the Agilent 4156C power supply. The current voltage curves obtained are shown in Figure 5.11.

Figure 5 .

 5 Figure 5.11: I(V) curves of the FIB prepared 1 µm thick, 1R, CBRAM sample using the Agilent 4156C power supply. Operations were performed in air at ambient pressure.

130 Chapter 5 .

 5 Figure 5.12: (a) HAADF STEM image of the in situ dedicated CBRAM sample electricaly connected to the TEM holder. (b) Electrical layout of the nal sample during in situ biasing experiment.

  perfect conditions, all 4 detectors should measure the same amount of counts for a given beam position. However, shadowing eects can be present due to the sample, the chip, or the TEM holder. It is then important to identify which detectors are partially obstructed. A single point spectrum is performed using a single detector at a time with an acquisition time of 5 seconds. Due to shadowing eects, two detectors measure a lower number of counts. During an EDS acquisition the signal obtained comes from an averaging of the counts collected on every detectors. A shadowed detector then leads to a loss of information during the acquisition. Consequently, the two detectors measuring a lower amount of counts are deactivated. The acquisition is performed for a duration of 60 minutes at a magnication of 57 k leading to a pixel size of 1.2 nm. The EDS map obtained is later compared to another EDS map obtained in the same conditions after resistive switching.Finally, the electron beam is blanked to avoid inuencing the switching mechanism and the FORMING operation is performed. The current voltage curve obtained is shown in Figure5.[START_REF] Guy | Investigation of forming, set, and data retention of conductive-bridge randomaccess memory for stack optimization[END_REF] and compared to the results obtained during ex situ characterization, and during the operation of the thick sample presented in Section 5.3.3 As shown in Figure 5.13, the current-voltage curve obtained during the FORM-ING operation of the device in the TEM foil is close to the one obtained during previous experiments. The distribution of SET and RESET voltages obtained during ex situ characterization are presented in Annex in Figure 5.26. While the FORMING voltage during the operation of a thick chunk is of 2.9 V, the FORMING voltage measured during ex situ and in situ characterization on a TEM foil are both around 3.15 V. No statistics are available for FORMING operation. However, ex situ measurements show that a dierence of 0.25 V is in agreement with the SET and RESET voltage variability of CBRAM devices.

Figure 5 .

 5 Figure 5.13: (a) I(V) curves obtained during the FORMING operation of 1R CBRAM samples. The results obtained during ex situ characterization on fully patterned devices (green) is compared to the ones obtained during in situ biasing using the TEM holder on (blue) 1 µm thick FIB prepared sample and (red) 250 nm thick TEM foil. (b) Resistance measured at 2.5 V during FORMING, and resistance obtained during READ operation on the rst LRS.

Figure 5 . 133 Figure 5 . 14 :

 5133514 Figure 5.14: Electron Dispersive X-ray Spectroscopy maps obtaine (a) before and (b) after in stu resistive switching of the CBRAM sample.

  tectors are composed of a very sensitive ultra thin window. Forcing a current for the duration of the EDS acquisition could damage the sample. The sample temperature would increase due to Joule heating. In these circumstances, it is impossible to guarantee the sample integrity for the duration of the acquisition The CF could become unstable and the resistance of the device would change. This would lead Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices to unexpected current surge. In some cases, this could even lead to the sample exploding. During EDS acquisition, the EDS detector shutters are open and the ultra thin window is exposed. If the sample were to be damaged during acquisition, sample debris could easily damage the detector. 5.5.5 Failure mechanisms observed during in situ biasing A possible solution to help locating the CF is to increase its size. In order to create a larger CF a SET operation with a high current compliance must be performed. Despite the increase in resistance caused by the EDS acquisition, the CBRAM device is supposedly still in a low resistance state. It is then rst necessary to perform a RESET operation as shown in Figure 5.15. At an applied voltage of -90 mV, an increase in the sample resistance is observed. Then, for applied voltage below -90 mV, the sample resistance keeps decreasing down to 1.67 * 10 3 Ω at -1.5 V.The device failure is then conrmed as no further SET or RESET operation could be performed.

Figure 5 . 2

 52 Figure 5.15: I(V) curves of the FORMING (red) and attempted RESET (blue) operations obtained during in situ biasing of the 250 nnm thick CBRAM sample.

5. 5 . 137 Figure 5 . 16 :

 5137516 Figure 5.16: Electron Dispersive X-ray Spectroscopy maps obtained (a) before and (b) after the attempted RESET operation performed in situ leading to the CBRAM device failure.

Figure 5 . 17 :

 517 Figure 5.17: Schematic modeled structure showing the CF composed of oxygen vacancies or copper atoms. For each SET RESET cycles, a given volume is added/removed depending on the R ON /R OF F ratio. Defects are gradually created, nally leading to breakdown of the dielectric ofter N cmax cycles.Figure obtained

5. 5 .Figure 5 . 18 :

 5518 Figure 5.18: Schematic of the defect-migration process during (a) a SET transition and (b) a RESET transition and (c) a negative SET transition. Defects and atoms injected from the top and bottom electrode are reported in red and green respectively, with arrows indicating the migration direction dictated by the applied voltage. Figure obtained from reference[START_REF] Balatti | Voltage-controlled cycling endurance of HfO x -based resistiveswitching memory[END_REF]

Figure 5 .

 5 [START_REF] Coue | Electrical characterization & TEM study of the physical mechanism simplied in reliability issues of Ge-rich GST phase-change memories[END_REF] shows Kinetic Monte Carlo simulations of the impact of temperature on the CF morphology[START_REF] Guy | Evaluation of the performances of scaled CBRAM devices to optimize technological solutions and integration ows[END_REF].The Figure5.19 shows that changes in morphology already occur when exposing a device in LRS to temperature of 70• C for prolonged period of time. It also shows that higher temperatures induce a quicker degradation of the CF. The dissolution of the CF is made possible by the increased mobility of copper atoms in the oxide layer at high temperature. As previously described, radiation damage can induce copper diusion. The change in device resistance observed following EDS acquisition can then be associated with a similar change in morphology. the device failure.

  The electrical properties of the FIB prepared CBRAM device are monitored at dierent stage of the preparation. The current-voltage proles as well as the window margin are systematically compared to measurements performed ex situ. Due to the improvements performed on the dierent stages of the in situ biasing experiment, it Chapter 5. Application of TEM in situ biasing techniques on CBRAM devices has been possible to do in situ operation of a device and obtain identical electrical properties compared to conventional characterization methods.Electron Dispersive X-Ray spectroscopy maps are acquired before and after in situ operation of the CBRAM device. It is demonstrated that radiation damage coupled with beam induce heating causes critical damage to the CF. It is shown that operating a CBRAM device in situ in a TEM foil produces CFs with poor physical and chemical properties. The failure of the CBRAM device is observed in the TEM. The mechanism causing device failure duirng in situ biasing is attributed to a negative SET operation. Finally, the change in elemental distribution following in situ failure of the device provided an insight on the mechanisms involved in the formation of the CF. General conclusions In this work, we have addressed the current challenges encountered during in situ Transimission Electron Microscopy characterization of emerging non volatile data storage technologies. Random Access Resistive Memories are subject to intense research activity, but some functioning mechanisms of those devices remain unclear. In situ TEM is currently considered as the best candidate to answer these questions. TEM holders based on silicon micro chips are a recent innovation. They show great improvements compared to previous technologies especially for electrical biasing experiments. Still, in situ is a particularly complicated technique and experiments are extremely dicult to implement. This work provides new solutions to perform live observations at the atomic scale during both heating and biasing of a specimen inside the TEM. This was made possible through several improvements performed at dierent stages of the in situ TEM experiments. The main focus of this PhD concerned the issues faced during in situ biasing of a nanometer size resistive memory device. This was made possible through hardware investigation, sample preparation method developments, and in situ biasing TEM experiments. The rst chapter describes the context of this work as well as the current state of the art of resistive memories technologies. The second chapter presents the tools used in this work for in situ TEM characterization of resistive memories. This extends from conventional ex situ characterization techniques for ReRAM devices, to FIB sample preparation and TEM imaging. In the third chapter, a new method is developed specically to perform in situ heating experiments. Through this work, live crystallization of a GeTe phase change Memory Material is observed in the TEM. This allowed us to obtain valuable information for the development of chalcogenide based Phase Change Resistive Memories. The fourth chapter focuses on electrical biasing techniques in the TEM. Here, a new chip dedicated to in situ biasing experiments have been developed and manufactured. The FIB sample preparation is studied in order to improve electrical operation in the TEM. Then, quantitative TEM measurements are performed on a reference PN junction to demonstrate the capabilities of this new in situ biasing experimental setup. Finally, the fth chapter presents results obtained on Conductive Bridge Resistive Memories using the improvements performed on the TEM in situ biasing technique. This allowed to obtain new information on the resistive memories functioning mechanisms, as well as the in situ TEM characterization technique itself.

Figure 5 . 20 :

 520 Figure 5.20: Breakdown voltage and depletion layer width at breakdown versus doping density of an abrupt one-sided p-n diode. Values are shown for planar (top curves), cylindrical (middle curves) and spherical (bottom curves) junction with 1 mm radius of curvature [113].

Figure 5 . 21 :

 521 Figure 5.21: Schematic of the composition of a triax cable. The signal conductor and the inner shield are kept at the same potential. Leakage current in the signal conductor is therefore prevented. Instead, leakage current is emitted by the inner shield toward the outer shield.

Figure 5 . 22 :

 522 Figure 5.22: Voltage measured through a 26 kΩ resistor when applying 2.5 V and 5 V pulses using a Keithley 2636B power supply. At t=260 ms, a voltage drop down to 0 V is observed.

Figure 5 . 23 :

 523 Figure 5.23: Voltage measured through a 26 kΩ resistor when applying 2.5 V and 5 V pulse using a Agilient 4156C power supply

Figure 5 . 24 :

 524 Figure 5.24: Electrical schematic of a Keithley 2636B power supply in (a) voltage source mode and (b) current source mode. The schematic is obtained from the Keithley 2636B specication sheet.

Figure 5 . 25 :

 525 Figure 5.25: Scheamtic of a power supply with feedback and transistor current limiting obtained from [138]. "The value of the sense resistor is chosen so that at when the maximum allowable current ows from the power supply, a voltage equal to the turn on voltage of the current sense transistor is developed across it. When the current sense transistor starts to turn on, the voltage at the base of the main power supply pass transistor is pulled down, thereby preventing any increase in the output current of the power supply"

Figure 5 .

 5 Figure 5.26: SET and RESET voltages obtained over 100 cycles performed during ex situ characterization of a 1R CBRAM device.

Figure 5 . 27 :

 527 Figure 5.27: Schematic describing the clean room process logic used for customized in situ biasing chip manufacturing

Figure 5 .

 5 Figure 5.28: 5 keV SEM image showing the origin of the measurement error on a tungsten deposit performed with a 16 keV gallium ion beam.

Figure 5 . 29 :Chapitre 3 :Chapitre 5 :

 52935 Figure 5.29: Schematic showing the origin of surface leakage currents. Energy levels created by dangling bond on surface atoms lead to a reduction of the energy gap between the valence and conduction band[123].

  Non volatile resistive memories working principles . . . . . . 7 1.2.3 Current limits of resistive memory technologies . . . . . . . . 9

1.1 Expanding needs of data storage . . . . . . . . . . . . . . . . 4 1.2 Emerging technologies . . . . . . . . . . . . . . . . . . . . . . 6 1.2.1 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.2 1.3 In situ characterization research motivation . . . . . . . . . 11 1.4 PhD outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Chapter 1. The needs of data storage technologies 1.

Table 1 .

 1

	1.3. In situ characterization research motivation		11
			Flash	PCRAM	CBRAM
		2013	16	45	5
	Integration (nm)
		Projected	<10	8	<5
		2013	4	4	4
	Cell surface (F2)
		Projected	4	4	4
		2013	1 / 0.1 ms	100 ns	<1 ns
	Programming / erasing time
		Projected	1 / 0.1 ms	<50 ns	<1 ns
		2013	4x10-16	6x10-12	1x10-12
	Programming power(J/bit)
		Projected	1x10-16	1x10-15	1x10-16
		2013	10	>10	<10
	Data retention (year)
		Projected	10	>10	>10
		2013	10 5	10 9	10 12
	Endurance (Cycle)	Projected	10 5	10 9	>10 12

1: Characteristics and performances of PCRAM and CBRAM compared to current ash technologies

Table 2

 2

	.1 presents the size of the damaged area

Table 3 .

 3 1: Thermal conductivity of the dierent element involved during in situ

	annealing experiments [99, 100, 101, 102]
		Thermal Conductivity (W/mK)
		300 K	500 K
	Si	148	98.9
	SiO 2	1.1	1.2
	W	174	146
	GeTe	6	5
	BaTiO 3	6	3.9 (420 K)

Table 4 .

 4

	1: Table summarizing the conductivity measured of ion beam and electron
	beam deposited materials. Highly resistive materials which conductivity was too
	low to be measured by the Keithley 2636B are labeled "-".
	Precursor	Beam	Energy (keV)	Conductivity σ (Ω -1 .m -1 )	Error (Ω -1 .m -1 )
	W(CO) 6	Ga	30	2.66 * 10 5	2.43 * 10 5 < σ < 2.94 * 10 5
	W(CO) 6	Ga	16	5.38 * 10 5	4.27 * 10 5 < σ < 7.08 * 10 5
	W(CO) 6	Ga	8	8.90 * 10 5	5.93 * 10 5 < σ < 1.53 * 10 6
	W(CO) 6	Ga	5	3.27 * 10 5	1.31 * 10 5 < σ < 1.96 * 10 6
	W(CO) 6	e -	2	2.34 * 10 4	1.12 * 10 4 < σ < 9.34 * 10 4
	Si(OCH 3 ) 3	e -	2	-	-
		Xe	30	-	-

(CH 3 ) 3 Pt(C p CH 3 ) Ga 30 1.25 * 10 5 1.16 * 10 5 < σ < 1.35 * 10 5 (CH 3 ) 3 Pt(C p CH 3 ) Xe 30 5.06 * 10 2 4.29 * 10 2 < σ < 6.07 * 10 2 (CH 3 ) 3 Pt(C p CH 3 ) Coaxial GIS Xe 30 2.22 * 10 4 1.80 * 10 4 < σ < 2.80 * 10 4 C 6 H 2 4O 6 Si 6

This section is an adapted version of the article[START_REF] Berthier | In situ observation of the impact of surface oxidation on the crystallization mechanism of GeTe phase-change thin lms by scanning transmission electron microscopy[END_REF] entitled "In situ observation of the impact of surface oxidation on the crystallization mechanism of GeTe phase-change thin lms by scanning transmission electron microscopy" by Rémy Berthier et al.

Remerciements

Considering the FORMING condition, it is shown that the CF initially presents a poor thermal stability. After the EDS acquisition, defects are injected in the CF and its morphology is degraded even further. This leads to a decreased conductivity, and an increased defect density in the surrounding of the CF. It has been reported that LRS with high ON resistance are more sensitive copper diusion in the electrolyte [START_REF] Barci | Impact of SET and RESET conditions on CBRAM high temperature data retention[END_REF].

When performing the in situ RESET operation presented in Figure 5.15 the device is in a condition likely to induce failure. The current-voltage curve presented in Figure 5.15 of the failed RESET operation presents similarities with the negative SET failure reported in the literature [START_REF] Ielmini | Resistive switching memories based on metal oxides: mechanisms, reliability and scaling[END_REF][START_REF] Balatti | Voltage-controlled cycling endurance of HfO x -based resistiveswitching memory[END_REF]. This shows that resistive switching occurred at -90 mV. As shown in Figure 5.26, this RESET voltage is abnormally low.

After this resistive switching, the applied voltage keeps increasing, and the resistance of the sample decreases. There is no compliance current during RESET operation.

Consequently, the measured current goes above 100 µA at an applied voltage of -0.89 V. Finally, the decreasing device resistance leads to a current of about 600 µA reported that the dominant ionic species contributing to the formation of the CF is Cu + [START_REF] Sankaran | Modeling of copper diusion in amorphous aluminum oxide in cbram memory stack[END_REF]. Moreover, the mobility of copper atoms and ions is increased due to the poor quality of the CF and high temperature involved during in situ biasing [START_REF] Barci | Impact of SET and RESET conditions on CBRAM high temperature data retention[END_REF][START_REF] Guy | Evaluation of the performances of scaled CBRAM devices to optimize technological solutions and integration ows[END_REF][START_REF] Cabout | Eect of SET temperature on data retention performances of HfO 2 -based rram cells[END_REF]. This can then explain the pronounced copper migration caused by