J A Fernandez-Roldan

A De Riz

B Trapp

C Thirion

J.-C Toussaint

O Fruchart

D Gusakova
email: daria.gusakova@cea.fr

Modeling magnetic-field-induced domain wall propagation in modulateddiameter cylindrical nanowires

Keywords: nanowire, micromagnetism, magnetic field-induced domain wall dynamics, finite element modeling, depinning field PACS numbers: 75.60.Ch, 75.78.Cd, 75.78.-n

Domain wall propagation in modulated-diameter cylindrical nanowires is a key phenomenon to be studied with a view to designing three-dimensional magnetic memory devices. This paper presents a theoretical study of transverse domain wall behavior under the influence of a magnetic field within a cylindrical nanowire with diameter modulations. In particular, domain wall pinning close to the diameter modulation was quantified, both numerically, using finite element micromagnetic simulations, and analytically. Qualitative analytical model for gently sloping modulations resulted in a simple scaling law which may be useful to guide nanowire design when analyzing experiments. It shows that the domain wall depinning field value is proportional to the modulation slope.

INTRODUCTION

Intensive study is devoted to circular cross-section magnetic nanowires due to their unique fundamental properties and their potential applications in a number of advanced technologies such as data storage, sensing and biomagnetics [1][2][3][4]. Electrochemical growth of cylindrical nanowires within self-organized porous templates [5,6] is continuously progressing, and is nearing compatibility with design of a three-dimensional race-track memory [7]. The information stored in this type of solid-state device would be encoded by magnetic domains separated by magnetic domain walls. Domain wall motion in wires may be achieved by applying an external magnetic field [5,8,9], spin-polarized current [10], spin waves or localized temperature gradients [11]. In addition, in a real device, the domain wall position must be precisely controlled. Control can be achieved by designing well-defined pinning centers, for example, by changing the composition of the wire [12] or by introducing geometrical irregularities during the fabrication process [5,8,[14][15][16][17]. In the latter case, modulated diameter of the nanowire synthesized by electrodeposition can be used to control domain wall position by locally reducing its magnetostatic and exchange energy in the smaller cross-sectional parts [18]. Thus, diameter modulation plays the role of a potential barrier which implies that some threshold driving force must be applied to overcome the barrier.

Few studies have theoretically addressed domain wall motion, induced either by applied field or current, within modulated-diameter nanowires [19][20][21][22][23]. Moreover, no theoretical model quantifying the threshold driving force as a function of geometric parameters has yet been reported, although experimental systems are now available. Thus, a general scaling law describing the domain wall depinning phenomenon would be useful to assist experimental system design and analysis of experimental results.

In this paper, we combine both approaches: quantitative micromagnetic description of the domain wall's behavior and development of a simplified qualitative analytical model which provides a simple general scaling law and relates geometric parameters to the domain wall depinning field. We focus on the case of wall motion under the conservative driving force produced by a magnetic field applied along the wire's axis. In this case, the magnetic field contribution can be treated in the framework of a potential energy well. However, our approach is quite general and may be extended further to study the effect of other driving forces such as spin-polarized current.

II. MICROMAGNETIC SIMULATIONS

To understand how geometry affects domain wall propagation in a modulateddiameter cylindrical nanowire when a magnetic field is applied, we used our home-made finite element software feeLLGood [22,24]. The non-regular finite element mesh of feeLLGood accurately describes the given geometry. The Landau-Lifshitz-Gilbert equation was solved for magnetization dynamics [START_REF] Hubert | Magnetic Domains[END_REF] by a micromagnetic approach

= - × + × , (1)
where m=M/MS is the unit vector in the direction of the local magnetization, and MS is the spontaneous magnetization. The following notations were used: γ0>0 for the gyromagnetic ratio, Heff for the effective field (including magnetostatic, exchange and applied field contributions), α for the Gilbert damping factor.

Cylindrical nanowires with a single smooth diameter modulation connecting two straight parts were considered. The smaller diameter was 2R1 and the larger was 2R2, as illustrated in Figure 1 The domain wall position and width were estimated by fitting the longitudinal magnetization component with the tanh-profile similar to the standard Bloch wall model [START_REF] Thiaville | Nanomagnetism and Spintronics[END_REF].

The profile fitted was = !ℎ # -# /∆ %& , where z0 is the position of the center of the domain wall, and ∆ %& is the domain wall parameter. For simplicity, this parameter is called the domain wall width hereafter. In contrast to the widely-used "dynamic" definition of the domain wall width proposed by Thiele [START_REF] Thiele | [END_REF][START_REF]The so-called dynamical Thiele's domain wall width definition is obtained for the stationary domain wall displacement without changing its profile along the invariable crosssection wire axis[END_REF], our formula does not impose constraints on the geometry or on the domain wall dynamics. Indeed, Thiele's definition of domain wall width assumes that the stationary domain wall moves along the invariable cross-section wire without changing its profile. These conditions do not hold in our case as the variable crosssection affects both the domain wall profile and its width. Although the profile corresponds to the one-dimensional Bloch model [START_REF] Hubert | Magnetic Domains[END_REF] rather than to fully three-dimensional magnetization distribution, it fits the transverse-like domain wall width well enough for moderate-diameter wires. Consequently, we restricted our calculations to moderate diameters. Larger diameters (≥40 nm) may favor Bloch Point domain walls with significantly different dynamic properties [START_REF] Hertel | [END_REF][START_REF] Jamet | Magnetic Nano-and Microwires : Design, synthesis, properties and applications[END_REF].

A. Straight wire limit

In this section we show that our numerical implementation is consistent with existing results for straight wires. Similar to what is reported by Jamet et al. [START_REF] Jamet | Magnetic Nano-and Microwires : Design, synthesis, properties and applications[END_REF] the domain wall width estimated from a tanh-profile fit increases with the wire's radius, as illustrated by the open circles in Figure 2(b). This curve tends to the Bloch wall parameter value ∆ '( )* = +4, -/. / 0 at R=0 [START_REF] Hubert | Magnetic Domains[END_REF][START_REF] Thiaville | Dynamics in Confined Magnetic Structures III[END_REF]. No significant difference was observed between tanh-fit values obtained in the absence or in the presence of an applied field. This result contrasts with those reported for rectangular strips, where the domain wall width is strongly affected by the magnetic field applied due to deformation of its structure [32,33]. This crucial difference underlines the leading role of dipolar energy for cylindrical wires.

Under the applied magnetic field, forward domain wall motion at speed 1 is accompanied by its azimuthal rotation at frequency f around the axis of the wire [START_REF] Hertel | [END_REF], as illustrated in Figure 2(a). In the one-dimensional model we expect [

= 72 8 9 :;; .

In our simulations, forward domain wall velocity increased with the applied field in a linear fashion, and, as expected, the slope depended on the wire's radius. Figure 2(c) superposes simulated points on the solid lines calculated using Eq. ( 2) and tanh-profile estimations of the domain wall width. For wires with a small radius (~2.5 nm), simulations perfectly agreed with the analytical expression. Thus, we can conclude that domain wall behavior is well reproduced by the one-dimensional model. We attribute the moderate discrepancy between simulated and analytical values for larger radii (>5 nm) to the deviation of the real wall profile from the perfect tanh-profile shape. This discrepancy is also observable in Figure 2(b) where red stars depict the domain wall widths calculated from the curve representing simulated velocities plotted against applied field dependencies.

In contrast to the slight differences for linear domain wall velocity, perfect matching between Eq.( 3) and numerical values was found for the domain wall rotation frequency [Figure 2(d)]. In this case, as expected, the domain wall's precessional frequency was independent of its width.

B. Nearing and overcoming the modulation

The presence of diameter modulation results in variation of the internal energy of the system depending on the position of the domain wall. To quantify this phenomenon, in Figure 3(a)

we plotted the internal energy as a function of the coordinates obtained with domain walls drifting freely from the broader part toward the thinner part of the wire in the absence of applied field. As expected, the energy of the domain wall was minimized in the thinner part of the wire, because it is proportional to the wire's diameter at any given position, as detailed below in Section III. The highest energy difference corresponded to the highest R2/R1 ratio.

The free drift was accompanied by non-monotonic modification of wall width [Figure 3(b)].

Similar behavior was reported elsewhere [20,22]. We hypothesize that the reduced domain wall width to the left of the modulation and its increase to the right of the modulation can be attributed to the spatial modification of the magnetic charge when entering or leaving the modulation. The domain wall width is adapted in order to ensure the total magnetic charge conservation in the volume, schematized in Figure 3(c). Far from the modulation, both the energy and the width of the domain wall recover the values observed in a straight wire.

Next, we prepared the domain wall in the narrow section of the wire and drove it toward the larger section by applying a magnetic field. Above a critical field value, the domain wall slows down but never comes to a complete standstill, it can thus overcome the energy barrier and continue traveling toward the right. Far to the right of the modulation, the domain wall moves at a constant rate according to Eq.( 2). Its velocity is greater than in the narrow part of the wire. Near to the modulation, the domain wall velocity has non-trivial behavior which is not reflected by the simplified formula. To estimate the final position of the domain wall and the critical field intensity required to unpin it, we developed the analytical approach presented in the following section.

III. ANALYTICAL APPROACH

In this section, we present a qualitative analytical model describing various features of the domain wall in the modulated-diameter wire. In particular, we establish an analytical scaling law which relates the critical applied field value to the geometry of the modulation. To determine this qualitative expression, we considered the domain wall's energy, based on the magnetostatic, exchange and applied field contributions. We also took the interaction between the domain wall and the magnetic charges induced by the modulation into account. For a circular cross-section wire [START_REF] Thiaville | Dynamics in Confined Magnetic Structures III[END_REF] the domain wall energy reads:

> = > + > , > = . 2 @ A B C DE + @ , -FG C B DE -. / 0 @ G C • A :;; B DE + > . 4
Below, we introduce the approximations that can be used to estimate each term.

For the dipolar energy, we considered that the magnetic charge K L:(( = -2M / 0 [35] carried by the tail-to-tail wall was uniformly distributed over a sphere of radius R with magnetic charge density N = 3K L:(( /4M P [Fig. 5(a)]. The real distribution of the magnetic charge is much more complex [36,37]. Nevertheless, our approximation is justified by the quasi linear relationship between the wall width and the wire radius in the dimensions considered [Fig. 2(b)]; it leads to a compact analytical expression for the different energy terms and gives a reasonable order of magnitude. By analogy with electrostatics, the magnetostatic field 9 is 9 Q > = K L:(( /4MQ outside the sphere and 9 Q < = K L:(( Q/4M P inside the sphere. Integration over the whole space reduces the magnetostatic energy contribution to 3M. / 0 P /5.

The exchange energy contribution in Eq.( 4) can be estimated by applying the onedimensional spin chain model [START_REF] Hubert | Magnetic Domains[END_REF] with slowly varying magnetization. In this case ∇ Q ≈ M/2 and the integration of the second term in Eq.( 4) over the sphere volume an exchange energy contribution equals to , -M P /3.

To estimate the Zeeman energy contribution, we neglected the inner structure of the domain wall and considered the Zeeman energy of two adjacent uniformly magnetized domains located at the domain wall's center position, z. With this assumption, the energy contribution would be equal to -2. / 0 9 :;; M W in the case of a straight wire. For the modulated-diameter wire, it would be equal to -2. / 0 9 :;; M X Y DY

The domain wall energy estimated is similar to the energy values extracted from the simulations [Fig. 5(b)] and thus is suitable to qualitatively describe domain wall behavior.

The domain wall interacts with magnetic charges induced by the change in diameter, as illustrated in Figure 5(a). This phenomenon gives rise to a supplementary energy term > , the derivative of which is related to the magnetic field generated by the magnetic charges of the modulation: c> /c# = -. K L:(( 9 # . This term is unlikely to have any analytical expression with the geometry studied here. The field distribution 9 # can be analytically calculated by making some assumptions. For simplicity, we assume that only surface charges are induced by the magnetization parallel to the z axis inside the modulation.

As a result, the field generated by these surface charges at any point along the central axis [START_REF] Durand | Electrostatique et Magnétostatique[END_REF] may be calculated as

9 # = d e X
0fgh Zi Zi j i jk i i +j 8 7 Zi 8 l )*:mg 0nm .

.

The distribution of the 9 # field for different geometries is shown in Figure 5(d). This field opposes the magnetic field applied, as illustrated in Figure 5(a), and amplifies the domain wall's repulsion from the modulation. It is probable that the surface charge simplification overestimates the amplitude of 9 # . Nevertheless, this approach provides an upper limit for 9 # .

For the analytical calculation, the circle-based wire profile used in the numerical simulations may be approximately replaced by the following analytical differentiable function: • j € 7j 8 8 .

# = + + - !ℎ 4#/ /2.
This analytical dependence is illustrated by the dashed red line in Figure 5(e). The corresponding critical field is given by

9 )mf = vd e j 8 Zj € ^• 1 + ( `a 8 = 8 • j € 7j 8 8 . ( 9
)
This approximated relation gives the lower limit for 9 )mf . Magnetostatic domain wall repulsion from a modulation due to surface poles, when not negligible, shifts 9 )mf towards higher values. Nevertheless, the analytical formula (9) provides a good estimation of the order of magnitude of 9 )mf and the relation between 9 )mf and geometric parameters. According to Eq.( 9), the critical field is simply proportional to the slope of the modulation -/ with a negligibly small exchange correction for large diameters. Thus, 9 )mf is almost a linear function of in Figure 6(a) and naturally equals zero in the case of a straight wire, where = . The inverse proportionality between 9 )mf and the modulation length is illustrated in Figure 6(b). This relation verifies the moderate values of 9 )mf for gently sloping modulations.

IV.

ANALYTICS vs. MICROMAGNETICS Figure 7 compares the critical field to the modulation parameters obtained from micromagnetic simulations and those predicted by Eqs. ( 7) and ( 9). This comparison reveals qualitatively similar tendencies. Moreover, small R2/R1 ratios and long λ, corresponding to gently sloping modulations, ensure the best fit between the simulations and the analytical expression. These parameters also provide the best fit for expression describing the final domain wall position as a function of the applied field [Figure 8]. Indeed, of the three simulations tested, that with the gentlest sloping modulation [Fig. 8(b)] showed the best agreement with Eqs.( 7) and (8). In this case, the slope of the modulation satisfies the -≪ condition and |9 | ≪ y9 :;; y, which reduces the magnetostatic contribution of the magnetic pole density stored on the modulation surface [40] and ensures better consistency between the tanh-based and circle-based profiles [39]. Under these conditions, the analytic formulae Eqs. ( 8) and ( 9) become a valuable tool for experimenters. These formulae can be helpful when determining the wire diameter and modulation sizes during the fabrication process to attain the most favorable conditions for domain wall depinning and propagation.

The comparison between analytical expressions and simulated values is less accurate for very abrupt geometries. In these cases the deviation between the two approaches becomes pronounced due to several assumptions used in the model. One of the approximations relates to magnetic charge distribution inside the domain wall. The approximation of a uniformly charged sphere turns out to be too rough and is not well reproduced in micromagnetic simulations [Figure 9]. Although the magnetic charge is concentrated in the confined region close to the center of the domain wall, its spatial distribution is far from constant within this area. The magnetic charge isovalues for the fully three-dimensional magnetic distribution have a non-trivial shape, with a maximum at the center of the domain wall. Another approximation showing limitations relates to the estimated exchange energy. The hypothesis of slow linear variation of the magnetization angle used here, by analogy with the onedimensional spin chain model, nears its limit with abrupt modulations. In addition, the approximation of the uniformly charged sphere may be too rough for radii significantly larger than the exchange length. To deal with this type of case, the domain wall width should be scaled as the square of the radius [START_REF] Jamet | Magnetic Nano-and Microwires : Design, synthesis, properties and applications[END_REF]. Despite these limitations, our simplified analytical approach gave a very reasonable estimation of the behavior of the critical depinning field in response to the modulation parameters. The cases for which the assumptions used in our model are too drastic should be covered by micromagnetic simulations.

Here, our analytical model was focused on a transverse-like domain wall. Typically, dimensions of a few tens of nanometers, with a maximum diameter value between 30 and 50 nm, should ensure transverse-like domain wall stability for most common ferromagnetic materials [41] and thus allow application of our simplified model. Larger diameters favor the so-called Bloch Point Wall configuration. Although the magnetic charges and energy distribution for both types of walls are very similar for large diameters [START_REF] Jamet | Magnetic Nano-and Microwires : Design, synthesis, properties and applications[END_REF], an open question is whether the linear relationship between the depinning field 9 )mf and the modulation slope -/ holds for magnetic textures that are different from transverse-like walls. The result of the corresponding experiments would provide clues for further numerical and analytical analysis.

V. CONCLUSION

This paper presents a theoretical study of transverse domain wall behavior under the influence of an applied magnetic field in a circular cross-section nanowire. In particular, we investigated the domain wall pinning phenomenon close to the wire diameter modulation. We proposed both a quantitative micromagnetic description of the domain wall behavior using our finite element micromagnetic software, and a simplified analytical model which relates geometric parameters to the critical magnetic field needed to unpin the domain wall.

Numerical simulations and analytical predictions based on an approximation of uniformly magnetized magnetic spheres agreed best in the case of gently sloping modulations. To provide a more accurate analytical description of domain wall behavior close to the modulation may require some correction of the model or the inclusion of additional energy terms. These terms may concern such phenomena as, for example, magnetocrystalline anisotropy and its fluctuations in the polycrystalline structure [42], any defects, domain wall structure modification close to an abrupt modulation, or spin-polarized-current-induced effects. Nevertheless, the analytical model developed here is a simple scaling law which may be useful in resolving experimental and nanofabrication issues. R2=6 nm, λ=100 nm; (c) R1=5 nm, R2=10 nm, λ=100 nm.

FIGURE CAPTIONS

  1(b) suitably describes experimental cases[5]. The wire axis was taken as the z direction. The modulation of the length λ was centered at z=0 and L is the total length of the wire. Magnetic charges were numerically removed from the extremities to imitate an infinitely long wire and to prevent nucleation of magnetization reversal; and Brown (Neumann) conditions were used for magnetization components. The micromagnetic parameters used were those of a permalloy material, with MS=800•10 3 A/m, γ0=2.21•10 5 m/(A•s), α=0.05 and exchange constant Aex=1•10 -11 J/m. The system's geometry was discretized into tetrahedrons with dimensions not exceeding 2 nm. The initial magnetic configuration corresponded to a relaxed transverse-like tail-to-tail wall [Fig.1(c)].

  Figure 4(a) shows the domain wall position as a function of time; the changes to internal energy and domain wall width depending on its position are presented in Figures4(b) and 4(c). Below a critical field value, the domain wall slows down when approaching the modulation, partially enters the modulation and finally comes to a halt.

FIG. 1 :

 1 FIG.1: (Color online) (a) Cylindrical nanowire with modulated diameter from smaller value

FIG. 4 :

 4 FIG.4: (Color online) (a) Domain wall position over time. (b) Internal energy of the system as

FIG. 6 :

 6 FIG.6: (Color online) (a) Change to the critical field value depending on the larger radius R2,

FIG. 8 :

 8 FIG.8: (Color online) Comparison between simulated values, Eq.(7) and Eq.(8). Final domain

  At this point, we introduced the exchange length r -= 2, -/. / 0 . The numerical solution of this equation is illustrated by the solid black line in Figure5(e). Equation 7 can be

	+	v d e	9 :;; + 9	# =0.						7
	considerably simplified for gently sloping modulations, when |9 | ≪ y9 :;; y. In this case, the final position of the domain wall can be determined -/ + ≪ 1 and analytically: (8) # = -tanh Z + 1 + ~9:;; /4, where ~= ^• vd e j 8 Zj € 1 + ( `a 8 = 8
	The position of the energy minimum, c> # /c# = 0, corresponds to the position of a
	pinned domain wall. Moreover, the domain wall depinning condition, at a given critical
	applied field value 9 )mf , can be defined as the convergence of two extrema at the same point
	-the inflection point. The equation linking the final domain wall position z to the applied
	magnetic field 9 :;; reads 1 -!ℎ 4#/	q1 +	27	+	+	10r -M -	!ℎ 4 # ⁄	u	-	+

This type of approximation is appropriate for use with the gently sloping modulations studied in this paper

[39]

. To illustrate this case, the domain wall energy > is plotted as a function of the domain wall's position for different applied field values in Fig.

5(c

). Extending this figure by including the > term, if its analytical expression were available, would have no qualitative impact on the illustration, and would only result in shifts in the energy minima and maxima.

Fernandez-Roldan et alFIG.9

ACKNOWLEDGEMENT

We acknowledge financial support from the French National Research Agency (ANR) (Grant No. JCJC MATEMAC-3D) and from the European Union's Seventh Framework Programme (FP7/2007-2013) under grant agreement No.309589 (M3d). J. A. F.-R. is grateful for financial support from the Spanish MINECO under MAT2016-76824-C3-1-R and cosupport from the ESF though BES-2014-068789 and EEBB-I-16-10934.

based wire profile used in numerical simulations and of the analytical tanh-based profile close to the modulation center. This relates and … via the expression 4… = 1 --/ .

For the gently sloping modulation with -≪ this expression reduces to 4… ≅ .

The correction to this expression is quadratic in -/ . For -/ < 0.316 the relative error made by tahn-based shape approximation is less than 10%, which is suitable for a large range of modulation sizes. In the extreme cases of very abrupt diameter transition the disagreement between circle-based and tanh-based modulation shapes is more pronounced.

Nevertheless this mismatch is largely overtopped by such model imperfection as, for example, the omission of the magnetostatic domain wall repulsion from the modulation.

[40] J.


Oto Petura

Marek Laban
email: laban@micronic.sk

Noumon Allini
email: noumon.allini@univ-st-etienne.fr

Viktor Fischer
email: fischer@univ-st-etienne.fr

Elie Noumon Allini

Two Methods of the Clock Jitter Measurement Aimed at Embedded TRNG Testing

come

I. INTRODUCTION

Security of modern cryptographic systems is based on statistical quality and unpredictability of confidential keys. These keys are generated in random number generators using random physical phenomena, appearing in hardware devices, in which the system is implemented. The most frequently used source of randomness in digital devices is the jitter of clock signal generated inside the device in ring oscillators, self-timed rings, RC oscillators, phase-locked loops (PLLs), etc.

The quality and unpredictability of generated numbers depends on the quality and on the size of the clock jitter. It is therefore a good practice to monitor this jitter continuously using some embedded jitter measurement method. As required in the document AIS-20/31 edited by the German Federal Bureau for Information Security (BSI) [START_REF] Killmann | A proposal for: Functionality classes for random number generators[END_REF], the measured jitter parameters are then used as input parameters of the stochastic model used to estimate entropy characterizing unpredictability of generated numbers.

In [START_REF] Baudet | On the security of oscillator-based random number generators[END_REF], Baudet et al. proposed a comprehensive stochastic model for an oscillator based random number generator, in which the entropy rate at generator output is estimated from the variance of the random jitter.

In [START_REF] Haddad | On the Assumption of Mutual Independence of Jitter Realizations in P-TRNG Stochastic Models[END_REF], Haddad at al. proposed to measure the variance of the random jitter from the variance of counter values obtained by counting the number of periods of the jittery clock signal during a time interval defined using a second clock signal generated in the same device as presented in Fig. 1. Instead of computing the variance outside the device, we implement the embedded variance measurement. In this paper, we implement two methods of measurement of the variance of the jitter presented in Section II and evaluate their implementation results in Section III. Next, we study the impact of the measurement circuitry and of the additional logic represented by an AES cipher on the source of randomness in Section IV. In Section V, we present and discuss the jitter measurement results in various implementation conditions. We conclude the paper in Section VI.

II. THE VARIANCE MEASUREMENT METHODS

The first studied variance measurement method is based on the Koenig-Huygens theorem, from which the variance is expressed as follows:

V (X) = 1 n n i=1 x 2 i -E(X) 2 , (1)
where x i are the counter values and E(X) is their mean value.

The second method computes the variance from the frequencies f 1 , f 2 , ..., f m of the possible counter values x 1 , x 2 , ..., x m :

V (X) = m i=1 f i x 2 i - m i=1 f i x i 2 .
(

While both methods should give the same results, it is clear that their implementation and execution in hardware is completely different.

The circuitry corresponding to implementation of Eq. ( 1) in hardware is depicted in Fig. 2. As can be seen in this figure, all the computations are made in a fixed-point arithmetic.

Numbers before and after the radix point indicate number of bits before and after this radix point. Two multipliers (one of 12 bits and the second one of 24 bits) are used to square data. Two adders and associated registers (one of 24 bits and the second one of 12 bits) are used to implement accumulators. One subtractor is used before the output of the block. Four additional data registers are used to store intermediate data.

The circuitry corresponding to implementation of Eq. ( 2) in hardware is depicted in Fig. 3. Again, all the computations are . Two multipliers (one of 12 bits and the second one of 36 bits) are used to square data, two other multipliers are used to multiply 24-bit data and 12-bit data, respectively. Two adders and associated registers (one of 24 bits and the second one of 12 bits) are used to implement accumulators. One subtractor is used before the output of the block. Four additional data registers are used to store intermediate data.

III. IMPLEMENTATION RESULTS AND DISCUSSION

First, we evaluate common design parameters like area, speed and power/energy consumption for the two variance measurement methods. We implemented both of the variance measurements on Intel Cyclone V FPGA in order to obtain area requirements and timing analyzer speed estimation. Power consumption was measured using HECTOR evaluation platform [START_REF] Laban | Platform for testing and evaluation of PUF and TRNG implementations in FPGAs[END_REF]. The results are presented in Table I. The accumulation memory needed to compute the variance according to Eq. ( 2) is included in Tab. I. Although the first method clearly wins before the second one in terms of area and speed (only 119 Adaptive Logic Modules (ALM) needed by the first method vs. 156 needed by the second method, 163 registers vs. 311 registers in the second circuitry, no memory block needed vs. 6 block used in the second case), it is important to note that all the computations of the first method are made continuously and on the fly. They are thus impacted by the measured counter values.

On the other hand, the second method computes the variance in two steps. In the first step, which is running continuously, only simple computations are made (accumulation of samples in the accumulation memory). The second step is made independently from data acquisition -only the accumulation memory contents is addressed and used. We will study this difference in the next section.

The power consumption of both methods is comparable, even though the second one consumes always slightly more power.

IV. STUDY OF THE IMPACT OF THE MEASUREMENT CIRCUITRY ON THE SOURCE OF RANDOMNESS

Next, we propose a rigorous approach to study the impact of the embedded jitter measurement on the measured jitter itself. The impact of the jitter measurement on the jitter itself is evaluated in the following four steps:

1) Project 1 -Only two ring oscillators, which will be used as sources of randomness, are implemented in the selected logic device. The generated clock signals are output using low voltage differential signaling (LVDS) outputs and measured externally using high end oscilloscope and differential probes (see Fig. 4). 2) Project 2 -The two ring oscillators and the variance measurement circuitry are implemented in the device as presented in Fig. 5. The generated clock signals are output using LVDS pins and measured using oscilloscope as previously and their variance is measured also 3) Project 3 -A complete TRNG using two ring oscillators and the variance measurement circuitry are implemented in the device and at the same time, the differential signal outputs are used to measure the jitter variance externally (see Fig. 6). The TRNG output data are acquired in real time using an external acquisition card featuring 32-MB RAM and transfered to the host PC using a high speed USB connection. 4) Project 4 -An AES cipher is implemented alongside the complete TRNG in order to mimic the behavior of the real crypto SoC as presented in Fig. 7. The variance is measured both internally, and externally. In Projects 2 to 4, the embedded measurement gives the variance of counter values, which represent number of clock periods of Osc1 during K = 3000 reference clock periods of Osc2.

When performing the measurement using oscilloscope, the value of K cannot be fixed like it is done in hardware -it can be only deduced from the oscilloscope time base, which was set in our case to 2 µs per division. We measured the number of periods of both clocks in a time interval fixed by Fig. 7. External jitter measurement method using oscilloscope and differential probes combined with an internal jitter measurement method while the TRNG and the AES cipher are running the oscilloscope time base. Finally, to make the comparison of values obtained by the external and embedded measurements more consistent, we measure the number of cycles of both clocks at the same time base interval and process the data according to the following equation:

cnt = n 1 n 2 • K, (3)
where n 1 represents the number of clock periods of Osc1 and n 2 the number of clock periods of Osc2 appearing during the same time interval determined by oscilloscope's time base.

To maintain the measurement results consistent, it is impor-tant to guarantee the same placement and routing of Osc1 and Osc2 in Project 1 to 4. We generated the Exported Partition file (.qxp), which is the Quartus II software option used to export post-fitting netlists. The exported netlist was then used in all projects. We then used the same strategy to export the netlist of the variance measurement block from Project 2 (to Project 3 and 4) and the complete TRNG including the variance measurement method from Project 3 to Project 4.

Ring oscillators Osc1 and Osc2 had the same number of elements and the same topology. They oscillated at respective frequencies of 275.7 ± 1.17 MHz and 267.6 ± 0.8 MHz. The difference in their frequency in all projects was thus smaller than 1 %, which was important to get comparable results.

The variance measurement circuitry from Fig. 2 and 3 was clocked at 25 MHz (clock signal c in these figures). This clock signal was obtained from the low-jitter quartz oscillator oscillating at the frequency of 125 MHz using an embedded PLL, which divided its frequency by 5.

V. MEASUREMENT RESULTS AND DISCUSSION

In this section, we evaluate the two variance measurement methods implemented in the selected logic device as a part of Project 1 to 4 presented in the previous section. Namely, we are interested in comparing the two measurement methods in terms of their noise susceptibility. Table II shows the results of different variance measurement methods. Table II shows, that the variance measured externally has always higher values than that measured in hardware. This fact can be caused by the external measurement equipment (FPGA outputs, probes, oscilloscope, etc.), which adds some additional jitter and consequently, lowers measurement precision.

This observation is very important for the TRNG security. Indeed, the most dangerous error in the TRNG security evaluation is entropy rate overestimation due to incorrect quantification of the source of entropy, i.e. the counter values variations in our case. (we recall that a sufficient entropy rate guarantees unpredictability of generated random values and thus security).

Another important result that can be observed in Table II is that the variance values obtained using the first method based on Eq. 1 are always smaller than those obtained using the second method based on Eq. 2. This is consistent in all projects (Project 2 to 4).

It is also interesting to note that the variance measured using the oscilloscope has the same behavior: the variance of counter values measured outside the device is always smaller when Method 1 is implemented in the device (independently of the type of the project) comparing to the case when Method 2 is used. This can be caused by the noise generated by the measurement circuitry, which is more complex for Method 2 (it includes embedded memory and more multipliers and registers).

VI. CONCLUSIONS

The two measurement methods can be more or less suitable for different data format and for different kind of applications. However, in our testing scenarios, the first method is better in terms of area, speed, and power consumption.

Both embedded methods provide consistently lower variance values than the external measurement used by most designers. This means, that the jitter of internal clock signals is lower than the jitter observed outside the device, which avoids entropy rate overestimation.

Another positive fact is that we did not observe any significant impact of the surrounding logic (of the TRNG and AES cipher circuitry implemented in the same device) on the embedded measurement results. This is important to ensure that the generator output will not be manipulable.

However, it should be taken into account that the variance measurement method itself can still have some negative impact on the size of the counter values. This especially true when measurement Method 2 is applied.

Fig. 1 .

 1 Fig.1. Jitter variance measurement proposed by Haddad at al. in[START_REF] Haddad | On the Assumption of Mutual Independence of Jitter Realizations in P-TRNG Stochastic Models[END_REF]

Fig. 2 .

 2 Fig. 2. Counter variance measurement circuitry based on Eq. (1)

Fig. 3 .

 3 Fig. 3. Counter variance measurement circuitry based on Eq. (2)made in a fixed-point arithmetic. Note, that the figure does not depict the memory in which the histogram of counter values is saved (accumulated data are obtained using ram data and ram addr signals depicted in this figure). Two multipliers (one of 12 bits and the second one of 36 bits) are used to square data, two other multipliers are used to multiply 24-bit data and 12-bit data, respectively. Two adders and associated registers (one of 24 bits and the second one of 12 bits) are used to implement accumulators. One subtractor is used before the output of the block. Four additional data registers are used to store intermediate data.

Fig. 4 .Fig. 5 .

 45 Fig. 4. External jitter measurement method using oscilloscope and differential probes

Fig. 6 .

 6 Fig.6. External jitter measurement method using oscilloscope and differential probes combined with an internal jitter measurement method while the TRNG is running

ACKNOWLEDGMENT

This work has received funding from the European Union's Horizon 2020 research and innovation programme in the framework of the project HECTOR (Hardware Enabled Crypto and Randomness) under grant agreement No 644052.


Julien Fatome

Stphane Pitois

Aladji Kamagaté

Guy Millot

A Kamagate

D Massoubre

J L Oudar

All-Optical Reshaping Based on

Keywords: Optical 2R regeneration, Optical communication, Fabry-Perot microcavity, Switching gate, Saturable absorber, Ultrashort pulses, Nonlinear Optics, Autocorrelation

HAL is

I. INTRODUCTION

In the next-generation of transmission systems and in particular in future upgrading of the already installed fiber-optic networks to higher time-division-multiplexed (TDM) bit rates, picosecond and even subpicosecond pulses will be transmitted through optical fibers [START_REF] Weber | Single channel 1.28 Tbit/s and 2.56 Tbit/s DQPSK transmission[END_REF][2]. Consequently, impairments due to nonlinear, dispersion or polarization mode dispersion effects will be dramatically increased, severely limiting the propagation distance. Thus, in order to develop such future networks, and in a present context of bit-cost reduction, there is a growing demand for low-cost ultra high-speed all-optical regenerators capable to combat cumulative transmission impairments such as the generation of "ghost-pulses" in the "0" bit slots due to the combined effects of both dispersion and nonlinearities [START_REF] Essiambre | Intra-channel cross-phase modulation and four-wave mixing in high-speed TDM systems[END_REF]. Some preliminary experiments of signal reshaping at 160 Gbit/s have already been successfully done in back-toback configurations by means of Nonlinear Optical Loop Mirrors (NOLM) [START_REF] Bogoni | All-Optical Regeneration and Demultiplexing for 160-Gb/s Transmission Systems using NOLM-Based Three-Stage Scheme[END_REF] and Saturable Optical Amplifiers (SOA) [START_REF] Leuthold | 160 Gbit/s SOA all-optical wavelength converter and assessment of its regenerative properties[END_REF]. But it is well known that NOLMs generally suffer from a complex experimental setup, require very strong input energies and are strongly dependent on signal polarisation and fiber parameters; while SOAs are active components and based on a wavelength conversion process. On the other hand, the Saturable Absorber (SA) device is totally passive, polarisation independent, easy to use, its relaxation time can be adjusted to less than 1 ps [START_REF] Joulaud | Thermal stability of ion-irradiated InGaAs with (sub-) picosecond carrier lifetime[END_REF] and one may reshape several wavelengths on the same chip [START_REF] Rouvillain | Optical 2R regenerator based on passive saturable absorber at 40 Gbit/s for WDM long haul transmissions[END_REF], making it more suitable for low cost reshaping. Moreover, benefits of quantum well microcavity SA have already been demonstrated through 10-Gbit/s and 40-Gbit/s long haul transmission recirculating loop experiments [START_REF] Rouvillain | Optical 2R regenerator based on passive saturable absorber at 40 Gbit/s for WDM long haul transmissions[END_REF][START_REF] Gay | Cascadability Assessment of a 2R Regenerator Based on Saturable Absorber and Semiconductor Optical Amplifier in a Path Switchable Recirculating Loop[END_REF] and also by improving the extinction ratio of a 160-GHz pulse source using a 1-ps relaxation time component [START_REF] Massoubre | All-optical extinction ratio enhancement of a 160 GHz pulse train using a saturable absorber vertical microcavity[END_REF]. In this letter, the regenerative capabilities of such a saturable absorber-based microcavity device are investigated for the first time to our knowledge for future 160-Gbit/s applications. In this aim, a degraded "…01010101…" 160-Gbit/s bit pattern combined with autocorrelation function measurements have been used to characterize the regenerative properties of our saturable absorber component.

II. DESIGN AND FABRICATION OF THE DEVICE

The structure reported in this paper and its principle of operation are similar to the ones reported elsewhere [START_REF] Rouvillain | Optical 2R regenerator based on passive saturable absorber at 40 Gbit/s for WDM long haul transmissions[END_REF][START_REF] Gay | Cascadability Assessment of a 2R Regenerator Based on Saturable Absorber and Semiconductor Optical Amplifier in a Path Switchable Recirculating Loop[END_REF][START_REF] Massoubre | All-optical extinction ratio enhancement of a 160 GHz pulse train using a saturable absorber vertical microcavity[END_REF][START_REF] Massoubre | Scaling of the saturation energy in microcavity saturable absorber devices[END_REF][START_REF] Massoubre | Analysis of Thermal Limitations in High-Speed Microcavity Saturable Absorber All-Optical Switching Gates[END_REF]. It consists of an active layer (7 InGaAs/InP quantum wells) comprised inside an asymmetric Fabry-Perot micro-cavity and suitably located at the antinodes of the intracavity intensity. After MOVPE growth, the structure underwent 12°MeV Ni 6+ ion irradiation with a dose of 1x10 12 cm -2 . Such energetic ions create clusters of defects along the ion path through the active layer. These defects act as carrier recombination centers, which shorten the carrier lifetime down to a few picoseconds [START_REF] Joulaud | Thermal stability of ion-irradiated InGaAs with (sub-) picosecond carrier lifetime[END_REF]. Pump and probe measurement at 1555 nm showed a response time of 1 ps and already published results on the experimental reshaping of a 160-GHz pulse train have demonstrated that the response time of this SA device is fully compatible with 160-Gbit/s applications [START_REF] Massoubre | All-optical extinction ratio enhancement of a 160 GHz pulse train using a saturable absorber vertical microcavity[END_REF]. The back mirror was made by the deposition of a thin silver (Ag) layer, then a top-down mounting was made by soldering this Ag film on a silicon wafer by means of an In-Au metallic bonding to improve the heat dissipation. A finely controlled chemical etching of the top InP phase layers permitted the resonance matching with the quantum well excitonic absorption wavelength.

The microcavity resonance has a typical -3 dB bandwidth of 50 nm centered at 1.55 µm.

Finally a two period dielectric layer (2x SiO 2 /TiO 2 : λ/4 / λ/4) was deposited as front mirror of the cavity. The cavity was designed to have a reflectivity close to zero at low intensity (impedance matching).

III. EXPERIMENTAL RESULTS AND DISCUSSION

The experimental setup is shown in Fig. 1. A high quality 80-GHz 2.4-ps transform-limited pulse train was first generated at 1561 nm by using the multiple four wave mixing technique in a 1420-m long Teraligth fiber [START_REF] Fatome | 20-GHz to 1-THz repetition rate pulse sources based on multiple four wave mixing in optical fibers[END_REF]. Then, a 50:50 coupler combined with a 6.25 ps delay line was used to generate through multiplexing in the time domain, the following simplified bit pattern "…01010101…" at 160-Gbit/s. A variable attenuator (Att) has also been inserted into the delay line in order to adjust the energy of the ghost-pulses injected into the "0" bit slots. The resulting poor quality 160-Gbit/s pulse train was then amplified by means of an Erbium doped fiber amplifier (EDFA) and focused on the microcavity saturable absorber (SA) device thanks to a fiber-pigtailed high aperture lens producing a focus spot of 5 µm diameter at 1/e 2 of the maximum intensity (the insertion losses of the regenerative module were evaluated to 10 dB). Finally, the signal at the SA input and the corresponding regenerated pulse train at the SA output were recorded by means of a second-harmonic background-free autocorrelator. Figure 2a represents in a logarithm scale the output autocorrelation traces of the bit pattern as a function of the input average power focused on hal-00474851, version 1 -21 Apr 2010 the device. The Curve (1) in dashed line corresponds to the initial "…01010101…" 160-Gbit/s bit pattern recorded at the output of the delay line. After reflection on the SA device, we can clearly observe a large improvement of the signal quality as the input average power increases. This improvement is characterized by a strong reduction of the energy contained in the "0" bit slots with nearly an extinction of these ghost-pulses for an average power close to 80 mW (curve 4). Figure 2b illustrates the evolution with respect to the SA input average power of both the intensity extinction ratio (IER) improvement (circles) and the relative amount of energy, E r (stars), contained in the ghost-pulses; and defined as the ratio between the energy contained in the "0" slots and the total energy. IER and E r are given here by:

out in R IER=-10 log R ⎛ ⎞ ⎜ ⎟ ⎝ ⎠ , (1)
with

0 1 E R= E , (2)
where E 0 and E 1 are the energy contained in the ghost-pulses and in the "1" slots respectively, and 0 0 1

r E E = E E + , (3)
with E 0 +E 1 the total energy.

We can see on Fig. 2b that the optimum SA input average power for which the highest pulse quality improvement is observed, was measured to be 80 mW (19 dBm). With this experimental configuration, the IER enhancement is maximal and equal to 11.7 dB, leading to a drop of the relative amount of energy contained in the "0" slots from E r = 10.5 % to only E r = 0.8 %. Note that when the power is increased above 80 mW the IER enhancement decreases significantly, owing to a thermal shift of the spectral resonance with increasing average power [START_REF] Massoubre | Analysis of Thermal Limitations in High-Speed Microcavity Saturable Absorber All-Optical Switching Gates[END_REF]. A second series of experiments was carried out to test the regenerative efficiency of our SA device as a function of the ghost-pulse input energy. Figures 3a and3b represent the input (circles) and output (solid line) autocorrelation functions of the 160-Gbit/s sequence for an initial ratio of energy injected into the "0" slots of E r = 3.7 % (Fig. 3a) and E r = 19.6 % (Fig. 3b). After reshaping in the SA device at the optimum input average power, no dramatic change was noticed on the bits "1", except a small temporal compression from 2.46 ps to 2.30 ps. Note that Frequency Resolved Optical Gating (FROG) characterizations made on a 1.3-ps 160-GHz pulse train [START_REF] Massoubre | All-optical extinction ratio enhancement of a 160 GHz pulse train using a saturable absorber vertical microcavity[END_REF] have shown that a slight asymmetry could also be introduced by our component on the pulse intensity profile because of a pulse width comparable to the response time of our component. This phenomenon is hidden because of the symmetric feature of the autocorrelation function but should be negligible here because of a pulse width (2.4 ps) more than twice larger than the response time (1 ps). On the other hand, we can clearly observe a strong reduction of the ghost-pulses contained in the "0" bit slots which relative amount of energy decreased to E r = 0.5 % in Fig. 3a and to E r = 3.4 % in Fig. 3b, confirming the saturable regenerative action of our component. Figure 4a sums up all the "0" bit reshaping measurements. In this figure, we plot the nonlinear response of our SA device, i.e. the output ratio of energy E r contained in the ghost-pulses as a function of the input ratio.

As expected, our SA device is characterized by a nonlinear response with a large discrimination of low powers which is essential for any all-optical regeneration processing.

These results complete our previous work in the sense that the SA device is now proved to be able to reshape not only consecutive "1s" cadenced at 160 GHz [START_REF] Massoubre | All-optical extinction ratio enhancement of a 160 GHz pulse train using a saturable absorber vertical microcavity[END_REF] but also a sequence made of a "0" level followed or preceded by a "1", and separated by 6.25 ps. This is a strong indication that our SA component is compatible with future 160-Gbit/s regeneration applications. Finally, in order to complete the characterization of our SA device, we measured its sensitivity to possible patterning effects caused by transient thermal phenomena by recording the spectral resonance shift as a function of the 160-Gbit/s pattern length for a fixed input average power. For these measurements, we used an acousto-optic switch at the input of the SA device in order to adjust the sequence length and its duty-cycle. Figure 4b represents the experimental results obtained for a pattern length ranging from 100 ns to 10 ms and for an adjusted duty-cycle of 4 ensuring a constant average power at the device input. We can see that after a rough increase of the resonance shift, the spectral resonance stabilizes around 1561 nm from a pattern length of 100 µs, indicating that the characteristic time of thermal effects can be estimated to be 6 orders of magnitude larger than the bit slot duration (~10 µs compared to 6.25 ps). Consequently, assuming that the rising and decreasing times of thermal effects are equal, in the case of a pseudo-random bit sequence, the rapid changes of pattern even with long series of "1" or "0" will do not significantly shift the resonance wavelength of our component and thus, will not affect its regeneration efficiencies.

IV. CONCLUSION hal-00474851, version 1 -21 Apr 2010

In this paper, we have investigated the regeneration capabilities of a passive and all-optical saturable absorber-based switching gate for future 160-Gbit/s reshaping applications. A "…01010101…" 160-Gbit/s pattern was generated by multiple four wave mixing and time multiplexing at 1561 nm and used as degraded signal for the regenerative characterizations.

Autocorrelation function measurements show that a reduction up to 11.7 dB of the energy contained in the ghost-pulses can be achieved for an input average power of 80 mW (19 dBm). Moreover, we have shown that the thermal effects are sufficiently slow compared to the bit slot duration and consequently that any patterning effects should not affect its regeneration capabilities. These results have to be confirmed by a pseudo-random bit sequence 160-Gbit/s experiment but they already indicate that this device is a promising candidate for future low-cost all-optical 2R-regeneration at 160-Gbit/s.

Figure Captions

Fig. 1 :

 1 Fig. 1: Experimental setup. Att: variable optical attenuator, Δτ: delay line, EDFA: Erbium doped fiber amplifier, SA: saturable absorber.

Fig. 2 :

 2 Fig. 2: (a) Autocorrelation functions of the 160-Gbit/s pattern as a function of the SA input average power. (1) SA input reference, (2) 60 mW (17.8 dBm), (3) 70 mW (18.5 dBm), (4) 80 mW (19 dBm) (b) Intensity extinction ratio (ER) improvement (circles) and ratio of energy E r contained in the ghost-pulses at the SA output (stars) as a function of the input average power.

Fig. 3 :

 3 Fig. 3: Autocorrelation functions of the 160-Gbit/s sequence at the input (circles) and output (solid lines) of the SA device. (a) In: E r =3.7 %, out: E r =0.5 % and (b) In: E r =19.6 %, out: E r =3.4 %, respectively.

Fig. 4 :Fig. 1 :

 41 Fig. 4: (a) Nonlinear response of our SA device: ratio of energy E r contained in the ghostpulses at the output of the SA device as a function of the input ratio (b) Resonance wavelength as a function of the sequence length. hal-00474851, version 1 -21 Apr 2010

Fig. 2 :

 2 Fig. 2: (a) Autocorrelation functions of the 160-Gbit/s pattern as a function of the SA input average power. (1) SA input reference, (2) 60 mW (17.8 dBm), (3) 70 mW (18.5 dBm), (4) 80 mW (19 dBm) (b) Intensity extinction ratio (ER) improvement (circles) and ratio of energy E r contained in the ghost-pulses at the SA output (stars) as a function of the input average power.

Fig. 3 :

 3 Fig. 3: Autocorrelation functions of the 160-Gbit/s sequence at the input (circles) and output (solid lines) of the SA device. (a) In: E r =3.7 %, out: E r =0.5 % and (b) In: E r =19.6 %, out: E r =3.4 %, respectively.

Fig. 4 :

 4 Fig. 4: (a) Nonlinear response of our SA device: ratio of energy E r contained in the ghostpulses at the output of the SA device as a function of the input ratio (b) Resonance wavelength as a function of the sequence length.