Pierre-Olivier Bouchard
email: pierre-olivier.bouchard@mines-paristech.fr

Marc Bernacki

David M Parks

P.-O Bouchard

Analysis of stress intensity factors and T-stress to control crack propagation for kerf-less spalling of single crystal silicon foils

Keywords: mono silicon, stress intensity factors, T-stress, crack propagation, crack stability

come

Analysis of stress intensity factors and T-stress to control crack propagation for kerf-less spalling of single crystal silicon foils

Introduction

During the last decade, a huge effort was made in the photovoltaics (PV) industry in order to reduce the cost of production while improving the efficiency of solar cell systems. In terms of efficiency, it was shown that the peak in terms of efficiency can be reached for silicon foils thicknesses below 100 µm, in the range 40-60 µm [START_REF] Green | Very high efficiency silicon solar cellsscience and technology[END_REF]. Cost reduction can be achieved by reducing the cost of materials or decreasing processing costs. Manufacturing thin silicon foils without kerf-loss is thus interesting both in terms of cost reduction and efficiency improvement. One of the most promising techniques to produce such thin silicon foils without kerf-loss is based on a controlled fracture process of the silicon substrate. A stress-inducing layer is deposited on a suitable crystallographic plane of a moncrystalline silicon substrate. Residual tensile stress in the deposited film induces stress in the silicon substrate that can lead to crack initiation and propagation. This process is achieved below the brittle-to-ductile transition temperature of silicon [START_REF] Hirsch | The brittle-ductile transition in silicon[END_REF], so that linear elastic fracture mechanics can be used to model silicon brittle fracture. By controlling the film deposition process (e.g., film thickness; magnitude of residual tensile stress, etc.) it is possible to propagate a crack parallel to the interface at a given depth, in the process producing a uniform-thickness silicon foil.

Experimental feasibility of such a process was shown first by Dross et al. [3 -5]. In their process, the stress-inducing layer is made of two metallic layers sequentially deposited from a liquid phase at relatively high temperature. During the cooling stage, the higher thermal expansion coefficient of the metallic layers induces tensile stress in the silicon substrate, causing a crack to initiate and propagate until complete fracture. Controlling the crack stability is quite challenging in this technique, since it relies mainly on the cooling history of the metallic layers. The high temperatures used in this method are problematic for multiple reasons. First, at high temperatures, atomic metal diffusion into the silicon foil can dramatically reduce the efficiency of photovoltaic conversion; indeed, the first-deposited metal layer serves in part as a diffusion barrier. Secondly, depending on the cooling rate at the highest temperatures, the build-up of elastic strain due to thermal expansion mismatch is partially relieved by viscoplastic flow in the metals, reducing the final stress in the film.

More recently, Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] demonstrated that the same kind of kerf-less controlled fracture process was possible at ambient temperatures. The stress-inducing layer, made of nickel, is deposited using electroplating or by an electroless plating technique [START_REF] Bedell | Spalling for a semiconductore substrate[END_REF]. Control of both the thickness and the stress induced in the nickel layer determines the thickness of the fracture depth as well as inhibiting spontaneous fracture of the metal/substrate system. An additional flexible adhesion layer is then applied to the top of the metal layer. By pulling on this adhesive layer, the crack propagates in a controllable manner, parallel to the interface In this paper, a mechanical and numerical study of the fracture process is presented through a detailed analysis of stress intensity factors (SIF). This analysis aims at understanding the influence of different process parameters on the fracture phenomenon. In particular, the influence of the stress induced in the deposited layer, as well as its thickness on the depth of the propagating crack. First, preliminary theoretical studies made on crack propagating in brittle substrates beneath adherent films are presented to introduce fracture mechanics concepts for such configurations. In section 3, we present the configuration studied here. A nickel layer with a given thickness and a given residual tensile stress is deposited on a silicon substrate with an initial pre-crack. Numerical analyses are performed at room temperature with the FE software Abaqus. In section 4, stress intensity factors are computed to study the influence of the geometrical/process parameters on the crack propagation direction. Finally, The T-stress is analysed in section 5 to study the stability of the crack propagation direction.

Fracture mechanics in a thin film / brittle substrate system

A number of experimental and theoretical studies were conducted in the late 80's to understand the propagation of cracks in the presence of thin films. Depending on the configuration, these cracks can propagate at the film/substrate interface, or in the substrate, parallel to the interface. Spalling was first investigated under edge loading, and experiments conducted on glass and PMMA (polymethylmethacrylate) showed cracks propagating parallel to the side surface [START_REF] Thouless | The edge cracking and spalling of brittle plates[END_REF]. Thouless et al. [START_REF] Thouless | The edge cracking and spalling of brittle plates[END_REF] showed that for a homogeneous plate containing a sub-surface crack, the stress intensity factors can be given by: where P and M are, respectively, the edge load and edge moment per unit out-of-plane depth, as shown in Figure 1, d is the crack depth, and K I and K II are the stress intensity factors for modes I and II, respectively. As the crack tends to propagate in the direction for which K II =0, it is possible to compute the crack depth d * at which such a crack exhibits extensive propagation parallel to the adjacent free surface:

P M d 7 . 2 * = (2)
Subsequently, Drory et al. [START_REF] Drory | On the decohesion of residually stressed thin films[END_REF] investigated the effect of depositing a thin film under residual tension on edge cracks in the substrate. They observed that cracks have a strong tendency to propagate into the brittle substrate, parallel to the interface. Based on superposition principles, it can be shown that generalized edge loading and tensile thin films deposited on a substrate induce equivalent stress intensities at the crack tip. Accounting for the film thickness and elastic properties, Drory et al. [START_REF] Drory | On the decohesion of residually stressed thin films[END_REF] showed that it is possible to express the stress intensity factors as a function of the tensile stress in the film (σ 0 ), the crack depth (d), the film thickness (h f = η ⋅d), the substrate thickness (h s =τ ⋅d), the modulus ratio Σ and the moment of inertia (I) of the resulting bi-layer beam per unit out-of-plane thickness. I depends on the position of the neutral axis of the beam above the substrate crack, and its value is given in [START_REF] Drory | On the decohesion of residually stressed thin films[END_REF].

The modulus ratio is Σ=E f /E s for plane stress and Σ=E f (1-ν s 2 )/E s (1-ν f 2 ) for plane strain conditions. E f , ν f (resp. E s , ν s ) are the film (resp. the substrate) Young's modulus and Poisson ratio.

The stress intensity factors for edge cracks loaded by tensile films are given in equation 3,

where the parameter λ=h s /h f =τ/η representing the thickness ratio between the substrate and the film is added for the sake of simplicity. The steady-state cracking in brittle substrates beneath adherent films was then generalized by Suo and Hutchinson in [START_REF] Suo | Steady-state cracking in brittle substrates beneath adherent films[END_REF].

( ) ( ) ( ) ( )         + Σ + - + Σ =         + Σ + + + Σ =
Based on these results, Xu and Blume [START_REF] Xu | Crack interaction and propagation-stability in a thin film/substrate system[END_REF] extended the analysis of such cracks propagating beneath adherent films by studying the T-stress. The T-stress is the first non-singular term asymptotic expansion of the stress field as a function of stress intensity factors at a crack tip. It represents a normal stress parallel to the crack faces and can be used to study crack propagation stability and kinking.

Cotterell and Rice [START_REF] Cotterell | Slightly curved or kinked cracks[END_REF] modeled the directional stability of crack propagation based on stress intensity factors and T-stress analyses. They assume that if K II ≠0 for a straight crack, then as overall load magnitude is increased to critical level, the initial incipient cracking will kink from its original plane at an approximate angle of θ * =-2K II /K I (radian measure). The crack kinks up if θ * >0 and kinks down if θ * <0. In addition, Cotterell and Rice's perturbation solution showed that when a crack propagates "straight ahead" with K II =0 and θ * =0, it is directionally stable if T<0 but unstable if T>0. [START_REF] Xu | Crack interaction and propagation-stability in a thin film/substrate system[END_REF] studied edge cracking in a substrate where loading comes from a tensile film. Assuming straight ahead crack, they found a positive value of the T-stress for a steadystate substrate crack loaded by uniform film tension. According to the Cotterell-Rice criterion [START_REF] Cotterell | Slightly curved or kinked cracks[END_REF], the steady-state crack propagation should then be directionally unstable, a result in contradiction with the experimentally steady-state straight cracks propagation observed at a given depth below the interface.

Xu and Blume

In comment on this issue, Xu and Blume assumed that the stability of the propagating crack depends on the crack length. They hypothesized that, for a short crack, the laminated composite beam of materials (between the crack and the top surface) is short and dominated by compression, thus inducing a negative T-stress. They assumed further that when the crack exceeds a given critical length L c , the composite beam is submitted to bending effect, which causes a positive T-stress. This T-stress sign and the influence of the crack length will be studied in the last section of this paper.

Definition of the numerical configuration

A parallelepiped mono silicon substrate covered with a nickel thin film is considered (Figure 1.a), where h s , l s and t s denote respectively the in-plane thickness, length and out-of-plane thickness of the mono silicon substrate. The nickel film has the same length and out-of-plane thickness as the silicon substrate, and an in-plane thickness h f .

The numerical geometrical configuration is presented in Figure 1.b, where plane strain conditions are assumed. A symmetry plane is assumed on the right side. Figure 1.c shows the pre-crack configuration, where a, d and w are, respectively, the initial crack length, crack depth, and crack opening.

The aim of such a process being to obtain directionally-stable crack propagation at a given depth d in the Silicon substrate, d is chosen to be the reference length. The value of d will depend on the thickness of the stress-inducing film, but also on the Dundurs' parameters [START_REF] Dundurs | Elastic interaction of dislocation with inhomogeneities[END_REF] that are commonly used to characterize the elastic fields in isotropic bimaterial systems:

( ) ( ) ( ) ( ) 1 1 1 1 + + + Γ + - + Γ = f s f s κ κ κ κ α and ( ) ( ) ( ) ( )
1 1 1 1 + + + Γ - - - Γ = f s f s κ κ κ κ β . ( 4
)
Subscripts f and s refer to the film and substrate materials, respectively.

ν κ 4 3 - =
for plane strain and

( ) ( ) ν ν κ + - = 1 / 3
for plane stress and

s f µ µ / = Γ
. Here µ and ν are, respectively, the shear modulus and Poisson's ratio. The parameter

[ ] 1 ; 1 - ∈ α
and is a measure of the stiffness dissimilarity of the two materials. If the film is stiffer than the substrate, then α is positive. Conversely, if the film is more compliant than the substrate, α is negative. As shown in [START_REF] Drory | On the decohesion of residually stressed thin films[END_REF][START_REF] Suo | Steady-state cracking in brittle substrates beneath adherent films[END_REF], α has a significant influence on the crack depth and stability, whereas the parameter β has only weak influence on the crack depth exhibiting K II =0.

In the following, the fixed sample length is l s = 40 mm, and the plane strain assumption removes the out-of-plane thickness t s from consideration. In the next section, the influence of in-plane thicknesses h s and h f , as well as the target crack depth, d, will be studied. The Abaqus finite element program, part of the SIMULIA package of Dassault Systèmes, was used here. Eight-node quadratic quadrilateral elements (CPE8) were used, and particular attention was paid to the mesh refinement at the crack tip in order to avoid any mesh perturbations on stress intensity factors computation. The ratio between the size of crack tip element, l t , and the target crack depth is:

l t d = 4 ⋅10 -2 .
Linear elasticity is assumed for both materials, since only small strains are reached and the film deposition process is done at room temperature.

Mono silicon is an anisotropic material whose properties depend on its relative orientation to the crystal lattice. . However, as a simplifying assumption, both elastic and fracture properties will be considered isotropic in this study, and the effects of anisotropy on crack propagation will be studied in a future work. Properties adopted to model mono silicon are given in Table 1; more details on thermomechanical and fracture properties of mono silicon can be found in [START_REF] Masolin | Thermo-mechanical and fracture properties in single crystal silicon[END_REF].

The deposited nickel layer is considered as isotropic and homogeneous. Again, this is a simplifying assumption, since the creation of such a nickel layer using physical vapor deposition (PVD), chemical vapor deposition (CVD) or similar techniques [START_REF] Bedell | Spalling for a semiconductore substrate[END_REF] can induce thickness heterogeneity within the layer. Regarding anisotropy, the deposited nickel film is polycrystalline, but if the film is thin, there may be a 111 growth-type texture in grains, which might render the nickel as effectively transversely isotropic around a direction parallel to the growth direction.

Chosen values for the nickel Young's modulus, E Ni , and Poisson's ratio, ν Ni , are given in Table 1.

Table 1. Silicon and nickel elastic properties, and silicon toughness

Based on the plane strain elastic mismatch, the Dundurs parameters (4) for this configuration are: α = 0.19 and β = 0.067.

A symmetry plane is assumed on the right edge of both substrate and film, and the bottom right node of the mesh is fixed in order to suppress rigid body translation.

An initial horizontal tensile stress σ 0 is applied in the film (see Figure 3.a). This induced stress can be applied as an initial stress condition in Abaqus. The unloading of this initial tensile stress in the film induces a non-zero stress field in the silicon substrate as can be seen in Figure 3.b. However, it must be noted that in the real deposition process, the induced tensile stress field is non-uniform. In particular, the left lateral border of the nickel film (n = -e 1 ) is physically traction-free, which is thus locally different to the initial stress condition assumed here. But this difference has only local consequences at the extreme top left corner and does not influence the stress field at the crack tip.

In addition, depending on the deposition process used, a gradient of tensile stress may appear across the thickness of the film. The prediction and understanding of this gradient is not straightforward and is a recurrent topic of discussions in the literature. It is commonly accepted that, for different materials, the gradient of tensile stress increases with a reduction of the thickness or an increase of the temperature. However, a more accurate analysis must involve a multi-scale description of the physical phenomenon accounting for the polycrystalline structure of the deposited material and its evolution during the process [START_REF] Consonni | The flow stress in polycrystalline films: Dimensional constraints and strengthening effects[END_REF].

0.3 188 Ni 31.6 0.278 130 Si K Ic (MPa.mm 1/2 ) ν E (GPa) 0.3 188 Ni 31.6 0.278 130 Si K Ic (MPa.mm 1/2 ) ν E (GPa)
Such a modelling is out of the scope of this paper and we assume here that the initial stress condition used is the one that acts at the film/substrate interface. Last but not least, due to the plane strain assumption, the initial tensile stress field is assumed to be uniaxial, whereas it should be equal biaxial, due to the deposition process. This last assumption can be solved by performing a 3D simulation of the process and by imposing a biaxial initial stress field. But the two first assumptions would require an enhanced analysis of the film deposition mechanisms to get a better description of the stress field. The computations made in the following are based on a uniform uniaxial initial stress field in the nickel film.

Stress intensity factors (SIF) and T-stress are computed in Abaqus using domain interaction integrals, based on 5 layers of elements surrounding the crack tip. Special attention has been paid to the convergence of the results with respect to mesh size and number of contours.

Numerical study of SIF depending on geometrical configuration

Computations are performed using the implicit version of Abaqus. The initial tensile stress in the nickel film is relaxed while stress tends to increase in the Silicon substrate, in particular at the crack tip. Figure 3 shows the stress field at the end of the simulation for the following configuration: show, respectively, the σ 11 , σ 22 , σ 12 and σ 33 near-tip stress fields. For each figure, the stress scale has been chosen so as to have an optimal view of the stress distribution at the crack tip.

However, σ 22 is by far the predominant in-plane stress component, being two to three times larger than σ 12 and σ 11 . The distribution of σ 22 in Figure 3.d is characteristic of a stress concentration at the tip of the crack for a plane strain configuration. However, the stress field is singular for such linear elastic fracture configuration, so that the computed maximal stress value depends on the mesh refinement at the crack tip.

Stress intensity factors have to be computed to study whether the crack is going to propagate or not. An initiation criterion for mode I is used, e.g. the crack propagates when K I exceeds Silicon toughness Ic . The K II =0 criterion is used to define the direction of the crack kinking. This criterion states that the crack kinks to make K II =0. For a given crack depth, d, the crack will kink up (towards the interface) if K II is negative and will kink down (away from the interface) if K II is positive. If K II =0, then the crack will propagate horizontally, in a direction parallel to the interface.

Influence of nickel film thickness for 2 different values of silicon substrate thicknesses:

In this first configuration, we consider a reference geometrical configuration given by: a = 0.4 mm and d = 0.075 mm

( 3 . 5 = d a
), and we study the influence of silicon substrate and nickel film thicknesses. The mono silicon substrate thickness h s is equal to 1 or 10 mm. The film thickness h f varies from 0.01 mm to 0.1 mm. The initial tensile stress applied in the nickel film is equal to 380 MPa. Increasing the nickel film thickness induces an increasing of both K I and K II . Increasing the silicon substrate thickness has almost no effect on K I , but affects significantly K II . This is due to the fact that a lower substrate thickness allows more bending (max deflection equals to 0.15 mm) than a thicker one (max deflection equals to 0.012 mm). For h s = 10 mm, a value of h f = 0.03 mm would be needed to obtain mode I horizontal crack propagation at a depth d = 0.75 mm, whereas h f = 0.04 mm would be needed to obtain the same cracking in a thinner silicon substrate of h s = 1 mm. As can be seen on figure 5.a, decreasing the crack depth strongly changes the K II values, and consequently the direction of crack extension. A 0.05 mm depth crack propagation would only require a 0.015 mm film thickness instead of a 0.03 mm film thickness for a 0.075 mm crack depth. It is also interesting to notice that for a horizontal (K II = 0) crack propagation at 0.05 mm depth, the value of K I is equal to 21.43 MPa⋅ mm 1 2 , which is lower than the silicon toughness taken here equal to K Ic = 31. 6 MPa⋅ mm 1 2 . This means that for this particular configuration, the crack will require an additional loading to propagate. Conversely, for a 0.075 mm crack depth, the value of K I is equal to 31.77 MPa⋅ mm 1 2 , which is slightly higher than silicon toughness. In this case, the crack can propagate without additional loading.

Controlling crack propagation is essential, in particular in terms of crack propagation direction stability. When the stress mismatch between the film and the substrate comes from a difference of TCE (Thermal Expansion Coefficient) during a cooling stage (as in [3 -5]), it is difficult to control the evolution of stress equilibrium because it depends directly on the temperature decrease. This induces a lack of control of stress intensity factors and consequently a dynamic crack propagation which may not be controlled properly. By working at room temperature and controlling the induced stress in the film layer and the film thickness (as in [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF]) it is much easier to avoid spontaneous fracture which can conduct to unstable crack propagation.

This fracture process aims at producing thin homogeneous fractured silicon foils. These computations show that for a target silicon foil thickness (d) and for a given silicon substrate thickness (h s ), it is possible to find a set of nickel film parameters (σ 0 , h f ) for which fracture will occur parallel to the interface, at depth d. In the examples above, we have fixed the nickel film intrinsic stress, and we have studied the influence of the nickel film thickness. The same analysis can be done to find the appropriate intrinsic stress that needs to be applied in the nickel film for a given nickel film thickness. It is important to notice here that the choice of this couple of parameters (σ 0 , h f ) will depend on the deposition technique used. We have studied here the kinking direction of a pre-existing crack depending on the geometrical configuration. In the next section, the T-stress is analysed in order to check the crack propagation stability.

Numerical study of T-stress depending on the crack length

As initially showed by Cotterell and Rice [START_REF] Cotterell | Slightly curved or kinked cracks[END_REF], the T-stress is a good indicator of the stability of the crack propagation direction. If the T-stress is positive, the crack path is unstable, and may fluctuate around a straight trajectory under the influence of any defects or heterogeneities in the system. If the T-stress is negative, the crack path will keep following its straight trajectory at the depth corresponding to K II =0. This crack path stability must not be confused with the crack propagation stability, which is based on the comparison between the strain energy release rate, G, and the G-R curve. In [START_REF] Xu | Crack interaction and propagation-stability in a thin film/substrate system[END_REF], Xu and Blume found a positive value of the T-stress for a crack propagating in a brittle substrate with an adherent tensile film on top. They made the assumption that the sign of the T-stress may depend on the crack length. In order to study the T-stress, we chose the configuration given in the previous section for a crack depth d = 0.05 mm, and with a nickel film thickness h f = 0.015 mm. The intrinsic stress in the nickel film is equal to 380 MPa. This configuration is close to the one experimentally tested by Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF]. The T-stress is computed for 5 values of initial crack length, so that the ratio a/d ranges from 0.2 to 16.

Figure 6 shows the influence of the crack length on a

K I π σ 0 , a K II π σ 0 and 0 σ T .
Each of these values converges as the crack length increases. As indicated in [START_REF] Xu | Crack interaction and propagation-stability in a thin film/substrate system[END_REF], the value of the T-stress is positive, which should induce an unstable crack path. When the ratio a/d tends to 0, the Tstress becomes negative.

When a/d tends to 0 the local stress field becomes similar to the one which would be obtained for a SEC (Single Edge Crack) specimen with a short crack length compared to the specimen dimensions. For a SEC specimen submitted to a stress σ, K I is approximately equal

to a K I π σ 12 . 1 =
. In the same way T can be written as a function of the applied stress for a SEC specimen. Based on Harlin and Willis work [START_REF] Harlin | The influence of crack size on the ductile-brittle transition[END_REF], Hauf et al. [START_REF] Hauf | A modified effective crack length formulation in elastic-plastic fracture mechanics[END_REF] and Wang [START_REF] Wang | A two-parameter characterization of elastic-plastic crack tip fields and application to cleavage fracture[END_REF] showed that for a SEC specimen, when a/w tends to 0 (where w is the SEC width), the T-stress tends to -0.51σ. In our configuration, the applied stress Σ v (d) is the vertical stress in Silicon substrate without any pre-crack and at a given depth d . For d = 0.05 mm, Σ v (d)= 95 MPa.

Consequently, for short cracks (a/d→0), the ratios 0 σ T and a

K I π σ 0 should tend towards: ( ) ( ) ( ) ( ) 128 . 0 51 . 0 . 28 . 0 12 . 1 0 0 0 0 0 0 0 - ≈ Σ - ≈ Σ Σ = ≈ Σ ≈ → → σ σ σ σ π σ d d d T T d a K v v v d a v d a I (5)
These values are in good agreement with Figure 6 when a/d→0.

In [START_REF] Xu | Crack interaction and propagation-stability in a thin film/substrate system[END_REF], Xu and Blume plotted the T-stress of the steady-state crack with respect to Dundurs' parameter α. For a value of α = 0.19 they found that the ratio T/σ 0 is approximately equal to 0.11. This value is also in good agreement with the value of T/σ 0 for long cracks in Figure 6 which is equal to 0.114.

As assumed in [START_REF] Xu | Crack interaction and propagation-stability in a thin film/substrate system[END_REF], the T-stress is negative for very short cracks (stable crack path) but becomes positive (unstable crack path) when the ratio a/d exceeds a critical value around 0.6. This unstable crack path is not consistent with Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] experimental results, where a thin homogeneous silicon foil is obtained after peeling. At this stage, two main assumptions can be formulated to explain these results:

-Anisotropic fracture toughness: Cotterell and Rice [START_REF] Cotterell | Slightly curved or kinked cracks[END_REF] analysis, obtained under isotropic assumptions, was extended by Gao and Chiu [START_REF] Gao | Slightly curved or kinked cracks in anisotropic elastic solids[END_REF] for anisotropic materials. Gao and Chiu found the same influence of the T-stress sign on the crack path stability, but their demonstration was made under the assumption of a material who has a uniform fracture toughness, which is not the case for mono silicon. For mono silicon, the anisotropy in terms of fracture toughness may have a stabilization influence. If the crack slightly deviates from its straight path, the anisotropy in terms of fracture toughness may prevent the crack from kinking and stabilize it in the K II =0 direction.

-Peeling process: Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] thin foils were obtained after peeling using a flexible handle layer. This peeling process may have a double influence, on the stability of the fracture process and on the crack path stability of the crack when it propagates. As shown in Figure 6, K I remains lower than K Ic for each configuration, meaning that the system will require additional energy for crack propagation. An additional load is indeed applied in [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] to perform the spalling in a controlled manner. A flexible handle layer is applied on the top of the nickel film. Spalling is performed by pulling on this flexible layer, which induces more energy in the system. If this additional energy is too low, K I remains lower than K Ic and no propagation occurs. If this additional energy is too high, the crack propagation may be unstable, meaning that the crack propagates until complete failure without any additional force applied. By controlling the peeling process, it is possible to induce the right amount of energy to allow the crack to propagate on a given length at each peeling step. This additional loading may also influence the T-stress, and thus the crack path stability. In particular because the x position of the loading achieved during peeling is close to the x position of the crack tip.

To understand the influence of this peeling stage on stress intensity factors and T-stress, a new set of computations were carried out, using the same configuration with an initial precrack of a = 0.4 mm length at a depth d = 0.05 mm. Substrate silicon and nickel film thicknesses are respectively equal to h s = 10 mm and h f = 0.015 mm.

The Abaqus computation is performed in two steps. During the first step, an initial tensile intrinsic stress σ 0 = 380 MPa is applied in the nickel film and the stress relaxation is computed. During the second step, a force is applied to model the peeling process. This loading condition is idealized here by a concentrated force applied on the top of the nickel layer at a position x equals to the crack tip position as shown on Figure 7.a. F y is fixed to 100 N and we study the influence of F x on stress intensity factors (Figure 7.b) and T-stress (Figure 7.c). Applying such a peeling force does not change the crack propagation direction which remains equal to 0° because of the small values of K II compared to K I . The peeling force increases K I to a value higher than K Ic . For horizontal forces (F x ) lower than the half of the applied vertical force (F y ) Figure 7.c shows that the T-stress also becomes negative, meaning a directionally stable crack propagation. In this case, peeling with an additional force enables crack propagation (K I > K Ic ), and the crack would propagate horizontally, with a stable crack propagation direction. However, it must be noted that the boundary conditions used for peeling in these simulations are idealized. For an horizontal force F x higher than half of the applied vertical force F y , or for a force distributed on the top nickel layer, the T-stress remains positive. Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] do not mention such unstable crack propagation direction. The peeling process is made manually and its influence on crack propagation stability is not discussed.

We also should note that the 3-d situation of a round silicon crystal means that the situation in Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] peeling may be different still, and mono silicon fracture mechanics based on anisotropic elasticity becomes more relevant.

Conclusion

Controlled spalling of Silicon foils is a promising technique, which enables to obtain very thin silicon foils without kerf-loss. This process is extremely interesting in terms of cost production since the substrate can be re-used after each spalling. However, controlling the process remains the main issue. If experimental feasibility can be found in the literature [START_REF] Fr | Stress-induced large-area lift-off of crystalline Si films[END_REF][START_REF] Fr | Stress-Induced Lift-Off Method for kerf-loss-free wafering of ultra-thin crystalline Si wafers[END_REF][START_REF] Gordon | Three novel ways of making thin-film crystalline-silicon layers on glass for solar cell applications[END_REF][START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF], no detailed fracture mechanics analysis has been published to understand the process and exhibit the more influential geometrical and mechanical parameters. In this paper, the spalling process of silicon was analysed using a numerical investigation of stress intensity factors and T-stress.

The analysis shown that the model is able to predict an horizontal crack propagation parallel to the film/substrate interface for specific geometrical conditions. For a given target silicon layer thickness, the model shows that it is possible to find a couple of film parameters (film thickness h f and film intrinsic stress σ 0 ) to obtain a straight horizontal crack propagation. The thickness of the deposited film depends both on the Dundurs parameters, and on the target thickness silicon layer. The issue, then, is to be able to get the right amount of intrinsic stress in the film for this thickness so that the system is almost ready to spall. We also showed that the silicon substrate thickness may influence SIF. This means that silicon thickness has to be accounted for when defining the stress and thickness of the stressinducing layer. In addition, the homogeneity of this layer can also play a role, and any defects in the layer may disturb the crack path. An analysis of the influence of defects in the film on crack propagation and stability can be found in [START_REF] Xu | Crack interaction and propagation-stability in a thin film/substrate system[END_REF].

The T-stress was analysed in order to study the stability of crack propagation. The T-stress is positive and converges towards a constant value for long cracks, whereas it is negative for small cracks. This means that the crack propagation direction may be unstable for long cracks. However, this positive value is obtained together with a low value of K I , lower than the silicon toughness. Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] used a peeling method with a flexible adhesion layer on top of the nickel film to achieve complete fracture. According to Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF], this peeling process enables to propagate the crack in the Silicon in a controlled manner. It may also have a positive influence on the crack path stability by decreasing the T-stress to a negative value. The peeling stage was modelled here with a simple concentrated force. We have shown that this additional force was able to increase K I to values higher than K Ic and to decrease the Tstress to a negative value. This implies a directionally stable crack propagation in the silicon substrate. However, peeling forces have to be judiciously chosen in order to get these conditions (K I >K Ic and T<0), whereas peeling conditions are not described in [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF].

Further investigations have to be made to improve the control of the process. A 3D analysis of the system would be interesting to study the influence of the out-of-plane direction on the fracture process. In Bedell et al. [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] the contact area between silicon substrate and stressinducing film is circular whereas it is rectangular in Dross et al. [START_REF] Fr | Stress-induced large-area lift-off of crystalline Si films[END_REF] study. This may have a stabilizing impact on the crack propagation direction.

Simulations accounting for anisotropic mechanical properties and toughness of mono silicon will also have to be carried out. The mono silicon crystal orientation seems to play a role on the stability of crack propagation when the stress-inducing layer is obtained by a mismatch of TCE during cooling [START_REF] Fr | Stress-induced large-area lift-off of crystalline Si films[END_REF][START_REF] Fr | Stress-Induced Lift-Off Method for kerf-loss-free wafering of ultra-thin crystalline Si wafers[END_REF][START_REF] Gordon | Three novel ways of making thin-film crystalline-silicon layers on glass for solar cell applications[END_REF]. This orientation influence has not been mentioned in [START_REF] Bedell | Kerf-less removal of Si, Ge and III-Vs layers by controlled spalling to enable lowcost PV technologies[END_REF] when the fracture process occurs at near room temperature. Some preliminary anisotropic computations showed that accounting for mono silicon anisotropic properties has minor effects on K I but may change the optimal nickel film thickness (for a given tensile stress in the nickel film) of a few percent to get a straight ahead crack propagation at a target depth.

Finally, a dynamic analysis of the fracture process in mono silicon has to be done to investigate further the evolution of the crack path and its stability regarding thermomechanical loading conditions and mono silicon orientation [START_REF] Deegan | Wavy and rough cracks in silicon[END_REF][START_REF] Cramer | Energy dissipation and path instabilities in dynamic fracture of silicon single crystals[END_REF][START_REF] Sherman | I Be'ery, From crack deflection to lattice vibrations -macro to atomistic examination of dynamic cleavage fracture[END_REF][START_REF] Sherman | Macroscopic and microscopic examination of the relationship between crack velocity and path and Rayleigh surface wave speed in single crystal silicon[END_REF].

Figure 1 .

 1 Figure 1. Edge loading

Figure 2 .

 2 Figure 2. a) 3D Geometry of the silicon substrate with a tensile nickel layer deposited on top, b) 2D plane strain configuration, c) pre-crack geometry.

.

  Figure 3.a shows the initial stress state, in which a uniform tensile stress of 380 MPa is applied to the film thickness whereas the substrate is stress-free. Figure3.b shows the final von Mises stress field once the lateral surface traction in the film is relaxed to zero. Significant stress redistribution occurs in the top-left composite beam structure, resulting in stress concentration at the crack tip. A neutral axis also appears in the silicon portion of the laminated beam structure above the crack. Figures 3.c, 3.d, 3.e and 3.f

Figure 4 .

 4 Figure 4.a shows the evolution of K I σ 0 π ⋅ a in red (right axis) and K II σ 0 π ⋅ a in blue (left axis).Figure 4.b represents the kinking direction (in degrees), based on the K II =0 criterion. For both figures, plain curves correspond a silicon substrate thickness h s = 10 mm and dashed curves to h s = 1 mm.

Figure 4 .

 4 b represents the kinking direction (in degrees), based on the K II =0 criterion. For both figures, plain curves correspond a silicon substrate thickness h s = 10 mm and dashed curves to h s = 1 mm.

Figure 3 .

 3 Figure 3. a) Initial stress state, b) von Mises final stress state, c) σ σ σ σ 11 stress field at the crack tip, d) σ σ σ σ 22 stress field at the crack tip, e) σ σ σ σ 12 stress field at the crack tip and f) σ σ σ σ 33 stress field at the crack tip. Configuration h f /d = 0.8 and a/d = 5.3.

Figure 4 . 4 . 2 .

 442 Figure 4. a) K I σ 0 π ⋅ a and K II σ 0 π ⋅ a and b) kinking direction (in degrees) as a function of the nickel film thickness for an initial fixed crack length a = 0.4 mm and for two different silicon substrate thicknesses.

Figure 5 .Figure 5

 55 Figure 5.a shows the evolution of K I σ 0 π ⋅ a in red (right axis) and K II σ 0 π ⋅ a in blue (left axis).Figure 5.b represents the kinking direction (in degrees), based on the K II =0 criterion. For both figures, plain curves correspond to a crack depth d = 0.075 mm and dashed curves to d = 0.05 mm.

  075 mm -KI/Sigma0.Sqrt(Pi.a) d = 0.05 mm -KI/Sigma0.Sqrt(Pi.a) d = 0.075 mm -KII/Sigma0.Sqrt(Pi.a) d = 0.05 mm -KII/Sigma0.Sqrt(Pi.a)

Figure 6 .

 6 Figure 6. K I σ 0 π ⋅ a, K II σ 0 π ⋅ a and

Figure 7 .

 7 Figure 7. a) Simplified loading for the peeling stage and Influence of the horizontal force on b) stress intensity factors and c) T-stress

  Si , from 0.048 to 0.40, depending on the orientation of uniaxial tensile loading. Silicon also exhibits modest anisotropy of fracture properties. Depending on the orientation of crack loading and extension, mono silicon's fracture toughness, K Ic , ranges from 19 to 41 MPa⋅ mm1 2

	its Poisson's ratio, ν
		a)		b)			c)
	h f h s h f h s	Monocrystalline Silicon Substrate Ni layer Monocrystalline Silicon Substrate Ni layer	t s t s	h f h s h f h s	l s /2 MonoSi substrate Ni layer l s /2 MonoSi substrate Ni layer	Symmetry plane Symmetry plane	a a	d d
		l s l s

Its effective Young's modulus, E Si , ranges from 130 GPa to 188 GPa, and

Acknowledgements: this work was done within the European project SUGAR funded by the EU's 7th framework program for ICT. The authors are very grateful to IMEC for the coordination of the project and for interesting discussions related to the spalling process.


Marek Laban
email: laban@micronic.sk

Milos Drutarovsky
email: milos.drutarovsky@tuke.sk

Viktor Fischer
email: fischer@univ-st-etienne.fr

Michal Varchola
email: varchola@micronic.sk

Modular Evaluation Platform for Evaluation and Testing of Physically Unclonable Functions

Physical unclonable functions in field programmable arrays are always linked to the used hardware. Therefore, it is necessary to have high amount of simple devices for evaluation purposes. One of the suitable platform for such evaluation is HECTOR Evaluation Platform. The following paper describes this platform, compares it with existing solutions, and shows several examples of its using. The proposed platform consists of a motherboard and exchangeable daughter board modules. These are designed to be as simple as possible to allow cheap and independent evaluation across many devices. In comparison to similar existing solutions, proposed platform excels in its simple architecture, which allows remote using of module. The platform is also suitable for evaluation of other cryptographic primitives like true random number generators, encryption systems, and etc. Platform's components are adjusted for side channel attacks measurements.

HECTOR evaluation platform was designed and optimized to fulfil the European HECTOR project (H2020) requirements.

I. INTRODUCTION

These days information appears mostly in a digital form. An electronic mail is used more often than a traditional mail, documents are stored in a digital form more than on a paper and information is often very expensive. Therefore, cryptography has become increasingly important to ensure data security.

Cryptography applies mathematical methods to ensure information security requirements such as data confidentiality, integrity, and authentication, but also authentication of devices and subjects [START_REF] Menezes | Handbook of Applied Cryptography[END_REF]. It uses cryptographic primitives to build cryptographic protocols. Cryptographic primitives like Physical Unclonable Functions (PUFs) and Random Number Generators (RNGs) extract randomness from the underlying hardware [START_REF] Laban | Low-cost ARM Cortex-M0 Based TRNG for IoT Applications[END_REF]. Although other cryptographic primitives like symmetric-or asymmetric-key ciphers, and one way functions are deterministic, their implementation in hardware can leak confidential information and it is therefore hardware dependent, too.

A. Physically Unclonable Functions and Their Evaluation

There are many human attributes like fingerprint, DNA or human's dentition for unique and unpredictable person identification. Similarly, electronic device can be identified using a PUF. Its principle is based on an exploitation of Manufacturing Process Variation (MPV), in order to generate a binary number specific for various devices. The definition given in [START_REF] Ch | Physical Unclonable Functions in Theory and Practice[END_REF] defines PUF as a physical entity which produces an output value at least in dependence of physical structures which are hard to clone. PUFs can be used to authenticate hardware or to generate hardware dependent confidential keys [4], [START_REF] Paral | Reliable and Efficient PUF-Based Key Generation Using Pattern Matching[END_REF].

As with the other cryptographic primitives, PUF should meet the recommendations and criteria defined in a standard. However, such standard is just arisen. Its name is Security Requirements and Test Methods for Physically Unclonable Functions for Generating Non-Stored Security Parameters, marked as ISO/IEC NP 20897 [START_REF]International Organization for Standardization Security requirements, test and evaluation methods for physically unclonable functions for generating nonstored security parameters[END_REF]. The standardization process began in 2015.

Since every PUF is based on MPV, its output should differ from device to device. In order to properly evaluate PUF, it is necessary to test given PUF on many devices. In addition, temperature or voltage deviations have a big influence to the PUF's output and they need to be evaluated too.

B. HECTOR Project

In the framework of the information security politics of the European Union, a project called HECTOR (Hardware Enabled Crypto and Randomness) was recently accepted for funding [START_REF]HECTOR project web page[END_REF]. HECTOR is a European cooperative research project. The project emerged from the scientific cooperation of several partners. The main objective of this project is to close the gap between basic algorithmic approaches and hardwarelevel security implementations. The project task is to study, design and implement RNGs and PUFs with demonstrable entropy guarantees and quality metrics. This includes on-thefly entropy estimation and evaluation of robustness against physical attacks, which is needed in the security evaluation and certification process.

It requires to evaluate in a fair way many hardware dependent cryptographic primitives (RNGs, PUFs, authenticated encryption algorithms), in many different technologies. A flexible platform for testing and evaluation of primitives implemented on various Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) devices was therefore needed. According to minimal production costs and influence of environmental conditions, such platform should be very simple and carefully designed.

II. HECTOR EVALUATION PLATFORM

In the framework of the HECTOR project, HECTOR Evaluation Platform was arisen. The main motivation for designing of the platform was to design the modular hardware, which would be optimized for a thorough, but still easy evaluation of cryptographic primitives implemented in FPGA and ASIC devices. The platform consists of a motherboard and several types of interchangeable daughter boards. Evaluated cryptographic primitives are implemented in daughter board with hardware resources significantly reduced. Data are stored, processed, and transmitted to a PC using the motherboard featuring large choice of peripherals and interfaces. The daughter board can be connected to the motherboard remotely and can be thus placed in a hostile environment during attacks.

A. Daughter Board

The HECTOR daughter board modules are designed to allow evaluation of primitives across different FPGA families and ASICs. The selected architecture has two main advantages. First, the daughter modules contain only the necessary hardware components, which minimize their impact on the behaviour of the target primitive. Second, the module is simple and thus cheaper, i.e. a huge number of modules can be manufactured to test PUFs.

In the framework of the project four types of daughter modules were designed featuring Altera Cyclone V, Xilinx Spartan-6, Microsemi SmartFusion2 FPGA (see Fig. 1), and another one featuring a custom ASIC. Selected devices represent recent FPGA families of main FPGA vendors.

The daughter modules are connected to the motherboard using a SATA connector. It is used to power the board and to transfer data between the daughter board and the motherboard. The SATA connector is used mainly for its good signal integrity and mechanical features. The SATA interface protocol is not supported by the hardware. Instead, four LVDS (Low Voltage Differential Signaling) signal couples, three single ended wires and power supply voltages are present on the connector. The daughter boards contain high quality power filters. To reduce the cost and the electric noise, and to increase board's reliability, all power regulators are placed on the motherboard.

B. Motherboard

The main task of the motherboard is to control daughter modules, to read and eventually to process data from the modules and to ensure data transfers to the PC. The board uses USB interface to communicate with the PC and a variety of connectors for plugging in different daughter modules (see Fig. 2). The communication between the motherboard and the host PC is ensured via USB by two data channels. The first one, the virtual COM port, is designed to exchange the control and status packets using a simple UART protocol. It utilizes FTDI device supported by many operating systems. The second channel is designed to provide reliable high-speed data transfers using the USB mass storage class interface, which is natively supported by operation systems.

The motherboard is powered by an external power supply. In order to reduce the cost of daughter boards, the boards are powered from dedicated voltage regulators, which are placed Fig. 1: HECTOR daughter boards featuring Xilinx Spartan 6, Microsemi SmartFusion2, and Altera Cyclone V. on the motherboard. Three of them are user-configurable by micro switches. The configurable regulators ensure compatibility across various daughter boards, which usually require different power supplies (e.g. the power voltage of the FPGA core may be different). The whole set of power supplies is properly filtered to minimize interference and noise. Only linear regulators are used on the board due to their low noise compared to noisy switching regulators. This low noise feature is very important for fair TRNG and PUF evaluation, as well as for evaluation of robustness against side channel attacks.

The motherboard provides three connectors for connecting of modules:

• High-Definition Multimedia Interface (HDMI) connector,

• Serial-ATA (SATA) connector,

• Zero Insertion Force (ZIF) connector.

The daughter boards can be plugged directly into the motherboard using the SATA connector or remotely using a common HDMI cable with a custom HDMI to SATA adapter.

The SATA connector ensures easy, reliable, low cost and low noise connection. An optional aluminium lid can be used to protect the daughter board from surrounding electro-magnetic fields, if necessary.

Connection of the daughter board via the HDMI cable can be useful when the tested device should be placed in a temperature controlled chamber or a Faraday cage. To make the connection easier, the same data signals are presented on the both SATA and HDMI connectors. However, in the case of a remote use of daughter boards, the power must be provided from an external power source connected to the available HDMI to SATA adapter.

ZIF connector, which is available on the motherboard is dedicated to expansion boards, e.g. boards with switches and LEDs.

III. CONFIGURATION OF THE SYSTEM AND REFERENCE DESIGNS

A set of tools is provided in several reference designs: the user applications running on the PC, and the motherboard hardware and firmware adapted to various user applications placed in daughter boards [START_REF] Laban | Development tools for evaluation of cryptographic primitives implemented in reconfigurable hardware[END_REF].

The proposed software tools and configuration of the system vary depending on the application. For the sake of place, we will briefly present only the one example of a PUF implementation in Section III-C. However the platform is also suitable for evaluation of any other cryptographic primitives like TRNG, symmetric or asymmetric key cryptography, as well as Side Channel Attacks (SCAs) on some primitives.

A. PC Application Software

The main task of the PC application software is to provide the user API to the motherboard via USB interface. It uses a virtual COM port to transfer the commands and the state words and a USB mass storage interface to transfer data. Created data files can be accessed directly from the host PC.

To ensure flexibility and system independence, the software running on the PC is developed in a TCL language. Only a TCL interpreter is needed to read user scripts. The TCL interpreter is usually installed during the FPGA design software installation (e.g. Quartus or Libero). The script can be very easily edited and adapted to user requirements.

B. Motherboard Firmware and Hardware

The motherboard firmware runs on the microcontroller subsystem inside the FPGA device. The components of the platform are depicted in Fig. 4. The microcrontroller sybsystem part has the following roles: • Control of the device under test by sending commands to the FPGA fabric, • Maintenance of the file-system for data transfers (files can have up to 30 MB).

The main role of the Packetizer-Depacketizer block is to maintain a communication protocol based on transferring small packets via UART.

The USB mass storage class disk drive provides access to file-system located in the the first half of the external RAM. It behaves like a common USB flash drive connected to the PC, if it is activated. The second half of the RAM is used as a cache reserved for data acquisitions.

A Communication Control block contains several predefined functions, which manage operations in the FPGA and reply to received packets. These functions (instructions) are called by packets received from the PC.

Microcontroller communicates with FPGA using a several registers. These registers are used for controlling of the input/output pins, exchanging of the device state, and entering of some commands.

One of the registers is command register. It controls Command Execution State Machine implemented in the FPGA fabric. There are defined commands for selecting of the daughter board's connector, starting of the data acquisition, and etc. Serial Synchronous Interface (SSI) utilizes three signal wires for an easy data exchange between the host PC and the daughter board. It can be used for transferring of daughter board's state, or for controlling of the daughter board.

C. PUF Reference Design

We use Ring Oscillator (RO) PUF proposed by Kodytek et al. in [START_REF] Kodytek | A design of ring oscillator based PUF on FPGA[END_REF] as an example of HECTOR Evaluation Platform using. Proposed principle selects two ROs and counts theirs oscillations using two 16-bit counters. When one of the counters overflows value of the second one is recorded. Several selected bits from the recorded counter are extracted and used as response of the PUF function.

In our example, Kodytek PUF function is located in the daughter board, where the function is controlled by PUF Control Unit (see Fig. 5). PUF Control Unit selects RO pairs, sets the number of measurement repetitions, starts the PUF response generation and reports a daughter board status. Daughter board's statuses and commands are transferred to/from daughter board using SSI.

If one of the counters overflows, then the 16-bit value of the second one is always serialized and transferred to the motherboard via a fast serial interface. The interface uses three signals: Data, Strb, Sync. Serial data are shifted into the motherboard, where the 16-bit word is reconstructed and recorded to the external RAM. At the end of the data acquisition, recorded 16-bit words are available for the host PC as the file in the mass storage class device.

Multiplexers in the motherboard allow to connect the board either directly to the SATA connector, or via HDMI cable and an SATA to HDMI adapter.

The data acquisition is initialized and controlled by the host PC, which executes the TCL scripts. The scripts consist of the instructions, which reset the daughter board, create file-system on motherboard, start the acquisition, configure PUF Control Unit and etc. The proposed example simplifies the evaluation of the bit selection. The interface for acquisition is very fast and allows to record the data stream up to 30 MB. The PUF can be easily controlled and adjusted via SSI interface.

D. PUF Measurement Example

The main advantage of HECTOR Evaluation Platform is its independent measurement methods. It was mentioned earlier, that PUF functions are very sensitive to environmental changes like temperature or voltage. Therefore, it is necessary to test these changes. At the same time, the evaluator must be sure, that the environmental changes (e.g. high temperature) affect just the target device and not any devices which process data. Thanks to HECTOR Evaluation Platform, the target devicedaughter board, and processing device -motherboard can be independently connected using a HDMI cable. Fig. 6 shows an example of the laboratory measurement. Daughter board is placed into the temperature chamber. Data are transferred to the motherboard via the HDMI cable. Daughter board is powered from an independent laboratory power supply, where several power lanes are connected (core power, input/output pins power, and etc.). Since there are no voltage regulators on the daughter board, every FPGA power lane can be easily changed. Thanks to the control of laboratory power supply and temperature chamber from the host PC, measurement process can be automatized.

Host

If it is necessary to test response of many devices, several daughter boards can be placed into the chamber. They would be connected by several HDMI cables, but just one cable could be connected to the motherboard at one time. Alternatively they can be easily interchanged and tested via SATA connector (outside the chamber).

IV. STATE OF THE ART

The hardware dedicated to the evaluation of cryptographic primitives must fulfill special requirements, especially from the point of view of electric noises, electro-magnetic interference, and robustness of the design. Several solutions are currently available.

The Research Center for Information Security (RCIS) of AIST and Tohoku University developed the Side-channel Attack Standard Evaluation BOard (SASEBO) [START_REF]Side-Channel Attack Standard Evaluation Board SASEBO[END_REF] as a research project funded by METI (Ministry of Economy, Trade and Industry, Japan). Several SASEBO boards aimed at evaluation of cryptographic functions implemented in FPGAs, ASICs, and Smartcards are available. The boards were designed essentially as platforms for evaluation of the SCAs. They contain mostly two FPGAs: one as a Target of Evaluation (ToE), and the second one, which controls the target. Unfortunately, the platform is not modular, because both devices are located on the same board. Therefore the ToE cannot be separated and placed remotely in a hostile environment. The second disadvantage of the SASEBO boards in the context of the HECTOR project is, that only a limited choice of FPGA devices is available. This argument is valid also for SAKURA boards, which are successors of the SASEBO boards. Last but not least, the SASEBO (and SAKURA) boards are complex and thus expensive and consequently, not suitable for evaluation of PUFs, where a large amount of devices must be tested.

Another platform, a Flexible Open-source BOard for Sidechannel analysis (FOBOS) [START_REF] Velegalati | Kaps Towards a Flexible, Opensource BOard for Side-channel analysis (FOBOS)[END_REF] was designed by the George Mason University for conducting side-channel attacks on FPGAs. The platform consists of two different boards, one is used as a control board and another one as a Device Under Test (DUT). Both cards are connected together by a module, which is called a bridge connector. The advantage of this platform is that it uses commercially available boards -it is therefore cheaper. But the use of the commercially available general purpose evaluation boards is also the main disadvantage of this solution. These boards are not intended for SCA evaluation purposes, they contain many redundant components and switching power supplies generating significant electronic noise. In addition, various bridge connectors and communication interfaces are needed for different types of DUTs.

Evariste III [START_REF] Hubert | Evariste wiki page[END_REF] is a platform aimed at development and evaluation of cryptographic functions and primitives in reconfigurable hardware. The platform was developed by the Jean Monnet University in cooperation with the MICRONIC company. It is a modular platform containing daughter boards (featuring target FPGAs or ASICs) and a motherboard containing USB data interface device. Three daughter boards designed for Evariste III and several other daughter boards designed for older platform Evariste II are available. The Evariste III modules contain connectors for SCA measurements. The main disadvantage of the Evariste III (and the Evariste II) system is that the modules cannot be used remotely, and that they are relatively expensive since they contain power supplies. Last but not least, a large high-speed external RAM memory, which is needed for high-speed data acquisition, is available only on few daughter boards (which are thus more expensive).

V. CONCLUSION HECTOR evaluation platform was designed following the project requirements and it reflects the needs of all HECTOR partners. It is a little bit difficult to compare modularity or performance of the existing similar platforms, because every platform has a slightly different architecture. SASEBO and FOBOS boards are aimed mainly at SCAs. Evariste III is the successful predecessor of HECTOR evaluation platform. Nevertheless, the new proposed platform differs and excels from SASEBO, FOBOS, and Evariste III platforms in the following points:

• Motherboard features large 64 MB RAM memory, which is necessary for acquisition of long continuous data streams (e.g. data from TRNG). • The number of components on the daughter board module is limited to a strict minimum. It reduces price of the modules. This is particularly useful, if huge number of devices are needed for PUF evaluation. At the same time it minimizes undesirable effects on the ToE.

• The daughter board can be placed remotely in a hostile environment. Thanks to the HDMI cable connection daughter board can be placed into some chamber.

The separation minimizes undesirable influence to the measurement equipment and some active attacks can be performed.

• Every daughter board have the same communication interface and connector. Just like Evariste III, different types of daughter boards with the same implemented primitive do not require change of the motherboard implementation or its hardware. HECTOR Evaluation Platform is a unique and powerful tool set particularly suitable for testing and evaluation of cryptographic primitives as well as SCAs. However, the platform is sufficiently flexible to be adapted to a variety of the other applications.

Proposed hardware and software means will be used for development and testing of new PUFs. All the IP functions and software tools from the example are open-source. According to the HECTOR consortium agreement, the HECTOR evaluation boards can be used by third parties for an educational dissemination purposes.

Fig. 2 :

 2 Fig. 2: Motherboard hardware block diagram.

Fig. 3 :

 3 Fig. 3: Layout of the HECTOR motherboard featuring the SmartFusion2 FPGA device.

Fig. 4 :

 4 Fig. 4: Block diagram of SmartFusion2 internal system.

Fig. 5 :

 5 Fig. 5: Example of PUF implementation in Hector Evaluation Platform.

Fig. 6 :

 6 Fig. 6: Example of laboratory measurement configuration.

ACKNOWLEDGMENT

This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 644052. This work was also supported by the Slovak Research and Development Agency under the contract No. APVV-15-0692.