ADC Analog to Digital Converter

Keywords:

The Cascaded Integrator Comb filters (CIC) find many applications in recent electronic devices such as frequency selection functions in a digital radio or modem and any filter structure that is required to efficiently process large sample rate factor. These filters are normally located after the sigma delta modulator and have regular structure. These types of filters do not require multipliers and the coefficient storage unlike in the normal digital FIR and IIR filters because of all filter coefficients are unity. Hence, it can be efficiently implemented to operate at high speed. Hence, this book describes the Very Large Scale Integration (VLSI) implementation of the CIC filters that are suitable for high performance audio applications. A total of five cascaded integrators and comb pairs were chosen to meet the design requirement, particularly the effect of signal aliasing to increase the performance. The CIC filter makes use of pipeline architecture that consists of fast adders. The proposed filter was designed and implemented and from FPGA implementation and Xilinx ISE synthesis result shows that the filter can perform at the maximum frequency of 189MHz, which is required for high performance audio applications. For area and power consumption, the CIC filter was optimized in ASIC under SilTerra 0.18 m  and MIMOS 0.35 m  technologies file. The layout was performed by the 0.18 m  technology.

The research work proposes the design and implementation of high-speed and low power of a class of filters known as Cascaded Integrator Comb filters (CIC). To achieve the above objectives, the pipelined architecture and fast adders were incorporated into the design. The filters were designed using Verilog hardware description language (Verilog HDL) and were implemented on the field programmable gate array (FPGA) to test the functionality of the design.

BACKGROUND

In many audio systems such as the HiFi compact disc (CD), digital audio tape (DAT) and speech processing make use of analog to digital converters (ADC) like sigma delta modulator (∑Δ), [START_REF] Crochiere | Multirate Digital Signal Processing[END_REF][START_REF] Vaidyanathan | Multirate Systems and Filter Banks[END_REF][START_REF] Rabii | A 1.8-V digital-audio Σ∆ modulator in 0.8-mm CMOS[END_REF][START_REF] Peluso | A 900-mV low-power Σ∆ A/D converter with 77 dB dynamic range[END_REF][START_REF] Dessouky | A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping[END_REF], successive approximation register (SAR), [START_REF] Mortezapour | A 1-V, 8-Bit successive approximation ADC in standard CMOS process[END_REF][START_REF] Fayomi | A 1-V 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0[END_REF][START_REF] Ginsburg | An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[END_REF], pipeline ADC [START_REF] Li | A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique[END_REF][START_REF] Lin | A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-mm CMOS[END_REF][START_REF] Waltari | 1.0-Volt, 9-bit Pipelined CMOS ADC[END_REF][START_REF] Chiu | A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR[END_REF]) and re-circulating ADC [START_REF] Song | A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter[END_REF]Onodera et al. 1998) in their operations. Among the modulators mentioned above the sigma delta modulator is considered the best choice for audio process due to the high resolution obtained. ∑Δ modulator is an oversampled modulation technique which provides high resolution sample output in contrast to the standard Nyquist sampling technique.

To obtain the high resolution conversion, it is necessary to have high order sigma delta modulator. However this is not acceptable because of the high cost of implementation and the instability. To overcome this problem, the integration of high order decimation filters and the sigma delta modulator can be used. Thus the CIC filter is cascaded to the sigma delta modulator as the next stage so as to increase the resolution of the sigma delta modulator without sacrificing the area and low cost.

PROBLEM STATEMENT

In the standard design of oversampling and decimation system, two important digital signal processors are used: i) the sigma delta modulator and ii) the decimation low-pass filter [START_REF] Crochiere | Multirate Digital Signal Processing[END_REF][START_REF] Oppenheim | Discreet-Time Signal Processing[END_REF]. To obtain high resolution sigma delta ADC (more than 20-bit), the high order type of the modulator is required and this will produce disadvantages such as the instability. Additionally the use of digital decimation low-pass filter to cooperate with the modulator is complicated since the filter requires multiplications that result high power consumption and higher area die size. Thus the research work proposes the use of a special filter called the CIC filter which can produce high resolution and low power consumption in the sigma delta modulator due to the CIC filter does not require multiplier and the modulator can be relaxed of high computation.

In communication devices like mobile systems and wireless transceivers, low power and small device size are important issues. In transceivers, the programmable digital filter is required to select the desirable channel. This filter causes excessive of power consumption at also higher die area. Using sigma delta modulator in mobile devices is well suited because of the channel selection is carried out by decimation filter automatically. Additionally anti-aliasing low-pass filter requirements are also relaxed due to the CIC filter and oversampling. Furthermore, on FPGA chip or ASIC implementation of the CIC filters make it low cost for DSP and audio application [START_REF] Cummings | FPGA in the Soft ware Radio[END_REF][START_REF] Dick | Configurable Logic for Digital Communications: Some Signal Processing Perspectives[END_REF].

MOTIVATION

Assume that oversampling technique is required for audio applications. Hence it is necessary to achieve a minimum of 70 dB signal to noise ratio (SNR) in the conversion process. To achieve 70 dB SNR, a minimum of 12-bits converter resolution after oversampling is required. Thus the CIC filter is applied to increase resolution for 3 enhancing SNR and makes it well suited for audio application. Furthermore, the digital decimation system has been shown to reduce the power consumption due to sampling rate conversion [START_REF] Crochiere | Multirate Digital Signal Processing[END_REF]. The filter that uses this technique is expected to drive down the power consumption and thus allows the filter to operate at low voltage. Additionally, the CIC decimation filters are multirate filters (operates at different sampling frequencies) but unlike other multirate filters, the CIC filters only allow fixed-point arithmetic (Bit stream), since these filters are inherently fixed-point filters (MATLAB7 software 1994(MATLAB7 software -2006)). The fixed point CIC filters are much more efficient that is less area and relatively faster to design which can lead to cheaper products in the market.

By eliminating the zero number of multipliers, the CIC filter has the advantage of very compact architecture compared to other low-pass filters. This filter also permits the high rate of changing signal decimation or interpolation factor.

RESEARCH METHODOLOGY

From the discussion in the previous sections, the research methodology presented in the following:

1) To present the basic architecture of the fast CIC filters. The research also continues to achieve high speed CIC filter algorithm by using fast adder and pipelined structure.

2)

To perform simulation of the 3 rd order Sigma delta modulator and decimation process followed by CIC filter, associated half band filters and FIR filter to obtain desire frequency response.

3)

To conduct Verilog implementation of CIC filter with synthesizing and defining constrained for the design and test the filter with Logic Analyzer.

4)

To implement the design and download the design to Xilinx Virtex II FPGA board and test the filter with logic analyzer. The FPGA board output is compared with MATLAB simulation result.

5)

To synthesize the CIC filter in ASIC in order to power consumption and area optimization.

OBJECTIVES

The following research objectives have been applied during the course of the research to ensure a complete and quality research is carried out.

1) To design the CIC filters that have the SNR of 145 dB that can be cascaded with sigma delta modulator to give desired frequency response.

2) To optimize the architecture of the CIC filters for high-speed and low power with minimum area die size.

3) To design and to test the CIC filter implemented on FPGA board.

SCOPE OF WORK

Based on the outlined objectives above, available hardware and software resources, and the time frame allocated, this research project is narrowed down to the following scope of work.

Building on prevalent the CIC decimation filters theory and practices a new architecture and its implementation is proposed. Besides, simulation of the analogue to digital converter and designing the whole multi-stage decimation filters including the half band FIR and droop correction filters have been carried out.

The third order sigma delta modulators are the architectures being explored in recent times for use in audio applications. This work focuses on the decimation digital filters that are needed at the output of the modulators.

The aims of the project are achieve the improved CIC filters taking into consideration the power-speed trade off. In the filter implementation, we make use of both Silterra 0.18 μm technology and Mimos 0.35 μm technology. The design is also implemented on the FPGA for quick prototyping.

For this research, three methods to increase the speed of the filter are proposed whilst trying to minimizing the area and power consumption. Firstly, new algorithm based on the carry look-ahead adder (CLA) has been implemented in the CIC filter which gives for addition. Modified Carry Look-ahead Adder (MCLA) was designed and implemented with the speed of 270 MHz for 8 bit adder. Secondly, the pipeline structure of CIC filter has been considered with the use of minimum number of registers and finally truncation lead us to have low power and decreases the complexity of calculation.

The CIC filter must be able to receive digital signal from 3 rd Sigma delta modulator with low resolution and a 5 bit quantizer and decimate the signal by factor of 16 to achieve the high resolution of 25 bit. While decimation process is going on, the noise should be removed to out of band quantization noise. The SNR of CIC filter is estimated to be higher than 140 dB. The filter also provides the necessary additional aliasing rejection for the input signal as opposed to the internally generation quantization noise.

To achieve clean audio signal from sigma delta modulator, its output needs to pass through multistage decimation filters consist of low pass CIC filter, two half-band filters and droop correction filter. The next chapters will explain the design and implementation of this filter in more detail. The overall frequency response of multistage decimation filters has the pass-band frequency of 20 kHz. Among these multistage filters, the CIC filter is used as a decimator with maximum decimation ratio of 16. It also has pass-band frequency, stop-band frequency and transition band of 7 kHz, 384 kHz and 377 kHz respectively.

Finally the non-recursive filter is introduced to operate as decimator in order to high speed and low power consumption. This filter is suitable decimation filter to replace with the CIC filter when the decimation ratio and filter order are high. It is described that why the non-recursive comb filter structure is easier to implement compare to the CIC filter.

RESEARCH CONTRIBUTION

A new architecture of CIC filters that can be used in the ADC was designed and implemented. These filters with incorporated a pipeline architecture and MCLA adder as summation block can provide the speed up to 189 MHz with SNR of more than 140 dB. The estimated chip die area has been measured. which can be used as pipeline adder too. The advantage of the MCLA adder is the simple structure compared to the CLA adder especially when it is used in high number of bit. It is easy to develop in high number of bit. In next sections, the property of this adder will be explained in detail. Additionally the pipeline structure of the CIC filter is presented and implemented to improve the speed in decimation system.

Saving the power consumption is one of the key issues for designing and implementing the decimation filter. The CIC filter was tested by logic analyzer and a certain configuration circuit after its VLSI implementation. Testing by the certain configuration circuit takes the advantage of finding and selecting each part of the CIC filter which can not work properly.

CHAPTER ORGANIZATION

The work in this conveniently organized into seven chapters. The second chapter provides the review of oversampling technique, sigma delta modulator and the necessity of using decimator after sigma delta modulator. This chapter also describes brief summaries of the literature review prior to engaging the mentioned scope of work. The several topics related to this research are reviewed to give an overall picture of the background knowledge involved. The summary of the literature review is given to clarify the research rationale.

Chapter three presents the design methodologies that are employed. Besides, the application of the decimation system which the CIC filters is a part of that is described.

To clarify the decimation system, all decimator which are involved are introduced in brief. The system simulation is done by MATLAB software to verify the system properties.

Chapter four covers the principle definition of the CIC filter followed by introducing its structure in detail. The frequency analysis is done in this chapter.

Additionally the comparison between the conventional decimation filter and the CIC filter as decimator is explained. The advantages of using The CIC filter in digital circuit are described. Besides, the basic introduction of the interpolation is presented.

Chapter five focuses on realization of the CIC filter stages and its implementation. After implementing the standard CIC filter structure on FPGA board, the optimization of the filter architecture to achieve high speed and low power is presented. The new architecture of pipeline high speed CIC filter is designed and programmed to the FPGA board. The implementation is done by using Xilinx software and Synopsis tools.

The implementation and simulation result is given in chapter six. In this chapter the simulation result of overall modulator and decimation system are given by using MATLAB, Modelsim and cad tools. Frequency component evaluation is presented in this chapter. The CIC filter implementation results are shown by using Xilinx software and Synopsys tools. This filter is tested by using logic analyzer and a certain configuration digital circuit.

Chapter seven extracts the conclusions and proposes future work.

SUMMARY

In this chapter, an introduction was given on the background and motivation and objectives of the project. The need to design low order sigma delta modulator, leads us to design and implement the low power decimation filter called CIC filters. The CIC filters were proposed to reduce the sampling frequency, avoid the presence of aliasing in base band and finally to push quantization noise to out of frequency bandwidths.

Several objectives were presented and scope of project was set to achieve the desired objectives.

CHAPTER II FILTER BACKGROUND AND LITERATURE REVIEW

This chapter reviews the important DSP concepts that bridge to the full understanding of the CIC filters which is the subject of this research. The designed CIC filter could be used in the high resolution sigma delta ADC. In the sigma delta modulators, the oversampling technique is used in order to provide such a high signal to noise ratio.

This chapter starts with the principle definition of the oversampling technique to show the importance of the oversampling sigma delta modulator and continues with the necessity of the CIC filter in the system. Furthermore, the literature review of the CIC filter will be given, that leads to improving the performance of the CIC filter.

OVERSAMPLING TECHNIQUE

The audio bandwidth is the range of audio frequencies which directly influence the fidelity of a sound. The higher audio bandwidth creates the better sound fidelity. The highest practical frequency which the human ear can normally hear is typically 20 kHz or flat frequency response from 20 Hz to 20 kHz. Thus from the Nyquist criteria, in order to avoid aliasing to the original signal, the sampling rate must be at least more than 48 kHz. Every signal above Nyquist rate must be filtered by analog anti-aliasing filter. Since none of the filters are ideal, they have a finite slope as they begin attenuating frequencies which can corrupt the original audio signal. Additionally the implementation of analog anti-aliasing filters are very difficult due to sharp cut off necessary to maximize use of the available bandwidth without exceeding the Nyquist limit. Thus converting the signal into digital by using the analog to digital converter reduces the complexity of filtering significantly. It is due to using digital filter in comparison to implementation the same filter in analog.

Based on above explanation, it is good enough motivation to use oversampling technique [START_REF] Baird | A Low Oversampling Ratio 14-b 500-kHz Δ∑ ADC with a self calibrated Multibit DAC[END_REF][START_REF] King | A Nyquist-rate Delta-Sigma A/D Converter[END_REF][START_REF] Jovanovic | Oversampled A/D Conversion of Non-band limited Signal with finite rate of innovation[END_REF] Yonghong & Tenhunen 1999) to overcome aliasing in bandwidth (Figure 2.1).

Oversampling technique has immediate benefits for anti-aliasing filters. Because of making relaxed transition band requirements for anti-aliasing filters and reduced baseband quantization noise power. Oversampling means generating more samples from a waveform has already been digitally recorded. It is a technique which can be applied for signal processing or audio application. The sampling frequency significantly is much higher than twice the bandwidth. The signal is called oversampled signal if it oversampled by factor of R.

B s f f R 2  (2.1) B s f R f    2 (2.2)
Where s f is the sampling frequency, B f is the bandwidth or highest frequency of the signal.

The primary drawback is that oversampling needs the sigma delta modulator and the digital decimation filters to operate at the significantly higher clock rate [START_REF] Galton | Oversampling Parallel delta-Sigma Modulator A/D Conversion[END_REF]. Thus the requirement of using sigma delta modulator comes from utilization over sampling technique.

Figure 2.1 shows how oversampling changes the frequency response which has effect on anti-aliasing filter.

f Input -Input must be band limited prior to sampling

f S f B f Nyquist sampling S f 2 S f 3 S f 4 S f 5 ) ( * f H ) ( f H B f B S S f f f 2 (min)  f 2 s f B f Over sampling S f ) ( * f H B S f f 2  Anti-aliasing filter
Anti-aliasing filter technique was introduced in signal processing and audio application to draw out the audio data from audio devices [START_REF] Leung | The oversampling technique for analog to digital conversion. A tutorial overview[END_REF]Xueshen et. al 2000).

OVERSAMPLING SIGMA DELTA MODULATOR (∑Δ)

An early description of sigma delta modulator concept was given in a patent by [START_REF] Cutler | Transmission System Employing Quantization[END_REF] and also in 1946 [START_REF] Steele | Delta Modulation Systems[END_REF]. The name of the sigma delta modulator comes from putting the integrator (sigma) in front of the delta in structure of the modulator [START_REF] Park | Principles of Sigma-delta Modulation for Analog-to-Digital Converters[END_REF]). The Sigma-delta ADC [START_REF] Rabii | A 1.8-V digital-audio Σ∆ modulator in 0.8-mm CMOS[END_REF][START_REF] Peluso | A 900-mV low-power Σ∆ A/D converter with 77 dB dynamic range[END_REF][START_REF] Hu | A Low-Voltage 38 mW Sigma-Delta modulator dedicated to wireless signal recording applications[END_REF][START_REF] Baird | A Low Oversampling Ratio 14-b 500-kHz Δ∑ ADC with a self calibrated Multibit DAC[END_REF][START_REF] Dessouky | A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping[END_REF] is the analog-todigital converter that uses oversampling technique to produce disproportionately more quantization noise in the upper portion of their output spectrum. In this technique, the signal is codified using a time-density called bit-stream. Sigma delta modulator is particularly an attractive idea and has been successfully used in analog to digital converters in audio applications over the last two decades.

Although sigma delta concepts existed since the middle of the century, only recent advantages in VLSI technologies have made possible the appropriate handling of bit stream generated by n-bit ADC. The scheme of sigma delta modulator is simple (Candy & Benjamin 1991). The last two terms are in fact evocative of two basic principles involved in the operation of sigma delta ADC, oversampling and noise shaping that achieve high SNR in low resolution.

The first order sigma delta modulator circuit is shown in Figure 2.2. It includes a difference amplifier, an integrator, and a comparator with feedback loop that contains a 1-bit DAC.

The analogue input is fed to an integrator, whose output is fed to a quantizer.

The output of quantizer forms a subtracted feedback from the analogue input. This feedback forces the average value of the quantized signal to track the average input. The output of the modulator is a digital representation of the signal, which can be demodulated by smoothing the impulses in a low pass filter. The sigma delta is an example of pulse-density modulation [START_REF] Paramesh | Use of Sigma-delta Modulation to Control EMI from Switch-Mode Power Supplies[END_REF]. The number of pulse per unit time increases with the magnitude of the input. The sigma delta ADCs are well suited for low-frequency high resolution applications (Figure 2.3) such as for digital audio and integrated services digital network (ISDN). Extending this architecture to instrumentation and HDTV applications which require both high resolution and high bandwidth [START_REF] Baird | A Low Oversampling Ratio 14-b 500-kHz Δ∑ ADC with a self calibrated Multibit DAC[END_REF] necessitates in reducing the converters oversampling ratio (OSR) since the maximum sampling rate is limited by the IC process.

In z-domain, first order sigma delta modulator is shown in Figure 2.4. The noise

  z E
which is created by the quantizer, adds to the modulator structure.

+ - X(z) + - D/A E(z) Y(z) 1 1 1    z z Figure 2.4
First order sigma delta modulator in z-domain

The 1-bit D/A converter is assumed to be ideal and does not introduce any additional noise. In the z-domain, the output of the first-order modulator is

) ( ) 1 ( ) ( ) ( 1 1 z E z z X z z Y      (2.3)
which consists of the input, X(z), delayed by one sample period, plus a first-order high pass shaping of the additive quantizer noise, E(z).

Decreasing the over sampling ratio (OSR) of a particular sigma delta A/D converter causes a corresponding reduction in the dynamic range. This reduction in dynamic range may be compensated for by increasing the order of the modulator and/or using multibit quantization [START_REF] Sarhang-Nejed | A high-resolution Multibit Δ∑ ADC with digital correction and relaxed amplifier requirements[END_REF][START_REF] Fattaruso | Self-Calibration Techniques for a Second-Order Multibit Sigma_Delta Modulator[END_REF][START_REF] Brandt | A 50-MHz Multibit Sigma-delta for 12-b 2-MHz A/D Conversion[END_REF].

In a conventional ADC, the sine wave to the converter is sampled with the frequency of at least twice the bandwidth of the input signal in the frequency domain. (2.4)

Where N is number of bit in ADC. The noise comes from converting the continuous signal to digital discrete signal which result in the information lost. Figure 2.5 shows the spectrum of conventional ADC when input sine wave is converted to digital signal.

To improve the SNR in conventional ADC, the number of bit should be increased. However in order to decrease the noise and to enhance the conversion process the oversampling method [START_REF] Temes | A Tutorial discussion of the oversampling method for A/D and D/A conversion Circuit and Systems[END_REF][START_REF] Joseph | Analysis and Simulation of Cascaded Delta-Sigma Modulator[END_REF] is proposed. Thus according the oversampling rule, the sampling frequency is R times higher than sampling frequency:

al convention ng oversampli S S F R F  
(2.5)

Figure 2.6 shows the diagram of amplitude of signal in frequency domain after

oversampling. An FFT analysis shows that the noise floor has decreased significantly.

The signal tone is the same as before but the noise energy is spread out over the wider frequency range. The structure of the sigma delta modulator (with oversampling) has the effect of pushing the broadband noise to upper at high frequency which is outside of the range of interest as shown in Figure 2.7. Feedback loop in sigma delta modulator creates error by subtracting output with input signal. By summing the error voltage, the integrator acts as low pass filter to the input signal and high pass filter to the quantization noise [START_REF] Dunn | Measurement of Nonlinearity in High-Resolution Sigma-Delta Conversion[END_REF], thus most of the quantization noise is pushed in to higher frequencies.

Actually the oversampling has changed not the total noise power but it is distribution. Further noise reduction can be obtained by using higher order modulators. The higher order sigma delta modulator (Chao-liang & Wilson 1997;[START_REF] Ribner | A Comparison of Modulator Networks for High-Order Oversampled ∑-Δ Analog-to-Digital Converters[END_REF] If the quantizer in a first-order modulator is itself replaced by a first-order modulator, and the first-stage integrator is implemented without a delay, then the second-order modulator of Figure 2.9 is obtained.

+ - X(z) + - D/A E(z) Y(z) 1 1 1    z z 1 1 1   z + - Figure 2
.9 Second order sigma delta modulator in z-domain

The output of the second-order modulator is given by equation 2.6.

) ( ) 1 ( ) ( ) ( 2 1 1 z E z z X z z Y      (2.6)
Figure 2.10 shows the relationship between the order of sigma delta modulator and the amount of oversampling necessary to achieve a particular SNR. to perform SRC by a factor of 9/10. [START_REF] Losada | Reducing CIC filter Complexity[END_REF] have attempted to reduce the CIC filter complexity for interpolation and decimation. They described the new structure of decimation filter which is called non-recursive filters. These kinds of filters were used to avoid register bit-growth complexity. One of the difficulties in using the CIC filter is accommodating large data word growth, particularly when implementing integrators in multistage CIC filters. Thus non-recursive comb filter was introduced to overcome this problem. This method was also designed and implemented by Yonghong Gao et al. (1999). Nonrecursive comb filter is attractive when decimation ratio and filter order are high. [START_REF] Ritoniemi | A Stereo Audio Sigma-Delta A/D-Converter[END_REF] presented a stereo audio sigma-delta A/D converter followed by decimation filters for audio application. They implemented the fourth order sigma delta modulator and linear phase decimation filters. The result implementation showed the stop band attenuation of 120 dB in decimation filters, the pass band ripple less than 0.0003 dB, signal-to-noise ratio of 95 dB, power consumption of 30 mW in digital part and the die are of 4.7 mm x 5.5 mm for overall system. The design was implemented using a 1.2 m  double-poly BiCMOS process. Djadi et al. (1994) implemented CIC filters as decimator and interpolator which have programmable capability in decimation ratio from 0 to 256. The number of filter was fixed in their design. They used MOSIS 1.2 micron technology CMOSEN standard cell libraries. [START_REF] Mulpur | Faster and Better Embedded Signal Processing Systems: System-Level Design Begins to Pay-Off[END_REF] designed and explained System-Level Design (SLD) of fixed point down converter filter by the method of faster embedded signal processing system.

He implemented digital down converter (DDC) for simplified digital radio application.

The system was designed for GSM type application and it was implemented on FPGA/PLD platforms. From an SLD point of view the fixed point scaling lends itself quite well for automation so he used fixed point down converter to ensure that final implementation would be free of saturation and overflow problems.

Moreover, interpolation is widely used in D/A converter. [START_REF] Karema | A 20-Bit Sigma-Delta D/A Converter Prototype for Audio Applications[END_REF] introduced an oversampled high resolution sigma-delta D/A converter which is primary digital and suits very well for audio applications. Interpolation filter also implements as digital part using two in-house IC-chips and is very flexible due to the filters are realized by programmable filter processor. The silicon area of the chips is small and can still be reduced considerably by using modern MOS technologies.

Yonghong Gao et al. (1999) [START_REF] Grati | Relaxed Decimation filter specifications for Wireless Transceivers[END_REF] presented an optimized technique design for direct conversation wireless transceivers. They decimated the digital signal by multimode filtering structure compose of comb filters followed by a half-band and a FIR filter for both GSM and DECT standards. They tried to find the way to reduce complexity architecture. To decrease computational complexity and meet standard specifications a practical method introduced to compute filter stages relaxed specifications. [START_REF] Henker | Time-invariant CIC-filters for sample rate conversion with arbitrary rational factors[END_REF], presented time-variant implementation of CIC-filters which circumvents the high intermediate sample rate. This time-variant implementation results in a linear periodically time-variant system (LPTV) which is completely equivalent to its original linear time invariant system (LTI) consisting of the interpolator and decimator be used by analysing the LTI system, while implementation the system as an LPTV system, avoiding the high intermediate sample rates of the LTI system. Antialias and anti image filtering were principally realized in that paper and was implemented in LPTV systems.

In 2005, Dolecek and Carmona changed the structure of the CIC filter and modified it by multistage structure. This structure consists of cascaded modified CIC and cascaded cosine prefilters. The first section is realized in non recursive form and other stages were designed recursively. This structure was defined to improve magnitude response of this filter due to cosine prefilters in higher rate. This prefilter also can be shifted in lower rate.

Kei-yang [START_REF] Khoo | Efficient high-speed CIC decimation filter[END_REF] proposed an efficient architecture for the first integrator stage in a high-speed CIC filter implemented using carry save architecture.

The design is based on exploiting the carry propagation properties in a carry save accumulator. It will reduce the number of register to save power consumption. In this design a large number of full adder (FA) is replaced with half adder (HA). The result shows that the design reduces the number of registers in the integrator stages by 6.3 % to 13.5 % and replaces 18% to 42% of the FA.

Hyuk Jun [START_REF] Oh | On the Use of Interpolated Second-Order Polynomials for Efficient Filter Design in Programmable Downconversion[END_REF] [START_REF] Oh | Multiplierless FIR Filters Based on Cyclotomic and Interpolated Second-order Polynomials with Powers-of-two Coefficients[END_REF]. A design example demonstrated that this leads to a more efficient decimation filter implementation.

In 2003, Dolecek and Mitra proposed an efficient sharpening of a CIC decimation filter for an even decimation factor. The design structure consists of two main sections, a cascaded of the first-order moving average filters, and sharpening filter sections. The sharpening is moved to lower section which operates at the half of the high input rate and has only one half of the original sharpened CIC filter length. The result shows the gain responses of proposed CIC filter in the frequency range (0, 0.3) and dB scale (-200, 0). This New computationally efficient structure is well suited for sharpened CIC decimation filter.

Three leading semiconductor companies fabricated ICs with CIC decimation filters, namely Harris Semiconductor (now called Intersil) (Harris Semiconductor 1998;Harris Semiconductor 1990;[START_REF] Riley | High Decimation Digital Filters[END_REF]), Graychip Inc. (Texas Instrument 1996) and Analog Devices Inc. (Analog Devices 1998). Their functionality and performance are compared below.

In Harris' HSP50214 programmable DDC (Harris Semiconductor 1998), a fivestage CIC decimation filter is used, and the decimation ratio can be programmed from 4

to 32. The throughput can be as high as 52 MHz.

Harris' HSP43220 (Harris Semiconductor 1990;[START_REF] Riley | High Decimation Digital Filters[END_REF]) is a pure digital decimation filter. It composed of two modules, namely, a five-stage CIC decimation filter followed by a FIR decimation filter. The input word width is fixed at 16 bits, and the output at 24 bits. It accepts sample in 2's complement format with a sample rate of up to 35 MHz. The decimation ratio ranges from 10 to 1024.

In Gray chip's GC4016 Multi-Standard Quad DDC chip (Texas Instrument 1996), a five-stage CIC decimation filter is also used. The input data sampling rate can be up to 80 MHz, and the decimation ratio is programmable as any integer between 8 and 4K. Note: in this work, for throughput or data sampling rate, the unit is normally referred to as MHz.

Analog Device's AD6620 digital receiver (Analog Devices 1998) also uses a five-stage CIC decimation filter. The decimation ratio range is from 1 to 32 and the highest data input rate for the CIC decimator is 32.5 MHz. Laddomada and Mondin (2006) presented the design of a novel decimation filter, especially suitable for sigma delta converter, which showed better performances in terms of both pass-band drop and quantisation noise rejection with respect to conventional CIC decimation filters. In particular, the combination of the sharpened filters and the modified CIC filters with the goal of increasing the rejection of the sigma delta quantisation noise around the folding bands and reducing the pass-band drop of the designed decimation filters has been designed with respect to CIC structures.

Hong-Kui Yang and W. Martin Snelgrove (1996) took another approach to implementing a CIC decimation filter. They decomposed the decimation ratio R into two factors, namely,

2 1 R R 
(the parameters are integer). Instead of using one CIC filter to decimate the high speed digital signal, they used two CIC decimation filters:

one CIC filter with a decimation ratio of 1 R , and one with a decimation ratio of 2 R . The implementation of the first decimator was based on polyphase decomposition. It has been shown that the polyphase components can be realized with only a small number of adders and shifters. decimation rates up to 14 2 over a 16-bit 2's complement data field with 20-bit coefficient precision in single 33 MHz 84 pin low power CMOSIC.

SUMMARY

This chapter describes audio signal bandwidth and the necessity of using the oversampling technique to push quantization noise created by sigma delta modulator to higher frequency bandwidth. Utilizing the oversampling technique, the stringent requiring for anti-aliasing filter can be relaxed.

The chapter explains the reason of using the decimation filter to reduce sampling frequency rate and to get the audio signal from bandwidth. The CIC filter also rejects the quantization noise to achieve higher SNR.

The literature study presented above gives outline of the relevant fields that are required and used in the duration of this work. In next chapter, the study will focus on research methodology and the detailed explanation of the decimation filters.

CHAPTER III RESEARCH METHODOLOGY AND DECIMATION PROCESS

This chapter explains the research methodology of the project followed by implementation workflow in detail. After understanding of overall system workflow, the applications of the CIC filter are discussed completely. It is continued by the system verifications with the express of the advantages of using multi-stage decimation filters.

The oversampling and multi-stage decimation filter is briefly proposed and the system simulation is given by using MATLAB software.

PROJECT WORKFLOW

With the scope of work being successfully narrowed down to realistic goals, the design and development of the CIC filter is embarked up on. This overall research work involves the effort of simulation and VLSI implementation of high speed CIC filter to meet the required system functionalities. The design flow of the research work will be explained in the following section. Once the algorithm for the CIC filter is identified, a comprehensive MATLAB simulation was carried out to determine the functionality of the algorithm. The hardware coding (using Verilog) is written then followed by implementation using in ASIC or FPGA.

The literature reviews and documentation of project are done throughout the research process. The flowchart is followed by defining the algorithm, modification and the Verilog HDL implementation. The project is contributed to achieve the goals to enhance the previous decimation research work. The hardware code is transferred to UNIX machine to check the filter properties in gate level by CAD tools (Synopsys and Cadence). The workflow will go ahead if the design meets the desirable specifications and goes through the next stage which is the FPGA prototype and testing. In the same time, the design also is synthesized, timing verified and finally simulated at gate level on the 0.18 SilTerra and 0.35 MIMOS process technology. We also made a comparison between these two technologies in term of their performance (Speed, power consumption, area,…). Based on the filter architecture and design specifications, the hardware design flowchart of the CIC filter is proposed as shown in Figure 3.2. In the RF transceiver, the analogue signal in coming (at the antenna) usually passes through a signal conditioning circuitry which performs functions such as amplification, the attenuation and filtering. After amplifying RF signal, it is digitized by the ADC converter. The signal to the ADC is continuously sampled at rate equal to s f , and thus the ADC presents a new sample to DSP at this rate. Normally the sigma delta modulator ADC with will sample RF signal with extremely high sampling rate. This property makes the converter very costly in terms of processing requirements. Although sigma delta modulation to some extend is an analogue to digital converter, it does not produce a standard base representation for the analogue data [START_REF] Fowler | CMOS Area Image Sensors with pixel level A/D Conversion[END_REF]. Therefore some computation on sigma delta modulator must be performed in order to convert it into the actual digital data which represents the analogue signal. This digital signal needs to be down-converted, filtered and decimated by the decimation digital filter before being used in audio and radio signal. Decimation converts m-bit one samples into n-bit one sample and filtering is used to reject quantization noise (Figure 3.3). The decimation filter eliminates frequency components beyond baseband and reduces the sampling rate down to R f s . The selection of the bandwidth and all other processing would be handled in the digital domain. The low pass filter is required to remove unwanted signals outside the bandwidth of interest and prevent aliasing. In order to maintain real-time operation, the DSP must perform all its required computation within the sampling interval and present an output sample to the DAC before the arrival of the next sample from the ADC. Finally the DAC is required so that the analog signal (voice) can be obtained [START_REF] Kuan | A 70 MHz CMOS Band-Pass Sigma-Delta Analog-to-Digital Converter for Wireless Receivers[END_REF]Felman 1997Felman , 1998)).

Besides being used in digital transceivers, decimation filters are widely used in many systems involving multirate processing and conversion. Those applications include frequency shift keying (FSK) modems, speech/audio coding and image/video coding [START_REF] Vaidyanathan | Multirate Systems and Filter Banks[END_REF]. The comb filter which is part of the CIC filter is used in audio engineering to achieve special sound effects. It is also used in the construction of digital reverberation processors, where they represent the effects of multiple reflections of a sound wave off the walls of a listening space [START_REF] Orfanidis | Introduction to Signal Processing[END_REF]. In digital TV, comb filters are used in the case when both signals are periodic and must be separated from each other. The comb filters are used to separate the luminance (black & white) and chrominance (colour) signals from composite video signal and also to reduce video noise [START_REF] Orfanidis | Introduction to Signal Processing[END_REF].

MULTI-STAGE DECIMATION FILTER

Oversampling technique limits the possibility of the aliasing present in the base-band.

Thus the input signal could be sampled at higher rate to prevent aliasing. Later on, the sampled signal is decimated and filtered by using a digital decimation low-pass filter.

The combination of the filtering and decimation prior to performing another filtering operation on the data is called multi-stage digital decimation filtering. It takes the advantages of having enabled the processing of oversampled signals, and continues to drive down cost and power consumption by decimation. By decimating in multiple stages, the complexity of the whole filter is reduced and the subsequent filters operate at lower sampling rate, further reducing the power consumption. Whereas single stage decimation filter use large number of filter coefficients which is not suitable for powerefficient implementation.

The multi-stage digital decimation filter also achieves computational savings by performing sampling rate conversion and filtering over several stages while utilizing efficient implementation structures such as polyphase filters [START_REF] Crochiere | Multirate Digital Signal Processing[END_REF]. The benefit of the multi-stage approach is that economical due to lower order filters operate at the higher sampling rate and higher order filters operate in lower sampling rate. The architecture of the filter is designed to minimize arithmetic and hardware complexity.

By implementing the filter as a cascade of several linear-phase stages, the ratio of the input rate to the width of the transition band is dramatically reduced for each of the individual stages [START_REF] Brandt | A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation[END_REF]Fujimoni et al. 1997). This multi-stage decimation filter can achieve both greatly reduced filter lengths and computational rates as compared to standard single rate filter design and thereby provide a practical solution to an otherwise difficult problem.

In most existing implementations for audio applications, the filters have been

2 1  R 16 0  R 2 2  R 2 3  R Figure 3.4
Third-order sigma delta modulator followed by the multi-stage decimation filters

THE SIGMA DELTA MODULATOR

According the above explanation, the analogue input signal is oversampled by a factor of 128. It passes through the third order sigma delta modulator. This modulator transforms a band limited input analogue signal into 5-bit digital output signal. The clock frequency of sigma delta modulator is much higher than the highest frequency of the input signal. To get a sufficiently high SNR ratio from the digital output of the audio signal (at least 16 bit) when truncation is applied, or 20 bit without truncation, is required. Among oversampled and decimation system above, the sigma delta modulator with 5-bit quantizer in its architecture provides the 5-bit resolution.

Signal conversion in the sigma delta modulator, is based on quantizing the change in the signal from sample to sample rather than absolute value of the signal at each sample. There is digital-to-analogue converter (DAC) in the sigma delta modulator structure called zero-order hold block in simulation which converts the digital signal back to analog form. It is then subtracted from the analogue input. The difference signal, which is the "delta" part, is accumulated in to the integrator which is the "sigma" part and provide a local average of the input the feedback loop causes the quantization noise generated by the ADC to be high pass filtered pushing its energy towards the higher frequencies and a way from the relevant signal band .

The multi-stage decimation stage reduces the sampling rate to 48 kHz. During this process, it removes the high frequency quantization noise that was introduced by the feedback loop and removes any undesired frequency components that were not removed by the simple analog prefilter. First-order sigma delta modulator simulation is shown in Figure 3.5. The quantization noise is one limiting factor for the dynamic range of an ADC. This error is actually round-off error that occurs when an analog signal is quantized. The mean square value of the noise, 2 rms e produced, by quantization in the sigma delta modulator (assuming that the signal value is in the range of one step of the quantized value with an equal distribution) is given by: 12

1 2 1 1 2 2          de e e rms (3.1)
where Δ is the quantization interval or one LSB size.

The equation above assumes that the quantization noise is white. The assumption is not true in general but it gives a good approximation when the input signal is busy.

When a quantized signal is sampled at frequency T f s 1  , all of its power folds into the frequency band

s f f   0
. Then, if the quantization noise is white, the spectral density of the sampled noise is given by:

  s s f e f e f E 2 2 2   (3.2)   f E
has inverse proportional to quantization bits. The more quantization bits,

the lower   f E
is and the less noises alias into the signal band. To design high resolution ADC, the number of quantization noise should be increased which lead to the complex circuit design.

We can use this result to analyze oversampling modulators. Consider a signal lying in the frequency band 0ffB. The oversampling ratio (OSR), defined as the ratio of the sampling frequency s f to the nyquist frequency B f 2 , is given by the integer:

B s f f OSR 2  (3.3) 35
Hence, the in-band quantization noise will be given by (Jarman 1995;[START_REF] Kuan | A 70 MHz CMOS Band-Pass Sigma-Delta Analog-to-Digital Converter for Wireless Receivers[END_REF]:

  OSR e f f e df f E n s B f B 2 2 0 2 2 2       (3.4)
That means higher oversampling ratio, will give higher SNR and also higher resolution in bits.

The MATLAB simulation of the third order sigma delta modulator is shown in Figure 3.6. The multi-stage decimation filter introduced after the modulator, not only removes the noise at higher frequencies but also reduces the frequency of the signal and increases its resolution.

CASCADED INTEGRATOR COMB FILTER (CIC)

The fifth-order CIC filter was designed and implemented as a decimator. This filter is supposed to drive down the sampling frequency by the factor of 16 and reject the quantization noise to out of the desired bandwidths. The CIC filter provides 25 bit resolution to increase the SNR more than 140 dB. The architecture of digital CIC filter and its utility will be described in next chapter in detail.

FIRST AND SECOND HALF BAND FILTER

The other important components that must be designed are First and second half band filters (Figure 3.4). One issue encountered in designing these filters is the computational complexity. Since the transition band width is inversely proportional to the filter length, the number of multiplier required. To realize a sharp filter is large and thus the corresponding complexity becomes very high. Thus an efficient second stage filter can be selected from a class of filters called the half-band. These are even order linear phase FIR filters having a special property that every odd sample of their impulse response is zero, except for the sample at the centre of the impulse response which has a value of 0.5. Thus, the number of computations required to implement these filters is reduced by approximately half. Due to the known fact that half-band filters reduce the computational complexity of general filters with the same order, half band FIR filters are widely used (Min-Chi [START_REF] Kao | A novel Iterative design Technique for Linearphase FIR half-Band Filters[END_REF].

The standard architecture of half band filter shown in Figure 3.7. These filters divide the sampling frequency of the discrete time system into two. The FIR filters are often used as half band filters due to their linear phase response. It is used in decimation filtering because half of their time domain coefficients are zero. This means it can achieve the performance of an M-tab FIR filter while only paying the computational price of approximately M/2 multiplications per filter output sample.

The two cascaded half band filters with the filter order eight and eighty respectively are used to reduce the remaining sampling rate reduction to the Nyquist rate. First and second half band filter makes the frequency response more flat and sharper similar to the ideal filter specially second half band filter due to higher order of the filter (N=80), has most effect to make the frequency response sharp. The transition band of second half band filter is less than 5 kHz.

According to Figure 3.7, all the odd coefficients of half band filters are zero with the exception of last one the (0.5). It makes the two filters efficient for 2:1 decimation ratio and reduces the computational complexity by near 50% as compared to direct form filter architecture. ) (

1  z 1  z 1  z 1  z 1  z 1  z 1  z 1  z 1  z 1  z 0 C 2 C 4 C 6 C 8 C 0 1  C 0 3  C 0 5  C 0 7  C 5 . 0 9  C 1  z 1  z 1  z 1  z 1  z 1  z 1  z 1  z X Y Even Branch Odd Branch
         z h z h z h z h h z H (3.5)
The Matlab simulation of the first and second half band filters has been done a as low pass filter decimator to enhance decimation system. Every Y sample is calculated by even and odd coefficients in the half band filters. The tapped-delay lines in the even and odd branches in half band structure doubled back to exploit the symmetric impulse response of the linear phase filter and reduced the number of multiplications by a factor of two [START_REF] Oppenheim | Digital Signal Processing[END_REF]. The MATLAB simulation result shows that the pass-band, stop-band frequency and transition band are 32, 170 and 138 kHz for first half band filter and 21.77, 26.53 and 4.76 for second half band filter respectively.

SUMMARY

The chapter has presented the research methodologies adhered to in this research including research procedure, system design procedure and tool applied. It also has managed to describe the application of the CIC filter which is the subject of this research. This chapter is continued by the overview of multistage decimation filters compared to single stage decimation. Finally the principle definition of the modulator and the decimation filters was described in brief and simulated by MATLAB software.

CHAPTER IV THE CASCADED INTEGRATOR COMB (CIC) FILTER AS DECIMATOR

After reviewing the overall system in previous chapter, the definition of the digital filter as well as to present the basic principles of the decimation CIC filters with focusing on their properties is described in this chapter. The entire filter components are described separately and analyzed in frequency domain. The comparison is made between a conventional decimator and the CIC filters with the explanation of the CIC filter advantages. Additionally the functionality of a simple CIC filter is evaluated and proposed in chapter IV.

REVIEW OF THE BASIC DIGITAL FILTER

The digital filter operates on digital sampled signal. Implementing using digital filter is preferred as compared to the analogue filter since the digital filter has the advantages of high performance, low implementation cost and long term stability. Additionally, digital filter can be controlled easier than the analog filter.

The digital filter equation is given by:

      k n x k h n y k        (4.1) where   k h
is the filter coefficient. For casual filter, all coefficients all are zero for 0  k .

For the FIR filter, the number of the filter coefficients are limited, whilst for the IIR filter, it has unlimited number of the coefficients. The equation ( 4.1) can be written as:

      k n x k h n y L k       1 0 (4.2)
z  1 z  1 z  + + + ( )
x n

( 2)

x n 

( 1)

x n  ( 1) x n L   ( ) y n 0 h 1 h 2 h 1  L h Figure 4.1 The digital FIR filter structure
High value of L will make the filter sharper and close to the ideal filter at the expense of filter cost and a more complex filter structure. The digital filter can be introduced in the z domain as below:

      z X z H z Y   (4.3) where   z H
is the transfer function of the filter and z can be replaced with

 j e z 
in frequency domain given by:

    k L k z k h z H       1 0 (4.4)    j e H
is called the magnitude response of the filter and it is obtained by filter transfer function. The transfer function   z H , will also give the phase information of the filter. The filter is stable when its phase response is linear.

Unlike the FIR filter, the IIR filter has a feedback loop and infinitely long pulse responses. The equation of the IIR filter can be expressed as below:

          k n y k a k n x k h n y M k L k            1 1 0 (4.5)
Thus the transfer function in the z domain can be written as equation (4.6).

                 M k k L k k z k a z k h z H 1 1 0 1 (4.6)
The block diagram of the IIR filter with feedback loop is shown in Figure 4.2.

Although the length of the IIR filter is infinite, Yiqun [START_REF] Xie | High-speed Decimation Filter for a Delta-sigma Analog-to-digital Converter[END_REF] has shown that it can be implemented through an FIR subfilter with appropriate feedback.

   

k h     k a +   n x   n y     k n x k h L k      1 0     k n y k a M k    1

CONVENTIONAL DECIMATION FILTER

As mentioned before, a decimation filter is required after sigma delta modulator to remove out-of-band components of the signal and noise and resample the signal at the nyquist rate. According to Figure 3.4, the output of the modulator provides the input to the decimation filter, with additional quantization noise at higher frequencies.

In the past, a decimation filter was used to reduce the sampling rate. The structure of the decimation filter in Figure 4.3 consists of the low pass filter and a down sampler blocks. In order to produce one sample at the data output when the decimation ratio is R, M R  multiplications are required. Thus the number of calculation is increased and hence limiting the high speed and significant waste of the power consumption. To improve the decimation system, [START_REF] Proakis | Digital Signal Processing, Principles, Algorithms, and Applications[END_REF] introduced polyphase filter structure for high speed purposes. But the implementation increases the complexity. Then in 1981, Hogenauer has developed an alternative to the polyphase filter that has increased efficiency because it does not required multiplier.

 z R Y(m) R F s / s F h(0) x(0) s F h(1) 1  z h(2) h(M-2) 1  z h(M-1)

STRUCTURE OF CASCADED INTEGRATOR COMB FILTER (CIC)

The process of down-sampling is called decimation (Dongwon see et al. 2000;[START_REF] Rajic | Efficient implementation of sharpened CIC decimation filters for software radio receivers[END_REF]). On the other hand up-sampling is called interpolation [START_REF] Schafer | A digital signal processing approach to interpolation[END_REF][START_REF] Yaroslavsky | DFT and DCT based discrete sincinterpolation methods for direct fourier tomographic reconstruction. 3 rd international image and signal processing and analysis[END_REF][START_REF] Seidner | Poly phase antialiasing in resampling of images[END_REF]. In audio application, the sampling rate of the sigma delta modulator needs to be decimated and filtered by the filters. The Cascaded Integrator Comb (CIC) filter is used both in the decimation and interpolation. Figure 4.4 shows a complete oversampling system that consists of the sigma delta modulator and the CIC filter. Here the CIC filter is a decimator. In this work the 5-bit output of the modulator produced by the 5 bit quantizer (with the sampling frequency of 6.144 MHz) is inputted to the decimation filter. The CIC filter has three basic tasks:

1) Reject the quantization noise to remove out of frequency bandwidth.

As described before, sigma delta modulator creates some quantization noise in the baseband. This noise has direct effect on the SNR and can degrade the quality of audio signal.

2)

Reducing the sampling frequency or decimation (Babic et al. 2001;Babic & Renfors 2001;[START_REF] Chu | Multirate filter design using comb filters[END_REF]. Sampling frequency of the sigma delta modulator should decimate down to the Nyquist rate which minimizes the amount of information for digital signal processing. This important task is carried out by the CIC filter.

3) Anti-aliasing [START_REF] Hogenauer | An Economical Class of digital filters for Decimation and interpolation[END_REF]. The last and important task of the CIC filter is to prevent the aliasing that result from the down sampling.

The CIC filter has the advantage that it only has the adder and subtraction and not multiplier. This computational efficiency makes the CIC filter attractive in the DSP applications for low noise. The CIC filters are useful for a narrowband desired signal,

where the nulls of the filter are wide enough to protect the desired pass-band from aliasing distortion. Additionally its architecture has a regular structure and little external control or complicated local timing is needed.

Due to all filter coefficients equal to unity, this filter does not require storage for saving filter coefficients. The CIC filter consists of three main blocks which are the integrator, the differentiator and the down sampler as shown in the figure. Each block will be described in the next section.

INTEGRATOR

The Integrator is the first block of the CIC filter. This block consists of adder and one unit delay register which are connected as one-stage accumulator. The equation of integrator with the assumption of M is one unit delay in discrete time domain is:

      s s s nT x T n y nT y    ) 1 ( (4.7)
      1 1 1 1       z z z z x z y z H I (4.8)
The integrator modelled in the z domain is shown in Figure 4.9. As seen in the Figure, the integrator has low pass structure to push the noise to the high frequency band.

+ +   z x   z y 1  z Figure 4.

Integrator block diagram in z domain

The integrator is an IIR filter with a unity feedback coefficient [START_REF] Chandel | Design of Cascaded-Integrator-Comb filter for PSK modem[END_REF].

Using the equations for a single pole integrator system [START_REF] Oppenheim | Discreet-Time Signal Processing[END_REF]), it can be shown that:

      cos 1 2 1 2   j I e H (4.9)                  cos 1 sin tan 1 j I e H Arg (4.10)                   0

DIFFERENTIATOR

The second main block of the CIC filter is the differentiator. This block is also known as a comb filter. The comb filter running at the lower sampling rate of R f s , where R is the decimation factor. This stage consists of a subtractor and a time delay unit connected by a forward loop. This filter is Finite Impulse Response (FIR) filter and has no feedback loop. The Comb filter has a high pass structure to attenuate infinite DC component frequency created by the integrator part, making the whole system stable.

The equation of the differentiator block in time domain is given as:

        s s s T k n x nT x nT y    (4.12) where R M k  
(M is the differential delay, R is decimation factor) in the comb structure. M can be any positive integer (normally limited to 1 or 2). The differential delay is a filter design parameter used to control frequency response of the filter.

      k C z z x z y z H     1 (4.13)
where   z y is the comb output and   z x is the comb input in sampling frequency of R f s .

Again using Oppenheim equations [START_REF] Oppenheim | Discreet-Time Signal Processing[END_REF]), the phase and complex modulus of z achieve as below: radians apart around the unit circle, starting at 0   and there are MR poles at the origin. For even R, there is also a zero. Being an FIR filter, it is always stable for any R.

      k e H j c cos 1 2 2   (4.14)     2   k e H ARG j c   (4.15)     2 k e H grd
The CIC filter consists of the N ideal comb stages operating at the low sampling rate R f s / . While the integrator may produce overflow at the output, a serial connection of comb stages is located after the integrator to avoid overflow in the baseband and guarantee the filter stability.

DOWNSAMPLER

Down-sampling is the process of reducing the sampling rate of a signal. This is usually done to reduce the data rate or the size of the data. The operation of down-sampling by factor R, describes the process of keeping every R th sample and discarding the rest. This is denoted by "↓R" in block diagrams, as shown in Figure 4.19. R which is the decimation factor is an integer greater than unity. It is better to select R as power of two integer digit. This factor multiplies the sampling time or, equivalently, divides the sampling rate.

R   n x   m y s f R f s
    R m x m y   (4.17)
The input signal of the down-sampler is a series. These series can be introduced in z domain as follow:

    n n z n x z X        (4.18)
All the multiple coefficients of R will be kept after passing down-sampler and the rest of the sample will be discarded. To implement the down-sampler, the input must be multiplied with   n h where   n h is given by:

      0 1 n h      mR n mR n (4.19) 59
The output of the down-sampler in z domain described as below:

    mR m R z R m x z X         . (4.20)     m R m z m x          R z Y 
The down-sampling in time domain shown as Figure 4.20 when 4  R .

 

n x n   a 1   n h n   b   m y m   c
R    2  X   a 0 R   2  Y   b R  2 R  3 R  4 R  5 R  6 R  7
0 R   2  Y R  2 R  3 R  4 R  5 R  6 R  7 Aliasing Figure 4
.22 Presence of aliasing when the input signal is not limited to R



In fact, aliasing occurs when a signal is under-sampled which depends on the sampling frequency. If s f is too low, aliasing will happened in frequency domain. In general, aliasing by the factor R corresponds to a sampling rate reduction by a factor of R. To prevent aliasing when reducing the sampling rate, an anti-aliasing low-pass filter is generally used. The low-pass filter attenuates all signal components at frequencies outside the interval

       R f R f s s 2 , 2
so that all frequency components which produce alias is first removed.

CIC FILTER PROPERTIES

The CIC filter is a multi-rate filter supporting by the fixed point arithmetic. When a fixed-point filter is considered to design, in fact some data bit is thrown away after the accumulation if the input signal is defined float.

Z + + + - 1  Z + + R M Z  + - M Z  N stages integrator N stage differentiator   n x

  n y

High sampling rate Low sampling rate

               N RM k k N RM N N RM N C N I z z z z z z z z H z H z H                                    1 0 1 1 1 1 1 1 ... 1 1 1 1 (4.21)
where N is the filter order, R is decimation factor and M is differential delay.

The differential delay or M is used as a design parameter to control the placement of the nulls in the frequency response. For the CIC decimation filters the region around every M-th null is folded in to the pass band causing aliasing errors. This is necessary to prevent signals from aliasing back into the pass-band. The cut-off frequency of the pass-band is adjusted by the differential delay.

After decimation by downs-ampler, the clock frequency of the CIC filter is decreased by the factor of R and the transfer function when

1  M is converted as follow:   N R z z R z H             1 1 1 1 (4.22)
As stated in the literature [START_REF] Hogenauer | An Economical Class of digital filters for Decimation and interpolation[END_REF]Brandth 1991), the frequency response is given by (4.22) evaluated as: It is assumed that the decimation factor has large value and by using the relation,

x x  sin
(for small size of x), the amplitude response or power response of the CIC filter can be simplified

  f p A as.   N A Mf Mf RM f p 2 sin          M f 1 0   (4.25)
Error between Equations (4.24) and (4.25) is less than 1dB for The CIC filters are efficient since they provide attenuation only in frequencies required by using cascaded integrator and comb filters to form higher order CIC. This will be ensured a better attenuation over wider frequency range around zero. From N which is the number of stage determines the pass band attenuation. Increasing the N will improve the filter ability to reject aliasing and imaging but it also increases the droop (or roll off) in the filter pass band. For a sigma-delta modulator of order L, a cascade of N order CIC filter is needed to adequately attenuate the quantization noise that would alias into the desired band [START_REF] Candy | Decimation for Sigma-delta Modulation[END_REF].

1   L N (4.26)
Hence, for a third order modulator, a forth order CIC filter should be used. To ensure filter capability of reject aliasing in the baseband, the fifth order of CIC filter is used in this project. Figure 4.25 shows the effect of increasing filter order on the frequency response. The number of bit must be determined in the CIC filter structure in order to avoid overflow in the integrator and the comb stage. This necessitates determining the maximum magnitude. In other word, max G is the maximum register growth and a function of the maximum output magnitude due to the worst possible input conditions [START_REF] Hogenauer | An Economical Class of digital filters for Decimation and interpolation[END_REF]. N, M and R are parameters to determine the maximum register growth requirements necessary to assure no data loss and can be expressed as equations (4.27) and (4.28).

  N N RM k N RM k k N RM k k N RM k k N RM k k RM z z z z k h z H                                            1 0 1 0 1 0 1 0 ) 1 ( 0 1 ) ( ) ( ( 4
 Z + + + - 1  Z + + R M Z  + - M Z  N stages integrator N stage differentiator   n x

  n y

High sampling rate Low sampling rate

NON-RECURSIVE COMB FILTER

When the decimation ratio and filter order are high the CIC filter use high power consumption since the integrator stage works at the highest oversampling rate with a large internal word length. The circuit speed will also be limited by the recursive loop of the integrator stage. Thus the Non-recursive comb filter is introduced to replace when the decimation ratio and filter order are high. This filter is a decimation filter with regular structure. This property makes it suitable for VLSI implementation. It is investigated and developed [START_REF] Farag | A programmable power-efficient decimation filter for software radios[END_REF][START_REF] Candy | Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation[END_REF]Yonghong Gao et al. 1999) because of its advantages such as no recursive loop and using low power consumption due to computations are performed at lower sampling rate. The nonrecursive comb filter has ability of wide range of rate change. Its transfer function is shown as follow:

  N M i N i i N R i i i M z z z z H                               1 0 2 1 2 0 1 0 1 ) ( (4.30)
where R is the decimation factor, N is the filter order and M is the number of stage. Note that R should be a power of 2.

The non-recursive comb filter structure is shown in Figure 4.31. Compared to the CIC filter structure the Non-recursive comb filter has the specification as:

1. During decimation process and decreasing sampling frequency, the number of bit increases and it is the reason of the saving in power.

2. The comb decimator using the Non-recursive algorithm can achieve higher speed since the first stage always has small word length.

3. When decimation ratio increases, the silicon size of the Non-recursive comb filter design algorithm increases faster compared to the CIC filter design algorithm.

) (n y   N z 1 1     N z 1 1     N z 1 1   ) (n x i s f 2 / 1 2 /  i s f 2 2 2 Stage 1 Stage M Stage 2 C+MN bit C bit C+2N bit C+N bit
When N = 3 Block 1 Block 3 Block 2   N z 1 1    1 Z 1  Z  1 Z  1 Z  1 Z  1 Z + + + Figure 4
.32 One stage of the comb filter when 3  N

SUMMARY

In this chapter principle of the decimation and interpolation was introduced. The conventional decimation filter was described and the comparison has been done with the CIC filter structure. The CIC structure and its advantages were explained in detail. The frequency analysis of the CIC decimation filter was also presented in this chapter. The CIC filter has three important components that is the integrator, the differentiator and the down sampler. The integrator has low-pass structure to attenuate high frequency component and the differentiator has high-pass structure to attenuate DC component and makes whole system stable. Finally the structure of the non-recursive comb filter and its specification was described. The Non-recursive comb filter is replaced as decimator when the decimation ratio and filter order in the CIC filter are high.

CHAPTER V CIC FILTER IMPLEMENTATION

This chapter discusses on the implementation details of the CIC filters. After the functional testing of the CIC filter and its system simulation were performed, the filter implementation is embarked up on. The design and implementation of the CIC filters verified by Verilog HDL, is presented before the Verilog codes were loaded into the field programmable gate array (FPGA) chip. The FPGA chip is the integrated circuit that is field configurable by the end user for a logic design implementation [START_REF] Ashok | Programmable Logic Handbook[END_REF].

Besides, the CIC filter system is synthesized using SilTerra 0.18 m  and MIMOS 0.35 m  technologies, separately. The comparison results between two technologies are given that shows the design enhancement by different technologies.

In order to reach high throughput and low power consumption, some design innovations were considered. Thus, these techniques were introduced to overcome the problems. A new architecture is utilized to achieve the design objectives. The high speed filter is achieved by three methods i.e. using MCLA in adder, truncation and applying pipeline architecture. Furthermore, the power consumption is reduced by minimizing the number of calculations and optimizing the electronic elements.

STAGE REALIZATION

The overall stage realization of the CIC filter is redrawn in Figure 5.1. This section describes the logic blocks that function in architecture of the CIC filter such as cascaded integrator, downsampler and cascaded comb filter. The complete process flow for the IC design using Verilog HDL (i.e. top-down approach) will be described in future (chapter

V & VI).

CIC_out

Adjuster Counter

1  Z 1  Z 1  Z 1  Z 1  Z Figure 5.

Implementation of the CIC filter

The input signal which is fed to the filter is in the two's complement format to avoid the overflow effect on the data. Thus an adjuster is required to convert the 5-bit input data to the 25-bit and to make the input data as two's complement. Then input sample is sent to the first stage integrator filter for further computation. The integrator output is accumulated with the first input using the feedback loop and an adder, i.e. the result is passed from 1-bit register (delay) before adding with the input samples in the loop. At each clock cycle, the content of the shift register is shifted to complete the integration process. The same procedure is repeated in the five-stage integrator. The output of the 5 th integration is transferred to the down-sampler (Counter and R). Based on the decimation ratio (by using an up-counter), 1  R samples are discarded and multiple coefficients of R is kept before sent to the comb filter.

The subtractor in the comb structure subtracts the down-sampler output from the delayed input. Basically the subtractor is an adder with one input inverted. The comb output signal is passed through the five order comb structure. At the end of the process we obtain the decimation input signal.

In order to verify the functionality of the CIC filters, we have downloaded the Verilog codes into the FPGA so that we can test the CIC filter. Xilinx and Modelsim EDA tools were used to synthesize and to simulate the design. Table 5.1 shows the summary of Xilinx synthesis for the CIC filter.

SPEED AND POWER IMPROVEMENT

The result obtained as shown Table 5.1. The implementation of the CIC filter made use of the standard components in the library. In order to improve the CIC filter functionality, further speed and power optimization was implemented by using proposed new architecture. The new architecture proposes the following methods:

1. Faster adder algorithms 2. Truncation process 3. Pipeline structure

IMPLEMENTATION OF THE FAST ADDER

Fast adder is one of the approaches to increase the throughput of the CIC filter. There are different methods to do addition. The straight forward method of adding m numbers with n bits is to add the first two, then add that sum to the next and so on. This technique requires a total of m-1 addition and high number of gate delay and is normally known as ripple carry adder (RCA). In RCA [START_REF] Ciletti | Advanced Digital design with the Verilog HDL[END_REF][START_REF] Doran | Variance of an improved carry Look-ahead Adder[END_REF]), the most significant bit addition has to wait for the carry to ripple through from the least significant bit addition. This approach of carry calculation makes the adder very slow.

To reduce the delay other techniques chosen as follow.

CARRY SAVE ADDER (CSA)

The carry save adder (CSA) has proved to a powerful technique to improve the adder timing. This technique adds 3 numbers (x, y and z) and then converts them into 2 numbers (s, c) in one unit delay. The following example shows the procedure of the technique.

x The carry, c is added to s with consideration of carry grade. The advantage of CSA is that c and s can be calculated in dependently.

The CSA structure is shown in Figure 5.3. The n bit CSA consists of n disjoints of full adders (FAs). It uses three n-bit input vectors and produces two outputs, n-bit sum, S, and n-bit carry, C. Unlike other type of adders such as ripple carry adder (RCA) and carry look-ahead adder (CLA), the CSA contains no carry propagation.

Consequently the CSA has the same propagation delay as only one FA delay and delay is constant for any value of n, where n is number of bit. For sufficiently large number of n, the CSA implementation becomes much faster and relatively smaller in size than implementation of normal adders [START_REF] Waste | Principles of CMOS VLSI Design, A system perspective[END_REF][START_REF] Kim | Arthmetic Optimization Using Carry-Save Adders[END_REF].

FA 0 z 0 y 0 x i C o C 0 s 1 C FA 2  n z 2  n y 2  n x 2  n s 1  n C FA 1  n z 1  n y 1  n x 1  n s O C  Z Y X i C O C C S + SUM Figure 5.3 CSA structure
The integration of CSAs is used in the integrator sections of the CIC filter. The synthesized result shows the maximum clock frequency of 97 MHz in the CIC filter.

Although the above clock frequency is sufficient for normal audio application, we carried further research in order to increase the clock frequency due to using this filter in receiver applications. In digital receivers digitizing IF signals is at the high frequencies. In wide band communications signal, the bandwidth has increased to tens of MHz so oversampling frequency of A/D converters will be hundreds of MHz [START_REF] Brandt | A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation[END_REF][START_REF] Jensen | A 3.2-GHz Secondorder Delta-Sigma Modulator Implementation in INP HBT Technology[END_REF]. In order to isolate the signal of interest from the digitized signals and decimation it to lower sampling rate, high speed decimation filters are required. Not only does this decimator operate at high speed but it also requires high resolution as well. Thus this research work design and implement high speed and high resolution CIC filter use for audio application and suitable for IF digital receiver.

MODIFIED CARRY LOOK-AHEAD ADDER (MCLA)

Modified carry look-ahead adder (MCLA) is known as a solution to improve the CIC filter speed. The carry look-ahead adder (CLA) is the fast adder [START_REF] Naini | A 4.5 ns 96-b CMOS Adder Design[END_REF][START_REF] Tsujihashi | A high Density Data-path Generator with stretchable cells[END_REF] which can be used for speeding up purposes. However the disadvantage of the CLA adder is that the carry logic is getting complicated for more than 8 bits. Consequently, we developed the enhanced version of the CLA introduced to replace the CLA adder. Improvement in speed in MCLA based on CLA is due to the carry calculation. Therefore, the carry of the MCLA adder has become a focus of the study in speeding up the adder circuits. The 8-bit MCLA architecture is shown in Figure 5.4.

a[0] b[0] s[0] p[0] g[0] a[1] b[1] s[1] p[1] g[1] a[2] b[2] s[2] p[2] g[2] c[1] c[2] a[3] b[3] s[3] p[3] g[3] PFA PFA PFA CLL-1 c[3] a[5] b[5] s[5] p[5] g[5] a[6] b[6] s[6] p[6] g[6] c[6]
a [START_REF]Creating CIC decimator filters. Filter design toolbox[END_REF] b [START_REF]Creating CIC decimator filters. Filter design toolbox[END_REF] s [START_REF]Creating CIC decimator filters. Filter design toolbox[END_REF] c [START_REF]Creating CIC decimator filters. Filter design toolbox[END_REF] a [4] b [4] s [4] p [4] g [4] c [4]

      0 0 0 0 0 0 1 b a carryIn b carryIn a carryIn       (5.1)
The 2 carryIn for next two bit, 1 a and 1 b when these two bits are added with 1 carryIn can be expressed as:

      1 1 1 1 1 1 2 b a carryIn b carryIn a carryIn       (5.2)
These equations can be minimized as:

      0 0 0 0 0 0 1 b a c b c a c       (5.3)       1 1 1 1 1 1 2 b a c b c a c      
(5.4)

According to the above equations, 2 c can be written as:

        0 0 1 0 0 1 0 0 1 0 0 1 2 b a b c b a c a a b a a c             (5.5)       1 1 0 0 1 0 0 1 b a c b b c a b        
It is clear that the equation is too complicated and for higher order of bits, the equation grows exponentially. This complexity is reflected in the cost of the hardware for fast carry. The carry equation can be defined in general form as:

          i i i i i i i i i i i i c b a b a b a c b c a c            1 (5.6)
The Generate   i g and Propagate   i p are defined:

i i i b a g   (5.7) i i i b a p   (5.8) i i i i c p g c    1 (5.9)
In terms of generate and propagate the carry out is given as:

) . ( 0 0 0 1 c p g c  
(5.10)

) . . ( ) . ( 0 0 1 0 1 1 2 c p p g p g c   
(5.11) (5.14)

0 1 2 3 1 2 3 2 3 3 . . . . . . g p p p g p p g p g G G    
(5.15)

The most important equation to obtain carry for next stage is defined as below:

) ( 0 4 c P G c out out   
(5.16)

There are half adders (HA) and partial full adders (PFA) in MCLA structure to add each 2 bit data.

0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 82 a[0] b[0] s[0] p[0] g[0] c[1] HA Figure 5.5 Structure of the HA
The HA normally is used to add the LSB of the 2 n-bit data when carry is equal to zero or 0 0  c . obtained is compared with the CLA adder and is presented in Table 5.3. Generally the MCLA adder perform better than the CLA adder, however when the bit size is increased, the throughput of the MCLA shows a slight decreased in performance. We have chosen the MCLA because of the easier configuration and fast calculations compared to others fast adders. Table 5.4 shows better performance in the MCLA compared to the CLA.

TRUNCATION

Truncation improves the speed of the system as well as decrease the power consumption. Truncation means estimating and removing least significant bit (LSB) that helps to reduce the area requirements on the chip. Although this estimation and removing introduces additional error, this error can be made small enough to be acceptable for DSP and audio applications.

The error (E), created by the truncation process can be described in equation

(5.17).

b j E   2

(5.17

)
where b is the number of bit in LSB that can be discarded [START_REF] Rabiner | Theory and Application of digital signal processing[END_REF] and j is the number of stage in the CIC structure.

As stated in the literature [START_REF] Hogenauer | An Economical Class of digital filters for Decimation and interpolation[END_REF], when the truncation is applied for a system with M stages, M noise sources are created. For the N-order CIC filter, 2N+1

truncation noise sources are contributed to the output data if all stages need to be truncated. Thus there are a total of 2N+1 error sources. The first 2N sources are caused by the truncation at the inputs to the 2N filter stages. The "1" error source is truncation into output register. Since the error has uniform distribution then the mean of the error is:

1 2 2 1     b E  (5.18)
Thus the variance of the error is:

2 2 12 1 j j E   (5.19)
By multiplying the error mean and variance in k-th filter coefficient, the total mean and variance in the output will be:

j j Tj D    (5.20) where          1 k j j k h D       1 2 2 ,...., 2 , 1 N j N j
(5.21)

The total variance can be described as (5.22). where

         1 2 2 k j j k h F       1 2 2 ,...., 2 , 1 N j N j
(5.23) j D is simplified from (4.27) as following:

  N j RM D       1 0          1 2 2 ,...., 3 , 2 1 N j N j j (5.24)
From (5.24), the first and the last stages of the CIC filter create the error mean for the whole system. However, the truncation error is too small and negligible.

1 2 1 2 1 1        N T N j T Tj T     (5.25)       1 2 1 2 2 N j Tj T (5.26)
The number of bit which is neglected in the integrator stages is determined by Matlab software. Figure 5.8 shows the SNR reduction when CIC filter is truncated to lower number of bit. Note that audio application required the SNR of at least 80 dB.

PIPELINE CIC FILTER STRUCTURES

Pipeline structure is a technique to increase the throughput of the CIC filter. This structure improves the digital filter efficiency. The outputs of the adder and subtractor are stored into the pipeline register located between the sub-components in the filter unit. By incorporation these internal registers, the pipelined unit operates faster. This reason stands for the concurrent operation of the all stages. However there is also a latency introduced by these pipelining structures. Fortunately, this is not an issue in most applications [START_REF] Srivastava | Optimum and Heuristic Transformation Techniques for simultaneous Optimization of latency and throughput[END_REF]. This means that the number of clock cycles between the first input data and the appearance of valid output data is increased in pipeline architectures. It is due to the location of the register delay after adder in the CIC structure.

The latency depends on N, where N is the number of stages in either the comb or the integrator section of the filter. Thus, higher number of N increases the system latency. The pipeline adder is implemented for the MCLA as shown in Figure 5.10. The load and reset pins are the external pins to provide a better control for the CIC filters. The CIC filter structure has five subtractors in the 5 cascaded differentiators. To perform subtraction, it is necessary to take the one's complement of the bits of B and add 1 to the LSB [START_REF] Stine | Digital Computer Arithmetic Datapath Design using Verilog HDL[END_REF]. In this research work, ripple carry adder subtractor (RCAS) is designed to carry out the subtraction. This structure is shown in Figure 5.12.

+ - 1  Z Comb 5 16 bit CIC_out 1  Z 1  Z 1  Z 1  Z 1  Z 1  Z CIC_in Adjuster LSB rmv 1  Z + + LSB rmv 1  Z + + LSB rmv 1  Z + + LSB rmv
Note that the "Sub" pin should be 1; otherwise the RCSA is converted to the adder.

``F A FA FA FA S0 S1 S2 S n-1 Cn C3 Cn-1 C1 C2 S C S C S C S C a0 b0 a n-1 b n-1 a2 b2 a1 b1 Sub w0 Wn-1 w2 w1
n-bit RCAS In this project, multirate down sampler is selected to generate the output at a slower rate than the input. The schematic implementation of down-sampler is shown in

HIGH SPEED CIC IMPLEMENTATION

Based on the previous discussion, the pipeline (truncated) CIC filter is implemented using MCLA adder and RCAS subtractor. Then follow the standard procedure for FPGA, the CIC filter was downloaded into the FPGA chip.

Top level of the pipeline CIC filter is shown in figure 5.17.

Figure 5.17 CIC filter top level Figure 5.18 shows overall implementation of the CIC filter which includes the cascaded integrator, the cascaded comb, the down sampler and the adjuster. The output signal is truncated to 16 bit resolution.

Figure 5.19 illustrates the implementation of the 5 th -order cascaded integrator.

This stage which operates in high sampling rate is truncated to 25, 22, 20, 18 and 16 bit.

The Integrator limits the CIC filter throughput due to the maximum number of bit in the first stage.

The 5 th -order cascaded differentiator / comb is shown in Figure 5.20. This stage operates in low sampling rate of 16 bit. The synthesis report of the Xilinx ISE is shown in Table 5.6. The table shows the CIC filter can operate up to a maximum frequency of 189 MHz.

The FPGA power consumption depends on the amount of configurable blocks which are used for the filter implementation. This filter was implemented using 0.18 m  and 0.35 m  technologies which are expected to have better performance the FPGA chip.

Results are explained in the later sections.

FPGA DOWNLOADING

Additional blocks such as clock divider, memory and up-counter are required for downloading the high speed CIC filter design on the FPGA board. As shown in Figure

ASIC OPTIMIZATION (GATE LEVEL SYNTHESIS )

An application specific integrated circuit (ASIC) is an integrated circuit (IC) modified for particular use, rather than intended for general purpose use. ASIC is often termed a system on a chip (SOC) and bring about great saving of cost and lower power consumption. Minimal propagation delays can be achieved in ASICs versus the FPGA.

To describe the system functionality on ASIC, hardware language such as Verilog and VHDL are used.

From above explanation, the CIC filter is synthesized in ASIC to optimize the area

SUMMARY

In this chapter, the digital decimation CIC filter architectures were discussed and implemented. Several methods were explained and performed to increase the throughput of the filter. Firstly the standard CIC filter is implemented and then the adder was first replaced with the CSA.

RESULTS AND DISCUSSIONS

The chapter presents the simulation results of the designed CIC filter. The simulation process is first conducted for entire system that form the oversampling and decimation system. Once it is verified, then the implementation results of the CIC filter will be demonstrated. The FPGA and ASIC implementation of the CIC filter will be presented.

A comparison is made between different technology libraries (Mimos and Silterra technology) in terms of power consumption and area die size. Finally the layout of the CIC filter in 0.18 technology and FPGA will be presented.

FUNCTIONAL VERIFICATION OF THE OVERSAMPLING AND DECIMATION PROCESS USING MATLAB

As an initial step to verify the functionality of the designed CIC filters, Matlab software was used. The oversampling and decimation process is shown in Figure 6.1. Thus the selection of inputs to the block diagram must be properly chosen so that the input to the CIC filter is corrected. Thus SNR of the modulator will drop to zero if the input is greater than 1 V. This necessity is for the input signal to be about 1 V when the SNR is at its map value. The input bandwidth is also chosen to be less than 24 kHz, which is the required bandwidth for the audio application. Figure 6.3 shows the input audio signal used for the testing of our CIC filter. As mentioned in chapter II, because of the use of the integrator and the oversampling technique, the noise is pushed outside of the audio bandwidth resulting in the increased SNR. From the Matlab simulation, SNR is found to be 141.56 dB in the sigma delta modulator output which is acceptable for audio applications.

CIC FILTER SIMULATION RESULTS

The 5-bit output for the sigma delta is fed to the fifth order CIC decimation filter. That results in the reduction of the sampling frequency from 6.144 MHz to 384 kHz and as mentioned by the CIC filter, output has 25 bit width resolution. The frequency response of the 5 order CIC filter for M=1 is shown in Figure 6.6.

As illustrated in the Figure 6.6, the CIC filter has an abrupt droop in the passband (0-384 kHz) that is considered a wide bandwidth. The first half band filter with the order of eight provides the decimation ratio of two. Figure 6.9 shows the frequency response of the 8-order halfband filter when passband frequency, stopband frequency and transition band are 32 kHz, 170 kHz and 138 kHz respectively.

The output digital signal of the second half band filter is given with the sampling frequency of 192 kHz, whilst the frequency components between 170 kHz to 192 kHz (Figure 6.11) are attenuated. As described in chapter III, the droop correction filter is the 14-order FIR filter located after the half band filter. This filter also provides a decimation ratio of two. Thus the output signal appears with the sampling frequency of 96 kHz.

The frequency response and output signal of the droop correction filter are given in Figures 6.12 The digital output of the second Half-band filter with the Stop-band attenuation of 120 dB is given in Figure 6.15.

OVERALL SYSTEM SIMULATION RESULTS FOR THE DECIMATION FILTERS

The combination of CIC filter, first and second Half-band filters and the droop correction filter creates overall decimation system with a flat and sharp frequency response. We carried out the MATLAB simulation and the frequency response of the decimation filters are shown in Figure 6.16 and 6.17 This combination also reduces the filter ripple. The Pass-band ripple, after second Half-band filter is limited within  0.0001 dB. Figure 6.18 shows filter ripple in the Pass-band frequency which is negligible. For separate testing of the CIC filter blocks such as integrator, comb and downsampler a certain configuration of the CIC filter is used. In this configuration a number of multiplexers and de-multiplexers were used. Figure 6.27 shows the circuit configuration that was used to test the sub-blocks of the CIC filter.

As seen in the Figure 6.27, when signals 5

C and 6 C are high, only the integrator is tested, while other stages do not produce any output signal. The CIC filter specifications are summarized in table 6.1. Table 6.1 Summary performance of the CIC filter

SUMMARY

In this chapter, simulation result of the oversampling and decimation system using

CHAPTER VII CONCLUSIONS AND FUTURE WORK

CONCLUSIONS

The oversampling technique followed by the decimation process discussed was evaluated with the focused on the development CIC. The sigma delta modulator acts as an over-sampler and the decimation system acts as down-sampler. The third order sigma delta modulator with sampling frequency of 6.144 MHz converts analogue audio signal to digital sampled data and the high speed cascaded integrator comb filter (CIC), first and second half band filters and droop correction filter decimate the sampling rate from 6.144 MHz to 48 kHz in Nyquist rate. Among these filters, implementation of high speed CIC filter with the property of maximum decimation ratio, quantization noise rejection and anti-aliasing was the research topic of this project. The CIC filter has three main blocks which are the integrator, the down-sampler and the comb stages. The specifications of the filter in this research work are as follows: number of integrator is 5, number of comb filter is 5, decimation ratio is 16, and maximum number of bit is 25-bit that corresponds to maximum register growth of 120 dB. This filter was designed, investigated and implemented using MATLAB, Verilog HDL code, Xilinx and CAD synthesis tools. Enhanced high speed CIC filter was obtained by utilizing three methods. The pipeline structure which is applied for overall CIC filter blocks, using the modified carry look-ahead adder (MCLA) and truncation for integrator parts lead us to have high speed CIC filter with the maximum throughput of 189 MHz. The evaluation indicates that the pipelined CIC filter with MCLA adder is attractive due to high speed when both the decimation ratio and filter order are not high (the order and the decimation ratio of less than 10 and 64 respectively). Since the first stage of the CIC filter requires maximum word length and also because of the recursive loop in its structure, the power consumption is limited by the throughput. Reducing power consumption is one of the key issues in designing the CIC filter. It will be achieved by decreasing the number of calculation (achieved by truncation) and eliminating unnecessary elements (achieved by pipeline structure and using MCLA) in the filter.

The result of these efforts is the power consumption of 3.5 mW in Silterra 0.18 m  and 6.03 mW in Mimos 0.35 m  technology libraries at the maximum clock frequency.

FUTURE WORK

The layout was done. We proposed to have programmable CIC filter with the schematic of the chip in LD is an optional port and is only available with decimation filters. WE is active high write enable pin. This signal is associated with the in LD bus. The value on the in LD bus is latched by the core on the rising edge of the clock qualified with WE equal high. WE is an optional port and may only be selected for decimation filters (Logicore, 2002).

External control pins must operate together as parallel. Figure 7.2 shows the procedure of external control pins in the CIC decimation chip.

The CIC filter timing is also shown in

  the research background, problem statement, motivation, methodology, objectives of the research, scope of work, significance and contribution of the research, chapter organization and finally the summary of the chapter.



  It will be achieved by decreasing the number of calculation (achieved by truncation) and eliminating unnecessary elements (achieved by pipeline structure and using MCLA) in the filter structure. The CIC filter was synthesized in 0.18 m Silterra and 0.35 m Mimos technology libraries. The total estimated power consumption for the design after defining the constrained was less than 3.5 mW in 0.18 m Silterra technology and 6.03 mW in 0.35 m Mimos technology.

Figure 2 . 1

 21 Figure 2.1 Oversampling techniques to relax anti-aliasing filter

Figure 2 . 3

 23 Figure 2.3 Bandwidth resolution tradeoffs

Figure 2

 2 Figure 2.5 Conventional ADC spectrum with sampling frequency of s f

Figure 2 .

 2 Figure 2.6 Conventional ADC spectrum with sampling frequency of

Figure 2 . 7

 27 Figure 2.7 Sigma-delta ADC Spectrum with sampling frequency of

  Kewentus et al. (1997) described a new architecture for the implementation of high order decimation filters. Proposed design combined the CIC multirate filter structure with filter sharpening technique to improve filter pass band response. They implemented programmable high-order decimation filter in 1.0 m  CMOS technology.The chip can accommodate throughput rates up to 100 MHz for high performance.In 2003, Uusikartano and Takala presented a power-efficient CIC receivers. The power saving was based on running all the integrator at half the sampling frequency, regardless of the decimation ratio. The implementation result shows that the system can work with maximum throughput of 124 MHz with the power consumption of 4.5 mW. (Note that reference CIC filters utilize 5.8 mW power supply) The proposed architecture can utilize any decimation ratio even a prime or fractional number. In 1991, Riley et al. presented the architecture of an efficient high-decimation rate filter. A high decimation rate can extract narrow band signal intelligence from a wide band signal. The proposed system was multirate design consisting of a CIC section and a finite impulse response (FIR) filter. The function of the CIC section is to perform efficient high decimation rate filtering over the entire frequency band. The paper investigated the implementation of a 33 MHz high decimation rate filter and its hard ware implementation and performance. Riley reported the architecture and characteristics of an optimized decimating digital filter (DDF). The design can support

  Figure 3.1 illustrates the overview of the research in this work.

Figure 3 . 1

 31 Figure 3.1 Workflow of the project

Figure

  Figure 3.2 Hardware design methodology flowchart

Figure 3

 3 Figure 3.5 Matlab simulation of the first-order sigma delta modulator

Figure 3

 3 Figure 3.6 MATLAB simulation of the third-order sigma delta modulator

Figure 3 . 7 

 37 Figure 3.7 The half band filter structure

Figure

  Figure 3.10 MATLAB simulation of the second half band filter

Figure 3 .

 3 Figure 3.11 Droop in the CIC pass-band frequency

Figure 3 .

 3 Figure 3.12 MATLAB simulation of the droop correction FIR filter

Figure 3 .

 3 Figure 3.13 Droop compensation by the 14-order FIR filter

Figure 4 .

 4 Figure 4.1 shows the structure of the digital FIR filter which implying equation

  1

Figure 4 . 2

 42 Figure 4.2 The digital IIR filter constructed from the FIR sub-filter

  Figure 4.3 shows an example of the traditional decimation filter. These filters were widely used as decimator before the introduction of the decimation filter based on the cascaded integrator comb filter.

  1

Figure 4 . 3

 43 Figure 4.3 The low-pass conventional decimation filter[START_REF] Yang | Design and Implementation of a Cascaded Integrator Comb (CIC) Decimation Filter[END_REF]

Figure 4 Figure 4 . 4 Figure 4 . 5

 44445 Figure 4.4 Location of the CIC filter with its effect on sampling frequency

Figure 4 .Figure 4

 44 Figure 4.6 CIC filter structure in z domain

Figure 4 .Figure 4 . 7

 447 Figure 4.5 shows the basic structure of integrator in discrete time domain.

Figure 4 . 8

 48 Figure 4.8 Integrator frequency response when in single pole   1  z

  zero plots in real and imaginary domain and the magnitude response in frequency domain for the integrator are shown in Figures 4.10

  -4.13.

  Figure 4.10 Magnitude spectrum of integrator with 4 poles

Figure 4 .Figure 4 .

 44 Figure 4.11 Pole-zero plot of integrator with 4 poles

Figure 4 .Figure 4 .

 44 Figure 4.14 shows the basic structure of differentiator (comb) in discrete time domain.

  has a transfer function that looks much like the rounded teeth of a comb. Comb filter pole-zero pattern and frequency spectrum with different number of poles are shown in Figures 4.15

  -4.18.

Figure 4 .Figure 4 .

 44 Figure 4.15 Frequency spectrum of the comb with 4 poles

Figure 4 .

 4 Figure 4.19 Down-sampler block with the decimation factor of R

Figure 4 .

 4 Figure 4.20 Decimation in time domain when 4  R . (a) Sampled input signal (b) Decimation filter   n h ; (c) the output signal when all the zeros between every R-th sample are discarded

  0

Figure 4 .

 4 Figure 4.21 Magnitude spectrums of signals (a) before (b) after down-sampling

Figure 4 .

 4 Figure 4.23 N-Order CIC filter structure in z-domain

  and N are chosen to provide the acceptable pass-band characteristics over the frequency range from zero to predetermined cut-off frequency. The amplitude or power response of the CIC filter is given by:

Figure 4 .

 4 Figure 4.24 Magnitude response of the CIC filter

Figure 4 .

 4 Figure 4.26, the integrators allowing the low frequency content to pass then attenuate the high frequency content.

Figure 4 .

 4 Figure 4.25 shows the CIC filter frequency response when filter order is changed whereas the decimation factor   16  R and differential delay   1  M are fixed. The

Figure 4 .

 4 Figure 4.26 shows the CIC filter frequency response when decimation factor is variable, whereas the filter order and differential delay is fixed, 5  N and 1  M .

Figure 4 .

 4 Figure 4.28 presents the impulse response of the five stage CIC filter. The zeropole pattern of the CIC filter is also shown. As clear in the figures, The CIC filter has nulls at each multiple of the output sampling frequency R f f s  .

Figure 4 .

 4 Figure 4.25 Amplitude response of the CIC filter with different filter order

Figure 4 .

 4 Figure 4.26 Amplitude response of the CIC filter with different decimation factor

Figure 4 .

 4 Figure 4.27 Frequency and phase response of the CIC filter

Figure 4 .

 4 Figure 4.28 Impulse response of the CIC filter

Figure 4 .

 4 Figure 4.29 Pole-zero plot of the CIC filter

B

  input data word length the maximum number of bit in the CIC filter obtained by: is maximum word length of the filter output that is a function of the parameters, R, N and the Input bit width. Since the output of the integrators can grow without bound, max Brepresents the maximum number of bits which can be propagated through the filter without loss of data. max B is not only the maximum word length at the filter output; it is also the maximum word length for all sections in the CIC filter. max B is determined to avoid overflow in the CIC filter structure.The CIC decimation filter puts a constraint of the bit-size or the register width for the integrator and comb filter. Firstly the word lengths of the filter stages should not be increased. It means the each stage of the CIC filter must has greater size of the word length compared to next stage. Secondly the number of bit in the first filter stage which is first integrator must be greater than or equal to the quantity of Bmax.

  Figure 4.30, produces a CIC interpolator. The cascade differentiator operates at the low sampling frequency of R f s . The up-sampler in the filter structure increases a rate of sampling by factor of R. It is done by inserting 1  R zero valued samples between consecutive samples of the comb section output. Then the interpolated samples lead to the cascade integrator which is operated at high sampling rate of s f .

  1

Figure 4 .

 4 Figure 4.30 The interpolation CIC filter structure

Figure 4 .

 4 Figure 4.31 Block diagram of the M stage non-recursive Comb filter

Figure 4 .

 4 Figure 4.32 shows that each stage of M is included of N blocks non-recursive comb filter.

Figure 5 . 1 

 51 Figure 5.1 Block diagram of the CIC filter

  Figure 5.4 8-bit MCLA architecture

  Figure 5.6 PFA structure

Figure 5 .

 5 Figure 5.8 Estimated SNR vs. output resolution of the CIC filter

Figure 5 .

 5 Figure 5.10 8-bit pipeline adder in CIC structure

  Figure 5.11 Pipeline CIC filter architecture with truncation

Figure 5 .Figure 5 .

 55 Figure 5.12 N-bit RCAS subtractor architecture

Figure 5 .Figure 5 .

 55 Figure 5.15. The down-sampler is designed and implemented using Verilog HDL. The decimation factor is selected to be 16. The synthesis report of the Xilinx ISE software shows the maximum throughput of the down-sampler is 352.72 MHz. Decimation factor is defined by down sampler block.

Figure 5 .

 5 Figure 5.21 shows the down-sampler with the decimation ratio of 16. Downsampler creates low clock frequency for cascaded differentiator.

Figure 5 .

 5 Figure 5.22 and 5.23 show implementation of the one stage integrator and comb filter respectively in the CIC structure.

Figure 5 .

 5 Figure 5.24 and 5.25 show implementation of the RCSA and MCLA respectively. The RCSA is the subtractor when the "Sub" pin is connected to the voltage supply.

Figure

  Figure 5.18 5-order CIC filter block

Figure 5 .

 5 Figure 5.26 Schematic design of the CIC filter using ROM on FPGA board

Figure 5 .

 5 Figure 5.27 Successful implementation of place and route (PAR) the CIC filter in Xilinx synopsis ISE

  and power consumption by using Synopsys and Cadence tools. The technology libraries to do optimization are SilTerra 0.18 m  and MIMOS 0.35 m  . In this section the design is synthesized to convert from RTL code into the gate level. Timing constraints is defined to meet the final chip result. The RTL design code is divided into two parts, core and chip. The chip contains the top wrapper module that instantiates this core and puts I/O buffer pads along ports. In fact, analysis and simulation are required to ensure that the power supply is adequate. In this section the functionality of the Verilog behavioral CIC design is verified by Cadence Verilog simulation. In addition, the RTL model of the CIC design is converted into the Netlist (schematic).Using design compiler (Synopsys tool), the CIC filter is compiled and executed. Firstly, all the module and submodule in the CIC design are analyzed to check the Verilog syntax of the design. It is converted into intermediate format and stored in the specified library. Secondly, the top design is elaborated to convert the CIC into generic gates and logic blocks. The elaboration reports the memory elements in the CIC architecture. After elaboration process the overall system is checked for debugging the error. All errors are corrected to precede design to the next stage. Figure5.29 and 5.30show the symbol and schematic view of the CIC filter, respectively.

Figure 5 .

 5 Figure 5.29 Symbol view of the CIC filter

Figure 5 .

 5 Figure 5.31 shows the top level implementation of the CIC filter. All the filter components are located in the top level block (Figure 5.32). Figure 5.33-5.35 show the filter sub-blocks consist of differentiator, down-sampler and integrator. The CIC Filter in gate level after creating the netlist is shown in Figure 5.36 and 5.37.

Figure

  Figure 5.31 Top level implementation of the CIC filter

  Figure 6.1 Oversampling and decimation process

Figure

  Figure 6.3 Audio input signal

Figure 6 . 4

 64 Figure 6.4 Third-order sigma delta modulator output

Figure 6 . 5

 65 Figure 6.5 Signal to noise ratio of the sigma delta modulator

Figure 6 . 6 FigureFigure 6

 666 Figure 6.6 Frequency response of the fifth order CIC filter

Figure 6 .

 6 Figure 6.9 Frequency response of the 8-order halfband filter

Figure 6 .

 6 Figure6.12 Frequency response of the 14-order droop correction filter

  . The frequency response of overall decimation filter has the same specifications with the frequency response of second half band filter.

Figure 6 .

 6 Figure 6.16 Frequency response of all filter stages

  Figure 6.18 Passband ripple of overall decimation system

Figure 6 .

 6 Figure6.21 shows layout of the CIC filter active core using Silterra 0.18 m  technology. This layout was routed by Encounter tools. Figure6.22 demonstrates gate level output result of the CIC filter produced by NCLaunch using CAD tools.

Figure 6 .

 6 Figure 6.23 Implementation of the CIC filter on FPGA board

Figure 6 .

 6 Figure 6.26 shows the testing result of the FPGA board on logic analyser when the 25-bit CIC filter is downloaded. The clock frequency is set on the maximum rate (189 MHz).

Figure 6 .

 6 Figure 6.28 shows the integrator stage testing when digital quantized sine wave feed to the integrator. The output is increased without bounded which is the integrator property.

Figure 6 .

 6 Figure 6.29 illustrates the down-sampler stage testing when the input rate is changed to lower rate by decimation factor of 16. Every multiple data of 16 is kept to the register and the rest are discarded.

Figure 6 .

 6 Figure 6.30 demonstrates the comb stage result test when the integrator and down-sampler do not produce the output signal. This block limits the input data by subtractor.

Figure 6 .

 6 Figure 6.29 Down-sampler result test

  MATLAB tools are presented. The frequency response and digital output signal of decimation filters are given separately. This was found to give the required results of the overall frequency response with the Pass-band, Stop-band frequency and transition band of 21.77 kHz, 26.53 kHz and 4.76 kHz respectively. The simulation result also shows the Pass-band ripple less than 0.0001 dB. This chapter also demonstrates the FPGA implementation result of the CIC filter with the maximum throughput of 189 MHz in Xilinx synthesis report. For area and power consumption, the CIC filter was optimized in ASIC under Silterra 0.18 m  technology file. The Layout was shown in this chapter.

  of the CIC filter is tested by using Logic Analyzer which shows the operation of the CIC filter in maximum frequency of 189 MHz. A certain configuration was implemented to test different part of the CIC filter structure and the results were given.

Figure 7 Figure 7 . 1

 771 Figure 7.1 External control pin of the CIC fitter

Figure 7 . 2 Figure 7 .

 727 Figure 7.2 Performance of the CIC filter control pins

  The result shows that the chip size

	is	mm 308 . 0		mm 308 . 0	in Silterra 0.18	m  technology library and	mm mm 148 . 1 148 . 1 
	in Mimos 0.35

m  technology library. The speed improvement in decimation system is most important point of the research. The summation block which is called MCLA lead us to have high speed performance of the CIC filter. This adder is considered fast adder (270 MHz in 8 bit)

  requires adding more integrators (Figure2.8) however the circuit is highly unstable. Thus in this research we propose to use low-pass filter in order to obtain a stable sigma delta circuit but with improved SNR.

			C		C
		Sum		Sum		P(t)
	Input	∑ Amplifier + -	Integrator ∫	+ Amplifier -∑	Integrator ∫	Comparator + -1-Bit Analog /Digital Converter Serial Bit-Stream to the digital decimation filter
					+Vref
				1-Bit Digital/Analog	-Vref
				Converter
			Figure 2.8 Second order sigma delta modulator

Table 5

 5

		.1 CIC filter summary of Xilinx synthesis
	HDL Synthesis Report		Timing Summary
		QTY
		(Unit)
	25-bit adder	5	Minimum period (ns)	9.280
	25-bit subtractor	5	Maximum Frequency (MHz)	107.759
	4-bit down counter	1	Minimum input arrival time before clock (ns)	3.924
	1-bit register	1	Maximum output required time after clock(ns)	14.995
	25-bit register	11	Total equivalent gate count for design	5216
	4-bit register	1
	25-bit 2-to-1 multiplexer	1
	25-bit 2-to-1 multiplexer	1
	Number of 4-input LUT cells	253
	Number of external IOB	32
	Flip Flop Latch	280

  Notice that each 4-bit adder provides a group propagate and generate signal, which is used by the MCLA Logic block. The group Propagate

	c	4		g	3		(	p	3	.	g	2	)		(	p	3	.	p	2	.	g	1	)		(	p	3	.	p	2	.	1 p	.	g	0	)		(	p	3	.	p	2	.	1 p	.	p	0	. c	0	)	(5.13)
																																																						P and Generate	G of a 4-bit
																																																						out	out
	adder will have the following expressions:
																																		P G 	3 p	.		2 p	.	1 . p	0 p
								c	3		g	2		(	p	2	.	g	1	)		(	p	2	.	1 p	.	g	0	)		(	p	2	.	1 p	.	p	. 0	c	0	)	(5.12)
																																							81

  Table 5.2 and Figure 5.5 show the truth table and the logic circuit for the HA respectively while table 5.3 and Figure 5.6 show truth table and the logic circuit for the PFA respectively.

	Table 5.2 Truth table of the HA
	A	B	S	C

Table 5 .

 5 3 Truth Table of the PFA

Table 5 .

 5 4 Xilinx ISE synthesis summary for MCLA and CLA

	MCLA CLA

Table 5 .

 5 5 shows Xilinx ISE synthesis result after RCAS implementation. The Tableshowsthat the maximum throughput of the 8-bit subtractor is 219 MHz.As mentioned before, the down sampler block re-samples input data R times lower than the input rate. Offset sample must be less than R-1. To avoid any data lost at the beginning of the sampling, it is better to initiate the counter of the down-sampler by zero value.There are two down sampler types which are multirate down sampler and single rate down sampler. Down sampler is multirate when the output sample period is R times longer than the input sample period  

		Table 5.5 Xilinx ISE synthesis summary for RCAS
			RCAS
		Minimum period (ns)	219.010
		Maximum Frequency (MHz)	4.566
		Minimum input arrival time before clock (ns)	5.021
		Maximum output required time after clock(ns)	4.575
		Total equivalent gate count for design	96
	5.4	DOWNSAMPLER

Table 5 .

 5 6 Xilinx synthesis summary of the high speed CIC filter

	HDL Synthesis Report	Timing Summary
		No.
	MCLA (adder)	5	Minimum period (ns)	5.293
	RCAS (subtractor)	5	Maximum Frequency (MHz)	188.947
	4-bit down counter	1	Minimum input arrival time before clock (ns)	5.127
	Register	18	Maximum output required time after clock(ns)	4.575
	Multiplexer	2	Total equivalent gate count for design	6519
	Number of 4-input LUT cells	1344
	Number of external IOB	33
	Flip Flop Latch	273

  Table 5.7. Table 5.7 The estimated power and area result in different technology libraries

	The CIC	Silterra 0.18	m 	Mimos 0.35	m 
	specification	technology	technology
	Active core area   2 mm	308 . 0		308 . 0	148 . 1		148 . 1
	Power consumption   mW				3.14			6.03
	The schematic gate level of different components in the CIC filter is shown below. The
	filter in gate level is simulated by NCLaunch under Cadence software.

  The system was synthesized and shown that the CIC filter could operate with the maximum frequency of 97 MHz. Then the MCLA architecture is introduced to perform addition. Implementation result shows that maximum throughput of the 8-bit MCLA is 270 MHz. The new architecture of pipeline truncated high speed CIC filter was designed and programmed to the FPGA board. The

							CHAPTER VI
	Xilinx synthesis result shows that the filter can work with the maximum clock
	frequency of 189 MHz.
		Additionally, the CIC decimation filter was also synthesized in SilTerra
	0.18 m  technology and the MIMOS 0.35
	3.14 mW and	308 . 0		308 . 0	2 mm respectively in Silterra 0.18	m  technology and 6.03
	mW and	148 . 1		148 . 1	2 mm respectively in Mimos 0.35	m  technology.
							116

m

 technology. After synthesizing and constrained definition, the CIC filter netlist (gate level) was created to produce ASIC layout. The design compiler result shows the filter power consumption and die area of

  works under normal condition and the result can be evaluated. Figures 6.28, 6.29 and 6.30 show the result of testing different stages of the CIC filter.

	If signal 1 C , 2 C and 6 C are C is low, down-sampler provides output signal. If 3 high and signal 5 C , 4 C and 6 C are low the comb stage is tested and when 1 C , 2 C and 6 C are low and then 3 C and 4 C are
	high the system

LIST OF FIGURES

pipeline integrator is implemented by moving the feedback register to the location of the pipeline register (Djadi et al. 1994). This results the pipeline implementation of the integrator but with less one register for every integrator stage which is similar to the structure of the non-pipeline integrator. The CIC decimation filter clock rate is determined by the first integrator stage that causes more propagation delay than any other stage due to the maximum number of bit. Thus the high clock rate is used at the integrator of the CIC filter, to obtain high throughput. The clock rate in integrator section is R times higher than in the comb section. As shown in Figure 5.11, pipeline architecture is used for the integrator, comb and down sampler that results in a further increase of the CIC filter throughput by 20 MHz.