Sérgio Onofre
email: onofre@holos.pt

Bernardo Caseiro
email: b.caseiro@campus.fct.unl.pt

João Paulo Pimentão

Pedro Sousa

Using Fuzzy Logic to Improve BLE Indoor Positioning System

Keywords: Fuzzy Logic, indoor location techniques, Bluetooth low energy, trilateration

Accuracy and precision are key parameters in the definition of indoor positioning systems. We want to provide a mobile robot with the capacity to autonomously determining its location inside buildings, to allow it to autonomously navigate. The solution developed is based on spreading emitter beacons of Bluetooth Low Energy in the building and use location finding techniques to determine the robot's location. The main challenge is the capacity to obtain accurate readings of signal strength and the low repeatability of readings even under unchanged conditions. To improve the signal strength measurements it is necessary to deal with this imprecision. Our approach is based on the use of Fuzzy Logic to deal with the accuracy problem. Once better signal strength readings are achieved, using this method, approximate distances are calculated based on signal strength and the trilateration method is implemented to provide the location of the mobile robot.

Introduction

Indoor location is an emerging market that can be used for commercial purposes, public safety, and military. Commercially it can be applied to track children, people with special needs, help navigate blind people, locate equipment, mobile robots, etc. For military and public safety it will be useful to track prisoners, help policeman, soldiers and firemen navigate inside buildings [1].

Location and outdoors navigation was solved long ago with GPS. The problem occurs when you need accuracy or indoors location. GPS nowadays have an error of about 10 meters, radio signals coming from distant satellites don't work well with obstructed paths and the high-frequency waves bounce around when they hit metal and walls. This technology is therefore not usable on indoor location issues [START_REF]New Indoor Navigation Technologies Work Where GPS Can't -IEEE Spectrum[END_REF].

Actually there are some companies searching and testing solutions using different technologies to find a solution for indoors location. In general, the most important components of the system are location sensor devices that produce metrics of the relative position of a mobile terminal (MT) and a known reference point (RP). Most conventional positioning methods are Angle of arrival (AOA) to estimate direction; received signal strength indicator (RSSI), Time difference of arrival (TDOA) and Time of arrival (TOA) are used to estimate distance [1].

Our goal is to provide a mobile robot (ServRobot 1 ) with a tool to know is location using Bluetooth Low Energy beacons signals.

Cyber Physical Systems

The cyber-physical systems (CPS) consider computational components and physical units to cooperate with humans using different technologies. CPS are intelligent, realtime, distributed, networked (wired/wireless) control systems and likely linked in a loop. They can be useful in several fields. CPS design consists of a network of cooperating elements with physical inputs and outputs. It connects computational and physical rudiments to obtain better effectiveness, functionality, security and flexibility [START_REF] Reddy | Cyber-Physical Systems : Survey Cloud-based Cyber Physical Systems : Design Challenges and Security Needs[END_REF].

This work is related to cyber-physical systems, by combining physical entities: Bluetooth Low Energy (BLE) beacons, with computational elements that through a BLE signal receptor connected to a computer, allows to process the input values and implement algorithms to build the desired system. The final goal is to locate an autonomous mobile robot in a wireless network in real time that could be adapted in the future to locate other objects like phones or even people. It consists on build a system in real-time with feedback loops where physical processes, in this case the received signal strength indicator from the BLE beacon affect computations and have influence on the robot next moves and upgrade others functionalities by knowing the robot location, it can improve the efficiency, safety, reliability and functionality of the mobile robot.

This project could help the research on efficient and functional indoor location systems contributing for the cyber physical systems development too.

State of the Art

Conventional Positioning Methods

In the next sections, several conventional positioning methods are presented. RSSI -It is a process used to estimate the distance between the receiver and a beacon. It matches the probability distribution with the strength of the received signals, and estimates the distance using a statistical method. To start a sample of the signal strength is read in different locations, but the environment changes modify the path loss models that enables to repeat the same strength of the received signal. It is necessary an environment precise path loss model to use the location estimate system [START_REF] Park | Localization Algorithm Design and Implementation to Utilization RSSI and AOA of Zigbee[END_REF].

AOA-This method is used to measure the direction in a system and it can do it reading the direction of the received signal using two or more antennas on different positions [START_REF] Park | Localization Algorithm Design and Implementation to Utilization RSSI and AOA of Zigbee[END_REF].

TOA -It is a time-based positioning technique that measures the signal travel time between nodes [START_REF] Roxin | Survey of Wireless Geolocation Techniques[END_REF].

TDOA -This method estimates the time difference of arrival between two signals moving between two reference nodes and the given node [START_REF] Roxin | Survey of Wireless Geolocation Techniques[END_REF].

Table 1 compares the accuracy degradation of an indoor location system due to multipath fading and increase of the distance between devices for each positioning method.

Indoor Location Systems

There are different location determination systems and processes for indoor environments: ultrasound, infrared, electromagnetic, visual location, physical contact and radio frequency systems. We will focus on radio frequency systems.

Bluetooth based systems -Radio hardware (beacons) with Bluetooth low energy protocol. Beacons are spread over surface and the signals that they send can enable devices to determine their location. Some systems use beacons signal to incorporate on fingerprints database, others determine absolute or relative location by measuring distances, trilateration. Furniture and walls hinder signal propagation. Using three beacons is enough but a fourth one will decrease localization errors [START_REF] Akif | A Bluetooth Signal Strength Based Indoor Localization Method 7[END_REF]. Indoor location is challenging because of the reflections and absorptions. Besides Bluetooth Low Energy there are Wi-Fi, RFID, ZigBee and Ultra-Wideband based systems. More details in [7,[START_REF] Liu | The Research and Design of the Indoor Location System Based on RFID[END_REF][START_REF] Fernández | Indoor Location System based on ZigBee devices and Metric Description Graphs[END_REF]. Some developers combine multiple technologies like fusing data based on Wi-Fi and Bluetooth. Fusing helps to obtain more accurate results.

Location Techniques in Indoor RF-based Systems

There are two types of techniques to calculate the location using RF-based systems, geometric (traditional) and pattern recognition.

Geometric techniques -calculate positions based on distances between mobile transmitter-receiver and fixed receiver-transmitter. Trilateration -Provides an estimate of the device's location by using the received signal strength from different transmitters (non-linear). The distance estimation from the transmitters to the receiver is calculated using the relation between distance and signal strength:

(1) Pt is the transmitters power (in dBm), Pr is the power at the receiver, λ is the wavelength, n is the path loss exponent (n=2 is free space), d is the distance transmitter/receiver. The distance estimation generates a circle centered on each transmitter, the device will be located where circles coincide. The technique is called trilateration [START_REF] Liu | Survey of Wireless Indoor Positioning Techniques and Systems[END_REF]. Triangulation -Uses geometric properties of triangles to estimate the target's location. More details in [START_REF] Liu | Survey of Wireless Indoor Positioning Techniques and Systems[END_REF].

Pattern Recognition techniques -It consists in buildin a signal strength model. To estimate the mobile device's location is necessary to calculate the match with the signal strength model. It requires two phases: the offline phase, where a map is built after collecting the RF signals from defined location points. And the online phase, where an algorithm is used to find the match between the read signals and the previously collected signals to estimate the device location [START_REF] Roxin | Survey of Wireless Geolocation Techniques[END_REF]. Traditional methods are K-Nearest Neighbors, Neural Networks and Probabilistic. More details in [START_REF] Lin | Performance Comparison of Indoor Positioning Techniques based on Location Fingerprinting in Wireless Networks[END_REF].

Fuzzy Logic

Fuzzy Logic is bets fit on under uncertainty, it deals automatically with tolerance for imprecise values. The variables are represented by membership functions, instead of the absolute true or false values. It reproduces the human mind capacity to employ approximate reasoning. In classic logic the decision is binary, true or false, whereas in Fuzzy Logic variables have a range between 0 and 1, of degree of membership towards a fuzzy set [START_REF] Singh | Fuzzy logic based clustering in wireless sensor networks: a survey[END_REF]. Imprecise inputs can be considered and used as "linguistic variables" denoting values such as big and small, low/medium/high are used in the model. Common membership functions used in Fuzzy sets are triangular, Gaussian, trapezoidal, etc, although triangular (see fig. 2) is more widely used. Figure 3 shows the block diagram of fuzzy logic mechanism. Fuzzification is a procedure that classifies numerical values into fuzzy sets, the rule base contains the IF-THEN rules that represent the linguistic variables. The evaluation relates the IF-THEN rules to the fuzzy sets to get a fuzzy output. The Fuzzification changes crisp data into linguistic values using linguistic variables, membership functions map every element of the input variables onto a membership rate from 0 to 1. The evaluation makes approximate reasoning [START_REF] Singh | Fuzzy logic based clustering in wireless sensor networks: a survey[END_REF].

The defuzzification procedure alters the fuzzy output back to the classical output with the control goal. There are three defuzzification techniques normally used, the most widely used is the Center of Gravity method (COG) is identical to the physical calculation of center of gravity in objects, the weighted average of the membership function of the center of the gravity of the area limited by the membership function curve is computed to be the crispest value of the fuzzy values. Besides COG there are Mean of Maximum and Height Methods [START_REF] Singh | Fuzzy logic based clustering in wireless sensor networks: a survey[END_REF].

Development

Our system development starts with the interaction between a BLE transmitter (beacon) and the BLE receptor (sniffer).

Bluetooth low energy sniffer and beacon

To receive the received signal strength indicator (RSSI) from the beacons a Bluetooth low energy sniffer (Adafruit bluefruit LE Sniffer nRF51822) is used. This device is a USB-to-BLE board that allows the computer to communicate with a BLE enabled device. The Gimbal U-Series 5 proximity beacon is a small, USB powered device that transmits a Bluetooth Low Energy signal that can be detected by other devices, in this case by the Bluetooth Low Energy sniffer. This signal enables the identification of the beacon by the MAC Address. The sniffer captures the RSSI value and with it it's possible to calculate the distance estimation between the devices.

Obtaining distance from RSSI values

The code used by the device Adafruit bluefruit LE Sniffer nRF51822 is written in python and allows to retrieve the RSSI and MAC address of nearby BLE beacons, this project uses that code as start point. To obtain the distance in meters from the received signal strength indicator (RSSI) it was necessary to measure a bunch of RSSI measurements at known distances, then we did a best fit curve to match the data points, this algorithm was developed by David Young in Java. In this work the code was adapted to python language [START_REF] Young | Understanding ibeacon distancing -Stack Overflow[END_REF].

(2)

The variable txPower is the RSSI value at 1 meter of distance, it was calibrated and the obtained value was -87 db. The values 0.89976, 7.7095 and 0.111 are the three constants calculated when solving for a best fit curve to the measured data points. Each 0.95 seconds a distance reading is received, the main challenge is the capacity to obtain accurate readings of signal strength (and consequent approximate distance in meters) given the low repeatability of readings even under unchanged conditions. The direct signal strength measured by the Bluetooth signal receiver vary in each reading because of physical disturbing factors such as wall reflections and other devices transmitting the same frequency. To improve the measures, two normalizing techniques: "median and average filters" and "Fuzzy Logic" were implemented.

Median and Average Filters

After some tests comparing the real distance measured with a scale and the distance obtained at the program by the sniffer it was detected that the accuracy is bad and has low repeatability of readings. To try to improve the accuracy and the repeatability, a way to discard the absurd values on was developed. First a vector accumulates ten measurements and after that the values are sorted, the extremes are excluded and the four middle values are used to calculate the average. However, as the results were still far from good, since they were imprecise we decided to use another approach. Using Fuzzy Logic to deal with imprecision.

Fuzzy Logic implementation

To deal with imprecise values we decided to use Fuzzy Logic. This could be a good way to improve the results. The tool used was an open source java library called jFuzzyLogic. This library imports a Fuzzy control language file with the input and output variables and the linguistic terms configured, then checks the rules to return an output variable based on inputs. We take the results of the median process and in the end it will return only one output variable with the final value. For each of the four inputs there are twelve linguistic terms possibilities to do the fuzzification ranging from "less 0.5m" to "more 5m". Then the system will check the rules block with 23 rules and makes the decision (Fuzzy inference). To finish the defuzzification is done and a real value is obtained as output. Considering ten direct distance measures read by the sniffer at 1 meter away from the beacon (real distance), the four middle values are selected as inputs for the FCL file and each of them is fuzzified. Then the system checks the rules block, makes the decision and does the deffuzification to obtain a real value as output. In our test the final distance output is 1.02 m, close to the real distance 1 m. The defuzzification technique, Center of Gravity method was used.

Distance readings results

Three different ways to obtain the distance between the BLE beacon and BLE sniffer were tested in an office room without objects between the devices. The first method uses direct distance readings each 0.95 seconds, the second method applying median and average filters after ten direct readings and third method implements a fuzzy logic inference system after ten direct readings. The BLE beacon was fixed on a power supply and the BLE sniffer connected to a computer was positioned at different distances measured by a scale at 0.5m, 1m, 1.5m, 2m, 2.5m and 3m. The test values were obtained ten seconds after fixating the BLE sniffer position to guarantee receiving a stabilized signal. The following graphics compare the measurements obtained by the three methods:

Conclusions and Future Work

After doing these tests with the three methods some behaviors of the receiving signal were detected. The signal takes some time to stabilize after changing the distance between the beacon and the sniffer. It is necessary to wait some seconds until the values get closer to the real distance. Once the signal stabilizes the repeatability increases. In general as the distance between the beacon and the sniffer increases, the average error of distance estimations increases. That is an expected behavior because the disturbing factors like signal reflecting rise their negative influence as long as the direct signal wave power (the desired one) gets lower.

Comparing the direct readings average error and the estimations after applying median and average filter average error, the results of applying the filter are not as good as expected. That can be explained because even maintaining the sniffer at same fixed position when the distance estimation gets high or low it tends to still get higher or lower with time. The normalizing factor by applying median and average filter excludes the estimations that usually are far from real distance, but due to the trend to the estimation to get high or low with time, it doesn't improve the average error. In practice the average error obtained by direct readings method is similar to the average error applying median and average filter. Comparing the direct readings average error with the Fuzzy Logic inference system estimations average error, the implementation of Fuzzy Logic reduces the error between real distance and estimation, improving the accuracy and the repeatability. This normalizing method proved to be more satisfying that Median and Average method. It proved to be useful improving the estimation values and Fuzzy Logic inference system was adopted in this project. The next step will consist in implementing the trilateration algorithm after obtaining the estimated distance between three fixed BLE beacons in known positions at x, y coordinates and the BLE sniffer which is in an unknown position and can move.

Figure 2 .

 2 Figure 2. Triangular Fuzzy membership function[START_REF] Singh | Fuzzy logic based clustering in wireless sensor networks: a survey[END_REF]

Figure 3 .

 3 Figure 3. Fuzzy Logic Block diagram[START_REF] Singh | Fuzzy logic based clustering in wireless sensor networks: a survey[END_REF]

Figure 4 .Figure 5 .

 45 Figure 4. Distance Estimations at 0.5 meters

Table 1 .

 1 Comparison of position methods[START_REF] Roxin | Survey of Wireless Geolocation Techniques[END_REF]

		Accuracy Degradation
	Method	Multipath	Distance
	TOA/TDOA	Slightly	None
	AOA	Sligthly	Sligthly
	RSSI	Severely	Slightly

Table 2 .

 2 Radio frequency based systems[START_REF] Li | Low-Cost 3D Bluetooth Indoor Positioning with Least Square[END_REF]

		Frequency band Power consumption	Cost	Accuracy (meters)
	Wi-Fi 802.11	2.4 GHz	high	high	5 to 10
	RFID	Multiple	low	very low	2 to 10
	Bluetooth 4.0	2.4 GHz	low	low	1 to 2
	ZigBee	Multiple	low	low	3 to 5
	UltraWideBand 3.1 to 10.6 GHz	low	low	< 2

Table 3 .

 3 Average error for each method at different distances

		0.5m	1m	1.5m	2m	2.5m	3m
	Direct Readings	0.101	0.148	0.096	0.449	0.285	0.194
	Median	0.082	0.235	0.252	0.300	0.306	0.243
	Fuzzy Logic	0.028	0.115	0.136	0.050	0.118	0.193


Bruno Dos Santos

Rui Esteves

Initial Study on Fault Tolerant Control with Actuator Failure Detection for a Multi Motor Electric Vehicle

Keywords: Fault Tolerant Control, Fault Detection and Isolation, Unknown Input Observer, Electric Vehicles

This study presents a scheme to detect and isolate faults in overactuated electric vehicles. Although this research work is still emerging, it already provides a view of the main challenges on the problem and discusses some possible approaches that can be useful to overcome the key difficulties. This paper intends to present a fault detection algorithm based on Unknown Input Observer (UIO). The residuals are built through the difference of signals between the measured outputs and the output estimations from the observer. The main idea is to detect fault in the electric motors and steering wheel actuator. The algorithm is presented and tested with some fault scenarios using the co-simulation tool between Simulink/MATLAB and the high-fidelity model from Carsim software.

Introduction

The road map on road transport published by ERTRAC, EPOSS and SMARTGRIDS in 2010 had the expectation that the adaptation of conventional vehicles to electric power train is the first milestone [START_REF] Ertrac | SmartGrids: European Roadmap Electrification of Road Transport[END_REF]. At the present stage, most compact electric vehicle is based on today's drive train platforms with one central electric motor. However the potential of novel power drive concepts is not completely achieved with these first generation vehicles. Multiple electric motors mounted close to the wheels or even in the wheel open the development of new compact vehicle drive train architectures.

System redundancy could be explored in order to have high safety and robustness requirements. The system redundancy in multi-motor electric vehicles should be exploited. If an actuator fails, it is necessary to redistribute the control effort among the healthy actuators such that stability is retained. Some accidents are prevented by using mechanism that detect and inform the driver about a fault. Between July 2005 and December 2007 6.8% of all accidents are something related with some vehicle malfunction [START_REF]National Motor Vehicle Crash Causation Survey Report to Congress[END_REF]. In the next section will be focused on the formulation of the Research Questions that need to be answer with this PhD work.

Research Question

Research Question 1: How can we improve the architecture of the fault tolerant control with Fault Diagnosis for four-wheel independently driven electric vehicle?

The key idea to be explored is to replace the standard control allocation by the concept of "smart control allocation" in order to improve the overall structure. The main objective of the smart control allocation is to ensure that the system adapts in the best way when an actuator fails.

A general overview of control architecture is shown in the fig. 1. The reconfigurable allocator uses information provided by the fault diagnosis to accommodate faults by performing an appropriate reconfiguration. The fault diagnosis system uses the signals from the Hardware and IMU (Inertial Measurement Unit) sensors with Unknown Input Observer (UIO) algorithm to detect faults. The fault diagnosis system output will be a set of fault flags. This information will be interpreted as the total fault indicator vector, which will be an input for the reconfigurable allocator. The relationships between actuators states, fault type and remedial actions will be defined in the fault code table in order to specify the constraint bounds of the control allocation algorithm. Research Question 2: How should we exploit the fault tolerant detection subsystem to implement an active Fault Tolerant Control (FTC) for multi-motor electric vehicles?

If we started by investigating how the use of the information provided by the Fault Detection (FD) scheme, we could help to improve the active FTC performance. One of the biggest challenges of this thesis is the FD capability to send useful information to the controller. To be useful, the information sent to the controller has to be accurate and needs to be on time. Although some losses in accuracy can be compensated by using robust control techniques, also the delay issues will be crucial. The response time or detection test time needs to be the slowest possible in order to maximize the fault reaction time.

Contribution to Cyber-Physical Systems (CPS)

From the automotive electronic point of view, the modern vehicles contain a large number of CPS's such as Anti-Lock Brake Systems, Traction Control, Electronic Stability Program, etc. The same happen for the electric vehicles. The tight interaction between all the computational devices like the battery management system, electric drives of motors and the physical components brings many challenges in this field. For safety and efficiency reasons, these spatially distributed components require a sophisticated monitoring and control. For this purpose, a paradigm change for Electrical and Electronic (E/E) architectures becomes necessary to increase the flexibility between elements [START_REF] Sankavaram | An integrated health management process for automotive cyber-physical systems[END_REF].

Functional safety is taking more importance in electric vehicles development, due the increased complexity and the wide employment of electrical and electronic systems. In contrast with the past, it will be more important for automotive industry to put in place a normative process to assure the reliability of the safety-related systems, as opposed to regulate themselves with different rules [START_REF] Boules | Reinventing the Automobile: The Cyber-Physical Challenge[END_REF].

In order to ensure functional safety the automotive functional safety standard was launched (ISO 26262) [START_REF]ISO: ISO/DIS 26262 -Road vehicles -Functional safety[END_REF] to solve the problem of components faults in electrical and electronic system in vehicles. This standard is an adaptation of the IEC 61508 and overcome all the lifecycle of electrical/electronic components. Some metrics introduced by the norm can be useful to quantify the fault tolerant control performance.

State of the Art

The literature presents numerous FDI applications for aeronautical and aero-space systems, chemical process, nuclear plants, power system, automotive and electronic systems, see for example [START_REF] Isermann | Model-based fault-detection and diagnosis -status and applications[END_REF] or [START_REF] Zhang | Bibliographical review on reconfigurable fault-tolerant control systems[END_REF]. Also a FDI for the ROboMObil, a concept car, was designed and tested in real operating conditions on DLR (Deutschen Zentrums für Luft-und Raumfahrt) institute. They used the well-known parity equation to detect faults in sensors and actuators [START_REF] Ho | Fault Detection and Isolation of Vehicle Dynamics Sensors and Actuators for an Overactuated X-by-Wire Vehicle[END_REF]. Also, the work started by Rongrong Wang in his PhD thesis at Ohio State University [START_REF] Wang | Fault-Tolerant Control and Fault-Diagnosis Design for Over-Actuated Systems with Applications to Electric Ground Vehicles[END_REF] demonstrates the significance of having a FDI scheme to the same type of vehicles.

Only few papers about fault tolerant control of over actuated electric vehicles consider the fault diagnosis in their studies, others assuming that the faults are perfectly identified [START_REF] Lopes | Fault-tolerant control based on sliding mode for overactuated electric vehicles[END_REF]. However, this is not a realistic hypothesis since fault diagnosis is a very challenging topic, especially for non-linear systems.

In this paper is presented an FDI system based on a Linear Parameter Varying (LPV) UIO scheme. The idea of this approach is to represent the nonlinearities inherent in the model by a LPV approach. Then, the way to use the proposed LPV model is to develop a bank of UIOs that generates a set of residuals which will be sensitive to a pre-established set of faults while insensitive to the others which are considered as disturbances.

Vehicle Model

The vehicle modeling is composed by several physical quantities represented in a three coordinate system. The dynamics behavior is based on Euler and Newton laws of motion. The system axis (x,y) is fixed in the vehicle Center of Gravity (CoG), and the movement is based on CoG's velocities and forces:

ݒ ௫ ሶ = ݒ ௬ ݎ + ܨ ௫ ݉ , ݒ ௬ ሶ = ݒ- ௫ ݎ + ܨ ௬ ݉ , ݎሶ = ܯ ௭ ܫ ௭ (1)
Where v x is the longitudinal speed, v y is the lateral speed and r is the yaw rate. Through a simplified Euler-Newton equation system it is possible to represent the vehicle behavior as function of the longitudinal force F x the lateral force F y and the yaw moment M z applied in the CoG. These virtual forces are the forces that act to move the vehicle. The virtual inputs are related width the tire forces by:

ݒ = ሾܨ ௫ ܨ ௬ ܯ ௭ ሿ, ݒ = ܨܤ ௫௬ ݒ = ൦ 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 - ݈ ௦ 2 ݈ ݈ ௦ 2 ݈ - ݈ ௦ 2 -݈ ݈ ௦ 2 -݈ ൪ ܨ ௫௬ ܨ ௫௬ = ሾܨ ௫ி ܨ ௬ி ܨ ௫ிோ ܨ ௬ிோ ܨ ௫ோ ܨ ௬ோ ܨ ௫ோோ ܨ ௬ோோ ሿ ሾܨ ௫ ܨ ௬ ሿ = ߜሺݏܿ ሻ -݊݅ݏሺߜ ሻ ݊݅ݏሺߜ ሻ ߜሺݏܿ ሻ ൨ ܨ ܨ ൨ , ݅ ∈ ,ܮܨ{ ,ܴܨ ,ܮܴ ܴܴ} (2)
Where F ci and F li are the centripetal and longitudinal tire forces applied to the ground. In order to define the tire forces, the Pacjeka semi empiric model can be employed [START_REF] Pacejka | Tire and Vehicle Dynamics[END_REF]. In this section we assume that the forces are in the linear part of the tire function and also that the side slip angle for each tire is small and the difference between the torque input and the longitudinal force is zero (F li -T i r i ≈ 0). At this stage of the work we assume that the torque signal send to the in-wheel actuator is a combination of the motor and brake system signals. So the tire force components are:

ܨ = ܰ ⋅ ܦ ቆߜ - ݒ ௬ -݈ ݎ ݒ ௫ ቇ , ܨ ೌ = ܰ ⋅ ܦ ሺ ݒ ௬ -݈ ݎ ݒ ௫ ሻ ܨ = ܶ ܴ (3)
where T i is the input torque to each in-wheel motor, δ i is the steering angle in each wheel (δ i = 0 for the rear wheels and for the front wheels the steering angle is equal to the command input). Also N i is the normal force applied in the wheel; D i is the cornering stiffness; l f and l r are the distance from the CoG to the front and rear axis.

Fault Detection System through LPV UIO

In order to detect actuator faults, the command inputs from the driver are sent to the force observer. The virtual force observer is obtained applying the equations [START_REF] Ertrac | SmartGrids: European Roadmap Electrification of Road Transport[END_REF][START_REF]National Motor Vehicle Crash Causation Survey Report to Congress[END_REF][START_REF] Sankavaram | An integrated health management process for automotive cyber-physical systems[END_REF]. This estimator determine the value of each virtual forces that are delivered to the vehicle. As a result, the state reconstruction is carried out by a bank of UIOs using the virtual force provided by the force observer with different outputs. With the purpose to achieve isolation of faults, the inputs (individual virtual forces) need to be divided into groups and selected the output related with the fault in consideration.

LPV UIO

In this work, it is considered that only one actuator fault is detected by each UIO. More details about the UIO observer can be found in [START_REF] Ichalal | On Unknown Input Observers for LPV Systems[END_REF]. For a LPV system like:

ቊ ݔ ˙ሺݐሻ = ܣሺߩሻݔሺݐሻ + ܤሺߩሻݑሺݐሻ + ܦሺߩሻ݀ሺݐሻ + ܤ ௦ ሺߩሻ݂ ௦ ሺݐሻ ݕሺݐሻ = ሻݐሺݔܥ (4)
where

x(t)∈ ℝ n ; u(t)∈ ℝ m ; d(t)∈ ℝ d ; y(t)∈ ℝ p ;
and f s (t) ∈ ℝ 1 ; are the state vector, input vector, perturbation vector, output vector and fault vector, respectively. The distribution matrix for the fault is represented by the corresponding column number (s th ) of B (B s ). The parameter ρ(t)=[ ρ 1 ,…, ρ r ] ∈ ⅅ is a time varying function. The requirements to LPV system are: all the matrices are affine in ρ; the parameter ρ is accessible; as well as the ρ and ρ are bounded. We are going to first transform the system into is polytopic form:

ܣሺߩሻ = ℎ ሺߩሺݐሻሻܣ ௩ ୀଵ
, with: ℎ ሺߩሻ > 0 and ℎ ሺߩሺݐሻሻ = 1

ୀଵ ( 5
)
where v is the number of vertices limits of ρ. The new system is described by:

൞ ݔ ˙ሺݐሻ = ℎ ሺߩሻሺܣ ݔ + ܤ ݑ + ܦ ݀ + ܤ ௦ ݂ ௦ ሻ ௩ ୀଵ ݕሺݐሻ = ݔܥ (6)
This structure allows the usage of linear UIO for the transformed system:

ە ۔ ۓ ݖ ˙= ℎ ሺߩሻሺܨ ݖ + ܩ ݒ + ܭ ݕሻ ௩ ୀଵ ݔ ^= ݖ -ݕܪ (7)

Simulations

The proposed LPV-UIO scheme has been simulated in different case scenarios. The nonlinear vehicle model was simulated through the Carsim software in co-simulation with Simulink/MATLAB where the proposed observer was implemented. The vehicle parameters that have been used to perform simulations are on the table 2.

In order to demonstrate the capacity to detect faults in actuators it is defined two fault scenarios: The first, a J-turn maneuver with steer fault in constant acceleration with faults in two of the four motors. In this simulations only abrupt fault are considered (step). The fault amplitude is for the steering test a part of the steering input. For the wheel test it is always considered the total failure of the motor in-wheel unit. The inputs of torque to wheel and steering angle reference from the driver are the system input.In the simulations, when a fault occurs, the same fault has to be signalized by an alteration in the residual for each component. The residual amplitude has to be greater than a certain threshold in order to signalize that there is a fault.

Steer Fault -The vehicle starts with an initial longitudinal speed of 20 m/s with no steer input. At the time t=1s the steering angle is set in 0.05 rad. This steering is kept constant for the entire test. In this simulation, several faults input have been tested. From the Fig. 2 it is possible to see that the vehicle global trajectory is affected by the steering fault. At the moment when steering input is set to 0.05 rad, the residuals have a slightly change that are negated by the observer. When at t=5s the fault are injected in the system, all residuals reflects the actuator faults. Obviously the steering fault impact has more influence in the residual provided by the second UIO and from M z . The steering component has more impact in these residuals. In-wheel Motor Faults -In the second test, the vehicle starts with equal initial speed of the first test v x =20m/s. In this case the steering remains δ =0º rad for the entire test. At t=5s in-wheel motor faults combinations are injected in the system. The residuals for this test are shown in the Fig 3 . The first point to notice is that the faults in wheels are signalized with low amplitude signals. It is because the faults have low contribution to the trajectory. Also, it is necessary to point out that the observer gain is very low, approximately 10 -3 . However the trajectory deviation is not large. Also, in the residual in F x the value in a non-fault case is not zero due to the longitudinal friction forces that were not modeled in Equation (1).

Conclusions and Future Work

This work considers the design of UIO for use in fault detection for an over-actuated electric vehicle. Although research work is in its first steps, it already provides an overview on the problem while discussing some possible approaches and proposes a method to overcome the key difficulties. Simulation results show a good performance in order to detect several types of faults. Future work, currently under way, includes find a way that does not use the information about lateral velocity as well as implement a validation of the proposed scheme on the prototype vehicle.

Fig 1 -

 1 Fig 1 -Proposed FTC structure in the PhD.

Fig 2 -

 2 Fig 2 -Results for the steer fault test.

Fig 3 -

 3 Fig 3 -Results for the in-wheel motor fault test.

Table 1 -

 1 UIO Algorithm design for planar motion;

Table 2 -

 2 Vehicle Parameter used in the simulations

Acknowledgments. This work is partially funded by National Funds through FCT -Science and Technology Foundation, through the scholarships SFRH/BD/90418/2012.

The goal is that estimation error (e(t)=x(t)-x(t)) converges to zero under any initial conditions and any input. Replacing the estimate error expression from eq [START_REF] Zhang | Bibliographical review on reconfigurable fault-tolerant control systems[END_REF], it follows that e=T x -z, where T=I-H C (note that the index i is omitted). Solving this equation for the time derivative of the error gives:

In order to design the UIO, is necessary to meet the conditions:

Thus, if all conditions are respected the UIO error dynamics becomes ė =Fe+TB s f s and the residual correspond to r=Ce(t). For the disturbance decoupling, first it is necessary to check if rank(CD)=rank(D) to guaranteed a solution for the system HCD = D (from the condition (C2) and (C6)). One generalized solution for H can be expressed by [START_REF] Darouach | Full-order observers for linear systems with unknown inputs[END_REF]:

where (X + ) is the generalized inverse matrix given by (X) + =((X) T (X) -1 )(X) T , since X is full rank. H 0 is arbitrary matrix of appropriate dimensions and give some freedom on the design. The eigenvalues of F can be arbitrary located by choosing a suitable matrix L, only if the pair (TA,C) is observable. For LPV systems the condition (rank(CD i ) = rank(D i )) for the linear decoupling is not sufficient, it is necessary that

)) in order of to obtain (HCD ρ =D ρ ). Also the polytopic stability of (L i ) is subject to the global stability of F=TA ρ -L ρ C where (X ρ ) are all matrices from the "LPV space").

UIO design -The system in eq. ( 1) can be written into a LPV for the (x,y) dynamics. The LPV system has following parameters:

The residual in yaw rate dynamics is the difference between the models in a nonfault scenario with the read values. The UIO algorithm design is presented in Table 1.


Paulo Mendonça
email: paulo.mendonca@tecnico.ulisboa.pt

Duarte M Sousa
email: duarte.sousa@tecnico.ulisboa.pt

Scalar Variable Speed Motor Control for Traction Systems with Torque and Field Orientation Filter

Keywords: Variable speed, motor control, electric traction

Scalar traction control systems can be used in trains, trams and electrical vehicles equipped with induction motors. To increase the versatility and efficiency of such systems compared to conventional solutions, they must enable dynamic links to different types of power grids, i.e., be supplied by multi-frequency and multi-voltage power sources. Behind these solutions, there are control systems based on vectorial controllers. In order to set systems with the above features, in this work it is intended to build a scalar traction control system, in which the speed is controlled via a scalar controller. The system controls the motor speed and also the position of the rotor and stator fields. Furthermore, it allows to clearly setting the operation conditions, i.e., avoiding situations that would change from braking to traction and vice-versa due to operational and/or functional disturbances. To achieve the required speed reference follow up, the proposed solution includes a torque and field orientation filter.

Introduction

Nowadays are commercialized several types of electrical vehicles, both road and rail vehicles, but in the near future it is expected that even more electrical vehicles will be manufactured. Besides the electrical vehicles, there are several industrial systems and solutions based on different types of electrical motors. The main purpose of this is to build a command variable speed system, for a rail traction system based on an induction motor, in which the speed is controlled instead of the torque and the controller is scalar and not vectorial. In addition, the proposed system allows avoiding undesirable situations, as for instance, changing from braking to traction and viceversa due to operational and/or functional disturbances.

To build this system, which is a part of a larger traction system that is being developed in a PhD thesis, it was used as core systems a three arm inverter, a triphasic induction motor and a constant DC voltage source [START_REF] Mendonça | An approach to recover braking energy of a tram[END_REF]. The inverter uses IGBT semiconductors, and they are controlled via a PWM SVM controller, which can be disenabled by the main control system. This drive system must be adaptable to the different power grids used in the railway sector, i.e., be designed considering the requirements of multi-frequency and multi-voltage power supplies. Technically, should also constitute a step forward of other requirements and features, such as energy efficiency, energy recovery, service interruptions, interoperability of transport networks, disturbance and failures in power systems, for instance. The solution to synthesize be an energy efficient and versatile solution in the face of conventional solutions, namely dynamically adapt to different feeding systems (multi-voltage and multi-frequency). This PhD thesis has the objective of building energy efficient and versatile multi voltage traction system for a rail vehicle when compared to conventional solutions.

The main control system controls the voltage input of the induction motor. The direct voltage is kept always at zero, and the quadrature voltage module is regulated according to the speed, via a hysteretic controller and a proportional controller. The control angle is calculated and set according to the desired speed.

In many speed control systems, it is usual that the fluxes of the stator and rotor are, sometimes, in undesirable positions [START_REF] Kenny | Stator-and Rotor-Flux-Based Deadbeat Direct Torque Control of Induction Machines[END_REF][START_REF] Marques | Sensorless Direct Slip Position Estimator of a DFIM Based on the Air Gap pq Vector-Sensitivity Study[END_REF][START_REF] Marques | An Open-Loop Sensorless Slip Position Estimator of a DFIM Based on Air-gap Active Power Calculations-Sensitivity Study[END_REF][START_REF] Matteo | Stator Inductance Self-Tuning in an Air-Gap-Power-Vector-Based Observer for the Sensorless Control of Doubly Fed Induction Machines[END_REF][START_REF] Marques | Air-Gap Power-Based Sensorless Control in a DFIG Connected to a DC Link[END_REF]. In these cases, the motor breaks when it is submitted to a traction effort. In this paper, this situation is analyzed and presented a solution, by predicting the position of the two vector fields and not allowing undesirable flux positions. This way the fluxes are always in the correct position and this flux filter is combined with a torque limitation filter. With this type of solution it is not only guaranteed a better controller reference follow up, but also, energy savings.

For testing and validating the proposed solution, a model of the system was simulated [START_REF] Kenny | Stator-and Rotor-Flux-Based Deadbeat Direct Torque Control of Induction Machines[END_REF]. The main results illustrating the operation principles and the added value of the proposed solution are presented and discussed in this paper.

Contribution to Cyber-Physical Systems

Over the past decades, the operation of the railways have been changed in response to technological, social and economic challenges. As push factors of these changes, it is important to highlight the increasing number of rail operators sharing the same infrastructure, the advent of the smart grids and the adoption of cyber solutions. In this context, apart from the interoperability, security and safety of electric traction systems, remote control and cyber monitoring of railway operation are topics that have to be investigated and developed. To obtain efficient solutions that address these challenges have also to be made on valid cybernetic solutions.

It should be also referred that the operation of trams and of light rail vehicles can be monitored remotely in real time. These systems should also be able to optimize its operation, which can be set according to traffic or weather conditions, for instance. In addition, these systems have potential to incorporate new features, as for instance, acting as a backup energy storage system. Under this context, in this PhD work is described an approach that intends to contribute to control the speed of these type of electric vehicles. The proposed approach is integrated in a more complex solution that allows moving up the interaction of urban rail systems with smart electrical grids [START_REF] Mendonça | An approach to recover braking energy of a tram[END_REF].

Considering the operating principle of the proposed solution, the main contribution of this work to "Technological Innovation for Cyber-Physical Systems" consist on the development of a scalar variable speed motor control for traction systems that will allow implementing a full and remote automated driving.

System Description

Power System

The design used for the main power electronics system was a three arm inverted feed by a 600 V DC power source, which corresponds to the feeding voltage used in the Lisbon tramways. The inverter uses six IGBT semiconductors with parallel diodes [START_REF] Sun | Dynamics and Control of Switched Electronic Systems Advanced Perspectives for Modeling, Simulation and Control of Power Converters[END_REF][START_REF] Silva | Electrónica Industrial[END_REF].

The inverter feeds a 100 horsepower induction motor, which is a typical traction motor power in light railway.

The mathematical model used is the same as the one implemented in the simulation model. The induction motor electrical model is simulated based on the following equations:

ܸ ௦ = ܴ ௦ ݅ ௦ + ݀߮ ௦ ݐ݀ ൗ + ߱߮ ௗ௦ ܸ ௗ௦ = ܴ ௦ ݅ ௦ + ݀߮ ௗ௦ ݐ݀ ൗ -߱߮ ௦ ܸ′ = ܴ′ ݅′ + ݀߮′ ݐ݀ ൗ + ሺ߱ -߱ ሻ߮′ ௗ௦ (1)
ܸ′ ௗ = ܴ′ ݅′ ௗ + ݀߮′ ௗ ݐ݀ ൗ -ሺ߱ -߱ ሻ߮′ ௦
Equation system [START_REF] Mendonça | An approach to recover braking energy of a tram[END_REF], describes the voltage model in dq0 coordinates, where ߱ is the reference frame angular velocity and ߱ is the electrical angular velocity. Equation system (2) is used to describe the torque behavior.

ܶ = 1.5൫߮ ௗ௦ ݅ ௦ -߮ ௦ ݅ ௗ௦ ൯ (2)
Equation system (3) is used to describe the flux model.

߮ ௦ = ܮ ௦ ݅ ௦ + ܮ ݅′ ߮ ௗ௦ = ܮ ௦ ݅ ௗ௦ + ܮ ݅′ ௗ ߮′ = ′ܮ ݅′ + ܮ ݅ ௦ (3) ߮′ ௗ = ′ܮ ݅′ ௗ + ܮ ݅ ௗ௦
Equation system (4) describes the inductance relationship.

ܮ ௦ = ܮ ௦ + ܮ ′ܮ = ′ܮ + ܮ (4)
This model will give the dq fluxes components for the field orientation filter.

Main Controller

The main controller sets the direct voltage to zero and controls the quadrature voltage according to the desirable speed. The angle is calculated according to the desired speed, according to equation ( 5). The voltage provided by the controller is converted into gate pulses trough a space vector controller. Together with the main controller, the system has also two filters that are described in the following subsection. These two systems are responsible for limiting the torque, not allowing torques greater than 1000 Nm in the motor, and fluxes in undesirable positions.

Fig. 1. Model of the proposed system

To control the motor speed, it is assumed that the motor speed is measured by a sensor, which output is used as feedback in the control chain (Fig. 1). The real speed is compared with the reference signal and multiplied by a gain. This result is limited between 500 V and -500 V, which are the desirable limits to the voltage applied to the motor. In practice, this is a proportional controller that controls the quadrature voltage module. The direct voltage is kept always at zero.

The voltage angle ߠ is calculated according to equation [START_REF] Matteo | Stator Inductance Self-Tuning in an Air-Gap-Power-Vector-Based Observer for the Sensorless Control of Doubly Fed Induction Machines[END_REF].

ߠ = ܲ ቀ2ߨ ௧ ቁ ܰ (5)
In equation ( 5), ܲ is the number of pole pairs in the machine, which is two in this case, t is the time and ܰ is the reference speed.

The block "dq to alfa beta converter", converts the voltage in dq0 coordinates to αβ coordinates. The block "SVM" converts the αβ voltage components to PWM signals using a space vector modulator controller. So that, a control of the machine supply voltage is performed. The PWM signals command the six IGBT gates via a "Gate Enable" block, shown in figure 2, which is responsible for enabling and disenabling the command signals. This block is commanded by the "Enable" block, so when the enable signal is 0, all gates commands are put to 0 also.

Torque and Field Orientation Filter

This filter prevents the torque to be greater than 1000 Nm. Every time that the torque exceeds this value the gate signals are disenabled, which means in practice that all signals are set to zero. With this filter it is implemented a supervision of the torque avoiding to reach high torque values and thus preventing big current and torque surges.

Fig. 2. Model of the "Gate Enable" block

The positions of the fluxes, the torque and the speed are calculated within the "parameter estimator" block, according to equations ( 1), ( 2), ( 3) and ( 4). It is important to refer that the accuracy of this model and of the prediction implemented depends on the knowledge of the motor parameters, as for instance, the real inductance and inductor resistance. The angle values are inputs of the "Traction Detection" block that predicts if the motor is braking or in traction. This filter contributes for a best energy usage and better reference follow up. Figure 3 shows the flux position and its effect. Inside the "traction detection" block is the equation set ( 6) and [START_REF] Sun | Dynamics and Control of Switched Electronic Systems Advanced Perspectives for Modeling, Simulation and Control of Power Converters[END_REF]. If the statement ( 6) OR (7) = TRUE is valid, than the system is braking.

൞ ߮ + ߨ ߮ ௦ ߮ ௦ ߮ ߮ 0 ߮ ߨ (6) ൝ ߮ ௦ ߮ ߮ 0 ߮ ߨ (7)
After the selection had been made, than the enable block decides to enable or disenable the gate command block according to fig. 5.

Results

In order to validate the proposed solution the system was tested by simulation with variable speed steps and loads, i.e., submitting the motor to different torques. It was tested the influence of the flux and torque filter, as well. The filter is responsible for not allowing unwanted flux positions and torques higher than 1000 Nm.

In the fig. 5 it can be observer a simulated result using a 10 Nm load, fig. 6 has the same simulation using a 100 Nm load, fig. 7 has a 300 Nm load and simulation 8 has a 100 Nm load and has no filter applied. this ripple and transients will be reduced inside the rail vehicle car, because the transmission has a 1:6 reduction factor, in most light rail vehicles, and mechanic filters like silent blocks and other shock absorbing systems.

Conclusions and further work

In this work it was made a speed controller for rail traction, using a scalar controller. With the proposed system, it is achieved an effective control of the speed and, at the same time, the control system rejects states where the stator and rotor fluxes are in a traction position when the vehicle is in braking and states where the fluxes are in braking position when the vehicle is in traction. In addiction the system prevents high levels of torque. To implement this option, filters are used constituting an important feature of this system, giving that the filters are compatible with a scalar control system and allow to achieve the required performance. This system is an alternative to the field orientation systems available and widely used.

For testing the results consistency, laboratorial test will be performed for the proposed system. It is expected to confirm the transient states and the load ripple observed in the simulations, since in a real rail vehicle there are mechanic filters like silent blocks and other shock absorbing systems that contribute to overcome these technical issues.

Considering the results obtained and the characteristics of the proposed system, being the speed control robust, in the future it is expected to implement a full automated driving, although it can be conventionally driven. It has the advantage of being energy efficient when it blocks high torques and undesirable flux positioning.

As further work, an interesting development would be to build a similar controller using the same concept, but instead of controlling the speed, controlling the torque.

Fig. 3 .

 3 Fig. 3. Fluxes positioning and effect

Fig. 4 .

 4 Fig. 4. Model of the "Enable" block

Fig. 5 .

 5 Fig. 5. Results for 10 Nm load.

Fig. 6 .

 6 Fig. 6. Results for 100 Nm load.

Acknowledgements:

This work was supported by national funds through FCT -Fundação para a Ciência e a Tecnologia, under project UID/CEC/50021/2013.

In Fig. 5 to Fig. 8, it can be observed a good system follow up of the reference speed and without any static error. At higher speeds it can be observed some ripple and transients during some speed transitions. This can be due to simulation errors or a controller unable of guarantee every time smooth transitions. As it can be observed, at higher speeds the ripple decreases due to the machine characteristics, as expected, since the better performance of the system will be achieved in this speed range. All of


Rui Policarpo Duarte
email: rpduarte@ual.pt

Christos-Savvas Bouganis

Variation-Aware Optimisation for Reconfigurable Cyber-Physical Systems

Keywords: FPGA, error minimisation, over-clocking, reduced-precision redundancy, Bayesian optimisation

des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Introduction

The constant fabrication process scaling has led to devices operating faster, consuming less power, but with increased variability in their fabrication. Hence, transistors are not created equally on the same device. This negatively impacts the performance of the device. Besides variations introduced by the physical constraints, transistors are also affected by other parameters such as voltage and temperature. Therefore, the newly fabricated devices are more susceptible to such variations [START_REF] Sedcole | Parametric yield modeling and simulations of FPGA circuits considering within-die delay variations[END_REF] as the technology is further reduced. Modern devices are limited by their worst performing transistor for a given family of devices.

To guarantee error-free operation of the implemented designs, once synthesised, the synthesis tools are prudent in determining the maximum clock frequency of digital circuits for a set of devices to operate on an error-free regime. As such, there is a significant gap between the maximum clock frequency reported by the models used in synthesis tools, and the actual maximum clock frequency that the actual device can operate, where the circuit will be placed on.

This work investigates mechanisms to increase the throughput of arithmetic units on Field-Programmable Gate Arrays (FPGAs) under Process-Voltage-Temperature (PVT) variation without changing the algorithm being implemented, while investigating the tradeoff in throughput, circuit area and timing errors.

Many times Cyber-Physical Systems (CPSs) are implemented on FPGAs because of the advantages they offer as high-performance, low-power, and highly specialised embedded blocks. Moreover, FPGAs are well positioned to tackle the aforementioned research problems because of their reconfigurability capabilities which is essential for the characterisation process that no other competitive technologies offer.

Examples of candidate applications for such CPSs that demand real-time performance, under different operating conditions (i.e. high-performance and low-power) are: Synthetic Aperture Radar (SAR) [START_REF] Nascimento | Vertex component analysis: a fast algorithm to unmix hyperspectral data[END_REF] for real-time, or high-performance; and medical capsule robots [START_REF] Beccani | Systematic design of medical capsule robots[END_REF], and Electroencephalogram (EEG) [START_REF] Ke | Classification of eeg signals by multi-scale filtering and pca[END_REF] for low-power.

Contribution to Cyber-Physical Systems

CPSs can be seen as the combination of control theory and computer engineering, leading to control and computing co-design. They are usually comprised of sensors, actuators, and (feedback) controllers. The complexity of modern CPSs requires the usage of computational platforms to process large volumes of data. Nevertheless, these systems are discrete and suffer from delays (constant and variable) and also in variations in the system's response, which can make them instable. Moreover, data dependent control systems execute different branches of software, inducing different responses by the system. To minimise the influence of software, the most sensitive parts of these systems are implemented in hardware, usually in computational data-paths for increased performance and reduced delays. Hence, real-time CPSs use dedicated hardware (co-)processors in reconfigurable logic which ensure high-performance, constant throughput and flexibility to instantiate customised sub-systems. Nevertheless, as any other silicon device, reconfigurable logic is sensitive to degradation, and variation of its operating conditions. Consequentially, the work here presented makes important contributions to the implementation of more resilient CPSs on reconfigurable devices, by promoting their graceful degradation.

In a nutshell, this research contributes to the advancement of CPSs by investigating alternatives to reduce, or mitigate, timing errors in applications that tolerate some errors in its calculations, and proposes methods to close an existing gap in this research area. Additionally, a possible by-product of this research is the promotion of security in circuit designs by turning the replication of the CPS unfeasible (i.e. Physical Unclonable Functions).

Background and Related Work

Sources of Variation

The performance of transistors is affected by variation in their sizes, supply voltages, temperature, cross-talk and jitter [START_REF] Sedcole | Characterisation of FPGA clock variability[END_REF]. Contributions [START_REF] Stott | Degradation in FPGAs: measurement and modelling[END_REF][START_REF] Wong | Self-measurement of combinatorial circuit delays in FPGAs[END_REF] present how the performance of devices from the same family degrades with the aging of the device.

Variation-Aware Methods for Throughput Increase in FPGAs

Several methods have been proposed to minimise, or recover from, timing errors caused by the aforesaid sources of variation. They operate on different levels of the design, namely placement and routing, Register-Transfer Level (RTL) and algorithm level.

Variation-aware placement and routing [START_REF] Guan | A two-stage variationaware placement method for fpgas exploiting variation maps classification[END_REF] makes use of a model created from a characterisation of the fabric where the design is going to be deployed. The main benefit of this method is to instruct the placement and routing tool [START_REF] Betz | VPR: A new packing, placement and routing tool for FPGA research[END_REF] to assign the critical-paths to the fastest elements on the device, thus reducing the critical-path delay, increasing the designs' overall clock frequency. The drawback is the necessity to characterise the design before deploying the design, which is currently only available on FPGAs [START_REF] Wong | Timing measurement platform for arbitrary black-box circuits based on transition probability[END_REF].

In order to increase the clock frequency of a datapath, on the RTL level, typically the Digital Signal Processing (DSP) designer either reduces its word length or introduces additional pipeline levels. Word length optimisation while offering reductions in area and delay, it also reduces the precision of the results produced. Extensive work has been published on the aforementioned topics, offering techniques to implement and optimise DSP designs [START_REF] Constantinides | Synthesis and optimization of DSP algorithms[END_REF][START_REF] Deschamps | Synthesis of arithmetic circuits: FPGA, ASIC, and embedded systems[END_REF][START_REF] Moore | Automatic error analysis in digital computation[END_REF].

Error Recovery Methods

Since the early days of computing, engineers have been concerned with faults and errors from different natures [START_REF] Neumann | Probabilistic logics and the synthesis of reliable organisms from unreliable components[END_REF]. Most of the mechanisms and methodologies proposed to mitigate them rely on extra circuitry and processing time. Usually a compromise is achieved in terms of the minimum requirements by the application to work, amount of resources and the time to produce results. Recently [START_REF] Krause | Adaptive voltage over-scaling for resilient applications[END_REF] has proposed a method to adapt the circuit's voltage according to the level of errors, thus trading off power for accuracy. However, some circuits don't admit errors of any kind in their computations. Hence, circuits that require a deterministic output in their calculations have to rely on other methodologies to recover from errors [START_REF] Roberts | Error analysis for the support of robust voltage scaling[END_REF], such as Razor [START_REF] Ziesler | Razor: A low-power pipeline based on circuit-level timing speculation[END_REF]. Other alternatives for fault tolerance techniques, their benefits and their limitations have been presented in [START_REF] Sharma | Fault tolerant techniques for reconfigurable platforms[END_REF]. Reduced-Precision Redundancy RPR was originally presented in [START_REF] Shim | Reduced precision redundancy for low-power digital filtering[END_REF] as a mechanism to contain errors in designs under voltage over-scaling, for low-power, based on the assumption that DSP design can tolerate some errors in their calculations, trading off precision for power [START_REF] Hegde | Energy-efficient signal processing via algorithmic noisetolerance[END_REF][START_REF] Huang | A methodology for energy-quality tradeoff using imprecise hardware[END_REF].

It relies on a smaller implementation of the original system computed in parallel using truncated operands. It compares both outputs and verifies if the magnitude of the difference is below a user defined limit. The method selects the original output if this result is below the specified threshold (T), and the approximated result otherwise. Reduced-Precision Redundancy (RPR) has been compared with other error recovering schemes, such as Triple-Modular Redundancy (TMR) [START_REF] Hentschke | Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy[END_REF], in terms of the tradeoff between errors and resources.

Resource Optimisation through Bayesian Inference

A method to optimise linear projection implementations through inference was first introduced in [START_REF] Bouganis | Efficient mapping of dimensionality reduction designs onto heterogeneous FPGAs[END_REF] and later extended in [START_REF] Bouganis | Synthesis and optimization of 2D filter designs for heterogeneous FPGAs[END_REF][START_REF] Bouganis | Exploration of heterogeneous FPGAs for mapping linear projection designs[END_REF]. Here, the problem is to discover a projection matrix to compute the best approximation for the original data, minimising resources and reconstruction Mean-Square Error (MSE) of the projected data in the original space. One of the improvements, compared to other works is the avoidance of exhaustive search for solutions.

Being the factors F from a linear projection of data X and the basis matrix Λ, searching for a possible solution for Λ and F is an ill-conditioned problem, for which solutions from heuristic methods are suboptimal. The framework [START_REF] Bouganis | Exploration of heterogeneous FPGAs for mapping linear projection designs[END_REF] uses a Bayesian conception of the factor analysis model rather than the Karhunen-Loeve Transformation (KLT) algorithm to find the elements of the Λ matrix that minimise the area cost, rather than a constant area cost consideration in the KLT algorithm. The framework receives the problem data, the area models and its parameters and iteratively computes the basis for all projection vectors. As a result it returns the basis matrix and the assignment for the logic elements.

Summary

Here are some of the most important concepts present in the design of DSP designs for FPGAs focused on performance optimisation, and also methods to mitigate timing errors, or to achieve graceful degradation.

Table 1 summarises the different techniques that can be applied to minimise, or minimise, timing errors. For each technique it shows how it actuates and its limitations.

Table 1. Summary of the existing techniques for acceleration of computations, in order to mitigate timing errors, and their limitations.

Technique Effect Limitations

Deep pipelining Break the critical-path by inserting registers

Unsuitable for some streaming algorithms, or algorithms using recursion

Word length optimisation

Reduce the critical path by processing less bits from truncated operands Penalty in the quality of results

Razor [START_REF] Ziesler | Razor: A low-power pipeline based on circuit-level timing speculation[END_REF] Check if the output matches the shadow register Temporal redundancy is unsuitable for streaming applications

Reduced-Precision

Redundancy [START_REF] Shim | Reduced precision redundancy for low-power digital filtering[END_REF] Check if the error is within a threshold Requires extra latency. Unsuitable for algorithms using recursion

Reduced Precision Redundancy Framework

RPR as originally proposed in [START_REF] Shim | Reduced precision redundancy for low-power digital filtering[END_REF] replaces the result produced by the arithmetic unit with an approximate result, which is computed in parallel, in order to control the propagation of errors. This tool operates similarly as existing RPR implementations as it wraps the original combinatorial unit with a redundant circuitry. Yet, it separates itself from other architectures as it has characteristics that are distinct for high-throughput and applications intolerant to latency, and depends on a novel RPR architecture with zero latency cost. This tool reuses the concept of substituting a set of Most Significant Bytes (MSBs) from the original arithmetic unit with an approximate result, in case of error, nevertheless it introduces new mechanisms to: a) identify timing errors and b) generate approximations. Typically, RPR architectures use some of the MSBs of arithmetic operators, as usually they are the critical paths.

Architecture

The two main novelties in this architecture are: a) the use ROMs to have the MSBs of the approximations, rather than the simplified operator; and b) a bit-wise testing (XOR→OR) as a substitute of a subtraction before the comparison with a user-defined limit to identify errors in computations.

Fig. 1 presents the new architecture in a combinatorial unit op. Its inputs are A, B; and R is its output. Label a represents the inputs and b the original operator's output. The other labels refer to the paths added by the RPR. They are explained in more detail in [START_REF] Duarte | Zero-latency datapath error correction framework for overclocking DSP applications on FPGAs[END_REF].

The use of ROMs and bit-wise output testing (XOR→OR) minimises the delay between the input output ports of the new RPR unit. As long as the difference between the delay of the approximation's output and the original result inflates, it favours the increasing of the clock frequency.

As a results of potential realizations with the new RPR scheme, a taxonomy is presented to support the identification of key elements' word-lengths, such as: original unit, error-detection and error-correction ROMs. The structure is given by: iWL and oWL as the input and output word-lengths, and Ori, Det and Rep depict the Original, Detection and Replacement correspondingly: Ori iWL : Ori oWL / Det iWL : Det oWL / Rep iWL : Rep oWL Moreover, to discriminate the many RPR architectures, the succeeding prefix is included to the previous taxonomy, which is followed hereafter:

-LUT-SUB -existing RPR but without registers; approximate result is computed with a truncated arithmetic unit implemented with Look-Up Tables (LUTs)/ Logic Elements (LEs); errors are identified by the absolute difference between the output of the original unit and the approximation; -ROM-XOR -proposed RPR; detection approximation is obtained from a ROM, and errors are detected via a bitwise testing of the MSBs with the original unit.

Approximation Functions

The approximation functions aim to precisely produce the original unit's MSBs in order to decrease the approximation errors. The novelty when compared to other variations is the opportunity to use any approximation function, rather than depending on a truncated arithmetic unit computed simultaneously.

The new architecture employs two approximations simultaneously. One approximation in error detection (DET APX) combined with another approximation for replacement (REP APX) of erroneous results. Since data is removed from an approximation computed via truncated input arguments, a bit-wise testing between the expected and approximation results will be identified as a mismatch. Hence, REP APX is used to correct those MSBs.

ROM-XOR RPR Arithmetic Operators

The tool here presented supports any arithmetic unit. The details about how they are supported by this tool can be found in [START_REF] Duarte | Zero-latency datapath error correction framework for overclocking DSP applications on FPGAs[END_REF]. The tool is indifferent to synthesis of the operator and can be adapted to any arithmetic operator of any word-length.

Adder

Performance Evaluation

To assess this work, it was compared against standard arithmetic units, with and without RPR. It employs the default implementation for the synthesis of the combinatorial operators.

To obtain precise results, the device was kept at constant temperature of 20 degrees Celsius, by using a Peltier element on top of the FPGA device and a 1,2V core voltage from an independent power source. All tests were conducted on a EP3C16F484C6 Cyclone III FPGA from Altera [START_REF] Altera | Cyclone III device handbook[END_REF], on a DE0 board from Terasic [START_REF] Technologies | Terasic DE0 board user manual[END_REF]. Multiplier Three 8-bit multipliers were used in the performance comparison: no RPR, LUT-SUB RPR and ROM-XOR RPR. Fig. 2 presents the variance and mean of the difference between the expected value and the value obtained from the board for all multipliers. The top clock frequency of the ROM-XOR-RPR scheme is near the clock frequency of the multiplier without redundancy, and it surpasses any other multiplier being extremely over-clocked, e.g. 300 MHz. Going beyond 340MHz the ROM-XOR-RPR multiplier has similar variance values as the other multipliers. Nevertheless, its mean error is still near zero.

Linear Projection Designs Karhunen-Loeve transformation (KLT) [START_REF] Hotelling | Analysis of a complex of statistical variables into principal components[END_REF], or linear projection, is normally utilised to compress data. In this assessment, a 8:16/5:3/5:3 ROM-XOR RPR, a LUTSUB RPR with an approximation obtained from the 5 MSBs and a threshold equivalent to the 2 MSBs, is compared against the implementation of the linear projection without any redundancy.

The circuit to compute the linear projection corresponds to a fused Multiply-Accumulate (MAC) for each projected dimension. In the implementation all inputs are encoded with 9-bit sign-magnitude. The output of the multiplier is 16 bits unsigned. The word-length of the output increases with the number of accumulation stages (log 2 ).

Fig. 3 presents the results for the 3 implementations at 270MHz. The top row corresponds to the anticipated error-free result. The rows below relate to the results for: NO RPR, LUT-SUB RPR and ROM-XOR RPR. For all images the PSNR is computed from the projected data reconstruction, on the FPGA, into the original space in software. It's clear that the ROM-XOR RPR provides linear projections circuits with less errors and produce the smallest reconstruction Peak Signal-to-Noise Ratio (PSNR) for all images.

The results demonstrate that a small impact in the top clock frequency in the errorfree regime is paid back when in the error prone regime.

Optimisation of Linear Projection Designs for Over-Clocking

In the circuit to implement the Linear Projection, or KLT, design, the data path holds the most critical paths. The main focus of this work is on over-clocking multiplier circuits, as they're the components with the largest delay in the data path of the design. In the KLT algorithm, the calculation of the projection matrix Λ and its hardware mapping onto FPGAs are often considered as two independent steps in the design process. However, considerable area savings can be achieved by coupling these two steps as shown in [START_REF] Bouganis | Efficient mapping of dimensionality reduction designs onto heterogeneous FPGAs[END_REF][START_REF] Bouganis | Exploration of heterogeneous FPGAs for mapping linear projection designs[END_REF]. The Bayesian formulation presented considers the subspace estimation and the hardware implementation simultaneously, allowing the framework to efficiently explore the possibilities of custom design offered by FPGAs. This framework generates Linear Projection designs which minimise errors and circuit resources, when compared to the standard approach of the KLT transform application followed by the mapping to the FPGA. A key idea from [START_REF] Bouganis | Exploration of heterogeneous FPGAs for mapping linear projection designs[END_REF] is to inject information about the hardware (i.e. in this case about the required hardware resources of a Constant Coefficient Multiplier (CCM)) as a prior knowledge in the Bayesian formulation of the above optimisation problem. In more detail, the proposed framework in [START_REF] Bouganis | Exploration of heterogeneous FPGAs for mapping linear projection designs[END_REF] estimates the basis matrix Λ, the noise covariance Ψ, and the factors using Gibbs sampling algorithm [START_REF] Geman | Stochastic relaxation, Gibbs distributions, and the Bayesian restoration of images[END_REF] from the posterior distribution of the variables, having injecting knowledge about the required hardware recourses for the implementation of the CCMs through a prior distribution. Thus, a probability density function is generated for the unknown Λ matrix, which is used to for generation of samples, where the prior distribution tunes this posterior distribution, and thus accommodating the impact the required hardware resources. [START_REF] Duarte | High-level linear projection circuit design optimization framework for FPGAs under over-clocking[END_REF][START_REF] Duarte | A unified framework for over-clocking linear projections on FPGAs under PVT variation[END_REF][START_REF] Duarte | Over-clocking of linear projection designs through device specific optimisations[END_REF][START_REF] Duarte | Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only)[END_REF] provide an extension of the above work for the optimisation of Linear Projection designs using different arithmetic units implementations, to combat the effects of circuit area, performance variation and error minimisation.

The proposed work aims to support other arithmetic unit architectures and PVT variation in the characterisation, error modelling, and generation of designs to implement. The framework selects the multipliers used for the implementation of each dot product in along with the coefficients of the Λ matrix that define the lower dimension space.

Defining the Objective Function

In this work, the objective function is based on the Mean Square Error (MSE) of the reconstructed data when are projected back to the original space, as well as on arithmetic errors at the output of the embedded multipliers that are generated when the design is over-clocked, due to PVT variation. In order to simplify the optimisation process and avoiding the formation of a multi-objective function, in this work it is assumed that the errors at the output of the embedded multipliers are uncorrelated for consecutive inputs. As such, the objective function is formed only by the errors due to dimensionality reduction and the variation of the error at the output of the multiplier when it is stimulated by a random input. Error Models The proposed framework builds a database of the errors that can be observed at the output of the multipliers when one of the multiplicands is fixed, modelling the constant coefficient of the Λ matrix. The process is repeated for a set of frequencies, as well as for a set of multiplicands resembling in this way the possible values of the coefficients in the the Λ matrix. The observed error variance at the output of the multiplier under the different operating conditions can be seen as the uncertainty in the computations which needs to be minimized.

Prior Distribution

The prior distribution p(•) in the framework aims to favour designs that are known (due to the previous error profiling) to perform poor under certain conditions. As the expectation of the error at the output of an overclocked multiplier can be compensated, the focus is on the minimisation of the variance of the error, which in effect it resembles the uncertainty in the computation. Furthermore, the prior distribution can also favour certain coefficients in terms of how well the corresponding constant coefficient multiplier "fits" in the FPGA device in terms of resources, power, and so on. However, in this work, the above has not been taken into account and thus an informative prior on the value of the coefficients has been employed. Thus, the employed prior distribution captures only information regarding the errors at the output of the embedded multipliers, as a function of the targeted clock frequency, the actual physical placement on the FPGA device, the utilised core voltage, and finally the operating temperature of the device.

Design Exploration

The optimisation problem falls under Bayesian Inference, where the aim is to infer the distribution of the parameters (i.e. the coefficients of the Λ matrix) that would approximate (in MSE manner) the targeted data. In this work we selected to use Gibbs sampling [START_REF] Geman | Stochastic relaxation, Gibbs distributions, and the Bayesian restoration of images[END_REF], a sampling methodology that breaks the joint distribution to conditional distributions and samples the parameters one at a time, leading to computational efficient implementations. The sampled design points (effectively the coefficients of the Λ matrix) converge to designs that minimise the objective function U. To further improve the computational complexity, the proposed framework samples each dimension (i.e. column) of the Λ matrix sequentially. The designer provides the dimensionality of the low-dimensional space K, as well as the targeted operating conditions of the device, which define the prior distribution p(•) and effectively guide the framework to select coefficients that perform well under the targeted operating conditions.

Performance Evaluation

The proposed framework is evaluated for a set of Linear Projection problems when various operating conditions such as process variation, voltage, and temperature are targeted. The performance of the resulting design from the proposed framework was compared to standard design (i.e. baseline) that follows the utilises the KLT algorithm for the computation of the coefficients for the Λ matrix, thus it is unaware of the actual operating conditions and the variance of the error that is expected at the output of the multipliers. The DEO board from Terasic was used for the experiments, which hosts a Cyclone III EP3C16 FPGA. The control of the core voltage that was supplied to the FPGA was done through the PL303QMD-P [35] power supply from TTI. To fine control the temperature of the device, a thermoelectric cooler was placed on top of the device and it was calibrated using a digital thermometer from Lascar Electronics [36] with a deviation below 1•C. It should be noted that all the reported results have been collected by running the actual system. As a case study the problem of generating a Linear Projection design that projects data from Z 6 to Z 3 is utilised. The characterisation of the embedded multipliers under various conditions as well as the estimation of the projection matrix was performed utilising a different set of data to the ones that were used of the computation of the reconstruction error of the system (i.e. evaluation of the design). The utilised metric for the performance of a design is the PSNR of the reconstructed data in the original space.

Optimisation for Maximum Performance This scenario captures the case where maximum performance is required from the system, which requires an increased FPGA core voltage and the application of an active cooling method for the device. In our test, the device was kept at 5 • C and supplied with 1400mV, instead of the 1200mV specified as the maximum supply voltage by the manufacturer. Further than that, the device was clocked with a clock frequency that was double the the maximum frequency specified by the synthesis tool for the normal working conditions. Figure 4 shows the obtained results for a number of frequencies. The results demonstrate that the proposed methodology can generate designs that result in a gain of 10dB in PSRN of the reconstruction compared to the baseline design utilising the KLT algorithm. Moreover, fixing the targeted PSNR, the designs generated by the proposed framework can be clocked 20MHz higher than the designed based on KLT. Optimisation for Low Voltage This case investigates the gains providing by the proposed framework when a low-power system is targeted, by utilising a low core voltage and without any active cooling component. Figure 5 (left) demonstrates the performance achieved by the reference design that utilises the KLT algorithm when the device operates at 35 • C under a set of FPGA core voltages (0.9V to 1.2V) and a number of clock frequencies. The figure shows that as the core voltage drops, the maximum frequency where the design operates without computational errors decreases. Figure 5 (right) focuses on a subset of these results, and in particular the design point with core voltage of 900mV. The figure depicts also the performance achieved by the design generated by the proposed framework. The results show that an improved PSNR (around 10dB) is achieved by the design generated by the proposed framework, compared to the baseline design for the same clock frequency. Moreover, for a similar PSNR, a higher clock frequency of up to 10MHz is achieved by the new design compared to the reference design.

Optimisation for Device Temperature Tolerance This test scenario investigates the case where the generated design operates under various temperature conditions. A common design methodology to address the problem is to design for the worst case condition. The proposed framework has been extended in order to address the following case in order to generate designs that would achieve a good performance under various temperatures.

In this work, in order to capture the performance of the multiplier under a set of temperatures, a weighted average of the characterisation errors was utilised. In this test case, the design is assumed to operate in temperatures: 20, 35 and 50 • C with a proportional time spend in each temperature captured by the following weights: α 20 = 0.3, α 35 = 0.5 and α 50 = 0.2. Please note that these weights are also used in the weighted average of the characterisation errors. In practice, the proposed framework generates circuit designs per clock frequency, covering all the temperatures within the expected range. They are identified with NEW WAVG in the results.

Figure 6 (top-left) depicts the performance of the reference Linear Projection circuit (KLT) as a function of the utilised frequency for the targeted temperatures of the device, when the core voltage is 1200mV. The rest of Figure 6 focuses on the comparison between the reference (KLT design), the design produced by the proposed framework using the average weight approach (NEW WAVG), and the design generated by the proposed framework assuming that highest operating temperature (i.e. worst case scenario), for a set of frequencies and temperatures. The figure shows that the designs generated by the proposed framework outperform the Designs based on KLT across all operating temperatures and frequencies, providing at the same time significant improvements on the reconstruction of the data. Moreover, the NEW WAVG designs perform significantly better than the NEW ones for the two out of the tree operating temperatures, as they incorporate information about the performance of the device at these temperatures, performing slightly worst than NEW at 50 • C, as NEW has specifically optimised for this temperature.

Conclusions

The constant scaling in the fabrication process has led to devices exhibiting an increase in their process variation. Hence, when the maximum throughput offered by traditional design techniques isn't enough, over-clocking the design is a method to increase it. However, this makes the design susceptible to produce errors. This work investigated methods to assess the impact of errors on arithmetic units and applications, on devices under variation, as well as methods to mitigate those errors.

The proposed RPR scheme fulfils the need for a generic method that can provide resilience to a data path without introducing extra latency, neither having to change the implementation of the algorithm. The (non-trivial) solution imagined proved to work by accelerating the units in the data path while controlling the errors. Despite the fact that the novel architecture requires twice the LEs and 2 ROMs, tests have showed that the quality of the results at the output of the RPR unit can't be achieved by other mitigation methods for the same operating conditions. Moreover, even though only timing errors were considered in this work, it can be utilised to mitigate permanent faults.

In scenarios where resources are scarce and hence it's not feasible to add extra resources to mitigate errors, the optimisation framework uses information from the previous characterisation to create an error model. From that model it generates linear projection designs, through an inference method that can produce results with less errors, when compared to traditional implementations operating under the same conditions. This method is suitable to be adopted in FPGAs, due to its reconfigurability properties, as it allows to have a prior characterisation and a later implementation on the same device. It was also identified that when accounting for timing errors, throughput, errors and area, the designs generated by the optimisation framework were the ones offering the best trade-off.

Fig. 1 .

 1 Fig.1. The new RPR architecture on a generic operator.

  In this operator the linear approximation function examined was: apx(a,b,k) = a+b+k. Here a and b are the truncated input operands and k is an offset to balance the truncation of the input operands. The new RPR tool searches for values of k which minimise the objective function regarding the predicted and the approximation MSBs. Multiplier The RPR multiplier is similar to the RPR adder, being the arithmetic unit the only change. In this case, a new approximation function is investigated to attenuate the objective function. The approximation function is given by: apx(a,b,m,l) = (a + m) * (b + m) + l. Here a and b are the truncated operands, and m and l are the approximation function coefficients.

Fig. 2 .

 2 Fig.2. Error variance (top) and mean error (bottom) of an 8-bit unsigned LUT-based multipliers for different clock frequencies.

Fig. 3 .

 3 Fig.3. Images of reconstructed faces (A-E) in the original space without timing errors (EXPECTED), obtained from different multiplier implementations (NO RPR, LUT-SUB RPR, ROM-XOR RPR) at 270 MHz. On top of each face there's the corresponding reconstruction error.

Fig. 4 .

 4 Fig.4. Performance comparison between the design generated by the proposed framework (NEW) and the reference design (KLT) for a number of operating frequencies when the supply voltage is1400mV and the device temperature is kept at 5•C.

Fig. 5 .

 5 Fig.5. Performance of the KLT Linear Projection application under different core voltages (left), and a comparison between the two methods at 900mV (right).

Fig. 6 .

 6 Fig.6. Performance of the Linear Projection application for a set of device temperatures (top-left), and a comparison between the three methods at 20•C (top-right), 35•C (bottom-left) and 50•C