Hao Zou
email: hao.zou@lip6.fr.

Yasser Moursy

Ramy Iskander

Alexander Steinmair

Heimo Gensinger

Ehrenfried Seebacher

Jean-Paul Chaput

Marie-Minerve Louërat

J.-P Chaput

M.-M Louërat

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

Keywords: Smart Power ICs, parasitic noise, substrate modeling, CAD, meshing strategy

Smart Power integrated circuits receive an increasing attraction recently, especially in automotive industry. Substrate noise coupling is one of the major causes of failure in this kind of integrated circuits that requires circuit redesign and increases the overall cost. An exhaustive failure analysis is needed to identify failures due to substrate coupling. In this paper, we present a post-layout extraction and simulation methodology for substrate parasitic modeling. Based on this methodology, we have developed a dedicated Computer-Aided-Design tool that is used for substrate extraction from layout patterns. The extraction employs a meshing algorithm for substrate parasitic generation.

To validate the substrate model, the process of benchmarking uses industrial design structures in 0.35µm high-voltage-CMOS technology. Two test cases in transient simulation are considered in this work. The first one is a common used current mirror circuit. Our tool predicts the interference of substrate currents to this basic circuit. The second test case is an industrial design test-chip where parasitic coupling is investigated in a standard automotive test. Eventually, by using the proposed CAD tool, it becomes possible to simulate the behaviors of substrate noise at early phase before fabrication.

I. INTRODUCTION

M odern trend of microelectronics is to integrate more functionalities on a single chip, along with reducing the cost and the total number of external components. This integration increases the reliability and reduces the electromagnetic interference (EMI) of the overall system. The same idea is used in Smart Power integrated circuit (ICs) where high voltage (HV) power devices and low voltage (LV) analog and digital devices co-exist on the same silicon substrate [START_REF] Murari | Smart Power ICs[END_REF].

In a typical Smart Power IC, the power stage is commonly used to drive inductive loads, e.g. motor. During the power stage switching, the drain voltage of output transistor instantly goes below ground or above supply voltage that injects substrate currents. The induced substrate currents lead to a local shift of substrate potential that can reach hundreds of millivolts. As a consequence, it realizes the coupling between surrounding devices with possible activation of parasitic lateral NPN (N-well to P-substrate to N-well) bipolar junction transistors (BJT). The induced substrate current paths are considerably long and layout dependent.

Unlike the traditional IC in LV technology, the Smart Power ICs have to withstand harsh environmental conditions like high operating temperatures. Due to high chip temperature arising from power domains, the substrate noise increases and the impact of substrate coupling becomes even worse. As technology improves, HV devices continue to get larger to deliver more power, in the meantime LV digital devices are shrinking to provide higher frequency and less power consumption. Therefore, it can be quite challenging to ensure immunity against parasitic coupling. The coupled noise from power stage is disturbing the normal functionalities and compromising the system performances. Moreover, the possible activation of parasitic BJTs may cause destructive effects such as triggering the latch-up.

Failures due to coupling of substrate lateral NPN BJTs cause several circuit redesigns. Addressing such failures is becoming of interest since these failures are still reported in tests after fabrication. On the one hand, conventional IC design ignores the minority carriers related effects, however, such effects due to carriers (majority and minority) injection and propagation in substrate are significant in Smart Power ICs. On the other hand, the impact of minority carriers cannot be modeled in conventional way, since standard compact model cannot maintain the minority carriers propagation between devices.

Technology Computer-Aided-Design (TCAD) [START_REF]Synopsys Sentaurus Device[END_REF] tools are considered the only way to investigate the minority carriers related effects. This physical device simulator solves the 2D or 3D equations based on the finite elements method (FEM). They have reliable results, yet considerably time demanding. Investigations to substrate parasitic lateral NPN BJTs using TCAD simulators were performed in [3][4]. They show reliable results with agreement to measurements. However, the method is not applicable since it is time demanding (several hours), and using custom layout reduction.

In 2010, a methodology for substrate parasitic modeling was introduced [START_REF] Lo Conte | A Circuit-Level Substrate Current Model for Smart Power ICs[END_REF]. The idea relies on modeling the substrate with a network of enhanced parasitic models. Different from standard parasitic models, these models take into account the effects related to minority carriers. Besides the models, the geometry of layout is the key to model correctly the behaviors of substrate noise. Based on this idea, we extend the method by developing an automatic layout extraction tool. In this paper, the main idea will be introduced accompanied by several industrial test cases.

This paper is organized as follows: In section II, we recall the methodology of substrate parasitic modeling for Smart Power technology. Section III introduces our design flow with dedicated layout-extraction methodology. To validate our substrate model, process of model benchmarking in terms of parasitic diode and bipolar are discussed in section IV. In section V, we apply our method to two cases study. Finally, the conclusions are drawn in section VI.

II. MODELING METHODOLOGY

In the context of European Project AUTOMICS [6] with 7th framework entitled "Pragmatic Solution for Parasitic-Immune Design of Electronics ICs for automotive", we aim at proposing a new pragmatic, focused and well-structured solution for modeling of parasitic coupling in automotive ICs [START_REF] Moursy | AUTOMICS: A Novel Approach for Substrate Modeling[END_REF] [START_REF] Buccella | Methodology for 3-D Substrate Network Extraction for Spice Simulation of Parasitic Currents in Smart Power ICs[END_REF].

The idea relies on constructing automatically a 3-D network that takes into account both majority and minority carriers propagation in substrate. This substrate network is composed of enhanced parasitic models [START_REF] Stefanucci | Spice-Compatible Modeling of High Injection and Propagation of Minority Carriers in the Substrate of Smart Power ICs[END_REF][10] (i.e. EPFL diodes, resistor and homojunction) with extracted geometrical features from layout [START_REF] Zou | A novel CAD Framework for Substrate Modeling[END_REF]. Those enhanced models are compact spice models (written in Verilog-A), which have two additional terminals introducing minority carriers' concentration and gradient. At those terminal, the minority carriers concentrations are saved as voltage and their gradient are saved as current [START_REF] Lo Conte | Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage Hbridge at High Temperature[END_REF]. Therefore, bipolar effects can be simply modeled by two back-to-back (NPN) or front-to-front (PNP) diodes. By doing this, the substrate lateral NPN BJTs can be extracted and simulated [START_REF] Zou | Substrate Noise Modeling with Dedicated CAD Framework for Smart Power ICs[END_REF]. As a feature of our modeling methodology, this substrate network can be back annotated to circuit schematic, which is impossible by using TCAD simulations. As a consequence, the behaviors of substrate currents can be observed by fast simulation at early phase before fabrication of first prototype [START_REF] Buccella | Simulation, Analysis, and Verification of Substrate Current for Layout Optimization of Smart Power ICs[END_REF][15] [START_REF] Moursy | Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications[END_REF].

III. LAYOUT-BASED EXTRACTION METHODOLOGY

In the following, our approach of post-layout extraction is introduced. The flow in Figure 2 describes the overall idea: our extraction flow consists of 2 parts: a) extraction of substrate network. An extraction engine is developed based on OpenAccess [17], and encapsulated in a CAD tool. The CAD tool is integrated in Cadence design environment of ams AG Hitkit Process Design Kit (PDK). The idea of substrate modeling and parasitic extraction can be simply illustrated as in Figure 1, and will be explained in the following paragraphs. b) extraction of RC and netlist back-annotation. To back-annotate the substrate network with standard post-layout schematic, we extract pins at the interfaces of the substrate. Then these pins are extracted as short-vias between metal wires and substrate network. To extract the substrate parasitic, our methodology follows 3 steps:

A. Reduction Phase

The region of interest that we consider in our methodology is underneath transistor diffusion areas. In the one hand, we consider wells: e.g. deep N-well (DNTUB) and deep P-well (DPTUB) in ams AG 0.35µm HV-CMOS technology process, and implants: e.g. N-implant (NDIFF) and P-implant (PDIFF). On the other hand, all the others: e.g. metal layers and via that do not contribute to the substrate parasitics are ignored in our methodology. Hence, specific rules are used to define the masks involved in a target technology process. The rules are formed in Extensible Markup Language (XML), thus written in XML file. Therefore, in our approach, we start by reducing layers from the original layout, and deriving a reduced version of layout that is used for further extraction.

B. Meshing Phase

Meshing of substrate region is based on lumped elements (i.e. cubes) in 3-D. Each element, has a different size, and models a lumped region in substrate. To complete the meshing in 3-D, we consider three steps: 1). Substrate layering; 2). 2-D surface meshing; 3). 2-D mesh refinement. 1) Substrate Layering: For vertical meshing along z-axis, substrate will be divided into several stacked layers, or slices. The total number of slices is derived from the wells, thus their thickness are derived from the junction depths. For example, if we consider a substrate region of 20µm thickness, DNTUB and DPTUB are layers in our case (Figure 1 (b)). Eventually 3 slices are derived from vertical meshing. The "cut" through PN junction (DNTUB to P-substrate) and "cut" through DPTUB and P-substrate result in three slices: the slice on "top" includes DNTUB and DPTUB wells (Figure 3b); the slice in the "middle" includes only DNTUB (Figure 3c); and then the slice at "bottom" is only P-substrate region (Figure 3d). Table I records the relevant informations for meshing, such as thickness (second column) and involved wells or implants (third column) at each slice. Besides, Ntype and P-type diffusions are considered as the contacts on the surface of "top" slice (Figure 3a).

2) 2-D Surface Meshing: Once the substrate is layered, meshing on 2-D surface (x-y axis) is developed at each slice. Since wells have different junction depths, meshing on 2-D are different at each slice as well (see Figure 3). In our methodology, meshing on 2-D is based on points instead of shapes (e.g. rectangle or polygon is a combination of ordered points). The cost for computation and memory used increases as IC layout becomes more complex. Before meshing, we start to collect the vertices from the layers, and saved as:

S = {v1, v2, ..., vn}
where n is the total number of collected vertices, each one being a 2-D point, i.e. v j = (x j , y j ). If one 2-D point can describe a location on the surface, then two 2-D points describe a line segment corresponding to a junction boundary. The extension of this line segment to the edges results in a mesh line (black line in figure). The projection of these vertices on x-axis is called Xarray, and the ones on y-axis is called Yarray. In our case, they can be expressed as:

Xarray = {a 1 , a 2 , a 3 , ..., a p } Y array = {b 1 , b 2 , b 3 , ..., b q }
where p is the total number of coordinates in x-axis, and q is the one in y-axis. These two arrays build the coordinate system of resulting meshing. For each element in meshing, its depth equals to slice thickness (Table I), and its size on 2-D surface is defined by diagonal opposed corners, i.e. the lower left (LL) and upper right (UR) points. Eventually, the geometrical of element can be expressed as:

Length = U R.x -LL.x W idth = U R.y -LL.y Depth = d slice
Besides geometry, mesh element has been marked by material type. The available material types are: N-well, P-well, Nimplant, P-implant, P-substrate.

3) Mesh Refinement: We have just introduced a methodology for substrate meshing. This method relies on a rectilinear mesh in 2-D where substrate region is modeled. In [START_REF] Zou | An Adaptive Mesh Refinement Strategy for Substrate Modeling[END_REF], an enhanced strategy for 2-D surface meshing was introduced, which contribute to reduce significantly the size of meshing, thus speed up the entire simulation time. In this section, we recall this mesh refinement strategy on the "top" slice of structure, thus the idea can be applied to each one of the entire meshing in 3-D.

• Initial meshing strategy (S1), as depicted in Figure 4a.

In our methodology, mesh is constructed by cuboid in 3-D. Its height is defined by layer depth, and its surface (i.e. x-y) is defined by the diagonal opposed corners. To find these corners, a coordinate system in 2-D is built to help constructing the perpendicular mesh lines, thus the intersections are the corners of resulting mesh. For instance, mesh in Figure 4a has coordinates at the xaxis Xarray={a1, a2, a3, a4, a5, a6}, and coordinates at the y-axis Yarray={b1, b2, b3, b4, b5, b6}. These coordinates are the projection on x/y-axis of vertices from DNTUB, and DPTUB layers. As an example, vertices from DNTUB give the coordinate {a3, a4} to Xarray and {b3, b4} to Yarray.

• Enhanced meshing strategy (S2), as depicted in Figure 4b.

Beginning with initial mesh, the technique of mesh refinement is applied to reduce the number of elements by combining small sized elements. For those small sized elements who can be merged, they have to meet the following 3 conditions: 1) same material type; 2) the resulting merged element form a rectangular shape; 3) the resulting shape does NOT overlap any vertices (red in Figure ). For example, a group of initial elements {1, 2, 3, 4, 5} (Figure 4a) overlaps vertices (a2, b2) and (a5, b2), hence they can not be merged even if they consist of the same material type. Thus, the group of initial elements {2, 3, 4} (Figure 4a) can be merged to element 4 in Figure 4b. This has a consequence on the extracted parasitic components: the red line crossing the length of element 4 is an ideal connection, the parasitic resistors at the boundaries of elements 1 and 4 and elements 4 and 5 have to be modified to take into account the new geometry.

C. Extraction Phase

Extraction of parasitic components from meshing results in an equivalent netlist. This netlist consists of extracted components together with geometrical patterns. The extraction of component happens between two adjacent elements. Considering two elements, as illustrated in Figure 5, a parasitic component is extracted between their two centers. Depending on their material types, the resulting component can be either an enhanced diode (different material type), an enhanced resistor (same material types) or a homojunction (same material type but different doping concentration) [START_REF] Stefanucci | Spice-Compatible Modeling of High Injection and Propagation of Minority Carriers in the Substrate of Smart Power ICs[END_REF] [START_REF] Stefanucci | Impact of Enhanced Contact Doping on Minority Carriers Diffusion Currents[END_REF]. The parameters to extract are length, area, etc (see Table II). Besides geometry, semiconductor materials are extracted as well. For instance, resistor extracted from DNTUB well differs from the one extracted from DPTUB well in terms of silicon doping, and they differ from the one extracted from P-substrate as well. Therefore, resulting extracted resistors are differentiated by definition, such as:

La Lb

• R DP : inside DPTUB well; • R DN : inside DNTUB well;

• R P S : inside P-substrate. The same idea stands for enhanced parasitic model of diode and homojunction. Benchmark structures are extracted using tool and parameters are calibrated using special algorithm to fit simulation results with measured data. We will not detail the calibration process itself, but we show the results of model benchmarking.

A. Modeling of diode

As the first case study, a benchmark structure of DNPS diode has been investigated. The structure under study is an area diode with dimension 800µm × 800µm. The output parameters from extraction and simulation are summarized in Table IV. Results of DC behaviors including forward and reversed biased conditions are reported in Figure 6. Results from simulations are drawn with straight lines and measurements with dots. In the same figure, curves in colors illustrate also the temperature behaviors at: 27 • C (blue), 75 • C (black) and 125 • C (red).

B. Modeling of lateral NPN

Modeling of parasitic lateral NPN BJT is a hard task. In HV-CMOS technology, the emitter of NPN BJT is the injecting N-well of substrate currents (usually power device), the collectors are the surrounding N-wells while the base is the whole substrate. Therefore, extraction of this parasitic device with layout geometry becomes impossible by using standard BJT model. In our methodology, modeling of such parasitic lateral NPN BJT is realized by constructing substrate network as shown in Figure 7. This substrate network models lateral NPN BJT with back-to-back diodes only according to layout geometry. Eventually, bipolar effect of parasitic lateral NPN can be added to circuit schematic. The second structure is from an industrial design test chip, named test-chip 1. This test chip has 15 DNPS diodes sharing the same substrate. It has 16 I/O PADs: the first 15 of them (PADs 1 to 15) connect to each of the 15 N-wells individually, and the last one (PAD16) connects to P-well rings, which are the surrounding substrate contact of the 15 N-wells. The whole test-chip is extracted using our methodology (reported in Table IV). Extraction of whole chip is performed in two steps: 1) the extraction of device (each DNPS diode individually); 2) the extraction of substrate region outside devices. The structure with meshing is depicted in Figure 8a. Since the models in ams AG process include these 15 DNPS diodes, they should be disabled during circuit simulations because our substrate model already takes them into account.

In our test case, as shown in Figure 8b, 5 Nwells PAD1 to PAD5 are involved. We mainly focus on this test structure the investigation of parasitic lateral NPN BJTs where the distance effect is under study. Each N-well has the same dimension (20µm × 20µm), thus different spacing to PAD 5. As for simulation, PAD5 is the emitting point of substrate current while collector is one of the 4 other PADs, and the others are left open. A good agreement to measurements shows reliable results from simulation (see Figure 9), while the temperature behaviors are considered as well.

C. Modeling of vertical NPN and PNP

In HV-CMOS technology, a deep N-well isolates the transistors from the substrate. Inherently this structure introduces a parasitic vertical NPN (for N-MOS) or PNP (for P-MOS) bipolar junction transistor (BJT). The drain of P-MOS transistor corresponds to the emitter of vertical PNP, which is usually connected to the load. The below ground or above supply voltage condition activates the vertical BJT that injects substrate current into the substrate. This kind of configuration is often seen in HV automotive application. Typically, the effect of parasitic vertical BJT can be added in compact model of standard spice model. However, the propagation of substrate currents is impossible to model since they are layout dependent. Hence, modeling of parasitic BJT is also considered in our methodology.

In previous test structure, effect of the parasitic lateral NPN is observed by adding lateral connected back-to-back diodes

PAD5 to PAD2

ie(-25c, m) ic(-25c, m) ic(-25c, s) ie(-25c, s) ie(27c, m) ic(27c, m) ic(27c, s) ie(27c, s) ie(125c, m) ic(125c, m) ic(125c, s) ie(125c, s) 27c 75c 125c Ve [V] -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 ie, ic [A] 10 -15 10 -10 10 -5 10 0

PAD5 to PAD3

ie(-

[V] -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 ie, ic [A] 25c, m) ic(-25c, m) ic(-25c, s) ie(-25c, s) ie(27c, m) ic(27c, m) ic(27c, s) ie(27c, s) ie(125c, m) ic(125c, m) ic(125c, s) ie(125c, s) 125c 27c 75c Ve
10 -15 10 -10 10 -5 10 0

PAD5 to PAD4

ie(-25c, m) ic(-25c, m) ic(-25c, s) between N-wells. Following the introduced methodology, extraction of parasitic vertical BJT results from various N and P wells of the substrate. Hence, various types of parasitic diodes are extracted at the PN junction of wells. The back-toback connection of these enhanced diodes propagates minority carriers allowing NPN transistor simulations. In the same way, the front-to-front connection of the enhanced diodes can simulate parasitic PNP transistor [START_REF] Stefanucci | Spice-Compatible Modeling of High Injection and Propagation of Minority Carriers in the Substrate of Smart Power ICs[END_REF]. Besides the DNPS diode (yellow), DPDN diode (blue) and NDDP diode (green) are the two other parasitic diodes to extract (as mentioned at Table III). The calibration of these diodes are performed by using the standard bipolar cells from library which has well defined structure of vertical BJT, see Figure 10. Report on extraction and simulation of two BJTs is summarized in Table IV. It has to be noticed that if the target process/models include already these parasitic vertical BJT's then designers would need to disable the instantiation of these BJT's during circuit simulations, since they are included in our substrate model. Curves from simulation are depicted in Figure 11, DC behaviors of BJTs are confirmed by fitting the simulation with measured data.

V. CASE STUDY

A. Current Mirror

Current mirror is a simple circuit that is widely used in analog IC design. This circuit is designed to replicate a current through one active current path (reference current) to another active current path of circuit, therefore keeping the output current constant regardless of loading. In this case under study, we are interested in the influence of substrate currents to this basic analog circuit. The test circuit is illustrated in Figure 12. Transistor M1 is a self-biasing N-channel LDMOS transistor that injects substrate currents from a negative supply voltage source marked as "Vin" in figure. Transistors M2 and M3 are also N-channel LDMOS and have the same size (i.e. W and L) as transistor M1, thus transistor M2 is closer to M1 than transistor M3 in layout point of view. They are used as a current mirror sink having two different configurations:

• case 1: transistor M2 is the current source of current mirror configuration, it is closed to aggressor M1; • case 2: transistor M3 is the current source of current mirror configuration, then it is farther from aggressor M1;

The extracted substrate networks in both cases are the same, because they have the same geometry in substrate as depicted in Figure 12c. The extracted netlist of substrate parasitic is back-annotated to circuit schematic through the extracted PIN.

A transient signal of negative pulse (-1V, 2µs) is applied to input voltage source, see Figure 13 d M 1-M 2 < d M 1-M 3 . As a consequence, the voltage drop at DNTUB of transistor M2 is higher than of transistor M3.

• In case 1, transistor M2 is the source of current mirror who converts current into voltage. The voltage drop at drain of M2 (D2) causes the drop of controlling voltage at the gate of M2. Because controlling voltage drops, the mirrored current at transistor M3 decreases. However, the drop of mirrored current cannot be compensated by the increase of coupled substrate currents, then the total current at M3 (I Out) decreases. On the contrary, the total current at M2 (I Ref) increases since the coupled substrate currents are more significant. • In case 2, transistor M3 is the source of current mirror.

Since M3 is farther than M2 from the aggressor of substrate currents, the interference of coupling to mirrored current is less than in the previous case. Hence the decrease of mirrored current is less important than the coupled substrate currents. In both sides, the total currents at M2 (I Out) and M3 (I Ref) are increased depending on the distance to M1.

In Figure 13, results of simulation confirm the correct behaviors of substrate parasitic NPN BJT under test conditions. The interferences of substrate noise to the basic current mirror circuit are clearly observed by using our tool. However, this effect cannot be simulated in the conventional way since the lack of modeling of parasitic NPN BJTs.

B. Test-chip 2

The second test case is from an industrial design and fabricated test chip [START_REF] Tomasevic | Bandgap failure study due to parasitic bipolar substrate coupling in Smart Power mixed ICs[END_REF]. The principle structure under study is shown in Figure 14. The entry is an IO PAD which consists of two series connected diodes supplied between VDD and ground. The injection point for the aggressor is between two diodes marked as "Vin" in Figure 14. Two N-wells with geometry d4 × d6 each, are placed to collect the injected charges. The distance to the emitter is different as d5 for the closer placed one (DN1) and d5 + d6 + d7 for the second one (DN2). The output "Vout" is implemented as PAD. Laser cut options are used to connect or disconnect the different N-wells to PAD "Vout".

In order to reach production maturity, all automotive products must pass qualification tests. Some of these tests may cause substrate parasitic currents. In our test case, a standard automotive test signal (ISO 7637-2 Pulse 1) is applied as injecting signal to PAD "Vin". This input signal is an example of severe test signal requiring that the product remains fully functional while the output terminals are stressed with negative voltage. The behavior of this test signal is shown on the top of Figure 15. It simulates a negative polarity transient pulse caused by the disconnection of the DC supply through an inductive load. The peak voltage "Vs" is varied as 6V, 12V

Fig. 1 .

 1 Fig. 1. Modeling approach for substrate parasitic extraction in case of simple diode.

Fig. 2 .

 2 Fig. 2. Overall flow of post-layout extraction.

  Fig.3. 2D-meshing at each slice: (b) "top", (c) "middle", (d) "bottom", and (a) N+/P+ diffusions on the surface of "top". {a1, a2,...} are coordinates at x-axis, and {b1, b2, ...} are coordinates at y-axis. Lines in black represent the mesh lines. Lines in red represent ideal connections in the future netlist. Component symbols in yellow and red are DNPS diodes and resistors in P-substrate respectively.

Fig. 4 .

 4 Fig. 4. Idea of 2-D mesh refinement at "top" slice. The red points in (b) represent the vertices of geometrical shapes (DPTUB layer is polygon and DNTUB layer is rectangle).

Fig. 5 .

 5 Fig. 5. Basis of a parasitic component extraction from 2 meshed cuboids. Centers act as nodes in resulting netlist. At each center, two nodes are used: one for majority carriers (red) and the other for minority carriers (blue).

  BENCHMARKINGCalibration of technology parameters, such as doping profile and carriers' lifetime, is performed using industrial benchmark structures. Various structures to benchmark the diodes in terms of geometry (area, perimeter), and technology patterns (e.g. DNPS diode, DPDN diode, etc) are provided by ams AG.

Fig. 6 .Fig. 7 .

 67 Fig. 6. Temperature behaviors in both forward and reverse biased conditions, at 27 • C (blue), 75 • C (black) and 125 • C (red).

  point of substrate current (c) Color map in test case

Fig. 8 .

 8 Fig. 8. (a) Meshing of the entire test-chip; (b) simplified structure of test case. (c) color map of voltage distribution in terms of minority carriers.

75cFig. 9 .

 9 Fig. 9. Current-voltage characteristics and temperature behaviors: -25 • C (blue), 27 • C (black) and 125 • C (red) of parasitic lateral NPN BJTs. The currents at emitter (Ie) and collector (Ic) are shown in figure while simulation (straight lines are Ie and dash lines are Ic) is compared to measurement (triangle symbols are Ie and circle symbols are Ic). The distance effect is observed also from the 4 test cases where collector is PAD1 to PAD4 respectively (from top to bottom).

Fig. 10 .Fig. 11 .

 1011 Fig. 10. Structure of NPN (VERTN1, a) and PNP (VERTPH, b) BJT and their equivalent circuits modeled by our methodology.

Fig. 12 .Fig. 13 .

 1213 Fig. 12. (a, b) Test circuit of 2 current mirror configurations, and (c) the equivalent substrate network.

Fig. 14 .

 14 Fig. 14. (a) Layout view of test-chip 2 and chosen test case; (b) simplified structure of test case.

Fig. 15 .

 15 Fig. 15. Result of fast transient simulation with automotive test pulse: as 6V, 12V or 20V peak voltage. Voltages simulated at output on 50Ω with or without our tool. Laser cut option to choose the corresponding N-well: DN1 or DN2.

RC Extraction Substrate Extraction Extraction Engine Rules Reduction Phase Extraction Phase Meshing Phase Substrate Netlist Post-layout extraction LVS, QRC Layout with Extracted PIN Layout Final Netlist Schematic + Symbol

TABLE II LIST

 II OF PARAMETERS TO EXTRACT FOR PARASITIC COMPONENTS.

	Parasitic model	Doping profile	Geometrical parameters Length [m] Area [m 2 ]
	Diode	n p	La/2 L b /2
	Resistor	n or p	La/2 + L b /2	w × h
	Homo-junction	n or p n+ or p+	La/2 L b /2

  Table III lists all combinations of parasitic component to extract according to describing rules.

TABLE III POSSIBLE

 III COMBINATIONS AND THE AVAILABLE PARASITIC COMPONENTS.

ACKNOWLEDGMENT

This work was supported by the project AUTOMICS: Pragmatic solution for parasitic-immune design of electronics ICs for automotive, which is funded by the European Commission within the 7 th Framework Program (FP7/ICT 314135). The authors would like to thank the consortium of European project AUTOMICS for their technical cooperation.

This work was supported by the European commission through the European FP7 within the AUTOMICS Project.

and 20V for different tests. The recovery time of this pulse signal is 2ms. Finally the voltage supply VDD is 14V .

Results for this tests are shown in the rest of the Figure 15 as voltage at output "Vout" measured on 50Ω. The curves displayed are according to the different values of peak voltages: 6V (green), 12V (yellow) and 20V (red). In the conventional way, signals caused by substrate coupling cannot be simulated. However by using our tool, pulse signals are observed on the corresponding well (DN1 and DN2). In agreement, the simulated signal on the corresponding well is higher for the larger input signal. Shorter distance to the substrate current source results in a higher signal.

VI. CONCLUSION

Substrate noise modeling becomes of interest for designing Smart Power ICs. The noise coupling in substrate is due to carriers injection and propagation, in particular from HV power devices. Moreover, they could be even worse in high operating temperature condition. In conventional way, this kind of coupled noises are not predictable in simulation because the lack of modeling of substrate parasitic lateral NPN. In this paper, a post-layout extraction and simulation methodology for substrate parasitic was presented. This methodology is based on a layout extraction tool where substrate network is generated. The use of our tool completes the existing post-layout verification flow. Thus the behaviors of substrate currents can be also taken into account in simulation. In 0.35µm process node of ams AG HV-CMOS technology, we extracted the technology parameters of substrate model from various benchmark structures. We have investigated in this work the effect of parasitic lateral NPN BJTs in two different test cases: the interferences of substrate currents to a current mirror configuration was studied at first. Then, an automotive test case was included. The proposed approach at post-layout stage gives the designers the possibility to simulate the substrate parasitic behaviors. The verification at early phase before fabrication enables the optimization of design against substrate coupling. Eventually, it contributes to reduce the design cycle thus increases the reliability and safety of Smart Power ICs. Heimo Gensinger is Principal Engineer at ams AG, a leading designer and manufacturer of high performance analog ICs. Heimo has been working in the semiconductor industry for more than twenty years. His current responsibility is the development of ams' high voltage design environment. Heimo holds a degree in Electronic Engineering from the Technical University of Graz, Austria, in 1997.

Ehrenfried Seebacher earned an M.Sc. in physics at Graz University of Technology in 1993. From 1994-1998 he has been working in the R&D department of austriamicrosystems, on compact modeling of CMOS, BiCMOS and HV CMOS processes. Since 1999 he is the section manager of a group responsible for compact modeling, process characterization, physical verification, and DFM. His scientific interests are compact modeling of MOS, bipolar transistors and passive elements mixed-mode circuits and specialized electro-optical system-on-chip solutions. He now is a senior manager of the EDA department at ams AG and a project leader of technology and PDK development projects. He authored or coauthored more than 30 papers. Since 2013, she is the head of the System on Chip Department at LIP6.


Emmanuel Moulay
email: emmanuel.moulay@univ-poitiers.fr

Time-dependent cosmological interpretation of quantum mechanics

Keywords: Emmanuel Moulay, Time-dependent cosmological interpretation of quantum mechanics, 2016

published or not. The documents may come

Introduction

A new interpretation of quantum mechanics, called the cosmological interpretation of quantum mechanics, has been developed in order to take into account the new paradigm of eternal inflation [START_REF] Aguirre | Born in an infinite universe: A cosmological interpretation of quantum mechanics[END_REF][START_REF] Moulay | Non-collapsing wave functions in an infinite universe[END_REF][START_REF] Vilenkin | A quantum measure of the multiverse[END_REF]. Eternal inflation can lead to a collection of infinite open Friedmann-Lemaître-Robertson-Walker (FLRW) bubble universes belonging to a multiverse [START_REF] Coleman | Gravitational effects on and of vacuum decay[END_REF][START_REF] Garriga | Eternal inflation, bubble collisions, and the persistence of memory[END_REF][START_REF] Guth | Eternal inflation and its implications[END_REF]. This inflationary scenario is called open inflation [START_REF] Linde | Toy model for open inflation[END_REF][START_REF] Yamauchi | Open inflation in the landscape[END_REF]. Such a multiverse implies that there exist an infinite number of observers belonging to similar observable universes which are indistinguishable inside an infinite open FLRW bubble universe [START_REF] Aguirre | Born in an infinite universe: A cosmological interpretation of quantum mechanics[END_REF][START_REF] Tegmark | Parallel universes[END_REF]. A quantum state |Ψ i ∈ H is associated with each observer i belonging to these similar observable universes and it is possible to define a quantum state gathering all these observers

|Ψ ∞ = ∞ i=1 |Ψ i (1)
which belongs to the Hilbert space

H ⊗∞ := H ⊗ H ⊗ H ⊗ • • • (2)
For sake of simplicity, we only consider pure states in this article. The reader may refer to [START_REF] Bub | How to solve the measurement problem of quantum mechanics[END_REF][START_REF] Gutmann | Using classical probability to guarantee properties of infinite quantum sequences[END_REF][START_REF] Neumann | On infinite direct products[END_REF][START_REF] Neumann | Quantum mechanics of infinite systems[END_REF] for more details about the notion of infinite quantum states. Such a modelling is compatible with the Born rule [START_REF] Aguirre | Born in an infinite universe: A cosmological interpretation of quantum mechanics[END_REF][START_REF] Farhi | How probability arises in quantum mechanics[END_REF][START_REF] Finkelstein | The logic of quantum physics[END_REF][START_REF] Hartle | Quantum mechanics of individual systems[END_REF][START_REF] Vilenkin | A quantum measure of the multiverse[END_REF] and can avoid the problem of wave function collapse [START_REF] Moulay | Non-collapsing wave functions in an infinite universe[END_REF]. However, the notion of time is not well defined because similar observable universes are not causally related.

The first goal of this article is to define a time-dependent quantum state for observers in similar observable universes. This problem can be solved by using the particle horizon and the Fischler-Susskind cosmological holographic principle [START_REF] Fischler | Holography and cosmology[END_REF][START_REF] Susskind | An introduction to black holes, information and the string theory revolution[END_REF]. The holographic principle has also been used in [START_REF] Bousso | Multiverse interpretation of quantum mechanics[END_REF][START_REF] Nomura | Physical theories, eternal inflation, and the quantum universe[END_REF] to render the many-worlds interpretation of quantum mechanics compatible with eternal inflation.

The second goal of this article is to prove that the wave function collapse of the time-dependent quantum state for observers in similar observable universes is avoided.

The organization of the article is the following. In Section 2, a timedependent quantum state is defined for observers belonging to similar observable universes of an infinite open FLRW universe by using the particle horizon. The problem of wave function collapse of this quantum state is addressed in Section 3.

Time-dependent quantum states

Let us consider two similar observers belonging to two similar observable universes of an infinite open FLRW universe which are indistinguishable. Let us denote by |Ψ 1 the quantum state of the observer 1 and by |Ψ 2 the quantum state of the observer 2. We may wonder if it is possible to define a common notion of time for these two observers. We want to use the time elapsed since the creation of the particle horizon as the same reference time. We may wonder if the two observers belonging to two similar observable universes at a given time have a similar past since the creation of the particle horizon.

The FLRW metric is given by

ds 2 = c 2 dt 2 -a(t) 2 dr 2 1 -kr 2 + r 2 dΩ 2 .
(

) 3
and a natural definition of a cosmological horizon for a FLRW universe is the particle horizon whose proper radius is defined at time t by

R P (t) = a(t) t ti c a(s) ds (4)
where t i denotes the post-inflationary epoch [START_REF] Coles | Cosmology: The origin and evolution of cosmic structure, 2nd Edition[END_REF]Section 2.7]. The particle horizon is the largest comoving spatial distance from which light could have reached an observer if it was emitted at time t i [START_REF] Roos | Introduction to cosmology[END_REF]. It represents the boundary between the observable and the unobservable regions of the universe for an observer.

A particle cannot be ejected out of the observable universe of an observer by crossing his particle horizon [23, page 37]. It implies that the existence of the particle horizon ensures that an observer has access to the information concerning the past of his observable universe since the creation of the particle horizon, even if there is a repulsive cosmological constant. The Fischler-Susskind cosmological holographic principle, which ensures that the particle horizon is compatible with special relativity [START_REF] Fischler | Holography and cosmology[END_REF][START_REF] Bak | Holographic principle and string cosmology[END_REF], states that the entropy of matter inside the post-inflationary particle horizon must be smaller than the area of the cosmological horizon [START_REF] Fischler | Holography and cosmology[END_REF][START_REF] Kaloper | Cosmology versus holography[END_REF]. It is true for open and classical flat FLRW universes [START_REF] Bousso | The holographic principle[END_REF]. As open inflation leads to infinite open FLRW bubble universes [START_REF] Coleman | Gravitational effects on and of vacuum decay[END_REF][START_REF] Garriga | Eternal inflation, bubble collisions, and the persistence of memory[END_REF][START_REF] Guth | Eternal inflation and its implications[END_REF], the Fischler-Susskind cosmological holographic principle can be applied in this framework.

Thus, we have the following result: We define the quantum state

|Ψ 12 (t) = |Ψ 1 (t) ⊗ |Ψ 2 (t) , t i ≤ t ≤ t f (5)
and we know that |Ψ 1 (t) and |Ψ 2 (t) are indistinguishable for all t i ≤ t ≤ t f . If we consider all the quantum states of all the observers having an observable universe similar to the observable universes 1 and 2 in an infinite open FLRW universe, then the generalization to the quantum state ( 1) is straightforward and we obtain the time-dependent quantum state

|Ψ ∞ (t) = ∞ i=1 |Ψ i (t) , t i ≤ t ≤ t f (6)
associated with the cosmological interpretation of quantum mechanics Let us remark that it is possible to extend the existence of the particle horizon of an open FLRW universe to the Planck epoch by using string cosmology [START_REF] Bak | Holographic principle and string cosmology[END_REF].

Wave function collapse

Wave function collapse associated with the quantum state (6) must be avoided after the post-inflationary epoch t i . If there exists a meta-observer who is able to know the global result of a measurement process occurring in each similar observable universe of the multiverse at a given time then the measurement problem cannot be avoided. We have shown in [START_REF] Moulay | Non-collapsing wave functions in an infinite universe[END_REF] that the collapse of the time-independent quantum state (1) can be avoided. However, the same reasoning cannot be used for the time-dependent quantum state [START_REF] Guth | Eternal inflation and its implications[END_REF]. Indeed, if a measurement is done at time t m > t i , all quantum states |Ψ i (t) collapse at the same time t m after the post-inflationary epoch which was not the case for time-independent quantum states.

First, let us remark that if we have only a finite fixed number of similar observable universes, the wave function collapse cannot be avoided. Suppose that we have only a finite fixed number N of similar observers i in similar observable universes having quantum states |Ψ i (t) . Just after the measurement at time t + m = t m + ǫ, we may have for instance

Ψ i (t + m ) = Ψ j (t + m ) (7)
for all i, j ∈ {1, • • • , N } where ǫ > 0 is a sufficiently small number. So, the quantum state N i=1 |Ψ i (t) collapses at time t m and all its possible evolutions cannot be explored. Let us remark that the Born rule is also not satisfied in a large but finite universe [START_REF] Page | The Born rule fails in cosmology[END_REF][START_REF] Page | Born's rule is insufficient in a large universe[END_REF] whereas it can be recovered in an infinite universe by using the frequency operator [START_REF] Aguirre | Born in an infinite universe: A cosmological interpretation of quantum mechanics[END_REF].

Then, we prove that the wave function collapse of the time-dependent quantum state |Ψ ∞ (t) is not possible. Let us denote by t - m the time just before the measurement in each similar observable universe and t + m the time just after the measurement. We study the quantum state |Ψ ∞ (t - m ) in order to see if its collapse is possible. As the number of quantum states in a finite region of the universe is finite [START_REF] Tegmark | Parallel universes[END_REF], there exists 1 < K < +∞ such that for all i ∈ N * = N \ {0}

Ψ i (t - m ) = K k=1 α ik Ψ k (t + m ) (8)
where α ik ∈ C and

K k=1 |α ik | 2 = 1. (9)
We have

Ψ ∞ (t - m ) = ∞ i=1 Ψ i (t - m ) = lim N →+∞ N i=1 K k=1 α ik Ψ k (t + m ) (10)
We develop the previous expression in square brackets and we obtain

Ψ ∞ (t - m ) = lim N →+∞   fN ∈TN N i=1 α ifN (i) Ψ fN (i) (t + m )   (11)
where T N is the set of all the functions between {1, • • • , N } and {1, • • • , K}.

We also have card(T N ) = K N . Then, we gather the coefficients α by using the properties of the tensor product and it leads to

Ψ ∞ (t - m ) = lim N →+∞   fN ∈TN p fN N N i=1 Ψ fN (i) (t + m )   (12)
with

p fN N = N j=1 α jfN (j) . (13)
The term

p fN N 2 = N j=1 α jfN (j) 2 = N j=1 α jfN (j) 2 (14)
is the probability of having the quantum state N i=1 Ψ fN (i) (t + m ) for the first N observable universes. Let T be the set of all the functions between N * and {1, • • • , K} and

p f = lim N →+∞ p fN N = ∞ j=1 α jf (j) (15)
with f = lim N →+∞ f N ∈ T then we have

Ψ ∞ (t - m ) = f ∈T p f ∞ i=1 Ψ f (i) (t + m ) . (16)
In [START_REF] Moulay | Non-collapsing wave functions in an infinite universe[END_REF], we have proved that

|α ik | = |α jk | (17)
for all i, j ∈ N * by using the Finkelstein-Hartle theorem [START_REF] Finkelstein | The logic of quantum physics[END_REF][START_REF] Hartle | Quantum mechanics of individual systems[END_REF]. As

|α ik | 2 < 1 (18)
for all i ∈ N * , k ∈ {1, • • • , K}, we have lim N →+∞ p fN N 2 = ∞ j=1 α jf (j) 2 = 0 (19)
for all f ∈ T . Indeed, a necessary condition for the product ∞ j=1 α jf (j) 2 to be equal to a finite non zero positive real number is that

lim j→+∞ α jf (j) 2 = 1. (20)
The reader may refer to [START_REF] Melnikov | Green's functions and infinite products: bridging the divide[END_REF]Chapter 2] for more details on infinite products. It is obvious that Condition (20) cannot be satisfied if we have [START_REF] Fischler | Holography and cosmology[END_REF] and [START_REF] Susskind | An introduction to black holes, information and the string theory revolution[END_REF]. Let us remark that even if K = +∞ which corresponds to an infinite number of quantum states in a finite volume, a necessary condition for ( 9) is that lim k→+∞ |α ik | 2 = 0 which is also not compatible with [START_REF] Nomura | Physical theories, eternal inflation, and the quantum universe[END_REF]. Finally, the result given by ( 19) leads to the following proposition: Proposition 2 The probability of measuring the following quantum state

∞ i=1 Ψ f (i) (t + m ) (21)
is zero for all f ∈ T . Thus, the collapse of the quantum state |Ψ ∞ (t - m ) is not possible.

We have defined a time-dependent quantum state |Ψ ∞ (t) for observers in similar observable universes in Section 2 and we may wonder why this quantum state does not collapse. This is due to the fact that the wave function collapse is associated with the notion of observer. In an infinite universe, this notion of observer falls down and then also the notion of wave function collapse. An observer i can only see the wave function collapse of his quantum state |Ψ i (t) and he also knows that all the other observers in similar observable universes can see the wave function collapse of their quantum state at the same time t m elapsed since the post-inflationary epoch t i with a probability in accordance with the Born rule [START_REF] Aguirre | Born in an infinite universe: A cosmological interpretation of quantum mechanics[END_REF]. However, the global picture is not the wave function collapse of the quantum state |Ψ ∞ (t) at time t m with the existence of a meta-observer.

  Proposition 1 If two similar observers of an infinite open FLRW universe have indistinguishable observable universes at time t f after the post-inflationary epoch t i then they have similar observable universes since the post-inflationary epoch, i.e. the quantum states |Ψ 1 (t) and |Ψ 2 (t) are indistinguishable for all t i ≤ t ≤ t f .

Acknowledgements

The author wants to thank Anthony Aguirre from the University of California for helpful discussions.