Xavier Michel

Alexandre Verle

Nadine Azemard

Philippe Maurine

Daniel Auvergne

Optimization Protocol Based on Performance Metric

Keywords: Performance optimization, constraint feasibility, constraint distribution, gate sensitivity, sizing, buffer insertion

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I. INTRODUCTION

he design of more and more complex, integrated and fast circuits implies to manage trade-off between speed, power and area can be achieved with circuit simulators and critical path analysis tools to modify iteratively the size of the transistors until complete constraint satisfaction [START_REF] Shyu | Optimization-based transistor sizing[END_REF][START_REF] Fishburn | Tilos : a posynomial programming approach to transistor sizing[END_REF][START_REF] Sapatnekar | An exact solution to the transistor sizing problem for CMOS circuits using convex functions[END_REF][START_REF] Sutherland | Logical effort, designing fast cmos circuits[END_REF]. More general speed-up techniques involve buffer insertion [START_REF] Vemuru | CMOS tapered buffer[END_REF][START_REF] Jiang | Interleaving buffer insertion and transistor sizing into a single optimization[END_REF] and logic transformation [START_REF] Paulin | Logic decomposition algorithm for the timing optimization of multilevel logic[END_REF]. If these techniques may be found efficient for speeding-up combinational paths they may have different impacts in the resulting power dissipation or area. Gate sizing is area (power) expensive and, due to the resulting capacitive loading effects, may slow down adjacent upward paths. This implies complex and iterative timing verifications. Buffer insertion preserves path interaction but is only efficient for relatively highly loaded nodes. To manage these alternatives it is necessary to evaluate and compare the performance of the different implementations. Without using any robust indicator, selecting between all these different techniques for the various gates of a library is NP complex and induces more iterative attempts which are processing time explosive.

A reasonable selection of speed-up technique must be based on a characterization of the available speed on a critical path, on the determination of the critical nodes and the characterization of the gate sensitivity to the sizing or buffering alternatives.

The main contribution of this paper is to define different metrics for path characterization, transistor sizing and buffer insertion, to be used as efficient indicators for characterizing the logic gates in terms of sensitivity to the sizing and buffering techniques.

Section II presents the elements used to define the optimization protocol. The optimization alternative with structure conservation is presented and validated in section III. The proposed optimization method with structure modification is detailed and validated in section IV, in which the resulting optimization protocol is presented, before to conclude in section V.

II. OPTIMIZATION PROTOCOL

Current path optimization tools [START_REF] Singh | Power Conscious CAD tools and Methodologies: a Perspective[END_REF] require large CPU times and too significant calculation computer resources to manage the complexity of nowadays developed circuits [START_REF] Chen | Critical Path Selection for Performance Optimization[END_REF]. The uncertainty in parasitic capacitance estimation imposes to use many iterations or to consider very large safety margin resulting in oversized circuits.

A. Optimization tool

As a solution to these drawbacks, we have developed an analysis and performance optimization tool based on an accurate representation of the physical abstraction of the layout (POPS: Performance Optimization by Path Selection) [START_REF] Azemard | POPS : A tool for delay/power performance optimization[END_REF]. It gives facilities in analyzing and optimizing combinatorial circuit paths in submicronic technologies.

This tool allows to consider an user specified limited number of paths [START_REF] Yen | Efficient Algorithms for Extracting the k Most Critical Paths in Timing Analysis[END_REF][START_REF] Crémoux | Path resizing based on incremental technique[END_REF], for easy application and validation of the different path optimization criteria. The delay model implemented in this tool is based on an analytical representation of the timing performance, allowing to obtain for any logic gate, in its environment, an accurate evaluation of its switching delay and output transition time.

B. Delay Model

Real delay computation must consider finite input ISBN 2-9522971-0-X transition and I/O coupling [START_REF] Jeppson | Modeling the Influence of the Transistor Gain Ratio and the Input-to-Output Coupling Capacitance on the CMOS Inverter Delay[END_REF]. We capture the effect of the input-to-output coupling and the input slope effect in the delay as: (1) where v TN,P represents the reduced value (V T /V DD ) of the threshold voltage of the N,P transistors. ? INHL,LH , ? outHL,LH are the input and output transition time duration, respectively. C M is the coupling capacitance between the input and output nodes, that can be evaluated as one half the input capacitance of the P(N) transistor for input rising (falling) edge, respectively or directly calibrated from SPICE simulation.

) i ( 2 ) C C C 2 1 ( ) 1 i ( 2 v ) i ( t ) i ( 2 ) C C C 2 1 ( ) 1 i ( 2 v ) i (
The general expression of the transition time has been developed in [START_REF] Maurine | Transition time modeling in deep submicron CMOS[END_REF]

where ? is a time unit that characterizes the process. C L , and C IN represent, respectively, the output load and the gate input capacitance. S HL,LH represent the symmetry factor of the falling, rising edges. R represents, for identical load and drive capacitance, the ratio of the current value available in N and P transistors, k is the P/N configuration ratio and D WHL,LH the gate logical weight defined by the ratio of the current available in an inverter to that of a serial array of transistors [START_REF] Maurine | Transition time modeling in deep submicron CMOS[END_REF].

If eq.2,3 are quite similar to the logical effort expressions [START_REF] Sutherland | Logical effort, designing fast cmos circuits[END_REF], they only represent the transition time expression. The delay is given by (1) that completely captures the input-tooutput coupling and the input transition time effect on the delay. Using these expressions to define metrics for optimization, we always consider that the resulting implementation is in the fast input control range [START_REF] Maurine | Transition time modeling in deep submicron CMOS[END_REF].

As shown from eq. (1-3) the delay on a bounded combinatorial path is a convex function and these expressions can easily be used to determine the best condition for path optimization under delay constraint.

By bounded combinatorial path we signify that the path input gate capacitance is fixed by the load constraint imposed on the latch supplying the path. This implies that the path terminal load is completely determined by the total input capacitance of the gates or registers controlled by this path. This guarantees the convexity of the delay on this path.

III. OPTIMIZATION WITH STRUCTURE CONSERVATION

The goal of gate sizing is to determine the optimum size for path delay constraint satisfaction at the minimum area/power cost. For that an essential parameter to be considered is the feasibility of the constraint imposed on the path. The target of this section is twofold: defining the delay bounds of a given path and determining a way for distributing a delay constraint on this path with the minimum area/power cost.

A. Constraint feasibility

This is the important section of this approach. Without indication on the feasibility of a constraint any iterative method may infinitely loop with no chance to reach a solution. For that, in order to verify the feasibility of a constraint, we explore the path optimization space by defining the max and min delay bounds (Tmax, Tmin) of this path. It is clear that if the delay constraint value is lower than the minimum delay achievable on this path, whatever is the optimization procedure, there is no way to satisfy the constraint without path modification. These bounds are of great importance in first defining the optimization alternative.

Theoretically and without gate size limitation, no upper delay bound can be defined on a path. To define a pseudoupper bound we just consider a realistic configuration in which all the gates are implemented with the minimum available drive.

The definition of the lower bound has been the subject of numerous proposals. For ideal inverters without parasitic loading the minimum is reached when all the inverters have an equal tapering factor that can be easily calculated from a first order delay representation [START_REF] Paulin | Logic decomposition algorithm for the timing optimization of multilevel logic[END_REF][START_REF] Mead | Minimum propagation delays in VLSI[END_REF]. Applying the explicit representation given in (1) to a bounded combinatorial path, the inferior delay bound is easily obtained by canceling the derivative of the path delay with respect to the input capacitance of the gates. This results in a set of link equations ? ?

) 1 i ( C ) i ( C ) 1 i ( C A A ) i ( C IN
where (i) specifies the rank of the gate, C par (i) is the gate (i) output parasitic capacitance and the A i correspond to the design parameters involved in [START_REF] Shyu | Optimization-based transistor sizing[END_REF][START_REF] Fishburn | Tilos : a posynomial programming approach to transistor sizing[END_REF].

As shown, the size of gate (i) depends on that of (i+1) and (i-1). This is exactly what we are looking for. Instead to solve the corresponding set of equations we prefer to use an iterative approach starting from a local solution defined with C IN (i-1) equal to the minimum available drive (C REF ). Then processing backward from the output, where the terminal load is known, to the input, we can easily determine an initial solution. Then by applying this solution in (4) we can reach, after few iterations, the minimum of delay achievable on the path. An illustration of the evolution of these iterations is given in Fig. 1. We can easily verify that the final value, tmin is conserved whatever is the initial solution, ie the C REF value. This method has been implemented in POPS. First, we identify with POPS the longest path of the different ISCAS and validations with AMPS are made on these longest paths. Validation by Hspice simulations has been obtained by comparing on the longest path of different ISCAS'85 benchmarks (process CMOS, 0.???m) the minimum delay value, obtained from the proposed method, to that reached by an industrial tool (AMPS from Synopsis). Fig. 2 illustrates the resulting comparison that demonstrates the accuracy of the proposed method. For any path the determination of the delay bounds gives facilities in verifying the feasibility of the constraint. For a delay constraint value higher than the minimum bound, the optimization alternative to be chosen is transistor sizing with structure conservation. Next step is to develop a fast technique allowing to efficiently distribute the constraint on the path.

B. Constraint distribution: constant sensitivity method.

Several methods can be used. The simplest method is the Sutherland method [START_REF] Sutherland | Logical effort, designing fast cmos circuits[END_REF], directly deduced from the Mead's optimization rule of an ideal inverter array [START_REF] Mead | Minimum propagation delays in VLSI[END_REF]: the same delay constraint is imposed on each element of the path. If this supplies a very fast method for distributing the constraint, this is at the cost of an over sizing of the gates with an important logical weight value

We propose a new method based on the gate sensitivity to the sizing, that can be directly deduced from (4), as illustrated in Fig. 3.

"a" = 0 corresponds to the minimum, varying the value of this coefficient from 0 to a high negative value allows the exploration of the full design space. Solving: [START_REF] Jiang | Interleaving buffer insertion and transistor sizing into a single optimization[END_REF] supplies a sizing solution for each value of the sensitivity coefficient "a", at which corresponds a value of the path delay. Few iterations on the "a" value allows a quick satisfaction of the delay constraint.

....... a C C C A C 1 A a C C C A C 1 A 2 1 i 1 Pi 2 i 1 i i i 2 i Pi 1 i i 1 i
This method has been implemented in POPS and validated on different ISCAS circuits. In Fig. 4 we compare the final area, given as the sum of the transistor widths (? W), necessary to implement the critical path of each circuit under an identical hard constraint (Tc = 1.2Tmin), using POPS and AMPS. As shown the equal sensitivity method results in a smaller area/low power implementation. In Table 1 we compare the CPU time necessary for AMPS and POPS in sizing under delay constraint different benchmarks. As illustrated the use in POPS of a deterministic approach, results in a two order speed up of the constraint distribution step. When the delay constraint has a smaller value than the minimum delay available, the only alternative is to modify the structure of the path.

IV. OPTIMIZATION WITH BUFFER INSERTION

The goal of this part is to define a way to select between sizing and buffer insertion. We just focus here on the buffer insertion method, that can be easily extended to the logic path modification. The problem is to determine, at minimum area cost, the best location to insert a buffer and the minimal sizing satisfying the delay constraint.

In Fig 5 we represent a path general situation where an overloaded node is guessed to be sped up by buffer insertion. The problem is to remove the guess by a metric directly determining for what level of load a gate switching speed can be improved. For that we compare the delay (1) of the A and B structures for determining at what fan out value (F =C L /C IN ) the B structure becomes faster than A. This defines the "load buffer insertion limit" (Flimit). In a first step we use a local insertion method in which we conserve the size of gates (i-1) and (i) and just size the buffer (4), for minimizing the delay between the output of (i) and the terminal load. The values of these Flimit are listed in Table 2. In the configuration of Fig. 5, (i-1) is an inverter and we have considered the evolution of the limit with the gate (i). A complete characterization must involve all possibility of (i-1) gates and can be done easily following the same procedure. Validation of these limits has been obtained through Hspice simulations. As expected, greater is the logical weight of the gate, lower is the limit that may constitute a measure of the gate efficiency. In fact the buffer insertion acts as a load dilution for the initial gate. In this case the size of this gate can be decreased. A complete consideration of the method involves using the predefined limits for critical nodes identification and then to distribute the delay constraint on the full path using the constant sensitivity method in order to preserve an area efficient gate sizing.

Validation of this approach is given in Table 3 where we compare the minimum delay obtained, from POPS, on the different ISCAS circuits using sizing and buffer insertion techniques. As shown, depending on the path structure significant minimum delay value improvement can be obtained with buffer insertion. Note that considering the delay sensitivity to the gate sizing (Fig. 4), any minimum delay improvement on a path will result in a delay constraint satisfaction with smaller area. This is illustrated in Fig. 6 were we compare, on a 13 gate array, the path delay versus the area for the two methods: gate sizing (full line) and buffer insertion with global gate sizing (dotted line). Three regions can be defined, a weak constraint domain where sizing is the best solution (Tc > 2.5Tmin), a medium constraint domain where buffer insertion is not necessary, but allows path implementation with area reduction (1.2Tmin < Tc <2.5Tmin) and a hard constraint domain (Tc < 1.2Tmin), where buffer insertion is the most efficient alternative.

The resulting optimization protocol, (Fig. 7), has been implemented in POPS for validation on the different ISCAS benchmarks. The comparison of the different steps is illustrated in Fig. 8 where for three different delay constraint values (weak, medium, hard) we compare the path implementation area on the ISCAS circuits.

As shown, if for weak and medium constraints the different optimization methods are quite equivalent in terms of area, for hard constraint the buffer insertion with global sizing always results in important area saving.

Fig. 1 .

 1 Fig. 1. Illustration of the sensitivity of the path delay to the gate sizing.

Fig. 2 .

 2 Fig. 2. Comparison of the min imum delay value (Tmin) determined with POPS and AMPS.

Fig. 3 .

 3 Fig.3. Example of design space exploration on a 11gate path, using the constant sensitivity method.

Fig. 4 .

 4 Fig. 4. Comparison of the constraint distribution methods on different ISCAS circuits.

Fig. 5 .

 5 Fig. 5. Local buffer insertion

Fig. 6 .

 6 Fig. 6. Constraint do main definition

TABLE 1

 1

	CPU T IME COMPARISON IN SATISFYING PATH DELAY CONSTRAINT
	Circuits Circuits	Gate nb Gate nb	POPS (ms) AMPS (ms) POPS (ms) AMPS (ms)
	Adder16 Adder16	99 99	159 159	23700 23700
	fpd fpd	14 14	19 19	6120 6120
	c432 c432	29 29	29 29	9950 9950
	c499 c499	29 29	30 30	9050 9050
	c880 c880	28 28	29 29	9850 9850
	c1355 c1355	30 30	49 49	11400 11400
	c1908 c1908	44 44	49 49	11760 11760
	c3540 c3540	58 58	69 69	15890 15890
	c5315 c5315	60 60	90 90	19400 19400
	c6288 c6288	116 116	210 210	21920 21920
	c7552 c7552	47 47	69 69	16400 16400

TABLE 2

 2

	FANOUT LIMIT (FLIMIT) FOR A GATE (I) CONTROLLED BY AN
		INVERTER.
	Gate i-1 Gate i-1	Gate i Gate i	Calcul. Simulation Calcul. Simulation
	inv inv	inv inv	5,7 5,7	5,9 5,9
	inv inv	nand2 nand2	4,9 4,9	5,4 5,4
	inv inv	nand3 nand3	4,5 4,5	5,2 5,2
	inv inv	nor2 nor2	3,8 3,8	3,5 3,5
	inv inv	nor3 nor3	2,7 2,7	2,5 2,5

TABLE 3 COMPARISON

 3

		OF SIZING AND BUFFER INSERTION T ECHNIQUES
	Circuits Method Tmin(ns) Circuits Method Tmin(ns)	Circuits Method Tmin(ns) Circuits Method Tmin(ns) Circuits Method Tmin(ns)
		sizing sizing	4,53 4,53		sizing sizing sizing	2,66 2,66 2,66
	Adder Adder	buff buff	4,39 4,39	c1908 c1908	buff buff buff	2,32 2,32 2,32
		gain gain	3% 3%		gain gain gain	15% 15% 15%
		sizing sizing	2,22 2,22		sizing sizing sizing	3,29 3,29 3,29
	c432 c432	buff buff	1,97 1,97	c3540 c3540	buff buff buff	3,21 3,21 3,21
		gain gain	13% 13%		gain gain gain	2% 2% 2%
		sizing sizing	1,79 1,79		sizing sizing sizing	3,57 3,57 3,57
	c499 c499	buff buff	1,64 1,64	c5315 c5315	buff buff buff	3,20 3,20 3,20
		gain gain	9% 9%		gain gain gain	12% 12% 12%
		sizing sizing	2,09 2,09		sizing sizing sizing	7,98 7,98 7,98
	c880 c880	buff buff	1,71 1,71	c6288 c6288	buff buff buff	7,74 7,74 7,74
		gain gain	22% 22%		gain gain gain	3% 3% 3%
		sizing sizing	2,16 2,16		sizing sizing sizing	3,08 3,08 3,08
	c1355 c1355	buff buff	1,89 1,89	c7552 c7552	buff buff buff	2,60 2,60 2,60
		gain gain	14% 14%		gain gain gain	18% 18% 18%

V. CONCLUSION

Based on a realistic model for gate timing performance, we have defined metrics for selecting path optimization alternatives. We have proposed a method for determining the minimum delay, Tmin, achievable on a path. Then we have defined, at gate level, the fan out limit for buffer insertion, Flimit. Flimit has been used to determine the path critical nodes and Tmin, to select between sizing and buffer insertion alternatives. We have defined a gate sensitivity factor "a", to distribute the delay constraint, allowing path optimization at provably minimum area cost. These metrics have been used to define a general path optimization protocol that has been implemented in an optimization tool.

Validation on various benchmark circuits has demonstrated the validity of the defined boundaries for selecting between the different optimization alternatives.


A Verle

P Maurine
email: pmaurine@lirmm.fr

N Azémard
email: azemard@lirmm.fr

D Auvergne
email: auvergne@lirmm.fr

Definition of P/N Width Ratio for CMOS Standard Cell Library

The efficiency of cell-based design synthesis of high performance circuit is strongly dependent on the content of the library. Great effort has been given in the design of libraries, to define the optimal selection of the logic gate drive strength. But few justifications are available to determine the P/N width ratio of each cell. In this paper we use an extension of the logical effort model to characterize the dissymmetry of gate delay and define the best P/N width ratio allowing a path minimum area implementation under delay constraint. This delay model explicitly represents the sensitivity of delay to gate structure and P/N width ratio. Application is given on a 0.18µm process on different logic path implementations.

I. INTRODUCTION

The relative merits of different cell libraries can be evaluated in terms of area/power necessary in achieving a particular delay for implementing a specific circuit. For that important effort has been devoted to supply high-performance standard cell libraries. Work has been devoted to define the optimal content of the library [START_REF] Scott | Improving cell libraries for synthesis[END_REF] as well as for determining the best selection of drives [START_REF] Coudert | Gate Sizing: a General Purpose Optimization Approach[END_REF][START_REF] Jiang | Interleaving buffer insertion and transistor sizing into a single optimization[END_REF]. A fluid cell approach is emerging [START_REF] Northrop | A semi-custom design flow in high performance microprocessor design[END_REF], in which a cell generation tool is used to create a discrete library with 10 to 25 drive strengths and 1 to 4 different P/N width transistor ratios. The question arise to know if it is possible to define an optimal value for the gate transistor ratio allowing to implement a CMOS logic circuit with the best delay/power trade-off. Recent work has been published [START_REF] Kung | Optimal width ratio selection for standard cell libraries[END_REF] on P/N transistor width selection, based on an asymmetric implementation of the gate rise and fall delays. Considering that, for an array of inverters, the minimum delay can be obtained using asymmetric edges, [START_REF] Kung | Optimal width ratio selection for standard cell libraries[END_REF] use a first order gate delay model to determine an optimal transistor width ratio for each gate. They minimize the average of the rising and falling delays to obtain an optimal solution in which they in over-size the Nand gates and undersize the NOR gates, with respect to that of an inverter. In fact on a logical path a separate consideration of the falling and rising edges must be given. In this case it can be shown that, considering only the critical edge, the fastest solution is obtained for an inverter implementation with balanced fall and rise delays. Moreover, for gates great attention must be given to the modeling of the transistor serial array current. On a non critical path the minimum gate area solution can be obtained with unbalanced edges, resulting from identical equal N and P transistor sizes. We want to demonstrate, here, that on a critical path performance constraint satisfaction may result in transistor over-sizing and extra power consuming, if no care is given to the balancing of the gate rise and fall delays.

In this paper we propose a method for determining the P/N transistor width ratio for implementing high performance library cells. The method is based on a delay model developed around the logical effort [START_REF] Sutherland | Logical Effort: Designing Fast CMOS Circuits[END_REF], but with an explicit consideration of the input ramp and Miller effects. This model is presented in part II. In part III, this model is used to determine the optimal value of the P/N transistor width ratio. Application to different logical paths is given in part IV, where we compare, at constant delay value, the area resulting from different sizing alternatives to that resulting from the proposed solution.

II. DELAY MODEL

The delay of a CMOS logic gate is load, gate size and input slew dependent. Following the value of the gate internal P/N width ratio, consideration of different rising and falling edges must be given. Considering the I/0 coupling [START_REF] Jeppson | Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay[END_REF], the input slope effect can be introduced in the propagation delay as:

2 ) ( ) 2 1 ( ) 1 ( 2 ) ( 2 ) 2 1 ( ) 1 ( 2 ) ( ) ( i C C i v i t C C i v i t outLH LTOT M NHL I TP LH i outHL LTOT M NLH I TN HL τ τ τ τ + + - = + + - = (1)
where for each element the delay is evaluated as the time interval between the input and output waveforms, evaluated at mid-supply voltage value. τ INHL,LH (τ out,HL,LH ) is the transition time of the signal applied to the input (generated at the output). It is evaluated as the time duration of a linear approximation of the output waveform of the controlling (switching) structure. Indexes (i), (i-1) refers to the location of the cell in the array. v TN,P represent the reduced values of the N(P) transistor threshold voltage with respect to the supply voltage V DD . C LTOT =C L +C M +C DIFF includes the coupling capacitance C M between the gate input and output nodes, the load C L at the output node and the diffusion capacitance C DIFF . As shown, for each edge, the delay expression is a linear combination of the output transition time of the controlling and the switching gate. Let us first consider a simple situation in which each switching gate is equivalent to a constant current generator. Following [START_REF] Maurine | Transition time modeling in deep submicron CMOS[END_REF] the gate output transition time value can be obtained from

IN LTOT LH outLH IN LTOT HL outHL C C DW R k k C C DW k ⋅ ⋅ ⋅ + ⋅ = ⋅ ⋅ + ⋅ = ) 1 ( ) 1 ( τ τ τ τ . ( 2
)
where τ is a unit delay characterizing the process.

The configuration ratio k = C P /C N , represents the P/N transistor width ratio. R is an equivalent mobility ratio between N and P transistors, that can directly be calibrated on an inverter. As defined in [START_REF] Maurine | Transition time modeling in deep submicron CMOS[END_REF], DW HL,LH is the current reduction factor in the gate series-connected transistor array, evaluated as the ratio of maximum current available in an inverter and a gate of identical size. C IN = C N +C P , represents the active gate input capacitance.

Considering that the input-to-output coupling capacitance and the parasitic capacitance are input gate size dependent, the effective loading factor can be defined as

IN L IN LTOT C C A C C + = . ( 3
)
Where A is gate input capacitance independent for a cell sizing at 2 or 3 times the minimum value allowed by the process. Eq.2 can then be identified to the logical effort model delay expression [

⋅ + ⋅ τ = τ (4)
The comparison of eq.2 and 4 gives an easy way to explicit the different parameters of the logical effort model for a general gate configuration. Here p is the gate input independent parasitic delay contribution, which is edge and configuration ratio dependent. h is the electrical effort defined by the ratio of output load to gate input capacitance and

LH LH HL HL DW k k 1 R g DW ) k 1 ( g ⋅ + ⋅ = ⋅ + = (5)
represent the detailed expression of the logical efforts. As shown, the value of this parameter is a direct indicator of the symmetry of the response and the efficiency of a logic structure. Note here that (4) identifies a transition time and, in general implementations, is not accurate enough to represent a switching delay as given in (1) and almost for evaluating the delay on a logic path.

III. P/N CONFIGURATION RATIO DETERMINATION

Considering the logic path delay, the contribution of each element is due to the loading term including I/O coupling effect (second term on the right hand part of (1)) and the input slope effect on the next stage. The total stage contribution is thus given by 2

) ( 2 1 )) ( ( 2 ) ( 2 1 )) ( ( i v C C i G t i v C C i G t outLH TN TOT M LH outHL TP TOT M HL τ τ         + + =         + + = (6)
We represent in Fig. 1 The intersect points A, B, C correspond to the value of k balancing the edges of the inverter, Nand and Nor gates, respectively. As shown, for each gate, the edge symmetry is obtained for a well defined value of k. Not fulfilling this condition increases the edge asymmetry. We can note that the delay average of both edges corresponds nearly to the value of delay obtained for the symmetrical case. This may explain the claim of [START_REF] Kung | Optimal width ratio selection for standard cell libraries[END_REF] that asymmetric rise and fall delay will result in a minimum delay implementation on an array of inverters. In fact in an array of gates the delay is given by the contribution of the successive edges. As given in (1) the delay of each gate is modified by the transition time of its preceding gate and in the same way modifies the delay (from its output transition time contribution) of its loading gates. In this case it is easy to understand from Fig. 1 that the symmetric implementation will always have the shortest delay or under delay constraint, will result in the smallest area/power implementation. Let us now determine the k value balancing the rise and fall delay gate contribution to a logic path. Developing eq.6 we obtain ( ) ( )

) ( . ) ( 2 1 )) ( ( ) ( . ) ( 2 1 )) ( ( i h g i p v C C i G t i h g i p v C C i G t LH LH TN LTOT N N LH HL HL TP LTOT P P HL + ⋅         + + = + ⋅         + + = α α (7)
where α P,N =C M /C P,N for falling or rising edges respectively, are the Miller coefficients [START_REF] Meyer | Semiconductor Device Modeling for CAD[END_REF] (a #0.5 or may be calibrated on the process). Balancing the delay contribution of the gate (i), imposes equal contribution of each edge. In the usual case, the expression of the configuration ratio value satisfying this condition is quite complicated and will be discussed later. To get a first idea, let us consider the asymptotic value of ( 7), corresponding to a large value C LTOT . In this case the I/O coupling contribution becomes negligible. Searching for the value of k that balances the falling and rising delays, [START_REF] Jeppson | Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay[END_REF] gives

TP TN HL LH asympt v 1 v 1 DW DW . R . k + + ⋅ = ( 8
)
where the value of R and DW HL,LH , characterize each structure [START_REF] Schindler 2 | Continuous representation of the performance of a CMOS library[END_REF]. In Table I we give the resulting values of k asympt , calculated from ( 8), for a library developed in a 0.18µm process (R =2.25, v TN =0.39 v TP =0.36 ). The DW values are directly calibrated on the process. The values given in this table are evaluated for the critical input. For Nand and Nor gates this has been shown to be the input controlling the transistor near the output node. For complex gates the most critical branch must be considered. In any way the edge symmetry will only be obtained for the critical switching condition, that must be optimized on a critical path.

Considering now the input-to-output coupling effect we obtain, from [START_REF] Jeppson | Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay[END_REF], the general solution as

v 3 ' F 1 v 1 v 3 ' F 1 k v 1 v 3 ' F 1 1 k 4 1 v 1 v 3 ' F 1 1 k 2 1 k . asymp + + ⋅ α + + + ⋅ α + +               + + ⋅ α + - + + + ⋅ α + - = (9) where F' 0 = A+C L /C IN = A + F 0 .
We can easily verified that k asymp is the asymptotic value of this expression, for large F' 0 value. As shown, in the general case and for small values of the loading factor, the P/N with ratio, balancing the rising and falling gate delays, is load dependent. This is a direct result of the input-to-output coupling effect.

The curves in Fig. 2 represent, for the simple gates of Table I, the simulated (Spice level 49 on a 0.18µm process) variation with the loading factor F 0 , of the k value balancing the rise and fall gate delays. As shown, for the interval of F 0 values ranging between 2 to 6, which corresponds to nearly optimal design conditions for performance, the P/N width ratio value balancing the delay edges, is constant for Nand and inverters, but is load dependent for Nor gates. In Table II we compare the values of k sym , calculated from ( 9), to the simulated values (Fig. 2). As shown the agreement between simulated and calculated values, obtained for different values of the loading factor, is quite satisfactory.

EXPERIMENTAL VALIDATION

We have determined in the preceding part the value k of the P/N width ratio for balancing the gate delay contribution on a logical path. As a result (Table II) it may appear that imposing a gate sizing for delay edge balancing results in a gate over-sizing. At first sight, an implementation with unbalanced edges, using k=1 or the value recommended in [START_REF] Kung | Optimal width ratio selection for standard cell libraries[END_REF], appears to be less area consuming. We demonstrate, in this part, that under a delay constraint, a logic path implemented with the k values given in Table II, necessitates less area than an unbalanced edge implementation. In Fig. 3 we represent the simulated (Hspice) variation of the delay of a logic path with respect to the sum of the gate transistor widths of each implementation, under the following protocol.

-We consider 3 P/N width ratio values, k=1, k from [START_REF] Kung | Optimal width ratio selection for standard cell libraries[END_REF], corresponding to a gate implementation with asymmetric fall and rise delays, and the k value from (9) for symmetrical edge implementation.

-The gate input size value is obtained, for each implementation, by imposing a constant value to the derivative of the total delay equation with respect to each input gate capacitance. Varying this constant from a negative value to zero allows to explore the design space and to reach the minimum delay achievable on the path [START_REF] Verle | Delay bound based CMOS gate sizing technique[END_REF].

The variations corresponding to k = 1 and k from [START_REF] Kung | Optimal width ratio selection for standard cell libraries[END_REF], correspond to the critical edge of the path delay (the delay imbalance is 23% and 37% respectively). The variation corresponding to k, from [START_REF] Meyer | Semiconductor Device Modeling for CAD[END_REF], represents the variation of the rise and fall path delays (5% of delay imbalance).

Fig. 1 .

 1 Fig.1. Variation of the gate delay (0.18µm) with the P/N width ratio value.

Fig. 2 :

 2 Fig.2: P/N width ratio sensitivity to the load.

Table I DW HL DW LH k asympt

 I

	INV	1	1	2.3
	ND2	1.55	1	1.5
	ND3	2.1	1	1.1
	ND4	2.6	1	.88
	NR2	1	1.9	4.4
	NR3	1	2.9	6.6
	NR4	1	3.6	8.3
	AOI21	1.55	1.9	2.9
	AOI31	2.1	1.9	2.1
	OAI21	1.55	1.9	2.9
	OAI31	1.55	2.9	4.4

  Fig.3. Logic path delay sensitivity to the gate P/N width ratio value (0.18µm process).

	Delay (ps)
	1100			Cref=5,65fF Cref=5,65fF Cref=5,65fF
	1 1 1	2 2 2	3 3 3	4 4 4	5 5 5	6 6 6	7 7 7	8 8 8	9 9 9
		4.Cref 4.Cref 4.Cref	6.Cref 6.Cref 6.Cref	8.Cref 8.Cref 8.Cref	6.Cref 6.Cref 6.Cref	6.Cref 6.Cref 6.Cref	4.Cref 4.Cref 4.Cref	6.Cref 6.Cref 6.Cref	4.Cref 4.Cref 4.Cref	5.Cref 5.Cref 5.Cref
	700		k=[5] k=[5]
					k=1 k=1	k=(9) k=(9)
	300									Σ Σ Σ Σ Wi (µm)
	70			570			1070

As shown, the gate implementation with balanced rise and fall delays results in the less area consuming implementation. For a weak delay constraint the area difference between the implementations is not very important. However for a more severe constraint, not only the recommended P/N width ratio value [START_REF] Meyer | Semiconductor Device Modeling for CAD[END_REF] results in a reduced area implementation, but may give the possibility to obtain a smaller delay value than allowed by the other methods.

In Table III we detail the results of the comparison of the different sizing alternatives (k from [START_REF] Kung | Optimal width ratio selection for standard cell libraries[END_REF], k=1, k from ( 9)) on benchmark circuits of various complexity. These values are just given for completeness. We compare the values of the minimum allowed delay, the sum of the transistor widths and the delay symmetry of the rising and falling edges of the different implementations. We also compare the area necessary to satisfy different delay constraints, defined with respect to the minimum delay obtained with the implementation obtained from [START_REF] Meyer | Semiconductor Device Modeling for CAD[END_REF]. (xxxx) corresponds to a non satisfaction of the delay constraint, ie a configuration where the delay constraint value is smaller than the minimum delay allowed by the corresponding implementation. The maximum delay value has been obtained by imposing the input capacitance of all the gates to be at the minimum allowed value, C REF = 5.65fF. The minimum delay value has been obtained in the same way than for Fig. 3, by cancelling the derivative of the total delay equation of each path with respect to each gate input capacitance. As shown, in all the considered situations, the P/N sizing method, we propose, allows a fastest and smaller area implementation. This is particularly verified for strong delay constraints. Considering the very low sizing sensitivity of the delay near the minimum we have to note here that the area corresponding to the minimum delay is far to be of practical use.

V. CONCLUSION

Using an extension of the logical effort model, we have developed in this paper a method for determining the best P/N width ratio of gates in a standard cell library. We have defined the explicit expression of the P/N width ratio, which is shown to be loading factor and structure dependent. Validations have been obtained, with respect to Spice simulations on a 0.18µm process, by comparing, on different benchmarks, simulated values of the delay using different P/N width ratio strategies. We have obtained clear evidence that imposing on a logic path equal rise and fall gate delay, results in a high performance implementation for the best area-delay trade-off.


P Maurine
email: pmaurine@lirmm.fr

N Azémard
email: azemard@lirmm.fr

D Auvergne
email: auvergne@lirmm.fr

RC on-chip interconnect Performance revisited

The delay of on-chip interconnect wiring is having an important influence on the timing performance of logic path. This is particularly true where drivers are connected through non-negligible length of wire. If the Elmore resistance-capacitance delay model remains popular due to its simple formulation, limitations have been shown in submicrometer domain due to the inability of a so simple model in capturing input slope effects. This paper presents an analytical expression for the transition time and the switching delay of an RC interconnect, including the line input and output drivers. Based on a previously developed model of inverter transition time and switching delay, we propose a model of the shielding capacitance effect on the input driver. We determine the transition time of the output driver and the switching delay of the complete structure for various sets of line parameters and different size of input drivers. We validate these analytical expressions with respect to electrical simulations, on a 0.13µm process, using the ELDO's transmission line model.

I. INTRODUCTION

Due to the increased integration density allowed by today ultra deep sub micrometer process the contribution of RC interconnect loading is increasing, mostly for inter block communications where drivers may be overloaded by long interconnect lines. As feature sizes are scaling down, increasing the circuit density, the gate delay is getting faster and the RC delay longer, due to higher value of the wire resistance and fringing capacitance. As a result the RC interconnect contribution delay increases with respect to the gate delay. Consequently, physical design optimization tools must be able to efficiently compute the delay across a huge number of wires and interconnect levels. Circuit simulators such as SPICE, ELDO or modelorder reduction techniques such as AWE [START_REF] Pillage | Asymptotic Waveform Evaluation for Timing Analysis[END_REF][START_REF] Dartu | Performance Computation for Precharacterized CMOS Gates with RC loads[END_REF] can be used to compute delays with a good accuracy, but are too expensive for evaluation at the optimization phase of the physical design. At this level, closed form delay equations or metrics for the delay are preferable. The most widely applied interconnect delay metric is the Elmore delay metric [START_REF] Elmore | The transient response of damped linear network with particular regard to wide band amplifier[END_REF] applied to a lumped interconnect model. The accuracy of this model is not sufficient for actual processes, it does not capture the effect on delay of the transition time of the edge controlling the interconnect line and ignores the gate reduction delay induced by the resistive shielding of downstream capacitance [START_REF] Quian | Modeling the effective capacitance for the RC interconnect of CLOS gates[END_REF].

Extending the Elmore's based work, several authors have proposed metrics based on higher circuit moments [START_REF] Celik | IC Interconnect analysis[END_REF]. Main concern in these works is to model the delay on the interconnect line, modeling the input driver as a voltage generator supplying the line through an equivalent resistance, with no consideration, except in [START_REF] Agarwal | Simple metrics for slew rate of RC circuits based on two circuit moments[END_REF], on the interconnect slew rate. The operating mode of an interconnect line is to propagate a signal from the output of a transmitter (line input driver) to the input of the receiver (line output driver). The important parameters, for the corresponding path, are the total delay value between the transmitter input and the receiver output, together with the transition time value of the signal at the receiver output. The accurate determination of the output transition time is of fundamental importance, it has a non-negligible contribution to the delay of the subsequent gate. These parameter values depend on the design of the drivers and the structure of the wiring. The primary contribution of this work is to present an analytical modeling of the interconnect delay and transition time, including the contribution of the input and output drivers. We focus on RC lines and establish the limiting conditions in using purely capacitive or RC representation of interconnect wire. The remainder of the paper is organized as the following. Section II provides background material on this study. Section III summarizes the delay and transition time models previously defined. Section IV presents the equivalent line model, considered in this evaluation, with emphasis on the modeling of the resistance shielding effect. Experimental results, and validations are given in Section V, before to conclude in Section VI.

II. BACKGROUND

Addressing the delay modeling in interconnect line implies to consider the propagation of signals from the input of the driver supplying the line, to the output of the driver at the termination of the line. This is illustrated in Fig. 1, where the different performance terms are defined. The fundamental problem is then to accurately determine:

-the switching delay, T OUT -T IN , (Fig1) between the input and the termination driver, -the output transition time value, T OUTDRIVE2 at the termination driver.

-the loading and propagation effect produced by the interconnection line.

T OUT -T IN

Concerning the input driver, its timing performance depends on its size and the equivalent load seen from its output. This completely determines the transition time of the signal edge supplied to the line. The problem is then to calculate the time spent by the line driver output edge to propagate across the line, and the evolution of this edge transition time. As shown in Table I, he value of the line output transition time contributes in a nonnegligible part to the switching delay and transition time (T OUTDRIVER2 ) of the terminal driver. The first parameter (T OUT -T IN ), completely characterizes the performance of the line while the second one (T OUTDRIVE2 ) gives the sensitivity of the output driver to the line performance, which may produces great variations in the output driver timing. This sensitivity is illustrated in Table 1 that shows examples of the value of the different line performance parameters simulated on the general structure illustrated in Fig. 1. The simulations are obtained using the ELDO's transmission line model (LDTL) [START_REF] Anacad Ees | Eldo User's Manual[END_REF], for a 0.13µm process. The line parameters are R LINE =115 /mm, C LINE =472fF/mm, they correspond to a higher level of metal used for long-range interconnection. The output driver is a minimum size driver (C IN = 0.82 fF), loaded by 5fF. The input driver is controlled by a short duration input ramp, three different sizes of input drivers are considered. We have limited the length line to 5mm that is longer, in high performance designs, than the maximum length allowed between repeaters.

III. INVERTER MODEL

The modeling of the transition time and switching delay of inverters (gates) has been the subject of numerous works. A realistic delay model must be input slope dependent and distinguish between falling and rising signals [8]. We use a model developed for deep sub-micrometer process [9], in which the switching inverter (gate) is considered as a current generator supplying the output load. The elementary switching process of a CMOS structure can then be resumed to an exchange of charge between the structure and its output loading capacitance. The output transition time (defining the input transition time of the following cell) can then be directly obtained from the modeling of the charging (discharging) current that flows during the switching process of the structure and from the amount of charge (C LTOT .V DD ) to be exchanged with the output node as T xx specify the 50% delay and T OUTxx the output transition time, determined on the output edge between 40 and 60% of its variation and extrapolated on the 100% range. The different terms are defined in Fig. 1. As shown these parameters are strongly dependent on the length line and the size of the input driver. Moreover the transition time of the input driver (T OUTDRIVER1 ) is far to be proportional to the line length as it could be expected. This is an evidence of the load shielding effect. The transition time value of the output driver (T OUTDRIVER2 ) exhibits a great sensitivity to the transition time at the output of the line (T OUTLINE ). As shown despite of its constant loading the DRIVER2 transition time value can be multiplied by 4 in the considered range of line length. This gives evidence of the necessity to accurately determine the total switching delay (T OUT -T IN ) and the output driver transition time that are the fundamental parameters to be determined for any timing evaluation or optimization on a path involving the RC interconnect.

PMax DD LTOT OUTLH NMax DD LTOT OUTHL I V C T I V C T (1)
where V DD is the supply voltage value and C LTOT the total output load, including the parasitic and input-to-output coupling capacitance [8]. In this expression the output voltage variation is supposed linear and the driving element considered as a current generator.

The key point here is to determine the realistic value of this current. Two controlling conditions are considered. The fast input control range, in which the input signal reaches its maximum value before the output begins to vary, in this case the switching current exhibits a constant and maximum value. The transition time expression for a fast input control condition is easily obtained as: For that different sub-models must be clearly established:

IN LTOT Fast OUTLH IN LTOT Fast OUTHL C C R k ) k 1 ( T C C ) k 1 ( T (2)
-the switching delay and transition time of an inverter (gate) and its sensitivity to the input controlling ramp, If the time constant of the line is smaller than some value to be determined, let us say the driver transition time, it is easy to understand that the driver equivalent output load is only constituted by the total line capacitance. In that case an accurate 50% delay prediction can be obtained as:

where is a unit delay characterizing the process, k=W P /W N the inverter configuration ratio, R is the speed ratio between electron and hole, C LTOT the purely capacitive load and C IN the inverter input capacitance.

In the slow input range the input and output voltages vary simultaneously. The duration of the input ramp applied to the N and P transistors decreases the current value available at the output. This is the main input slope effect on the transition time. Considering the symmetry property of the current wave shape, this new value of the current has been shown input transition time dependent resulting in [9] T OUT -T IN = T TOTLINE + T DRIVER2

(5) where T TOTLINE is the 50% propagation delay between the input driver and the output of the line. The input driver propagation delay is given by (4) and the line propagation delay can be approximated by R Line .C Line /2, [11]. The delay across the line structure is the sum of the driver and the interconnect delay. Moreover, the transition time value at the input and output of the line are identical. This is illustrated in Fig. 2 that represents the simulated wave shapes at the input (Driver1 output) and output of a 0.5mm long line in the configuration given in Fig. 1.

INLH Fast OUTHL DD TN DD Slow OUTHL T V V V T ( 3
)
with an equivalent expression for a rising edge. V TN,P represents the threshold voltage value of the N,P transistors.

In a realistic switching delay evaluation, consideration must be given to the finite value of the input controlling edge. As developed in [8] we introduce the input slope effect and the related input-to-output coupling in the model as: In this configuration T OUTDRIVER1 = T OUTLINE = 50 ps. As shown the wave shapes are parallel, the line input driver see the total line capacitance and the driver and line output transition times can easily be deduced from the simple capacitance model [START_REF] Dartu | Performance Computation for Precharacterized CMOS Gates with RC loads[END_REF].

1) (i T 2 v (i) T LH INLH, P TN, LH HL, 2 (i) T ) C C C 2 (1 LH HL, OUT L M M (4)
Note that the value of each parameter strongly depends on the transition time value of the signal edge applied to the input of the device under consideration.

If the resistance of the line has a sufficiently important value such as the line propagation delay becomes greater than the output transition time of the input driver (DRIVER1), a shielding effect can be observed. Its equivalent loading capacitance becomes smaller than the total line capacitance. This can be observed in Fig. 3 that represents, for a 1.5mm long line, the evolution of the output wave shapes given in Fig. 2. In this case T OUTDRIVER1 = 185 ps, T OUTLINE = 1352 ps. As shown the wave shapes are no more parallel, the driver output edge is much faster than the line output one. Moreover the output transition time of the input driver is reduced from 625ps (12.5 times the value for the 0.5mm long line) to 185 ps, giving evidence of the shielding effect introduced by the line resistance.

IV. LINE PERFORMANCE MODEL

The time and space variation of the voltage on a wire described as a RC distributed line is governed by the well-known diffusion equation that has no closed form solution [10].

An equivalent lumped RC model can be used with a satisfactory accuracy if the equivalent capacitive and resistive components are clearly determined. As observed in Table I, it has been shown in [START_REF] Celik | IC Interconnect analysis[END_REF] that when the driver equivalent resistance value becomes comparable or smaller than the line resistance, part of the load capacitance is shielded from the line driver, resulting in large discrepancies in evaluating its output transition time and switching delay. For that let us consider a line modeled by distributed RC elements. This result can be understood, considering that the current supplied by the input driver firstly load an equivalent capacitance (part of the line capacitance) of which loading voltage supplies the rest of the line. We get the superimposition of two mechanisms: -a constant current loading of the capacitance C LINE (1-x),

-diffusion of this loading on the rest of the line R LINE .C LINE .x. Where x appears as a shielding parameter. The determination of this parameter is of prime importance. For that us consider the limiting conditions defined with respect to the ratio of the driver transition time to the line output transition time. When this ratio is greater than unity the input driver see the complete line capacitance. Whereas if this ratio is smaller than unity ,the input driver see part of the line capacitance. Following these considerations the output transition time of the input driver and of the line can be obtained from /mm, C LINE =472fF/mm. The output driver is kept at minimum size with a 5fF load. Fig. 4 and5 illustrates the validation obtained using (6,7) to model the output transition time variation at the input line driver and at the output of the line, including the resistance shielding effect on the line. As shown the agreement between calculated and simulated values is very good, we observe less than 5% of discrepancy in modeling the line output transition time. The divergence obtained in modeling the output transition time of the input driver A is the consequence of its heavy output loading (C L /C IN =216) for which the driver can not be considered as a current generator on the full range of line length. However this condition is far away the normal design conditions. Note that eq.6,7, although much simpler than that proposed in [START_REF] Quian | Modeling the effective capacitance for the RC interconnect of CLOS gates[END_REF], allows to estimate the line output transition time with a satisfactory accuracy. As shown in Table I, the influence of the shielding parameter is line length and input driver dependent. It induces a 30% load reduction when T OUTFASTDRIVER1 /R LINE. C LINE = 1 and increases quickly when this ratio value decreases. As a result this ratio of transition time value can be used as a robust metric for considering shielding effects.

V. EXPERIMENTAL RESULTS

Using (6,7) the total delay on the line and the total delay between the input of DRIVER1 and the output of DRIVER2 can easily be obtained as For illustration, in

Fig. 1 .

 1 Fig.1. Identification of the different delay terms to be considered.

  ,P are the reduced values (V TN,P /V DD ) of the threshold voltage of the N,P transistors. T INHL,LH is the duration time of the input signal. C M is the coupling capacitance between the input and output nodes and C L the output loading capacitance. Indexes (i), (i-1) specify the switching and the controlling gates, respectively.

Fig. 2 .

 2 Fig.2. Simulated output wave shapes at the DRIVER1 output (Drive C) and the line termination for a 0.5mm line in the configuration given in Fig.1.

Fig. 3 .

 3 Fig.3. Simulated output wave shapes at the DRIVER1 output (Drive C) and the line termination for a 1.5mm line in the configuration given in Fig.1.

  shielding model has been obtained by comparing the transition time value simulated with the ELDO's transmission line model and calculated from eq.6 and 7. As specified in Table I we use three different sizes of input driver (DRIVER1 A,B,C), a minimum size output driver and two line parameters: R LINE =232 /mm, C LINE =352 fF/mm and R LINE =115

Fig. 4 .Fig. 5 .

 45 Fig.4. Simulated (full line) and calculated (dashed line) values of the input driver transition time for the configuration specified in Table I, with different size of input drivers (R LINE =115 /mm, C LINE =472fF/mm).

Fig. 6 .Fig. 7 .Fig. 8 .

 678 Fig.[START_REF] Agarwal | Simple metrics for slew rate of RC circuits based on two circuit moments[END_REF]. Simulated (full line) and calculated (dashed line) values of the total line propagation delay for the configuration specified in TableI, with different size of input drivers (R LINE =115 /mm, C LINE =472fF/mm).

  Table 2 we directly compare the calculated and simulated values of the total delay and the output driver transition time for the second set of line parameters we have considered: R LINE =232 /mm, C LINE =352 fF/mm. the line on the transition time and the delay of the line input and output drivers. Load shielding of the input inverter has been captured with respect to the input drive-line transition time ratio, which can be used as an efficient metric for considering shielding effects. Line output transition time effect on the transition time and delay of the output driver has been clearly defined. Validations with respect to transmission line simulations have demonstrated the potential application of this model in estimating the RC interconnect impact on circuit performance. Applications to be considered in using this analytical model are in driver selection and in line repeater insertion.[8] K. O. Jeppson, "Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay", IEEE J. Solid State Circuits, vol.29, pp.646-654, 1994.[9] xxxx for anonymous review IEEE trans. on Computer Aided Design, 2002.[10] Y. I. Ismail, E. G. Friedman, "On-chip inductance in high speed integrated circuits" Kluwer Acad. Publishers, 2001.[11] J. M. Rabaey, "Digital Integrated Circuits, A Design Perspective" Prentice Hall, Inc., New Jersey, 1999.

								As shown the agreement between calculated and
								simulated values is excellent, the maximum discrepancy
								is smaller than 5% on the full-considered range. Note
	DRIVER1 A C IN = 11fF DRIVER1 B C IN = 28fF	Line lgth mm 0.1 1 3 5 0.1 1 3	T OUTDRIVER1 ps 63 591 1850 3126 33 239 670	here the effect of the line output transition time on the output driver. Smaller is the transmitter (DRIVER1) greater is the value of the line output transition time (columns 3,4) and that of the output driver (columns 5,6). This is directly reflected in the value of the total delay (columns 7,8). This justifies the need for an accurate modeling of the line output transition time. VI. CONCLUSION We have proposed a complete modeling of the resistance-capacitance (RC) effect on the delay of an interconnect link between two inverters. Considering a previously developed deep sub-micrometer model, in which the inverter (gate) is considered as a current generator, we have obtained an analytical expression allowing to estimate the T OUTLIN E ps T TOTLINE ps T OUTDRIVER2 ps T OUT -T IN ps 63 33 125 102 592 327 226 505 1900 1175 400 1462 3243 2024 508 2383 33 16 123 82 241 148 141 265 loading effect of Table I 879 518 261 727
				5		795		1700	1025	398	1295
	DRIVER1 C	0.1		16		16	12	126	75
	C IN = 56fF			1		115		125	71	143	167
				3		185		562	273	240	455
				5		185		1352	660	358	904
						Table II
	Line lgth	T OUTLINE	T OUTLINE	T OUTDRIVER2	T OUTDRIVER2	T OUT -T IN	T OUT -T IN
		mm	Sim.(ps)	Calc. (ps)	Sim.(ps)	Calc. (ps)	Sim.(ps)	Calc.(ps)
	DRIVER1 A	0.1	49		52		124	124	99	102
	C IN = 11fF	1		452	450		204	193	375	377
		3		1624	1466		380	348	1057	1008
		5		3015	2984		525	496	1911	1846
	DRIVER1 B	0.1	23		27		123	123	79	86
	C IN = 28fF	1		189	192		158	126	214	189
		3		870	867		300	267	622	650
		5		2197	2140		449	420	1343	1388
	DRIVER1 C	0.1	13


Ahmed A Rekik

Florence Azaïs

Frédérick Mailly

Pascal Nouet

Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy

Keywords: MEMS, convective accelerometer, test, calibration, design-for-manufacturing I. heater detectors sensing direction

and research institutions in France or abroad, or from public or private research centers.

Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy

INTRODUCTION

MEMS convective accelerometers are an interesting alternative to comb-drive accelerometers even if current market is largely devoted to the latter [START_REF] Xie | 05 of Comprehensive Microsystems[END_REF]. Their interest is twofold. On the one side, they can be fabricated in a CMOS technology with a single self-aligned additional etching [START_REF] Chaehoi | Experimental and finite-element study of convective accelerometer on CMOS[END_REF]. This postprocess called Front-Side Bulk Micromachining is one of the most popular in MEMS. On the other side, such accelerometers exhibit large dynamic range and huge safety range (they can support several thousands of g's without any damage).

Apart from the previous two advantages, we intend to demonstrate in this paper that convective accelerometers can be associated with design for manufacturing approaches to make them more appealing. Design for Manufacturability (DfM) generally includes Design for Test, Calibration, Reliability… often called DfX [START_REF] Richardson | Design for Manufacture Challenges in MEMS enabled Micro & Nano Systems[END_REF]. In our case, convective accelerometers already demonstrated their reliability so it is not necessary to work on their design to improve reliability. In some previous studies, we proposed techniques for test and calibration of such accelerometers using electrical-only stimuli [START_REF] Rekik | Investigations on Electrical-only Test Setup for MEMS Convective Accelerometer[END_REF][START_REF] Rekik | An electrical test method for MEMS convective accelerometers: development and evaluation[END_REF][START_REF] Rekik | A MEMS convective accelerometer equipped with onchip facilities for sensitivity electrical calibration[END_REF]. This point is really important as the cost of these test procedures may drastically impact the final cost in the case of low-end products such as those used for consumer applications. In this paper, we propose to extend the previously proposed go/no-go scheme to a complete calibration and binning procedure.

The paper is organized as follow. In section II, the Device Under Test (DUT) is introduced together with a parametric fault model used to represent process scattering effects. In section III, electrical-only calibration procedure is described to introduce, in section IV, the adaptive electrical calibration strategy that allows binning on device sensitivity and power consumption. Finally, section V reports experimental results before conclusion.

II. DEVICE UNDER TEST OVERVIEW

A. Device description

The device under test is a convective accelerometer obtained by Front-Side Bulk Micromachining (FSBM) of a CMOS die. As illustrated in figure 1, three thin bridges composed of the CMOS process back-end layers (oxide, polysilicon, aluminum, and nitride) are suspended over a silicon etched cavity and polysilicon is used to realize temperature-sensitive resistors for heat generation (R H ) and temperature sensing (R D1 , R D2 ). Sensor operating principle relies on heat transfer and more precisely on free convection of a hot bubble in a cavity. The hot bubble is created within the cavity by dissipating power in the heating resistor. In absence of acceleration, the temperature profiles around the heater are symmetrical and both detectors sense the same temperature. Acceleration applied along the sensitive axis causes disturbance of temperature profiles due to convection and a differential temperature appears between both detectors. This difference of temperature is then converted into a differential variation of resistance thanks to the Temperature Coefficient of Resistance (TCR) of polysilicon. Finally, a differential voltage is obtained as temperature sensors are arranged in a Wheatstone bridge with two reference resistors (R REF1 , R REF2 ) located on the substrate. The so-obtained differential output voltage is directly proportional to applied acceleration and device sensitivity. For more details on sensor modeling, manufacturing and characterization please refer to previous works from some of the authors [START_REF] Chaehoi | Experimental and finite-element study of convective accelerometer on CMOS[END_REF][START_REF] Leman | Modeling and system-level simulation of a CMOS convective accelerometer[END_REF].

B. Parametric fault model

The behavioral model presented in [START_REF] Rekik | Modeling the influence of etching defects on the sensitivity of MEMS convective accelerometers[END_REF] is used in this work to simulate parametric faults due to process scattering. More precisely, all electrical and geometrical model parameters will be altered to represent the effect of process scattering.

In particular, we consider a Gaussian distribution with 3=20% for electrical resistances, i.e. heater resistance R H0 , detectors' resistances R Di0 , and reference resistances R REFi . This distribution corresponds to typical uncertainties given by the foundry and is a global variation, i.e. it affects all resistances in the same amount. In addition, we consider a mismatch error with 3=2% for detectors' resistances R Di0 and reference resistances R REFi . We also consider a Gaussian distribution with 3=10% for polysilicon temperature coefficient of resistance TCR as this parameter is quite sensitive to doping fluctuations.

Regarding geometrical parameters, we consider a Gaussian distribution with 3=2µm for the distance r 2 between the heater and the cavity boundary. Indeed, lateral dimensions are parameters that are rather well controlled during the manufacturing process and exhibit a low dispersion. In contrast, the cavity depth h 1 is a parameter that it is very sensitive to the etching post-process (etching solution composition, etching time and etching solution movements) and therefore very difficult to control. As we have no information from foundry, we consider a random uniform variation of cavity depth h 1 between 50µm and 490µm.

III. PREVIOUS WORK ON ELECTRICAL CALIBRATION

In a previous work [START_REF] Rekik | A MEMS convective accelerometer equipped with onchip facilities for sensitivity electrical calibration[END_REF], we developed an alternative electrical scheme that permits to calibrate the sensor sensitivity without the need of applying a calibrated acceleration. The basic principle consists in adjusting the power dissipated in the heating element so that the relative deviation of Wheatstone bridge equivalent impedance is set to a given target value corresponding to sensitivity nominal specification. A simple on-chip circuitry based on a pulse-modulated generator is integrated within the circuit to permit the adjustment of the power level through digital programming. As illustrated in figure 2, the generator is composed of an N-bit register to store the programming word, an N-bit maximal-length LFSR and an N-bit comparator. The comparator output controls two switches that bias the heating element to either V dd or ground. As a result, the average power level dissipated in the heating element P H is directly proportional to the programming word stored in the N-bit register. The fundamentals of the calibration technique are recalled in this section. The key parameter of the calibration technique is the relative deviation of Wheatstone bridge impedance due to power dissipation in the heating element. The evaluation of this parameter only necessitates two simple static measurements of the current flowing through the Wheatstone bridge: (i) the current I W0 when no power is dissipated in the heating element (Programming_Word = "00000") and (ii) the current I W when a power P H is dissipated in the heating element (Programming_Word  "00000"). The corresponding relative deviation of Wheatstone bridge impedance R eq /R eq0 is then computed with the following equation:

 0 0 W W W eq0 eq I I I R R        
The main interest of this parameter is that it presents a good correlation with device sensitivity. It can therefore be used to evaluate the device sensitivity without the need of applying a calibrated acceleration. As an illustration, figure 3 plots the relative deviation of Wheatstone bridge impedance for nominal heater power level P H =50% versus the device sensitivity to 1g acceleration (obtained from Monte-Carlo simulations). Then to act on the device sensitivity, the chosen approach was to adapt the power dissipated in the heating element. Indeed as depicted in figure 4, it exists a monotonic relationship between device sensitivity (S) and power dissipated in the heater (P H ), and therefore a possibility to perform calibration by playing on this electrical parameter. Such a solution is exploited in [START_REF] Zhao | Thermal convection accelerometer with closed-loop heater control[END_REF] to compensate for temperature variations in the silicon substrate and/or the local environment. In our case, the objective is to adjust the power dissipated in the heating element to compensate for process variation device susceptibility. The proposed calibration strategy consists in adjusting the power dissipated in the heating element depending on the measurement of the relative deviation of Wheatstone bridge

R D1 R D2 R H R REF1 R REF2 V dd N-bit register N-bit ML-LFSR Programming Word Clock N-bit comparator V dd

Pulse-Modulated Generator

impedance since this parameter presents good correlation with device sensitivity. More precisely, the idea is to adjust the heater power level so that the relative deviation of Wheatstone bridge impedance is set to a given target value R eq /R eq0 | target corresponding to the nominal device sensitivity S spec . The problem is that it is not possible to relate the relative deviation of Wheatstone bridge impedance and the heater power level with a unique relationship, but each device has a different curve which is not known a priori (see figure 5). In other words to reach the same target value R eq /R eq0 | target for each individual device k, a different setting on the heater power P H k has to be realized. To cope with this issue, we developed an iterative procedure that permits to search, for each individual device k, the appropriate power level P H k . More precisely at each iteration, the device is biased with the power level P H (i) determined in the previous iteration and the current I W (i) flowing through the Wheatstone bridge is measured in order to determine the corresponding relative deviation of Wheatstone bridge impedance R eq /R eq0 (i). Taking into account the target value R eq /R eq0 | target ., the following value of the heater power level P H k (i+1) is then determined from a linear interpolation/extrapolation between the two preceding measurements with:

) i ( / ) 1 i ( / ) i ( / ) 1 i ( ) 1 i ( / ) i ( / ) 1 i ( / ) i ( / ) 1 i ( ) i ( ) 1 i ( k eq0 eq k eq0 eq k eq0 eq k H k eq0 eq k H target eq0 eq k eq0 eq k eq0 eq k H k H k H R R R R R R P R R P R R R R R R P P P                        
The electrical calibration flow is summarized in figure 6. The initial step of the procedure consists measuring the current flowing through the Wheatstone bridge at ambient temperature (P H (0)=0) and under nominal power level condition (P H (1)=50%). From this, the relative deviation of Wheatstone bridge equivalent impedance R eq /R eq0 (1) can be computed and the iterative search begins. We actually determined that two iterations are sufficient to determined the appropriate heater power level, i.e. P H (3) is the final heater power level used for each device. In addition, an intermediate constraint was introduced at the end of the first iteration that reject devices for which the initial relative deviation of Wheatstone bridge equivalent impedance R eq /R eq0 (1) is below a predefined limit R eq /R eq0 | limit . Indeed these devices correspond to devices with a very low sensitivity; taking into account that the maximum power level is limited to (2 N -1)/2 N *P H max , the possible increase in the power dissipated in the heater is not sufficient for these devices to compensate their poor sensitivity.

IV. ADAPTIVE ELECTRICAL CALIBRATION STRATEGY

An interesting feature of the calibration method is that it permits to adjust devices at different sensitivity values depending on the target value chosen for the relative deviation of Wheatstone bridge impedance. This flexibility can be exploited in the general context of design-formanufacturability. In this section, we first present an adaptive version of the calibration procedure with multiple sensitivity targets in order to improve production yield. We then introduce a refinement of the procedure that permits to perform product binning taking into account both sensitivity and power consumption specifications.

A. Binning on device sensitivity

The objective is to exploit the flexibility offered by the calibration method in order to improve the production yield. Indeed a number of devices are rejected by the calibration procedure presented in the previous section because they present a poor initial sensitivity under nominal heater power level. The idea is, instead of rejecting these devices, to calibrate them to a lower sensitivity specification.

To illustrate this strategy, let us consider 2 different values of sensitivity specification S spec1 and S spec2 (with S spec1  S spec2 ), corresponding to 2 different target values R eq /R eq0 | target1 and R eq /R eq0 | target2 . The related adaptive calibration flow is depicted in figure 7, which bins devices in three categories:

-Category 1: devices that exhibits an initial relative deviation of Wheatstone bridge impedance R eq /R eq0 (1) higher than R eq /R eq0 | limit1 . These devices

R



go to the calibration procedure using R eq /R eq0 | target1 .

Their sensitivities would be centered on S spec1 ; they correspond to accepted devices. -Category 2: devices that exhibits an initial relative deviation of Wheatstone bridge impedance R eq /R eq0 (1) lower than R eq /R eq0 | limit1 but higher than R eq /R eq0 | limit2 . These devices go to the calibration procedure using R eq /R eq0 | target2 ; their sensitivities would be centered on S spec2 ; they correspond to accepted devices. -Category 3: devices that exhibits an initial relative deviation of Wheatstone bridge impedance R eq /R eq0 (1) lower than R eq /R eq0 | limit2 . These devices are rejected by the procedure.

Obviously, the number of categories can be freely chosen depending on the application. The test limit values have then to be adapted for each category.

B. Binning on both device sensitivity and power consumption

Depending on the application, power consumption may be another important parameter in addition to sensitivity. Since the proposed calibration procedure is based on the adjustment of the heater power level, it is more than probable that for some circuits (especially circuits with very poor initial sensitivity), power consumption significantly increases after calibration.

In this context, a refinement of the calibration procedure consists in including an extra criterion on power consumption in addition to sensitivity calibration, as illustrated in the flow diagram of figure 8. In this procedure, each device is first directed for calibration towards the highest possible sensitivity specification according the measurement of initial relative deviation of Wheatstone bridge impedance, and then possibly redirected to lower sensitivity specification if power consumption constraints are not satisfied (we assume that most of the power consumption comes from the power dissipated in the heating element). A number of simulations have been carried in order to evaluate the performances of the proposed adaptive calibration strategy. A population of 1,000 devices generated through Monte-Carlo simulations has been considered using the parametric fault model described in section II.

First, we have applied the original calibration procedure with a single sensitivity target. The objective was to calibrate devices to a nominal sensitivity S spec = 100µV/g, which corresponds to a target value R eq /R eq0 | target = 3.657% (determined from a simulation with all parameters at typical value). Results are illustrated in figure 9, which gives the distribution of device sensitivity before and after calibration. Initially, device sensitivity exhibits a rather large dispersion and only 541 out of 1,000 devices are within 10% nominal sensitivity specification. Applying the calibration procedure, 67 devices are actually rejected (with R eq /R eq0 | limit = 1.87%), but the dispersion on device sensitivity is significantly reduced compute R eq /R eq0 (  and the distribution is well centered on the desired specification. This calibration procedure therefore permits to increase the production yield from 54.1% to 93.3%. Then, we have applied the adaptive calibration strategy considering multiple sensitivity targets. In this experiment, we consider three different values of sensitivity specification S spec1 = 100µV/g, S spec2 = 75µV/g and S spec3 = 50µV/g, corresponding to three different target values R eq /R eq0 | target1 = 3.657%, R eq /R eq0 | target2 = 2.937% and R eq /R eq0 | target3 = 2.208%. Devices are therefore binned in four categories:

-Category 1: devices that exhibits an initial relative deviation of Wheatstone bridge impedance ΔR eq /R eq0 (1) higher than R eq /R eq0 | limit1 = 1.87%. These devices go to the calibration procedure using R eq /R eq0 | target1 . Their sensitivities would be centered on S spec1 ; they correspond to accepted devices. -Category 2: devices that exhibits an initial relative deviation of Wheatstone bridge impedance ΔR eq /R eq0 (1) lower than R eq /R eq0 | limit1 = 1.87% but higher than R eq /R eq0 | limit2 = 1.52%. These devices go to the calibration procedure using R eq /R eq0 | target2 ; their sensitivities would be centered on S spec2 ; they correspond to accepted devices. -Category 3: devices that exhibits an initial relative deviation of Wheatstone bridge impedance ΔR eq /R eq0 (1) lower than R eq /R eq0 | limit2 = 1.52% but higher than R eq /R eq0 | limit3 = 1.11%. These devices go to the calibration procedure using R eq /R eq0 | target3 ; their sensitivities would be centered on S spec3 ; they correspond to accepted devices. -Category 4: devices that exhibits an initial relative deviation of Wheatstone bridge impedance ΔR eq /R eq0 (1) lower than R eq /R eq0 | limit3 = 1.11%. These devices are rejected by the procedure.

On this example, the test limit values have been set so that they favor the categories of highest sensitivity specification. Results are illustrated in figure 10, which gives the distribution of device sensitivity after application of the calibration procedure. As expected, the sensitivity histogram reveals three non-overlapping distributions centered on the targeted sensitivities. In this case, only 5 devices are rejected by the calibration procedure, which corresponds to a theoretical production yield of 99.5%. The effectiveness of the adaptive calibration strategy to improve production yield is therefore clearly demonstrated. However, it should be noted that the procedure is not able to guarantee a calibration success rate of 100%. In this experiment, there are 15 accepted devices for which sensitivity is close to the specification, but not exactly within 10% range. This corresponds to a test escape of 1.5%. The actual production yield is therefore 98% after calibration. Because the calibration procedure is based on the adjustment of the heater power level, the device power consumption is significantly affected. To illustrate this point, figure 11 reports the heating power distribution before and after calibration. Before calibration, all devices have their heating power in a range of ±25% of the typical heating power value (P Htyp =12.2mW); after calibration, only 80.2% of calibrated devices have their heating power in a range of P Htyp +25%. Consequently, if power consumption is also a specification to be satisfied, it is clear that some calibrated devices should be rejected, therefore reducing production yield. On this example, rejecting all devices with a heating power that exceeds P Htyp +25% results in a global production yield of 80.2%. The objective of the adaptive calibration procedure introduced in section IV.B is to optimize product binning when specifications on both device sensitivity and power consumption have to be satisfied. In this case, an additional constraint on the heating power P H | limit is inserted in the calibration procedure. Figure 12 compares the distribution of device sensitivity and heating power achieved after calibration, without and with this additional criterion inserted in the flow (P H | limit = P Htyp ±25% in this experiment). With the first approach, 198 devices are rejected whereas only 70 devices are rejected with the second approach. The production yield therefore improves from 80.2% to 93%. Moreover, an interesting consequence of the insertion of the additional constraint on heating power is that the calibration success rate is increased. In this experiment, there is only one accepted device for which sensitivity is close to the specification, but not exactly within 10% range. More generally to analyze the performance of the proposed adaptive calibration strategy, we have compared the repartition of devices in each category (considering both device sensitivity and power consumption) before and after application of the calibration procedure. Results are summarized in figure 13, for different values of the constraint on the heating power P H | limit . In all cases, the proposed adaptive calibration strategy permits to significantly improve the production yield. When considering only sensitivity, production yield theoretically increases from 65.4% to 99.5%. However as already mentioned, there are some test escapes that lead to a slightly lower production yield at 98%. Interestingly when considering both sensitivity and power consumption, the number of test escapes falls to 1 or 2, resulting in an actual production yield extremely close to the theoretical one. Besides, it can be noticed that the proposed strategy is able to efficiently manage different constraints on power consumption: even with a very tight constraint at P Htyp +10%; the actual production yield after calibration is higher than 90% while only about 50% of the devices are initially within specification.

VI. CONCLUSIONS

In the context of design-for-manufacturing of MEMS convective accelerometers, we have proposed an adaptive calibration strategy that permits product binning based on both sensitivity and power consumption performances. The idea is to adjust devices at different sensitivity values using different target values for the relative deviation of Wheatstone bridge impedance. The target value applied for each device depends on both its initial sensitivity and power consumption constraint. Results have shown the efficiency of the technique that permits to improve initial production yield ranging from 50% to 65% up to production yield ranging from 91% to 98% depending on power consumption constraint. Moreover it is a low-cost procedure since it requires only electrical measurements.

Figure 1 .

 1 Figure 1. MEMS convective accelerometer

Figure 2 .

 2 Figure 2. Schematic view of the device equipped with on-chip calibration facilities

Figure 3 .

 3 Figure 3. Relative deviation of Wheatstone bridge equivalent impedance (R eq /R eq0 ) vs. device sensitivity (S)

Figure 4 .

 4 Figure 4. Device sensitivity (S) vs. heater power (P H )

Figure 5 .

 5 Figure 5. Relative deviation of Wheatstone bridge equivalent impedance (R eq /R eq0 ) vs. heater power level (P H ) for three different devices

Figure 6 .

 6 Figure 6. Electrical calibration flow

Figure 7 .

 7 Figure 7. Adaptive procedure for product binning with focus on device sensitivity

Figure 8 .

 8 Figure 8. Adaptive procedure for product binning with focus on both device sensitivity and power consumption V. RESULTS

Figure 9 .

 9 Figure 9. Distribution of device sensitivity before (a) and after (b) calibration with single sensitivity target.

Figure 10 .

 10 Figure 10. Distribution of device sensitivity after calibration with multiple sensitivity target.

Figure 11 .

 11 Figure 11. Distribution of heating power before (a) and after (b) calibration.

  Figure 12. Distribution of device sensitivity and heating power after adaptive calibration.

Figure 13 .

 13 Figure 13. Distribution of device sensitivity after adaptive calibration for different values of P H | limit .

eq /R eq0 | target

					device k
			apply P H (0)=0 and
			measure I W (0)
			apply P H (1)=50%
			and measure I W (1)
			compute R eq /R eq0 (1)
		device i device j	eq0 eq ΔR R	) 1 ( yes 	eq0 eq ΔR R	limit	no	device rejected
			compute P H (2)
		device k	apply P H (2) and
			measure I W (2)
			compute P H (3)
	P H i P H j	P H k	apply P H (3)
					 device calibrated
					to S spec

Quito, Ecuador, April 11-13, 2012