Djeber Guendouz

Marina Deng #
email: 2marina.deng@ims-bordeaux.fr

Chhandak Mukherjee
email: 3chhandak.mukherjee@ims-bordeaux.fr

Christophe Caillaud
email: christophe.caillaud@3-5lab.fr

Patrick Mounaix
email: 5patrick.mounaix@ims-bordeaux.fr

Magali De Matos
email: 6magali.dematos@ims-bordeaux.fr

Cristell Maneux
email: 7cristell.maneux@ims-bordeaux.fr

Access Modelling-based De-embedding Method for High-frequency Characterization of Uni-traveling carrier Photodiodes

Keywords: Test structures, on-wafer HF, hybrid electronic photonic systems, UTC-PD, de-embedding method, measurements, compact model, S-parameter

This paper presents a new one-port de-embedding method demonstrated on a uni-traveling carrier photodiode (UTC-PD) technology for reliable on-wafer high frequency characterization. This method is based on small-signal modelling of RF pads and access lines connected to the active area of the UTC-PD. The new method has been investigated, validated and compared to conventional methods up to 110 GHz. Moreover, the extraction of electrical equivalent circuit elements of the UTC-PD has been validated and compared with conventional methods up to 110 GHz.

I. INTRODUCTION

Integrated hybrid electronic photonic systems (IHEPSs) are one of the most promising candidates for beyond 5G wireless telecommunications in the coming years [START_REF] Mukherjee | Towards Monolithic Indium Phosphide (InP)-Based Electronic Photonic Technologies for beyond 5G Communication Systems[END_REF]. This is due to several advantages, namely, high bandwidth and efficient transmission capacity low losses. For example, wireless telecommunications based on IHEPSs can be composed of a laser source, a modulator and a photodiode connected to an antenna for the transmission part. For the reception part of such a system, a Schottky diode can be used [START_REF] Sengupta | Terahertz integrated electronic and hybrid electronic-photonic systems[END_REF]. In IHEPSs, photodetectors play a major role. Among these photodetector technologies, the most promising are the uni-traveling carrier photodiodes (UTC-PD) which only rely on electron transport [START_REF] Ishibashi | Uni-Traveling-Carrier Photodiodes[END_REF]. This has significantly improved its saturation power and bandwidth compared to PIN photodiodes [START_REF] Ishibashi | Uni-Traveling-Carrier Photodiodes[END_REF]. As a result, UTC-PDs have become a key element for the emerging electronicphotonic technologies operating in the millimetre-wave frequency band. Reliable characterization and accurate modelling of these devices are therefore essential to enable the design of IHEPSs [START_REF] Mukherjee | Efficient compact modelling of UTC-photodiode towards terahertz communication system design[END_REF]. At high frequencies, the accuracy of the de-embedding method, that sets the measurement reference plane at the device terminals, is of utmost importance. In case of one-port active devices, such as UTC-PDs, de-embedding techniques are rarely studied and conventional methods are not readily compatible with all types of pads and access designs [5][6]. To overcome the limitations of existing methods, in this work, we propose a new one-port de-embedding method applied to a UTC-PD technology, based on the extraction of the small-signal electrical circuit of the pads and access lines specific to these devices. For method validation, we have compared the de-embedded RF measurements with compact model simulation of the UTC-PDs. Afterwards, we compare the results with existing conventional methods up to 110 GHz depicting that our proposed method offers a more reliable deembedding over the entire frequency range. The rest of the paper is organised as follows: Section II details our access modelling based de-embedding approach; Section III compares results from different de-embedding method followed by model validation; finally, Section IV draws the conclusions.

II. ACCESS MODELLING AND DE-EMBEDDING TECHNIQUE

A. Test Structures Description

The UTC-PD under test have been fabricated by III-V Lab. The UTC-PD structure is formed by a mesa connected to a waveguide by evanescent coupling. The mesa is composed of an active region. This active region is created mainly by the juxtaposition of a p-doped absorption layer and an n-doped collection layer (Fig. 1a and Fig. 1b). The small-signal electrical equivalent circuit of the UTC-PD (Fig. 1c) is mainly composed of a junction capacitance, , which models the p-n junction of the active region and a resistance, , which models the doped semiconducting layers and metal contacts. The mesa device can be biased via the P + and N + doped contacts, above and below it, respectively. On both sides of the mesa, the access lines are formed, which are connected up to the GSG pads.

The layout of the pad and the access regions of this technology is presented in Fig. 1d. The signal pad has a size of 75x80 µm 2 with a pitch of 150 µm between the signal and ground pads. The pads are connected to access regions with 50 Ω CPW transmission lines which then end on a mesa bridge. In order to remove the contributions of pads and accesses and in order to obtain the intrinsic characteristics of the UTC-PDs, complete (including the mesa bridge accesses) Open and complete Short test structures have been designed and characterized.

The complete Open and complete Short test structures are ideally modelled by a capacitance and an inductance respectively. Fig. 2 shows that this approximation is valid only up to 40 GHz, beyond which there is a frequency dependence of these electrical equivalent elements. The observed behaviour is more likely equivalent to a distributed electrical network. In order to model the later, complementary test structures have been designed and fabricated. These include, a Pad-Short and a Pad-Open (Fig. 3a) structures for the extraction of inductive and capacitive parasitic due to the pads, mesa-free Short and Open (Fig. 3b) structures for the extraction of the inductive, resistive and capacitive parasitics caused by the access lines. The complete Open and Short test structures are used for the extraction of inductive and capacitive parasitic caused by the mesa. The more detailed study will be presented in the next section.

B. De-embedding Procedures

There are mainly two de-embedding methods dedicated to these RF type of test structures. The first method is the conventional Open-Short de-embedding Method [START_REF] Koolen | On-wafer high-frequency device characterization[END_REF]. It consists of subtracting the contribution of the capacitance equivalent from the Open and the inductance equivalent from the Short. The intrinsic impedance, ZINT, of the UTC-PD can be determined by the equation ( 1 The second method, known as S-parameter based deembedding method [START_REF] Xu | A de-embedding procedure for one-port active mm-wave devices[END_REF], relies on determining the four Sparameter matrix of the pads and access (Fig. 4). For this, an Open and a Short test structure are necessary. For this method the property of the passivity of the accesses is taken into account in order to reduce the matrix elements . Also, an assumption of the symmetry of the accesses is considered

. Such an assumption cannot be verified on a one-port test structures, and therefore may introduce errors in the de-embedding process. This is further investigated in [START_REF] Konstantinou | Investigation of de-embedding techniques applied on unitraveling carrier photodiodes[END_REF]. After determining and simplifying the S-parameter matrix by using the properties of the test structures Open | | 1 and Short | | 1 , the intrinsic reflection coefficient of the UTC-PD can be simplified as (2):

- ! " # # " " ! " # ! " (2)
Where ΓO and ΓS are the reflection coefficients of the Open and Short test structures respectively, and ΓM is the total measured reflection coefficient of the UTC-PD. The new de-embedding method proposed in this work relies on the S-parameter matrix. All four matrix elements have been taken into account and no simplifications have been made, i.e. without the assumption of symmetry of the access that can introduce errors. In order to determine the matrix elements, construction of an electrical equivalent circuit of the pads and of the access lines is necessary. Then a two-port simulation can be performed to determine its four matrix elements.

The global equivalent circuit of the pads and the access has three sections as shown in Fig. 5a. The first section represents the electrical equivalent circuit of the pads. The equivalent parasitic elements of the pads can be determined from the Pad-Short and the Pad-Open test structures and their equivalent circuits (Fig. 5b and Fig. 5c). The inductive element is modelled by an inductance, $ %&' , which can be determined from the Pad-Short reflection coefficient, The second section represents the mesa-free access regions. The corresponding parasitic elements can be determined from the mesa-free Short and mesa-free Open test structures through their respective equivalent circuits (Fig. 6a and Fig. 6b The third section is equivalent to the mesa bridge access lines. The parasitic elements can be determined from the complete Short and complete Open test structures and their equivalent circuits (Fig. 7a and Fig. 7b). The parasitic lumped elements, $ 0-& and 0-& can be determined from reflection coefficients, ()*+ and %-. , de-embedded from the parasitic contributions of the pads and the mesa-free access regions. Once the equivalent circuit of the pads and the access regions is determined, the S-parameter matrix can be determined and the reflection coefficient of the UTC-PD can therefore be expressed by the following expression (3):

22 # 22 33 33 # 23 32 (3)
Where, 4 are the S-parameter matrix elements and is the total measured reflection coefficient.

III. RESULTS AND DISCUSSIONS

In order to investigate the validity of the previously discussed de-embedding methods, measurements of the S-parameters were performed on a UTC-PD with an active area of 5x25 µm 2 and on all proposed test structures: Pad-Open and Pad-Short, mesa-free Open and mesa-free Short, complete Open and complete short.

An off-wafer SOLT calibration on CS-S substrate was used to set the measurement reference planes at the probe tips. The on-wafer S-parameter measurements were carried out up to 110 GHz using an Agilent E8361 PNA, with frequency extenders for the 67-110 GHz frequency range, using Picoprobe tips.

A. De-embedding with Conventional methods

The two conventional de-embedding methods have been applied on the S-parameter measurements of the UTC-PDs up to 110 GHz. The results are shown in Fig. 8, which are compared with compact model simulation results of the intrinsic UTC-PD. A good agreement is observed until 40 GHz for both the amplitude and the phase. Beyond that, the deembedded S-parameters deviate from the model predictions.

B. De-embedding with the proposed method up to 110 GHz

Following the procedure explained in the last section, the new de-embedding method has also been applied on the measurements of the S-parameters. The parasitic elements were determined for each segment of the electrical network. Fig. 9 shows the mesa inductance, $ 0-& , extracted from ()*+ . The extracted value is overestimated since it includes a return inductance to ground. A correction to this value has been made by optimising the simulated value on the imaginary part of the admittance, %-. /6. C. Validation on UTC-PD Characterization Up to 110 GHz Following the procedure explained in the section above, the parasitic elements were determined for each segment of the electrical network. The set of the parasitic elements equivalent to the pads and access model are summarized in table I. The new de-embedding method has been applied on the one port S-parameter measurements performed on the UTC-PD technology under test. The de-embedding results and the compact model simulations are presented in Fig. 10a and Fig. 10b, showing the amplitude and the phase of the , respectively. The measurements and the model predictions are in very good agreement over the [0-110 GHz] range for all bias voltages ranging from 0 to -2 V.

Fig. 1 .

 1 Fig. 1. (a) Schematic of the UTC-PD structure (b) cross section of the UTC-PD active region (c) basic electrical equivalent circuit of the UTC-PD (d) complete Open and Short test structures.

Fig. 2 .

 2 Fig. 2. Extraction of parasitic equivalent capacitance and inductance of the complete Open and Short test structures.

Fig. 3 .

 3 Fig. 3. Complementary test structures: (a) Pad-Short and Pad-Open (b) mesa-free Short and mesa-free Open.

  device, short and open Y-parameters, respectively.

Fig. 4 .

 4 Fig. 4. Representation of S-parameter based de-embedding method.

  &' ()*+ , converted to impedance, &' ()*+ . %&' can be determined from Pad-Open reflection coefficient &' %-. converted to admittance &' %-. and then de-embedded from the pad inductances.

Fig. 5 .

 5 Fig. 5. (a) Global electrical equivalent circuit of the pads and the access of the UTC-PD; (b) electrical equivalent circuit of the Pad-Short (c) electrical equivalent circuit of the Pad-Open.

Fig. 6 .

 6 Fig. 6. Electrical equivalent circuit of the mesa-free access test structures (a) Short (b) Open.

Fig. 7 .

 7 Fig. 7. Electrical equivalent circuits of the complete (a) Short test structure (b) Open test structure.

Fig. 8 .

 8 Fig. 8. Magnitude and phase of de-embedded S11 comparing measurement (symbol) and compact model simulations (line) for a UTC-PD with an active area of 5x25 µm 2 using (a) Open-Short method (b) S-parameter based method.

Fig. 9 .

 9 Fig. 9. (a) Frequency dependence of the complete Short inductance and resistance (b) imaginary part of the admittance of the complete Open test structure.

Fig. 10 .

 10 Fig. 10. De-embedded measurements (symbol) and compact model simulations of (line) S11 for a UTC-PD with active area of 5x25 µm 2 : (a) magnitude (b) phase up to 110 GHz for biases ranging from 0 to -2V.

Table 1 .

 1 Extracted equivalent elements values for the pad and the access.

	Lpad	Cpad	Raccess	Laccess	Caccess	Lmesa	Cmesa
	18pH	15fF	1Ω	28pH	11fF	5pH	5fF

ACKNOWLEDGMENT

This work was supported partly by the European project H2020 5G-PHOS (no. 761989), http://www.5g-phos.eu/.

An extraction of the electrical equivalent circuit elements of the intrinsic UTC-PD model, namely the junction capacitance, , and the series resistance, , (real part of at high frequency) is presented in Fig. 11, comparing the three deembedding methods discussed in this work. The results obtained with the two conventional deembedding methods show a frequency dependence of the equivalent circuit elements (Fig. 11a and Fig. 11b). Among the two conventional methods, the S-parameter based method shows relatively better results in this frequency range, given that only one type of test structures, namely the complete Open and complete Short, are available. Provided that we have all the test structures necessary to construct the distributed model, the access modelling-based method remains more accurate and reliable up to 110 GHz (Fig. 11c), compared to conventional methods. It should be noted that a 3-dB cut-off frequency of 44 GHz has been extracted at -2V for this device.

IV. CONCLUSION

In this paper, we have evaluated two conventional deembedding methods, namely the Open-Short method and the Sparameter based method. The results show that these methods are not compatible for all types of test structures and are no longer valid above 40 GHz, with however slightly better result for S-parameter based method. To provide accurate deembedding above 40 GHz, we have proposed a new access modelling-based de-embedding method that has been validated against S-parameter measurements of a UTC-PD. The results obtained from this method shows good accuracy in comparison with the compact model simulations up to 110 GHz. Furthermore, we have also extracted the small-signal equivalent circuit parameters of the UTC-PD with the three de-embedding methods. Unlike the two conventional methods that give frequency-dependent values and are not representative of the UTC-PD equivalent circuit model, our method allows to extract frequency-independent model parameters up to 110 GHz. Our proposed method can prove to be quite essential for on-wafer high-frequency characterization of UTC-PDs, especially beyond 110GHz.


Nil Davy

Marina Deng

Virginie Nodjiadjim

Mukherjee Chhandak

Muriel Riet

Colin Mismer

Jérémie Renaudier

Cristell Maneux

Marina Deng²

Chhandak Mukherjee²

Cristell Maneux²

InP DHBT test

Keywords: Characterization, Millimeter-wave, Double heterojunction bipolar transistor (DHBT), InP/InGaAs, Indium Phosphide (InP) C

published or not. The documents may come   L'archive ouverte pluridisciplinaire

I. INTRODUCTION

Due to the increase in the volume of data exchanged, developing high-speed communication systems has become crucial, be it for optical or wireless communications. For this purpose, developing transistor technologies that combine high speed and high breakdown voltage has become mandatory. InP double heterojunction bipolar transistors (InP DHBT) have these characteristics. Both Type-I [START_REF] Rode | Indium Phosphide Heterobipolar Transistor Technology Beyond 1-THz Bandwidth[END_REF] and Type-II [START_REF] Arabhavi | InP/GaAsSb Double Heterojunction Bipolar Transistor Emitter-Fin Technology With fMAX = 1.2 THz[END_REF] DHBTs have already demonstrated fMAX above 1 THz while having breakdown voltages of 4.1 V and 5.4 V, respectively.

To benefit from these performances, accurate characterization of these transistors is crucial in order to confirm the high cutoff frequency and to validate the associated compact model used for integrated circuit (IC) design. Transistor characterization below 110 GHz often involves off-wafer calibration and open-short de-embedding [START_REF] Rode | Indium Phosphide Heterobipolar Transistor Technology Beyond 1-THz Bandwidth[END_REF]- [START_REF] Xu | 0.5 THz Performance of a Type-II DHBT With a Doping-Graded and Constant-Composition GaAsSb Base[END_REF]. It has been shown that measurements beyond 110 GHz are particularly difficult [START_REF] Yau | Device and IC Characterization Above 100 GHz[END_REF]. To perform InP DHBT characterization at higher frequencies, on-wafer thru-reflectline (TRL) calibration has been introduced along with optimized test structures [START_REF] Deng | InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design[END_REF]- [START_REF] Williams | Calibrations for Millimeter-Wave Silicon Transistor Characterization[END_REF]. This method has demonstrated excellent results. However, it requires more area on the wafer to accommodate additional calibration structures and one needs to change the inter-probe distance during the calibration step.

However, most of these previous works do not take into account the "industrial" point of view of characterizing transistors and rather invest of developing techniques that are area consuming. With that in mind, in this paper, we introduce a new industrially compatible design. This new design contains optimized test structures as well as a high density of transistors. The rest of this paper is organized as follows: section II details the transistor technology and the three RF test structures design; section III presents the comparison of the three test structure designs on deembedding structures characterization and InP DHBT RF figures of merit extraction.

II. RF TEST STRUCTURE DESIGN OPTIMIZATION

A. Technology description

The InP DHBT structure is grown on a 3-inch semiinsulating substrate using solid source molecular beam epitaxy (SSMBE). The intrinsic emitter is 40-nm thick InP. The highly C-doped (8 • 10 19 cm -3 ) 28-nm InGaAs base is compositionally graded (from In0.47Ga0.53As on the emitter side to In0.53Ga0.47As on the collector side) in order to reduce the base transit time. The 130-nm thick composite collector is composed of a non-intentionally doped InGaAs spacer, a 20-nm thick highly doped layer and a lightly doped collector region. The transistors are processed using a wet-etch selfaligned triple mesa technology as described in [START_REF] Nodjiadjim | 0.7-μ m InP DHBT Technology With 400-GHz fT and fMAX and 4.5-V BVCE0 for High Speed and High Frequency Integrated Circuits[END_REF]. This technology, which also includes three levels of gold metallization for interconnections, is compatible with circuit design [START_REF] Konczykowska | Extreme Speed Power-DAC: Leveraging InP DHBT for Ultimate Capacity Single-Carrier Optical Transmissions[END_REF], [START_REF] Hersent | 160-GSa/s-and-Beyond 108-GHz-Bandwidth Over-2-V ppd Output-Swing 0.5-μm InP DHBT 2:1 AMUX-Driver for Next-Generation Optical Communications[END_REF]. Among the characterized devices, different transistor geometries were considered: emitter width varied from 0.4-µm to 0.7-µm while the emitter length varied from 5-µm to 10-µm. Fig. 1 shows a scanning electron microscopy view of a 0.4 × 7 µm² InP DHBT. The performances of the 0.4 × 5 µm² InP DHBT under test have been presented in [START_REF] Davy | 0.4-μm InP/InGaAs DHBT with a 380-GHz fT[END_REF]. The common emitter breakdown voltage BVCE0 is greater than 4.5 V and the static current gain β is around 30. The transition frequency, fT, and the maximum oscillation frequency, fMAX, are 380 GHz and 605 GHz, respectively.

B. Layout and floor-plan optimization of RF test structures

In this study an optimized design of RF test structures for industrial application is proposed. In order to analyze its performances, three different RF test structures are compared. The first design is used in an "industrial" context while the second has been designed to prove the feasibility of measurement up to 500 GHz. The third one is the new optimized design proposed in this work

1) High density pads (design 1)

This design (see Fig. 2) is the pre-defined design in standard III-V Lab process. It is designed with the purpose of maximizing the number of test structures within the chip area with different geometries of transistors. These highdensity constraints are imposed due to the fact that a large number of transistors is required for process yield and variability analysis. The RF pads are compatible with 100µm pitch probes. The density of transistor targeted with this design is 20 transistors per chip.

Fig. 2. Photograph of a die with high density pads

2) High quality pads (design 2) As presented in [START_REF] Deng | InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design[END_REF], this design (see Fig. 3) combines two optimization strategies to improve the on-wafer measurement accuracy up to 500 GHz. First, a continuous ground plane was implemented in order to minimize the probe-to-substrate coupling, as well as the coupling between neighbouring structures. By connecting all the ground pads together and creating a signal pad shielding, this continuous ground plane also contributes to the improvement of the RF signal propagation along the access line. Second, on-wafer TRL calibration method was used up to 500 GHz, requiring the design of TRL standards on the same InP substrate as the devices to characterize. In addition, the RF pads were compatible with the 50-100 µm probing pitch required by the RF probes in different frequency bands up to 500 GHz. The density of this design is 8 transistors per chip (Fig. 3 shows a chip, which has twice the area of the one in Fig. 2). Fig. 3. Photograph of a die with high quality pads

3) Optimized pads for industrial process fabrication (design 3)

This third design (see Fig. 4) re-uses the continuous ground plane method used in the design 2 as it reduces the probe to substrate interaction for high frequency measurements. Moreover, a checkerboard configuration, as introduced in [START_REF] Cabbia | Silicon Test Structures Design for Sub-THz and THz Measurements[END_REF], was implemented. It allows the reduction of the distance between the neighbouring structures that are above and below. Thus, this configuration allows to optimize the density of test structures while maintaining a reduced coupling between neighbouring test structures. These pads are designed for 100-µm pitch probes. The density is 14 transistors per chip. To analyze the performances of these three test structure designs, the measurements on a 0.4 × 5 µm² InP DHBT and on its associated de-embedding test structures were performed. The S-parameters measurements were carried out from 1 GHz to 110 GHz with an Anritsu Vectorstar network analyzer using an off-wafer Short-Open-Load-Through (SOLT) calibration and 100-µm pitch Picoprobe RF probes.

A. De-embedding test structures characterization up to 110 GHz

The accurate extraction of transistor parameters relies on a precise de-embedding of parasitic capacitances and inductances that surround the device. In order to verify the validity of the de-embedding, open and short structures are associated to electrical equivalent circuits (see Fig. 5). To verify that open capacitances and short inductances are not frequency-dependent, their values were extracted using Y and Z parameters (see Fig. 7.). As observed from Fig. 7, the measured open capacitances and short inductances of the three different test structure designs are quite constant over the frequency range. There is no resonance over the 110 GHz band. Design 1 is strongly asymmetric; it explains why C1 and C2 (as well as L1 and L2) show different values. The value of C1 and C2 can be correlated to the metal that surrounds the signal pad, which is why capacitances of design 2 (which is designed for 50-µm probe pitch) are twice the capacitances of design 1. Moreover, for the same design, a difference between L1 and L2 is visible. It is caused by the different RF probe tip positioning on the pads at port 1 and port 2, resulting in an unequal distance from the center of the test structure. The sensitivity to the probe tips positioning is one of the main drawbacks of probe-tip calibration methods, such as the SOLT calibration used in this work. Fig. 8 shows the C12 capacitances of the three test structure designs. It appears that in all three cases, the capacitance value starts to drop after 80 GHz. This behavior is certainly due to the signature of the Picoprobe RF probes, since it has already been observed both in EM simulation and measurement in [START_REF] Deng | Design of On-Wafer TRL Calibration Kit for InP Technologies Characterization up to 500 GHz[END_REF], where Picoprobe RF probes were also used.

The capacitance in design 1 is not constant (up to 80 GHz), this indicates that coupling (with substrate or adjacent structures) still occurs. The probe-to-probe distance is different in the three test structure designs which explains the difference between the C12 capacitances values.

B. Extraction InP DHBT RF figures of merit up to 110 GHz

The InP DHBT were measured at VCE = 1.6 V and different collector current densities JC (from 0.25 mA/µm² to 9 mA/µm²). This chosen value of VCE is a trade-off to combine high values of both fMAX and fT. Open-short deembedding is performed to extract the performances of the device.

The extraction results of fT are shown in Fig. 9. The extraction of fT up to 110 GHz gives pretty similar results between the three designs. On the other hand, extraction of the maximum oscillation frequency fMAX is more challenging and is sensitive to the design (see Fig. 10). Design 1 leads to an inaccurate extraction of fMAX, certainly due to a combined effect of crosstalk between ports and additional coupling effects for using this non-optimized RF test structure design. The industrial design 3 produces results comparable to the optimized design 2 for the extraction of fMAX up to 70 GHz. This confirms the satisfying tradeoff made in design 3 between optimization of RF test structures design and high device density. The drop of the three curves after 70 GHz is attributed to RF probes (and their coupling with structures). This effect is described in [START_REF] Fregonese | Importance of Probe Choice for Extracting Figures of Merit of Advanced mmW Transistors[END_REF] where probe effects appear after 40 GHz. In our case, these effects appear at higher frequencies, which is why it is still possible to extract fMAX by fitting a single pole function on the measurements up to 60 GHz (as shown on Fig. 10).

Fig. 1 .

 1 Fig. 1 . Scanning electron microscopy view of a 0.4 × 7 µm² InP DHBT before interconnection level

Fig. 4 .

 4 Fig. 4. Photograph of a die with optimized pads

Fig. 5 .

 5 Fig. 5. Equivalent electrical circuit of (a) open and (b) short structures

Fig. 7 .Fig. 8 .

 78 Fig. 7. Measured open capacitances and short inductances of the 3 test structure designs

Fig. 9 .

 9 Fig. 9. Determination of fT with gain-bandwidth product of a 0.4 × 5 µm² DHBT at VCE = 1.6 V and JC ≈ 6 mA/µm

Fig. 10 .

 10 Fig. 10. Determination of fMAX with gain-bandwidth product of a 0.4 × 5 µm² DHBT at VCE = 1.6 V and JC ≈ 6 mA/µm

ACKNOWLEDGMENT

This work was supported by ANR-FNS through ULTIMATE project (ANR-16-CE93-0007) and by the European Commission through the Photonics Public Private Partnership Initiatives under Grant H2020-ICT-2019-2 (Twilight Project).