Alexandre Goeritz

Selin Tolunay

Ngan Big

Pierre Grenoblois

Fanny Ferris

Special thanks to the

Introduction

The wireless sensor networks for present consumer applications requires improved capabilities of wireless systems, including extremely high data rate, increased security, reduced electromagnetic interference, extreme miniaturization and low power consumption but with low cost. These applications include wireless personal area networks (WPAN), wireless highdefinition video distribution, point-to-point links, automotive radars, backhauling. Due to congested aspect of the low frequency bands, these applications are moving to a significantly higher region of the frequency spectrum, at the millimeter-wave range.

To achieve well distributed point-to-point communication, most Wi-Fi applications at mmwave require phased arrays. Phased arrays allow long communication range and minimize power consumption. A phased array is composed of an array of antennas in which the relative phases of the respective signals feeding the antennas are set to reinforce the radiation pattern in a desired direction and suppressed in other. In that context, phase shifters constitute the main challenge. Several technologies have been used to develop phase shifters at mm-wave for the consumer market, including CMOS, BiCMOS, BST, Liquid Cristal and MEMS. The present state-ofthe-art shows that the phase shifters either consume high amount of power or occupy large surfaces and with significant insertion loss.

Due to the poor quality factor of varactors above 30 GHz frequency range it does not constitute a well-suited tunable element. MEMS technology is preferable in terms of electrical performance, but lead to large foot-print areas. In that context, tunable integrated slow-wave coplanar waveguides (S-CPWs) offer many advantages since (i) the floating shield of S-CPWs offers an additional degree of freedom for design purpose, (ii) S-CPWs exhibit inherently good quality factor, above 40, due to their strong slow-wave effect, and (iii) they present a high miniaturization factor (about 3 compared to classical non-slow-wave transmission lines).

The aim of the present thesis is to develop a distributed-MEMS phase shifter based on tunable slow wave CPW in BiCMOS technology. The phase tunability of the S-CPW can be achieved by etching the material between the floating shield and the CWP strips of the S-CPW.

According to the voltage difference applied between floating shield and CPW strips, the shield can move, likely as in a NEMS. Note that tunability has already been demonstrated with such etched components by replacing the removed part with liquid crystals. In this thesis, a post-CMOS etching process has been applied to demonstrate good tunability without liquid crystals, thanks to the electromechanical effect.

In the first chapter, after explaining the principle of phase shifters and their applications, we will describe the existing technologies before presenting the background of tunable phaseshifters based on Slow-wave CPW. We will justify with a brief discussion the use of MEMS technology with a post-CMOS process (0.25 µm BiCMOS technology from IHP, Germany) and we will introduce the main objectives of this thesis.

In the second chapter, a brief review about RF-MEMS switches (i.e. ohmic switches and capacitive switches) and the electrostatic actuator will be carried out. Then, the simulated electrical performance of S-CPW in 0.25 µm BiCMOS technology will be presented. A new design topology of tunable S-CPW (TS-CPW) will be proposed. This proposed topology will be optimized in order to get good performance in terms of quality factor and insertion loss.

In the third chapter, the proposed TS-CPW will be used to design a distributed-MEMS phase shifter. A 1-bit phase shifter is first proposed by regrouping the floating ribbons of the TS-CPW, followed by the presentation of the design methodology used to design a digital phase shifter with N-bit of resolution and N-commands. The proposed methodology is then used to design a 3bit phase shifter working at 60 GHz.

In the last chapter, the first measurement results of the distributed-MEMS phase shifter will be presented, and compared to the state-of-the art. Finally, a brief study about the parasitic effect of the substrate is made, followed by a solution in order to solve this issue.

Chapter 1

1.

Mm-wave phase shifters: overview and state-of-the-art

Among the large number of integrated circuits in millimeter waves (mm-waves), phase shifter (PS) is a fundamental device of front-end transceivers. It is also the most important component in phased arrays for adjusting the phase on each antenna in order to achieve adaptive beam-steering.

Phase shifter can be passive or active with digital or analog tuning. It can be controlled electrically, magnetically or mechanically, and can be realized in various technologies with different topologies. Only passive phase shifters are considered in this thesis. The term "passive"

will not be precised each time alongside the manuscript.

In this chapter, we present first an overview about several topologies of phase shifters and their recent applications in mm-waves. Then, a state-of-the-art on tunable phase shifters is carried out, classified according to the various technologies that can be used for tunability. In particular, a tunable phase shifter based on slow wave transmission lines is described. This technique is called distributed MEMS. Finally the description of the former and actual technologies in which the distributed MEMS approach has been developed at IMEP-LaHC is proposed, with a specific focus on IHP technology that was particularly studied and used during this PhD thesis.

1.1.Overview

The difference in phase angle between the input and the output signals of a 2-port device is expressed by the insertion phase angle 𝜑, as illustrated in Figure 1-1. The S-parameters of the transmission mode can be given by eq. (1-1) when perfect matching and lossless network are considered. [𝑆] = [ 0 𝑒 𝑗𝜑 𝑒 𝑗𝜑 0 ]

(1-1)

The difference between two insertion phase angles (when an array of phase shifters is considered) or between an insertion phase angle and a reference phase angle (when making the insertion phase angle to vary) defines the relative phase shift that is expressed by eq. (1)(2).

𝛥𝜑 = 𝜑 2 -𝜑 1 (1-2)
An important parameter is the figure of merit (FoM in °/dB), defined as the maximum phase shift (∆𝜑 𝑚𝑎𝑥 ) divided by the maximum insertion loss (𝐼𝐿 𝑚𝑎𝑥 in dB) (See eq. (1-3) and (1-4)).

Phase shifters may have analog or digital tuning. Analog phase shifters generate a continuous phase shift like the voltage-controlled phase shifter, which is controlled by varactor diodes. Digital phase shifters provide a discrete set of phase shifts. It discretizes the absolute phase into predetermined phase states, and the different phase states can be changing by digitally controlling each phase-shifter bit. It is an important issue to switch to different states of the digital phase shifter precisely. They are many methods to carry out a digital phase shifters, in this thesis; we are interested for digital phase shifter using the microelectromechanical systems (MEMS) to realize its switch.

Phase shifters are used in several applications. At mm-wave frequencies, the most important application is within a phased array antenna and reconfigurable antenna architecture for consumer applications such as wireless personal area networks (WPAN), wireless high-𝐼𝐿 = -20𝑙𝑜𝑔 10 𝑆 21

(1-3)

𝐹𝑜𝑀 = ∆𝜑 𝑚𝑎𝑥 𝐼𝐿 𝑚𝑎𝑥

(1-4)

definition video distribution, point-to point links, automotive radars and wireless sensor networks in general. Other applications of phase shifters include RF and microwave measurement instrumentation, PA linearizers, voltage controlled oscillator (VCO) and smallshift frequency translators [1] [2] [3]. Three main applications are presented herein: the tunable antenna phased array, the Butler matrix and the VCO.

A phased array is composed of an array of antennas in which the relative phases of the respective signals feeding the antennas are set in such a way that the effective radiation pattern of the array is reinforced in a desired direction and suppressed in all undesired ones. The phase relationships among the antennas can be fixed or adjustable by using tunable phase shifters, as for beam steering. Adding a phase shift to the signal received by each antenna in an array of antennas permits the common signal of these individual antennas to act as the signal of a single antenna with performance greatly different from the individual antennas in the array. In Figure 1-2, tunable phase shifters are integrated in an optimized design of a low-cost phased array antenna. One application for phase shifters is the Butler matrix, offering beam forming and scanning network capabilities. The Butler matrix is a microwave network, constituted of couplers and phase shifters. A voltage controlled oscillator (VCO) is one of the most important circuits in wireless communication systems as a part of frequency synthesizers. A classical VCO is implemented by using a 𝐿𝐶 ↗ tank to generate signals at a particular frequency. Frequency control is traditionally achieved through a varactor diode or a variable MOS capacitance, etc., but power consumption is a special concern for portable devices using VCOs. This is the reason why some researches started a few years ago to implement PSs (mostly passive PSs) in VCOs due to their low power consumption to replace the conventional 𝐿𝐶 ↗ resonator. For example, Figure 1-4 shows a common collector Colpitts VCO using a tunable phase shifter as the frequency tuning component. This is a non-conventional use for phase-shifters. Here, to realize a tunable VCO, a voltage controlled analog phase shifter (tunable phase shifter) is placed between the input of the common collector Colpitts oscillator and ground. In this sub-section, we present three topologies to perform phase shifting:

• Reflection type phase shifter (RTPS),

• Loaded-line phase shifter,

• Switched-line phase shifter,

The first kind of phase shifter is the reflection type phase shifter (RTPS), which was proposed for the first time in 1960 by [8]. An ideal reflection load (here a reactance 𝑍 𝐿 = 1/𝑗𝑐𝜔) can be considered as a single-port circuit with a reflection coefficient of magnitude unity and a relative phase shift. The phase angle of the transmission coefficient between ports 1 and 2 is expressed in eq. (1)(2)(3)(4)(5).

𝜑 = 𝜋 -2atan ( 𝑧 𝐿 𝑧 0 )

(1-5)
where 𝑍 0 is the port impedance.

The relative phase shift obtained from the tunable reactance (𝑧 𝐿𝑚𝑖𝑛 , 𝑧 𝐿𝑚𝑎𝑥 ), is given by eq. (1)(2)(3)(4)(5)(6).

𝜑 = 2[atan ( 𝑧 𝐿𝑚𝑖𝑛 𝑧 0 ) -atan ( 𝑧 𝐿𝑚𝑎𝑥 𝑧 0 ) (1-6)
The second type of phase shifters is based on a loaded-line topology, which is used to tune the characteristics of a transmission line. The basic form for the loaded-line phase shifter is a transmission line possessing characteristic impedance (𝑍 𝑇 ) and electrical length (𝜃), periodically loaded with reactive loads (shunt or series). The relative phase shift is obtained when the impedance of loads is changed, as shown in Figure 123456. This type of phase shifter has one disadvantage that is the interruption of the signal during the transmission, and this may be a problem in some communication applications, where protocols do not devote time for this interruption.

1.2.State-of-the-art

In this section, we present the state-of-the-art of passive phase shifters at mm-waves. Four technologies available at mm-waves are described:

• Ferroelectrics,

• Liquid crystals,

• Silicon (CMOS/BiCMOS),

• MEMS.

Ferroelectrics are non-linear materials, but their main characteristic is the high and tunable relative permittivity. Several materials are available: Barium-Strontium-Titanate (BST),

Potassium-Niobium-Titanate (KTN) or Lead-Zirconium-Titanate (PZT). The BST is the most popular ferroelectric material used in various microwave devices, such as phase shifters, filters, etc., because it has low dielectric losses, high tunability and low coercive field, thus reducing the hysteresis effect and simplifying the electric command [19].

A 360° phase shifter in the Ka-band with a moderate bias voltage using BST material was proposed in [START_REF] Vel | A 310°/3.6-dB K-band phaseshifter using paraelectric BST thin films[END_REF]. The phase shifter consists of a CPW for (CoPlanar Waveguide) periodically loaded by interdigitates BST capacitors (Figure 12345678). This design is also used by [START_REF] Liu | BaSrTiO interdigitated capacitors for distributed phaseshifter applications[END_REF]. The measured insertion loss of the proposed phase shifter is around 0.8 dB at low frequencies (1 to 5 GHz) and 3.6 dB at 30 GHz. The return loss is better than 12 dB in the entire frequency range which shows a good matching of this circuit. The maximum value of phase shift is 310° with a DC voltage of 35 V, leading to a figure of merit of 85°/dB.

The phase shifter proposed in [START_REF] De Paolis | High-Tunability and High-Q-Factor Integrated Ferroelectric Circuits up to Millimeter Waves[END_REF], based on [START_REF] De Paolis | Characterization of ferroelectric BST MIM capacitors up to 65 GHz for a compact phase shifter at 60 GHz[END_REF] and [START_REF] Erker | Monolithic Ka-band phase shifter using voltage tunable BaSrTio parallel plate capacitors[END_REF], is based on a high impedance CPW loaded with 12 identical MIM capacitors. It represents the first tunable phase shifter based on BST MIM capacitors working at 60 GHz. The schematic of the phase shifter and the design of a MIM capacitor are given in Figure 123456789. The measured electrical characteristics of the phase shifter are 12 dB and 5.9 dB for return loss and insertion loss, respectively. When varying the applied voltage from 0 to 90 V, the maximum value of phase shift is 150° at 60 GHz, which gives a FoM of 25°/dB. Due to the high dielectric losses (in literature tan δ is 0.07, 0.13 and 0.2 in [START_REF] Yashchyshyn | Tunable ferroelectric ceramic-polymer composites for sub-THz applications[END_REF], [START_REF] Houzet | Dispersion and loss of ferroelectric Ba Sr TiO thin films up to 110 GHz[END_REF] and [START_REF] De Paolis | Characterization of ferroelectric BST MIM capacitors up to 65 GHz for a compact phase shifter at 60 GHz[END_REF],

respectively) in the mm-waves, the FoM remains quite low at 60 GHz. (a)

(b) (c)
Liquid crystal (LC) is an anisotropic material, which exhibits two different permittivities depending on molecule direction. In between their solid and liquid states it has, depending on the LC mixture used, different mesophases such as the smectic and the nematic phase [START_REF] Strunck | Reliability study of a tunable Ka-band SIW-phase shifter based on liquidcrystal in LTCC-technology[END_REF]. The nematic liquid crystal (LC) can be employed as a tunable dielectric in the microwave devices.

In [START_REF] Bulja | Liquid crystal based phase shifters in 60 GHz band[END_REF], two LC-based phase shifters working in the 60 GHz band were presented. The first one is a meandered line phase shifter (MLPS) and is illustrated in Figure 1-10(a). It is based on a microstrip line with CPW transitions, as detailed in [START_REF] Bulja | A new structure for reflection-type phase shifter with 360° phase control range[END_REF]. These transitions are proposed in order to provide low reflection as well as DC connectivity to the conductor pattern exposed to LC. An insertion loss of 11 dB and a return loss of 12 dB were observed. The maximum value of phase shift was 47°, leading to a figure of merit around 4°/dB.

In [START_REF] Jost | Continuously tuneable liquid crystal based stripline phase shifter realised in LTCC technology[END_REF], a LC phase shifter with a stripline configuration is integrated in a LTCC technology (for low temperature cofired ceramic), a low loss multilayer technology. The LC is an available commercial solution, as compared to the special LC solution used by the same team in [START_REF] Mueller | Tunable passive phase shifter for microwave applications using highly anisotropic liquid crystals[END_REF],

together with a standard inverted microstrip in a TMM3 technology (a low permittivity composite ceramic substrate). In [START_REF] Jost | Continuously tuneable liquid crystal based stripline phase shifter realised in LTCC technology[END_REF][33], the figure of merit at 24 GHz was as high as 110°/dB, but the used LC solution might suffer from badly aging which does not seem the case in [START_REF] Jost | Continuously tuneable liquid crystal based stripline phase shifter realised in LTCC technology[END_REF].

What's more, the topology suffered from large response time, which was in the order of minutes depending on the LC material and layer thickness. These are the two reasons why this work has not been referred to in Table 1-2. In [START_REF] Franc | Compact and Broadband Millimeter-Wave Electrically Tunable Phase Shifter Combining Slow-Wave Effect With Liquid Crystal Technology[END_REF], the same team associates with IMEP-LaHC on a commercially available LC solution.

The phase shift effect is high but conjugated with a distributed-MEMS effect which leads to a very interesting FoM of 51°/dB at 45 GHz. In [START_REF] Mueller | Passive tunable liquid crystal finline phase shifter for millimeter waves[END_REF], in 2005, the aim was to test a specific solution, with similar benefits and disadvantages than in [START_REF] Mueller | Tunable passive phase shifter for microwave applications using highly anisotropic liquid crystals[END_REF]. The FoM is thus very interesting but the PS presents an off-time still superior to 10 s. Main results for phase shifters using liquid crystal technology are presented and compared in Table 1-2. In recent years, devices based on silicon in CMOS/BiCMOS technologies have dominated the integrated circuits applications. Thus, in this sub-section we describe the main results carried out in these technologies.

In [START_REF] Vadivelu | Integrated CMOS mm-wave phase shifters for single chip portable radar[END_REF], three different passive and active phase shifters were designed and fabricated in a standard 1P7M 90 nm CMOS process. Here, we present only the passive phase shifter used in the Insertion loss of 16.75 dB and phase shift of 141° were obtained, leading to a FoM of 8.4°/dB.

A 4-bit passive phase shifter with phase resolution of 22.5° for automotive radar applications operating in the frequency range from 67 to 78 GHz was designed in a 0.12 µm BiCMOS process (IBM 8HP) in [START_REF] Young | A 4-bit Passive Phase Shifter for Automotive Radar Applications in 0.13 µm CMOS[END_REF]. It consists of a low-pass π-network and CMOS passive switches. All inductors that form the low-pass π-network were implemented with a grounded CPW as shown in Figure 1-14 (a). The design, fabrication and characterization of a 2-bit switched line phase shifter using dccontact single-pole-quadruple-throw (SP4T) RF-MEMS switches for 60 GHz applications were investigated in [START_REF] Songbin Gon | A 60-GHz 2-bit Switched-Line Phase Shifter Using SP4T RF-MEMS Switches[END_REF]. The SEM of the SP4T switches and the 2-bit phase shifter are shown in An average insertion loss of 2.5 dB in the frequency range from 55 to 65 GHz was achieved for the 2-bit phase shifter, with a return loss better than 12 dB for all 4 states (0°, 90°, 180°and 270°), leading to a FoM equal to 108°/dB when considering the maximum phase shift of 270°.

A V-band CMOS-MEMS switchable phase shifter based on reflection-type topology was proposed in [START_REF] Chang | A V-Band Three-State Phase Shifter in CMOS-MEMS Technology[END_REF]. The schematic of the proposed phase shifter and its images of fabrication are shown in Figure 1 After the fabrication of the phase shifter in a 0.18 µm CMOS technology, a post-CMOS process is necessary to release the MEMS structure. When an actuation voltage of 46 V is applied, three discrete phase states of 0°, 89° and 144° are achieved at 65 GHz. The measured return loss is better than 14 dB and the insertion loss is around 2.2 dB over the 55-65 GHz range.

This performance is attributed to a specifically developed technology with an optimization of the design methodology. Table 1-5 The request for higher data rates and spectrum limitation makes 60 GHz the most promising frequency to return multi-gigabit high throughput wireless communication. This is due to its abundant multiple gigahertz license-exempt spectrum frequency and particularly for WPAN and WLAN implementation. Table 5 summarizes the main performance (FoM, insertion loss, return loss, phase shift and etc.) for 60-GHz phase shifters described in previous sections. For all of these reasons, this PhD thesis will focus on a particular type of MEMS-based technologies, patented by the IMEP-LaHC laboratory, in the mm-wave frequency band. More precisely, a distributed MEMS slow wave coplanar waveguide (S-CPW) will be used as the basic element for tunability.

Solution based on slow wave transmission lines

There are several planar transmission lines such as microstrip and coplanar waveguide, which can be realized in different technologies as the printed circuit PCB and integrated CMOS/BiCMOS.

In the following sub-sections, we focus on the characteristic of a transmission line and how to make it tunable with two ways.

A transmission line (Tline) is characterized by different parameters. The propagation constant 𝛾 is the sum of the attenuation constant 𝛼(dB/m) and the phase constant 𝛽(rad/m) as seen in eq. (1)(2)(3)(4)(5)(6)(7)(8)(9).

𝛾 = 𝛼 + 𝑗𝛽

(1-9)

When the Tline exhibits very low loss, 𝑅 𝑙 and 𝐺 𝑙 can be neglected, and the characteristic impedance can be considered as real, eq. (1-10).

𝑍 𝑐 = √ 𝐿 𝑙 𝐶 𝑙

(1-10)

In low-loss case, the attenuation constant 𝛼 can be expressed by eq. (1-11 The phase shift 𝜑 (or electrical length) for a TLine is expressed by eq. (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14).

𝜑 = 𝛽. 𝑙 (1-14)

where 𝑙 is the physical length of the TLine.

The efficiency of a Tline is defined by an important parameter called quality factor 𝑄, given by eq. (1-15), [START_REF] Hsu | On the general relation between /α/ and Q (Correspondence)[END_REF] and [START_REF] Golde | On a relation between α and Q[END_REF].

𝑄 = 𝛽 2𝛼

(1-15)

Eq. (1-16) can be obtained when the numerator and the denominator of eq. In integrated technologies, the performance of a Tline is limited by technology and price, which depends on the surface area. Some miniaturization methods have been developed in order to obtain good performances. In this section, we focus on the Slow-wave CoPlanar Waveguide called S-CPW, which is a topology that has been studied since more than ten years to reach higher quality factors than the microstrip line in integrated CMOS/BiCMOS technologies.

Concept

The classical CPW was invented in 1969 by Wen [START_REF] Wen | Coplanar waveguide: A surface strip transmission line suitable for nonreciprocal gyro-magnetic device applications[END_REF]. It is a planar Tline such as the microstrip, while the signal and the ground of CPW are formed on only one layer of metal. The structure of CPW is composed of the central strip for the signal and two strips for the grounds, deposited on a dielectric substrate. In order to improve the performance of the CPW, in particular the quality factor, we can reduce the losses or increase the phase constant in respect to eq. (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15). Usually, 𝛼 is imposed by the technology used for fabrication, so the solution is to increase 𝛽 without changing the fabrication process. From eq. (1-13), with increase in 𝛽 , the phase velocity decreases, and then the capacitance or the inductance increases. Thus, we can increase the capacitance by loading the CPW with shielding ribbons, also called fingers or sometimes shielding strips, without varying the inductance. This shielding layer is floating; it is made of metallic strips of width 𝑆𝐿 (for Shielding ribbons Length), which are separated by a gap 𝑆𝑆 (for Shielding ribbons Spacing). The spacing between the CPW strips' plane and the shielding layer plane is given by h. The topology of a S-CPW is shown in Figure 123456789101112131415161718. As shown in Figure 1-18, the magnetic field passes through the spaces between the shielding strips. This leads to an inductance per length unchanged as compared to a classical CPW, whereas the electrical field lines end at the shielding strips; electrical field is concentrated between the CPW strips and the shielding strips. Thus, the capacitance per length is increased as compared to a classical CPW.

Electrical model

Eq. (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17) describes the total capacitance (𝐶𝑡𝑜𝑡) of the S-CPW constituted of the capacitance between the CPW strips and the shielding layer, 𝐶𝑊, in series with the capacitance between the CPW ground and the shielding layer, 𝐶𝑊𝑔. To model the conductive loss that occurs in the shielding strips, a resistance 𝑅𝑠𝑡𝑟𝑖𝑝𝑠 is added in series with𝐶𝑡𝑜𝑡. The total resistance 𝑅𝑡𝑜𝑡 is given by eq. (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18).

𝐶𝑡𝑜𝑡 = 2. 𝐶𝑊. 𝐶𝑊𝑔 𝐶𝑊 + 𝐶𝑊𝑔

(1-17)

𝑅𝑡𝑜𝑡 = 𝑅𝑠𝑡𝑟𝑖𝑝𝑠 2

(1-18)

The RLCG model for CPW is not sufficient to evaluate the full behavior of S-CPW when losses In practice, the dielectric loss G bulk due to the substrate is negligible because the electrical field is blocked by the shielding layer. Hence G bulk is due to silicon oxide layers only that present low dielectric losses and can be avoided in the model. In order to fast compute the electrical performances of a slow-wave CPW, an analytical method was developed in [START_REF] Bautista | An Accurate Parametric Electrical Model for Slow-wave CPW[END_REF] and [START_REF] Bautista | Accurate Parametric Electrical Model for Slow-Wave CPW and Application to Circuits Design[END_REF].

1.4.Tunable slow-wave transmission lines

More than five years ago, several research projects have started at IMEP-LaHC based on a totally innovative technology of tunable S-CPW. Make this TLine tunable is proposed in two patents in 2011 [START_REF] Rehder | Tunable High-Frequency Transmission Line[END_REF] and 2012 [START_REF] Rehder | Ligne de transmission haute fréquence accordable[END_REF]. This sub-section and section 1.4.3 focus on the description of how to make this S-CPW Tline tunable.

Per definition a tunable Tline is a Tline that has variable characteristic impedance. Then, according to equation (1-10), to change the characteristic impedance of a Tline, we have two possibilities: vary 𝐿 𝑙 or 𝐶 𝑙 . Changing 𝐿 𝑙 will not be the right way as we need to maintain a good quality factor. This is due to extra conductive losses that will be added when making 𝐿 𝑙 to increase whereas it is explicit that 𝛼 should not be higher, according to equation (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15). Hence, it is chosen to vary the capacitance 𝐶 𝑙 . Therefore, in order to make the S-CPW tunable (TS-CPW), In that case, the topology of TS-CPW is based on varactors; its principle is to add varactors between the signal strip and the shielding plane as shown in Figure 1-21. The total capacitance that is controlled by the bias voltage applied to varactors (DC voltage is depending of the technology used) causes the variation of the phase and of the characteristic impedance.

𝐶𝑡𝑜𝑡
[51] has proposed a phase shifter based on TS-CPW with varactors implemented in the 55 nm technology by STMicroelectronics. The shielding plan is broken in order to connect the varactors 𝐶 𝑣 in between as shown in Figure 1-22(a). The total TS-CPW's capacitance is variable and is given by equation (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19).

𝐶 = 2. 𝐶𝑠. 𝐶𝑔. (𝐶𝑣 + 𝐶𝑝) 2. 𝐶𝑔. (𝐶𝑣 + 𝐶𝑝) + 2. 𝐶𝑠. (𝐶𝑣 + 𝐶𝑝) + 𝐶𝑠. 𝐶𝑔 (1-19)

C p is the parasitic capacitance coming from the coupling between the two extremities of the broken floating shield. The phase constant of the Tline is varying due to the variation in the total capacitance 𝐶 and then the absolute phase of S-CPW is changed. This phase shifter is working at 60 GHz and the varactors are chosen in order to obtain a maximum tuning rang (TR) and a maximum FoM.

Unfortunately, the parasitic capacitance and the varactor loss may degrade the performances of this kind of tunable S-CPW.

The second method to design a tunable Tline is with distributed MEMS. In this method, the phase tunability of the S-CPW can be achieved by controlling the distance between the CPW strips and the shielding layer, which gives the capacitance 𝐶 𝑙 . The idea is to apply a DC voltage between the shield and the CPW in order to vary the capacitance value, leading to a distributed MEMS effect.

In [START_REF] Rehder | Development of a slow-wave MEMS phase shifter on CMOS technology for millimeter wave frequencies[END_REF] a distributed MEMS phase shifter is implemented in CMOS a 0.35 µm technology by AMS. In this design, DC electrodes were added for electrostatic actuation to move the shielding plane. A post-CMOS maskless etch step is necessary to make the shielding plane mobile. Then, the distance between the CPW strips and the shielding plane are controlled via the DC voltage. If the DC voltage is applied between the shielding plane and the CPW strips, the shielding strips move up to the CPW trips. Thus, the capacitance per unit length increases, leading to phase velocity decrease. If the DC voltage is applied between the shielding plane and the bottom electrodes, the shielding plane moves far away from the CPW strips. Thus, the capacitance per unit length decreases. At 60 GHz, the TS-CPW (for Tunable S-CPW) presents a variation of permittivity from 4.5 to 58 when the position of the shielding plane is varied from 0.08 to 2 µm, and the characteristic impedance varies from 26 to 95 Ω. The length of the proposed structure is 908 µm for area less than 0.14 mm 2 . Finally, the return loss is better than 10 dB, and the insertion loss for a 360° phase shifter is 0.7 dB for a minimum quality factor (Q) of 40.

PTA technology

PTA (for ''Plateforme Technologique Amont'') is a clean room installed in Grenoble where the process to fabricate the tunable phase shifter with a classical ''bottom-up'' MEMS technology approach was developed.

On a bare glass substrate, a deposit of 350 nm of aluminum is realized by e-beam, and then the CPW strips are defined by optical lithography, Figure 1-24(a). In order to avoid short circuits during MEMS actuation, a 50-nm layer of alumina is deposited by atomic layer deposition (ALD),

CEA technology

Thanks to the partnership between CEA-LETI and IMEP-LaHC, the classical MEMS technology of CEA was used to design a tunable phase shifter based on distributed MEMS. This technology is confidential, and thus we solely present the steps of fabrication for a MEMS structure without the thicknesses and types of materials that were used.

In the beginning, the cavity where the CPW strips are deposited is defined by photolithography and etching in a high resistivity substrate. Then, the etched substrate is covered with a silicon oxide,

AMS 0.35 µm technology

The BEOL of the AustraMicroSystems AMS 0.35 μm technology is shown in The BEOL is constituted by five aluminum metallization levels, with two thick upper levels (TM1 and TM2) of 2 and 3 microns thickness, respectively. M2 and M3 levels are 0.73 μm thick,

and the lower metal level M1 has a thickness of 0.58 µm. The gap between TM1 and TM2 is 3 µm thick, whereas the gap between the other layers is 0.9 µm thick.

In 2009, in reference [START_REF] Kaynak | BEOL embedded RF-MEMS switch for mm-wave applications[END_REF], IHP presented the first BiCMOS embedded RF-MEMS switch for mm-wave applications. The M1 level was utilized to implement the high-voltage electrodes in order to move the MEMS membranes, while the capacitance switch was formed between M2 and M3 layers. M2 and M3 were used to RF signal line and membrane, respectively. On the M2 level, a thin layer stack of thin Si3N4/TiN was composed, which is a part of BiCMOS metal insulator-metal capacitor and forms the switch contact region. This configuration creates a height difference between the highvoltage electrodes and the signal line, which serves also as a stopping layer for the switch membrane. The MEMS membranes in M3 were realized using a stress compensated metallic layer Ti/TiN/AlCu/Ti/TiN.

There is also the 0.13 μm BiCMOS technology (SG13), utilized for example in [START_REF] Kaynak | Modular extension of high performance SiGe BiCMOS technologies ̶ Following the more-than-moore path[END_REF], that is composed of two more metal layers than the SG25 technology to offer more opportunities for designing passives circuits.

In the following, we will use these abbreviations SG25 and SG13 for simplicity, instead of the full name 0.25 µm BiCMOS and 0.13 µm BiCMOS, respectively.

A previous analysis in the state-of-the-art section has shown that the phase shifters based on MEMS and CMOS/BiCMOS technologies had good performances; MEMS circuits in terms of FoM and CMOS devices in terms of occupied area. Some other limitations for the original integrated approach (MEMS technology) for MEMS circuits exist: higher level of complexity for this integrated process lead to lower yields and the need of advanced packaging.

In addition, the fabrication process of a CMOS integrated circuit is much more simple and cost effective than a MEMS process.

For these reasons, a combination of these two technologies (MEMS and CMOS) can make a great revolution mostly for mm-wave applications and obtain reduction in term of size and cost.

Recently, some researcher from institutes like IHP released MEMS structures which are fabricated directly on top of standard CMOS.

The challenge of this thesis is to design novel phase shifters based on distributed-MEMS technology in the 0.25 µm BiCMOS IHP's technology.

Conclusion

This chapter has presented an overview of phase shifters designed with different topologies and technologies, and some applications, followed by a state-of-the-art review for passive mmwave phase shifters. With regards to the transmission lines based on slow-wave effect, characteristics and electrical model of tunable slow-wave transmission lines have been explained throughout the chapter.

In chapter 2, after an overview about the RF MEMS switches, previous designs of tunable transmission line using MEMS and CMOS technologies will be presented. Then, the proposed solution using MEMS technology with a post-CMOS process will be detailed.

Chapter 2

Design of tunable slow-wave coplanar waveguides (TS-CPWs) based on distributed MEMS

Various topologies and applications of tunable phase-shifters have been described in chapter

1. An innovative solution, based on tunable slow-wave transmission lines with distributed MEMS, in integrated technologies, has been proposed. It should enable to further design a tunable N-bits phase shifter whose design and topology will be considered in chapter3.

This chapter 2 is devoted to deeper detail the design of TS-CPWs in a CMOS technology. First, a brief presentation of RF-MEMS switches theory including their types and operating principle is performed. This theoretical study is necessary to establish the preliminary basis for designing the TS-CPWs. Next, previous TS-CPWs topologies at IMEP-LaHC in MEMS technologies are presented. Then, the optimization of the tunable transmission lines through an electromagnetic simulation step is described. The impact of each physical dimension is studied.

2.1.RF-MEMS switches: types and operating principle

MEMS for "Micro-Electro-Mechanical System" refers to the deformable electrical micrometric systems which uses a mechanical movement to perform an electrical function. The idea was validated in 1967 [1] by producing the first MOS transistor with mechanically moving gate. This gate was like a suspended electrode whose movement could modulate the current.

A few years later, this coupling between electrical and mechanical components was demonstrated in the microwave field. In 1979 [2], the first MEMS component for communication applications has emerged and thus a new technology "Radio Frequency Micro-Electro-Mechanical Systems" (RF-MEMS) was developed.

There are two main types of RF-MEMS switches: capacitive switches (metal-dielectric contact) and ohmic switches (metal-metal contact). In both types, there is a movable structure where a force is applied to move the MEMS membrane in order to achieve the electrical function.

This applied force can be magnetic [3], thermal [4] or electrostatic. In the latter case, it is derived from the electric potential difference applied between the movable membrane and the activation electrode.

The behavior of RF-MEMS ohmic switches is similar to that of an interrupter (switch); it has a metal contact between the input and the output of the component in the actuated state. Figure 2-1 illustrates the operating principle. In the off state, the membrane does not contact the output, hence no transmission of the RF signal can be observed. However, a capacitance 𝐶 𝑜𝑓𝑓 is considered between the membrane and the output. When the voltage is applied to the activation electrode, an electrostatic field is created, which enables the membrane to move down (on-state). The metal-metal contact connects the input to the output and the signal is transmitted via a contact resistor (𝑅 𝑜𝑛 ) of a few ohms. A classical figure-of-merit to characterize an ohmic switch is the product 𝑅 𝑜𝑛 𝐶 𝑜𝑓𝑓 (in seconds).

RF-MEMS capacitive switches use a thin dielectric layer to create a component that will be a variable capacitor that can take two possible values between the input and the output (see As for ohmic contacts, in the off-state, the membrane does not contact the output. The capacitance 𝐶 𝑜𝑓𝑓 has a low value that does not enable the transmission of the RF signal. This capacitance is increased in the on-state, the signal is transmitted via a capacitive contact metaldielectric-metal (𝐶 𝑜𝑛 with 𝐶 𝑜𝑛 >>𝐶 𝑜𝑓𝑓 ). A classical figure of merit to compare various capacitive switches is given by the ratio 𝐶 𝑜𝑛 /𝐶 𝑜𝑓𝑓 .

As it will be explained later in this chapter, the solution with distributed MEMS is based on a capacitive contact to avoid shunting the RF signal to ground.

Introduction

RF-MEMS switches are generally composed of a movable metallic membrane. Hence the most prevalent method for applying forces to deformable elements in microsystems is seemingly the electrostatic actuation.

Operating principle

The electrostatic actuation of RF-MEMS is generally comparable to that of a simple mechanical system of plate-ressort. The movable membrane is similar to a mass/spring system located on top of a fixed metal electrode. This electrode enables to generate an electrostatic field due to an electric potential difference between both, which creates an attractive force on the membrane enabling to change its position [5]. In order to approximate this force, the electrode is modeled as a parallel plate capacitance. The model of the electrostatic actuator is shown in Given that the length of the actuation electrode is 𝑤 𝑒 and the width of the pull-down electrode is 𝑊, the parallel plate capacitance is given in eq. (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19).

𝐶 = 𝜀 0 . 𝐴 𝑔 = 𝜀 0 . 𝑊. 𝑤 𝑒 𝑔 (2-1)
where 𝑔 is the gap between the membrane and the electrode and 𝜀 0 the vacuum permittivity.

The electrostatic force (𝐹 𝑒 ) applied to the membrane is found by considering the power delivered to the capacitance and is given by eq. (2-2) [5].

𝐹 𝑒 = 1 2 𝑉 2 𝑑𝐶(𝑔) 𝑑𝑔 = - 1 2 𝜀 0 . 𝑊. 𝑤 𝑒 . 𝑉 2 𝑔 2 (2-2)
where 𝑉 is the applied voltage between the membrane and the electrode. In the capacitive MEMS case, a dielectric layer is located above the actuation electrode; such layer is not considered in Figure 23. Thus its effect is neglected in eq. (2-2). In addition, it is considered that the electrostatic force is evenly distributed across the section of membrane above the electrode.

The mechanical restoring force (𝐹) due to the stiffness of the membrane depends on the displacement of the membrane during the actuation and the spring constant associated with the membrane material and dimensions, see eq. (2)(3).

𝐹 = 𝐾. (𝑔 -𝑔 0 ), (2-3)
where 𝑔 0 is the zero-bias bridge gap. Weighting force is totally negligible with respect to restoring force. Hence, when the system is well-balanced, the electrostatic force (𝐹 𝑒 ) and the mechanical restoring force (𝐹) are equal, leading to eq. (2-4) and (2-5) [5]. The restoring force varies linearly with the gap while the electrostatic force varies nonlinearly with gap and bias voltage. Both forces are getting higher when g reduces. There is no compensating phenomenon. From eq. (2-5) it can be seen that the relationship between V and g is non-linear. Figure 234shows the evolution of the gap with the applied voltage, and identifies the region of instability when a third of the gap height (g = 2 3 g 0 ) is achieved [5]. This value can be determined very easily firstly by calculating dg/dV and then identifying the position for which this derivative becomes infinite, hence leading to instability. This derivation is performed from eq. (2-6) to (2-10), as mentioned below. So the minimum applied voltage 𝑉 𝑝 needed to move down the membrane and achieve contact is given by eq. (2)(3)(4)(5)(6)(7)(8)(9)(10)(11). The pull-in instability produces some difficulties in some special design (i.e. comb-drives, charge actuation [6]) and operation modes, but it is used in other applications to achieve a fast transition between two states of an electromechanical switch [6].

𝑉 𝑝 = 𝑉( 2 3 ⁄ 𝑔 0 ) = √ 8. 𝐾 27. 𝜀 0 . 𝑊. 𝑤 𝑒 𝑔 0
An RF-MEMS component actuated with an electrostatic force can be exposed to several types of failure. First type is electrical such as the dielectric failure (breakdown due to ESD: Electro Static Discharge or EOD: Electrical Overstress), [8], and failure due to injection and charge trapping, which causes the deterioration of capacitive RF-MEMS due to the electronic conduction mechanism in the dielectric [9]. Second type is mechanical, and can be due to deformation with the apparition of a mechanical stress after the actuation step; it can be due as well to plots deterioration in the case of ohmic RF-MEMS. Another kind of mechanical failure is the creep phenomenon that can be accelerated with temperature. It is present probably in all RF-MEMS structures. There are also failures due to high microwave power [12], thermal effects [13], and external environment [14].

2.2.Tunable Slow Wave CoPlanar Waveguide (TS-CPW) with distributed MEMS in IHP 0.25 µm BiCMOS technology

Before designing TS-CPWs based on distributed MEMS in IHP's 0.25 µm BiCMOS technology (SG25), a study was necessary in order to find the best design for the classical S-CPW in SG25

that will be used to perform high-performance TS-CPW. The S-CPW concept was already detailed in chapter 1. We just remind here that loading a conventional CPW with shielding ribbons leads to the increase of the capacitance, enabling slow-wave effect. This shielding layer can be realized above or below the strips of the conventional CPW.

.

By comparing the topologies of the S-CPW and the RF-MEMS switch, M3 can be chosen to realize the tunable shielding layer in the TS-CPW [START_REF] Rehder | Development of a slow-wave MEMS phase shifter on CMOS technology for millimeter wave frequencies[END_REF], such as the movable membrane in the RF-MEMS switch.

There are many possibilities to choose the appropriate metallic layer for the CPW strips. M1

has the lowest thickness with respect to the others layers, and would lead to high metallic losses.

The suitable layer must be chosen among M2, TM1 and TM2.

The geometrical parameters of a classical S-CPW are:

• Parameters linked with CPW Usually 𝑆𝑆 and 𝑆L are given by the minimum width allowed by the DRM (Design Rule Manuel), 0.5 µm for each. Here, the floating shield will be actuated. For precaution, we preferred fixing 𝑆𝑆=𝑆L = 1 µm .

The dimensions of the CPW (𝑊, 𝑊 𝑔 , 𝐺) allow to determine the characteristic impedance.  𝑒𝑓𝑓 depends on the capacitance per unit length 𝐶 𝑙 , which is not the same in the four cases. M2 has the smaller thickness layer among M2, TM1, TM2 and TM1-TM2 stack. This small thickness of M2 which is also the closer layer to the lossy doped silicon substrate, leads to higher dielectric losses and decreases the quality factor of the S-CPWs built in this layer.

The gaps between the substrate and TM1 and TM2 are 9.38 µm and 12.3 µm, respectively. As shown in Figure 234567, whatever the stack is, a good quality factor can be obtained with an optimal value of 𝑍 𝐶 . The maximum attenuation constant in TM2 is less than 1 dB, which gives a minimum quality factor better than the quality factor of the other lower layers due its high thickness and its distance from the lossy substrate.

When comparing TM1 and TM1-TM2 stack, losses are in favor of TM1-TM2. This is due to the stack higher thickness. Meanwhile the effective permittivities are quite similar, which leads to a better quality factor for TM1-TM2. A comparison between TM1 and TM2 alone imply a compromise between lower losses for TM2 (less proximity effect and higher thickness) but higher effective permittivity for TM1 (nearer to M3). The compromise leads to a better quality factor for TM2. Finally, even if the effective permittivity is higher for TM1-TM2 stack than for TM2 alone, due to the proximity with M3, the quality factor is highest for TM2 alone.

Fabrication priorities and specifications

Two priorities should be followed in practice for fabrication purposes:

• Etching release until M2, M2 included,

• Dimensions of the released floating strips not exceeding 200 µm; over length has to be a fixed part encapsulated with dielectric.

The previous study demonstrates that best performances for S-CPWs are obtained for CPW strips in the TM2. However, to release the TS-CPW structure a post etching process of the dielectric is necessary. When the CPW strips are on top of the membranes, the risk is high to have them movable too after etching, even with periodic pillar to support them. Therefore, the configuration in Figure 2-6 (a) has been chosen even if less promising in terms of quality factor.

Finally, the TS-CPW topology is presented in Figure 2 The high voltage electrode is realized in M1 below the CPW strips, as for IHP's capacitive switch [START_REF] Kaynak | BEOL embedded RF-MEMS switch for mm-wave applications[END_REF], in order to have the floating membrane moving after applying a voltage. The minimum voltage needed to move the membrane depend on its size and the size of electrodes, as for RF-MEMS switches.

Figure 2-9 shows the cross sectional view of TS-CPW before actuation (off-state). The etching of the dielectric (SiO2) is processed up to Metal 2. Hence the central part of the movable membrane of length (𝑙) has been kept in air in order to allow capacitance variation, while the ground strips and the electrodes are totally embedded in dielectric. Embedding the ground strips and the floating membrane part over ground strips enable to reduce the released membrane length as recommended (see priorities). A longer release would be convenient for a higher on/off capacitance ratio with a strong signal strip capacitance in series with two strong ground strips capacitances, but the risk would be high to get a weak spring effect and no tunability at all. On the contrary, the movable membrane is fixed on each side with SiO2.

The supplementary parameters used in Figure 2-9 as compared to Figure 2-5 (c) are listed below:

• 𝑙: length of movable membranecorresponding to the etched zone

• 𝐺 1 : air gap between signal and oxide

• 𝐺 2 : oxide gap between air and ground strip

• 𝐺 = 𝐺 1 + 𝐺 2 : gap between signal and ground strips

• 𝑔: gap between membrane and actuation electrode

• 𝑤 𝑒 : width of actuation electrode A thin layer of TiN, with dielectric specification, takes place above the aluminum of the CPW strips in order to prevent the metal-metal contact (short circuit) that would lead to the destruction of the component during actuation. It is not shown in Figure 23456789.

Figure 2-10 shows the cross sectional view of the same TS-CPW after actuation (on-state).

The application of a DC bias voltage between the membrane and the electrode leads to moving the membrane in the etching zone near to the central strip of the CPW thanks to the electrostatic force. Therefore, the gap between the membrane and the signal decreases and creates a variation in the capacitance formed between membrane and signal strip. The gap after actuation is equal to of few nm of air [START_REF] Kaynak | BEOL embedded RF-MEMS switch for mm-wave applications[END_REF].

Capacitances overview

For better understanding, Figure 2-11 presents a simple model of the capacitances formed between membrane and CPW strips. Capacitance 𝐶 𝑔 is formed between CPW ground strips and membrane, all embedded in dioxide. 𝐶 𝑔 does not vary with actuation. The variable capacitance is 𝐶 𝑆 , which is formed between CPW signal strip and the movable part of the membrane. Dielectric is air after etching. The expression of this variable parallel plate capacitance 𝐶 𝑆 is given in eq.

(2-12). 𝐶 𝑠 = 𝜀 0 . 𝜀 𝑟 . 𝐴 ℎ

(2-12)
where 𝐴 is the area (𝐴 = 𝑊. 𝑆𝐿) and ℎ is the variable gap between movable membrane and signal strip. ℎ is changed from 900 nm for off-state to a few nm (≈11 nm) for on-state.

In practical cases, the electrical model for capacitance is composed of the parallel plate capacitances and fringing capacitances which are around 30 % of the global capacitance. The parasitic capacitances can be calculated and determined using electromagnetic software like HFSS. This will be detailed in chapter 3 dedicated to phase shifters. As for RF-MEMS previously presented in section 2.1, an electrostatic actuator is used to actuate the TS-CPW. Figure 2-12 shows the model of the electrostatic actuator for TS-CPW.

The minimum applied voltage (𝑉 𝑝 ) to actuate the movable membrane of TS-CPW is given by eq. (2-13). The force must be evenly distributed over the center portion of the movable membrane fixed at both ends in the oxide. For this case the spring constant can be calculated by eq. (2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14).

𝑉 where 𝑆𝐿 is the width of the movable membrane, 𝑙 is the moving part of the membrane placed in the etching zone, as shown in Figure 2 From Table 2-2, we observe that the length of the movable membrane and the width of the actuation electrode are very important parameters to play with in order to reduce 𝑉 𝑝 . In practical cases, we cannot increase greatly 𝑙 in order to avoid mechanical failures. From the electromagnetic point of view, the electrode is placed below the signal strip, so it is possible to strongly disturb the propagation by increasing greatly 𝑤 𝑒 . We can note that the SiO2 between the In section 2.2.3, we already saw that the length of the membrane is a very important parameter to consider in order to decrease the minimum applied voltage needed to make the membrane movable but with the priority of not exceeding 200 µm long. Two studies were carried out with respect to 160 µm of 𝑙 corresponding to the etched zone, at various frequencies and for various signal widths. The other parameters were let fixed. In this section devoted to theoretical simulations only, we explain the dependency of the electrical parameters in two ways:

• versus the signal width 𝑊 when 𝑙 = 160 µm, at 60 GHz; other geometrical parameters are fixed

• versus frequency when 𝑙 = 160 µm; all the geometrical parameters are fixed.

Simulation set 1 with 𝒍 = 160 µm; signal width varies

The fixed dimensions of the simulated TS-CPW are presented in Table 2-3. Here, 𝑙 was fixed to 160 µm. The signal width 𝑊 and the gap 𝐺 and 𝐺1 are variable. As expected, the characteristic impedance decreases with the width of the CPW signal strip.

The capacitance is higher in the on-state than in the off-state. Consequently, as shown in Figure 2-15 (a), the characteristic impedance is lower in the on-state. For the same reason, the effective permittivity is five to six times higher in the on-state. Unfortunately, due to proximity effect, the attenuation constant is higher in the on-state, about three times higher. Therefore, the quality factor is slightly lower for the on-state than for the off-state. For strip widths above 10 µm, both quality factors are superior to 20, which is a value near the state-of-the-art for integrated transmission lines in CMOS BEOL. The highest 𝑄 are reached with 30 µm of width (the maximum allowed by the technology) but they correspond to low characteristic impedances. Therefore, we choose a configuration for 𝑊 equal to 20 µm to present the electrical characteristics versus frequency in the next section.

Simulation set 2 with 𝒍 = 160 µm, frequency varies

After the parametric study of the previous section, another example of simulation is shown.

The fixed dimensions of the simulated TS-CPW are presented in From Figure 2-16 (a), the values of the characteristic impedances from ≈68 Ω in the off-state to ≈30 Ω in the on-state guaranty a return loss better than 10 dB in the whole frequency range.

The average impedance of TS-CPW, defined as √ 𝑍 𝑐_𝑜𝑛 . 𝑍 𝑐_𝑜𝑓𝑓 , is around 45 Ω. The effective permittivity is 4.5 times greater in the on-state than in the off-state, so that we can expect an on/off ratio a little higher than 2. The quality factor is varying between 13 at 10 GHz and 23 at 80 GHz in the on-state and from 12 at 10 GHz to 27 at 80 GHz in the off-state. It is better than 20 at 60 GHz.

As a consequence of the high variation of the effective permittivity between the off-and onstates, the electrical length of the TS-CPW will change as well. For this example, the electrical length is changed from 110° in off-state to 240° in on-state with 345 µm of physical length. This variation of the electrical length is named phase shift which can lead to design a phase shifter.

Various phase shifters were designed and fabricated in IHP's SG25. They will be presented in chapter 3.

2.3.Previous works

In The tunable transmission line presented here is formed by a classical S-CPW as presented in [17], where the metallic ribbons that form the floating shielding are supported by another membrane that allows motion when a bias voltage is applied. The application of a DC voltage between the CPW strips and the shielding strips causes the membrane with shielding plane to move towards the CPW strips, due to the electrostatic force. Thus, the capacitance per unit length increases, reducing phase velocity, as explained in [18]. This TS-CPW was designed on a high resistivity silicon substrate. In this topology, we do not need an electrode to activate the shielding strips because the strips of the CPW are used as electrodes. Then when this TS-CPW is measured, DC ground is connected to RF ground and the high voltage is applied onto the membrane.

As in the previous technologies, this proposed TS-CPW was fabricated within a commercial The actuation of the shielding layer is done via a DC voltage applied to the CPW strips while this shielding layer is DC grounded. In addition, mechanical stoppers are used to prevent a short circuit between the actuated membranes and the CPW strips.

2.4.Conclusion

Table 2-5 gathers the physical parameters and performances of the simulated and sent to fabrication TS-CPWs in the 0.25 µm BiCMOS technology of IHP at 60 GHz. Note that the minimum activation voltage is around 32 V for this configuration. where the slow-wave effect leads to very interesting characteristics in terms of quality factor and longitudinal length reduction. The TS-CPW is based on distributed MEMS. Electromagnetic simulations were done in order to extract the electrical characteristics and follow their evolution with the variation of the geometrical dimensions and frequency. Besides, the design methodology of the TS-CPW in IHP's BiCMOS technology was described in details. The transmission line measurements, either at off-state or on-state, will be detailed in the last chapter.

Chapter 3

Design of digital phase shifters

In chapter 1, a review of the existing technologies for tunability, i.e. ferroelectrics [START_REF] Vel | A 310°/3.6-dB K-band phaseshifter using paraelectric BST thin films[END_REF], liquid crystal [2], MOS [START_REF] Vadivelu | Integrated CMOS mm-wave phase shifters for single chip portable radar[END_REF] and MEMS [4], was presented. It was concluded that MEMS and CMOS technologies lead to the highest Figure of Merit and the lowest surface area, respectively.

Also, several topologies of passive phase shifters are available, i.e. reflection type [5],

switched line [6] and loaded line [START_REF] Bautista | Accurate Parametric Electrical Model for Slow-Wave CPW and Application to Circuits Design[END_REF]. A new topology of tunable coplanar waveguide [START_REF] Rehder | Tunable High-Frequency Transmission Line[END_REF]- [START_REF] Rehder | Ligne de transmission haute fréquence accordable[END_REF] based on distributed MEMS was presented in chapter 1 and chapter 2. In this chapter, a loaded line phase shifter is studied. It is based on MEMS-based TS-CPWs.

First, earlier N-bit phase shifters in MEMS technology, designed at IMEP-LaHC in collaboration with other institutes, and tested during my PhD, are presented. Then several phase shifters designed by myself are studied, with different degrees of maturity. First, a 1-bit phase shifter is studied, which uses the TS-CPWs designed in chapter 2. Then, the design methodology of an N-bit phase shifter with N commands is described in sections 3.3 and 3.4.

3.1.Previous Work

This thesis work is based on two patents [START_REF] Rehder | Tunable High-Frequency Transmission Line[END_REF], [START_REF] Rehder | Ligne de transmission haute fréquence accordable[END_REF] and some previous work, i.e. clean room technology (PTA), CEA technology and AMS technology. These technologies have been described in chapter 1 (section 1.5). In previous works, phase shifters were developed in several technologies and were based on distributed MEMS S-CPWs. In this section, a brief description of previous phase shifter designs is presented in order to understand the improvements that were carried out during my thesis. The measurement results of these phase shifters are presented in chapter 4 dedicated to measurement results.

A digital phase shifter was designed and fabricated [10]. The structure of this phase shifter is shown in Figure 3-1. This phase shifter is constituted of only 4 groups. All groups have the same length and each group is connected to one pad. So, there are 4 digital commands, which lead theoretically to 16 states of phase. However there are 11 redundant states due to the symmetry of the structure. For instance, states 0001 and 1000 give exactly the same phase shift, and states 0001, 0010, 0100 and 1000 give almost the same phase shift (small differences are due to standing wave effect that differ from one state to another). Finally, this phase shifter has only 5 different states: at rest (state 0000); when only the first group is actuated (state 0001); when first and second groups are actuated (state 0011); when the three groups are actuated (state 0111) and when all groups are actuated (state 1111). It behaves like a thermometer. This phase shifter was designed to achieve 135° of phase shift at 60 GHz technology [11]. The shielding ribbons of the S-CPW were divided in groups that can be actuated independently. Ideally, to obtain n-bits of resolution the shielding ribbons should be distributed into 2^n groups. However, the phase shift is not linear with respect to the length of each group, because of the different characteristic impedances shown between actuated and unactuated sections leading to standing waves formation and hence a non-linear phase variation. Therefore, in this first design, even if 128 phase shift positions were obtained with the use of 7 groups, corresponding to 7 commands, this phase-shifter is only a 3-bit one enabling to achieve 8 very precise phase shift steps given by the number of bits. Anyway, many phase shift steps occur between the latter's, and can be used in practice.

The Bragg effect must be considered when designing the phase shifter, since a periodic-like high-low characteristic impedance structure may appear for certain states. In order to minimize the Bragg effect, the groups were subdivided in eight interlaced sections, as exemplified in This phase shifter was designed to achieve a maximum phase shift of 152°. The phase shift resolution between two successive states is around 21°.

In this technology, a 2-bit phase shifter was designed [12]. The proposed phase shifter is constituted of 3 groups of membranes in order to achieve 2 bits of resolution. Normally This phase shifter was designed to have a maximum phase shift of 45° at 60 GHz. It has 4

different states: at rest (state 00); a smallest phase shift is achieved with the actuation of only one group (Group1: state 01); the next phase state is obtained with the actuation of two groups (Group 1 and Group 2: state 10) and the maximum phase state is obtained with all three groups actuated (Group 1, Group 2 and Group 3: state 11).

3.2.TS-CPW as a 1-bit phase shifter

As explained in previous chapters, the use of a slow-wave approach allows shrinking the transmission line size by increasing the effective dielectric constant, which finally enhances its quality factor.

As discussed in chapter 2 also, the TS-CPW is composed of a conventional CPW loaded by a patterned shield, which is electrically controlled via a bias voltage in order to change the characteristics of the TS-CPW. In IHP's SG25 this shield is implemented over the CPW strips. When moving from off-state to on-state by applying a bias, the electrical length of the TS-CPW is changing as well. We can define a phase for each state: 𝜑 𝑜𝑓𝑓 and 𝜑 𝑜𝑛 (see eq. (3-1) and (3-2)).

The difference between these two phases is called phase shift (𝛥𝜑) (see eq. (3-3) to (3)(4)(5)(6)).

Therefore, the TS-CPW is working as a 1-bit phase shifter because it has only two states, i.e. offand on-.

𝜑 𝑜𝑓𝑓 = 𝛽 𝑜𝑓𝑓 . 𝑙

3.3.Phase shifter (N bit/N commands): design1

The idea, as for the CEA based phase shifter, consists in combining the ribbons in several groups as shown in Figure 3-6, and to develop in main time a design methodology that permits to reduce the number of commands to the number of bits, i.e. an N-bit phase shifter with only N commands.

For this purpose, the design procedure consists in optimizing the number of ribbons in each group. As an example, Figure 3-6 shows the TS-CPW as a succession of n similar groups. The distance between two successive groups is equal to 𝑆𝑆 to maintain the same slow-wave effect along the entire length of the TS-CPW. The way to optimize the number and the size of groups is described in section 3.1.7.

Before describing the design methodology, it is important to clearly define group and segment definitions.

Group definition

As discussed above, the ribbons will be combined in several groups. A small study in this subsection is presented to find the right shape forming the groups. In first shape (Figure 3-7 (a)), the two strips of width 2 µm, the ones that force a same potential for all the ribbons of a same group, are fixed in the oxide, letting a long moveable part of ribbons. Hence the group of ribbons lacks rigidity. The second shape is shown in Figure 34567(b). Here, we force the ribbons to a unique potential with many strips of width 1 µm, which also enable to stiffen the structure. The electrical characteristics of the simulated TS-CPW for the two shapes in off-state are given in Table 3-1. From calculated values of inductance and capacitance per unit length, we can determine the characteristic impedance (Z c = √L/C) and effective permittivity (𝜀 𝑟𝑒𝑓𝑓 = 𝐶 0 2 • 𝐿 • 𝐶), given in shape 1, as the stiffening strips slightly prevent the magnetic field from circulating.

Consequently the corresponding characteristic impedance and effective permittivity are lower.

What's more, shape 2 offers much possibilities for eddy current losses, hence leading to a much lower quality factor as compared to shape 1.

Shape 3 (Figure 3-7(c)) was proposed to overcome the problem of high eddy currents of shape 2 and low rigidity of shape 1. The electrical performance is almost the same as shape 1.

However, shape 3 is more rigid in the etching zone as compared to shape 1.

So, the final definition for group is: a set of ribbons spaced 1 µm from each other. These ribbons are connected by two metal strips of width 2 µm placed in the moveable part of group. Its size is variable and depends on the number of ribbons. Note that the length of the group will always be equal to an odd value or it can be null.

Segment definition

The segment is constituted of a set of groups, as shown in It is important to note that all first groups of each segment are connected to the same DC command. In other words, first group of segment 1 is connected to first group of segment 2 up to segment p. That does not mean that group 1 of segment 1 has the same number of ribbons than group 1 of segment 2 or segment p. This is just a question of DC command. On the contrary, each length of each group is optimized for the best final linearity between phase shift states. In step 1, the dimensions of the TS-CPW and their respective metal layers are fixed. This step was described in chapter 2. The electrodes, the CPW strips and the moveable ribbons were implemented in Metal 1, Metal 2 and Metal 3, respectively, as described in section 2.2 chapter 2.

Table 3-2 summarizes the dimensions of the used TS-CPW. In step 2, 𝛽 𝑜𝑓𝑓 and 𝛽 𝑜𝑛 are extracted for a particular frequency, from HFSS simulations of off-and on-states of small sections of TS-CPW (for example 150 µm of length). Also, the difference 𝛥𝛽 between 𝛽 𝑜𝑓𝑓 and 𝛽 𝑜𝑛 is calculated in this step in order to determine the physical length of the phase shifter corresponding to the desired phase shift. For example, a 60 GHz phase shifter with a total phase shift of 𝛥𝜑 =157.5° leads to 𝛥𝛽 = 7963,7 rad/mm, leading to a physical length equal to 345 µm.

In step 3, the parameters of the phase shifter are defined: number of segments (p), number of bits (N) and number of individual ribbons for each group that is to say the length of each group, to be chosen among a certain number of possible lengths (m in total). For example: p=5 segments were used to design a 3-bit phase shifter. This means N=3 groups maximum in a segment (N-bits / N-commands). Eventually one group may have no ribbon at all (length of 0 µm). As a matter of fact, the number of groups in the corresponding segment will be less than 3. As a general rule for optimization, a group length can only show odd values varying from 9 µm to 39 µm with a step of 2 µm. Thus, the number of possible lengths for each group is m=17 i.e. 0, 9,11,13,15,17,19,[START_REF] Liu | BaSrTiO interdigitated capacitors for distributed phaseshifter applications[END_REF][START_REF] De Paolis | Characterization of ferroelectric BST MIM capacitors up to 65 GHz for a compact phase shifter at 60 GHz[END_REF][START_REF] Kozyrev | Ferroelectric (Ba,Sr)TiO thin-film 60-GHz phase shifter[END_REF][START_REF] Yashchyshyn | Tunable ferroelectric ceramic-polymer composites for sub-THz applications[END_REF][START_REF] Bulja | Liquid crystal based phase shifters in 60 GHz band[END_REF][START_REF] Deo | Development of 60 GHz phased antenna arrays using liquid crystal phase-shifters[END_REF][START_REF] Mueller | Tunable passive phase shifter for microwave applications using highly anisotropic liquid crystals[END_REF][START_REF] Mueller | Passive tunable liquid crystal finline phase shifter for millimeter waves[END_REF][START_REF] Young | A 4-bit Passive Phase Shifter for Automotive Radar Applications in 0.13 µm CMOS[END_REF][START_REF] Ellinger | Passive varactor tuned equivalent transmission line phase shifter at C-band in 0.25 μm BiCMOS[END_REF]. In step 4, the optimal dimension of each group in each segment is determined. Figure 3-10

shows the sub-steps of step 4. Firstly, one segment is generated with all possibilities of groups lengths (𝑚 𝑁 combinations available). For example, for a 3-bit phase shifter: 17 possible lengths for a group and 3 possible groups in a segment lead to 17 3 combinations for one segment. Then, the combination of one segment is repeated 𝑝 times to generate all segments (remember that the number of segments 𝑝 is fixed by the designer). So there are (𝑚 𝑁 ) 𝑝 segments possible, hence (17 3 ) 5 possibilities. Next, in order to find the maximum of possibilities we classify the total segments according the total length of phase shifter calculate in step 3 with condition 𝑙 𝑚𝑖𝑛 < 𝑙 < 𝑙 𝑚𝑎𝑥 . 𝑙 𝑚𝑖𝑛 and 𝑙 𝑚𝑎𝑥 are chosen close to the exact value of 𝑙 (with error value of 3%) . For example, for the length 345 µ𝑚 , we put condition 335 µ𝑚 < 𝑙 < 355 µ𝑚. After this sub-step, the possibilities (solutions) leading to physical lengths close to 𝑙 are known. Also, the corresponding lengths for each group per segment are known. Then, the ABCD matrix for all valuable combinations is calculated by cascading the ABCD matrix of each group already calculated during HFSS process, as shown in Figure 3-9 and eq.(3-7). Eq (3-7) corresponds to the case of 5 segments of 3 groups maximum each. Then the corresponding S parameters are calculated, followed by the calculation of phase 𝜑 ℎ of the h th state of the N-bit phase shifter for all combinations. Then the overall phase shifts 𝛥𝜑 ℎ between the first state 𝜑 0 , which is the off-state, and the last state 𝜑 2 𝑁 -1 (see eq. (3-9)) are calculated.

Note that ℎ varies from zero to 2 𝑁 -1. The input return loss is calculated as well as it can also make good criteria of discrimination.

[𝐴𝐵𝐶𝐷] 𝑖𝑗𝑘 =

[𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 1] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 2] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 3] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 4] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 5] 𝑖𝑗𝑘 (3-7)
with

[𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑖𝑗𝑘 = [𝐴𝐵𝐶𝐷 𝑔𝑟𝑜𝑢𝑝 1 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑖 * [𝐴𝐵𝐶𝐷 𝑔𝑟𝑜𝑢𝑝 2 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑗 * [𝐴𝐵𝐶𝐷 𝑔𝑟𝑜𝑢𝑝 3 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑘
with i=0 or 1 / j=0 or 1 and k=0 or 1, 0 is for off-state and 1 for on-state. where, 𝜑 000 and 𝜑 111 are the phases when no group is actuated and all groups are actuated, respectively. The rest of the intermediate states are expected to vary linearly.

Then, from eq. (3-10) we can calculate the phase shift errors 𝐸 ℎ for each state in all possibilities and we deduce the total quadratic errors 𝑒 with eq. (3)(4)(5)(6)(7)(8)(9)(10)(11)(12):

𝐸 ℎ = 𝛥𝜑 ℎ -(ℎ. 𝛿𝜑) (3-10)
where 𝛿𝜑 = 𝛥𝜑 2 𝑁 -1

(3-11) 𝑒 = √∑ 𝐸 ℎ 2 (3-12)
where 𝛿𝜑 given in eq. (3)(4)(5)(6)(7)(8)(9)(10)(11) is the phase shift step to reach linear intermediate phases. For example for 3-bit phase shifter with 157.5°of maximum phase shift, 𝛿𝜑 is equal to 22.5°. Then, the errors for each state are calculated as follows:

𝐸 000 = 𝛥𝜑 000 -0°

𝐸 001 = 𝛥𝜑 001 -22.5°

𝐸 010 = 𝛥𝜑 010 -45°

𝐸 011 = 𝛥𝜑 011 -67.5°

𝐸 100 = 𝛥𝜑 100 -90° The final sub-step in step 4 is the selection of the best combination: the one that fits the total targeted length and that gives the minimum error for the 3-bit phase shifter. With 5 segments for a 3-bit phase shifter, the best combination is shown in Figure 3-11. The last segment has a length of 37 µm, leading to a total physical length of 345 µm. Note that we performed some mistakes in this first design by forgetting the space length between groups in MATLAB computation (for MATLAB, the total length was 335 µm). The phase shift for the 8 states of this combination and their corresponding errors are given in Table 3-3. From Table 3-3, it can be seen that the maximum phase shift error is 5° for state 110.

In step 5, the best combination determined in step 4 is simulated in HFSS. The validation step is presented in section 3.1.9.

Before the validation step, a 315° 3-bit phase shifter was designed, with a simple idea of cascading two 157.5° 3-bit phase shifters. Note that combining two 157.5° 3-bit phase shifters leads to twice the phase shift error, leading to a -10° of error for state 110. As shown in Figure 3-13 (a), an insertion loss of 2 dB is obtained at 60 GHz for 151° of phase shift. The insertion loss has a maximum variation of only 1.6 dB. The return loss is better than 8 dB for off-and on-states. By comparing the phase shift obtained by HFSS simulation with MATLAB algorithm in Figure 3-13(d), it can be seen that the total phase shift 𝜟𝝋 𝟏𝟏𝟏 is in a good agreement (151° for HFSS and 155° for MATLAB). But this is not the case for the other states, i.e.

𝜟𝝋 𝟎𝟎𝟏 to 𝜟𝝋 𝟏𝟏𝟎 . This difference in HFSS simulation is due to the fact that there exist geometric discontinuities when cascading on-and off-groups consecutively. This discontinuity is taken into account by HFSS simulator in all states but not in MATLAB algorithm. We note that the characteristic impedances vary from ≈68 Ω in the off-state to ≈30 Ω in the on-state. This is the guaranty for a return loss better than 10 dB in the whole frequency range. The average impedance for the phase shifter, defined as √ 𝒁 𝒄_𝒐𝒏 . 𝒁 𝒄_𝒐𝒇𝒇 , is around 45 Ω.

Same analysis can be carried out for the 315° 3-bit phase shifter. As mentioned in section 3.1.8, this phase shifter is designed by cascading two 157.5° phase shifters, so the mismatch between HFSS and MATLAB algorithm is even higher for states 001 to 110. In Figure 3-14, the insertion loss, return loss and phase of off-and on-states are presented. As shown in Figure 3-14, the insertion loss is 0.7 dB and 2.2 dB at 60 GHz for off-and onstates, respectively. The return loss is as low as 7 dB for the worst case. This is an issue that was addressed in an optimized design described in the next section, whereas the total phase shift at 60 GHz is approximately the same for MATLAB algorithm and HFSS simulation.

This phase shifter with and without the additional bit for error correction was sent to fabrication in March 2014 before the validation in HFSS.

3.4.Optimized Phase shifter: design 2

In step 4 in the design methodology in section 3.1.7, we did not consider the space (1 µm) between two groups, neither the transition effect when we cascaded the ABCD matrices. This transition between two successive groups does not have a high effect when the phase shifter has the same state throughout the transmission line, i.e. off-state (all groups not actuated) and onstate (all groups actuated). Never-the-less this transition or discontinuity has a great effect when successive groups do not have the same state (i.e. the consecutive groups are on and off). We can deduce that we have four transitions possible: off-off, off-on, on-off and on-on transitions. The problem occurs in the off-on and on-off transitions. The ABCD matrices of these transitions were taken into account in the new calculation in the developed MATLAB algorithm. with i=0 or 1 / j=0 or 1 and k=0 or 1, 0 is for off-state and 1 for on-state. When s=5, there is no final transition.

Before starting the design and optimization of this 'second round' 3 bit phase shifter, an important issue to be considered was the rigidity of the distributed MEMS which is presented in chapter 4, as any mechanical or electrical characterization. With 'first round' of measurement, we remarked that, within a segment, if the adjacent groups were not in the same on-or offposition, for example in state 010 the actuated second group disturbs the adjacent first and third groups in off-position. This problem exists for all intermediate states, i.e. from 001 to 110. Due to this reason 'first round' measurements could only be performed for states 000 and 111. To make this design more rigid, the side walls of each membrane (i.e. the inner and outer ribbons for each group) were made wider as compared to other ribbons within the group, as shown in Figure The second modification that was carried out to avoid this problem of shorting between adjacent groups is the increase of the distance between the groups. In order to find the optimum gap between the groups, 𝑆 𝑔 , we calculated the pull-in voltage vertically and horizontally. The vertical pull-in voltage refers to the minimum voltage applied between the electrodes and membranes (eq. 3-13) to move the groups vertically, whereas the horizontal pull-in voltage refers to the minimum computed voltage between two adjacent groups that makes them to attract (eq. [3][4][5][6][7][8][9][10][11][12][13][14]. To move the membranes vertically and not horizontally, 𝑉 𝑝_ℎ𝑜𝑟𝑖𝑧𝑜𝑛𝑡𝑎𝑙 > 𝑉 𝑝_𝑣𝑒𝑟𝑡𝑖𝑐𝑎𝑙 . This condition leads to 𝑆 𝑔 > 𝑔 0 . Then, for an initial gap 𝑔 0 of 2.53 µm (gap between Metal 1 where membranes are placed and Metal 3 where electrodes are placed), the space between two successive groups must be more than 2.53 µm. So, for this new design, two cases will be tested: the space between groups, 𝑆 𝑔 ,will be fixed to 3 µm in one case and to 2 µm in the other case as 3 µm sounded too large to prevent electric field from leaking to silicon substrate.

𝑉
As for design 1, process flow starts at step 1 of the design methodology. The metal layers are the same as design 1, but the dimensions of the TS-CPW were modified (see Table 3-4). The new TS-CPW was simulated with HFSS. The characteristic impedance varies from 57  for off-state to 19  for on-state, leading to an average characteristic impedance of 33 . The quality factor is more than 20 for both off-and on-states.

As mentioned in section 3.1.7, the number of segments must be fixed by the designer. So to increase the number of possibilities, the number of segments was fixed to p=11. Then, the number of group lengths was reduced to 0, 25, 27, 37 µm (m=4) in order to reduce the MATLAB computation time necessary to evaluate all the possibilities which total number equals (𝑚 𝑁 ) 𝑝 = (4 3 ) 11 . The lengths are still odd values. The gap between two adjacent groups is considered in the transition. The same design algorithm than that of step 4 (section 3.1.7) was followed but with optimized ABCD matrices as defined in section 3.1.10. The structure of the new 3-bit phase shifter with 157.5° of phase shift is shown in Figure 3 The maximum simulated insertion loss is 0.

3.5.Conclusion

In this chapter a new concept of integrated distributed MEMS phase shifters based on TS-CPW for mm-waves applications was proposed. The use of the shielding layer as a moveable layer leads to a great design flexibility. A design methodology for an N bit phase shifter with N commands was developed. For a proof-of-concept, a 3 bit phase shifter with 158° of total phase shift was designed with eight linear states of phase at 60 GHz. The second generation of this 3 bit phase shifter was sent to fabrication in October 2015.

The layout and measurements of the fabricated TS-CPW and phase shifter are presented in Chapter 4. To explain discrepancies between simulated and measured phase shifts, an electrical model is also derived in Chapter 4 in order to study the evolution of the capacitance ratio between off-and on-states when varying the geometrical dimensions. The total phase shift measured at 60 GHz is 131°. We can observe due to the standing waves effect an undulation of phase. The attenuation constants at 60 GHz are 1.7 dB/mm and 2.5 dB/mm for 0 V and 13 V, respectively. Then we can deduce some figures-of-merit of 93°/mm and 52°/dB. It is important to note that due to the van der Waals attraction forces the membranes are sticking with the RF strips after actuation. They are not rigid enough to compensate for this attraction. Hence these phase shifters cannot be measured again.

The Figure 4-3 shows an optical microscope image of the fabricated 3-bit phase shifter in CEA-MEMS technology. This phase shifter was designed by Gustavo REHDER [11] and measured by myself at the IMEP-LaHC platform from 0 to 70 GHz. The phase shifter is 1.375 mm long and 340 µm wide, excluding RF and DC pads, leading to a total area of 0.47 mm². Large DC pads were used in this structure for wire bonding interconnection of the segments of each group. We can see from Figure 4-4 that the 𝐶 𝑜𝑓𝑓 and 𝐶 𝑜𝑛 are 1.5 pF and 19 pF, respectively. Hence the capacitance ratio 𝐶 𝑜𝑛 /𝐶 𝑜𝑓𝑓 is around 12.6 that allows obtaining a strong phase shift per unit length.

This phase shifter was measured in weak signal (S-parameters) using a vector network analyzer from DC to 67 GHz. The RF measurement results are presented in Figure 45. The FoM which is defined as the ratio between the maximum phase shift and the maximum insertion loss is around 50°/dB at 60 GHz. The simulated FoM is slightly different than measured FoM due to the overestimated insertion loss. Another FoM which is defined as the ratio between the maximum phase shift and the length of the phase shifter is around 110.5°/mm. A better optimization of the commands and phase shifter design could increase these two FoMs without increment in surface area.

This phase shifter was designed by Bruno VERONA [4] and implemented in AMS technology.

Bruno measured this phase shifter in 2013 at IMEP-LaHC laboratory from 0 to 100 GHz. Figure 4-6 shows the measured and simulated performances of the AMS phase shifter. leading to a small insertion loss variation. Further, there exists good agreement between simulated and measured values, except for some oscillations in the insertion loss that could be due to de-embedding issues. In this phase shifter the shielding layer start to move at 20 V and gives the higher phase shift of 25° at 60 V which leads to a FoM of approximately 36°/dB. This phase shift is 20° smaller than expected. The most probable cause is the presence of an unknown material above the shielding layer. This materiel can prevent the displacement of the shielding layer, thus, reducing the phase shift. The need for a completely known technology is mandatory for the etching post-process steps.

4.2.IHP phase shifter design 1 measurements

In this section three measurements are presented in detail, i.e. optical and electrical (DC) for geometrical and mechanical observations and RF for design characterization. Before presenting these measurements, we will first refer to the layout of the phase shifter fabricated in the SG25 technology of IHP in Figure 4567. In this section, we use the following abbreviations for phase shifters: Also, the RF measurements were re-performed at IMEP-LaHC on October 2016.

Optical measurements: laser Doppler velocimetry

First of all, we performed LDV (for laser Doppler velocimetry) measurements to check the placement of the membranes before and after actuation. From Figure 4-8, we can see that the membranes start to move at 25 V for the three phase shifters. The maximum displacement is obtained after 60 V for PS1 and PS3 and after 80 V for PS2. From this LDV measurement (for all the phase shifters) we can remark that the gap between membranes and signal strip is 700 nm only, as shown in Figure 4-8 while it was expected to be 900 nm, as specified in the SG25 BEOL description. Two reasons can be brought, (i) the membranes are wearing down at off-state, reducing the gap before actuation and/or (ii) the etching is less than expected in depth, letting about 200-300 nm of oxide on top of M2. This last hypothesis is not compatible with a standardized process as at IHP.

Note that these measurements are made at only one point of the device, i.e. in the middle of the membrane above the signal strip with some light reflected by the metallic ribbons of the membrane and some by the layer seen through the interstices of the membrane.

Optical measurements: white light interferometry

To understand a little more the LDV results in sub section 4. From Table 4-1, we can see that the displacement of the membranes is 0.75 µm after applying a voltage of 150 V (a little bit more than the 0.7-µm value obtained in LDV for a 60 V voltage but this sounds consistent with the hypothesis of a wearing down of the membrane). For 0 V again, the membranes come back to 10.9 µm. This measurement was repeated 10 times from 0 to 100 V without any problem. The device was burnt after the repetition of this measurement 3 times from 0 to 150 V. From Table 4-2, we can see that after 100 V the displacement is 1.1 µm and it is 0.2 µm more than specified by the technology (i.e. 0.9 µm). In those latter, we can note that the difference between displacements at 0 and 100 V is around 1 µm (> 900 nm) so we can confirm that complete etching has been performed, as expected. By comparing the results between Device 1

and Device 2, we can observe an inhomogeneity of etching on the wafer. More precisely, there can be an extra etch in some parts of the wafer. This extra etch cannot be estimated carefully as both effects (wearing down and extra etch) may superpose. Extra etch is not an issue. On the contrary, this guarantees a maximum of capacitance between the signal line and the membrane.

Concerning calibration, in white light interferometry as in LDV, the height absolute values do not make sense. In fact some light is reflected by the metallic membrane while some light, going through the interstices of the membrane, is reflected by the layer below; as a consequence, a mean height is calculated that is not the real position of the membrane. Never-the-less, the 7.9µm in off-state, which has been measured with white light calibration, is not so far than the expected design kit values. On the contrary, difference is valuable, as long as no variation in the laser spot position between off-and on-states occurs. This is guaranteed in white light interferometry.

In conclusion, by assuming that difference between off-and on-states make sense, we could conclude to i) an extra etch of at least 200 nm on the edge of the wafer which seems meaningful ≈7.9 µm at 0 V ≈8.9 µm at 100 V considering a total etch of around 9 µm and ii) a slight wearing down of the membrane of about 200 nm in some of the devices even if no actuation is performed. A wearing-up of the membrane ribbons could be enfaced as well. Statistical measurements correlated to the position on wafer should be done to confirm those assumptions. MEB observation could also be a good solution.

Meanwhile, capacitance measurements can already help to better analyze the geometry and the mechanical behavior. From Figure 4-10, we can see that the capacitance at 0 V is almost the same for PS1 and PS2 (500 fF). At 95 V, the capacitance of PS2 is bigger than the capacitance of PS1 (650 fF for PS1 and 680 fF for PS2) because PS2 is 20 µm longer than PS1 which does not have a big effect in offstate. As compared to PS1 and PS2, PS3 is smaller. Hence the capacitance of PS3 is around 305 fF at 0 V and 405 fF at 95 V. The capacitance ratio Con/Coff is: 1.3 for PS1, 1.36 for PS2 and 1.33 for PS3.

Electrical measurements: capacitances

Theoretically, we should observe a Con/Coff ratio of 2 by considering a 900 nm gap in offstate, with fringing effect, but no parasitic effect, as calculated in section 4.4.1.1. In practice, referring to the capacitance measurement a smaller capacitance ratio is observed. Thus, at first, this capacitance measurement can help us to understand the equivalent circuit of the phase shifter, and may be in second, to correlate it to geometrical observations. The S parameter measurements of the three phase shifters, i.e. one 157.5° and two 315° phase shifters are presented in this section. These measurements were done at IHP platform in July 2015 up to 67 GHz. The measurements are raw measurements without pad or 50- access de-embedding, which may deteriorate the losses but do not influence the phase difference. As shown in Figure 4-11(a), the return loss is better than 10 dB for off-and on-states over the whole bandwidth (200 MHz to 67 GHz). The measured insertion loss is 2.2 dB for 0 V and 2.8 dB for 95 V. The value of insertion loss is quite high due to the small thickness of metal M2 (730 nm only). A maximum phase shift of 55° was obtained for this 157.5° phase shifter, leading to 20°/dB of FoM (no de-embedding). The other FoM defined as the ratio between the maximum phase shift and the length of the phase shifter is around 162°/mm. As shown in Figure 4-12 (a) the return loss is better than 10 dB at 0 and 95 V over the whole bandwidth (200 MHz to 67 GHz). For this 315° phase shifter, the insertion loss varies from 3.5 dB at 0 V to 4.4 dB at 95 V, as shown in Figure 4-12 (b). As this phase shifter is twice the length of 157.5° phase shifter, the losses in this phase shifter should be twice of the insertion loss (i.e. 5.6 dB) obtained for the 157.5° phase shifter. Variation is due to standing wave effect that can be observed on Figure 4-12. The measured phase shift for this phase shifter is around 82° between 0 V and 95 V. The FoMs in this case are equal to ~19°/dB (no de-embedding) and 120°/mm. This phase shifter also showed the same issue of displacements as the 157.5° phase shifter. As shown in Figure 4-13 (a) the return loss is better than -10 dB at 0 and 95 V over the whole bandwidth (200 MHz to 67 GHz). For this 315° phase shifter with 4 commands, the insertion loss varies from 3.6 dB @ 0 V to 4.5 dB @ 95 V, as shown in Figure 4-13 (b). The measured phase shift for this phase shifter is around 100° between 0 V to 95 V leading to FoMs of ~22°/dB (no de-embedding) and 142°/mm. may cause this difference: it could be due to the parasitic effect of the substrate which has not been considered during the simulation. To understand more the substrate effect, we made a calculation of the parasite capacitances in section 4.4.1.

157.5° phase shifter/ 3 commands

315° phase shifter/3 commands

315° phase shifter/4 commands

4.3.IHP phase shifter design 2 measurements

Up to now, all the previous sections of chapter 4 considered the measurements of the first design in IHP SG25 technology. The measurements results of the optimized phase shifter of the second design (chapter 3, section 3.4) will be presented the day of my defense, the 15 th of December 2016.

4.4.Discussion on the parasitic effect of the substrate

As presented in Figure 4-7, the phase shifter has 3 parts: phase shifter, access and RF pads.

In this section dedicated to the observation of the parasitic effect of the substrate, we calculate all the capacitances that exist for each part of the 157.5°phase shifter in IHP SG25 technology. The calculation of the fringing capacitance is given into details in [START_REF] Bautista | Accurate Parametric Electrical Model for Slow-Wave CPW and Application to Circuits Design[END_REF]. Only the angle capacitance (see [START_REF] Bautista | Accurate Parametric Electrical Model for Slow-Wave CPW and Application to Circuits Design[END_REF]) has been considered here and roughly calculated in an analytical way. The As 𝐶 𝑠 is a capacitance that varies with the applied voltage between membrane and electrode, it is more appropriate to refer to it as 𝐶 𝑠-𝑜𝑓𝑓 in the off-state and as 𝐶 𝑠-𝑜𝑛 in the on- Finally, the total capacitance of the phase shifter for off-state, 𝐶 𝑜𝑓𝑓 , is equal to the addition of 𝐶 𝑃𝑆𝑜𝑓𝑓 + 2. 𝐶 𝑎𝑐𝑐𝑒𝑠𝑠 + 2. 𝐶 𝑝𝑎𝑑 = 142 + 90 + 64 = 296 𝑓𝐹 . This value of calculated 𝐶 𝑜𝑓𝑓 is matching quite well the measurement value of 305 fF for off-state. For on-state, the equivalent capacitance is 𝐶 𝑜𝑛 = 𝐶 𝑃𝑆𝑜𝑛 + 2. 𝐶 𝑎𝑐𝑐𝑒𝑠𝑠 + 2. 𝐶 𝑝𝑎𝑑 = 444 + 90 + 64 = 598 𝑓𝐹 . This calculated 𝐶 𝑜𝑛 is not matched with the measurement (405 fF). This mismatch between calculated and measured 𝐶 𝑜𝑛 is due to the fact that we estimate in calculation 𝐶 𝑠_𝑜𝑛 higher than the actual existing capacitance in the phase shifter. Also this mismatch can be due to the fact that the capacitance between CPW strips and substrate has not been well estimated.

Equivalent capacitances: phase shifter movable part

Equivalent capacitances: access

Equivalent capacitances: RF pads

The solution to reduce the parasitic capacitance due to the substrate is to place the membranes under the CPW strips in order to design the TS-CPW. In this proposition, we put the membranes in Metal 2, the CPW in Metal 3 and Top Metal 1 (TM1). Also, we place two high

Conclusion

The present thesis concerned the development of phase shifters based on Tunable Slow-wave CoPlanar Waveguides (TS-CPW) on MEMS technology with post-CMOS process for mm-wave frequencies. The objective was to answer new challenges for integrated circuit design, such as mm-wave front-end transceivers, for which a phased array can be required, thus needing the development of tunable phase shifters as presented in chapter 1. Thanks to the slow-wave effect, the TS-CPW exhibits a high miniaturization and high quality factor, thus leading to high electrical performance along with small foot-print. TS-CPW has been employed in this thesis work for designing a phase shifter with distributed MEMS in IHP 0.25 µm BiCMOS technology, IHP in Germany.

In chapter 2, an overview about RF-MEMS was presented with two types of switches (ohmic and capacitive) and their electrostatic actuator. Various types of failures due to the electrostatic force are also exposed. Also, before proceeding to TS-CPW design, the characteristics of the S-CPW on a 0.25 µm BiCMOS technology were studied. These characteristics gave us insight to choose the first design elements, as metal layer for TS-CPW strips or electrodes or movable membrane. The design topology of TS-CPW was defined taking into account the fabrication priorities. Also, the structure of the TS-CPW was simulated in HFSS in order to extract its electrical characteristics and optimized. These simulated and optimized TS-CPW structures have been utilized to design the phase shifters presented in the next chapter.

In chapter 3, a detailed design methodology to implement a digital phase shifter based on TS-CPW was presented. First, how to use a TS-CPW as a 1-bit phase shifter was explained after the presentation of previous designs of phase shifter carried out at IMEP-LaHC. Next, thanks to the movable membrane of the TS-CPW, ribbons are combined in groups and segments in order to design an N-bit phase shifter with N-commands. Then, the design methodology was proposed and used to implement at 60 GHz, one 157.5° and two 315° phase shifters with 3 commands in MATLAB. The three phase shifters were fabricated and received by the end of July 2015. Their simulated performance in HFSS clearly showed a problem in the MATLAB design methodology for the intermediate states of phase shift. This issue was then resolved by adding a transition for successive off-and on-states which was not taken into account before. Then, an optimized design for 157.5° phase shifter based on distributed MEMS with 3 commands was proposed with a good agreement between MATLAB and HFSS simulation. This optimized phase shifter was sent to fabrication on October 2015 and the measurement will be presented the day of my defense.

Figure 1 - 1 :

 11 Figure 1-1: Phase shifter (transmission mode).

Figure 1 - 2 :

 12 Figure 1-2: Phased array antenna using tunable phase shifters [4].

Figure 1 -

 1 Figure 1-3

Figure 1 - 3 :

 13 Figure 1-3: Block diagram of a 4x4 Butler matrix [5] using phase shifters.

Figure 1 - 4 :

 14 Figure 1-4: Common collector Colpitts VCO using tunable phase shifter [6].

Figure 1 -

 1 5(b) presents a RTPS that is composed of a branch-line coupler (Figure 1-5 (a)) loaded by two varactors Z L .

Figure 1 - 5 :

 15 Figure 1-5: RTPS loaded by varactors.

Figure 1 - 6 :

 16 Figure 1-6: Loaded-line phase shifter with a shunt-coupled load. Switched-line phase shifter (or switched delay-line phase shifter) is another kind of phase shifter, which consists of 𝑛 delay lines, connected each side by a single-pole-n-throw (SPnT) switch. A switched-line phase shifter using two single-pole double throw (SPDT) switches is illustrated in Figure 1-7.

Figure 1 - 7 :

 17 Figure 1-7: Switched-line type phase shifter [9].

Figure 1 - 8 :

 18 Figure 1-8: Schematic and optical views of the phase shifter proposed in [20].

Figure 1 - 9 :

 19 Figure 1-9: (a) Circuit schematic photograph of the fabricated phase shifter [24], (b) example of MIM capacitor [22] and (c) photograph of the BST tunable phase shifter, and of the MIM capacitor [23].

Figure 1 - 10 :

 110 Figure 1-10: Structure of (a) LC-based MLPS for 60 GHz band, (b) reflection load and (c) LC-based RTPS for 60 GHz band [29]. The second phase shifter is a RTPS (Figure 1-10(c)) composed of a 3 dB hybrid coupler and two reflective loads (Figure 1-10(b)) exposed to the LC layer. When a bias voltage is applied through the probe pads to the conductor, the LC molecules change direction beneath the electrode. This changes the effective dielectric constant, and hence a variation of the reactance of the reflective loads and a differential phase shift occur.

Figure 1 -

 1 Figure 1-11: (a) Meander line phase shifter and (b) four-elements array including meander line phase shifter [31].

Figure 1 -

 1 Figure 1-12(a) describes the stripline topology used in [32], where the ground plane has the same width as the signal line. A photograph and 3D-model of the LTCC based LC stripline phase shifter are shown in Figure 1-12(b) and Figure 1-12(c). Experimental results between 30 and 34 GHz give a return loss equal to 10 dB, and a worst insertion loss of 6 dB and 8 dB, at 30 GHz and 34 GHz, respectively. The phase shift is 61°, leading to a FoM of 10°/dB at 30 GHz. Deembedding of these results highlights that the FoM of the phase shifter increases to 13°/dB at

Figure 1 -

 1 Figure 1-12: (a) Schematic cross section of the stripline LC phase shifter, (b) photograph of the LTCC-based LC phase shifter device and (c) 3D-model of the phase shifter realized in LTCC technology [32].

  50 to 56 GHz for a passive quadrature generator. This phase shifter is of RTPS type. It consists in a coupled-line coupler loaded by shunts varactors. The schematic diagrams and the photographs of the phase shifter and the passive quadrature generator are shown in Figure 1-13 (a), Figure 1-13(b), Figure 1-13(c) and Figure 1-13(d), respectively.

Figure 1 -

 1 Figure 1-13: (a) Schematic of the phase shifter, (b) chip microphotograph of the passive phase shifter, (c) schematic of the quadrature generator with VM and (d) chip microphotograph of the quadrature generator based phase shifter [36].

Figure 1 -Figure 1 - 14 :

 1114 Figure 1-14: (a) The grounded-CPW, (b) schematic of the 4-bit digital phase shifter, (c) chip photograph of the 90°phase shifter cell and (d) chip photograph of the 4-bit digital phase shifter [37].

Figure 1 -

 1 Figure 1-15(a) and Figure 1-15(b), respectively.

Figure 1 -

 1 Figure 1-15: (a) SEM of the fabricated SP4T RF-MEMS switch, (b) SEM images of the fabricated V-band 2-bit phase shifter [41].

Figure 1 - 16 :

 116 Figure 1-16: (a) Circuit schematic of the proposed reflection-type phase shifter and (b) and (c) images of the fabricated phase shifter [42].

  For a transmission line propagating a TEM mode, the telegraph model is used (Figure 1-17). 𝑅 𝑙 (Ω/𝑚) is the linear resistance, which represents the resistive losses in the conductors, L l (H/m) is the linear inductance, C l (F/m) is the linear capacitance, and G l (S/m) is the linear conductance related to the losses due to the leaks through the dielectric.

Figure 1 - 17 :

 117 Figure 1-17: Telegrapher model (or RLCG model).The behavior of transmission line can also be described by other parameters like the characteristic impedance 𝑍 𝑐 and the propagation constant 𝛾. These parameters are related to the elements of the RLCG model as expressed in eq. (1-7) and (1-8).

( 1 -

 1 15) are multiplied by the TLine's physical length; this gives a ratio between the phase shift and the attenuation constant.

Figure 1 - 18 :

 118 Figure 1-18: Topology of the slow-wave coplanar waveguide

  are considered. Therefore, a new electrical model based on the physical behavior of the S-CPW was proposed in [49]. It is shown in Figure 1-19. The magnetic field has the same spatial distribution in a S-CPW and in a classical CPW; hence the modeled inductance 𝐿 𝑙 is similar for both topologies possessing the same geometrical dimensions.

Figure 1 - 19 :

 119 Figure 1-19: Proposed equivalent model for S-CPW.

  will change. The proposed equivalent model for TS-CPW is shown in Figure 1-20.

Figure 1 - 20 :

 120 Figure 1-20: Proposed equivalent model for TS-CPW. To vary the capacitance 𝐶 𝑡𝑜𝑡 of the S-CPW, we have two methods: a) the first method is based on varactors (sub-section 1.4.2), b) the second method is based on distributed MEMS (section 1.4.3).

Figure 1 - 21 :

 121 Figure 1-21: Cross view of S-CPW to form the tunable phase shifter with varactors.

Figure 1 -

 1 22(b) presents the phase shifter electrical model.

Figure 1 - 22 :

 122 Figure 1-22: Phase shifter electrical model [51].

Figure 1 -

 1 [START_REF] De Paolis | Characterization of ferroelectric BST MIM capacitors up to 65 GHz for a compact phase shifter at 60 GHz[END_REF] presents the cross views of the S-CPW with the DC electrodes and the tuning principle of the phase shifter.

Figure 1 -

 1 Figure 1-23:( a)Cross view of S-CPW to form the tunable phase shifter with distributed MEMS, (b) and (c) the tuning principle of the phase shifter [55].

1 . 5 .

 15 Integrated technologies description for distributed MEMSAn integrated circuit (IC) or monolithic integrated circuit is based on semiconductor material (silicon). An integrated technology consists of two parts: Front-end-of-line (FEOL) and back-end-of-line (BEOL) which consists in sandwiching metallic layers between isolating silicon oxide layers, on top of the silicon bulk.In this section, only the CMOS, BiCMOS and MEMS technologies used by our laboratory to fabricate a tunable phase shifter at mm-wave is discussed. First, the technologies used in the previous designs by Marcus Peregrini[START_REF] Pelegrini | Déphaseur accordables à 60GHz basés sur des lignes à ondes lentes à MEMS distribués[END_REF] (PTA technology), Bruno Verona[START_REF] Verona | Slowwave distributed MEMS phase shifter in CMOS for millimeter-wave applications[END_REF] (AMS technology) and Gustavo Rehder[START_REF] Verona | Slowwave distributed MEMS phase shifter in CMOS for millimeter-wave applications[END_REF] (CEA and AMS technologies) are presented. The results were characterized during this PhD thesis. Second, the main technology, 0.25 µm BiCMOS by IHP, used in this thesis to design a new tunable phase shifter is described.

Figure 1 -Figure 1 -

 11 Figure 1-24 (b). An oxide layer of 1.8 μm thickness is realized by plasma enhanced chemical vapor deposition (PECVD), Figure 1-24(c) followed by a chemical mechanical polishing (CMP), Figure 1-24(d). Finally, the floating strips of 350 nm thicknesses are formed by optical path above the CPW strips, Figure 1-24 (e), before releasing by HF vapor, Figure 1-24(f).

Figure 1 - 24 :

 124 Figure 1-24: Fabrication process with PTA technology.

Figure 1 -Figure 1 - 25 :

 1125 Figure 1-25: Fabrication process with CEA technology.

Figure 1 -

 1 [START_REF] Strunck | Reliability study of a tunable Ka-band SIW-phase shifter based on liquidcrystal in LTCC-technology[END_REF]. It has four levels of aluminum metallization: the upper level is the 2.8 µm thick M4 in order to minimize the conductive loss, the other three metal levels possess a thickness of 0.64 µm and each layer of SiO2 between two metal levels has a thickness of 1 µm. The stack is covered with a passivation layer (2 µm of silicon nitride Si3N4) to protect the devices from corrosion. The permittivity of silicon nitride is 7.4, which also serves to limit the leakage of the electric field lines in the air.

Figure 1 - 26 :

 126 Figure 1-26: BEOL of the AMS 0.35 µm technology.

Figure 1 - 27 :

 127 Figure 1-27: BEOL of the IHP's 0.25 µm BiCMOS technology.

Figure 1 -

 1 [START_REF] Houzet | Dispersion and loss of ferroelectric Ba Sr TiO thin films up to 110 GHz[END_REF] shows the 1 st generation of IHP's RF-MEMS switch in 0.25 µm BiCMOS technology.

Figure 1 - 28 :

 128 Figure 1-28: IHP's 1 st generation RF-MEMS switch in 0.25 µm BiCMOS technology.

Figure 2 - 1 :

 21 Figure 2-1: Operating principle of a RF-MEMS switch with an ohmic contact.

Figure 2 -

 2 Figure 2-2).

Figure 2 - 2 :

 22 Figure 2-2: Operating principle of a RF-MEMS switch with a capacitive contact.

Figure 2

 2 Figure 2-3.

Figure 2 - 3 :

 23 Figure 2-3: Modeling of the electromechanical operating principle of RF-MEMS electrostatically actuated.

Figure 2 - 4 :

 24 Figure 2-4: Gap height versus applied voltage with a spring constant of 10 N/m and 100*100 µm 2 of area [5].

Figure 2 - 5

 25 Figure 2-5 is a reminder of the SG25 BEOL, the design of IHP's already available capacitive RF-MEMS switch, [56], and the topology of an S-CPW.

Figure 2 - 5 :

 25 Figure 2-5: (a) BEOL of IHP's SG25 technology, (b) cross section embedded of IHP's RF-MEMS switch integration [56], (c) S-CPW topology.

•

  Figure 2-6 (a) shows the only possibility where the shielding layer is over the CPW strips.

Figure 2 -

 2 Figure 2-6 (b), Figure 2-6 (c) and Figure 2-6 (d) present the other cases where the shielding layer is below the CPW strips (TM1, TM2 and TM1-TM2 stack).

Figure 2 - 6 :

 26 Figure 2-6: Cross section of different topologies of S-CPWs in IHP's SG25.

  and (1-7), we can see that the characteristic impedance 𝑍 𝐶 depends on the capacitance per length 𝐶 𝑙 , which depends on the signal width 𝑊. Thanks to HFSS TM simulation tool, a parametric simulation of all S-CPWs presented in Figure2-6 was carried out in order to select the 50  S-CPW in the different stack configurations. Table2-1 gives the physical parameters and performances of different 50  S-CPWs at 60 GHz.

Figure 2 - 7 presentsFigure 2 - 7 :

 2727 Figure 2-7: Quality factor and maximum of linear loss versus CPW strips stacks.

- 8 .

 8 The structure is composed of CPW strips realized in M2. The floating shield (or floating membrane) takes place above the CPW strips in M3.

Figure 2 - 8 :

 28 Figure 2-8: TS-CPW topology.

Figure 2 - 9 :

 29 Figure 2-9: Cross sectional view of TS-CPW in IHP's SG25 technology before actuation (off-state).

Figure 2 - 10 :

 210 Figure 2-10: Cross sectional view of TS-CPW in SG25 technology after actuation (on-state).

Figure 2 - 11 :

 211 Figure 2-11: Simple model of the capacitances between the membrane and CPW strips.

Figure 2 - 12 :

 212 Figure 2-12: Electrostatic actuator of TS-CPWs.

  signal strip is not taken into account the sio2 so, we overestimate the actuation voltage.For a proof concept, a simulation was made for a TS-CPW based on IHP's 0.25 µm BiCMOS technology, which BEOL has been detailed in chapter 1 and remembered in Figure2-5. Figure2-13 presents the cross views of half a TS-CPW structure, simulated with HFSS, for off-and onstates.

Figure 2 - 13 : 2 Figure 2 - 14 :

 2132214 Figure 2-13: Cross view of TS-CPW (a) off-state and (b) on-state.The gap between signal strip and membrane is about 900 nm of air in the off-state and 11 nm of air in the on-state. In counterpart, the gap between the ground strip and the membrane is the same (900 nm of oxide) in both cases.

Figure 2 - 15 :

 215 Figure 2-15: Electrical characteristics. (a) Characteristic impedance, (b) effective permittivity, (c) attenuation constant and (d) quality factor, versus width of CPW signal strip.

Figure 2 -Figure 2 - 16 :

 2216 Figure 2-16 presents the electrical characteristics (characteristic impedance, effective permittivity, linear loss and quality factor) of the TS-CPW with the dimensions presented inTable 2-4.

  this section, three topologies of TS-CPWs based on distributed MEMS in classical MEMS technologies and a standard CMOS technology with post-process are described. These TS-CPWs were designed in our laboratory (IMEP-LaHC) and the LME laboratory of the University of Sao Paulo in Brazil. The first design was realized before my first year of PhD in the clean rooms. The second design was realized at the CEA by using their classical MEMS technology before the beginning of my thesis. The third design on a standard AMS CMOS technology was performed independently from IMEP-LaHC, in the LME, during my first year of PhD. I participated by characterizing these TS-CPWs, up to 110 GHz, at IMEP-LaHC or on IHP's RF measurements platform. The measurement results will be presented in chapter 3 where the TS-CPWs are used to design tunable phase shifters.

Figure 2 -

 2 Figure 2-17 presents the cross sectional view of the TS-CPW. The operating principle of TS-CPW in this technology is identical to the operating principle of TS-CPW in IHP technology. Here the substrate is glass due to its low cost and extremely low dielectric loss. To avoid the metal to metal contact (short circuit) between membrane and signal strip during actuation, a thin alumina layer of 50 nm is covering the CPW strips.

Figure 2 - 17 :

 217 Figure 2-17: Cross sectional view of TS-CPW with the clean room MEMS technology. The minimum actuation voltage needed in this topology to move the membrane is around 13 V. The parameters of the simulated and fabricated TS-CPW are: 𝑊 = 29 µm, 𝑊 𝑔 = 20.5 µm, 𝐺 = 40 µm, 𝑆𝑆 = 2 µm and 𝑆𝐿 = 2 µm.

Figure 2 - 18 :

 218 Figure 2-18: Cross sectional section of TS-CPW in the CEA MEMS technology.

  CMOS technology: the standard AMS 0.35 µm, and it is also based on classical S-CPW, with a little difference in topology anyway. Here, the CPW strips are over the shielding layer which is released and rendered mobile by removing the silicon oxide layers of the BEOL. They periodically rely on pillar made of SiO2 in order to hold them in place (refers Figure 2-19).

Figure 2 - 19 :

 219 Figure 2-19: Top view of the TS-CPW with the Si O2 pillars zone.

Figure 2 -

 2 [START_REF] Vel | A 310°/3.6-dB K-band phaseshifter using paraelectric BST thin films[END_REF] shows the cross sectional view of the proposed TS-CPW. The CPW strips where realized on the top metal layer (M4), the shielding layer on M2 and the stoppers on M3. The stoppers were anchored to the silicon substrate using vias.

Figure 2 - 20 :

 220 Figure 2-20: Cross sectional section of TS-CPW in the AMS technology. (a) Shielding layer at rest and (b) shielding layer actuated.

Figure 3 - 1 :

 31 Figure 3-1: Structure of the realized phase shifter with PTA technology. (a) Off-state (b) on-state (all groups actuated).

Figure 3 -

 3 Figure 3-2 presents the structure of a distributed MEMS phase sifter using the CEA MEMS

Figure 3

 3 Figure 3-2.

Figure 3 - 2 :

 32 Figure 3-2: the distributed MEMS phase shifter in CEA technology.

  , 2-bit phase shifter has 4 states of phase. In this phase shifter, we have 8 states of phase with 4 linear states to obtain 2-bit resolution. The other 4 states are not linear due to asymmetry of the structure. Figure 3-3 shows the structure of the 2-bit phase shifter designed and fabricated in AMS technology.

Figure 3 - 3 :

 33 Figure 3-3: Top of the 2 bit phase shifter in AMS technology.

Figure 3 -

 3 Figure 3-4 reminds the topology and the parameters of a TS-CPW designed in IHP's SG25.

Figure 3 - 4 :

 34 Figure 3-4: TS-CPW. (a) Topology, (b) Cross sectional view and (c) Top view.

(3- 1 )( 3 - 2 ) 6 )

 1326 𝜑 𝑜𝑛 = 𝛽 𝑜𝑛 . 𝑙 𝜑 𝑜𝑓𝑓 -𝜑 𝑜𝑛 = (𝛽 𝑜𝑓𝑓 -𝛽 𝑜𝑛 ). 𝑙 DC pads are necessary to apply the bias voltage. It is not possible to bias each ribbon individually; hence all ribbons of a group were connected together, with only one DC command, as shown in Figure3-5. The connections also permit to "rigidify" the moveable ribbons.

Figure 3 - 5 :

 35 Figure 3-5: Top view. (a) Group of 1-bit phase shifter and (b) TS-CPW.

Figure 3 - 6 :

 36 Figure 3-6: Top view of TS-CPW with a repetition of n similar groups.

Figure 3 - 7 :

 37 Figure 3-7: Group. (a) Shape 1, (b) shape 2 and (c) shape 3.

Figure 3 -Figure 3 - 8 :

 338 Figure 3-8: Top view of, (a) 1 segment of N groups, (b) 1 segment of N groups with the CPW strips drawn on the picture and (c) p segment of N groups.

Figure 3 -

 3 Figure 3-9 describes the flow diagram of the design methodology of the phase shifter (N bit/N commands).

Figure 3 - 9 :

 39 Figure 3-9: Flow diagram of the design methodology.

Figure 3 - 10 :

 310 Figure 3-10: Detail of step 4 from flow diagram of the design methodology.

(3- 8 )( 3 - 9 )

 839 Also, the phase shift of the eight states of a 3-bit phase shifter is, 𝛥𝜑 ℎ = 𝛥𝜑 𝑖𝑗𝑘 = 𝜑 𝑖𝑗𝑘 -𝜑 000 = 𝜑 ℎ -𝜑 0 𝛥𝜑 000 = 0 𝛥𝜑 001 = 𝜑 001 -𝜑 000 𝛥𝜑 010 = 𝜑 010 -𝜑 000 𝛥𝜑 011 = 𝜑 011 -𝜑 000 𝛥𝜑 100 = 𝜑 100 -𝜑 000 𝛥𝜑 101 = 𝜑 101 -𝜑 000 𝛥𝜑 110 = 𝜑 110 -𝜑 000 𝛥𝜑 111 = 𝜑 111 -𝜑 000

(3- 13 )

 13 𝐸 101 = 𝛥𝜑 101 -112.5° 𝐸 110 = 𝛥𝜑 110 -135° 𝐸 111 = 𝛥𝜑 111 -157.5°

Figure 3 - 11 :

 311 Figure 3-11: Structure of the 3-bit phase shifter with minimum average phase shift error. From Figure 3-11, it can be seen that the second and fourth segments have only two groups, whereas the fifth segment has only one group. This was obtained by the optimization procedure described above. The first segment has 90 µm of length (3 groups: 21 µm +1 µm of space, 29+1 µm and 37+1 µm). The second segment has 64 µm of length with 2 groups of 31+1 µm. The third segment has 94 µm of length (1 group of 29+1 µm, 2 groups of 31+1 µm). The fourth segment has 60 µm of length (1 group of 21+1 µm and 37+1 µm and 1 space). The last segment

Figure 3 -

 3 Figure 3-12(b). The latter is actuated only with states 101 and 110.

Figure 3 - 13 :

 313 Figure 3-13: HFSS simulation results of the157.5° phase shifter. (a) Insertion loss (b) return loss, (c) phase, and (d) phase shift

Figure 3 - 14 :

 314 Figure 3-14: HFSS simulation results of the distributed MEMS 315°phase shifter. (a) Insertion loss, (b) return loss and (c) phase.

( 3

 3 After simulating the four possible transition states in HFSS, S parameters of each transition were extracted. Then, the ABCD matrices were calculated. So, a new equation (eq. (3-15)) is derived from eq. (3-7) considering the ABCD matrices of transition states [𝐴𝐵𝐶𝐷 𝑇] 𝑙→𝑛 where [𝐴𝐵𝐶𝐷 𝑇] 𝑙→𝑛 describes the transition, materialized by the space between the group in the 𝑙 -state (𝑙 stands for on-or off-) and the following group in the n-state (𝑛 stands for on-or off-). [𝐴𝐵𝐶𝐷] 𝑖𝑗𝑘 = [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 1] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 2] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 3] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 4] 𝑖𝑗𝑘 * [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 5] 𝑖𝑗𝑘 with [𝐴𝐵𝐶𝐷 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑖𝑗𝑘 = [𝐴𝐵𝐶𝐷 𝑔𝑟𝑜𝑢𝑝 1 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑖 * [𝐴𝐵𝐶𝐷 𝑇] 𝑖→𝑗 * [𝐴𝐵𝐶𝐷 𝑔𝑟𝑜𝑢𝑝 2 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑗 * [𝐴𝐵𝐶𝐷 𝑇] 𝑗→𝑘 * [𝐴𝐵𝐶𝐷 𝑔𝑟𝑜𝑢𝑝 3 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠] 𝑘 * * [𝐴𝐵𝐶𝐷 𝑇] 𝑘 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠→𝑖 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑠+1

Figure 3 - 15 :

 315 Figure 3-15: New structure for a group.

  -16.

Figure 3 - 16 :

 316 Figure 3-16: Structure of the optimized 3 bit phase shifter with minimum phase shift error.

Figure 3 - 17 :

 317 Figure 3-17: HFSS simulation results of the optimized distributed MEMS phase shifter in IHP SG25 technology. (a) Insertion loss (b) return loss, (c) phase and (d) phase shift.

Figure 4 - 1 :

 41 Figure 4-1: MEB view of the PTA phase shifter measured at 60 GHz.

Figure 4 - 2 :

 42 Figure 4-2: Measurement results of the PTA phase shifter. (a) Characteristic impedance and dielectric constant and (b) phase. The off-and on-states of phase shifter were measured between 10 and 70 GHz. Then, the electrical parameters of the TS-CPW, shown in Figure 4-2, were extracted using Mangan method [2] for de-embedding. The characteristic impedance and the effective dielectric permittivity are shown in Figure 4-2(a). At 60 GHz, 𝑍 𝑐 varies from 41 Ω for 0 V (off-state) to 36 Ω for 13 V (onstate), which leads to 38 Ω as an average impedance. Meanwhile, at 60 GHz 𝜀 𝑒𝑓𝑓 grows from 20.5 at 0 V, to 34.5 at 13 V.Figure 4-2(b) shows the measured phase of the five states of phase shifter.

Figure 4 -

 4 2(b) shows the measured phase of the five states of phase shifter.

Figure 4 - 3 :

 43 Figure 4-3: Optical microscope image in CEA-MEMS technology.By applying DC voltage to the RF pads (RF ground and signal), and connecting the DC ground to the shielding layer (movable membrane), some pull-in and pull-out voltages of 17 V and 10 V were measured, respectively. The voltage was swept from -40 V to +40 V as shown by the capacitance versus voltage C(V) curve in Figure4-4. A small shift in the pull-in/pull-out was observed as the voltage was cycled several times. This indicates that the dielectric is charging, which is a well-known failure mechanism for capacitive MEMS switches.

Figure 4 - 4 :

 44 Figure 4-4: Measurement of the pull-in and pull-out voltages of the distributed MEMS phase shifter with CEA technology.

Figure 4 - 5 :

 45 Figure 4-5: Measured and simulated insertion loss, return loss and phase shift of the distributed MEMS phase shift with CEA technology.

Figure 4 -

 4 Figure 4-5(a), Figure 4-5(b) and Figure 4-5(c) compare the measured and simulatedinsertion loss, return loss and phase, respectively. The measurements showed maximum insertion loss of 2.9 dB at 60 GHz for 152° of phase shift. The insertion loss has a maximum variation of only 0.85 dB between off-and on-states. The measured return loss is better than 9.8 dB for all phase states. A good agreement was obtained between measurements and simulations, even if the simulation shows an overestimation of the insertion loss of almost 1 dB.

Figure 4 - 6 :

 46 Figure 4-6: Measured and simulated AMS phase shifter. (a) Insertion and return loss and (b) phase.

Figure 4 -

 4 Figure 4-6(a) presents the measured and simulated return and insertion losses for off-and on-states, respectively. The measured and simulated return losses are better than 10 dB in the frequency range from 0 to 100 GHz for both states. At 60 GHz, the insertion loss for off-state is around 0.7 dB for a 1120-µm long phase shifter. It does not change significantly in on-state,

Figure 4 - 7 :

 47 Figure 4-7: IHP phase shifter layout. As shown in Figure 4-7, the layout has 4 parts: phase shifter (etching zone), access (without etching), RF pads and DC pads. This layout corresponds to a 3-bit phase shifter with expected total phase shift of 157.5°. The phase shifter is 340 µm long. Each access has 100 µm of length. It occupies a surface area of 340 µm × 252 µm excluding RF pads, RF access and DC commands which may vary depending on circuit' design.

•

  PS1: for 3-bit phase shifter 315° with 3 commands (occupies 680 µm × 252 µm) • PS2: for 3-bit phase shifter 315° with 4 commands (occupies 700 µm × 252 µm) • PS3: for 3-bit phase shifter 157.5° with 3 commands (occupies 340 µm × 252 µm) The first set of measurements was performed in IHP platform on July 2015 except white light interferometry. This white light interferometry was performed in Grenoble on March 2016.

Figure 4 -Figure 4 - 8 :

 448 Figure 4-8: Gap variation.

2 . 1 . 1 ,

 211 IHP sent the wafer to IMEP-LaHC on October 2015. And then, a new measurement in white light interferometry was performed the 24 th of March 2016. Only two devices were measured: Device 1 was placed in the center of the wafer, Device 2 was placed on the edge of wafer.

Figure 4 -Figure 4 - 9 :

 449 Figure 4-9: (a) 3-D view of Device 2 at 0 V, (b) 3-D view of Device 2 at 100 V, (c) gap at 0 V and (d) gap at 100 V. The green lines in Figure 4-9 (a) and Figure 4-9 (b) are the cut lines for the measurements presented in Figure 4-9 (c) and Figure 4-9 (d).In those latter, we can note that the difference

Figure 4 -Figure 4 - 10 :

 4410 Figure 4-10 shows the capacitance variation at 3 GHz. This measurement of capacitances was done at IHP platform in July 2015. Figure 4-10 compares the capacitances of PS1, PS2 and PS3.

Figure 4 -Figure 4 - 11 :

 4411 Figure 4-11(a) shows the return loss (S11) measurement of the 157.5° phase shifter, from DC to 67 GHz. The insertion loss (S21) measurement of 157.5° phase shifter is shown in Figure 4-11 (b). The phase shift is shown in Figure 4-11(c).

Figure 4 -

 4 Figure 4-12 (a) and Figure 4-12 (b) give the measured return and insertion losses, respectively, for the 315° phase shifter with 3 commands. The measured phase of this phase shifter is shown in Figure 4-12 (c).

Figure 4 - 12 :

 412 Figure 4-12: Measurement results of the 315° phase shifter with 3 commands. (a) Return loss, (b) insertion loss and (c) phase.

Figure 4 -Figure 4 - 13 :

 4413 Figure 4-13 presents the measured return loss, insertion loss and phase of the 315° phase shifter with 4 commands from 200 MHz up to 67 GHz.

Figure 4 -Figure 4 -( 4 - 1 )( 4 - 2 ) 1 ( 4 - 4 ) 2 ( 4 - 5 )

 444142144245 Figure 4-15 shows the equivalent capacitances of the movable part of phase shifter. The structure has the same dimensions as those of the TS-CPW presented in chapter 2 (𝑊 = 20 µ𝑚, 𝑊 𝑔 = 12 µ𝑚, ℎ = 0.9 µ𝑚, ℎ 𝑠 = 2.91 µ𝑚 , ℎ 1 = 0.9 µ𝑚, ℎ 2 = 1.64 µ𝑚, 𝑙 = 340 µ𝑚) . See Figure 4-15 for a reminding of the geometry. The capacitances that exist between the CPW strips and the membranes are shown in Figure 4-15(a) and their expressions are given in eq. (2-12) and (4-2).

( 4 - 11 )Figure 4 - 15 :

 411415 Figure 4-15: Equivalent capacitances for phase shifter. (a) Between CPW strips and membranes, (b) between CPW strips and substrate and (c) equivalent phase shifter capacitances.

3 ( 4

 34 state. All other capacitances are fixed ones. 𝐶 𝑔 ,𝐶 1 , 𝐶 2 , and 𝐶 3 are equal to 182 fF, 70 fF, 288 fF and 536 fF, respectively. In off-state, 𝐶 𝑠-𝑜𝑓𝑓 is equal to 75 fF. Using eq.(4-11), the equivalent capacitance 𝐶 𝑃𝑆𝑜𝑓𝑓 (Figure 4-15(c)) is equal to 142 fF.For on-state, only the capacitance of the movable part of the phase shifter is changed after etching and applying voltage, that is to say the capacitance 𝐶 𝑠_𝑜𝑛 considering the parallel plate on-signal capacitance and a negligible on-signal fringing capacitance. 𝐶 𝑠_𝑜𝑛 is extremely high; in series with 2𝐶 𝑔 , then only 2𝐶 𝑔 has to be considered. Using eq. (4-12), the equivalent capacitance 𝐶 𝑃𝑆𝑜𝑛 (Figure4-15(c)) is equal to 444 fF. 𝐶 𝑃𝑆 = 2𝐶 𝑔 + 2𝐶 1 𝐶 2 𝐶 3 𝐶 2 𝐶 3 + 2𝐶 1 𝐶 2 +2𝐶 1 𝐶

Figure 4 -

 4 Figure 4-16 shows the equivalent capacitances of the access part of the phase shifter. This access consists in an S-CPW transmission line without etching. Its dimensions are 𝑊 = 10 µ𝑚, 𝑊 𝑔 = 12 µ𝑚, ℎ = 0.9 µ𝑚, ℎ 𝑠 = 2.91 µ𝑚, 𝑙 𝑎𝑐𝑐𝑒𝑠𝑠 = 100 µ𝑚. The capacitances that exist between the CPW strips and the membranes are shown in Figure 4-16 (a). Also, the parasitic capacitances that exist between the CPW strips and the substrate are shown in Figure 4-16(b). The equivalent capacitance 𝐶 𝑎𝑐𝑐𝑒𝑠𝑠 (Figure 4-16(c)) of one access is around 45 fF (refers eq. (4-13)) taking into account the fringing effect. Then for both access (100 µm long on each sides) the equivalent capacitance is double (90 fF).

Figure 4 - 16 :

 416 Figure 4-16: Equivalent capacitances for access. (a) Between CPW strips and membranes, (b) between CPW strips and substrate and (c) equivalent access capacitances.

Figure 4 -

 4 Figure 4-17 shows the equivalent capacitances of the RF pad part of the phase shifter. The dimensions of one pad are 𝑊 𝑝𝑎𝑑 = 60 µ𝑚, ℎ 𝑠 = 2.91 µ𝑚, 𝑙 𝑝𝑎𝑑 = 50 µ𝑚 . The equivalent capacitance due to pad, 𝐶 𝑝𝑎𝑑 , on one side of the circuit, is around 32 fF taking into account the fringing effect. Then, for both sides the equivalent capacitance is double (64 fF).

Figure 4 - 17 :Figure 4 -

 4174 Figure 4-17: Equivalent capacitances for RF pads. 4.4.1.4. Discussion and final calculation Figure 4-18 illustrates the equivalent capacitance for the fabricated phase shifter including the access and the RF pads for off-or on-state.

Figure 4 - 18 :

 418 Figure 4-18: Equivalent capacitance.

Table 1 -1: State-of-the-art of passive phase shifters based on ferroelectrics.

 1

Ref Frequency (GHz) Area (mm 2 ) Max. IL. (dB) Return Loss (dB) Phase shift (°) FoM (°/dB) FoM/Area (°/mm 2 )

	[20]	30	7	3.6	12	310	85	44
	[22]	60	1.2	5.9	12	150	25	125
	[24]	30	NA	5.8	12	157	27.1	NA
	[25]	60	33	10	5.5	220	22	6.6

Table 1 -2: State-of-the-art of passive phase shifters based on liquid crystal.

 1

Ref Frequency (GHz) Area (mm 2 ) Max. IL. (dB) Return Loss (dB) Phase shift (°) FoM (°/dB) FoM/Area (°/mm 2 )

	[29]	60	128	11.6	14	243	20	1.89
	[31]	60	NA	11	12	47	4	NA
	[32]	30	>15	6	10	60	13	NA
	[34]	45	0.38	5	NA	275	51	723
	[35]	40	NA	4.8	10	303	63	NA

Table 1 -3: State-of-the-art of passive phase shifters in CMOS/BiCMOS technologies.

 1

	The main advantages of MEMS phase shifters are: low loss, good linearity, broadband

frequency operation, large tuning ratio and good power handling capability. In addition, in recent years, MEMS devices combined with CMOS/BiCMOS technologies have paved the way of a

Ref/technology Frequency (GHz) Area (mm 2 ) Max. IL. (dB) Return Loss (dB) Phase shift (°) FoM (°/dB) FoM/Area (°/mm 2 )

	great revolution for mm-wave systems. In this section, state-of-the-art of phase shifters in MEMS
	technology with pure MEMS or CMOS-MEMS technology is described.
	(a)			(b)
	(c)
				(d)
	[36]/CMOS	50-56	0.14	16.7	NA	141	11.1	1007
	[37]/BiCMOS	67-78	0.13	19	10	337	17.7	2596
	[38]/CMOS	50-65	0.075	8	12	90	11.25	120
	[40]/CMOS	50-70	3.15	4	18	135	33.7	42.8

Table 1

 1

	-4 shows a comparison of the state-of-the-art for the phase shifters based on MEMS
	at mm-waves.

Table 1 -4: State-of-the-art of passive phase shifters based on MEMS.

 1

Table 1 -5: Summary of state-of-the-art of passive phase shifters at 60 GHz.

 1

	BST exhibits high loss tangent at mm-waves, which strongly affects the insertion loss. Liquid
	crystal material leads to lower insertion loss and usually a much higher FoM, but they require
	large areas. Very few references communicate on the area. On another hand, MEMS and CMOS
	phase shifters may present very high phase shift with a moderate to very low area on a chip. Due
	to the reasonable surface, MEMS and CMOS phase shifters exhibit a FoM (°/mm 2 ) two times
	higher than the other phase shifters implemented in other technologies. Anyway MEMS-based
	PS exhibit less insertion loss than CMOS-based PS but can be integrated in a CMOS process
	including a post-etching process. In addition, it is worth mentioning that advanced

Ref Frequency(GHz) Area (mm 2 ) Max. IL. (dB) Return Loss (dB) Phase shift (°) FoM (°/dB) FoM/Area (°/mm 2 )

	[41]	55-65	4	2.7	12	270	100	67.5
	[42]	55-65	1	2.2	14	144	65.4	144
	[43]	60	NA	2	10	118	60	NA
	[44]	75-110	NA	2.7	NA	100	37	NA
	[45]	50-57	3.15	4	11.7	135	33.75	42.8

Ref/Technology Area (mm 2 ) Max. I.L. (dB) Return loss (dB) Phase shift (°) FoM (°/dB) FoM/Area (°/ mm 2 )

	[22]/BST [25]/BST [29]/LC [38]/CMOS [40]/CMOS [41]/MEMS [42]/MEMS-CMOS 65.4 CMOS/BiCMOS technologies are mandatory for the design of mm-wave phase shifters working at 1.2 5.9 12 150 25 125 33 10 5.5 220 22 6.6 128 11.6 14 243 20 1.89 0.075 8 12 90 11.25 120 3.15 4 18 135 33.7 42.8 4 2.7 12 270 100 67.5 1 2.2 14 144 60 GHz.

Table 2 -1: Characteristics and performances of the simulated 50  S-CPWs in IHP's SG25 technology at 60 GHz.

 2

  -12, 𝐸 is the Young's modulus (elastic modulus) of the metal used in this technology (here, for aluminum 𝐸 = 70 𝐺𝑃𝑎, 𝐼 is the inertia coefficient, which describes the motion of the membrane (see eq.(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)).When 𝐼 is replaced in eq. (2-13) the new expressions of 𝐾 and 𝑉 𝑝 are given by eq.(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16) andThe dimensions of the movable portion of membrane and the actuation electrode are briefly studied in this section. From eq.(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17), it is possible to observe that the minimum actuation voltage is modified with the initial gap between the actuation electrode and the movable membrane equal to 2.53 µm, the length of the movable portion of the membrane, the width of the actuation electrode and the thickness of the membrane metal layer which is imposed by the technology; here 𝑡 𝑠ℎ𝑖𝑒𝑙𝑑 is fixed to 0.73 µm for M3. Calculations corresponding to different sizes of the movable portion of membrane and the actuation electrode are shown in Table2-2.

	𝐼 =	12 𝑡 𝑠ℎ𝑖𝑒𝑙𝑑 3 . 𝑆𝐿	(2-15)
	(2-17), respectively.
	𝐾 =	𝑙 3 2 4 . 𝑆𝐿. 𝑡 𝑠ℎ𝑖𝑒𝑙𝑑	3 . 𝐸	(2-16)
	𝑉 𝑝 = √ 8. 2 4 . 𝑡 𝑠ℎ𝑖𝑒𝑙𝑑 27. 𝜀 0 . 𝑙 3 . 𝑤 𝑒 3 . 𝐸	𝑔 0	3	(2-17)

Table 2 -2: Vp for different dimensions.

 2

Table 2

 2

	-4. One can check that

Table 2 -4: Dimensions of the simulated TS-CPW.

 2

Table 2 -5: Geometry and performances of the simulated and sent to fabrication TS-CPWs in the IHP's SG25 at 60 GHz.

 2

			Floatting			Dimensions			Performances
	States CPW layer	membrane layer	𝑊 (µm)	𝑊 𝑔 (µm)	𝐺 (µm)	𝑤 𝑒 (µm)	𝑆𝑆 (µm)	𝑆𝐿 (µm)	𝛼 (dB/mm)	Q	 𝑒𝑓𝑓	𝑍 𝑐 (Ω)
	Off-state	M2	M3	20	12	180	70	1	1	1.5	28	20	68
	On-	M2	-	20	12	180	70	1	1	2.1	22	114	30
	state

Table 3 -1: Comparison of the electrical characteristics of the TS-CPW versus the shapes of group.

 3

Table 3 -

 3

	Shapes	𝒁 𝒄 (Ω)	𝑸	𝜺 𝒓𝒆𝒇𝒇
	Shape 1	65	25.2	19
	Shape 2	58	10.5	16
	Shape 3	65	25	18.6

1. The inductance per unit length is a little bit smaller in shape 2 as compared to

Table 3 -2: Dimensions of the TS-CPWs used for design 1.

 3

Table 3 -3: Phase shift for the 8 states of the proposed structure and their corresponding errors.

 3

Table 3 -4: Dimensions of the TS-CPWs used for design 2.

 3

  As shown in Figure3-16, the structure of the phase shifter is made of 14 groups of 25 µm and 1 group of 27 µm. The total physical length of the phase shifter is thus 407 µm (407.8 µm more precisely) including the distance between groups. The simulated performance of the optimized 157.5° 3 bit phase shifter is given in Figure3-17.

	Dimensions
	𝑊	28 µm
	𝑊 𝑔	16 µm
	𝐺	110 µm
	𝐺 1	70 µm
	𝐺 2	40 µm
	𝑆𝑆 = 𝑆𝐿	1 µm
	Side wall SL	2 µm
	𝑆 𝑔	2.5 µm
	𝑤 𝑒 Phase shift (°) @60 GHz
		𝛥𝜑 000	0
		𝛥𝜑 001	22.8
		𝛥𝜑 010	45.9
		𝛥𝜑 011	67.2
		𝛥𝜑 100	91.1
		𝛥𝜑 101	118.3
		𝛥𝜑 110	143.6
		𝛥𝜑 111	158.2

  5 dB for off-state and 2.8 dB for on-state at 60 GHz. whereas the simulated return loss is better than 7 dB for all the states from 58 to 65 GHz frequency range. The phase shift in consecutive states is quite linear. The states 101 and 110 present the maximum of phase errors, i.e. 5.8° and 8.6° for 101 and 110, respectively. This simulated performance in HFSS is approximately matching with MATLAB algorithm (10% of error). We note that the characteristic impedances vary from ≈56 Ω in the off-state to ≈21 Ω in the on-state guaranty a return loss better than 7 dB in the whole frequency range. The average impedance for this phase shifter is around 34 Ω.

			0					0	000
								000	001
								001	-5	010
								010	011
		Insertion (dB) loss	-3 -2 -1					011 100 101 110 111	Return (dB) loss	-25 -20 -10 -15	100 101 110 111
			56	58	60	62	64	66	-30
								56	58	60	62	64	66
					Frequency (GHz)
								Frequency (GHz)
		-100
		-150
								000
								001
	(°)	-200					010
								011
	Phase	-250					100 101 110
								111
		-300
		-350
			56	58	60	62	64	66
					Frequency (GHz)

Table 4

 4

-1 presents the measurement results for Device 1.

Table 4 -1: White light interferometry for Device 1.

 4

Table 4 -

 4 2 presents the measurement results of the white light interferometry for Device 2.

Table 4 -2: White light interferometry for Device 2.

 4

Microwave Conference (EuMC), 2014 44th European, Rome, 2014, pp. 211-214.

(2-11)

Acknowledgement

First of all, I'm grateful to my director of the thesis Prof. Philippe Ferrari and my co-director of the thesis Dr. Florence Podevin for providing me an opportunity to work for a Ph.D. in IMEP-LAHC, Grenoble-Alpes University. I am extremely grateful and indebted for their guidance, encouragement, and patience in these three years. Your support was essential to my success here. I would to thanks also my co-supervisor from Lyon Dr. Boudjemaa Remake for providing advice, information and support in different aspects in my project especially the mechanical part of my work. I would like to thank my Ph.D. thesis reviewers, Prof. Didier Vincent from saint Etienne University and Dr. Fabio Coccetti from RF-Microtech Toulouse, for having accepted to examine this work and for their valuable insights. Thanks to Prof. Skandar Basrour and Dr. Mehmet Kaynak being part of my thesis committee as well as accepting my invitation to become part of my jury as well. I would like to acknowledge Nicolas Corrao and Xavier Mescot for their help during the measurement of my integrated devices many times. Thanks to Alexander Chagoya, for his help on the design kits and conversations during my stay in IMEP. Thanks to Gustavo Rehder from Brazil also for his support in these three years. The assistance, cooperation and experience of IHP microelectronics were essential for the

To proceed with step 5 of the design methodology in section 3.1.7, the 157.5° 3-bit phase shifter was simulated up to 65 GHz using HFSS. The insertion loss and the return loss of the offand on-states (000 and 111) of the distributed MEMS phase shifter are given in Figure 3-13 (a)

and (b). Figure 3-13(c) presents the phase of the 8 states.

TS-CPWs and phase shifters measurements

In chapter 1, a review on various tunable phase shifting techniques is carried out. Then, our solution, based on tunable slow-wave coplanar waveguides (TS-CPW) with a distributed MEMS approach, including the description of the BiCMOS 0.25-µm IHP technology used for realization, is outlined. Also the technologies used for three other previous works, anterior to my PhD and performed at IMEP-LaHC in collaboration with the University of Sao Paulo and the CEA, are presented. In chapter 2, the TS-CPWs based on distributed MEMS are described in depth. A focus is made on their design, depending on the four technologies enfaced, mine and the three others.

The millimeter wave N-bit phase shifters designs and their simulation results are explained in chapter 3. A specific focus is performed on the design methodology I developed to match the number of command to the number of bits of my phase shifters.

In this chapter, the measurement results of the various phase shifters are presented: first, the measurements of the previous phase shifters, next, the IHP phase shifters (optical, electrical, and RF measurements). Then, a discussion about substrate parasitic effect is done. And finally, a comparison with state-of-the art is made.

4.1.Previous Work measurements

The measurements of the previous millimeter wave phase shifters (PTA, CEA and AMS) previously presented in section 3.1 (chapter 3) are shown in this section. All phase shifters are measured in IMEP-LaHC platform.

The PTA phase shifter was fabricated and measured from 10 to 70 GHz by Marcus Pelegrini [1] in 2013 before the beginning of my PhD. In this section, we present a comparison between measurement and simulation results from 55 to 65 GHz. Figure 4-14 shows the return loss, insertion loss and phase comparison for the 157.5° phase shifter. From Figure 4-14, we can remark that the simulation and measurement are not matched.

The simulation shows an overestimation of the return loss for both cases off-and on-states of more than 7 dB in the whole frequency range (55 GHz to 65 GHz). The difference between simulated and measured insertion loss is almost 1.5 dB for off-and on-states. Also, we can observe in Figure 4-14 (c) that the total phase shift is 155° and 55° for simulation and measurement, respectively. This discrepancy between simulated and measured phase shift can be partly due to a smaller displacement than expected (700 nm instead of 900 nm) as explained in section 4.

4.5.Comparison with state-of-the art

In Table 4-3, the performance of our MEMS-based phase shifter in IHP SG25 technology has been compared with state-of-the art of millimeter-wave passive phase shifters. First, let us notice that the miniaturized phase shifter based on TS-CPW, and among them the IHP PS1, PS2 and PS3, present the lowest occupied area as compared to other MEMS based technologies, leading to a higher FoM3 (°/mm 2 ). However PS1, PS2 and PS3 showed higher insertion loss than their other MEMS counterpart, distributed or not. This can be improved by using the thick metal level in SG25 instead of M3, as proposed in the new solution to enhance Con/Coff. Then, the FoM1 will be improved. Never-the-less, even if PS1, PS2 and PS3 results

were not de-embedded they still show much better insertion loss than varactor or transistor based phase shifters. So, if both FoM1 and area are taken into account, our device is a very good trade-off. Also our phase shifters show a 3-bit resolution with 3 commands, which had never been done before with previous works at IMEP-LaHC. In chapter 4, the set of measurements for the phase shifters early designed in chapter 3 has been presented. Optical measurement (laser Doppler velocimetry and white light interferometry) of phase shifters showed that we need around 100 V of applied voltage to move the membrane. They enabled us to make some assumptions concerning the mechanical aspects of the membranes and the etching process. The electrical measurements showed the capacitance variation between off-and on-states. The capacitance ratio (Con/Coff) for the three measured phase shifters was 1.3. Also, RF measurements were performed in order to determine phase shift for each states and figures-of-merit (FoM). Thanks to the miniaturization of the TS-CPW caused by the slow wave effect, the FoM defined as the ratio between the maximum phase shift and the area of phase shifter is very high as compared to the other MEMS phase shifters existing in literature. This work demonstrates that a miniaturized phase shifter based on slow-wave CPW and MEMS may occupy a surface as low as 0.086 mm², with 2.8 dB of insertion loss, resulting in 21.5°/dBand 639°/mm², which is the best FoM in terms of °/Area reported in the literature for MEMS-based phase shifter, to our knowledge.

However, the phase shifter design based on a new topology of TS-CPW, recently developed in this thesis, has several points to be improved among which:

• A lack of linearity in phase states. The second design of phase shifter up-coming in October 2016 in the 0.25 µm BiCMOS technology at the working frequency of 60 GHz should confirm the solving of this issue with good linearity performances.

• Insertion losses due to the thin metal thickness for the CPW strips. The third design proposed in chapter 4 should enable to overcome this issue.

• Substrate parasitic effects that decrease the Con/Coff ratio and also bring much loss.

The third design proposed in chapter 4 should enable to overcome this issue.

As a short term prospective, this phase shifter can be also re-optimized in order to build a Voltage Controlled Oscillator (VCO) with phase shifter as resonator.

The long-term prospects will concern integrating the proposed phase shifter in a millimeterwave beam-steering system. Finally, the demonstrations should be carried out at frequencies higher than 60 GHz in order to explore the potentialities of this topology to address millimeterwave imaging systems above 100 GHz.

Publications

During PhD: