Prof Ian O'connor

Wim Dehaene

Prof. Régis Leveugle

Prof Jean-Michel Portal

Santhosh Onkaraiah

Natalija Hraziia

Georgio Jovanovic

Palma

Marc Belleville

Fredéric Jérome

Yvain, Pascal, Ivan Romain Alexander

Jean-Fredéric Michel

Meycene, Sébastien, Bartosz Adam David

Soundous, Thiago, Bilel, Guillaume Vincent Alex

Grégory For Mak-

The ever increasing complexity of digital systems leads the reconfigurable architectures such as Field Programmable Gate Arrays (FPGA) to become highly demanded because of their in-field (re)programmability and low nonrecurring engineering (NRE) costs. Reconfigurability is achieved with high number of point configuration memories which results in extreme application flexibility and, at the same time, significant overheads in area, performance, and power compared to Application Specific Integrated Circuits (ASIC) for the same functionality. In this thesis, we propose to design FP-GAs with several 3D technologies for efficient FPGA circuits. First, we integrate resistive memory based blocks to reduce the routing wirelength and widen FPGA employability for low-power applications with non-volatile property. Among many technologies, we focus on Oxide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) devices by assessing unique properties of these technologies in circuit design. As another solution, we design a new FPGA with 3D monolithic integration (3DMI) by utilizing high-density interconnects. Starting from two layers with logic-on-memory approach, we examine various partitioning schemes with increased number of integrated active layers to reduce the routing complexity and increase logic density. Based on the obtained results, we demonstrate that multi-tier 3DMI is a strong alternative for future scaling. This thesis has been the result of many disscussions and efforts from inspiring people. Hereby, I would like to acknowledge all of their contribution.

4.8

Total area of FPGA benchmark circuits for SRAM and NVSRAM integration. The results show an increase in delay on average by 18%.

4.9

Total power consumption of FPGA benchmark circuits for SRAM and NVSRAM integration. The results show an increase in delay on aver-

5.8

The supply connections designated in white box are overlapped due active area sharing for reduced total area. . . . . . . . . . . . . . . . .

5.9

Area of FPGA benchmark circuits for 2D and 3D architectures. Area can be reduced by 55% on average when designed in 3D. . . . . . . . .

The End of Scaling Era

Until now we relied on traditional scaling in order to increase performance and logic density. For more than four decades, according to Moore's law [START_REF] Moore | Cramming more components onto integrated circuits[END_REF], the number of transistors doubled every two years. As the transistors operated faster, higher frequencies are reached. However, traditional scaling is facing fundamental limitations on manufacturing, performance, and power consumption figures.

The structure of conventional transistor imposes difficulties on manufacturing for further scaling. The complexity of lithography process grows with each advancing node. Thus, either new lithography technologies or more patterning steps are required which increase the production cost tremendously. Secondly, the tiniest feature of the transistors, the width of the gate dielectric, recently reached the size of several atoms, which imposes problems: higher dependence to the number of atoms which change due to variations in manufacturing and lowered gate barrier which increases the leakage current.

Apart from manufacturing implications, the performance gains are shrinking due to the limits on interconnects. Even though the transistors are shrinking, the circuits cannot reach high performance without fast and dense interconnects. Unfortunately, the wires cannot be made fast and dense at the same time: wider cross-section increases the parasitic capacitance while reduced height or width increases electrical resistance.

As demonstrated in Fig. 1.1, the gap between the gains of gate performance and interconnect delay widens as the technologies advance. Since the interconnect wires cannot keep up with that trend, they become one of the major bottlenecks in traditional scaling.

The inevitable growing in power consumption leaded to the end Dennard's theory [START_REF] Dennard | Design of ion-implanted mosfet's with very small physical dimensions[END_REF]. Dennard stated that each advancing node should increase the performance by 40% while keeping the same power consumption. Recent trends show that scaling can only fulfill gains in either power efficiency or transistor density. The two components of power consumption leakage and dynamic are increasing significantly with each advancing technology node as depicted in Fig. 1.2. Previously, leakage consumption was assumed to be negligible, however as a result of scaling, it is becoming more significant because it reaches to the level of dynamic power. Dynamic power consumption increases as more devices switch at higher frequencies even though the supply voltage is reduced due to scaling. Furthermore, the severity of interconnects became more apparent recently as they account more than 50% of the total consumption [START_REF] Magen | Interconnect-power dissipation in a microprocessor[END_REF]. Since the wires are not shortening as expected with scaling, bigger transistor are needed to drive these wires which leads to higher power consumption. Consequently, power consumption is becoming the major bottleneck limiting the traditional scaling.

Due to the diminishing returns of scaling, we are now facing the so-called utilization wall. The designers aimed to keep the same power density while trusting scaling for increased logic density and higher frequency. However, the power density reached to highest limit that the chip could handle. Thus, acknowledging the end of frequency scaling, a new trend was born which proposed adding more cores working at lower frequencies. This allowed to add more functionality while still being lower than the power cap. Even though the frequency is lowered, more transistors are switching with each added core which push power consumption towards power cap. Namely, the utilization of transistors must be limited because only a number of transistor can be active at any given time due to the power constraint. Therefore, some of these transistors have to stay inactive which leads to the phenomena called dark silicon.

INTRODUCTION

Emerging 3D Technologies

The limitations of traditional scaling are forcing us to find next scaling paradigms.

Thanks to all the research efforts, we are now in reach of many possibilities. 3D technologies are receiving unprecedented attention for future circuits and they could create the aspired flexibility to address the demands. Fig. 1.3 depicts several promising 3D technologies as 3D integration and advanced memories. One of the 3D integration possibilities is with Through-Silicon Vias (TSV). TSV integration offers stacking of multiple wafers and it helps reducing the wirelength however they occupy a significant space for vertical connections. Thus, they only allow very limited number of connections between layers. In order to derive the maximum benefits from 3D integration, the technology must support a very high density of vertical interconnects with via dimensions compatible with device sizes. A new technology called 3D monolithic integration (3DMI) extends the limitations of TSVs by achieving 40x smaller inter-tier vias (Table 1.1). The unique feature of 3DMI is the sequential integration of active layers one after another on the same die. Thus, the layers are aligned with high precision which allows fabrication of inter-tier vias similar to regular vias. Apart from 3D integration, advanced memories can introduce increased functionality in the third dimension. Advanced memories bring substantial benefits to the conventional CMOS with the integration at the Back-End-of-Line (BEOL) and non-volatile operation possibilities. These memories can be fabricated between metal layers requiring no silicon area and store one bit of information. These emerging 3D technologies can address the challenges of existing technologies and be the next paradigm for future scaling. Current FPGAs, on the other hand, have already reached 28nm soon to be on 20nm and smaller process technologies. Most new ASIC designs lag behind FPGAs with a two or three nodes as illustrated in Fig. 1.4 [START_REF] Altera | Expect a breakthrough advantage in next-generation fpgas[END_REF]. This trend shows that there are extreme demands on FPGAs and more aggressive solutions are needed. It is, therefore, safe to say FPGAs will be the first platform to take benefit from emerging technologies.

Research Contributions

In this thesis, the application of 3D technologies for efficient implementations in FPGAs are analyzed. Among different technologies, 3D monolithic integration and nonvolatile memories are evaluated. The contributions of this work constitutes development of exploration framework and effective design solutions with emerging 3D technologies.

FPGA Experimental Evaluation Platform

The integration of emerging technologies to FPGAs cannot be accomplished without an evaluation platform. Even though the FPGA fabric is generic and simple, overall FPGA area, performance, and power metrics depend on the application that is mapped onto this fabric. Furthermore, the technological properties cannot be imposed by simple transistor parameters. Therefore, first an evaluation framework is established by a set of tools which takes an architecture definition of the FPGA fabric including Finally, a low power computing system is proposed using the designed NVFPGA.

Since all volatile elements are replaced with their non-volatile counterparts, NVFPGA can be switched off when not in use to save the static power while still keeping the configuration information. For this functionality, power gating is implemented and system level impacts are reported. The designed system is suitable for Normally-off

INTRODUCTION

Instantly-on applications which do intensive computation for a short amount of time and sleep during rest of the time. By carefully analyzing the applications and the impacts of the designed system, an activity ratio is defined for overall power savings.

3D-FPGA with Monolithic Integration

In this thesis, several 3D-FPGA circuits with monolithic integration are designed and evaluated. This work constitutes contributions in design and partitioning aspects with 3DMI.

In order to get the highest benefits from this novel technology, full-custom circuits for 3D-FPGA are designed. Layouts of the corresponding blocks are created using 14nm 3D LETI-FDSOI PDK considering logic-on-memory approach. All the blocks are characterized with post-parasitic simulations for area, delay, and power consumption values. The blocks are then integrated to create a 3D-FPGA. The 3D-FPGA is compared to the 2D counterpart and the improvements are reported.

The designed 3D blocks establish a basis for further partitioning exploration. Several partitioning schemes are investigated considering implementations having more than 2 active layers up to 4 layers. Architecture definitions for each of the design are developed and using the evaluation platform, area and EDP gains are estimated. The analysis of the results shows that 3DMI provides higher gains than traditional scaling expectations.

Thesis Summary

The thesis is briefly explained as follows:

In chapter 2, the context of this research work is outlined. The first section, 2.1.1., starts with a summary of recent FPGA history. The next section, 2.1.2., details the FPGA architectures. The baseline FPGA architecture is formed with logic blocks and routing resources. In the next section, 2.2., the limitations of current FPGAs are identified. The limitations are categorized as configuration memory and routing resource.

Emerging technologies are introduced as advanced memories and 3D integration in Section 2.3.. State-of-the-art implementations are compared and related works on integration of emerging technologies on FPGAs are presented in Section 2.3.3..

Thesis Summary

In chapter 3, the FPGA exploration framework and methodology for emerging In chapter 4, we target OxRAM and CBRAM technologies for efficient FPGA design. First, the motivation towards RRAM-based FPGAs is explained. In section 4.1., the circuits NVSRAM, NVFF, and NVE are characterized in terms of area, performance and power consumption including operating principle of each circuit. In the section 4.2., new applications fields are proposed as configuration-saving and contextsaving. The modification needed for NVFPGA with the analyzed circuits using OxRAM and CBRAM technologies are explained. In section 4.3., a new computing scheme with low-power property is discussed. In order to meet the low-power goal, power-gating opportunities and the associated cost are explored in section 4. FPGAs are under rapid growth and they are becoming one of most popular digital circuit implementation solution. FPGAs are reconfigurable devices which enable the use of the same silicon for different applications. They can fulfill high performance requirements and at the same time, lower the NRE costs and time-to-market. The programmable nature of FPGA make them very flexible while making them larger, slower, and more power consuming than ASICs. Thus, the FPGA adoption in embedded applications is very limited.

The advancements in process technology has lead to improvements of FPGA efficiency. As explained in the previous chapters, FPGAs gained benefits from advanced technologies faster than ASICs. It is observed that FPGAs lead ASICs with at least 1

BACKGROUND AND MOTIVATION

process node ahead. In this perspective, emerging technologies will appear first in an FPGA integration. For the highest benefits, these technologies must be fully exploited.

Especially, advanced memories with nonvolatile property and 3D integration are very promising for increased logic density, functionality, performance, and power efficiency in the FPGAs.

In this chapter, first an overview of reconfigurable devices and FPGAs is provided.

The FPGA architecture is explained in detailed. In the following section, existing FPGA programming technologies are expressed. Based on the present FPGAs, the limitations due to configuration memory and routing resource are specified. Emerging 3D technologies, advanced memories and 3D integration are explained in detail. Related works of FPGA-based solutions with these technologies are discussed. The chapter is then concluded with insights for the thesis work.

FPGA Background

In computing systems, many different processing elements exist depending on programmability, cost, performance, and power consumption requirements. They span from General-Purpose Processors (GPP), reconfigurable systems, Application-Specific Integrated Circuits (ASIC) up to full-custom integrated circuits. Reconfigurable systems are becoming widely adopted in system design where Field Programmable Gate Arrays (FPGAs) find interest as a reconfigurable device. Several reconfigurable architectures have been presented in the literature [START_REF] Hartenstein | A decade of reconfigurable computing: a visionary retrospective[END_REF].

Among other computing solutions, FPGAs are considered as a bridge between GPPs and ASICs. FPGAs are able to cover an extremely wide range of applications with varying trade-offs and efficiencies. The point multiplication of elliptic curve cryptography algorithm implementation example shows that FPGAs can compute the result 540x faster while operating at a clock frequency 40x slower than a GPP [START_REF] Telle | Customising hardware designs for elliptic curve cryptography[END_REF]. Moreover, according to Stitt et al., when critical software loops are moved to reconfigurable hardware, energy savings up to 70% can be achieved [START_REF] Stitt | Energy savings and speedups from partitioning critical software loops to hardware in embedded systems[END_REF]. On the other hand, ASICs perform better than FPGAs in terms of area, speed and power. Kuon et al. quantify the difference between FPGA and ASIC designs [START_REF] Kuon | Measuring the gap between fpgas and asics. Computer-Aided Design of Integrated Circuits and Systems[END_REF]. They show that purely Look-Up Table(LUT)-based mapping requires 35x larger area with 4x higher delay and 14x more power consumption. It is also noted that with extensive usage of hard-implemented blocks (ex. multipliers, accumulators, block memories) the area difference can narrow below 5x.

FPGAs bring the possibility to use the same circuit for many different applications thanks to reconfigurability. This eliminates the long design cycle required for ASIC development. Thus, FPGAs significantly reduce time-to-market and Non-Recurring Engineering (NRE) costs. Design of an ASIC can only be justified for applications requiring products in large quantities such as mobile market. For low-to-medium volume applications FPGAs are often preferred. Moreover, FPGAs always lead ASICs with at least 1 and often 3-4 technology nodes ensuring circuits with the most advanced technologies to reduce the performance gap compared to ASICs. Whereas the same technology used for FPGAs becomes highly costly for ASIC manufacturing. Consequently, FPGAs provide a viable solution for digital circuit applications with a trade-off between flexibility, performance and cost.

Recent History of FPGAs

The ability to configure the logic functionality of a circuit after fabrication, started to appear in the 1970s with read-only memory-based arrays called Programmable ROMs (PROM). In these one time programmable devices, the address lines serve as logic inputs and data lines as output. Thus, N address inputs can implement any N-input functions. PROMs became area inefficient because the required area increases exponentially with the number of inputs (N). Thus, Programmable Logic Arrays (PLA) are introduced specifically for logic functions. A two-level AND-OR plane including a programmable wired-AND plane, followed by a programmable-OR plane, can closely match the structure of common logic function. In a PLA, any input can be ANDed together in the AND plane corresponding to the product terms and OR plane can be configured to produce the sum of any AND plane output. Even though PLAs provided sufficient flexibility, the programmable planes were difficult to manufacture and the performance suffered from high propagation delays. Programmable-Array Logic (PAL) was introduced as a solution to address these problems. As opposed to the two programmable planes in PLAs, PALs feature a single programmable AND-plane followed by fixed-OR gates. Many variants of these circuits are developed for increased functional capabilities including sequential logic circuits with flip-flops connected after the fixed-OR gate outputs.

BACKGROUND AND MOTIVATION

PAL-like structures continued to be seen in the market with higher capacities. As the area of the devices grows quickly with increasing number of inputs, manufacturing became difficult for traditional PAL-like architecture. Complex Programmable Logic Devices (CPLD) provided a solution with programmable interconnects. More sophisticated devices for digital hardware became apparent as the difficulty to integrate more devices increased significantly. Mask Programmable Gate Arrays (MPGAs) achieved the highest capacity general purpose logic chips. The wire routing is carried out according to user demands where the transistors are prefabricated. Although they are not user programmable, they created the motivation for Field Programmable Gate Arrays (FPGA).

Wahlstrom introduced the first Static Random Access Memory (SRAM)-based FPGA in 1967 [START_REF] Wahlstrom | Programmable logic arrays, cheaper by the millions[END_REF]. By loading a bitstream to the SRAM cells, both the logic functionality and the interconnect configuration can be altered. Although a programmable architecture with the most flexibility is established, a large portion of the device has to be allocated for the SRAM configuration cells compared to ROM implementations. Thus, the development of a commercial product had to be postponed until the transistor cost became affordable. Today's classical FPGA was first announced by Xilinx in 1986 [START_REF] Carter | A user programmable reconfiguration gate array[END_REF]. The device capacity and complexity had grown tremendously ever since.

FPGA Architecture and Hardware Structures

The conventional FPGA design consists of programmable logic blocks to implement logic functions, programmable routing to create interconnects between these functions and I/O blocks to make off-chip connections. The generalized view in Fig. 2

Logic Blocks

LBs provide the basic computation capability and storage cells that are used in digital systems. The LB architecture can be built using various granularities. On one end, the logic block can be built using simple transistor pairs proposed by Crosspoint as in Fig. 2.2 [START_REF] Marple | An mpga compatible fpga architecture[END_REF]. With this very fine-grained approach, routing resources occupy very large area resulting in reduced area efficiency, low performance, and high power consumption. Conversely, an entire processor can build the LB. With this approach, the flexibility of the customizable hardware suffers and implementing smaller circuits results in area inefficiency. Several LB designs have been proposed which fit in between these extreme ends of granularity. In the literature, LBs built with transistors [START_REF] Marple | An mpga compatible fpga architecture[END_REF],

NAND gates [START_REF]Era60100 preliminary data sheet[END_REF], multiplexers [START_REF] Ae | Two-dimensional stochastic model for interconnections in master slice integrated circuits[END_REF], Look-Up Tables (LUT) [START_REF] Carter | A user programmable reconfiguration gate array[END_REF] and PAL-like planes [START_REF] Wong | A 5000-gate cmos epld with multiple logic and interconnect arrays[END_REF] can be found. These architectures affect three key parameters of FPGAs: total area, critical path delay, and total power consumption.

Most commonly used LB is a LUT-based design. Basically, as in Fig. 2.3 the LB

BACKGROUND AND MOTIVATION

) !)

Transistor Pair can be configured as one 6-input LUT or two 5-input LUTs as long as some inputs are shared among the two LUTs. Functions up to 8 inputs can be implemented using multiplexers to combine the output of two LUTs.

Altera uses the logic blocks called Logic Array Blocks (LABs). Several Adaptive Logic Modules (ALMs) are interconnected in the LAB. Fig. 2.7 depicts the Stratix-V ALMs [6] which has a variety of LUT-based resources that can be divided between two combinational Adaptive LUTs (ALUTs) and four registers. An ALM can implement various combinations of two functions up to eight inputs when some of the inputs are shared. An ALM also includes two dedicated full adders and the interconnections necessary to create a carry chain with the neighboring ALMs.

Conventionally, FPGAs were built with LUT4s because the LBs with LUT4 gives the best area-delay product [START_REF] Singh | The effect of logic block architecture on fpga performance[END_REF]. Increasing the LUT size decreases the delay because of the reduced global routing complexity but results in increased overall FPGA area.

Latest commercial FPGAs, on the other hand, employ larger LUTs. In these FPGAs, the inherent area cost of increasing the LUT size is reduced by the utilization of fracturable LUTs [32][33]. These LUTs can be configured into smaller sizes and packed together efficiently with a combination of shared inputs. As a result, the input muxing cost is greatly reduced and the utilization rate of LBs is improved. When the LUT4s are replaced with fracturable LUT6, Altera [START_REF] Hutton | Fracturable fpga logic elements[END_REF] claims 15% performance improvement

BACKGROUND AND MOTIVATION

XSRef Target S Figure 2S3 A6 with a 12% area overhead and Xilinx [START_REF] Klein | Xilinx -power consumption at 40 and 45 nm[END_REF] shows 15-20% decreased power consumption.

Routing Resource

Programmable routing in the FPGA achieves connections between LBs and I/O blocks. Programmable switches containing SRAM cells connect wires and creates the desired routing. Some FPGA applications are calculation dominated requiring more local connections and other types are I/O dominated requiring long wires to the I/O blocks. The routing resource must be flexible enough to accommodate the application while fulfilling the design constraints. Additionally, in the design, there may be signals like clock and reset which require dedicated interconnect network apart from the routing resource.

Most commonly, FPGAs are designed with island-style routing where the evenly distributed routing resources surround the LB placed in two dimensional mesh structure. LBs have connections to the routing resource on all four sides through wires which form the channel. The detailed routing structure is shown in Fig. 2.8. The channel width is fixed during fabrication. In Fig. 2.8 the channel width, w, is fixed as 4.

In the routing fabric, a variety of segment lengths are included. Depending on the wire length, the segment can make a connection to all the LBs if it is a short wire or it can span more than one LB if it is a long wire. A long wire can be extended to the width of FPGA. Including various segment length, increases the area efficiency. In Fig. 2.9, a routing architecture example includes length 1, 2, and 4 tracks.

A LB input is connected to channel wire segments through the input Connection Block (CB) switches and LB output is connected to the channel through the output CB.

A number of channel wire can connect to the LB input defining the input connection block flexibility, F c,in and the number of wires connected to the LB output defines the output connection block flexibility, F c,out . In Fig. 2.8, only 2 tracks out of 4 are connected to the LB input, meaning that the F c,in = 2/4 and the LB output is only connected to 1 track, making F c,out = 1/4.

A Switch Block (SB) creates the connections of wire segments at the channel intersections where the horizontal and vertical channels meet. The number of possible connections between adjacent segments define the switch block flexibility, F s . In Fig. connection styles different switch types have been proposed [START_REF] Joseph | Architectures and Algorithms for Field-programmable Gate Arrays with Embedded Memory[END_REF]. Universal, disjoint, and Wilton have been the most popular types.

Apart from the connection pattern, the type of the switches that are used in the SB affects the routing architecture performance. Many FPGA architectures have been developed using pass transistors and tri-state buffers as routing switches [START_REF] Lemieux | Directional and single-driver wires in fpga interconnect[END_REF]. These switches support bidirectional wire segments and each segment can be driven by multiple switches. Fig. 2.10 illustrates the bidirectional routing architecture. The use of bidirectional segments can leave up to 50% of the total switches unused because only one tri-state buffer can be programmed for each segment. A unidirectional approach is now widely used instead, which contains wire segments driven in a single direction. As depicted in Fig. 2.11, multiplexers are used to connect the tracks. Memory cells are connected to the select signals of the multiplexers as shown in Fig. 2.12. The unidirectional approach while reducing the flexibility of the individual routing segments, was found to be advantageous for both area and performance reasons. The area reduction is achieved mainly due to the increased utilization rate. Delay is improved because less buffers are utilized and the driving strength of the multiplexers are higher than tri-state buffers.

Logic Block Logic Block

Logic Block Logic Block Routing Driver Block

FPGA Configuration Techniques

One of the main defining features of FPGAs is its ability to be configured according to the application needs by the end user. In this section, we will review available approaches and technologies to FPGA programmability.

Each configurable element in an FPGA includes 1 bit of storage. The programmable locations maintain the contents of logic block and the connectivity of the routing fabric.

Configuration of the FPGA is achieved by programming the storage bits connected to these programmable locations. For the LUTs, the memories are filled with 1s and 0s based on the desired function. For the routing fabric, programming connects and disconnects the switches along the wires.

There are several configuration techniques in the literature with significant effects on the programmable architecture. Most popular approaches for FPGA programmability are discussed as follows.

SRAM

The most widely accepted method for storing the configuration information by the FPGA vendors is the SRAM based programming technology. SRAM-based solution has received attention because it provides re-programmability with fast configuration in a well-known standard CMOS process technology. In these FPGAs, static memory cells are distributed throughout the FPGA to provide configurability.

Traditionally 6T are used for the SRAM functionality. However, in FPGAs the configuration is constantly connected to the succeeding programmed transistor. Thus, one of the access transistors becomes obsolete which leads to the adoption of 5T SRAM cells in FPGAs. The fig. 2.13 shows a 5T-SRAM cell.

SRAM cells are inherently volatile. Since the configuration information is lost at each power down, the SRAM cells have to be configured at each start up. Hence, external devices are required to permanently store the configuration data. At the power on, the configuration has to be transferred to the FPGA which requires very long cycles and consumes a significant amount of energy. Thus, these external devices not only adds extra cost and area overhead to FPGA but also requires long boot-up time and high power.

FPGA Background

Flash

Instead of the SRAM-based configuration nodes, flash or EEPROM-based programming technology can be integrated in the FPGA. This solution offers non-volatile operation. Thus, the FPGA remains configured with user-defined logic when the power is cut off and it does not require extra storage or devices. Further, Flash memory cells can be realized with fewer transistors compared to SRAM cell. However, flash solution is facing several drawbacks: 1)additional masks due to non-standard CMOS process and complex CMOS co-integration. 2) higher voltage requirement for write operation and slow access time. 3) finite number of writes and scaling limitations.

Antifuse

A third approach is the use of antifuse for programmability. In this technology, a metal-based link is integrated which is normally open when unconnected and when a high current is applied, the link is melted to form an electrical connection. The main advantage stems from the low area and zero static power consumption as no transistors are required for the connection. Also, the capacitance and the resistance is significantly reduced which results in very low propagation delays. Since the link has undergone a physical transformation, it offers a non-volatile operation. However, because of this transformation, the links cannot be reprogrammed. Thus, FPGAs based on this technology are considered One-Time Programmable (OTP). Furthermore, the fabrication requires non-standard CMOS process. As a result, these antifuse FPGAs have limited exposure in the market.

FPGA Limitations

As explained previously SRAM-based FPGAs are considered as the main market driver and therefore, in this section, the limitations for these FPGAs are discussed in detail.

FPGA Limitations due to Configuration Memory

One of the main feature of FPGAs is the reconfigurability and memory cells are used to grant this feature. Lin et al. quantified the memory overhead of the FPGAs based on a Xilinx Virtex-4 FPGA [START_REF] Mingjie Lin | Performance benefits of monolithically stacked 3-d fpga. Computer-Aided Design of Integrated Circuits and Systems[END_REF]. In Fig. 2.14, authors show that the memories occupy nearly half of the FPGA area. This area overhead makes wirelenghts longer than that of ASICs resulting in higher capacitive loads. Thus, it affects not only the area but also the delay and dynamic power consumption of the FPGA circuit. Another major limitation of the configuration memory is the contribution to the leakage power consumption. Tuan et. al. examined the leakage consumption in Xilinx Spartan-3

FPGA designed in 90nm node [START_REF] Tuan | Leakage power analysis of a 90nm fpga[END_REF]. The breakdown in Fig. 2.15a of leakage power based on the blocks in Spartan 3 shows that the configuration memory has a major effect on the overall FPGA leakage consumption by 38%.

Even though the number of SRAM cells are reduced with architectural improvements such as gate-based LBs [START_REF] Ho | Architecture and design flow for a highly efficient structured asic. Very Large Scale Integration (VLSI) Systems[END_REF] and hard-wired SBs [START_REF] Sivaswamy | Harp: Hard-wired routing pattern fpgas[END_REF], for reconfigurability feature, the memory cells will always be a significant part of FPGA area. Additionally, since these memory cells are used for node configuration, they are distributed on the entire FPGA making it very difficult to use strict SRAM design rules in large SRAM macros. Moreover, the volatile nature of SRAMs highly limit power management possibilities. Consequently, SRAM configuration memory creates a large overhead in total area, performance and power consumption.

FPGA Limitations due to Routing Resource

The dominance of interconnect in FPGA is majorly due to the routing flexibility in order to increase routability of the targeted applications. The routing resource area correspond to more than 75% of the total area which is composed of pre-fabricated wire segments. Each wire segment includes used and unused switches which contribute to the switching capacitance in logic transition. Such periphery does not exist in ASICs.

Thus, there is a direct effect of the routing resource on the delay and dynamic power consumption of the FPGA. The Fig. 2.14 shows that routing resource constitutes 80% of critical path delay. The work of Shang et al. [START_REF] Shang | Dynamic power consumption in virtex™-ii fpga family[END_REF] demonstrates that in FPGAs, 60% of total power consumption are consumed by the interconnect in Fig. 2.15b which differs from that of ASICs where clock networks are usually the major contributor of dynamic power consumption [START_REF] Gary | Practical Low Power Digital VLSI Design[END_REF]. Moreover, the switches contribute to the leakage consumption significantly, following after the configuration memory, by 34% as illustrated in Fig.

BACKGROUND AND MOTIVATION

2.15a. Therefore, the routing resource, while bringing the benefits of flexibility of FPGAs, effects the area, delay, and power consumption of FPGA heavily.

Emerging Technologies

In this section, several emerging technologies are presented. The main focus in on advanced memories and 3D integration. The advantages and disadvantages are discussed including recent applications. method is proposed in order to reduce the write current [START_REF] Koch | Thermally assisted magnetization reversal in submicron-sized magnetic thin films[END_REF]. TAS-MRAM increases the selectivity, scalability and thermal stability [START_REF] I L Prejbeanu | Thermally assisted mram[END_REF]. Recently, spin-torque transfer random access memories (STT-RAM) took attention in the literature due to the advantages it provides over traditional MRAM devices [START_REF] Slonczewski | Current-driven excitation of magnetic multilayers[END_REF]. The schematic of the memory cell is presented in Fig. 2 relaxes the large area requirement of the access transistor. Thus, STT-RAM brings an added benefit of reduced area due to smaller access transistor and simpler design.

Advanced Memories

STT-RAM is one of the preferred MRAM technology and several circuits have already been developed as DRAM replacements. Sony demonstrated 4Kb Spin-RAM in 0.18µm with 10 12 endurance [START_REF] Hosomi | A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram[END_REF]. Hitachi fabricated a 2Mb [START_REF] Kawahara | 2 mb spram (spin-transfer torque ram) with bit-by-bit bi-directional current write and parallelizing-direction current read[END_REF] and 32Mb SPRAM circuits [START_REF] Takemura | A 32-mb spram with 2t1r memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme[END_REF]. Finally, Toshiba released 64Mb memory [START_REF] Tsuchida | A 64mb mram with clamped-reference and adequate-reference schemes[END_REF]. Beyond storage, STT-RAM found interest in logic applications. Several Non-volatile Flip-Flop (NVFF) circuits are analyzed in [START_REF] Na | A comparative study of stt-mtj based non-volatile flip-flops[END_REF]. A full-adder with STT-RAMs is designed in [START_REF] Deng | Low power magnetic full-adder based on spin transfer torque mram[END_REF]. Recently, NEC presented a non-volatile microcontroller in 90nm [START_REF] Sakimura | 10.5 a 90nm 20mhz fully nonvolatile microcontroller for standby-power-critical applications[END_REF].

In summary MRAM technology is one of the candidates for non-volatile memory applications. Estimated STT-MRAM endurance reaches 10 15 as in [START_REF] Tehrani | Magnetoresistive random access memory using magnetic tunnel junctions[END_REF] however highest reported value is 4 × 10 12 [START_REF] Huai | Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects[END_REF]. As scaling continues further in sub 50nm regime, the power density is expected to increase which puts constraint on the write energy [START_REF] Haiwen Xi | Spin transfer torque memory with thermal assist mechanism: A case study[END_REF]. The reported resistive states are low with R low : 2KΩ and R high : 4KΩ [START_REF] Chen | Advances and future prospects of spin-transfer torque random access memory[END_REF].

Moreover as stated in [START_REF] Bi | Stt-ram cell design considering cmos and mtj temperature dependence[END_REF], the performance of STT-RAM is very susceptible to ambient temperature and, thus, it brings challenges for high performance applications.

Phase-Change Memory (PCRAM)

A Phase-Change Memory (PCRAM) cell stores the bit information using the large resistance difference between crystalline (low resistance state) and amorphous (highresistance state). The cell is composed of thin-film chalcogenide material (typically Ge 2 Sb 2 T e 5 -GST) layer in contact with a metallic heater. Fig. 2.17 shows the crosssection of the PCRAM device. When a large electrical current pulse is applied for a time period, the GST material is first melted and then quickly cooled-down forming a highly resistive amorphous region at the boundary of the heater. In this case the cell is said to be reset. In order to set the cell back into crystalline form, GST is heated beyond the crystallization temperature and then cooled-down slowly for sufficient time to crystallize.

Depending on the materials and cell geometry, varied resistance windows, endurance programming current, and durations can be achieved [START_REF] Wong | Phase change memory[END_REF]. Up to five orders of magnitude (10 5 ) resistivity contrast between high and low resistances is observed [START_REF] Wong | Phase change memory[END_REF]. Set operation can be achieved in 200ns with 60µA and reset in 20ns with 200µA [START_REF] Huang | A low active leakage and high reliability phase change memory (pcm) based non-volatile fpga storage element[END_REF].

Recently, an endurance value of 10 10 has been reported [START_REF] Cai | An 8-mb phase-change random access memory chip based on a resistor-onvia-stacked-plug storage cell[END_REF].

One of the major challenges in PCRAM is the requirement of large reset current which puts limitation on scaling beyond 20nm [START_REF] Baldi | Emerging memories[END_REF] and creates thermal disturbs among adjacent bits. The addition of an inter-facial Hf O 2 layer can reduce the current by 80% [START_REF] Hubert | Detailed Analysis of the Role of Thin Hf O 2 Interfacial Layer in Ge 2 Sb 2 T e 5 Based PCM[END_REF] and up to 10x reduction can be achieved with SiO 2 layer [START_REF] Kanán | Computational analysis of rupture-oxide phase-change memory cells[END_REF].

Main PCM applications include DRAM replacement. An 8 Mb memory in 130nm technology is reported in [START_REF] Cai | An 8-mb phase-change random access memory chip based on a resistor-onvia-stacked-plug storage cell[END_REF]. Micron released 1Gb memory in 45nm [START_REF] Baldi | Emerging memories[END_REF]. Samsung fabricated a 8Gb memory in 20nm with 4F 2 cells [START_REF] Choi | A 20nm 1.8v 8gb pram with 40mb/s program bandwidth[END_REF]. Several techniques are proposed to reduce the number of writes due to limited PCM endurance [START_REF] Chen | Rethinking database algorithms for phase change memory[END_REF] especially for cache applications.

Resistive Memory (RRAM)

Various [START_REF] Wong | Metal oxide rram[END_REF].

Two major categories can be identified depending on the switching properties:

unipolar and bipolar as explained in Fig. 2.19. In unipolar memories, the amplitude of the voltage determines the switching direction. In bipolar RRAMs, the switching depends on the polarity of the applied voltage. Classically, switching from high-resistance state (HRS) to low-resistance state (LRS) refers to set and LRS to HRS switching refers to reset.

BACKGROUND AND MOTIVATION

During set operation, high electric field causes the oxygen atoms to drift and creates oxygen vacancies leading to a Conductive Filament (CF). Usually the device goes through a forming process at a higher voltage than set voltage. Although several explanations have been discussed for the understanding of reset operation, a unified mechanism for both unipolar/bipolar modes is proposed [START_REF] Yu | A phenomenological model for the reset mechanism of metal oxide rram[END_REF]. For devices switching in unipolar mode, increased temperature due to the current flowing through, dissolves the oxygen ions either in the bulk to combine with the oxygen vacancies or in the metal boundary to oxidize the metal precipitates. Thus, a larger reset current is necessary.

However, in bipolar mode, the inter-facial oxide layer created at the anode presents a significant diffusion barrier which requires a reverse electric field because pure thermal diffusion cannot overcome the barrier.

Since the high forming voltage imposes difficulties in circuit design, forming free devices have been proposed. Hf O 2 is shown to operate without forming due to the reduced oxide layer thickness at 3nm [START_REF] Lee | Low power and high speed bipolar switching with a thin reactive ti buffer layer in robust hfo2 based rram[END_REF].

RRAMs received interest because of back-end-of-line (BEOL) compatibility and reduced programming current requirement. Compact modeling took effort for fast circuit simulations [START_REF] Bocquet | Robust compact model for bipolar oxide-based resistive switching memories[END_REF]. Several logic applications have been proposed [START_REF] Vianello | Back-end 3d integration of hfo2-based rrams for low-voltage advanced ic digital design[END_REF] with OxRAM cell having 100ns switching time and 10 8 endurance. Samsung reported the highest OxRAM endurance of 10 12 with 10ns switching duration. Panasonic released a 8Mb

OxRAM in 0.18µm technology [START_REF] Kawahara | An 8mb multi-layered cross-point reram macro with 443mb/s write throughput[END_REF]. Recently, Toshiba and Sandisk fabricated a 32 Gb OxRAM in 24nm tehnology [START_REF] Tz Yi Liu | A 130.7mm2 2-layer 32gb reram memory device in 24nm technology[END_REF].

Conductive-Bridge Memory (CBRAM)

CBRAMs, also known as Programmable Metallization Cell (PMC) [START_REF] Symanczyk | Electrical characterization of solid state ionic memory elements[END_REF] or NanoBridge [START_REF] Sakamoto | A ta 2 o 5 solid-electrolyte switch with improved reliability[END_REF] Several works target the application of CBRAMs in the literature. NEC demonstrated a novel 1T1R CBRAM cell [START_REF] Sakamoto | A ta 2 o 5 solid-electrolyte switch with improved reliability[END_REF] with a very low on resistance of 50Ω to be included in FPGA. A 1T2R memory cell for FPGA configuration memory is proposed and different material stacks are compared to achieve reduced leakage current and footprint [START_REF] Palma | Interface engineering of ag-ges 2 -based conductive bridge ram for reconfigurable logic applications[END_REF]. Furthermore, the cell is characterized under various voltage levels and it is shown that the cell can be configured with distinctive resistance values (R ON :4kΩ -10kΩ, R OF F :10 6 Ω -10 8 Ω). Various materials have been considered when constructing the stack in different process nodes resulting in different resistance levels and endurances [START_REF] Valov | Electrochemical metallization memories-fundamentals, applications, prospects[END_REF]. ALTIS fabricated a 2Mb CBRAM memory core in 90nm technology with 10 11 Ω R of f resistance [START_REF] Dietrich | A nonvolatile 2-mbit cbram memory core featuring advanced read and program control[END_REF]. Taking advantage of high resistance window and well-separated resistance values, Multi-Level Capability (MLC) of CBRAM has been investigated for R ON between 10 3 Ω -10 6 Ω with programming currents ranging from 100nA to 100µA [START_REF] Kund | Conductive bridging ram (cbram): an emerging non-volatile memory technology scalable to sub 20nm[END_REF]. Using the MLC concept, ALTIS fabricated a 4Mb CBRAM memory in 90nm with 4F 2 1T1R cells programmable under 1.4µs. Recently, the crossbar concept is revisited with CBRAM-based cells using the high resistance advantage of CBRAMs to overcome the sneak-path problems and increase selectivity [START_REF] Wang | Nonvolatile cbram-crossbar-based 3-d-integrated hybrid memory for data retention. Very Large Scale Integration[END_REF].

Ferroelectric Ram (FRAM)

FRAM cell is composed of ferroelectric capacitor, similar to DRAM (1T1C) to store the logic value of either 1 or 0 in the form of positive or negative polarization

BACKGROUND AND MOTIVATION

charge states of ferroelectric dielectrics made of peroskite films such as P bZr

x T i 1-x O 3 (

Discussion

Reconfigurability in FPGAs brings the main advantage but at the same time it is the main drawback. The configuration memory cells occupy almost half of the chip, imposing deterioration on performance and power consumption due to the increased routing wirelengths and complexity. Configuration memories are, thus, the main target of emerging memory technologies in FPGAs. A comparison of emerging memories is illustrated in Table 2.1.

PCRAM, RRAM, and CBRAM cells provide area advantages due to the achievable 4F 2 memory cell footprint. MRAM cells have larger footprints which results in less area improvement. Smaller cell area means that the memory overhead is less in FPGA which not only decreases total area but increases performance and power efficiencies.

Endurance is a metric which indicates how many times the memory cell can be written. Normally, in FPGAs, the bitstream is created once for an application. The bitstream can then be stored in the non-volatile memories which avoids consequent write operations if the same bitstream is preserved. If the FPGA executes with many different applications and bitstreams, a high endurance value is desired. Even though the highest demonstrated endurance is 10 12 for MRAMs, 10 15 values are expected.

PCRAMs and CBRAM under perform in endurance with 10 6 . RRAM endurance can reach similar levels as that of MRAM with 10 12 cycles.

R low /R high (Ω) 10K/2M 1K/100K 10K/10G 2K/4K

BACKGROUND AND MOTIVATION

In terms of resistance values, CBRAMs reach the highest R of f with low R on ensuring the largest resistance window. Large resistive window increases design possibilities as it improves selectivity when integrated in a circuit.

When several write operations are requested to the memory, write energy plays a significant role in the total power consumption. Thus, the write energy consumption should be analyzed considering the target application. Compared to CBRAMs and RRAMs, MRAMs and PCRAMs have higher power consumptions during programing stage. It should be also noted that thermal effects due to the programming in MRAM and PCRAM might present reliability degradation on the surrounding transistors.

In comparison to other technologies, CBRAM and RRAM present small footprint, low write current, and thermal stability required for dense CMOS integration. Furthermore, RRAM reaches high endurance values and CBRAM provides large resistance window. Considering these properties, FPGAs can take significant benefits from RRAM and CBRAM integration.

3D Integration

With exponentially increasing cost of new technology nodes, 3D integration becomes an appealing solution for "low cost" scaling. 3DICs provide performance benefits as improved packing density, noise immunity, optimized total power consumption due to decreased wire length/lower capacitance, increased performance, and more functionalities [START_REF] Topol | Three-dimensional integrated circuits[END_REF]. Theoretically, introducing the third dimension brings the possibility to decrease the wirelength by a factor N 1/2 tiers , delay by N tiers and power by N

1/2
tiers where N tiers is the number integrated tiers [START_REF] Davis | Demystifying 3d ics: the pros and cons of going vertical[END_REF]. Previously, several fabrication methods have been proposed for 3D integration based on design trade-offs such as wire bonded integration, microbump and through via [START_REF] Davis | Demystifying 3d ics: the pros and cons of going vertical[END_REF]. Through Silicon Vias (TSV) [START_REF] Koyanagi | High-density through silicon vias for 3-d lsis[END_REF] have potential due to the higher interconnect density it provides. On the other hand, recently developed 3D Monolithic Integration (3DMI) [START_REF] Batude | 3d monolithic integration[END_REF] technology achieves the highest interconnect density.

In TSV-based technologies, chips are processed with TSVs and integrated into 3D stacks either at the wafer or die level [START_REF] Karnik | Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration[END_REF]. The dies or wafers are thinned to typically 50 -100 µm before bonding. Depending on the top layer orientation during the process, the assembly can be face-to-face if the top of the second layer faces the top of the bottom layer and face-to-back if the bottom of the second layer faces the top of the bottom layer as demonstrated in Fig. 2.21 [START_REF] Topol | Three-dimensional integrated circuits[END_REF]. Following the bonding process Si is etched to form the TSVs connecting the two layers. Face-to-face bonding option requires creation of high-density Cu-Cu bonded links as well as deep TSVs to bring the signals out of the package. On the other hand, face-to-back relaxes the requirements for alignment as it has the largest via dimensions and thus lowest via density. The process of TSV-based assembly imposes difficulties in wafer thinning, alignment, bonding, TSV fabrication and thermal dissipation. In order to overcome the wafer handling problems during the bonding process wafers cannot be thinned below 50 µm increasing the demand for highaspect ratio TSVs for smaller via surface. At the same time, large alignment tolerance restricts having smaller vias. Typically, the alignment achieved is 0.5 -1µm resulting in a TSV size with 2 -4µm.

Recently developed 3D Monolithic Integration consists of sequential fabrication of active layers on the same die. Fig. 2.22 shows the cross-sectional view of 3DMI. Since the inter-tier vias are fabricated same as regular vias between metals, the process alignment is only limited with lithography. An alignment tolerance of 10nm is achievable resulting in an inter-tier via diameter of 100nm [START_REF] Jung | Highly cost effective and high performance 65nm s3 (stacked single-crystal si) sram technology with 25f2, 0.16um2 cell and doubly stacked sstft cell transistors for ultra high density and high speed applications[END_REF]. Thus, high-granularity and less capacitive vertical interconnects are obtained with 3DMI. Technological properties of TSV-based integration and 3DMI are summarized in Table 2.2. The size of the vertical vias in the technologies determines the achievable granularity. The TSV pitch of 4µm yields an interconnect density of ∼ 60k TSVs/mm 2 whereas in 3DMI ∼ 1.2M inter-tier vias/mm 2 can be fabricated. Consequently, the number of TSVs between two layers can only support coarse/medium grain partitioning. On the contrary, very fine grain partitioning is achievable with 3DMI. Fig. 2.23

shows partitioning on different granularity levels. At coarse grain level, core-on-core type integration is more suitable due to the reduced number of required vertical interconnects. In this case 3D TSVs provide efficient integration. As the granularity is increased, ex. gate-on-gate integration, high number of vertical interconnects is required. Since TSVs occupy large area due to alignment limitations, 3DMI becomes an ideal choice for 3D circuits with high density interconnects.

In circuit design, TSVs can provide performance advantages by reducing the wire lengths and placing the functional units closer. In [START_REF] Gabriel | Processor design in 3d die-stacking technologies[END_REF], a 1mm long wire is replaced with a TSV and the delay is reduced from 225ps to 8ps. A number of works focused on circuit level gains with TSVs. Samsung [START_REF] Kang | 8gb 3d ddr3 dram using through-silicon-via technology[END_REF] demonstrated a TSV-based four layer 8Gb DRAM memory with 50% less standby and 25% less active power while reaching an I/O speed more than 1600Mb/s. In [START_REF] Black | Die stacking (3d) microarchitecture[END_REF], 3D DRAM stacking on Pentium 4 core increases the performance by 15% with 15% less power consumption with an 14 o C elevated operating temperature.

Compared to TSV-based circuits, there are few works related to design with 3DMI.

Jung et al. fabricated their SRAM design with single-crystal thin-film-based process [START_REF] Jung | Highly cost effective and high performance 65nm s3 (stacked single-crystal si) sram technology with 25f2, 0.16um2 cell and doubly stacked sstft cell transistors for ultra high density and high speed applications[END_REF]. Thomas et al. demonstrated an SRAM design in 45nm with placing PMOS and NMOS transistors seperately resulting in 20% area gain [START_REF] Thomas | Compact 6t sram cell with robust read/write stabilizing design in 45nm monolithic 3d ic technology[END_REF]. Golshani et al.

fabricated monolithically integrated silicon layers of SRAM and image sensors [START_REF] Derakhshandeh | Monolithic 3-d integration of sram and image sensor using two layers of single-grain silicon[END_REF]. In [START_REF] Liu | A design tradeoff study with monolithic 3d integration[END_REF], various design tradeoffs in 3DMI are studied and they are compared with TSVbased integration. The power benefits of 3DMI are discussed in [START_REF] Lee | Power benefit study for ultra-high density transistor-level monolithic 3d ics[END_REF]. Several design techniques have been developed in order to design 3D circuits with existing 2D standard cell libraries [START_REF] Bobba | Celoncel: Effective design technique for 3-d monolithic integration targeting high performance integrated circuits[END_REF][93].

FPGA with Emerging Technologies

In the previous section, various emerging technologies have been reviewed. The main focus is on the emerging nonvolatile memories and 3D integration. In this section, related works on FPGAs with emerging technologies are presented as Non-Volatile Memory (NVM)-based FPGAs and 3D-FPGAs.

NVM-based FPGAs

Reconfigurable circuits such as FPGAs can be designed with nonvolatile STT-RAM- FPGA design with gains 11% in area, 11% in delay and 16% in power consumption [START_REF] Paul | A circuit and architecture codesign approach for a hybrid cmos sttram nonvolatile fpga[END_REF].

A number of works focused on PCRAM-based FPGAs. Simulations are carried out to prove the performance gains when the PCMs are integrated in FPGAs [START_REF] Gaillardon | Emerging memory technologies for reconfigurable routing in fpga architecture[END_REF][99] [START_REF] Huang | A low active leakage and high reliability phase change memory (pcm) based non-volatile fpga storage element[END_REF].

In [START_REF] Gaillardon | Emerging memory technologies for reconfigurable routing in fpga architecture[END_REF], a novel PCM-based switchbox is presented where the pass transistors are replaced with PCRAMs. In [START_REF] Chen | 3d-nonfar: Three-dimensional non-volatile fpga architecture using phase change memory[END_REF], PCRAMs and TSVs are integrated and 2-layer FPGA is simulated. Unfortunately, the result is very optimistic because the PCRAM access transistor is not taken into account in the area model. Moreover, as scaling continues the TSV overhead will become higher which decreases the area benefits. In [START_REF] Huang | A low active leakage and high reliability phase change memory (pcm) based non-volatile fpga storage element[END_REF]

3D-FPGAs

The benefits of 3D integration are especially greater for designing FPGAs compared to other logic circuit applications, since FPGAs suffer from communication overhead: the interconnect delay and power are the main bottlenecks compared to ASIC alternatives. With 3D, the wirelenghts can be extremely reduced which results in increased performance with lowered power consumption. Furthermore, the replicated architecture of FPGAs ensure fast adoption of 3D technologies and efficient scalability.

In the literature a number of works has shown interest in the FPGA with TSV integration. In this case, multiple layers of FPGA tiles can be stacked. In [START_REF] Gayasen | Designing a 3-d fpga: Switch box architecture and thermal issues. Very Large Scale Integration[END_REF],

different 3D switch box topologies are surveyed. Since more complex switch boxes are required, the improvement of delay is limited to 10% when two layers are considered.

There are several works which focus on decreasing the number of TSVs in order to reduce area and delay [105][106]. A novel approach placing the I/O and logic resources in different layers improves the maximum frequency by 26% [START_REF] Sidiropoulos | A novel 3-d {FPGA} architecture targeting communication intensive applications[END_REF]. Finally, a tool called TPR is developed for placement and routing of FPGA benchmarks with TSVs [START_REF] Ababei | Placement and routing in 3d integrated circuits[END_REF]. Hamada et al. designed an FPGA using face-to-face integration with 30% less critical path delay on a 48% smaller footprint [START_REF] Hamada | Threedimensional stacking fpga architecture using face-to-face integration[END_REF] where the technological properties of TSV and microbumps are not included in the evaluation. Therefore, the research for TSV-based FPGAs has been carried out in different levels and perspectives.

Silicon interposers are proposed as a low cost solution node between 2D and 3D.

FPGA vendor Xilinx has released an FPGA fabricated on interposer [START_REF] Banijamali | Advanced reliability study of tsv interposers and interconnects for the 28nm technology fpga[END_REF]. In this work, the TSV aspect ratio is reduced to 10 with increased yield. Several slices, which correspond to a group of FPGA tiles, are integrated on the passive interposer. As a result, the fabricated slice circuit surface is reduced which increases the yield of each slice.

Recently, a number of works focused on monolithically integrated FPGAs. Naito et al. demonstrated the first 3D FPGA design with monolithic integration in 90nm by placing TFT-based configuration SRAM cells in the BEOL [START_REF] Naito | World's first monolithic 3d-fpga with tft sram over 90nm 9 layer cu cmos[END_REF]. Due to the large footprint of the SRAMs with TFTs, an underoptimized tier utilization is expected. In [START_REF] Mingjie Lin | Performance benefits of monolithically stacked 3-d fpga. Computer-Aided Design of Integrated Circuits and Systems[END_REF], authors show improvements depending on several different stacking scenarios of FPGA blocks. The blocks are separated based on the area estimation and evaluations up to 3 layers are carried out with technological assumptions. Assuming smaller area in 3 layer stack, the results show improvements of 69% area, 41% delay and 41% power reduction. In [START_REF] Batude | 3-d sequential integration: A key enabling technology for heterogeneous co-integration of new function with cmos. Emerging and Selected Topics in Circuits and Systems[END_REF], a switchbox with memory and logic separation is presented different benchmarks are evaluated on the FPGA. The overall effect of the proposed 3D SB on the FPGA is estimated as reduced delay by 22% and area by 21%.

Conclusion and Work Positioning

FPGAs have received remarkable attention in the digital circuit domain due to their reconfigurable, high-performance, and low-cost solutions. However, compared to ASICs, the reconfigurability comes with overheads in area, performance and power consumption. It is worth noting that FPGAs are designed by replicating the tilebased units which offers a scalable implementation. FPGA design is also accompanied by efficient tools which can define the FPGA architecture in detail. These properties create a very efficient platform for advanced technologies. Industry trends have already shown that FPGAs are usually the first applications for new technologies and, thus, well-suited for fast adoption of emerging technologies.

Emerging memories provide a unique feature of non-volatility in a very small form factor with CMOS-compatible integration. Several nonvolatile memory technologies

Conclusion and Work Positioning

have been surveyed and it is observed that, the properties of these memories vary in a wide range. When designing with these memories, it is extremely important consider the device properties and, then, evaluate FPGA level implications. CBRAM and OxRAM technologies offer promising results small footprint, low write current, and thermal stability required for dense CMOS integration. Furthermore, with nonvolatility, FPGAs can support a very efficient power reduction mechanism. Conventional FPGAs offer very limited power management. The main limitation stems from the volatile memories. Even though significant leakage reductions can be achieved with technological improvements, until the power supply is cut off, the leakage cannot be completely reduced to zero and when power gating is applied, configuration memories lose their information. Therefore, with non-volatile memories, FPGA power consumption can be efficiently reduced.

Logic design in the third dimension addresses the difficulties of traditional CMOS scaling. FPGAs in this case can highly benefit due to their regular architecture. As explained before, TSV and 3DMI are the candidate technologies for 3DIC design. Previous works with TSV integration shows limited improvements on FPGA while the only mainstream application is the yield improvement with the inclusion of interposers. It can concluded that FPGAs clearly need high-granular 3D interconnects due to their communication dominated nature which cannot be fulfilled by the available TSV integration. Due to the very-high granular interconnects proposed by 3DMI, FPGAs can gain more advantages. When emerging technologies are targeted, it is mostly impossible to explore all the design possibilities by designing and optimizing with these technologies and measuring the performance metrics from the fabricated FPGA circuits. Therefore, a fast, reliable, and flexible FPGA evaluation environment is indispensable.

FPGA Evaluation with Emerging Technologies

FPGA vendors use their own environments for the development of the FPGAs. The tools in these environments are optimized for the specific architectures offered by the vendors. Therefore, it is not possible to evaluate different architectures with these tools.

In the academia, some research effort has been spent to develop a toolflow which uses a parameterized FPGA fabric. Commonly, an empirical approach is employed to study and explore different architectures. In this approach, application benchmark circuits are mapped into the FPGA fabric to determine the area, speed, and power benefits of the developed FPGA architecture as illustrated in Fig. 3.1.

FPGA Computer-Aided Design (CAD) flow in Fig. 3.1 fills the gap between highlevel application and the low-level implementation. The flow has to map the functionality into a predetermined architecture of logic and routing resources. The CAD tools, which are used to configure the programmable logic and routing switches of the FPGA, have a significant impact on speed, area and power of an application. Hence, the tools have to closely follow the low-level implementation properties in order to optimize the application mapping.

The architecture definition includes all architectural properties and technology dependent parameters. The flow in Fig. 3.1 was used for the exploration of architectural modifications such as LUT size, cluster size, channel width etc. Beyond that, the architecture definition also provides enough flexibility for evaluation with technology dependent details such as the delay of the connection box, the resistance and the capacitance of the switches, the leakage current of the memory cell etc. Thus, by modifying the architecture definition, not only architectural modifications but also technological improvements can be imposed in the FPGA evaluation.

Several emerging technologies are presented in the Section 2.3.. Before designing FPGAs with these technologies, an evaluation platform has to be established. Therefore, in this chapter, first an FPGA CAD flow is assembled. This flow produces the design comparison metrics; area, delay, and power, at the output of each evaluation run. In order to evaluate different architectures, architecture definition, which is an input to the flow, has to be generated accurately. Thus, a methodology is developed for creating the architecture definition for FPGA evaluation using emerging technologies. Consequently, with this evaluation platform, FPGA fabric can be designed with emerging technologies and several benchmark circuits can be evaluated with this fabric to assess the potential improvements from these technologies.

In this chapter, first section describes the typical FPGA CAD flow. The next section presents the FPGA experimental evaluation framework, which is used in this thesis.

The architecture definition, modeling for area, performance, and power, and MCNC benchmark circuits are also explained. The final section provides the development of architecture definition necessary for the adoption of emerging technologies.

CAD for FPGAs

Usually, the functionality of FPGA is defined at a higher level of abstraction, generally with a hardware descriptive language (such as VHDL or Verilog). Computer-aided design (CAD) tools transform this high-level descriptions into configuration bitstreams.

Circuits are, then, mapped into FPGAs using the bitstreams which contain the state information of each configuration point defining the connections in routing resource and the logic functionality in Logic Blocks (LB). FPGA CAD flow consists of sequential execution of several tools. A typical CAD flow is illustrated in Fig. 3.2 and described in the following sections.

Technology Mapping

The resulting netlist from front-end synthesis is a circuit definition using Boolean gates, flip-flops and connecting wires. Before mapping, various technology-independent techniques are applied to optimize boolean network. Removing redundant gates and simplifying netlist help to reduce area utilization and switching nets. After this optimization step, for a given netlist, technology mapping can be expressed as finding a network of cells using the cell library associated with the target technology. In the case of FPGA logic, the cell library is composed of Look-Up Tables (LUT) and Flip-Flops (FF). Therefore, technology mapping in FPGAs refers to transforming the Boolean netlist into LUTs. Each cell is then implemented with a k-input LUT (K-LUT). Since a K-LUT can implement any K-input function, the mapping task of a Boolean network to a LUT is simply choosing a set of K-feasible cuts that include all the nodes in the network. Depending on the objectives, technology mapping algorithms can optimize the design for logic depth, area and power. SIS [START_REF] Sentovich | Sis: A system for sequential circuit synthesis[END_REF], FlowMAP [START_REF] Cong | Flowmap: an optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs[END_REF] and ABC [START_REF] Synthesis | Abc: a system for sequential synthesis and verification, release 70930[END_REF] tools have been proposed to address the technology mapping problem. The cut algorithm in ABC produces much lower literal count.

Packing

In typical FPGAs a hierarchical structure is used for logic blocks. In the first stage, logic functions are mapped into the K-LUTs, which, along with the corresponding FF, Thus, a trade-off can be defined using cluster and the LUT size. When too many BLEs and large LUTs are clustered, the area efficiency decreases because the CLBs cannot be fully utilized and the critical path suffers because of the increase area. In the case of small or no clusters and small LUTs, the delay is dominated by the global connections.

It has been proven that for highest efficiency in area and delay, 4-6 input LUTs are included in the BLEs with 4-10 BLEs in the LBs [START_REF] Ahmed | The effect of lut and cluster size on deep-submicron fpga performance and density. Very Large Scale Integration (VLSI) Systems[END_REF].

FPGA EVALUATION WITH EMERGING TECHNOLOGIES

Clustering algorithms can be categorized mainly into three approaches: top-down [START_REF] Hagen | Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning[END_REF], depth-optimal [START_REF] Eslami | The effect of cluster packing and node duplication control in delay driven clustering[END_REF] and bottom-up [120] [121]. In FPGA CAD flow, bottomup is the preferred approach due to its fast and simple execution because they only consider local connectivity and can satisfy the LB pin constraints.

The VPack algorithm is proposed using the bottom-up approach [START_REF] Marquardt | Using cluster-based logic blocks and timing-driven packing to improve fpga speed and density[END_REF]. In this algorithm, the clusters are built sequentially one at a time. For each cluster, an attraction function ise used to select a seed LB from the available set of LBs and new LBs related to the seed LB are selected until the cluster is full or all the cluster inputs are exhausted. A timing-driven version of VPack is the T-VPack algorithm [START_REF]Architecture and CAD for Deep-Submicron FPGAs[END_REF]. The clustering algorithm is identical to VPack whereas the attaction function selects the seed LBs which are on the critical path rather than the LBs with the most used inputs as in VPack. Other algorithms include RPack [START_REF] Bozorgzadeh | Rpack: routability-driven packing for cluster-based fpgas[END_REF], T-RPack [START_REF] Bozorgzadeh | Rpack: routability-driven packing for cluster-based fpgas[END_REF], iRAC [START_REF] Singh | Efficient circuit clustering for area and power reduction in fpgas[END_REF], multi-level clustering [START_REF] Cong | Performance-driven multi-level clustering with application to hierarchical fpga mapping[END_REF] and simultaneous mapping-clustering [START_REF] Lin | Optimal simultaneous mapping and clustering for fpga delay optimization[END_REF].

Placement

Placement determines the best on-chip location for every resources (ex. LB) based on the netlist produced by the clustering algorithm. The optimization goals are to reduce wire length by placing connected logic blocks close together (wire length-driven placement), and sometimes to balance the wiring density between blocks (routabilitydriven placement) or to minimize the critical path delays (timing driven placement).

Placement approaches can be categorized by three classes: min-cut (partitioningbased) [START_REF] Dennis | Partitioning-based standard-cell global placement with an exact objective[END_REF], analytic [START_REF] Alpert | Faster minimization of linear wirelength for global placement[END_REF], and simulated annealing [START_REF] Sechen | The timberwolf placement and routing package. Solid-State Circuits[END_REF]. Among all approaches simulated annealing is preferred because its algorithm is more adaptable to new opti-

Routing

In the final stage of FPGA CAD flow, all the nets are assigned to the prefabricated configurable routing resources in a way that only one net corresponds to one routing resource. The main objective is to minimize the critical path delay while avoiding congestion. Choosing direct connections and balancing the usage of routing wires ensure congestion-free routing. Delay minimization is achieved by routing the high-criticality nets first in the case of contention for a given resource.

Routing algorithms are categorized with two approaches: two-step routing [START_REF] Guy | On two-step routing for fpgas[END_REF] [132] which performs detailed routing after global routing and combined global-detailed routing [7] [133] which is performed in a single step. In FPGAs, typically, two-step approach is not preferred due to the difficulty in detailed routing as a result of the limited flexibility of the routing fabric. In single-step approach, during global routing, nets are assigned between logic block pin and routing channel, and during detailed routing, wire segments in a routing channel are assigned to nets. The routing of a circuit is generally represented by a directed graph, where each wire source node must be connected to its sink nodes without any overlapping and often, directed search algorithm is included for efficient analysis of routing graph.

VPR [START_REF] Betz | Vpr: A new packing, placement and routing tool for fpga research[END_REF] router is the most commonly used router in academic research. The routing algorithm is based on PathFinder [START_REF] Mcmurchie | Pathfinder: A negotiation-based performance-driven router for fpgas[END_REF]. In the router, an iterative routing algorithm is adopted which routes nets using minimum costs even though the solution may lead to congestion in some routing channels. Next the cost function is adjusted to increase the penalty of routing through congested resources. This process continues until a congestion free routing is achieved. The cost function includes a delay term and a congestion term. Thus, the cost function in VPR can optimize either the routability or performance. In routability-driven router, the cost function minimizes wirelength by limiting each net to use the fewest number of routing resources possible. In timingdriven router, the cost function assigns timing critical nets to use the fastest routing resource.

Experimental FPGA Evaluation Framework

A toolflow for FPGA CAD can be assembled using the previously discussed tools.

The experimental process used in typical VPR-based flow is illustrated in Fig. 3.3.

All the tools included are open-source which allows evaluation on various different architectures unlike the commercial tools which are targeted for specific architectures.

The toolflow takes a benchmark circuit and an FPGA architecture definition to implement the design and evaluate on a specified FPGA. ODIN is used as the frontend synthesis tool to convert high-level description (ex. VHDL) into flattened BLIF netlist. ABC tool takes the BLIF netlist and maps all the logic circuits into LUTs.

Since ABC does not connect the clock signals to the FFs in the BLEs, a latch binding script is executed to allow evaluation with sequential circuits. ACE2.0 [START_REF] Lamoureux | Activity estimation for field-programmable gate arrays[END_REF] performs the switching activity estimation which is necessary for power evaluation. A modified version of T-VPack [START_REF] Kara | A flexible power model for fpgas[END_REF] enables to cluster considering switching activities. VPR5 with

Power Extension [START_REF] Jamieson | An energy and power consumption analysis of fpga routing architectures[END_REF] accomplishes placement and routing of the circuit and extracts estimations of area, delay, and power.

VPR5 [START_REF] Luu | Vpr 5.0: Fpga cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling[END_REF] offers several advantages in the evaluation framework. Similar to previous VPR, timing-driven placement and routing algorithms are included. Furthermore, The remaining of this section discusses the architecture definition for design under evaluation, the estimation approach for area, delay, and power, and the MCNC benchmark circuits.

Architecture Definition

In general, tools cannot directly take the transistor size definitions of the FPGA fabric for correct evaluation. Typically, an architecture definition file is included in the evaluation toolflows. This file provides the freedom to define various FPGA architectures using parameters for LB organization, CB connectivity, and SB topologies, and technological characterization such as transistor capacitance, resistance, and area. For the toolflow defined in section 3.2., the architecture file can be defined as in 3.4. The device section defines the generic FPGA fabric such as LB area and SB topology. In the following parts, the routing resource properties are defined such as switch capacitance and segment properties. In the architecture, a simple timing model such as the delays of the switches in SB and CB are also included. For power calculations, parameters such as transistor parasitics, supply voltage level, and memory leakage are given.

Area, Delay, and Power Estimation

Area, delay, and power estimations of the FPGA circuit are obtained with the toolflow in Fig. 3.3. After generating an FPGA architecture with the definition discussed previously, VPR5 first places and routes the circuit and then extracts area, delay, and power based on the models implemented in VPR5.

VPR models area by accumulating the area of all the transistors in the FPGA including the routing resource, LBs, clock network, and configuration memory. The area approximation is achieved using Minimum Transistor Equivalents (MTE) metric as defined in [START_REF]Architecture and CAD for Deep-Submicron FPGAs[END_REF], which calculates the layout area occupied by a minimum sized transistor plus the minimum spacing.

The delay is modeled after routing is completed. Based on the architecture definition, using the intrinsic delay of LBs and routing resource components, a directed graph is constructed. The capacitance and resistance of each node are then extracted based on the final routing. Thus, an RC equivalent is assigned to each node and the delay estimate of the critical path is calculated by Elmore delay model [START_REF]Architecture and CAD for Deep-Submicron FPGAs[END_REF].

For power consumption modeling dynamic, short circuit, and leakage power have to be estimated. The dynamic power component depends on the activity of the node.

The switching activity of the node implies how of the associated capacitance of node charges and discharges which directly affect power dissipation. For switching activity estimation the tool called ACE2.0 [START_REF] Lamoureux | Activity estimation for field-programmable gate arrays[END_REF] is included in the framework as shown in Fig. 3.3. ACE2.0 takes the technology-mapped netlist and determines the switching activity of each node in the circuit. Since the activity estimation is carried out before clustering, a tool is necessary to match the switching activities with clustered architecture. For this reason, the T-VPack tool from [START_REF] Marquardt | Timing-driven placement for fpgas[END_REF] is modified to consider the activity information [START_REF] Kara | A flexible power model for fpgas[END_REF]. The modified T-VPack determines the switching activities of the nets between clusters, the global clock lines, and the input/output of the LBs.

As a part of VPR5 with Power Extension [START_REF] Jamieson | An energy and power consumption analysis of fpga routing architectures[END_REF], Poon et al. integrated a flexible power model to estimate dynamic, short circuit and leakage power for island style FPGA architectures [START_REF] Kara | A flexible power model for fpgas[END_REF]. The operating frequency of the application is determined with the critical path delay of the circuit under evaluation and the dynamic power is, then, calculated assuming that the circuit is operating with this frequency. Dynamic power dissipation is calculated based on the signal activities and associated node capacitances that are extracted in VPR5 tool. The short circuit power consumption is defined as a percentage of total power consumption which is 10% by default and can be modified by the user. Subthreshold leakage consumption model is used for the calculation of leakage power.

Benchmarks

Since FPGAs are programmable devices, performance, area, or power efficiency of an architecture cannot be measured until the designed FPGA is programmed with the desired application. Therefore, the performance of a particular FPGA implementation is experimentally measured using the 20 largest MCNC benchmarks [START_REF] Yang | Logic Synthesis and Optimization Benchmarks User Guide: Version 3.0[END_REF]. The included benchmarks (Table 3.1) range from computation intensive to routing intensive and small area to large area to observe the effects of each architectural modification.

Methodology for Emerging Technology Evaluation

Even though FPGA fabric is a simple functional unit, several design choices can be imposed in the architectural development. Especially, when emerging technologies are employed, accurate modeling of these architectural and technological parameters is crucial. It is expected that several runs have to be executed iteratively for architecture optimization and design space exploration. Therefore, fast, flexible, technology and architecture-aware exploration platform is necessary.

FPGA Evaluation Platform

For the adoption of emerging technologies, the conventional design approach is not sufficient. In general, a standard cell library is constructed and then verified for logic design. These cells are provide varying driving capabilities and other properties such as low-power or high-performance. The cells are then used in an automated place and route tool. This approach is optimized for advanced technologies where the tools and libraries are mature enough for reliable designs. However, during design with emerging technologies, this level of maturity cannot be attained for design exploration. Since these technologies are not mature enough, it is sometimes difficult and most of time impossible to find the required tools and the standard cell libraries.

In order to accomplish an FPGA design a partial standard cell library might suffice because FPGA building blocks are not very complex and the entire FPGA design can be accomplished with few cells. However, depending on the targeted technology new tools might be included in the automated CAD flow such as a 3D place and route tool to design 3D circuits. Thus, a certain level of abstraction is necessary. In this thesis, a FPGA evaluation methodology for emerging technologies is proposed as shown in Fig.

Architecture Definition Development for Emerging Technologies

With the framework defined previously in Section 3.2., the impacts of LUT, cluster size, SB topology, or transistor parasitics can be observed rapidly. In these cases, the FPGA architecture is evaluated based on parameterized assumptions where the layout parasitics can not be effectively examined. Thus, in this thesis, the methodology in With the methodology, architecture definition is built using FPGA building blocks.

As described in Section 2.1., FPGAs are tile-based circuits and one tile is constructed with one Logic Block (LB), two Connection Boxes (CB), and one Switch Box(SB).

These building blocks are established with configuration memories, multiplexers, and buffers. Hence, once these elementary blocks are designed in the layout and included in the design library, all the FPGA related blocks can be designed quickly. The de-sign process is, therefore, shortened substantially because only few blocks need to be designed on layout rather than the entire FPGA.

Memory Cell Area Modeling

Normally, VPR assumes in the source code, a 6T SRAM cell implemented with minimum size transistors. This memory transistor count is a part of the FPGA area model and used for the area estimation of the configuration memory in the FPGA blocks which is then used to estimate the routing wirelength. Hence, it not only affects the area but also routing complexity which is directly related to performance and power consumption due to the resistance and capacitance implications. In different technologies and topologies, however, SRAM might consume less or more area than a 6T estimation. Thus, we modified the VPR tool and the architecture file to be able to change the area of the memory cell. The trans_SRAM variable in the source code is added in the architecture file as shown in Fig. 3

Conclusion

FPGAs are the first computing units that benefit from the emerging technologies.

In order to estimate the improvements achieved from these technologies, an evaluation framework is constructed in this chapter. The framework consists of a complete set of tools for the evaluation of benchmark circuits. Technological and architectural properties are expressed in an architecture definition which constitutes the FPGA fabric.

The framework offers a fast, flexible environment to estimate area, performance, and power benefits of the designed FPGA.

As surveyed in Chapter 2, emerging technologies have impacts on various levels in the design process. For the assessment of the these impacts using the evaluation framework, a methodology is proposed. This methodology lowers the design effort with emerging technologies by introducing an abstraction level. Only FPGA building blocks are characterized and the properties are included in the architecture definition for the evaluation using the framework.

The architecture definition methodology and the experimental framework from this chapter allow estimating the impacts of emerging technologies. This platform will be the basis for the evaluation of targeted emerging technologies in the following chapters. With the integration of NVM in FPGA, new application fields can be targeted.

Since SRAMs lose the information when the power is cut-off due to their volatile nature, the configuration information (bitstream) has to be transferred into the FPGA during wake-up. Thus, an external non-volatile memory (ex. Flash) is dedicated to store the bitstream. With the integration non-volatile memories, the configuration information can be kept locally in the FPGA. Thus, configuration-saving applications can be accommodated with the designed FPGA.

For the replacement of FFs, an OxRAM-based non-volatile FF (NVFF) is introduced in the FPGA for non-volatile context storage. OxRAM elements store the information when necessary and the NVFF operates exactly as a FF. For some applications previously computed data are required for new calculations, as most of the information is contained in the evolution of monitored data. In this case, the previously calculated information (context) has to be stored in an external memory before the FPGA power is cut off and it has to be fetched when FPGA is turned to continue calculations. With the integration of NVFFs, the context can be locally stored in the NVFFs and the communication with the external memory can be avoided. Thus, context-saving applications can be accommodated with the designed FPGA. Furthermore, when OxRAMbased NVSRAM and NVFF are integrated together in the FPGA, configuration and context-saving applications can targeted.

When SRAM configuration memory cells are replaced with the NVM counterparts, significant area improvements can be achieved. The area reduction of configuration memories decreases the wirelength of routing wires which also improves the wiring capacitance. In order to observe the benefits, compact CBRAM-based 1T2R cell is integrated in the FPGA by replacing all the SRAM nodes. With this memory node, the FPGA area can be reduced by 33%. The reduction of area leads to less capacitance and resistance in the routing wires which results in decreases delay and power consumption by 34% and 23% respectively.

With the development of Internet-of-Things (IoT), embedded applications are emerging with varied specifications. Some of these applications can be categorized as "Normallyoff, Instantly-on". These applications require short highly intensive computing phase in between of long idle periods. As explained in Chapter 2, FPGAs can fulfill the requirement for intensive computing however FPGAs have high overhead in power consumption which prevent FPGA from being employed in battery operated applications.

Taking advantage of the non-volatility, the proposed FPGAs can store the information locally in the FPGAs and power gating can be applied to cut-off the power during idle periods. The FPGA can then be switched on rapidly for computations before switching off. In this case, a zero leakage state can be achieved during the idle periods and the overall power consumption can be reduced. For applications having low activity, the power consumption can be reduced by 90%.

In this chapter, first the OxRAM and CBRAM-based elementary non-volatile circuits are explained. The area and power consumption characteristics are extracted. In the following section, non-volatile FPGA circuits are designed using the elementary cells for configuration and context-saving applications. Area, delay, and power consumption figures of the FPGA circuits are extracted using the flow in Chapter 3. Normally-off, Instantly-on computing is discussed in the following section. Power-gating implementation is explained for the utilization in FPGA and the power gains of the designed non-volatile FPGAs are evaluated.

RRAM-based Elementary Circuits

In this section, several basic elements are analyzed with OxRAM and CBRAM technologies. The design and operation of the cells are explained in detail. The elementary circuits can be used in other applications such as in ASICs if non-volatility is desired.

In this thesis, the main objective to have non-volatile FPGAs. Therefore, the cells are characterized in area and power consumption targeting FPGA usage. For reset, appropriate signals are applied to the control lines, CTRL1 and CTRL2, to obtain a higher potential at the bottom electrode with respect to the top electrode of the RRAM devices. This operation is achieved by turning on CM1 and CM2 and providing a voltage of 1.5V to CTRL2. Depending on the logic value at the data nodes of the SRAM cell, either R1 or R2 will be reset; i.e. when D= '0' (DN= '1'), the negative potential drop across R1 will reset R1 and when D= '1' (DN= '0'), R2 will be reset.

For information storing, the control transistors are turned on and CTRL2 is set to 0V. A positive potential drop across one of the RRAM devices will set the corresponding RRAM device and the same potential at the top and bottom electrode of the other RRAM will make the corresponding RRAM stay at the same resistance state. In this way, the logic values at the data nodes (D= '1'/ '0', DN= '0'/ '1') are stored into the RRAMs as '1'/ '0' (R1= SET/RESET) and '0'/ '1' (R2= RESET/SET). The inherent non-volatile characteristic of RRAMs ensures the retention of this information when a power-down occurs. During the power-down, all the control signals are pulled down to VSS (0V). Thus, a state with no leakage consumption is achieved. At power-up, before restoring the information from the RRAMs, VDD is put to 1V and at the same time VSS is pulled up to VDD to have D=DN='1'. This prevents the flipping of the RRAMs during the RESTORE operation.

For restoring, CM1 and CM2 are turned on and simultaneously, 1V is applied to

VDD(V) VSS(V) CTRL1(V) CTRL2(V) NORMAL 1 0 0 0 RESET 1 0 0 1.5 STORE 1 0 0 0 POWER-DOWN 0 0 0 0 POWER-UP 1 1 1 1 RESTORE 1 0 0 1
CTRL2. With respect to CTRL1 and CTRL2, VSS is lowered to 0V after a delay of 5ns. If R1 is low, node D is maintained at logic '1' but if R2 is high, node DN discharges through M3. In this way, the values are restored at the data nodes.

Normal SRAM operation can be performed right after the restore operation without having to reset the RRAM at low resistance state. SRAM operation is not influenced by the addition of the control transistors and RRAMs. In fact, CM1, and CM2 isolate the RRAMs preventing the degradation of the SRAM cell stability during normal SRAM mode. Thus, the control transistors do not affect the normal SRAM operation because they remain switched off after the restore phase is completed.

NVSRAM Cell Characterization

In order to evaluate system level impacts of NVSRAM integration in FPGA, power For a fair comparison of area between SRAM and NVSRAM, the OxRAM devices and control transistors are removed to obtain a regular SRAM cell. The total area is calculated for the NVSRAM and SRAM by normalizing the transistor dimensions to minimum size transistor. Table 4.2 shows that NVSRAM is 32% larger than SRAM.

The area overhead stems from the additional control transistors. Since the OxRAM devices are manufactured at the BEOL between metal layers, no area impact from OxRAM devices is observed. As explained before, for a single ON/OFF cycle, NVSRAM has to go through the following stages: reset, store, power-down, power-up, and restore as discussed previously. Using Eldo, an NVSRAM cell including the OxRAM model is simulated and, then, average power consumption for each operation is extracted with corresponding duration. Table 4.3 shows the results. For the completion of single ON/OFF cycle, NVSRAM dissipates 17.9 fJ. This value assumes that new information has to be stored in the OxRAM devices each time before powering down. The total cycle does not need to be followed if the stored information in OxRAMs is the same as the information in the SRAM part during normal operation.

When the NVSRAMs are integrated in the FPGA as configuration storage, it is not required to follow all the steps in the ON/OFF cycle. Specifically, the configuration bitstream does not change once it is generated and transferred to the FPGA.

Since the same information is retrieved when restoring, it is not necessary to reset and store repeatedly. Hence, only power down and restore operations are taken into account. Considering this characteristic, the total required power for one ON/OFF cycle is reduced to 0.78 fJ per unit cell as shown in Table 4.3.

Non-volatile Flip-Flop (NVFF)

Flip-Flop Architecture

A Non-volatile Flip Flop (NVFF) based on RRAM is necessary when not only configuration, but also data values must be restored in an ON/OFF application. The NVFF cell architecture and operating principle are proposed in collaboration of LETI

Operating Principle

The entire sequence of operations that is followed to faithfully store and restore the state of the flip-flop is shown in Fig. 4 Store operation is triggered by the control signals STR_RST_CTRL = '1', CE = '1', and CTRL = '0' guiding the logic state present in the slave latch to be stored in RRAM. For example, when slave has a '1', the RRAM in the NVM_R is SET (LRS), since a positive bias is applied between its terminals. The NVM_L block remains unchanged (HRS) since there is no potential drop between the RRAM_L terminals is 0V. In essence, the NVM_R with RRAM_R in LRS and NVM_L with RRAM_L in HRS form the logic state of '1'. Once RRAMs are programmed the flip-flop and, hence, the FPGA can be powered-down completely owing to the information stored in

VDD(V) STR_RST_CTRL(V) RESET_ENABLE(V) CE(V) CTRL(V) RESET 1 0 1 1 1 NORMAL 1 0 0 0 0 STORE 1 1 0 1 0 POWER-DOWN 0 0 0 0 0 RESTORE 1 1 0 1 1
non-volatile memories.

The restore is initiated by signals STR_RST_CTRL = '1', CE = '1', CTRL = '1', and RESET_ENABLE = '0'. The logic is restored on the slave latch for resuming normal operation with the VDD restoration. This is, in fact, a read operation on the RRAM. The presence of the complementary logic in NVM_L and NVM_R assists the acceleration of logic restoration process. This is followed by resetting the RRAMs to HRS using STR_RST_CTRL='0', CE = '1', CTRL= '1', and RESET_ENABLE = '1', which puts a negative bias on the RRAM terminals.

NVFF Cell Characterization

In order to evaluate system level impacts of NVFF integration in FPGA, power dissipation for each operation and total area of an NVFF cell are extracted. All the simulations are performed using Eldo simulator from Mentor Graphics and the results are validated on 22nm FDSOI process design kit (PDK) developed at CEA-LETI. The same OxRAM model used for NVSRAM is included for simulations [START_REF] Cagli | Experimental and theoretical study of electrode effects in hfo2 based rram[END_REF]. In order to observe the total overhead imposed by the nonvolatile functionality, normal FF and NVFF are compared. As described previously, the nonvolatile block consists of 3 transistors and 1 OxRAM for each complementary node, adding up to 6 transistors and 2 OxRAMs in total for 1 NVFF. The total area is calculated for the FF and NVFF by normalizing the transistor dimensions in each cell to minimum size transistor. It can be observed from Table 4.5 that NVFF has 26% larger area than a regular FF. The area overhead stems from the additional control transistors. Since the OxRAM devices are manufactured at the BEOL between metal layers, no area impact from OxRAM devices is observed.

Similar to NVSRAM, NVFF has to follow reset, store, power-down, and powerup/restore stages in one ON/OFF cycle. The average power consumption for each

NON-VOLATILE FPGA WITH RESISTIVE MEMORIES

operation is extracted from the simulations carried out using Eldo as shown in Table 4.6.

Contrary to NVSRAM integration in FPGA, NVFFs are used for context-saving purposes. Specifically, NVFFs will be utilized to store the results of the calculations carried out in the LUTs. Thus, before power-down, the information stored in the NVFF needs to be updated for no information loss. As a result, it is necessary to do the reset and store operations before power-down and restore. Considering this operation scheme, each NVFF consumes 11.4 fJ for one ON/OFF cycle as shown in Table 4.6.

NVE-based Design

Elementary Non-volatile 1T2R Memory Element(NVE)

A resistive divider node is a very attractive solution for storing information because of the reduced footprint. The memory cell called Non-Volatile Element (NVE) in Fig. the area of the memory cell is limited with the area of the access transistor. Thus, compared to an SRAM cell, the memory area can be reduced significantly. However, even though there is an area advantage, the design of resistive divider imposes restrictions on the memory technology. Since two resistive elements are connected between source and ground, there is a continuous flow of leakage current. When all the configuration memories are considered in FPGAs, the leakage current becomes reasonably high. Another implication is that when sufficient voltage difference is attained on the resistive device programmed to LRS, the resistance value might flip leading to information loss. Therefore, in order to limit the leakage current and retention implications, a large HRS and a large resistance window (the ratio between LRS and HRS) are required.

As explained in Section 2.

Operating Principle

The (non-volatile element) NVE consisting of a transistor and two CBRAM cells is programmed by first selecting the cell using the selection transistor and then applying the appropriate voltages to the terminals across the CBRAM devices. The conditions for storing 0 and 1 to the cell are illustrated in Fig. 4.5 . For storing 0, the top CBRAM should be reset and the bottom CBRAM should be set, which is achieved by applying logic 1 to the the X Y nodes and logic 0 to the write signal. For storing 1, the previous condition is reversed. Namely, logic 0 is applied to the X Y nodes and a logic 1 to the When new information is written to the NVE, the resistors have to reset and store the new value. If an ON/OFF operation follows the the write operation, the total energy consumption is the sum of reset, store, power-down, and restore. Using Eldo, an NVE cell including the CBRAM model is simulated and, then, average energy consumption for each operation is extracted with corresponding duration. Table 4.8

NON-VOLATILE FPGA WITH RESISTIVE MEMORIES

shows the results. For the completion of single write operation including ON/OFF cycle, NVE dissipates 3.42 pJ. This value assumes that new information has to be stored in the CBRAM devices each time before powering down.

When the NVEs are integrated in the FPGA as configuration storage, it is not required to follow all the steps in the ON/OFF cycle. Specifically, the configuration bitstream does not change once it is generated and transferred to the FPGA. Since the same information is retrieved when restoring, it is not necessary to reset and store repeatedly. Hence, only power down and restore operations are taken into account.

Considering this characteristic, the total required power for one ON/OFF cycle is reduced to 1 fJ per unit cell as shown in Table 4.8.

Towards Non-volatile FPGA

As explained in Section 2.1.2., all the blocks in the FPGA are constructed with configurable nodes. These nodes, conventionally being SRAM, need to be programmed with configuration information in order to map the correct application functionality.

NON-VOLATILE FPGA WITH RESISTIVE MEMORIES

Hence, a bitstream has to be created based on the functionality and transferred into FPGA. Usually, an external non-volatile memory (ex. Flash) stores the bitstream and transfers it to the FPGA upon start-up because the volatile SRAMs lose configuration data when the power source is cut off. With this scheme several cycles are required to load the bitstream and due to the external communication, a high level of power is wasted. Moreover, application security cannot be guaranteed because the external memory is accessible for external attacks and the content might be duplicated which creates vulnerability for valuable intellectual property.

In FPGAs FFs are included in the BLEs. These FFs act as registers which store the result (context) of the operations. Some applications require computations based on temporal evolution. In this case, previously calculated data has to be present in the FPGA. In order not to lose context information, all the calculated results must be transferred to an external storage (ex. Flash) and then retrieved at start-up. The communication to the external unit requires very long cycles and consumes a high level of power. The data in the external memory can also be duplicated by unauthorized access which creates vulnerability as the data might contain sensitive information.

In order to eliminate external storage, Flash cells can be integrated in the FPGA [START_REF] Joonhan | A novel flash-based fpga technology with deep trench isolation[END_REF]. FPGA vendors such as Actel [START_REF]Actel igloo[END_REF], Lattice [144], and finally Xilinx [START_REF]Xilinx. Xilinx spartan T M -3an fpgas[END_REF] have announced their flash FPGAs which enclose a hybrid SRAM+Flash architecture where the configuration data is stored in Flash memory. However, the integration of Flash is costly in terms of CMOS process and offers slow operation speeds with a large footprint [START_REF]Executive summary[END_REF]. Moreover, commercial products only consider configuration data for Flash storage not the context which imposes implications on Flash integration as Flash

Evaluation on Applications Requiring Configuration Saving

In this section, NVFPGAs with configuration saving property are designed using OxRAM and CBRAM-based memories. Since all the configuration nodes are replaced with non-volatile counterparts, the bitstream can be kept locally in the FPGA. With these FPGAs, there is no need for an external memory to save the bitstream. Thus, following benefits are obtained: 1) The start-up period can be significantly shortened.

The FPGAs can be turned on instantly. 2) There is no power consumption due to the bitstream transfer. 3) Bitstream security is granted since there is no external memory.

OxRAM-based NVFPGA

In the OxRAM-based FPGA all the configuration memory nodes are replaced with NVSRAM cells. The VPR flow in Chapter 3 is used for evaluation. In order to consider the effects of 22nm LETI-FDSOI process, the architecture definition in VPR is modified accordingly and then changes due to the NVSRAM cell are included. The memory area parameter defined in Section 3.3. is updated with the area estimation calculated in Table 4.2. Due to the two additional transistors in NVSRAM, there is an increase of the routing wire length between LBs. Thus, beyond the direct increase of the memory area, there exists a routing congestion due to the extra transistors. As a result, the addition of two transistors affects all the performance metrics i.e. critical path delay, total area and total power consumption.

The results from the VPR5 flow can be found for the SRAM and NVSRAM-based FPGA on Fig. 4.7, 4.8, and 4.9. Delay and area are increased on an average by 7% and

NON-VOLATILE FPGA WITH RESISTIVE MEMORIES

Critical path delay (ns)

SRAM NVSRAM(+7%) 18% respectively in NVSRAM implementation. Total power consumption is affected by a 2% increase which is due to the effect of more complex routing due to NVSRAM area overhead.

CBRAM-based NVFPGA

CBRAM technology is available in 130nm CMOS process. Using the values in Sec- NVLUT integration while the NVFPGA achieves 33% better area efficiency. As a result of smaller area, routing wires shorten in length reducing the routing complexity leading to decreased critical path delay and power consumption. NVLUT integration reduces delay by 24% and the NVFPGA reaches 34% reduction. Finally, power consumption is decreased by 18% with NVLUT integration and in NVFPGA 23% lower power is achieved.

Discussion

By replacing the SRAM in the configuration memory with non-volatile memo- additional control transistor. This overhead results in longer wirelength which increases delay and power consumption. 2) Leakage: The leakage consumption of the NVE, due to the direct path between the source and ground lines, is still significantly higher than that of SRAM. High HRS value is crucial for the limitation of this leakage current. In NVSRAM, on the other hand, since the resistive devices are connected separate nodes, the leakage is similar to the value in SRAM. 3) Write Energy: The write energy of NVE is higher than that of NVSRAM. Normally, the bitstream is stored in the nonvolatile memories in the FPGA once and then retrieved from the same memories at each start-up. However, when different applications are considered, the bitstream of each application has to be transferred to non-volatile memories which consumes the write energy. If a configuration-saving FPGA is used for many different applications, the write energy should be considered. 4) Endurance: As discussed in Table 2.1, CBRAM has considerably smaller endurance (10 6 ) compared to OxRAM (10 12 ). If the FPGA fabric is reprogrammed with many different applications, endurance might limit FPGA utilization.

Evaluation on Applications Requiring Context and Configuration Saving

Some of the applications targeted in the FPGA may require computation based on temporal evolution. Namely, some functions may require previous values to be included in the calculation. As discussed previously, it is possible to retain the configuration in the NVSRAMs after a sleep period. However, computational results that are stored in the FFs cannot be preserved when switched-off. Therefore, non-volatile elements must be included to save the contents of registers. In the designed OxRAM-based Previously, in the configuration saving applications, combinational circuits were used in which the FFs in the LBs are bypassed by the MUXs. In order to observe the impact of NVFF, sequential circuits from MCNC benchmarks are assessed where the FFs are activated.

The results from VPR5 evaluation flow can be found in Figures 4.13 -4.15 for critical path, area, and power metrics. For sequential benchmarks, NVSRAM integration presents similar overhead as the combinational ones resulting in 6%, 17%, and 1,5% increase in delay, area and power respectively. Proceeding with the NVFF integration results 3%, 1%, and 1% delay, area and, power overhead respectively. Since the NVFF has a larger area than a FF due to the extra 6 transistors as described previously, the routing resource becomes more complex and, hence, there exists an influence on delay and power parameters. Moreover, the NVFF has a slightly higher Clk-to-Q delay than a regular FF, due to the additional capacitance from the control transistor, which affects the final critical path delay metric. The overall effect is smaller compared to NVSRAM integration because the number of employed FFs is relatively smaller than that of SRAMs.

Optimization of Resistance States for NVFPGA

As explained previously, the technologies, OxRAM and CBRAM, offer different properties which affect the design of the memory architectures. In the NVSRAM as shown in Fig. 4.1, the nonvolatile devices are connected to the data nodes of SRAM As explained before, the NVE is either connected to the gate of the transistors in the switches (Fig. 4.6a) or the source of the transistors in the LUTs (Fig. 4.6b). When it is in the switches, it has no impact on the performance but in the case of LUTs, it affects the delay of the LUTs. As explained before, the top and bottom resistive devices are programmed in complementary values, i.e. at any time one of them is programmed with high resistance (R OF F ) and the other with low (R ON ). The R ON of the NVE determines how long it takes to charge or discharge the configuration node of the LUTs. Thus, the lower the R ON the higher is the operating speed.

In the NVE structure during normal operation, regardless of where it is connected for configuration, there is a direct current path between the supply and ground sources.

Considering the complementary states of the resistances, a resistance value of R on + Rof f lies between the supply and ground voltage sources. The leakage current becomes; Assuming that R OF F R ON and V ss = 0, the leakage equation simplifies to;

I leakage = V dd -V ss R ON + R OF F (4.1)
I leakage ≈ V dd R OF F (4.2)
The impact of R ON on delay is investigated based on the LB delay. Using evaluation platform in Chapter 3, several architecture files are created. Benchmark circuits are evaluated with varied memory resistance values and average critical path delay for each resistance value is reported. Fig. 4. [START_REF] Kuon | Fpga architecture: Survey and challenges[END_REF] shows the resistance impact on the critical path delay. For increased performance, the trend from the results confirms the expectation that the resistance should be lowered for increased performance. It can also be noticed that even with very high resistance of 100kΩ, the performance of NVE-based FPGA is still 23% better than the SRAM counterpart. This can be explained with the area advantage of NVE-based implementation which is still higher than the diminishing effect of high resistance.

R OF F impact on leakage current is examined by using the equation in 4.2. Table 4.9

shows the resistance pair examples reported in the literature with different technologies and corresponding leakage current values in NVE configuration assuming V dd = 1.5V .

Depending on the technology, the achievable R OF F value changes significantly and the effect of the R OF F can be observed clearly as it is the dominating factor. The highest R OF F is offered by CBRAM technology as 10GΩ with a leakage as low as 15nA per NVE cell. This study examines several trade-offs of the resistance states over critical path delay and power consumption values. Depending on the application requirement and power budget, the resistance values and the targeted technology can be selected. Thus, with this study, the process engineers can get a feedback for the selection of material stack of the NVE device to fulfill the FPGA requirements.

Towards Non-volatile FPGA

Normally-OFF Instantly-ON Computing

Many new embedded applications can be characterized as "Normally Off, Instantly

On". Video surveillance, smart grids distributed sensors or healthcare monitoring systems are some examples of such applications. They share a common feature: a long idle period followed by a short highly intensive computing phase. A small circuitry can be reserved in the chip to generate the wake-up signal by observing the events with an appropriate sampling frequency. When incoming burst of events happens, wake-up process should be completed as quickly as possible in order to avoid missing important information after the arrival of the wake-up signal. For example, a disruptive event on power grids must be quickly analyzed by reacting in few milliseconds. Similarly, a heart attack can be anticipated by analyzing electrical signals after an abnormal event.

Especially, avoiding false detections is particularly challenging due to the high number of measurements that needs to be processed in a few microseconds after a wake-up event.

The solutions are generally embedded, frequently battery-powered, and distributed on large areas. Their computing performance requirements tend to increase with higher complexity of applications (e.g. aggression detection for video surveillance). On the other hand, these systems being pervasive in our environment and, thus, more and more numerous, static power consumption must be minimized during sleep periods, while keeping the dynamic power consumption as low as possible.

General Purpose Processors (GPP) are not efficient for these computing intensive applications as they offer reduced power efficiency and require long boot sequences when switching into 'ON' states [START_REF] Tian | High-performance quasi-monte carlo financial simulation: Fpga vs. gpp vs. gpu[END_REF]. Application Specific Integrated Circuits (ASIC)

or System-On-Chip (SoC) are power efficient but are expensive to develop and not flexible enough to address a wide range of applications. Field Programmable Gate Arrays (FPGA) offer a good compromise between flexibility and power efficiency, as they are flexible enough to accommodate a large number of applications and have reduced dynamic power consumption compared to GPP [START_REF] Tobias | Reconfigurable components for application-specific processor architectures[END_REF]. Moreover, they can be designed using high-end technologies to provide the required performance. However, as the supply voltage decreases and the feature size becomes smaller, the leakage current of FPGA increases very rapidly [START_REF] Deepaksubramanyan | Analysis of subthreshold leakage reduction in cmos digital circuits[END_REF]. As a result, the leakage is the major source of power consumption and reduce FPGA field of applications.

Several techniques have been proposed to achieve low-power FPGAs. Meng et al.

studied the use of drowsy modes to reduce leakage in the embedded memory [START_REF] Meng | Leakage power reduction of embedded memories on fpgas through location assignment[END_REF] and proposed a method that is applicable to the block memories in the FPGA. However, since the configuration memory is distributed, the granularity of the control circuitry imposes a high area overhead. Lewis et al. proposed power management schemes featuring body biasing [START_REF] Lewis | Architectural enhancements in stratix-iii™ and stratix-iv&#8482[END_REF] while Li et al. evaluated the effects of dual-V dd and dual-V t fabrics on power consumption [START_REF] Li | Low-power fpga using pre-defined dualvdd/dual-vt fabrics[END_REF]. These solutions require technology dependent adjustments and it is still not possible to have full power down mode.

In order to improve total power consumption, power-gating technique is massively employed [START_REF] Masudh | An innovative power-gating technique for leakage and ground bounce control in system-on-a-chip (soc)[END_REF]. It can help decrease the leakage current by a factor of more than 1000; however, in the case of FPGA, all the information contained in SRAM memories is lost when switched off. To solve this issue, FPGAs can be associated with external nonvolatile Flash memories to store their context. In such a case, restoring a context after a power-off stage is accomplished by serially loading a bitstream to all the configuration cells of the FPGA. This process is quite long and can take up to hundreds of milliseconds for a large FPGA. Moreover, for calculations requiring a history of data, information stored in the registers is lost after an ON/OFF cycle. For such applications, the results must be stored externally and they need to be restored after every power-off operation.

Hence, due to external storage communication overhead, switching-off FPGA is not compatible with fast wake-up and requires very long idle periods. As explained in Section 4.2.1., Flash memories can be integrated in FPGAs to reduce wake-up period.

Lattice reports that when Flash memory is integrated in the FPGA, the transfer of configuration from Flash to SRAM takes 1ms. Even though, the wake-up time is significantly reduced, it is still very high for instant-on feature. Consequently, current FPGA structures are not compatible with "Normally Off, Instantly ON" application constraints.

Power-gating Implementation

Power Overhead -Duty Cycle Relation

In an application where FPGA is switched into sleep mode, the dissipated leakage power will be conserved. However, it is necessary to take into account the power overhead due to RRAM integration and power switch implementation. In Fig. 4.18, P 1 and P 2 refer to anticipated power consumption of SRAM and RRAM-based architectures, P L is leakage power consumption of SRAM configuration, t 0 and t 1 are the ON and standby durations respectively. In an activity when the consumed leakage energy during t 1 exceeds the energy overhead due to the power overhead (P OH = P 2 -P 1 ) spent during t 0 , the leakage energy for a smaller duty cycle will be conserved.

Initially, as in Eqn. 4.3, a ratio between t 1 and t 0 can be defined when the leakage energy in t 1 duration is equal to the energy spent during t 0 due to the power overhead:

t+t 0 t P 2 -P 1 dt = t+t 0 +t 1 t+t 0 P L dt (4.3)
t 1 t 0 = P 2 -P 1 P L (4.4)
The ratio given by Eqn. 4.4 defines the minimum t 1 in terms of t 0 when the energy overhead is in equilibrium with the gained leakage energy. It is possible to relate this ratio to duty cycle, which is defined as the ratio of 'ON' duration to the total period.

Specifically, in an on/off application, break-even time (BET) indicates the duty cycle when the energy overhead is equal to the leakage energy. In this application, it is calculated based on the following equation:

BET = t 0 t 0 + t 1 = 1 1 + P 2 -P 1 P L (4.5)
Eqn. 4.5 defines the break-even time (BET). When the actual duty cycle of the application is smaller than the BET, it is possible to save leakage power and reduce the total power consumption. For applications having a duty cycle larger that BET, total power gains are observed. The gain can be defined as follows:

P ower Gain(%) = P L t 1 -(|P 2 -P 1 |)t 0 P 1 t 0 + P L t 1 100 = P L -(|P 2 -P 1 |)D P 1 D + P L 100 (4.6)

Logic Module

Power Down 𝑉 = 𝑉 𝐷𝐷 -𝑉 𝑃 𝑉 𝐷𝐷 where (|P 2 -P 1 |) denotes the total power consumption difference between RRAM and SRAM-based FPGA implementations, (t 1 , t 2 ) the on/off durations, D = t 0 /t 1 the duty cycle, and P L SRAM configuration leakage power consumption.

Power Gating Cost

If a logic circuitry is considered in which a PMOS switch, as in Fig. 4.19, provides the power gating functionality, the absolute source voltage available for the logic operation is decreased due to the voltage drop on the switch transistor. If the highest available VDD is not increased to compensate the effect, the lowered source voltage will affect the performance of the logic circuit. The voltage drop is directly proportional to the size of the switch. If the area of the switch is increased, its resistance will be decreased, thus, the voltage drop will be decreased and the performance will suffer less.

Therefore, it is possible to define a trade-off between switch size and performance of the circuit, i.e. the maximum frequency of the circuit.

Assuming a switch, with an area of 'A s ', driving a load of area 'A', and providing current 'I', the trade-off between area and performance can be defined as [START_REF] Chabloz | Globally-Ratiochronous, Locally-Synchronous Systems[END_REF]:

∆f = α I A A s g on V DD V DD -V T H 1 ∆A (4.7)
where g on is the conductivity of the switch, α is the velocity saturation index, V DD is the supply voltage, and V T H is the threshold voltage of the switch. ∆f and ∆A refer to the change in frequency and area. With this equation, it is possible to observe the effect of switch strength on operating frequency. In the trade-off defined in 4.7, I/A and g on /A s provide area independent ratios. In other words, as defined in [START_REF] Chabloz | Globally-Ratiochronous, Locally-Synchronous Systems[END_REF], a module with area of 'A' and consuming current 'I', will have the same trade-off as another module which has K times bigger area and K times higher current consumption. In the NVSRAM cells, write current is critical in order to obtain successful operation. Hence, for the sizing of the power switches, write current of the NVSRAM cells are considered as the worst case. Consequently, one NVSRAM cell is simulated in Eldo and the required typical current is obtained as 12µA.

Finally, the performance/area trade-off is calculated for 22nm technology using Eqn.

4.7 as shown on Fig. 4.20. From the figure, it can be observed that the rate of change of area-frequency trade-off decreases as the area increases. After 8% of area overhead, increasing the area does not reduce the frequency overhead significantly. Therefore, 8% area overhead is considered which results in 8% frequency overhead for the power gating application in the RRAM-based FPGA.

Normally-OFF Instantly-ON FPGA

In Normally-off Instantly-on applications, the computation unit is powered off when it is not in use and it is turned on very fast to continue computing. Due to the volatile memories and registers, these applications cannot be addressed in traditional FPGAs.

The proposed FPGAs in Section 4.2., on the other hand, can fulfill the requirement of these applications. Moreover, with the integration of non-volatile memories, the leakage consumption can be preserved by introducing a zero-leakage state. In this section

OxRAM-based Normally-OFF Instantly-ON FPGA for Configuration-Saving Applications

When a power on/off application is considered, with the use of non-volatility, leakage power is gained during sleep mode. As mentioned earlier, Break-Even Time (BET)

indicates the activity ratio necessary for power savings. In order to observe the power gain resulting from switching-off the FPGA, the BETs for different benchmarks are calculated using Eqn. 4.5. Table 4.10 shows the power overhead (P OH ), leakage power of SRAM configuration (P L ) and the BET for each of the benchmark circuits. The BET values range between 30% and 51% with an average of 42%. If the targeted FPGA application has an activity time smaller than 42%, the leakage power is reduced and the overall power consumption is decreased.

The duty cycle of the application has a direct influence on the conserved power levels. Fig. 4.21 shows that for the on/off application, if the duty cycle is much lower than the BET, the power gain increases rapidly. The zero crossing of the curves gives the BETs of the circuits. Starting from 42%, if the duty cycle is reduced to 10% and 5%, power gains of 7% and 16% can be obtained respectively. For a specific application where the circuit is effective for 1% of the time, power gain reaches 50% on average. If the on time is further reduced, higher power gain can be attained.

Normally-OFF Instantly-ON Computing

CBRAM-based Normally-OFF Instantly-ON FPGA for Configuration-Saving Applications

As explained previously in Section 4.

OxRAM-based Normally-OFF Instantly-ON FPGA for Configuration and Context-Saving Applications

With the previously assessed FPGAs, only configuration can be stored in the FPGA for Normally-off Instantly-on applications. However, for applications requiring temporal evolution, the calculated results in the FFs are lost when the FPGA power is cut-off.

With the integration of NVSRAM and NVFF, the OxRAM-based FPGA designed in Section 4.2.2. accomplishes both configuration and context saving property which is a requirement for fast power on/off cycles.

For the evaluation of power gain in Normally-off Instantly-on applications, the results from Section 4.2.2. are analyzed. After extracting the leakage power and power overhead of the sequential benchmarks including the NVSRAM and NVFF integrations, the BET values are calculated for the ON/OFF application. It is assumed that perfect clock gating is already present in the SRAM-based FPGA; i.e. there exists no performance overhead due to the extra control logic, which is necessary to prune the clock tree. Consequently, compared to a volatile FPGA, our solution provides a massive reduction of total power consumption. Table 4.11 show the calculated BETs using Eqn. 4.5. The BET values range between 20% and 53% with an average of 38%.

Specifically, depending on the application, if the duty cycle is at most 38%, total power consumption can be reduced due to the conserved leakage power. After the BETs are obtained, the power consumption for several duty cycles are calculated with Eqn. 4.6 to observe their effect on power saving. Fig. 4.23 shows that the gained power increases rapidly for lower duty cycles because more leakage power is conserved. Starting from 38% reduced duty cycles of 10% and 5% guarantee 6% and 13% power gain, respectively. For applications remaining inactive for most of the operation period, activating the FPGA for 1% of the time and powering down for the rest, provide more than 40% power gain. In the past, FPGAs have always relied on advanced technologies for better performance. The regular tile-based architecture of FPGAs allows fast adoption of advanced nodes. In this case, 3DMI can bring unprecedented advantages to FPGAs. The main problem to be addressed with 3DMI design is the utilization rate of stacked layers due to partitioning for optimized performance. It is expected in the current 3DMI technology that only 2 active layers are integrated because of the complex fabrication process.

Conclusion

However, we can also imagine the integration of more than 2 layers as the technology matures. Therefore, careful partitioning has to be analyzed considering multi-tiers to gain the highest benefit from 3DMI.

In this chapter, several 3D FPGA blocks are designed using 3DMI technology.

As explained in 2.2.1., the main bottleneck of the FPGAs is the high utilization of configuration memories. Since these memories are distributed, they require a large number of interconnects. Taking advantage of high-density interconnects in 3DMI, logic-on-memory technique is adopted for the design of 3D cells. 2D FPGA cells are also included in the design library for comparison and design space exploration. Starting from 2 layers up to 4 layers, several 3D-FPGA circuits are analyzed and evaluated with varying partitioning schemes. Based on the results, 3DMI demonstrates to be very efficient in area, performance and power improvements for FPGAs. Furthermore, the gains from stacked layers with 3DMI outperform the expected scaling gains, which proves that 3DMI can be an alternative for future scaling.

The chapter is organized as follows: Section 5.1. briefly explains the 3DMI fabrication steps. In Section 5.2., the logic-on-memory approach is explained, 3D blocks are designed and characterized, and a 3D-FPGA is assessed with the proposed approach.

In Section 5.3., multi-tier FPGAs are designed and evaluated. Section 5.4. compares traditional scaling and 3DMI results. Concluding remarks are given in Section 5.5.. In the first step, the transistors are fabricated on the bottom layer and standard high temperature spike anneal at 1050 • C is applied for dopant activation [START_REF] Batude | Advances, challenges and opportunities in 3d cmos sequential integration[END_REF]. Due

3DMI Technology

3DMI Technology

to the implications imposed by the integration of the second active layer, the thermal robustness of the bottom layer has to be guaranteed. The thermal budget for subsequent steps is limited by the stability of the salicidation step. In order to avoid additional dopant diffusion or interfacial oxide growth, top FETs must be processed under 600 • C.

Considering this low temperature limit, an approach is established with incorporation of platinum together with flourine and tungsten implantation to enable stable Ni-based salicide [START_REF] Batude | Low temperature fdsoi devices, a key enabling technology for 3d sequential integration[END_REF].

High quality active layer has to be deposited for better performance of the top transistor. Low temperature molecular bonding process (at 200 • C) allows obtaining pristine crystalline quality and accurate thickness control. Before bonding, a thin Inter Layer Dielectric (ILD) is deposited and planarized on the top of the bottom transistors. At this step, the intermediate metal layers are realized. Typically, the integration of 2 metal layers is foreseeable. Molecular bonding is, then, performed for full transfer of monocristalline Silicon layer. Silicon layer thickness can be as thin as 10nm and the ILD can be reduced down to 23nm [START_REF] Batude | Demonstration of low temperature 3d sequential fdsoi integration down to 50 nm gate length[END_REF].

The top transistor thermal budget is limited to 600 • C in order to retain the performance of the bottom layer transistor. The most critical thermal budget is the dopant activation step. The Solid Phase Epitaxy Regrowth (SPER) allows replacing the high temperature spike dopant activation anneal. Currently, SPER is the most mature way which can reduce the temperature for dopant activation below 600 • C. In this technique, the dopant activation occurs during the recristallization of an amorphized semiconductor region.

In the last step, 3D contacts are connected and the BEOL metal layers are integrated. Several metal layers are realized same as in 2D BEOL. For contact realization, a single lithography can be used between top and bottom transistors. In this case, a highly-selective etch is used to open contacts reaching down to the bottom layer without passing through the upper layer [START_REF] Batude | Enabling 3d monolithic integration[END_REF]. Consequently, equal lithography alignment performance for top and bottoms is obtained which grants no additional enclosure ensuring high density vertical interconnects. The pitch of the vertical vias can be as small as 100nm.

3DFPGA with Logic-on-Memory Approach

3D Design Implications

One of the main focus with 3DMI is the partitioning planning while taking advantage from high density interconnects. In order to exploit these benefits, recent works focus on transistor-on-transistor [START_REF] Liu | A design tradeoff study with monolithic 3d integration[END_REF] and gate-on-gate 3D integration [92] [START_REF] Sarhan | 3dcob: A new design approach for monolithic 3d integrated circuits[END_REF]. Transistoron-transistor approach improves the total area, critical path delay and power. However, well balanced NMOS and PMOS transistor footprints are necessary in order to reach highest benefits. As will be discussed in the next section, a large portion of the FPGA is built with NMOS-only MUXs. Therefore, for the proposed FPGA, gate level partitioning is preferred.

Technological and cost-related challenges must be taken into consideration during design with 3DMI. Fabrication of the bottom layer is classical but the top transistors, even if performed in a cold process, imply technological difficulties on the intermediate metal layers. Moreover, due to cost, the total number of available intermediate metal layers must be limited. Typically, integration of one or two metal layers is a reasonable is at least of one order of magnitude higher than its 3D TSV counterpart.

As described in Section 2.2.1., almost half of the FPGA is made of memories.

In consideration of this characteristic, we determine the 3DMI partitioning as follows:

The bottom layer contains SRAM cells while the top, computing and routing resources.

For keeping a good global performance, SRAM cells must be entirely integrated on the bottom layer which leads to the choice of two intermediate metal layers. A second target is on the design side: a good equilibrium between the two layers must be reached while retaining modularity and scalability capacities of FPGA for performance and low area purposes. To fulfill the first requirement, a coarse grain top and bottom layer co-design must be carried out, while the second constraint leads us to keep the classical FPGA partitioning for design optimization, i.e. LB, SB and CB.

Logic-on-memory approach is depicted in Fig. 5.2 in which the distributed CRAM in 2D tile is placed into bottom layer in the 3D tile. Logic-on-memory partitioning scheme helps attaining following gains: 1) CRAM is kept close to configuration nodes which reduces the demand on routing wires. 2) Since all the memory cells are in the bottom layer, the cell layout can be optimized with strict memory design rules for decreased footprint and high-V t cells can be utilized without area penalty for further leakage reductions. Also, the programming circuitry can be integrated in the bottom layer which decreases the routing complexity due to programming wires. 3) Since all the routing resource is placed on the top layer, no critical path signal crosses between layers which allows avoiding the effect of inter-tier vias.

3D-FPGA Blocks

All the blocks in the FPGA are designed using the 3D 14nm FDSOI process. First the layouts of 2D blocks are prepared and then by placing the Configuration Memory (CRAM) cells into the bottom layer, 3D blocks are obtained. All of the remaining logic such as multiplexers and buffers, are placed into the top layer. The optimized input number to the LB (I) is achieved with 2 × N + 2 = 10 [START_REF]Architecture and CAD for Deep-Submicron FPGAs[END_REF]. This configuration gives the highest area efficiency [START_REF] Betz | Cluster-based logic blocks for fpgas: area-efficiency vs. input sharing and size[END_REF]. Unidirectional routing is preferred because it achieves higher area and performance efficiency [START_REF] Jamieson | An energy and power consumption analysis of fpga routing architectures[END_REF]. The channel width is fixed to 32 for the routability of MCNC benchmarks. The CB connects the tracks to LB input via 32-input MUXs (MUX32) and the LB output to tracks via 4-input MUXs (MUX4). The SB supports 32 channel width and is constructed with MUX4-based switchpoints (SP).

3D MUX4

In the designed FPGA multiplexers are used to create unidirectional routing blocks.

The main component used in the CB and SB is the 4-input MUX with 2 memory cells.

Each memory cell integrated with the MUX is a traditional 6T SRAM. The MUX is designed with NMOS-only pass gates with 6 transistors for minimized footprint. Buffers with PMOS keeper [START_REF] Yano | Top-down pass-transistor logic design[END_REF] are added after the MUX to improve the signal levels. Fig. 5.4

3DFPGA with Logic-on-Memory Approach

shows the designed 2D and 3D cells. The 14nm 3D process allows dense placement of inter-tier vias as close as 100nm (Fig. 5.4). As a result of the stacked NMOS placement and the small footprint of the inter-tier vias in the MUX, a very compact layout is achieved. With this partitioning, the MUX4, SRAM, and the buffer occupy equal area and therefore a balanced area between the top and bottom layers is established which is one of the major challenges in 3D design. Compared to the 2D cell (in Fig. A.27e), the 3D MUX4 achieves a very small area

3D LUT

LBs are constructed with a cluster 4-input LUTs (LUT4). The LUT4 contains 16 SRAM cells, 16-input MUX, input, and output buffers as shown in Fig. 5.5. The memory and logic layers are designed and optimized separately. SRAM cells are placed in 4x4 configuration in order to keep close proximity to the configuration nodes. Even though the area of the memory layer is larger than that of the MUX, the difference is compensated when the input selection multiplexers, which use fewer memory cells, are added to construct the BLEs.

3D SB

A switch point for unidirectional routing is designed as shown based on 3D MUX4 (Fig. 5.4). Each Switch Point (SP) includes four 3D MUX4. Fig. 5.6 shows the designed 3D SP. The number of inputs to the SPs is limited to 3, i.e. the switchbox flexibility: F S = 3. Switch points are placed in 4x4 configuration which allows keeping the same height of the CB. In the designed 3D SB, there are 16 3D SPs which support a channel width of 32. The SB has the same connectivity scheme of a disjoint SB which is used in Xilinx XC4000 family FPGAs [START_REF]e and xc4000x series field programmable gate arrays (version 1.6)[END_REF].

3D CB

The connection box (CB) is composed of two different blocks: one block to connect the output of LB to the channels (CB out ) and one block to connect the channels to the input of LB (CB in ). CB in is designed with 32-input MUXs. LB input number (I) is set to 10 and the inputs are distributed along each side of the LB as 3 inputs in the south, 2 in the north, 3 in the east, and 2 in the west. Thus, each CB in between 2 LBs

3D TILE

Using the previously designed blocks, FPGA tiles are designed. As explained in Section 2.1.2., FPGA is comprised of replicated tiles. The tile contains a LB, a SB, and two CBs that interface the LBs and SBs.

Two different tiles are constructed with the 2D and 3D blocks. Fig. 5.7a and 5.7c

show the 3D and 2D tiles respectively. The layout of the tiles are similar because the conventional FPGA architecture is preserved. The height of the tiles are kept the same because same logic and routing structure is adopted for the two tiles. Fig. 5.7b shows the memory layer of the 3D tile. It can be observed that logic-on-memory partitioning achieves high area utilization between the two layers.

Performance Comparison of 2D and 3D Blocks

For each 3D block described in the previous section, the corresponding 2D blocks are also designed in the layout. Post-layout parasitic extraction is carried out for each cell and all the parasitics are back annotated. The extracted netlist with parasitics is simulated with ELDO and, delay and power metrics are measured. Dynamic power values assume an activity of 2GHz. Table 5.1 shows the performance metrics for the 2D and 3D MUX4s. A gain of 51%, 14% and 12% in area, delay and power can be achieved. More than 50% of area reduction is achieved because the MUX4 and buffer shapes enable closer placement.

Since the area is significantly reduced, the routing complexity is lowered. As a result, the output is generated faster with decreased power consumption. Furthermore, since the CRAM cells are connected to the selection input of the MUXs, the CRAMs are not on the critical path. Therefore, no effect from the inter-tier vias is observed on the performance. Table 5.2 shows that the LUT4 area can be reduced by 56% but the delay and power are increased by 1% and 3%. In the 3D LUT4 although the routing is simplified, the additional capacitance on the critical path introduced by the vertical inter-tier vias connection increases the delay and the power consumption. Table 5.3 shows the performance metrics for the 2D and 3D CBs. It can be observed that the area is lowered by 39%, delay by 5% and power by 4%. The decreased area reduction in the CB is due to the 3D MUX32s since they only have 5 SRAM cells which are placed in the bottom layer. Thus, the area cannot be reduced as much as it is for the MUX4s.

Table 5.4 shows the performance figures for the SB. Since the SB is constructed with replicated MUX4 cells, similar results are expected for the SB figures. Compared to the 2D SB, 3D SB provides improvements by 55% reduction for area, 12% for delay and 5% for power. The area gain is more than that of MUX4 because the layout can be optimized by active area sharing which enables overlapping source/drain connections if they are connected to the same signal. Fig. 5.8 shows that the active area connecting to the same supply lines are overlapped which reduces total area. Delay and power metrics improves with less gains than MUX4 due to the increased capacitance and length of wires. 5.5 shows the performance figures for the 3D tile. 2D tile occupies an area of 287.8µm 2 . On the other hand, the 3D tile requires an area of 157.6µm 2 . The placement of memory cells to the bottom layer grants area reduction of 47%. The power and delay metrics are decreased by 6.2% and 2.4% respectively due to the reduced wirelength and

3D-FPGA WITH MONOLITHIC INTEGRATION

overall capacitance. Despite the the higher capacitance 3D vias which are introduced in 3D LUT, overall improvements are still observed.

Evaluation on 3D-FPGA with Logic-on-Memory Approach

In order to correctly evaluate the changes in the planar and 3D circuits, first the results from post layout simulations are extracted. Using the flow in Section 3.3., the architecture files for 2D and 3D FPGAs have been created. The timing model is updated with the wirelength and capacitance reductions. The area model is updated with the parameterized memory area in Fig. 3.7 by allocating no area for the configuration memory since the 3D architecture is constructed with logic-on-memory approach.

The architecture parameters of the 3D-FPGA for VPR experiments are shown in Table 5.6. The parameters are set to match the previously designed FPGA blocks. A set of MCNC benchmark circuits are evaluated with this configuration. It can be observed in Fig. 5.9 that the area is reduced by 55%. The area benefits of 3D Monolithic Integration can be described as follows: First, the memory is completely removed from the logic layer. Second, due to the high density of vertical connections, replacing the memory on the bottom layer does not impose any routing congestion.

Especially, the use of metal layers between the top and bottom layers enables very flexible memory placement while keeping high proximity to the logic layer.

The Energy-Delay Product (EDP), as shown in Fig. 5.10, can be reduced by 47%

with the proposed 3D FPGA. The improvement in the EDP is twofold: The intrinsic delays of the blocks are reduced with 3D integration due to simplified internal routing and the wirelength between blocks decreases leading to lowered wiring capacitances.

In LUT4, however, even though the area is decreased, as well as the internal routing, the intrinsic delay becomes higher because of the vertical interconnects which represent additional loading to the critical path and power consumption (Table 5.2). After the VPR run, the results show that there is a significant reduction in the EDP. The main reason is, even though the 3D LUT has increased delay, shorter wire length in the global routing between blocks due to lowered area overcomes this effect and the EDP is further improved.

Multi-tier 3DFPGA

In the previous section, all the corresponding blocks for 2D and 3D FPGA are designed and the 3D-FPGA with logic-on-memory approach is evaluated. Using the library of 2D and 3D blocks and considering different partitioning granularities, multitier FPGA exploration can be carried out. In this section, several blocks partitioning schemes are analyzed considering 2, 3, and 4 active layers integration. Fig. 5.11 depicts the baseline 2D FPGA TILE designed in Section 5.2.2.5..

2-Tier FPGA Stack

Two different schemes are considered for two layer integration (Fig. 5.12). The first scheme (2L_1) refers to the FPGA designed in Section 5.2.4. in which the blocks are separated in logic-on-memory approach. This FPGA is considered for comparison with other partitioning schemes. In the second scheme (2L_2), 2D layout is separated into two tiers, with block level partitioning. The LB and one CB are placed in one layer and the remaining CB and SB are placed into the other. The effect of 3D vias is observed due to the crossing of the critical path signal into the second layer. Nevertheless, the wirelength is significantly reduced compared to the 2D layout.

3-Tier FPGA Stack

For an implementation including three active layers, two different schemes are analyzed (Fig. 5.13). In the first scheme (3L_1), the LB is kept in one layer. The CBs are placed in separate layers and the SB is divided into two layers. Since the LB and CBs are in different layers, the effect of 3D vias is observed on the local routing between CB and LB. The effect of 3D via on the global routing is minimized because the partial SBs are kept on the same layer as CBs. In the second scheme (3L_2), the LB is separated into two (2x BLEs each) layers. CBs are put close to the BLEs and the SB is kept as one block in middle layer. The internal delay of LB is increased because of the additional 3D vias. Since SB is in the middle layer, global routing is carried out in one layer and the effect of 3D vias is minimized. When three layers are considered, logic-on-memory approach cannot be applied because it does not significantly improve area results compared to 2-tier: logic-on-memory requires even number of tiers due to inherent symmetric area partitioning.

4-Tier FPGA Stack

For an implementation including four active layers, two different schemes are analyzed (Fig.

Multi-tier FPGA Performance Evaluation

For the evaluation of the proposed stacking schemes, several benchmarks are analyzed in VPR5 with Power Extension flow 3.3.. Separate VPR architecture files are created for each of the partitioning schemes. The 2D and 3D logic-on-memory cell layouts in 14nm using 3D add-on are characterized. In order to observe the realistic effects of the schemes, wirelength and capacitive loading of the wires are modeled based on the area improvements. Table 5.7 shows the results of several FPGA benchmark circuit evaluations considering multiple tiers with 3D monolithic integration. The final average values of all schemes are normalized to 2D for comparison.

Starting from 2-tier schemes, compared to 2D, significant area improvements are

3DMI Impact on Scaling

observed as the number of tiers is increased. The area is reduced up to 55%, 69% and 77% in comparison to 2D for 2, 3, and 4-tier implementations respectively.

The results for EDP show that the reduction in area improves the EDP substantially. According to the results two different types of improvements are observed: 1) reductions due to shorter wirelength and less capacitive loading and 2) reduction of gate internal delay and capacitive loading due to logic-on-memory approach. When two layers are considered, EDP can be reduced by 47% and 26% for the different schemes in comparison to 2D. In 2L_2, the partitioning is performed using 2D blocks and in 2L_1, logic-on-memory approach is applied. Specifically, in 2L_2 reductions stem purely from the shorter wirelength. In 2L_1, however, the delay is reduced not only by shorter wirelength but also by smaller internal delay of the blocks as a result of the logic-on-memory approach. In three and four layer solutions, it is possible to observe the effect of decreased wirelength. In three layers, up to 40% EDP reduction is observed depending on the scheme and in four layers, up to 66% compared to 2D. These results show that the improvement in delay is proportional to the reduction in wirelength however, redesign of blocks (eg. with logic-on-memory approach) can further improve EDP.

3DMI Impact on Scaling

In this section, the best results obtained by multi-tier FPGA partitioning exploration are compared to the scaling expectations. The reason is that when the number of integrated layers with 3DMI are increased, logic density, performance, and power efficiency values are improved. Traditional scaling defined by Moore's law also aims to make these values better with each advancing node. The comparison between 3DMI multi-tier stacking and traditional scaling demonstrates what can be achieved from 3DMI for future implementations.

Recent ITRS 2013 report [START_REF]System driver summary[END_REF] concludes that the transistor count is expected to continue scaling by 1.6x per node. Similarly in 3DMI, as more layers are stacked, the logic density increases. Expected ITRS trend and the highest 3DMI area improvements from previous results are illustrated in Fig. 5.15. The designed 2L FPGA in 14nm decreases the area by 27% more than traditional 10nm scaling can achieve. 3L integration in 3DMI can be comparable to an intermediate node which provides 40% improved area figure. Finally, 4L FPGA integration in 14nm exceeds the gains in 7nm by 41%.

It is also interesting to notice in Fig. 5.15 that the extrapolated 2D FPGA in 7nm node and the 2L 3D FPGA exhibit similar area gains with only 14% difference. Since the difficulties of traditional scaling affect the gains per each node advancement, it is expected that this difference between 2D and 3D case will be narrowing down for the new nodes. Thus, the area gain with 2-tier case might attain the same level as advancing two nodes with scaling in the future.

Based on the ITRS report [169], the EDP improvements, up to 7nm node, are calculated. The ITRS trend and the highest 3DMI EDP improvements from the designed FPGAs are illustrated in Fig. 5.16. It can be observed that for the 2L implementation in 14nm not only reaches 10nm node performance but also further improves it by 24%.

Since logic-on-memory approach is not utilized in 3L, the relative improvement is only by 6%. This result shows the importance of partitioning as the gain is strongly corrolated to the design when using 3DMI technology. The 3L case can be an intermediate node which targets low area (due to the improvements in Fig. 5.15) while still keeping similar performance to the next scaling advancement. The 4L implementation in 14nm surpasses the 7nm improvements by 29%.

It is also worth noting in Fig. the difficulties in scaling, this difference might disappear in the near future. Thus, the 2-tier 3D-FPGA in 14nm can reach the same efficiency of a 2D-FPGA in 7nm.

This shows that the integration with 2 tiers might be an alternative to not only one technology node but two nodes advancement.

Consequently, multi-tier 3DMI shows a very efficient way of improving the logic density and EDP. When the number of integrated layers is doubled, the gains not only reach the scaling improvements of one node but also outperform them. Furthermore, considering the reduced gains of scaling trends, doubling the number of layers might exhibit the same gains as two nodes advancement with scaling. Therefore, multi-tier 3DMI is a very strong alternative for future scaling.

Conclusion

In this chapter, the details about 3DMI technology are explained and the advantages that it can bring to the future 3D FPGA designs are discussed. 3DMI offers a very unique design opportunity due to the high density inter-tier connections while integrating multiple active layers on the same die. FPGAs can benefit from these dense connections to separate the logic and configuration memories which are distributed and consume a large portion of FPGA surface. 3DMI also enables optimizing the layers individually which allows placement of low leakae devices for memories on one layer and high performance for logic on the other one.

Initially, taking advantage of 3DMI, all the FPGA blocks are designed by separating the memory and logic cells in 2 layers with logic-on-memory approach. All the designs are realized with 3D 14nm FDSOI process. By benefiting from high density intertier connections, the design effort is put for compact layouts and no area overhead is observed due to the inter-tier vias. It is proven that 3DMI reduces the total area and the routing complexity significantly. Moreover, the performance and power consumption metrics are improved substantially due to decreased wire lengths and capacitances.

Several 3D FPGA designs are analyzed using the designed blocks. First, an FPGA including 2 active layers is designed and evaluated with FPGA benchmark circuits. In this thesis, we are motivated by the opportunities of emerging 3D technologies from which the FPGAs can take advantage. Available technologies are vast and they have advantages on different levels. Hence, these technologies should not only be assessed but also exploited in order to find the unique benefits. In this work, we have proposed an evaluation framework for emerging technologies applied to FPGAs. Using the FPGA evaluation framework, several emerging 3D technologies (OxRAM, CBRAM, and 3DMI) have been assessed. The results show that circuit footprint can be significantly reduced with 3D technologies mainly because some of the circuit functionality can be integrated in the third dimension. Moreover, the simplified routing enables higher performance and low power consumption. Apart from that, the inclusion of nonvolatility leads to greater power savings with added functionality. All these results

show that FPGAs are one of the leading computing platforms which offers many opportunities for improvement and now we can rethink how the FPGAs will be employed in future computing systems.

In this concluding chapter, results are discussed for final comparison of gains achieved with these emerging technologies. The contributions are also summarized and future

CONCLUSION & PERSPECTIVES

perspectives are provided for further continuation of this research. In this thesis emerging 3D technologies, RRAM and 3DMI, are analyzed for future adoption possibilities in FPGAs. The benefits from these technologies are estimated using the established FPGA evaluation framework. The results show that RRAM integration and active layer stacking with 3DMI accomplish significant benefits in terms of performance, power, and area (PPA). In the thesis work, these technologies are studied individually but as a short term future work, an FPGA design can be envisioned using both of these technologies. Recently, Zhang et al. fabricated an FPGA with low temperature 3DMI process and RRAM integration for the purpose of proof concept [START_REF] Zhang | Low-temperature monolithic three-layer 3-d process for fpga[END_REF].

In this FPGA RRAM-based cells are integrated to replace the configuration memories and in the second active layer, PMOS transistors are integrated. PMOS-only second layer limits partitioning possibilities to only transistor-on-transistor approach. In the new FPGA, the memory cells can be replaced with a cell similar to the previously examined NVE cell in Chapter 4. The rest of the logic and routing blocks can be partitioned using 3DMI. In this case, finding an efficient partitioning scheme is important because block separation should consider the layout designs of the blocks as well as the area of the control transistor in the NVE. The evaluation framework defined in Chapter 3 can be used for fast exploration of several partitioning schemes. The designed FPGA also supports Normally-off Instantly-on computing defined in Chapter 4 with which the power consumption can be further optimized.

Thermal impacts of FPGA designs with 3DMI

One of the main concerns in the design and manufacturing of 3D circuits is the heat dissipation [START_REF] Gayasen | Designing a 3-d fpga: Switch box architecture and thermal issues. Very Large Scale Integration[END_REF]. Stacking multiple layers and increased logic density lead to higher thermal density which is becoming more difficult to dissipate. The created hotspots impose challenges in packaging but also the circuit performance is linked to the ambient temperature. In order to address these concerns, in the 3DMI technology, the thermal model must be created based on the material stack including the thermal resistivity of the vias. FPGA blocks designed in Chapter 5 can be used towards circuit specific thermal evaluation. The effect of inter-tier vias on thermal dissipation can be also evaluated to find the best placement of vias for optimized thermal dissipation.

Reliable designs with SiNWFETs

Extreme scaling and increased operation frequencies lead the devices to deeper submicron levels. Hence, noise margins significantly shorten and circuits become severely susceptible to soft errors. In addition to these trends, the ever increasing complexity of the systems requires more efficient solutions for fault tolerance. In this context, integration of mature CMOS and emerging technologies might lead to unreliable systems.

Technological variabilities during the fabrication process due to the lack of maturity might highly impact the devices properties. This implies that these impacts should be expected during the design step where architectural solutions can target reliable operation with unreliable devices.

In order to demonstrate reliable design opportunities with emerging technologies, we designed a self-checking adder with Silicon Nanowire FETs (SiNWFET) in collaboration between LETI and EPFL [START_REF] Turkyilmaz | Selfchecking ripple-carry adder with ambipolar silicon nanowire fet[END_REF]. SiNWFETs present good channel control properties and limited fabrication complexity. They have strong arguments thanks to their classical CMOS material compatibility and they exhibit ambipolar behavior, i.e., both n and p-type conduction, that can be controlled by the use of an extra gate. Recently, very efficient implementations of digital circuits, e.g., XOR, have been demonstrated using this technology and more specifically its ambipolar property [START_REF] Sacchetto | Ambipolar gate-controllable sinw fets for configurable logic circuits with improved expressive capability[END_REF]. These XORs lead to the design of very compact full adder designs. In the designed self-checking 6.2. Future Works adder, SiNWFETs reduce the overhead arising from the application of self-checking.

Therefore, compared to CMOS design style up to 56% smaller and 62% faster adders can be achieved with reliable operation.

Design with SiNWFETs represent promising opportunities due to their reduced transistor count and increased functionality. For future work, the same concept of self-checking property can be applied to other arithmetic blocks such as multipliers.

The designed blocks can be included in the datapath of a processor in ASIC or DSP.

Additionally, in FPGAs, heterogeneity is an increasing trend for future FPGAs as more dedicated units are included as a part of circuit. SiNWFET-based blocks can be integrated as standalone units for reliable FPGA operation. The exploration framework defined in Chapter 3, can be used for the estimation of impacts on area, performance, and power consumption as it supports evaluation with heterogeneous blocks. La structure des transistors classiques impose des difficultés de fabrication avec des noeuds avancés. La complexité du processus de lithographie augmente avec chaque noeud avancé. Ainsi, des nouvelles technologies de lithographie ou plusieurs étapes de patterning sont nécessaires qui augmentent le coût de production considérablement.

A Résumé en Français

Deuxièmement, la partie plus petite du transistor, la largeur du diélectrique de grille, a récemment atteint la taille de plusieurs atomes, qui impose des problèmes suivants: la dépendance supérieur au nombre d'atomes qui changent en raison des variations dans la fabrication et la réduction de la barrière porte qui augmente les courants de fuites.

Outre implications de fabrication, les gains de performance diminuent en raison des limites sur les interconnexions. Même si les transistors diminuent, les circuits ne peuvent pas atteindre des performances élevées sans interconnexions rapides et denses. dans le scaling traditionnel.

La consommation croissante de la puissance inévitable a mené à la fin de la théorie de Dennard [START_REF] Dennard | Design of ion-implanted mosfet's with very small physical dimensions[END_REF].

A.1.3. Résumé de la Thèse

Le manuscrit est construit en trois sections principales qui sont expliqués de la manière suivante suivante: Dans la section A.2. , le cadre de l'exploration des FPGA et de la méthodologie pour l'adoption de nouvelles technologies sont présentés. Le chapitre commence par une synthèse des outils CAO FPGA. Les détails du cadre de l'exploration du FPGA sont discutées. Une méthodologie est présenté pour l'adoption rapide de nouvelles technologies grâce à des modifications de définition de l'architecture FPGA. Cette plateforme d'évaluation établit la base pour le reste de la thèse. A.19 pour les mesures de chemin critique, de surface et de consommation énergétique.

L'intégration NVSRAM présente des augmentations de 6%, 17%, et de 1,5% de délai, de surface et de consommation énergétique respectivement en raison de la surface de la cellule NVSRAM. L'intégration NVFF mène à des augmentations de 3%, 1% et 1% de délai, de surface et de consommation énergétique respectivement en raison de la surface de la NVFF. Initialement, un ratio entre t 1 et t 0 peut être définie lorsque l'énergie de fuite pendant t 1 est égale à l'énergie dépensée au cours de t 0 en raison de la surcharge de puissance:

A.3.2. Optimisation des

I leakage = V dd -V ss R ON + R OF F ≈ V dd R OF F (A.1)
t+t

2. 16 5 FPGA

 165 STT-RAM memory cell with 1T/1MTJ structure. Data is stored in the form of magnetization in the MTJ. a) The parallelized state exhibits low resistance to represent the logic 0. b) Anti-parallelized state exhibits high-resistance to represents the logic 1. c) Memory cell circuit connection between bit line (BL), source line (SL) and word line (WL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.17 (a) Phase-change memory cell schematic. When electrical current flows between the top electrode and the bottom electrode, the heater affects the boundary in the phase-change material to form high/low resistance states. (b)The device is programmed and read by electrical pulses which change the temperature accordingly.(Adapted from [11].) . . . . 30 2.18 RRAM memory cell cross-section with select transistor. . . . . . . . . 31 2.19 RRAM I-V characteristics for a) unipolar devices and b) bipolar devices.(Adapted from [12].) . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.20 CBRAM device switching mechanism for SET and RESET operations. (Adapted from [13].) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.21 3DIC assembly diagrams. a) SOI-based face-to-back process. b) faceto-face bonding. c) face-to-back process with deep vias formed between layers. (Adapted from [14].) . . . . . . . . . . . . . . . . . . . . . . . . 37 2.22 Cross-sectional view of 3D monolithic integration. Inter-tier vias are fabricated as traditional vias ensuring very small footprint and high interconnect density. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.23 3D partitioning for circuits from coarse to fine grain [15] a)Core-on-core b) Functional unit block c) Gate-on-gate d) Transistor-on-transistor. . 39 3.1 Architecture exploration empirical FPGA flow [16]. . . . . . . . . . . . 46 3.2 Typical FPGA CAD flow. . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3 VPR5 with power estimation toolflow. . . . . . . . . . . . . . . . . . . 53 3.4 Architecture definition file for VPR5. . . . . . . . . . . . . . . . . . . . 55 3.Exploration platform with emerging technologies. . . . . . . . . 58 3.6 Methodology for architecture definition creation with emerging technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.7 Parameterized memory cell area. . . . . . . . . . . . . . . . . . . . . . 60 xiii LIST OF FIGURES 4.1 NVSRAM schematic of 8T2R architecture [17]. . . . . . . . . . . . . . 4.2 NVSRAM operation cycle: Normal SRAM operation -Reset -Store -Power-down -Power-up -Restore. . . . . . . . . . . . . . . . . . . . 4.3 NVFF architecture with non-volatile block based on RRAM, the RRAMs store the slave state in NVM_L and NVM_R blocks. . . . . . . . . . 4.4 Control signal and state transition of NVFF. . . . . . . . . . . . . . . 4.5 NVE circuit scheme for programming and reading of CBRAM cells in voltage divider configuration. . . . . . . . . . . . . . . . . . . . . . . . 4.6 (a)NVE configuration node connection in the FPGA switches.(b)NVE configuration node connection in the FPGA LUTs. . . . . . . . . . . . 4.7 Critical path delay of FPGA benchmark circuits for SRAM and NVS-RAM integration. The results show an increase in delay on average by 7%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5. 10 OF TABLES 5 . 7 127 A. 1 160 A. 2 1 Introduction Contents 1 . 1 . 1 1. 2 . 4 1. 3 . 5 1. 4 . 6 1. 4 . 1 . 6 1. 4 . 2 . 7 1. 4 . 3 . 8 1. 5 .

 10571271160211112435464164274385 figuration memory (CRAM) on the bottom and logic on the top tier. b) block-level partitioning (2L_2): 2D blocks are separated between two tiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Block level FPGA partitioning in 3 tiers: a) 3L_1 b) 3L_2. . . . . . . 5.14 Block level FPGA partitioning in 4 tiers: a) 4L_1 b) 4L_2. . . . . . . 5.15 Projection of area improvement for future technology nodes based on ITRS roadmap and gain from multi-tier 3DMI approach. . . . . . . . 5.16 Projection of EDP improvement for future technology nodes based on ITRS roadmap and gain from multi-tier 3DMI approach. . . . . . . .

Figure 1 . 1 :

 11 Figure 1.1: Transistor and interconnect delay scaling for future nodes. Adapted from [1].

Figure 1 . 2 :

 12 Figure 1.2: Total chip dynamic and static power dissipation trends based on ITRS2006 [2]. Gate leakage is improved significantly with High-k materials.

Figure 1 . 3 :Figure 1 . 4 :

 1314 Figure 1.3: Emerging 3D technologies.

1. 4 .

 4 Research Contributionstechnological impacts and maps benchmarking circuits onto the fabric to obtain area, performance, and power consumption values. A methodology is proposed for accurate architectural and technological modeling. In this methodology, post layout parameters are extracted and the blocks are characterized in terms of area, delay and power.With these values an architectural definition is created which allows FPGA evaluation platform (Versatile Place and Route-VPR-based) to be used for fast evaluation of design level improvements on real Microelectronics Center of North Carolina (MCNC) benchmark circuits. This developed platform forms the basis for all explorations with targeted emerging technologies in this work.1.4.2. RRAM-based NVFPGAIn this thesis, we focus on FPGA evaluation using Non-Volatile Memory (NVM)based blocks with Oxide Random Access Memory (OxRAM) and Conductive Bridge RAM (CBRAM) technologies. Main contributions include the improvement assessment of design with each technology. Furthermore, new low-power application fields are targeted taking advantage of the Resistive RAM (RRAM) non-volatility. First, novel RRAM-based architectures are characterized in terms of area and power consumption. With OxRAM, Non-Volatile Static Random Access Memory (NVSRAM) and Non-Volatile flip-flop (NVFF) circuits and with CBRAM, a voltage-divider based Non-Volatile memory Element (NVE) are analyzed through layout and power simulations. The characterization results for each RRAM-based block are reported. In the next step, RRAM-based modules are integrated in the FPGA by replacing each corresponding module with the non-volatile counterpart. FPGA architecture models are created based on the characterized blocks. When all the Static Random Access Memories (SRAM) are replaced with NVSRAM or NVE, configuration-saving applications and when all FFs are replaced with NVFF, context-saving applications are targeted. Consequently, Non-Volatile FPGA (NVFPGA) operation is achieved and the FPGA employability is extended with new set of applications utilizing non-volatility.

  technology adoption is presented. The chapter starts with an overview the FPGA CAD flow in Section 3.1.. It explains the properties of available open-source FPGA tools. In Section 3.2., the details of the FPGA exploration framework are discussed. Architecture definition, area, performance, and power modeling, and MCNC benchmark circuits are explained in the sections between 3.2.1. -3.2.3.. The final section, 3.3., presents a methodology for fast adoption of emerging technologies through modifications for FPGA architecture definition.

  3.1.. System level implications of NVM-based low-power FPGA are determined for each technology in the final section, 4.3.2.. In chapter 5, 3D-FPGA with monolithic integration is proposed. 3D Monolithic Integration technology is detailed in section 5.1.. The Logic-on-Memory approach is explained in section 5.2.. The designed 3D blocks are included in section 5.2.2. and the performance of the blocks are compared to the 2D in section 5.2.3.. Using the VPR flow, the designed blocks are evaluated in FPGA. In section 5.2.4., 2D and 3D FPGAs are compared in terms of area, delay and power consumption. Section 5.3. discusses a multi-tier 3D FPGA approach. Starting from two up to four layers are evaluated in section 5.3.4.. Multi-tier FPGA results are compared to traditional scaling expectation in Section 5.4.. In chapter 6, all the results obtained from this work are summarized for global comparison. The contributions of the research work are highlighted and possible future extensions are presented.

Figure 2 . 1 :

 21 Figure 2.1: Island-style FPGA architecture.

Figure 2 . 2 :Figure 2 . 3 :Figure 2 . 4 :Figure 2 . 5 :

 22232425 Figure 2.2: Transistor pair tiles in Crosspoint FPGA [4].

Figure 2 . 6 :

 26 Figure 2.6: Xilinx Virtex-7 slice diagram [5].

Figure 2 . 7 :

 27 Figure 2.7: Altera Stratix-V ALM diagram [6].

Figure 2 . 10 :

 210 Figure 2.10: Bidirectional routing switches.

Figure 2 . 11 :Figure 2 . 12 :

 211212 Figure 2.11: Unidirectional routing switches.

Figure 2 . 13 :

 213 Figure 2.13: 5T-SRAM cell for configuration node in FPGA.

Figure 2 . 15 :

 215 Figure 2.15: (a)Detailed breakdown of leakage power consumption of Xilinx Spartan-3 [9]. (b)Detailed breakdown of dynamic power consumption of Xilinx Virtex-II [10].

Figure 2 . 16 :

 216 Figure 2.16: STT-RAM memory cell with 1T/1MTJ structure. Data is stored in the form of magnetization in the MTJ. a) The parallelized state exhibits low resistance to represent the logic 0. b) Anti-parallelized state exhibits high-resistance to represents the logic 1. c) Memory cell circuit connection between bit line (BL), source line (SL) and word line (WL).

Figure 2 . 17 :

 217 Figure 2.17: (a) Phase-change memory cell schematic. When electrical current flows between the top electrode and the bottom electrode, the heater affects the boundary in the phase-change material to form high/low resistance states. (b)The device is programmed and read by electrical pulses which change the temperature accordingly.(Adapted from [11].)

Figure 2 . 18 :Figure 2 . 19 :

 218219 Figure 2.18: RRAM memory cell cross-section with select transistor.

  PZT). These cells exhibit non-volatile property however there are drawbacks due to low-compatibility with standard CMOS and large cell footprint. Toshiba recently fabricated a 128Mb chain FRAM memory to reach 25% low operation energy with high read/write bandwidth of 1.6GB/s[START_REF] Takashima | A 128 mb chain feram and system design for hdd application and enhanced hdd performance[END_REF]. Koga et al. proposed an FPGA in which the configuration SRAM cells are replaced with a FRAM-based Non-Volatile Flip-Flop (NVFF)[START_REF] Koga | First prototype of a genuine power-gatable reconfigurable logic chip with feram cells[END_REF]. Through the use of power gating a low stand-by power mode is established with a power-on duration of 1ms. Since the NVFFs are 9.6x bigger than a regular FF, the performance of the designed FPGA decreases by 1.8x. A work from Lien et al. demonstrates NVM/CMOS hybrid chip using FRAM-like nonvolatile memories and transistor stacking with 3D sequential integration[START_REF] Lien | 3d ferroelectric-like nvm/cmos hybrid chip by sub-400c sequential layered integration[END_REF].

Figure 2 . 21 :Figure 2 . 22 :

 221222 Figure 2.21: 3DIC assembly diagrams. a) SOI-based face-to-back process. b) face-to-face bonding. c) face-to-back process with deep vias formed between layers. (Adapted from [14].)

Figure 2 . 23 :

 223 Figure 2.23: 3D partitioning for circuits from coarse to fine grain [15] a)Core-on-core b) Functional unit block c) Gate-on-gate d) Transistor-on-transistor.

  based memories[START_REF] Paul | A circuit and architecture codesign approach for a hybrid cmos sttram nonvolatile fpga[END_REF][95][START_REF] Guillemenet | Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories[END_REF].STT-RAM based-FPGA logic circuits are presented targeting runtime reconfiguration and multicontext configuration [97]. Only LUT and routing switches are proposed and compared with other MRAM technologies such as TAS-MRAM and FIMS-MRAM. STT-RAM shows the highest benefits compared to other MRAM technologies and reaches up to 50% smaller LUT compared to SRAMbased counterpart. Paul et. al. proposed CMOS and STT-RAM hybrid approach for

Contents 3 . 1 .

 31 CAD for FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1. Front-end Synthesis . . . . . . . . . . . . . . . . . . . . . . . 3.1.2. Technology Mapping . . . . . . . . . . . . . . . . . . . . . . 3.1.3. Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4. Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.5. Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3 . 1 :

 31 Figure 3.1: Architecture exploration empirical FPGA flow [16].

Figure 3 . 2 :

 32 Figure 3.2: Typical FPGA CAD flow.

compose

  Basic Logic Elements (BLE). In the second stage, N LUTs are grouped together to form clusters. In this phase of CAD flow, clusters are created using the technology mapped BLIF netlist consisting of LUTs and FFs. Clustering tool groups several LUTs and the associated registers into one logic block, considering the limitations such as the number of LUTs contained in a logic block, the size of the LUT, independent number of input signals and clocks associated with the logic block. The main optimization goals are to cluster connected LUTs together to minimize the routing complexity between logic blocks and to reduce the number of logic blocks by utilizing the maximum capacity of each logic block. Clustering problem is mainly dividing the netlist into several pieces each of which containing minimum number of interconnections while respecting constraints such as maximum partition size. Packing communicating BLEs together improves routability and critical path delay significantly [117]. Specifically, through clustering most of the global connections are converted into local connections. The efficiency of clustering depends also on LUT size.

  mization goals and architectural modifications. The algorithm in simulated annealing starts with an initial random placement of logic blocks to available locations in FPGA.Pairs of blocks are randomly selected and swapped repeatedly. At the end of each swap, the change in cost is calculated based on the new location. If the cost decreases, the new location is always accepted and the block is moved. If the cost increases, the block may or may not be moved depending on the improvement in the further steps. The output of placement stage is the detailed floorplan with an accepted location of all the resources.Several tools are proposed for the placement of blocks in FPGAs. In general, the main objective is to minimize the wirelength between blocks. In all the tools, simulated annealing is selected as the placement algorithm. Betz et al. proposed VPlace tool as a part of Versatile Place and Route (VPR) tool[START_REF]Architecture and CAD for Deep-Submicron FPGAs[END_REF]. VPlace attemps to minimize the amount of the interconnect required by placing the blocks that on the same net close together. The cost function is calculated based on wire-length estimation between placed blocks.Since the amount of routing in FPGAs is limited, the placement tool can optimize not just the wirelength but also the routability. Ebeling et al. developed a placer for Triptych FPGA[START_REF] Ebeling | Placement and routing tools for the triptych fpga. Very Large Scale Integration (VLSI) Systems[END_REF]. Apart from the term for wirelength optimization, similar to VPlace, the cost function of the placer includes another term which monitors the fraction of logic blocks in a local area that are being used. Marquardt et al. proposed the tool called T-VPlace, which is part VPR tool, as a timing-driven placement algorithm [130]. The main objective of T-VPlace is to minimize total wirelength and critical path delay. The cost function of T-VPlace has therefore two components: wiring cost, which is the sum of all dimensions of all nets and timing cost, which is the sum of connection delays weighted based on how close they are to the critical path.

3. 2 .Figure 3 . 3 :

 233 Figure 3.3: VPR5 with power estimation toolflow.

Figure 3 . 4 :

 34 Figure 3.4: Architecture definition file for VPR5.

Figure 3 . 5 :

 35 Figure 3.5: FPGA Exploration platform with emerging technologies.

3. 5 .

 5 Depending on the maturity of the technology, cells are designed and characterized either at the device or block level. With this characterization, FPGA architecture definition is created. This definition is used as an input to the VPR-based CAD flow for performance, area, and power evaluations.

Fig. 3 .

 3 Fig. 3.6 is proposed for the development of the architecture definition with emerging technologies.

  After the layout is completed, design and technology related parameters are extracted for architecture definition development. The parameters span from transistors, to configuration memories and blocks. First transistor related parameters are extracted. Transistors parasitics capacitances are necessary for the calculation of dynamic power. Transistor dimensions are used for the area estimation of the FPGA circuit. With these parameters, technological details of transistors are introduced in the architecture definition. Memory properties refer to the configuration memories in the FPGA. Cell area allows the estimation of the configuration memory area of the FPGA. Leakage power refers to the leakage power consumption of one memory cell and it is included in the calculation of total leakage of FPGA circuit. In the next step, FPGA building blocks are characterized. FPGA blocks are designed with full-custom design rules. Using the layout dimensions of the blocks, area related parameters are calculated. The blocks are then simulated considering the parasitic extraction. I/O capacitance, resistance and delay of the blocks and segments are carefully measured. With this methodology, FPGA architectures can be evaluated following closely the technological impact and achieving very rapid adoption of emerging technologies.

Figure 3 . 6 :Figure 3 . 7 :

 3637 Figure 3.6: Methodology for architecture definition creation with emerging technologies. <device> <trans_sram trans_sram_bit= " 6" /> </device> Figure 3.7: Parameterized memory cell area.

  RRAM-based Elementary Circuits . . . . . . . . . . . . . . . . . . . 4.1.1. Non-volatile SRAM (NVSRAM) . . . . . . . . . . . . . . . 4.1.2. Non-volatile Flip-Flop (NVFF) . . . . . . . . . . . . . . . . 4.1.3. NVE-based Design . . . . . . . . . . . . . . . . . . . . . . . 4.2. Towards Non-volatile FPGA . . . . . . . . . . . . . . . . . . . . . .

  Non-volatility can be introduced in the FPGA using Non-Volatile Memories (NVM)based circuit elements. For the quest of non-volatile FPGA all the volatile elements have to be replaced. Mainly the memory is used for configuration storage (CRAM) as explained previously. Apart from CRAMs, the registers, Flip-Flops (FF) in the Basic Logic Elements (BLE), are also volatile elements of FPGA. A FF stores 1-bit result of the computation completed in the corresponding Look-Up Table (LUT). For the exploration with non-volatile elements, OxRAM and CBRAM based solutions are analyzed in FPGAs. For the replacement of CRAMs, first, OxRAM-based non-volatile SRAM (NVS-RAM) cells are integrated in FPGAs by replacing the SRAM counterparts. An NVS-RAM operates exactly as an SRAM with the extended capability due to the nonvolatile devices. Second, CBRAM-based 1T2R cell is used as CRAM by replacing the SRAM memories. This cell takes advantage from the high resistance window offered by CBRAM which allows to design a very compact cell.

4. 1 . 1 . 4 . 1 . 1 . 1 .Figure 4 . 1 :

 11411141 Figure 4.1: NVSRAM schematic of 8T2R architecture [17].

Figure 4 . 2 :

 42 Figure 4.2: NVSRAM operation cycle: Normal SRAM operation -Reset -Store -Power-down -Power-up -Restore.

  dissipation for each operation and total area of an NVSRAM cell are extracted. All the simulations are performed using Eldo simulator from Mentor Graphics and the results are validated on 22nm FDSOI process design kit (PDK) developed at CEA-LETI. A bipolar OxRAM model, calibrated on experimental results obtained on Hf O 2 -based devices, is included for simulations[START_REF] Cagli | Experimental and theoretical study of electrode effects in hfo2 based rram[END_REF]. NVSRAM cell is optimized to achieve data store and restore operations at 20ns with low operating voltage of 1V. During powerdown phase, a duration of 3.8µs is necessary to discharge all the capacitances.

FF_STRFigure 4 . 3 :

 43 Figure 4.3: NVFF architecture with non-volatile block based on RRAM, the RRAMs store the slave state in NVM_L and NVM_R blocks.

. 4 .

 4 In the normal operating mode of the flip-flop, the input data is latched in the master stage at active low clock signal and subsequently pushed to the slave part to be available at the output for following clock signal. During this phase all the control signals (STR_-RST_CTRL, CE, RESET_ENABLE, CTRL) governing the NVM blocks are inactive and, hence, the NVM blocks are isolated. The RRAMs remain in High Resistive State (HRS).

Figure 4 . 4 :

 44 Figure 4.4: Control signal and state transition of NVFF.

4. 5

 5 is proposed in collaboration between LETI and IM2NP[START_REF] Onkaraiah | A hybrid cbram/cmos look-up-table structure for improving performance efficiency of field-programmable-gate-array[END_REF]. The cell only requires one transistor (1T) which is used for programming of the cell and two resistive devices (2R) in complementary resistance states (one in High Resistance State (HRS) and one in Low Resistance State (LRS)). Since the resistive devices are fabricated at the BEOL,

Figure 4 . 5 :

 45 Figure 4.5: NVE circuit scheme for programming and reading of CBRAM cells in voltage divider configuration.

  3., CBRAM offers a very large HRS of 10 10 GΩ and wide on/off state resistance window of 10 6 . Thus, with CBRAM technology, reliable operation of resistive divider node can be achieved. The structure including one programming transistor and two CBRAM devices (1T2R) stores one bit of information. It can be integrated in the FPGAs to replace SRAM based configuration memory (CRAM) with NVE-based counterpart. Due to the compact layout NVE leads to reduction in FPGA silicon area in comparison to the traditional SRAM. Taking advantage of large HRS, the leakage consumption of the cell is in the range of SRAM.

Figure 4 . 6 : 4 . 1 . 3 . 3 . 4 . 1 . 3 . 4 . 4 . 2 .

 464133413442 Figure 4.6: (a)NVE configuration node connection in the FPGA switches.(b)NVE configuration node connection in the FPGA LUTs.

Figure 4 . 7 :Figure 4 . 8 :

 4748 Figure 4.7: Critical path delay of FPGA benchmark circuits for SRAM and NVSRAM integration. The results show an increase in delay on average by 7%.

tion 4 . 1 . 3 .Figure 4 . 9 :

 41349 Figure 4.9: Total power consumption of FPGA benchmark circuits for SRAM and NVS-RAM integration. The results show an increase in delay on average by 2%.

Figure 4 . 10 :

 410 Figure 4.10: Total area of FPGA benchmark circuits for SRAM and CBRAM integration. Reduced area values are achieved by 5% with NVLUT and 33% with NVFPGA.

Figure 4 . 11 :

 411 Figure 4.11: Critical path delay of FPGA benchmark circuits for SRAM and CBRAM integration. Reduced critical path delays are achieved by 24% with NVLUT and 34% with NVFPGA.

Figure 4 . 13 :

 413 Figure 4.13: Critical path delay of FPGA benchmark circuits for SRAM, NVSRAM and NVFF integration. The results show an increase in delay on average by 6% in NVSRAM and 3% in NVFF implementations.

Figure 4 . 14 :

 414 Figure 4.14: Total area of FPGA benchmark circuits for SRAM, NVSRAM and NVFF integration. The results show an increase in delay on average by 17% in NVSRAM and 1% in NVFF implementations.

Figure 4 . 15 :Figure 4 . 16 :

 415416 Figure 4.15: Total power consumption of FPGA benchmark circuits for SRAM, NVS-RAM and NVFF integration. The results show an increase in delay on average by 1.5% in NVSRAM and 0.5% in NVFF implementations.

Figure 4 . 17 :

 417 Figure 4.17: R OF F impact on FPGA total power consumption. Power consumption increase with reduced resistance value.

Figure 4 . 18 :

 418 Figure 4.18: Conceptual view of potential gain and power overhead of SRAM and RRAMbased implementations. During standby mode, the circuit with SRAM consumes leakage power, whereas it is possible to reduce consumption in the same mode to zero with RRAM integration.

Figure 4 . 19 :

 419 Figure 4.19: Power gating switch utilization for power down mode.

Figure 4 . 20 :

 420 Figure 4.20: Operating frequency/area trade-off in power gating application with 22nm FDSOI technology.

Figure 4 . 21 :

 421 Figure 4.21: Power gain depending on duty-cycle values for OxRAM-based FPGA with configuration saving applications. Considering 1% ON time, gained power reaches 50% on average.

Figure 4 . 22 :

 422 Figure 4.22: Power gain depending on duty-cycle values for CBRAM-based FPGA with configuration saving applications. Considering 1% ON time, gained power reaches 97% on average.

Figure 4 . 23 :

 423 Figure 4.23: Power gain depending on duty-cycle values for OxRAM-based FPGA with configuration and context-saving application. Considering 1% ON time, more than 40% power gain can be achieved.

5 3D 1 .

 51 scheme, power gating, is integrated by taking advantage of non-volatility. It has been demonstrated that the power consumption can be reduced up to 97% for Normally-off Instantly-on applications with the proposed NVFPGAs. The results from this chapter are published in[START_REF] Onkaraiah | A hybrid cbram/cmos look-up-table structure for improving performance efficiency of field-programmable-gate-array[END_REF][157][START_REF] Vianello | Resistive memories for ultra-low-power embedded computing design[END_REF][159][START_REF] Turkyilmaz | Rrambased fpga for normally off, instantly on applications[END_REF].

  3DMI allows sequential fabrication of several active layers on the same die. The fabrication is achieved with the following steps (Fig.5.1): fabrication of bottom transistor, top film deposition, and the realization of top transistor.

Figure 5 . 1 :

 51 Figure 5.1: Description of the process flow enabling to achieve stable performance bottom FET, high quality top substrate, high performance top FET with 600 • C process and 3D contacts realization.

Figure 5 . 2 :

 52 Figure 5.2: Logic-on-Memory approach

Figure 5 . 3 :

 53 Figure 5.3: Tile block diagram.

Fig. 5 .

 5 Fig. 5.3 shows the block diagram of the tile design assumption for the 2D and 3D FPGAs. LB is constructed with a cluster of 4 BLEs which contain 4-input LUTs (LUT4). Thus, N(number of BLEs in LB)=4 and K(number of input to LUT)=4. Each LUT4 input requires one 16-input MUX (MUX16) for selection from LB inputs.

  Bottom layer view.

Figure 5 . 4 :

 54 Figure 5.4: MUX4 full view

  Bottom layer view.

Figure 5 . 5 :

 55 Figure 5.5: 3D LUT4 design

Figure 5 . 6 :

 56 Figure 5.6: 3D SP design for SB.

  3D tile bottom layer view.

Figure 5 . 7 :

 57 Figure 5.7: 2D and 3D FPGA tiles.

Figure 5 . 8 :

 58 Figure 5.8: The supply connections designated in white box are overlapped due active area sharing for reduced total area.

Figure 5 . 9 :

 59 Figure5.9: Area of FPGA benchmark circuits for 2D and 3D architectures. Area can be reduced by 55% on average when designed in 3D.

Figure 5 . 10 :

 510 Figure 5.10: EDP of FPGA benchmark circuits for 2D and 3D architectures. EDP can be reduced by 47% on average when designed in 3D.

Figure 5 . 11 :

 511 Figure 5.11: Island style FPGA a) Highlighted FPGA tile. b) 2D layout based view of FPGA tile in 14nm. Distributed CRAM and logic cells are highlighted.

Figure 5 . 12 :Figure 5 . 13 :

 512513 Figure 5.12: FPGA design in two-tiers: a) logic-on-memory approach (2L_1): configuration memory (CRAM) on the bottom and logic on the top tier. b) block-level partitioning (2L_2): 2D blocks are separated between two tiers.

Figure 5 . 14 :

 514 Figure 5.14: Block level FPGA partitioning in 4 tiers: a) 4L_1 b) 4L_2.

  scheme (4L_2), the LB and SB are put into different layers. The CBs are placed close to the SB. In this way the effect of 3D vias on global routing is minimized. On the other hand, there is significant effect of the vias on the local communication between CBs and LB.

A. 1 .

 1 IntroductionJusqu'à présent nous nous sommes appuyés sur le scaling traditionnel afin d'augmenter la densité et la performance. Depuis plus de quatre décennies, conformément à la loi de Moore[START_REF] Moore | Cramming more components onto integrated circuits[END_REF], le nombre de transistors double tous les deux ans. Comme les transistors fonctionnent plus rapidement, les fréquences plus élevées sont atteintes. Cependant, le scaling traditionnel se confronte aux limitations fondamentales avec la fabrication, la performance et la consommation d'énergétique.

Fig. A. 1 Figure A. 1 :

 11 Fig. A.1 montre que l'écart entre les gains de la performance de grille et le délai d'interconnexion s'élargit avec technologies avancées. Car les fils d'interconnexions ne peuvent pas suivre cette tendance, ils deviennent l'un des principaux goulets d'étranglement

Figure A. 3 :

 3 Figure A.3: Logique programmables vs. ASIC pour de nouvelles conceptions dans les processus primaires. [3]

Figure A. 6 :A. 3 . 1 .Figure A. 8 :Figure A. 9 :Figure A. 10 :

 6318910 Figure A.6: Méthodologie de Création de la Définition de l'Architecture avec les Technologies Emergentes

  Niveaux de Résistance pour le NVFPGA Cette section étudie l'impact des états de résistance de NVE sur le délai et la consommation. Les dispositifs résistifs haut et bas de NVE sont programmés dans un manière complémentaires. Donc, à tout moment l'un d'eux est programmé avec une haute résistance (R OF F ) et l'autre avec une faible (R ON ) résistance. Le R ON de la NVE détermine combien de temps il faut pour charger ou décharger le noeud de configuration des LUTs. Ainsi, la faible résistance R ON , améliore les performances. . Dans le structure NVE pendant le fonctionnement normal, il y a un chemin de courant direct entre les sources d'alimentation. Compte tenu des états complémentaires des résistances, une valeur de résistance de R ON + R OF F se situe entre les sources d'alimentation. Le courant de fuite est, par conséquent;

Figure A. 11 :Figure A. 12 :

 1112 Figure A.11: La consommation totale d'énergie des circuits de référence pour l'intégration FPGA avec SRAM et NVSRAM. Les résultats montrent une augmentation de consommation en moyenne de 2%.

Figure A. 13 :

 13 Figure A.13: La surface totale des circuits de référence pour FPGA SRAM et l'intégration CBRAM. La surface réduite de 5% avec NVLUT et de 33% avec NVFPGA.

Figure A. 14 :FF_STRFigure A. 16 :

 1416 Figure A.14: Le délai du chemin critique des circuits de référence pour les FPGA SRAM et l'intégration CBRAM. Le délai réduit de 24% avec NVLUT et de 34% avec NVFPGA.

Figure A. 17 :A. 3 . 3 . 2 .Figure A. 18 :A. 4 .Figure A. 19 :

 1733218419 Figure A.17: Le délai du chemin critique des circuits de référence pour FPGA avec SRAM, NVSRAM et NVFF. Les résultats montrent une augmentation du délai en moyenne de 6% et 3% dans les implémentations de NVSRAM et NVFF.

Figure A. 20 :A. 4 . 1 .Figure A. 21 :

 204121 Figure A.20: R ON impact sur le chemin critique. Le gain est réduit avec la valeur croissante de la résistance.

Figure A. 22 :Figure A. 23 :

 2223 Figure A.22: Vue conceptuel du potentiel gain et consommation de l'énérgie des implémentations basée de SRAM et de RRAM. En mode d'attente, le circuit avec SRAM consomme de l'énergie de fuite, alors qu'il est possible de réduire la consommation dans le même mode à zéro avec RRAM intégration.

Figure A. 25 :Figure A. 26 :

 2526 Figure A.25: Le gain de puissance en fonction de cycle d'utilisation pour le FPGA à base d'OxRAM avec les applications de sauvegarde de configuration et de contexte. Considérant la durée ON 1%, la consommation gagnée atteint plus de 40% en moyenne.

  Vue couche basse.

Figure A. 27 :Figure A. 28 :

 2728 Figure A.27: MUX4 en 2D et 3D.

Figure A. 29 :

 29 Figure A.29: EDP des circuits de référence FPGA pour 2D et 3D EDP peut être réduite de 47% en moyenne avec les blocs 3D.

Figure A. 30 :A. 4 . 5 .Figure A. 31 :

 304531 Figure A.30: Projection de l'amélioration de la surface pour les futurs noeuds technologiques basées sur l'ITRS 2013 et le gain de multi-niveaux approche 3DMI.

  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.16 R ON impact on FPGA critical path. Gain is reduced with increasing resistance value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.17 R OF F impact on FPGA total power consumption. Power consumption increase with reduced resistance value. . . . . . . . . . . . . . . . . . . 88 4.18 Conceptual view of potential gain and power overhead of SRAM and FPGA tiles. . . . . . . . . . . . . . . . . . . . . . . . . . .

	LIST OF FIGURES	LIST OF FIGURES
	5.7	4.15 Total power consumption of FPGA benchmark circuits for SRAM, 2D and 3D
			NVSRAM and NVFF integration. The results show an increase in
			delay on average by 1.5% in NVSRAM and 0.5% in NVFF implemen-
			. 97
		5.1	Description of the process flow enabling to achieve stable performance
			bottom FET, high quality top substrate, high performance top FET
	4.13 Critical path delay of FPGA benchmark circuits for SRAM, NVSRAM with 600 • C process and 3D contacts realization. . . . . . . . . . . . . . 104
		and NVFF integration. The results show an increase in delay on aver-5.2 Logic-on-Memory approach . . . . . . . . . . . . . . . . . . . . . . . . 105
		age by 6% in NVSRAM and 3% in NVFF implementations. . . . . . . 5.3 Tile block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
	4.14 Total area of FPGA benchmark circuits for SRAM, NVSRAM and 5.4 MUX4 full view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
		5.5	xiv 3D LUT4 design . xv

age by 2%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Total area of FPGA benchmark circuits for SRAM and CBRAM integration. Reduced area values are achieved by 5% with NVLUT and 33% with NVFPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Critical path delay of FPGA benchmark circuits for SRAM and CBRAM integration. Reduced critical path delays are achieved by 24% with NVLUT and 34% with NVFPGA. . . . . . . . . . . . . . . . . . . . . 4.12 Power consumption of FPGA benchmark circuits for SRAM and CBRAM integration. Reduced critical path delays are achieved by 18% with NVLUT and 23% with NVFPGA. . . . . . . . . . . . . . . . . . . . . NVFF integration. The results show an increase in delay on average by 17% in NVSRAM and 1% in NVFF implementations. . . . . . . . . tationsRRAM-based implementations. During standby mode, the circuit with SRAM consumes leakage power, whereas it is possible to reduce consumption in the same mode to zero with RRAM integration. . . . . . 91 4.19 Power gating switch utilization for power down mode. . . . . . . . . . 92 4.20 Operating frequency/area trade-off in power gating application with 22nm FDSOI technology. . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.21 Power gain depending on duty-cycle values for OxRAM-based FPGA with configuration saving applications. Considering 1% ON time, gained power reaches 50% on average. . . . . . . . . . . . . . . . . . . . . . . 95 4.22 Power gain depending on duty-cycle values for CBRAM-based FPGA with configuration saving applications. Considering 1% ON time, gained power reaches 97% on average. . . . . . . . . . . . . . . . . . . . . . . 96 4.23 Power gain depending on duty-cycle values for OxRAM-based FPGA with configuration and context-saving application. Considering 1% ON time, more than 40% power gain can be achieved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.6 3D SP design for SB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 1 . 1 :

 11 Comparison of 3D Integration interconnect size.

		Diameter(µm) Pitch(µm)
	TSV	2 -4	4 -8
	3DMI	0.1	0.2
	3DMI vs. TSV gain	20x -40x	20x -40x

1. INTRODUCTION 2 Background and Motivation Contents 2

  .1. FPGA Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1. Recent History of FPGAs . . . . . . . . . . . . . . . . . . . 13 2.1.2. FPGA Architecture and Hardware Structures . . . . . . . . 14 2.1.3. FPGA Configuration Techniques . . . . . . . . . . . . . . . 24 2.2. FPGA Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.1. FPGA Limitations due to Configuration Memory . . . . . . 26 2.2.2. FPGA Limitations due to Routing Resource . . . . . . . . . 26 2.3. Emerging Technologies . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.1. Advanced Memories . . . . . . . . . . . . . . . . . . . . . . 28 2.3.2. 3D Integration . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.3. FPGA with Emerging Technologies . . . . . . . . . . . . . . 40 2.4. Conclusion and Work Positioning . . . . . . . . . . . . . . . . . . . 42

  2.8, the switch box can make 3 possible connections making F s = 3. Depending on the

	Pass transistor	Tri-state buffer
	routing switch	routing switch
	Logic Block	OutputSConnectionSBlock Fc,out =S1/4 Logic Block	ProgrammableSRouting Switch Logic Block
		Logic		Logic
		Block		Block
	Logic InputSConnection Block Block	Logic Block	Logic Block
	Fc,in =S2/4
	Routing Track
		Logic Block		Logic Block	LongSWire Segment
					ShortSWire
					Segment
	W
		SwitchSBlock	RoutingSTrack
	Figure 2.8: Island-style FPGA detailed routing architecture [7].
	Logic block	Length 1 wire	Length 2 wire	Length 4 wire
		Figure 2.9: Channel segment distribution.

2.2. FPGA Limitations

		35%	Memory
					80%	60%
	Routing
		43%	MUX,
				buffer
	Logic	Logic Memory 14% 8%	20%	40%
		Area		Delay Power
	Figure 2.14: Area, delay and power breakdown of different components in Xilinx Virtex-4
	[8].

Interconnect 34% Configuration SRAM 38% LUTs 16% Other 12% (a) Interconnect 60% Logic 16% Clocking 14% IOBs 10% (b)

2.3.1.1. Spin-Torque Transfer RAM (STT-RAM)

	Although magnetic memories have existed in a large variety since the earliest mag-
	netoresistance based memories with ferromagnetic films [39][40], the development of
	Magnetic Tunnel Junction (MTJ) material with high Tunneling Magneto-Resistance
	(TMR) offered efficient memory integration [41][42]. Typically, an MTJ includes an
	oxide barrier (e.g. MgO) between two ferromagnetic (FM) layers. The relative direc-
	tions of magnetization in FMs determine the MTJ resistance. When the layers are
	magnetized in different directions, i.e. polarization in anti-parallel, the MTJ has high
	resistance and when the layers magnetized in the same directions, i.e. polarization in
	parallel, the MTJ has low resistance. During the write operation, a bit of informa-
	tion is stored using two perpendicular lines to create the necessary magnetization at
	the crosspoint. A large current is required for this operation resulting in large access
	transistor to guarantee enough driving current. Thermally Assisted Switching (TAS)

  Al 2 O 3 , T aO 2 and T iO 2

	terms have been used for devices exhibiting resistive properties by switching
	from high resistive state to low resistive state by flowing a current through the device
	such as RRAM, ReRAM, OxRAM, OxRRAM. The device structure is constructed by a
	simple Metal-Insulator-Metal (MIM) where an oxide material is placed in between two
	metal electrodes as shown in Fig. 2.18. Several materials have been researched which
	exhibit resistive switching behaviors. Most extensively studied metal oxide materials
	include Hf O 2 ,

  CBRAM device switching mechanism for SET and RESET operations.

	+V	-V
	TE(Cu or Ag)	TE(Cu or Ag)
	ions	ions
	conductive	conductive
	filament grows	filament dissolves
	BE	BE
	Figure 2.20:
	, are one of the emerging technologies for Non-Volatile Memories (NVMs). It is a
	two terminal device composed of an active anode and an inert cathode layer where a
	solid electrolyte is embedded in between. CBRAM switching mechanism is based on
	polarity dependent electrochemical deposition and removal of metal in the thin solid
	state electrolyte film. The device switching mechanism is illustrated in Fig. 2.20.
	When a positive voltage is applied to the anode electrode, CBRAM goes into a fast
	program operation where the Ag ions are carried into chalcogenide material as a result
	of a redox reaction. The device is said to be set and a Low Resistance State (LRS) is

achieved due to the stable conductive bridge between the electrodes. In order to reset, (Adapted from

[START_REF] Yu | Compact modeling of conducting-bridge random-access memory (cbram). Electron Devices[END_REF]

.) a reversed voltage is applied, i.e. a positive bias at the cathode electrode. Since the conductive bridge is dissolved, the metal ion concentration is reduced. The electrodes are disconnected and a high resistance state (HRS) is achieved.

Table 2 . 1

 21

		FRAM
		CBRAM STTRAM
	: Comparison of emerging memories	Flash PCM RRAM
		DRAM
		SRAM
		Cell size (F 2

Table 2 . 2 :

 22 3DMI VS TSV VERTICAL CONNECTION COMPARISON

		Alignment(µm) Diameter(µm) Pitch(µm) Minimum depth(µm)
	TSV	0.5 -1	2 -4	4 -8	20 -50
	3DMI	0.01	0.1	0.2	0.1
	3DMI vs. TSV gain	50x -100x	20x -40x	20x -40x	200x -500x

  Due to the reduced footprint of memory cell, FPGAs can benefit highly from RRAM integration. Cong et al. proposed a RRAM-based FPGA where the interconnect MUXs are replaced with RRAM-based cells[START_REF] Cong | Fpga-rpi: A novel fpga architecture with rram-based programmable interconnects. Very Large Scale Integration[END_REF]. Only routing resource is updated with this approach. Results show major improvements in the routing resource with 96% less area, 55% higher performance and 79% lowered power consumption. Even though sig-

, a PCRAM-based Non-Volatile Static Random Access Memory (NVSRAM) is proposed and integrated in the FPGA for multi-context functionality. A low leakage operation is achieved, however area and delay evaluations are not carried out. Recently, a non-volatile look-up table is fabricated with IBM 90nm CMOS technology [100]. nificant improvements are gained, sneak-path effects must be considered as it degrades selectivity. Chen et al. proposed a RRAM-based LUT which uses a crossbar-based design [102]. The LUT4 design grants 24% less area with 26% reduced delay. Sneak-path effects and power consumption including additional circuit are not analyzed. Recently, Liauw et al. fabricated a RRAM-based FPGA in which the SRAM-based configuration memory nodes are replaced with RRAM-based memories [103]. The adoption of RRAM-based memory node reduced the FPGA area by 40% and EDP by 28%.

Table 3 . 1 :

 31 Properties of MCNC 20 largest benchmark suite.

	Benchmark BLEs FFs	I/Os	Type	Operation
	alu4	1592		14/8	Compute-bound Combinational
	apex2	2072		38/3	Compute-bound Combinational
	apex4	1299		9/19	Compute-bound Combinational
	bigkey	2039	224	4/6	IO-bound	Sequential
	clma	8383	33	75/69	Compute-bound	Sequential
	des	2155		29/106	IO-bound	Combinational
	diffeq	1875	305 229/197 Compute-bound	Sequential
	dsip	1619	224	38/304	IO-bound	Sequential
	elliptic	4183	194	41/35	IO-bound	Sequential
	ex1010	4682		256/245 Compute-bound Combinational
	ex5p	1162		64/39	Compute-bound Combinational
	frisc	5869	886 229/197 Compute-bound	Sequential
	misex3	1477		131/114 Compute-bound Combinational
	pdc	5353		10/10	Compute-bound Combinational
	s298	2429	14	8/63	Compute-bound	Sequential
	s38417	8108 1462 20/116 Compute-bound	Sequential
	s38584.1	6920 1260	16/46	IO-bound	Sequential
	seq	1911		14/14	Compute-bound Combinational
	spla	3865		16/40	Compute-bound Combinational
	tseng	1401	385	52/122	IO-bound	Sequential

  .7.

	Emerging Technologies	FPGA Architecture
	Transistor Characterization
	Transistor Capacitances	Min Transistor Area
	Memory Cell Properties
	Cell area	Leakage power
	Block Layouts
	Block dimensions
	Parasitic Extraction
	Segment Resistance & Capacitance	Block I/O Capacitance
	Post Layout Simulation
	Block Delays
	Architecture File

  4.2.1. Evaluation on Applications Requiring Configuration Saving 4.2.2. Evaluation on Applications Requiring Context and Configuration Saving . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2. Normally-OFF Instantly-ON FPGA . . . . . . . . . . . . . 4.4. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In order to support the main benefit of FPGAs which is the reconfigurability, a high number of Configuration Random Access Memory (CRAM) cells is necessary. As discussed in Section 2.1., almost half (43%) [8] of the FPGA area is allocated for CRAM with Static Random Access Memory (SRAM) being the preferred choice. The inclusion of these memories not only increases the total area of the FPGA but also extends the length of routing wires which deteriorates performance and power consumption. Apart from area, these memories also contribute to the leakage power consumption heavily. Power gating can be incorporated for zero leakage but configuration memories lose the configuration information because they are volatile. Flash-based solutions can be integrated but CMOS integration difficulties, cost, and scaling limitations prevent Flash integration for large scale usage. Therefore, compact and non-volatile memories are of quest for area-efficient, high performance, and low power FPGAs. Resistive memory technologies can mitigate the overheads due to configuration memories in FPGAs. A selection of emerging memories is surveyed in Section 2.3.. In this thesis Oxide Random Access Memory (OxRAM) and Conductive Bridge Ran-

4.2.3. Optimization of Resistance States for NVFPGA . . . . . . . 4.3. Normally-OFF Instantly-ON Computing . . . . . . . . . . . . . . . 4.3.1. Power-gating Implementation . . . . . . . . . . . . . . . . .

4

dom Access Memory (CBRAM) are the targeted technologies. These memories offer promising opportunities with inherent non-volatile operation capability and small footprint with CMOS Back-End-of-Line (BEOL) compatibility. Furthermore, with OxRAM high endurance, not only the configuration information but also operation results in the registers can be stored. CBRAM technology offers very high resistance windows which allows to design very compact memories.

Table 4 . 1 :

 41 NVSRAM signal conditions during different operation phases.

Table 4 . 2 :

 42 Area comparison of SRAM and NVSRAM cells

		Normalized area(x min. size transistor area) Area(µm 2 )
	SRAM	11.5	4.10
	NVSRAM	15.25	5.44

Table 4 . 3 :

 43 Power Data for general NVSRAM operation

		P avg (nW)	Duration(ns)	Energy(fJ)
	Reset	425	20	8.5
	Store	434	20	8.7
	Power down	0.06	3800	0.23
	Restore	28	20	0.56
	Energy for general operation including on/off (fJ)	17.9
	Energy for FPGA configuration memory on/off (fJ)	0.78

Table 4 . 4 :

 44 NVSRAM signal conditions during different operation phases.

Table 4 .

 4

		5: Area comparison of FF and NVFF cells
		Normalized area(x min. size transistor area) Area(µm 2 )
	FF	78.2	27.9
	NVFF	99.2	35.4

Table 4 . 6 :

 46 Power data for general NVFF operation

		P avg (nW)	Duration(ns)	Energy(fJ)
	Reset	180	20	3.6
	Store	180	20	3.6
	Power down	0.419	3800	1.6
	Restore	131	20	2.6
	Energy for general operation including on/off (fJ)	11.4

Table 4 .

 4

	7: Area and leakage comparison between 6T SRAM and NVE
	130nm Bulk Cell Area(µm 2 ) Leakage current(pA)
	SRAM	6T	11.28	25
	CBRAM	1T2R	4.00	150

Table 4 . 8 :

 48 Power data for general NVE operation

		P avg (nW)	Duration(ns)	Energy(fJ)
	Reset	1170	500	585
	Store	5670	500	2835
	Power down	900	0.5	0.45
	Restore	1200	0.5	0.6
	Energy for general operation including on/off (pJ)	3.42
	Energy for FPGA configuration memory on/off (fJ)	1.05

Table 4 . 9 :

 49 Resistance state values reported in the literature.

		OxRAM[147] CBRAM[73] PCRAM[148]
	R ON	1kΩ	4.2kΩ	10kΩ
	R OF F	100kΩ	10GΩ	2MΩ
	I leakage	15µA	0.15nA	0.75µA

Table 4 .

 4

	10: Break-Even Times (BET) for OxRAM-based Configuration-Saving Applica-
	tions
	Circuit P OH (mW) P L (µW ) BET (%)
	alu4	0.03	24.97	48.24
	apex2	0.04	37.90	50.64
	apex4	0.11	46.66	30.46
	des	1.12	994.48	47.01
	ex1010	0.04	39.89	47.08
	ex5p	0.04	24.63	36.17
	misex3	0.04	37.12	46.66
	seq	0.05	50.22	48.06
	pdc	0.28	129.26	31.36
	spla	0.29	120.07	29.62
			Avg.	42.26

previously designed NVFPGAs are analyzed in Normally-off Instantly-on computing based on the requirement of application activities for increased power gain.

Table 4 .

 4

	11: Break-Even Times (BET) for OxRAM-based Configuration and Context-
	Saving Applications
	Circuit P OH (mW) P L (µW ) BET (%)
	bigkey	0.96	721.30	42.95
	clma	0.55	181.96	24.92
	diffeq	0.09	21.93	19.28
	dsip	0.99	727.92	42.26
	elliptic	0.02	10.81	38.71
	frisc	0.16	117.57	43.04
	s298	0.01	3.47	24.66
	s38417	0.13	109.74	45.14
	s38584.1	0.34	325.27	48.89
	tseng	0.09	95.02	52.69
			Avg.	38.25

Table 5 . 1

 51

		: MUX4 Performance
	MUX4	Area(µm 2 ) Delay(ps) Power(µW )
	2D	1.18	28.48	2.75
	3D	0.57	24.35	2.39
	3D vs. 2D gain(%)	51	14	12

Table 5 . 2

 52

		: LUT4 Performance
	LUT4	Area(µm 2 ) Delay(ps) Power(µW )
	2D	7.93	60.17	7.10
	3D	3.47	60.98	7.37
	3D vs. 2D gain(%)	56	-1.3	-3.8

Table 5 .

 5

	3: Connection Block Performance
	CB	Area(µm 2 ) Delay(ps) Power(µW )
	2D	61.8	98.4	7.2
	3D	37.1	92.6	6.9
	3D vs. 2D gain(%)	40	5.9	4.6

Table 5 .4: Switch

 5

			Box Performance
	SB	Area(µm 2 ) Delay(ps) Power(µW )
	2D	79.3	30.6	2.8
	3D	65.3	26.7	2.7
	3D vs. 2D gain(%)	55	12	5.3
	Table

Table 5 .

 5

		5: Tile Performance
	Tile	Area(µm 2 ) Delay(ps) Power(µW )
	2D	287.8	240.3	19.9
	3D	151.6	225.4	19.4
	3D vs. 2D gain(%)	47	6.2	2.4

Table 5 .6: 3DFPGA Architecture parameter

 5

	Parameter	Description	Value
	K	Number of inputs per LUT	4
	N	Cluster size (BLEs per LB)	4
	I	Inputs per LB	10
	F C,in	CB input flexibility	1
	F C,out	CB output flexibility	1
	F S	SB flexibility	3
	W	Channel width	32
	L	Segment length	1

Table 5 . 7 :

 57 Area and EDP results of FPGA benchmark circuits based on multi-tier design Projection of area improvement for future technology nodes based on ITRS roadmap and gain from multi-tier 3DMI approach.

	to 2D (avg.)	Normalized	seq	misex3	ex5p	ex1010	des	apex4	apex2	alu4
	100 45.4 48.6 30.4 30.7 23.1 24.3 100 53 74.3 65 59.6 34.8 52.4	7.3 3.3 3.6 2.2 2.3 1.7 1.8 170.5 69.7 135.1 111.9 101.4 51 90.4	4.7 2.1 2.3 1.4 1.4 1.1 1.1 87.4 38.6 58.9 52.1 46.2 28.3 40.5	3.6 1.6 1.8 1.1 1.1 0.8 0.9 38.4 20.7 29.2 25.9 25.5 15.1 21.6	8.1 3.7 3.9 2.5 2.5 1.9 2 49.5 36.1 46.7 39.7 40.2 19.2 30.5	32 14.6 15.6 9.8 9.9 7.4 7.8 427.5 240.1 334.8 307 272.3 162.1 259.8	6 2.7 2.9 1.8 1.8 1.4 1.4 129.9 50.5 64.6 53.1 48.4 27.9 43.5	6.6 3 3.2 2 2 1.5 1.6 143 67.2 91.2 83.9 71.2 47.6 64.5	5.3 2.4 2.6 1.6 1.6 1.2 1.3 78.6 55.1 67 60 54.1 32.2 49	2D 2L_1 2L_2 3L_1 3L_2 4L_1 4L_2 2D 2L_1 2L_2 3L_1 3L_2 4L_1 4L_2	Area (mm 2 ) EDP (pJ*ns)

  Projection of EDP improvement for future technology nodes based on ITRS roadmap and gain from multi-tier 3DMI approach.

	5. 3D-FPGA WITH MONOLITHIC INTEGRATION
	1 1.1	2D 14nm	Normalized EDP	3DMI ITRS
	0.9
	0.8
			10nm
	0.7			Intermediate
	0.6		24%	6%
	0.5	2L	7%	3L	7nm
	0.4			29%
					4L
	0.3
	Figure 5.16:
			5.16 that the extrapolated 2D FPGA in 7nm node and
	the 2L 3D FPGA demonstrate similar EDP gains with only 7% difference. Considering

  Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.2. Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.2.1. Towards 3DNVFPGA: Merging RRAM and 3D Integration 129 6.2.2. Thermal impacts of FPGA designs with 3DMI . . . . . . . 130 6.2.3. Reliable designs with SiNWFETs . . . . . . . . . . . . . . . 130

	6
	Conclusion & Perspectives
	The designed FPGA blocks are, then, utilized considering several partitioning schemes
	for evaluation of 3D FPGAs up to 4 active layers. The 3D FPGA with 4 layers presents
	significant improvements in terms of area (77%) and EDP (66%) in comparison to the Contents
	2D counterpart. 6.1.
	The results show that each stacked active layer with 3DMI improves logic density
	and EDP. When compared to the extrapolated results of 14nm 2D FPGA into 10nm
	and 7nm nodes based on ITRS figures, stacking layers with 3DMI in 14nm outperforms
	the expected scaling improvements. Namely, adding more active layers while keeping
	the same technology can be an alternative to the traditional scaling. The results from
	this chapter are published in [170][171][172][173][174][175].

Table 6 .

 6 1 summarizes the gains accomplished with different 3D technologies. The depicted results are expressed in comparison to the conventional FPGA implementation in the corresponding technology node. Area and Energy-Delay Product (EDP) are chosen as the global comparison metrics. Area refers to the silicon footprint of the implementation. EDP refers to both performance and energy efficiencies as it can be interpreted as improved performance in the same energy level or improved energy considering the same operating frequency.Circuit footprint can be significantly reduced with 3D technologies mainly because some of the circuit functionality can be integrated in the third dimension. In the FPGA, almost half of the chip area is dedicated for the configuration nodes which is one of the main limitations of the FPGA. With Resistive RAM(RRAM)-based integration, resistive devices can be fabricated between metal layers and only the control transistors consume silicon area. The CBRAM-based compact memory cell achieves 33% less area when it replaces the SRAM cells in an FPGA. Highest area gains can be achieved with 3DMI taking advantage of very compact inter-level via contacts. Considering a logicon-memory partitioning in 2 tiers, area can be reduced by 55%. With integration of more layers, the area can be reduced by 77% for the case of four layers.

	Since FPGA fabric is also dominated by routing resource, the reduction in area leads
	to reduced wirelength. This enables reduction in routing capacitance which significantly
	improves circuit performance and power consumption. CBRAM-based FPGA improves
	the EDP by 66%. With 3DMI, 2-tier integration reduces the EDP by 47% and 4-tier
	achieves 66% better EDP. Even though more area gain is achieved with 3DMI, the
	EDP is improved less compared CBRAM-based implementation. One reason could be
	the inter-tier via capacitance overhead in LUTs in 3DMI which affects performance and
	power consumption.
	One of the major benefits of RRAM integration is the non-volatility. This prop-
	erty enables saving configuration bitstream and context results in the registers. Thus,
	external Flash memories become redundant. Moreover, with non-volatility, FPGAs
	can target Normally-off Instantly-on applications which can save significant power con-
	sumption. Depending on the application activity, OxRAM-based implementation re-
	duces the EDP by 42% for configuration saving applications and 32% for configuration
	and context saving applications. CBRAM-based FPGA, on the other hand, achieves

Table A .

 A

	10 nm*				10 nm*
	14 nm*				14 nm*
	20 nm	TippingEPointEOccuredEinE1**8 whenEPLDsEMovedEtoE4*Enm	PrimaryEPLD	20 nm
				ProcessENode
	32 nm 28 nm	andEb4ENodesEaheadEofEASICs		28 nm 32 nm
	45 nm 40 nm	GapEBeganEtoEEmerge inE1**5EwhenEPLDs			40 nm 45 nm
				Widening
		MovedEtoE9*Enm
	65 nm			TechnologyEGap	65 nm
	90 nm				90 nm
	130 nm				130 nm
				PrimaryEASIC
				ProcessENode	180 nm
	2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013	2014 and Beyond
	Source:EAltera;EDataEappliesEtoEnewEdesignEstartsf
	8EFinFETETechnologyfETimeframeEforEPLDsEonEF4EnmEandEF*EnmEFinFETEtechnologyEtoEbeEannouncedf
		1: Comparaison de la taille de l'interconnect 3D
			Diamètre(µm) Emplacement(µm)
	TSV	2 -4	4 -8
	3DMI	0.1	0.2
	Gain 3DMI vs. TSV	20x -40x	20x -40x

2. Evaluation du FPGA avec les Technologies Emer- gentes

  Dans le section A.3., les conceptions FPGA plus efficaces sont démontrées en utilisant des mémoires avancées. Premièrement, la motivation pour les FPGA avec des mémoires avancées s'explique. Les nouveaux domaines d'applications sont proposées comme l'application de sauvegarde de configuration et de contexte. La modification nécessaire pour NVFPGA avec des circuits utilisant des technologies OxRAM et CBRAM est expliqué. Un nouveau système de calcul avec la propriété basse consommation est présenté. Les implications de mémoire avancée au niveau du système sont déterminées pour chaque technologie dans la dernière section. Dans le section A.4., la conception de 3D-FPGA avec l'intégration monolithique est proposée. Logic-sur-Mémoire approche est présentée et les blocs conçus avec cette approche sont évalués en utilisant de plateforme VPR. La concept de multi-niveaux FPGA est discutée et les FPGA à partir de deux jusqu'à quatre couches sont évalués.Enfin, les résultats du FPGA multi-niveaux sont comparés aux attentes de scaling traditionnel.

A.

Par rapport à l'ASIC, les FPGA bénéficient des technologies plus avancées. Losqu'un réel FPGA industriel est conçu, les concepteurs de circuits passeront mois pour ajuster soigneusement les aspects de la conception de circuits pour cibler la nouvelle technologie. Surtout, lorsque les technologies émergentes sont ciblés, il est impossible d'explorer toutes les possibilités de la conception, d'optimiser avec ces technologies et de mesurer les indicateurs de performance des circuits FPGA fabriqués. Par conséquent, un environnement d'évaluation du FPGA rapide, fiable et flexible est indispensable .

A.2.1.

Cadre d'Evaluation du FPGA Expérimentale

	Le processus expérimental utilisé dans le cadre basé de VPR est illustré à la Fig. A.4.
	Tous les outils inclus sont open-source qui permettent l'évaluation sur des différentes
	architectures.
	Le toolflow prend un circuit de référence et une définition de l'architecture du FPGA

pour implémenter la fonctionnalité et évaluer sur l'FPGA. ODIN est utilisé comme outil de synthèse frontal pour convertir la description de haut niveau (ex. VHDL) à une A.2.

2. Méthodologie pour l'Evaluation des Technologies Emergentes

	Emerging Technologies	FPGA Architecture
	Même si, la structure du FPGA est une unité fonctionnelle simple, plusieurs choix de
	conception peuvent être imposées dans le développement architectural. Surtout, lorsque
	Benchmark les nouvelles technologies sont employées, une modélisation précise de ces paramètres Block Layout Design Circuits and Extraction
	architecturaux et technologiques est crucial. Il est prévu que plusieurs essais doivent
	être exécutées de manière itérative pour optimiser l'architecture. Par conséquent, une
	plateforme d'exploration est nécessaire qui est rapide et flexible. VPR5 with Power Architecture Estimation Flow Definition
		Area	Speed	Power
	Afin d'accomplir une conception FPGA, une bibliothèque de cellules partielle est
	suffisante car des blocs élémentaire du FPGA ne sont pas complexes et la conception du
	FPGA totale peut être accomplie avec quelques cellules. Toutefois, selon la technologie
	ciblée, nouveaux outils pourraient être inclus dans le cadre de CAO automatisé, ex. un
	outil de placement et de routage en 3D. Dans cette thèse, une méthodologie d'évaluation
	du FPGA pour les technologies émergentes est proposée (Fig. A.5). Selon la maturité
	de la technologie, les cellules sont conçues et caractérisés soit au niveau de l'appareil
	ou bloc. Avec cette caractérisation, la définition de l'architecture du FPGA est créée

A.2.2.1. Plateforme d'Evaluation du FPGA Pour adopter des nouvelles technologies, l'approche de conception classique n'est pas suffisant. En général, une bibliothèque de cellules standards est construite et ensuite vérifiée pour la conception de la logique. Ces cellules offrent divers capacités de conduite et d'autres propriétés telles que faible puissance ou haute performance. Les cellules sont ensuite utilisés dans un outil de placement et de routage automatisé. Cette approche est optimisée pour les technologies de pointe où les outils et les bibliothèques sont assez matures pour les conceptions fiables. Cependant, lors de la conception avec des technologies émergentes, ce niveau de maturité ne peut pas être atteint pour l'exploration de la conception. et utilisée comme une entrée à la CAO basée de VPR afin d'évaluer la performance, la surface, et la puissance.

Figure A.5: Plateforme de l'exploration du FPGA pour les technologies émergentes.

A.

2.2.2. Développement de la Définition Architecture pour des Technolo- gies Emergentes

  Les FPGA sont conçus à base de tuiles et une tuile est construite avec un bloc logique (LB), deux boîtes de connexion (CB), et une boîte de commutation (SB).

	Emerging Technologies	FPGA Architecture
	Transistor Characterization
	Transistor Capacitances	Min Transistor Area
	Memory Cell Properties
	Cell area	Leakage power
	Block Layouts
	Block dimensions
	Parasitic Extraction
	Segment Resistance & Capacitance	Block I/O Capacitance
	Post Layout Simulation
	Block Delays
	Architecture File
	Ces blocs de base sont établis avec des mémoires de configuration, les multiplexeurs, et
	des buffers. Par conséquent, une fois que ces blocs élémentaires sont conçus en layout
	et inclus dans la bibliothèque de conception, tous les blocs du FPGA liés peuvent être
	conçues rapidement. Le processus de conception est, donc, considérablement simplifié
	car quelques blocs doivent être conçus sur la disposition plutôt que de l'ensemble du
	FPGA.

En utilisant du cadre d'évaluation FPGA, les impacts de LUT, la taille de cluster, ou SB topologie peuvent être observés rapidement. Dans ces cas, l'architecture du FPGA est évaluée sur la base d'hypothèses paramétrées où les parasites de circuit ne peuvent pas être examinés efficacement. Ainsi, la méthodologie de la Fig. A.6 est proposée pour le développement de la définition de l'architecture avec les technologies émergentes. Dans cette méthodologie, la définition de l'architecture est construite en utilisant des blocs FPGA. Après le layout se termine, les paramètres concernant la conception et la technologie sont extraites pour le développement de définition de l'architecture. Premièrement, les

  Le ratio donné par l'équation Eqn. A.3 définit le minimum de t 1 en termes de t 0 lorsque les frais généraux de l'énergie sont en équilibre avec l'énergie de fuite gagnée.Il est possible de relier ce ratio au cycle d'utilisation, qui est défini comme le rapport de la durée ON à la période totale. Plus précisément, dans une application on / off, le temps de rentabilité (BET) indique le cycle d'utilisation lorsque la surcharge de l'énergie est égale à l'énergie de fuite. Dans cette application, BET est calculé sur la base de l'équation suivante:

	Critical path delay (ns)
	SRAM	NVSRAM(+6%)	NVFF(+3%)
	18
	16
	14
	12
	10
	8
	6
	4
	2
	0
		0				t+t 0 +t 1
		P 2 -P 1 dt =	P L dt	(A.2)
	t					t+t 0
			t 1 t 0	=	P 2 -P 1 P L	(A.3)
	BET =	t 0 t 0 + t 1	=	1 +	1 P 2 -P 1 P L	(A.4)

Table A . 2 :

 A2 Area and EDP results of FPGA benchmark circuits based on multi-tier design

	1.2 0.8 1 to 2D (avg.)	Normalized	ex5p 14nm misex3 2D seq	ex1010	des	alu4 Normalized Area apex2 10nm apex4	ITRS 3DMI
	0 0.2 0.4 0.6	74.3 65 59.6 34.8 52.4 53 48.6 30.4 30.7 23.1 24.3 100 100 45.4	135.1 111.9 101.4 51 90.4 3.6 2.2 2.3 1.7 1.8 170.5 69.7 7.3 3.3	58.9 52.1 46.2 28.3 40.5 2.3 1.4 1.4 1.1 1.1 87.4 38.6 4.7 2.1	29.2 25.9 25.5 15.1 21.6 1.8 1.1 1.1 0.8 0.9 38.4 20.7 3.6 1.6	46.7 39.7 40.2 19.2 30.5 3.9 2.5 2.5 1.9 2 49.5 36.1 8.1 3.7	64.6 53.1 48.4 27.9 43.5 2.9 1.8 1.8 1.4 1.4 129.9 50.5 6 2.7 14% 334.8 307 272.3 162.1 259.8 15.6 9.8 9.9 7.4 7.8 427.5 240.1 32 14.6	67 60 54.1 32.2 49 2.6 1.6 1.6 1.2 1.3 78.6 55.1 5.3 2.4 27% 91.2 83.9 71.2 47.6 64.5 3.2 2 2 1.5 1.6 143 67.2 6.6 3 2L	2L_1 2L_2 3L_1 3L_2 4L_1 4L_2 2D 2L_1 2L_2 3L_1 3L_2 4L_1 4L_2 2D	Area (mm 2 ) EDP (pJ*ns) 40% 3L	Intermediate 41%	4L 7nm

Acknowledgments

enthusiasm in 3D Monolithic Integration, Maud Vinet for directing the research effort in 3D Technologies, Olivier Rozeau for his help on transistor modeling, Olivier Billoint

List of Publications

A.3. FPGA Non-Volatile avec Mémoires Resistives

Le principal avantage des FPGA est la reconfiguration, pour cela un nombre élevé des cellules de mémoire de configuration à accès aléatoire (CRAM) est nécessaire. Près de la moitié (43%) [START_REF] Mingjie Lin | Performance benefits of monolithically stacked 3-d fpga. Computer-Aided Design of Integrated Circuits and Systems[END_REF] de la surface d'un circuit est dédiée aux CRAM, parmi les différentes mémoires existantes, les mémoires SRAM restent la solution préféré. L'intégration de ces mémoires augmente non seulement la surface totale du FPGA, mais aussi la longueur des fils de routage qui détériore les performances et la consommation énergétique. En plus de la surface, ces mémoires impactent les courants de fuites de manière importante. La technique de power gating peut être implémentée pour éliminer les courants de fuites mais les mémoires de configuration perdent les informations de configuration car les mémoires sont volatiles. Les solutions à base de mémoire flash peuvent être intégrées mais les difficultés d'intégration CMOS (le coût et les limites de scaling) empêchent l'intégration de flash pour une utilisation à grande

A.3.3.1. Relation entre Consommation et Cycle d'Utilisation

Dans une application où le FPGA non-volatile est mis en mode veille, la puissance de fuite, qui est normalement dissipée, sera conservée. Cependant, il faut prendre en compte de l'impact de l'intégration de RRAM sur la consommation. Dans la Fig.

A

A.4.4. évaluation de 3D-FPGA Multi-Niveaux

Les fichiers d'architecture VPR distincts sont créés pour chaque manière de partitionnement. Afin d'observer les effets réelles de chaque manière de partitionnement, la longueur des fils de routage et la charge capacitive des fils sont modélisées à partir des améliorations de la surface. Le tableau A.2 montre les résultats des évaluations de circuits FPGA de référence envisagent plusieurs niveaux avec 3DMI. Les valeurs moyennes de tous les systèmes finaux sont normalisées à l'aide des valeurs moyennes du 2D pour pouvoir comparer.

Á partir de deux couches, par rapport au 2D, des améliorations de la surface significatives sont observées lorsque le nombre de niveaux est augmenté. La surface est réduite jusqu'à 55%, 69% et 77% par rapport au 2D pour les implémentations de niveaux 2, 3, et 4 respectivement.

Les résultats de l'EDP montrent que la réduction de la surface permet d'améliorer sensiblement l' EDP. Selon les résultats, deux différents types d'améliorations sont observées : 1) les réductions dues à la longueur plus courte de fils de routage et à la charge capacitive moins élevée 2) les réductions du délai interne de la grille et de la charge capacitive dues à l'approche logique-sur-mémoire. Lorsque deux couches sont considérées, l'EDP peut être réduite de 47% et 26% par rapport au 2D. Dans les solutions de trois et quatre couches, il est possible d'observer l'effet de la simplification de routage. Dans trois couches, jusqu'à 40% de réduction d'EDP est observée et dans quatre couches, jusqu'à 66% par rapport au 2D. Ces résultats montrent que l'amélioration de délai est proportionnelle à la réduction de routage néanmoins, la reconception de blocs peut encore améliorer l'EDP (ex. l'approche logique-sur-mémoire).