Christophe Huriaux
email: christophe.huriaux@irisa.fr

Olivier Sentieys
email: olivier.sentieys@inria.fr

Russell Tessier
email: tessier@umass.edu

FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams

Keywords: Partial reconfiguration, FPGA, heterogeneous fixed-function blocks

The use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this paper we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty.

I. INTRODUCTION

Almost since the creation of the first SRAM-based FPGAs there has been a desire to explore the benefits of partially reconfiguring a portion of an FPGA at run-time while the remainder of design functionality continues to operate uninterrupted. Recent advances in FPGA technology have fueled increased interest in the area from an application standpoint. Dynamic FPGA reconfiguration has been used successfully in applications such as communication coding [START_REF] Atieno | An adaptive Reed-Solomon errors-and-erasures decoder[END_REF], image processing [START_REF] Sedcole | Runtime integration of reconfigurable video processing systems[END_REF], and networking [START_REF] Unnikrishnan | Reconfigurable data planes for scalable network virtualization[END_REF], among others. In most cases, dynamic reconfiguration plays an important role in enhancing application performance, although reduced power consumption and increased fault tolerance are additional motivations.

Contemporary FPGA devices provide hardware interfaces which allow for portions of an FPGA to be modified at run-time without affecting the operation of unmodified areas. Although numerous papers have been written which examine region packing [START_REF] Unnikrishnan | Reconfigurable data planes for scalable network virtualization[END_REF], software scheduling [START_REF] Compton | Configuration relocation and defragmentation for run-time reconfigurable computing[END_REF], and bitstream writing techniques [START_REF] Mignolet | Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip[END_REF] to facilitate partial reconfiguration, the approach is still used by designers on a limited basis.

Currently, the use of partial reconfiguration imposes limitations on the FPGA design: partially-reconfigurable regions must be constrained to a certain size and, in many cases, region bitstreams must be precompiled before application execution. In cases where a partial bitstream is translated from one region to another, the resources in both source and destination regions must match in terms of both functionality and the location of the resources (e.g. logic, fixed-function blocks) in the region.

In this paper, we develop an FPGA architecture which allows for easy translation of partial bitstreams (also called tasks) across partially-reconfigurable regions even if the relative placement of fixed-function blocks within the region is changed. This flexibility comes at the cost of isolating the routing resources from the fixed-function blocks. Our approach can be applied without the need for storage of numerous bitstreams for the same task or for the use of place-and-route tools when a task is moved from location to location.

Although our idea could be used for any island-style FPGA, the work presented in this paper has been specifically conducted in the context of the the European FP7 project FlexTiles [START_REF] Lemonnier | Towards future adaptive multiprocessor systems-on-chip: an innovative approach for flexible architectures[END_REF], in which a dynamically reconfigurable logic fabric in a many-core architecture is used to accelerate specific functions. For this project, an architecture has been developed in which inputs and outputs in the fabric are made through dedicated fixed-function blocks inside the fabric, rather than I/Os spread in a ring around the fabric. This increases the importance of the free movement of tasks across partially-reconfigurable regions. As a result, it is necessary to translate tasks flexibly to locations on the fabric where the relative placement of fixed-function blocks (e.g. memory blocks, multipliers, I/Os) in the region is different.

The remainder of the paper is structured as follows. Section II presents previous work exploring the concept of partial reconfiguration including the relocation of tasks. In Section III, we present FPGA architectural enhancements which allow for the relocation of tasks with fixed-function blocks. In Section IV, our experimental methodology using a modified version of VPR 6.0 [START_REF] Rose | The VTR project: architecture and CAD for FPGAs from Verilog to routing[END_REF] is described. Experimental results are presented in Section V to quantify the area and performance overhead of the approach. Section VI concludes the paper and offers directions for future work.

II. RELATED WORK

The use of partial dynamic reconfiguration in FPGAs has been studied for over twenty years. Although early analysis primarily targeted Xilinx XC6200 series FPGAs [START_REF] Brebner | A virtual hardware operating system for the Xilinx XC6200[END_REF], almost all recent work in the area has focused on Xilinx Virtex families and Altera Stratix V devices, which allow for partial reconfiguration of device regions. Most recent software systems in the area require the precompilation of task bitstreams [START_REF]Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs[END_REF] [START_REF]Partial Reconfiguration User Guide[END_REF] that are assigned to partially-reconfigurable regions (PRR). Occupancy in these locations can be managed by scheduling and region packing software [START_REF] Compton | Configuration relocation and defragmentation for run-time reconfigurable computing[END_REF].

In many cases it is desirable to place and route a task targeted to a PRR once and then to migrate the task to multiple locations on the FPGA die as needed. Often some routing is still needed to connect the newly placed region with surrounding interconnect. In Mignolet, et al [START_REF] Mignolet | Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip[END_REF], a fast router is used to connect a task to surrounding blocks. In Flynn, et al. [START_REF] Flynn | Bitstream relocation with local clock domains for partially reconfigurable FPGAs[END_REF], the routing of clock signals to the region is performed. If additional routing is performed during the merge, the migration of a task to a new PRR can be as long as 97 seconds [START_REF] Silva | Creation of partial FPGA configurations at run-time[END_REF], a prohibitive time for most applications.

PRRs are connected to static regions in recent Xilinx and Altera devices using lookup tables as an interface [START_REF]Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs[END_REF] [START_REF]Partial Reconfiguration User Guide[END_REF]. Older partial reconfiguration approaches overcome the inter-PRR communication issue by using a standard bus interface for communications between the PRR and the remainder of the circuit. Both Carver, et al. [START_REF] Carver | Relocation of FPGA partial configuration bit-streams for soft-core microprocessors[END_REF] and Tan and DeMara [START_REF] Tan | A multilayer framework supporting autonomous run-time partial reconfiguration[END_REF] use bus macros at fixed locations to allow a task to be located at a variety of positions within an FPGA. In some cases for the Virtex architecture, it is necessary to make bitstream modifications to the stored task (such as a new CRC) if it is moved to a different on-chip location, even if the logic resources in the original and destination locations exactly match. Touiza, et al. [START_REF] Touiza | A novel methodology for accelerating bitstream relocation in partially reconfigurable systems[END_REF] provide a high-throughput method for moving a task from one region to another with a single bitstream by calculating most of the needed changes offline.

Two previous partial FPGA reconfiguration schemes directly address the issue of migrating a task which contains fixed-function blocks. Krasteva, et al. [START_REF] Krasteva | Virtex II FPGA bitstream manipulation: Application to reconfiguration control systems[END_REF] examine techniques which move a task with fixed-function blocks to a new region where the blocks are in the same relative position in the region. To date, the only work which examines moving a task with fixed-function blocks to a new location where the blocks are not in the same position is Becker, et al. [START_REF] Becker | Enhancing relocatability of partial bitstreams for run-time reconfiguration[END_REF]. In this case, the blocks are not used, eliminating their need for migration. Unfortunately, given the diversity and abundance of fixedfunction blocks in contemporary FPGAs, simply ignoring and not using them is not a viable option for PRRs.

III. TASK MIGRATION WITH HETEROGENEOUS BLOCKS

In this paper we describe FPGA routing architecture changes which allow tasks to be migrated so that fixed-function (hard) blocks are located in different locations within the target PRR. The approach does not require time-consuming placeand-route during the migration process. Since fixed-function blocks generally are aligned in vertical columns in contemporary FPGAs, we provide the ability for tasks to "float" horizontally within the logic array. The main contributions of this paper are:

• FPGA routing architecture enhancements which allow for routing connections to fixed-function blocks which are isolated from other routing in the FPGA routing fabric.

S src S new T 1

Fig. 1: Relocation problem in modern FPGAs: task T 1 , placed on a set S src of resources, is only movable to another set S new with resource positions matching those in the original set

• An evaluation of the performance and area overheads incurred by this routing isolation for a collection of benchmark designs which include components mapped to both FPGA logic and fixed-function resources.

A. Background

To promote direct comparisons with contemporary FPGAs, we modify the well-known island-style FPGA model [START_REF] Betz | Architecture and CAD for Deep-Submicron FPGAS[END_REF]. This architectural model (Figure 1) includes a two-dimensional array of logic blocks (LB) shown in grey squares that are interconnected via a programmable routing network. Our modeled LBs include a single four-input lookup table (LUT) and a flip flop (FF), although clusters of LUTs and FFs could also be used. The programmable routing consists of horizontal and vertical channels made of multiple wire segments. The channel segments can be connected to inputs and outputs of the LBs through connection boxes (CB). The channels are also connected to each other via switch boxes (SB). To optimize area and performance, modern FPGAs contain a spectrum of fixed-function blocks (shown as rectangles in Figure 1). These hardware resources reduce the demand for logic blocks for common functions, such as multiplication and bulk memory.

In an island-style FPGA, fixed-function blocks such as block RAMs and signal processing blocks (DSP blocks) are aligned in columns to simplify FPGA layout and the combining of multiple blocks into larger functional resources. Depending on block complexity, the height of a fixed-function block is often larger than a single grid location (e.g. the height of a logic block), as shown in Figure 1.

The allocation of fixed-function blocks across the logic fabric complicates task relocation for the shaded task which spans three columns in Figure 1. Given a hardware task placed at the position (x source ; y source ) in the array, it is limiting to find a position (x new ; y new ) in the logic fabric that contain a set of resources S new with all resources in exactly the same relative position as S source . Overcoming the restrictions imposed by fixed-function resources requires making the routing connections to the fixed-function blocks more flexible.

B. Fixed-function blocks abstraction

Increased routing flexibility for fixed-function blocks is introduced via an abstracted view of heterogeneous resources. Starting from the original architecture illustrated in Figure 2a, two separate logic resource layers are considered. The first layer, the logic array, includes the logic resources (LBs) of the architecture and its routing network, connection boxes and switch boxes. The second is made up of the fixedfunction blocks in the baseline logic array (e.g. memory blocks, DSP blocks, communication interfaces, etc.). The heterogeneous plane has its own routing network, composed of bidirectional routing long lines which span a defined region of the FPGA. Each of these lines can be connected to an input or output of the fixed function blocks. The fixed-function block input and output connections are restricted to their dedicated routing network. Links to the logic array are made via the heterogeneous-only long lines which connect to switch boxes of the logic array routing network. The extent of each of the long lines is optimized to provide good delay performance. The abstraction is presented in Figure 2b. It should be noted that this abstraction does lead to an increase in horizontal delay for routing in the logic-only (homogeneous) plane. Since the positioning on the die of fixed-function blocks is not known at place and route time, it must be assumed that such a block is physically located horizontally between each LB. The additional delay associated with the longer horizontal wires in the homogeneous plane must then be considered. emanating from logic blocks. Heterogeneous-only long lines are connected to the homogeneous routing network through switch boxes at horizontal and vertical channel intersections, as shown in Figure 3. Routing segments spanning multiple LBs (e.g. 2, 4, 8, etc) are commonly found in island-style architectures. These segments do not make intermediate switch box connections to reduce wire delay. However, the heterogeneousonly long lines do connect to multiple adjacent switch boxes. Thus, it is possible to connect to these lines from multiple switch boxes. This additional level of routing allows for the ability to slide a given task horizontally along the horizontal heterogeneous-only long lines without affecting either layer of routing, as illustrated in Figure 4. Only the use of horizontal, heterogeneous-only long lines for fixed-function input and output signals was explored to avoid complex routing and excessive overhead for the overall circuit.

2) Partitioning: Since the size of fixed-function blocks can vary, the vertical and horizontal extent in LBs of a reconfigurable partition must be carefully selected. The width of the partition is bounded by the length of the heterogeneousonly long lines. The height of a partition is defined as the least common multiple of the height of the fixed-function blocks it contains. In this work, the FPGA partitions are identical in size and they are evenly distributed. The partitioning also improves

C 3 (3, 1, t 2 ) C 2 (5, 2, t 2 ) C 1 (2, 3, t 1 )
C 0 (4, 4, t 1 ) Fig. 5: Task model: each connection C i has to be linked to a fixed-function block via heterogeneous-only routing the scalability of our approach: partitions can be duplicated to extend the size of the logic fabric.

3) Task model: In the context of this paper, we consider a hardware task to be a set of logic resources that are interconnected. A hardware task is described by a bitstream to be loaded into the configurable logic fabric. Unlike standard FPGA development where a hardware task contains an IP block that is loaded into the FPGA at a specific location, in this case a task is an aggregate of both interconnected homogeneous logic resources and a set of connections to heterogeneous-only long lines, as depicted by Figure 5. Each connection is characterized by its position (x, y) within the task and its type t is used to determine its resource connection. This set of connections is fixed, relative to the task itself, and the problem of relocation requires finding a corresponding match of fixed-function resources to this set. A task is defined as T = {C i (x i , y i , t i )}, where x i , y i is the position of the connection and t i is its type.

IV. EXPERIMENTAL METHODOLOGY

To experimentally evaluate the impact of our revised FPGA architecture on FPGA area and performance, the Versatile Place and Route (VPR) tool set (version 6.0) was modified. The following subsection details changes made to VPR for experimentation. In subsection IV-B, we describe the set of benchmark designs used for our experiments.

A. Modeling in VPR

The changes made to the VPR source code were made on the latest version 1 available in the Verilog To Routing (VTR) [START_REF] Rose | The VTR project: architecture and CAD for FPGAs from Verilog to routing[END_REF] project repository.

1) Architecture:

The VPR architecture description XML file that was used to model our circuit is based on k4_N10_memSize16384_memData8.xml, which is one of the default files shipped with the VTR tool flow. The file defines a simplified version of the Stratix IV architecture. The architecture was adapted to suit our needs and to provide a generic FPGA supporting multiple types of fixed-function blocks. The blocks include a 36 × 36 multiplier and a configurable dual-port RAM similar to a Stratix 144 Kbit embedded memory block. Figure 6 demonstrate two placements of the 1 The checked out version was revision 3034.

2) Routing abstraction:

The key modifications to the VPR code base resulted in a dual-layer routing graph which allows inter-layer routing connections at switch boxes (Figure 3).

The segment types of the separated routing networks were modeled using two different segment type definitions in the architecture file. The first segment type, used for homogeneous routing, contains wires which span a single logic block. The second segment, used for heterogeneous-only routing, contains long lines spanning the whole chip. Since we restrict the routing to the fixed-function blocks to horizontal wires, the vertical routing adjacent to the fixed-function blocks is not used. In many VPR architecture definitions, a logic array block will be defined to have its inputs and outputs spread across its four sides. This behavior is undesirable in our case since inputs and outputs on left-hand and right-hand sides of the block will connect to vertical routing channels. As a result, we defined the location of input and output signals for fixed-function blocks as the top and bottom of the block.

Since VPR does not provide support for separate routing networks which are only interconnected in a few locations, modifications were made to the VPR routing graph generator. Source code was modified to enable the marking of segments of the architecture file segmentlist with an additional attribute, selective_routing. This attribute tags the segment as appropriate for either homogeneous signals (i.e. to or from a LB), heterogeneous-only signals (to or from a fixed-function block), or both types. Our model only uses heterogeneous-only long lines and segments which can carry both signal types. Additionally, the graph building procedures were adapted so that input and outputs of the complex blocks marked as heterogeneous are not routed on routing segments which are not tagged to route them. Similar marking was used for homogeneous routing segments.

In the original VPR release, long lines are balanced and their connections are rotated among the wires of the channels in which they reside. This behavior is desirable in an FPGA where one wants to leverage the full routability of the circuit. However, this rotation is not desirable in our model since connections to the heterogeneous-only long lines are more substantial. To circumvent this issue, we disabled the long line balance feature for segments marked as heterogeneous, which allows the wires modeling the fixed-function routing to effectively span a fixed amount of the same columns. Currently, for a given defined segment, VPR will create both horizontal and vertical tracks in the routing graph. For our implementation, only horizontal long lines are used. Although vertical long lines for the heterogeneous-only routing layer were created, they were marked as unusable by the router and their area cost was ignored. All switch block and connection block connections to these wires were removed.

B. Benchmarks

Benchmarks with heterogeneous resources were used to evaluate our modified FPGA architecture. We choose to use the set of benchmarks included in the VTR design flow for experimentation. Among these benchmarks, 12 of them that use heterogeneous blocks (i.e. memories and multipliers) were selected to test our enhanced architecture. Table I sums up the benchmark details. The number of fixed-function blocks was calculated after the packing stage for our architecture. A total of 8 out of 12 designs make use of memories, and 7 out of 12 use multipliers. Of these designs, two of them have more than a thousand logic blocks.

V. RESULTS

In this section we evaluate results obtained with the benchmarks described in Section IV-B using the enhanced architecture detailed in Section III. We use the modified version of VPR described in Section IV-A to perform timing-driven packing, placing and routing for the 12 designs. Comparative results are obtained with respect to a standard architecture which is similar to the enhanced one, with the exception of the new routing for the heterogeneous-only routing. Place and route data concerning the standard architecture are presented in Table II. The basic partition of both architectures is a 8×8 array of logic blocks with one column dedicated to a memory of 8 blocks height, and another column containing two multipliers of 4 blocks height. The results of the enhanced architecture were generated with multiple side-by-side horizontal partitions of size 8 since this is the smallest common denominator of the logic fabric. Each long line tied to a specific heterogeneous block spans a single partition.

A. Logic array size

As observed in Table III, our enhanced architecture has no influence on the minimal array size (in number of logic blocks) on which a task can be placed.

B. Critical delay

The critical delay of each circuit is expressed in nanoseconds in Tables II and III. To ensure an equal quality of results for both architectures, the same timing driven options were given to VPR, and the same routing seed was used in both cases. Most of the benchmarks sees a critical delay change by less than 10% between the standard architecture and the enhanced one.

The critical path delay increase in Table III is limited and results from routing congestion when vertical routing tracks in the homogeneous routing layer are used to reach the horizontal long lines and the increased capacitance of the long lines for short connections. Some of the benchmarks expose a decrease in critical path delay (in particular diffeq2, mkPktMerge). These improvements originate from the use of long lines to reach heterogeneous blocks, reducing the wire delay for signals in the critical path. The critical path timing of a task must consider relocation-related issues. Since the logic content of a relocatable task is placed relatively to the heterogeneous blocks, we do not know in advance where homogeneous signal will step over a fixed-function block. This issue is addressed at the place-and-route stage through the use of conservative timing.

In our case, the main area impact is a result of the distribution of long lines across the FPGA: a horizontal routing channel contains the minimum number of long lines required to route every I/O of a partition of the biggest channel (i.e. the amount of connections to the most connection-intensive fixedfunction block). Long lines which are not tied to a specific I/O in a horizontal channel can be used for other purposes, which can result in a reduced critical delay.

C. Routing resources

Our approach primarily focuses on routing network enhancements. The isolation of routing resources for logic-block only and fixed-function blocks has several implications. As described in Section III, each input and output of the fixedfunctions blocks is tied to a unique long line of a partition.

We observe an increase in the routing resources needed in the homogeneous routing network (the channel width in Table III), of 1.97× on average. Routing resources due to the routing heterogeneous-only long lines dedicated to fixedfunction blocks in the partition are shown in the h-wire column in Table III. It should be noted that the heterogeneous long lines (h-wires) in the table for each benchmark are spread across an entire partition and not isolated in just one channel. As the number of h-wires increases, the number of logic-only homogeneous wires required to route signals up to the long lines increases to avoid network congestion.

Given these results, it is reasonable to define a nominal partition width of 8 columns, including heterogeneous blocks, for this specific architecture, as used in our experiments. This size allows for good performance in terms of flexibility, while still making a good trade-off in routing resources demand and occupied area. Our approach eliminates the need for routing when a task is moved. The only required change for the task bitstream is to shift the homogeneous-to-heterogeneous and heterogeneous-to-fixed-function block connections horizontally. The position of these connections in the bitstream can easily be offset by a fixed amount for the hundred or so connections for each fixed-function block as the task is loaded into the device.

VI. CONCLUSIONS AND FUTURE WORK

This paper presents an enhanced FPGA architecture supporting the relocation of tasks and associated partial bitstreams even if the relative position of fixed-function blocks in the target partially-reconfigurable region is changed. A standard island-style FPGA architecture has been expanded to include a dedicated routing layer for fixed-function blocks. Long lines are used in this layer to allow blocks to "float" horizontally within a region, greatly expanding partially-reconfiguration region placement. The routing implications and costs associated with this freedom have been investigated for a variety of VTR benchmarks including fixed-function resources. This architecture is only the first step in the development of a dynamically reconfigurable FPGA for the FlexTiles project which allows for fast task migration and ease-of-use from a designer standpoint. The architecture treats I/Os in addition to multipliers and DSP blocks as fixed-function blocks, necessitating our new approach. Future implementations will allow for both horizontal and vertical connections in the heterogeneousonly routing layer. Additionally, research is needed to study the impact of various architectural parameters (e.g. task geometry, routing lines spreading) on detailed performance.

Fig. 2 :

 2 Fig. 2: Abstraction of heterogeneous resources: (a) Original logic array (b) Resulting set of logic-only and fixed-function only arrays

1 )Fig. 3 :Fig. 4 :

 134 Fig. 3: Switch box enhanced to include connections between heterogeneous and homogeneous layers. Red and blue horizontal wires (the top four wires) represent heterogeneousonly long lines while the remaining black wires represent homogeneous routing

Fig. 6 :

 6 Fig. 6: Two placements of the same task on the enhanced architecture with VPR

TABLE I :

 I VTR design flow benchmark suite

	Benchmark	Memories	Multipliers	LBs
	LU8PEEng	45	8	2,174
	bgm	0	11	2,977
	boundtop	1	0	272
	ch intrinsics	1	0	41
	diffeq1	0	5	43
	diffeq2	0	5	30
	mkDelayWorker32B	41	0	497
	mkPktMerge	15	0	17
	mkSMAdapter4B	5	0	181
	or1200	2	1	273
	raygentop	1	7	192
	stereovision1	0	38	990

TABLE II :

 II Place and route benchmark results on the standard architecture

	Benchmark	Array size	Chan. width	Crit. delay (ns)
	LU8PEEng	56	77	124.06
	bgm	64	91	34.66
	boundtop	20	36	7.17
	ch intrinsics	8	25	3.57
	diffeq1	12	32	16.17
	diffeq2	12	28	13.84
	mkDelayWorker32B	50	65	11.25
	mkPktMerge	32	24	5.60
	mkSMAdapter4B	18	44	7.34
	or1200	25	55	13.36
	raygentop	17	45	5.11
	stereovision1	37	76	6.24

TABLE III :

 III Place and route benchmark results on the enhanced architecture

	Name	Size	Chan. width	H-wire	Crit. delay (ns)
	LU8PEEng	56	139	(1.81×)	324	134.41	(1.08×)
	bgm	64	108	(1,19×)	324	35.67	(1.03×)
	boundtop	20	56	(1.56×)	324	7.51	(1.05×)
	ch intrinsics	8	25	(1.00×)	162	3.84	(1.08×)
	diffeq1	12	96	(3.00×)	234	15.96	(0.99×)
	diffeq2	12	65	(2.32×)	234	12.66	(0.92×)
	mkDelayWorker32B	50	117	(1.80×)	324	11.46	(1.02×)
	mkPktMerge	32	92	(3.83×)	324	4.84	(0.86×)
	mkSMAdapter4B	18	83	(1.89×)	324	7.35	(1.00×)
	or1200	25	77	(1.40×)	324	13.62	(1.02×)
	raygentop	17	98	(2.18×)	324	5.78	(1.13×)
	stereovision1	37	129	(1.70×)	324	6.97	(1.12×)

ACKNOWLEDGMENT

This research was sponsored by the European Commission under the 7th Framework program within the FlexTiles project (FPT ICT-288248) and by the French Ministry of Research. R. Tessier was supported in part by National Science Foundation grant EECS-1201834.


Vivek D Tovinakere
email: vivektd@gmail.com

Olivier Sentieys
email: sentieys@irisa.fr

Steven Derrien
email: sderrien@irisa.fr

Christophe Huriaux
email: christophe.huriaux@irisa.fr

Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes

Keywords: Low power, microcontrollers, power gating, reconfigurable hardware, wireless sensor networks

A key concern in the design of controllers in wireless sensor network (WSN) nodes is the flexibility to execute different control tasks involving sensing, communications and computational resources of the node. In this paper, low power flexible controllers for WSN nodes based on reconfigurable microtasks composed of an FSM and datapath are presented. Coarse grain power gating opportunities are exploited in FSM and datapath for low power operation in reconfigurable microtasks. Power estimation results on typical benchmark microtasks show a 2× to 5× improvement in energy efficiency w.r.t a microcontroller at a cost of 5× relative to a microtask implemented as an ASIC with higher NRE costs.

I. INTRODUCTION

Wireless Sensor Network (WSN) nodes typically need to process signals from sensors and perform transceiver tasks as part of wireless communications in the network. Adaptive nodes may need to change their roles dynamically while the internal resources of a node are also to be managed implying that flexibility of controllers is an important consideration in the design of WSN nodes. An important aspect in the design of WSN nodes that conflicts with flexibility is their energy efficiency. It is estimated that upto 25% of total power budget in a node may be consumed by controllers in active mode and a considerably higher fraction in idle mode. Hence it is important to optimize controllers integrated within a node for low power in both active and standby states.

In general, microcontrollers and FPGAs offer flexibility but are not energy efficient as dedicated circuits. WSN platforms described in [START_REF] Polastre | Telos: Enabling ultra-low power wireless research[END_REF] and [START_REF] Beutel | BTnodes -a distributed platform for sensor nodes[END_REF] have used low-power microcontrollers as their driving engines for control tasks. A spectrum of low power techniques -from clock gating to power gating and subthreshold design [START_REF] Seok | The Phoenix processor: A 30pW platform for sensor applications[END_REF], [START_REF] Sheets | A power-managed protocol processor for wireless sensor networks[END_REF] -have been implemented in such microcontrollers. Nevertheless, microcontrollers are far from being optimal solutions in several applications as sequential execution of instructions for control tasks exercise significant logic of a microcontroller to cause high power consumption. Several works have focussed on low power optimizations of island-type FPGA architectures using subthreshold supply voltages, dynamic voltage scaling, power-efficient routing fabric [START_REF] Lin | A low-power field-programmable gate array routing fabric[END_REF], power gating [START_REF] Ishihara | A low-power FPGA based on autonomous fine-grain power gating[END_REF] and different circuit techniques for LUT design. An outcome of these works has been customization of recon-figurable systems for specific classes of energy-constrained applications. In this paper, the intermediate design space between dedicated ASIC solutions and microcontrollers is explored. The focus of our work is to identify architectures for reconfigurable controllers that are amenable to low power optimizations and yet retain flexibility for a variety of control tasks in WSN nodes.

II. MICROTASK-BASED CONTROLLERS

Consider a controller that is required to execute combinations of M control tasks T i , i = 0, 1, 2, ..., M -1 as specified by a task flow graph (Figure 1(a)). A microtask is a physical realization of T i and may be obtained as combination of an FSM for control and a datapath for computations. A system level view of realization of a task flow graph as a set of microtasks is shown in Figure 1(b). A typical structure of microtask is shown in Figure 2. A microtask is dedicated to execution of a specific control task once it is generated by the design flow. A system monitor manages scheduling of microtasks according to the task flow graph. In order to exploit low-power techniques in generated controllers, the tasks are mapped onto microtasks in such a way that, during the operation of the controller based on a run-to-completion semantic, all microtasks than those required may be power-gated to suppress leakage power. However, unlike microcontrollers, the utility of generated microtasks is limited due to the specificity of application. Reconfigurable circuits offer an alternative in terms of flexibility, particularly in specific application domains like WSNs. In this paper, low power reconfigurable architectures with routing fabric customized for FSMs and variable-precision adders in datapaths targeted towards flexible microtasks are presented. We use power gating to suppress high leakage power in nanoscale CMOS circuits. Whereas energy savings in standby mode of system operation due to power gating is obvious for low duty cycle operation, it is sought to achieve active mode leakage reduction in FSM and datapath elements by a divide and conquer approach.

III. LOW POWER RECONFIGURABLE FSMS

A. Notations

Let at time unit t, the n primary inputs to the FSM be denoted by the vector x(t) = [x 0 (t), x 1 (t), ..., x n-1 (t)], the m outputs of FSM by y(t) = [y 0 (t), y 1 (t), ..., y m-1 (t)] and the state vector of N -bit state register by s(t) = [s 0 (t), s 1 (t), ..., s N -1 (t)]. For notational convenience, we use the triplet (N , n, m) to denote the FSM parameters defined above. The next-state functions of an FSM of Moore type may be written as

s i (t + 1) = 2 (n+N -K) -1 k=0 m k f i (n(m k ), ..., s N -1 ) k (1)
where K corresponds to number of variables on which f i (.) k depends after Shannon decomposition and denotes logical-OR of the boolean functions. The minterm generated by first n + N -K input variables of the sequence x i , ..., s i (t + 1) is denoted by m k . Similarly, the output functions may be written as

y l =      2 Ns -1 k=0 m k g l (n(m k ), ..., s N -1 ) k K op < N (Case 1), g l (s 0 , ..., s N -1 ) k K op ≥ N (Case 2)
(2) where K op denote the number of inputs of a K op -LUT and N s = N -K op . The FSM is fully reconfigurable if its realization can be configured to support any set of boolean functions f i and g l temporally. Assuming that each f i (.) k can be realized with K-LUTs and g l (.) k with K op -LUTs, it can be inferred that realization of s(t + 1) and y(t) requires the resources as shown in Table I.

Resources

Next-state functions Output functions

# LUTs N × 2 (n+N -K) m × 2 Ns K-LUTs Kop-LUTs Decoder Size (n + N -K)-to- (n + N -K)-to- 2 (n+N -K) 2 (n+N -K) (shared) AND logic N × 2 (n+N -K) m × 2 (n+N -K) OR logic 2 (n+N -K) 2 (n+N -K) (Case 1) Configuration Bits N × 2 n+N m × 2 N Table I RESOURCES FOR RECONFIGURABLE FSMS

B. Power Gating Opportunities in Reconfigurable FSMs

In this work, we seek to identify power gating opportunities in reconfigurable FSMs at a granularity of LUT decoding logic to reduce leakage power. It should be noted that to preserve configuration data, the reconfiguration memory needs to be in always-on power domain. Power gating opportunities can be identified in Figure 3 at the granularity of a LUT and associated AND gates. This network of sleep transistors requires as many control signals as the number of LUTs. When the reconfigurable FSM is configured as a particular FSM, its operation depends on some of the primary inputs that possibly vary slowly and therefore, depending on the values of those inputs all but one of the minterms evaluate to logic 0. The decoder outputs, then can function as control signals (SLEEP k = power gate i + m ′ k in Figure 3) to power-gate the respective LUT while also eliminating the need for a separate controller.

C. Overall Architecture

The overall architecture for a power-gated reconfigurable FSM is shown in a schematic form in Figure 4. Each unit of the architecture corresponds to Figure 3. N such units constitute the logic for state register bits and m units corresponding to FSM outputs. The power consumption at any given time is due only to N + m LUT logic clusters apart from blocks in always-on domain.

D. Low Power Reconfigurable Precision Adders

In this work, we use a 32-bit adder partitioned into 4 clusters, each representing slices of 8-bit datapath along with their input and output stages. The clusters together represent the parallel prefix carry generation logic of the adder. Each cluster, along with its input and output stages are powergated by sleep transistors. The sizes of sleep transistors are approximately 10% of the total size of all transistors in the power-gated cluster.

IV. POWER ESTIMATION AND ANALYSIS

The total average power consumption of the power-gated architecture for a particular mapping of FSM is given by Equation (3) in the next page, where N F SM and m F SM are number of mapped state register bits and outputs, N CB denotes the total number of configuration bits, P static,LU T , P static,CB , P static,SR , P static,iso and P static,IP D denote the static power of K-LUT logic, a configuration bit register, state register bit, isolation cell and input selector-decoder respectively. Further, E dyn,LU T and E dyn,IP D represent the average dynamic energy components of LUT logic and input selector-decoder due to changes in inputs. An average activity factor for transitions is assumed by means of f inp,av , the average rate of change of inputs. We consider the worst case with wakeup transition for all state register bits and outputs to account for wakeup energy E wu .

We consider a 6-LUT for lookup table implementations in reconfigurable FSM. The combinational logic of 6-LUT is synthesized using a 65nm industrial technology library. Switching energy for a single LUT is determined by applying 10000 sets of random inputs and computing the average total switched load for one input set at a supply voltage of 1.0V as

E dyn LU T = V dd r 1 N input Ninput i=1 C swi,LU T (4)
where C swi,LU T is the total switched capacitance of the LUT per input set and r 1 is the steady state Virtual-V dd . The various parameters of power-gated 6-LUT decoding logic is shown in Table II

E op,F SM = P static,F SM f clk + E dyn,F SM . (5)

A. Energy Efficiency and Cost of Flexibility

A metric to measure energy efficiency of different realizations is the equivalent energy per instruction of a low power microcontroller. We consider controller task implementations on openMSP430 [START_REF] Opencores | The openMSP430 User Guide[END_REF], an opencores microcontroller with an instruction set isomorphic to MSP430 used in WSN platforms, to compare microtask based implementations across different tasks. The energy per operation of a microtask E op,M T is given by E op,M T = (P static,F SM + P static,adder + P static,RF )/f clk +E dyn,F SM + E dyn,adder + E dyn,RF [START_REF] Ishihara | A low-power FPGA based on autonomous fine-grain power gating[END_REF] where P static,adder , P static,RF , E dyn,adder and E dyn,RF represent static power of 32-bit adder power-gated for 16-bit addition, register file and energy per operation of adder and register file respectively. The total energy for execution of a task is then

E task = N st E op,M T (7)
where N st is the number of operations or state transitions required to execute the task. Hence the equivalent energy per instruction is determined as

E ef f = E task N inst (8)
where N inst is the number of instructions required to execute the same task on the microcontroller. Table III shows the metric for control tasks realized with a microcontroller, reconfigurable microtasks and hardwired microtasks. Among the three realizations, hardwired microtasks represent the most energy efficient implementation for a specific controller since they are obtained as a result of ASIC synthesis. In this exercise, a register file of size 16 × 16 was used.

It can be inferred from the table that among hardwired and reconfigurable microtasks, the latter has about 5× cost in the energy per operation of the benchmark microtask.

P total,F SM = (N F SM + m F SM )P static,LU T + N CB P static,CB + 2 N (N F SM 2 n-K + m F SM 2 -Kop )P static,iso + N F SM (P static,IP D + P static,SR ) +

N F SM E dyn,IP D f inp,av + (N F SM + m F SM )(E wu + E dyn,LU T )f inp,av . (3)
Similarly among flexible controller implementations, it can be inferred that energy per instruction in microcontrollers is typically higher than energy per operation of reconfigurable microtasks assuming that in both realizations energy consumption is same for a control task. It should be noted that the energy per instruction metric for openMSP430 microcontroller excludes energy due to instruction and data memories making the comparison equitable.

Microtask [START_REF] Nazhandali | SenseBench: Toward an accurate evaluation of sensor network processors[END_REF] Equivalent typically require about 50 tasks to be integrated. The total area of a controller would be the sum of areas of all microtasks and associated system monitor and memories. In principle, a reconfigurable microtask can be used in place of hardwired microtasks by time-multiplexing tasks at the controller level. The advantages of power gating are present in both active and standby modes of operation.

V. CONCLUSION A common thread in our exploration of scalable reconfigurable architectures for low power in this paper was to identify and power-gate unused logic for aggressive leakage power savings in active modes of operation. An analysis of power estimation in reconfigurable microtasks show that they offer flexibility with a significantly reduced cost in equivalent energy per instruction compared to a microcontroller. The primary drawback of LUT-based flexible circuits is the large reconfiguration memory that consumes substantial power as they must always remain in ON state.

A useful approach at an architecture level is to investigate alternate reconfiguration mechanisms and is proposed for future work.

Figure 1 .

 1 Figure 1. (a) A task flow graph and (b) system-level view of a task flow graph.

Figure 2 .

 2 Figure 2. Structure of a typical microtask T i .

Figure 3 .

 3 Figure 3. Power gating opportunity for aggressive active mode energy savings in a reconfigurable FSM.

  . The total average energy consumption

	Power-Gated K-LUT Parameter	K=6
	P static at V dd =1V (µW)	12.56
	Mean switching snergy per state or input transition	0.059pJ
	Sleep transistor width W (µm)	0.54	12
	Steady state Virtual-V dd r 1 (mV)	980	998
	Table II
	POWER-GATED K-LUT PARAMETERS FOR POWER ESTIMATION.
	per operation (clock cycle) is obtained from

Table IV

 IV

	gives a comparison of area estimates of hard-
	wired microtasks and the proposed reconfigurable microtask.
	From a controller's perspective, a WSN application would
	Microtask	Hardwired Microtask(µm 2 ) Microtask (µm 2 ) Reconfigurable
	Crc8	3097
	receiveData Crc16	2858 3102	140522.2
	firBasic	7164
		Table IV
	COMPARISON OF AREAS OF 16-BIT HARDWIRED AND
	RECONFIGURABLE MICROTASKS.

VI. ACKNOWLEDGEMENTS

The first author wishes to acknowledge University of Rennes 1, France for supporting this work carried out in the CAIRN/IRISA Lab., Lannion, France.


P Lemoine

N R Lee-Hone

D H Ryan

A Vernière

B Malaman

G Le Caër

Neutron powder diffraction and Mössbauer spectroscopy ( 119 Sn and 155 Gd) studies of the CeScSi-type GdMgSn and GdMgPb compounds

Keywords: number(s): 75.25.-j, 61.05.fm, 76.80.+y

The magnetic structures of the CeScSi-type GdMgSn and GdMgPb compounds have been studied by both neutron powder diffraction and Mössbauer spectroscopy ( 119 Sn and 155 Gd). The neutron diffraction results show that the two compounds adopt incommensurate antiferromagnetic structures at 5.4 K with propagation vectors k = [0.910,0.077,0] for GdMgSn and k = [0.892,0,0] for GdMgPb. The magnetic moments lie in the basal plane, which is confirmed by both 119 Sn and 155 Gd Mössbauer spectroscopy. Mössbauer spectroscopy refinements and simulations reveal that the magnetic structure of GdMgSn is cycloidal at low temperature and undergoes a transition to a modulated magnetic structure above T ∼ 40 K. A similar magnetic transition is inferred for GdMgPb. The magnetic structures of GdMgSn and GdMgPb are compared with those of other CeScSi-type compounds.

I. INTRODUCTION

The RMgSn and RMgPb compounds (where R is a rareearth element) crystallize in the CeScSi-type structure (space group I4/mmm, No. 139) [1][2][3] and order antiferromagnetically with T N ranging from 2.5 K for TmMgPb to 79 K for SmMgSn [3,4]. A few other compounds in the RTX series (where T is a transition metal and X is a p-block element) such as PrScSi [5], PrScGe [5,6], and ErZrSb [7] are antiferromagnetic at low temperatures, while most CeScSi-type compounds are ferromagnetic at low temperatures: RScSi (R = Ce,Nd,Sm,Gd) [5,[8][9][10], RScGe (R = Ce -Nd,Sm,Gd,Tb) [5,6,[8][9][10][11][12][13][14], RZrSb (R = Gd -Tm) [7,15], and RTiGe (R = Gd,Tb) [16][17][18][19][20].

Neutron powder diffraction studies on the CeScSi-type RMgSn and RMgPb compounds [4,21,22] have revealed relatively complex magnetic structures with similar magnetic arrangements for any given rare-earth element. For example, at very low temperatures PrMgSn, PrMgPb, NdMgSn, and NdMgPb each adopt commensurate antiferromagnetic structures, TbMgSn and TbMgPb adopt incommensurate sine-wave-modulated magnetic structures, and DyMgSn, DyMgPb, HoMgSn, HoMgPb, ErMgSn, and ErMgPb adopt square-wave-modulated magnetic structures [4,22]. The only exception to this consistency seems to be between the * pierric.lemoine@ensicaen.fr † nicholas.lee-hone@mail.mcgill.ca TmMgSn/TmMgPb pair. TmMgSn adopts a square-wavemodulated magnetic structure while TmMgPb adopts a more complicated magnetic structure with two propagation vectors [4,22].

Mössbauer spectroscopy and neutron diffraction play complementary roles in the study of magnetic order in rare-earth intermetallics. The first provides local information on magnetic environments, while the second yields values for ordered moments and a description of the long-range magnetic order [23]. We have therefore used these techniques to complete the magnetic structure characterization of the CeScSi-type RMgSn and RMgPb series by studying the antiferromagnetic structure of GdMgSn and GdMgPb (T N = 48(2) K and 47(2) K, respectively) [3,4]. We performed 119 Sn and 155 Gd Mössbauer spectroscopy and neutron powder diffraction using a largearea flat-plate-geometry sample holder [24,25]. The flat-plate sample holder allows one to obtain diffraction patterns of intermetallic compounds with high thermal neutron absorption cross-section elements (Sm, Eu, Gd, Cd, B), without resorting to short wavelengths or isotopically enriched samples. This technique has been used successfully in many recent studies [26][27][28][29][30][31].

II. EXPERIMENTAL METHODS

The polycrystalline samples were synthesized starting from stoichiometric amounts of high-purity commercially available elements (99.9 wt % for lead and gadolinium, 99.99 wt % for magnesium and tin). As a general precaution, all sample manipulations were undertaken in a purified argon-filled glovebox ensuring an oxygen level of less than 2 ppm O 2 and about 3 ppm H 2 O. Due to the high volatility of magnesium, the elements were placed in an arc-welded Mo crucible. The elements were then melted in a water-cooled copper crucible using a high-frequency induction furnace (CELES), under secondary vacuum. To prevent oxidation, the Mo crucibles were subsequently enclosed in a silica tube under purified argon (300 mm Hg), placed in a furnace for two weeks at 1073 K, and then water cooled. There was no noticeable reaction between the samples and the container.

The crystallographic structure and presence of impurities were checked by x-ray powder diffraction (Philips X'Pert Pro Diffractometer, Cu Kα). The analysis of the patterns was performed by Rietveld profile refinement using the FULLPROF/WINPLOTR suite [32,33]. It is worth noting that at this stage, the samples were clearly observed to deteriorate in air, justifying the precautions taken during sample preparation.

Thermal neutron diffraction experiments were carried out on the C2 multiwire powder diffractometer (DUALSPEC) at the NRU reactor, Canadian Neutron Beam Centre, Chalk River, Ontario. A large-area silicon flat-plate sample holder [24,25] was used to minimize the effects of absorption by the natural Gd in the sample. Most of the data were taken at a neutron wavelength of λ = 1.3286(1) Å to make best use of the available flux from the thermal source. However, a set of diffraction patterns was also obtained at the longer wavelength of λ = 2.3731(1) Å to ensure that no low-q magnetic diffraction peaks were being lost in the direct beam at λ = 1.3286(1) Å. Temperatures down to 5.4 K were obtained using a closed-cycle fridge. As the samples are air sensitive, they were ground and mounted in the flat-plate sample holder under a helium atmosphere and then sealed into an aluminum can to guarantee a helium atmosphere at all times during transport and measurement. These materials blacken quite rapidly on exposure to air but when the samples were removed from the mounts several months after the measurements, no such discoloration was observed. All full-pattern magnetic and structural refinements employed the FULLPROF/WINPLOTR suite [32,33] with neutron scattering length coefficients for natural Gd taken from the tabulation by Lynn and Seeger [34]. No absorption correction was applied; however, the data were truncated at 2θ = 52.5 • to minimize the impact of angle-dependent absorption effects.

For the 155 Gd Mössbauer spectroscopy measurements, the sample and 50 mCi 155 SmPd 3 source were mounted vertically in a helium flow cryostat, and the drive was operated in sine mode. The drive system was calibrated using a laser interferometer with velocities cross-checked against both 57 CoRh/α-Fe at room temperature and GdFe 2 at 5 K. The spectra were fitted using a nonlinear least-squares minimization routine with line positions and intensities derived from an exact solution to the full Hamiltonian [35].

119 Sn Mössbauer spectra were collected in transmission mode on a constant-acceleration spectrometer using a ∼10 mCi Ba 119m SnO 3 source with the sample in a helium flow cryostat. The source was kept at room temperature. A 25 μm Pd foil was used to absorb the Sn Kα x rays also emitted by the source. The spectrometer was calibrated with a 25 mCi 57 CoRh source and α-Fe at room temperature, and the 119 Sn isomer shifts are referenced to BaSnO 3 at room temperature. Mössbauer spectra that have no hyperfine field distribution were fitted with a standard least-squares method assuming Lorentzian peaks. The magnetically split spectra that have a distribution of hyperfine fields were analyzed by a constrained Hesse-Rübartsch method as described in Ref. [36]. This method extracts a hyperfine magnetic field distribution P (B) from an experimental spectrum, where P (B) B represents the fraction of tin atoms whose field is between B and B + B. To obtain P (B) ( 0), the spectrum is considered to be a sum of N sextets of Lorentzian lines with a full width at half maximum of 0.6 mm/s, characteristic of the 119 Sn isotope. The calculated distribution is thus a histogram of N bins of identical widths B ∼ 0.15-0.20 T. It is normalized so that

N i=1 P (B i ) B = 1, with B i = (i -1/2) B (i = 1, . .

. ,N).

III. RESULTS AND DISCUSSION

The neutron powder diffraction patterns taken at 60 and 5.4 K, along with the difference between these patterns, are shown in Fig. 1. The appearance of purely magnetic peaks at low temperature in the angular range 4 • 2θ 28 • is clearly observed, confirming the antiferromagnetic order of these compounds.

A. Paramagnetic neutron diffraction

The neutron powder diffraction patterns recorded in the paramagnetic state (T = 60 K) clearly show the nuclear Bragg peaks of the CeScSi-type GdMgSn and GdMgPb compounds (Fig. 2). Extra diffraction peaks due to the sample mount were observed in the 2θ = 34 • -41 • range, so this entire region was excluded from the refinements. The crystallographic data obtained from the refinements of the 60 K neutron diffraction patterns are presented in Table I. The GdMgX (X = Sn,Pb) compounds crystallize in the tetragonal space group I4/mmm. In this structure the Gd, Mg, and X atoms occupy the 4(e) (0,0,z Gd ), 4(c) (0,1/2,0), and 4(e) (0,0,z X ) crystallographic sites, respectively. The crystallographic unit cell contains four gadolinium atoms with positions (0,0,z Gd ), (1/2,1/2,1/2 + z Gd ), (0,0,z Gd ), and (1/2,1/2,1/2z Gd ), which we label Gd 1 , Gd 2 , Gd 3 , and Gd 4 , respectively. These atoms are connected in pairs by the I-centering operation as shown in Fig. 3.

B. Magnetic structure of GdMgSn

The neutron powder diffraction pattern recorded at 5.4 K (Fig. 1) has many additional purely magnetic peaks. The upper panel of Fig. 4 shows the thermal variation of the intensity of the strongest magnetic diffraction peak of GdMgSn. The kink in the intensity at around 25 K suggests a change in the magnetic structure. Further evidence for a change in magnetic structure comes from the position of this peak which clearly starts to move to higher angles above 25 K (lower panel of Fig. 4).

The diffraction pattern recorded at 5.4 K (Fig. 5) can be indexed by the propagation vector k = [∼0.93, ∼0.09,0], indicating an incommensurate antiferromagnetic structure. The absence of any contribution to the nuclear diffraction peaks immediately rules out a conical magnetic structure with cone angles other than 90 • . Although the absence of higherorder harmonic peaks suggests that a square-wave-modulated magnetic structure can be excluded, the magnetic diffraction peaks corresponding to the first odd integer harmonic (3k) would be difficult to observe due to the low signal-to-noise ratio and the very weak amplitude expected for these magnetic peaks [i.e., A(3k) = A(k)/3].

The neutron diffraction pattern can be refined using either a planar helimagnetic structure (corresponding to a conical magnetic structure with a cone angle of 90 • ) or a sinusoidally modulated magnetic structure. When performing conical magnetic structure refinements with FULLPROF, no symmetry operations can be introduced (i.e., all of the magnetic atoms within a primitive unit cell must be given), meaning the magnetic refinements have to be performed using the P1 magnetic space group. As a result, in order for the propagation vector k = [q x ,q y ,0] to remain within the first Brillouin zone, q x and q y are restricted: q x 0.5 and q y 0.5 [START_REF] Rossat-Mignod | Neutron Scattering[END_REF]. However, to facilitate comparison with the magnetic structures previously reported for the CeScSi-type RMgSn and RMgPb compounds (refined with the magnetic space group I1) [4,22], we have used the propagation vector k = [q x ,q y ,0] with q x 1 and q y 0.5.

For the planar helimagnetic structure (flat spiral or cycloidal magnetic structure) [38], the magnetic moments are oriented in the ab plane (θ n = 0 • ) with a magnitude μ Gd of 6.11 (10)μ B (Table II). The planar orientation of the Gd 3+ magnetic moments combined with the q x and q y components of the propagation vector give a cycloidal magnetic structure [38]. The magnetic moments of the alternative, sinusoidally modulated magnetic structure are also oriented in the ab plane with a sine-wave amplitude A(k) = 8.53( 14)μ B , giving a magnetic moment μ Gd of 6.03(10)μ B (Table II). As q y is almost equal to 1q x , (q x ∼ q y with the propagation vector k ), the azimuthal angle φ (relative to the a axis) cannot be refined for either magnetic structure. Finally, the two magnetic structures lead to similar refinements and it is virtually impossible to distinguish between them on the basis of the various refinement R factors presented in Table II.

A further neutron diffraction pattern recorded at 5.4 K with a wavelength of λ = 2.3731(1) Å confirms the absence of very low-angle magnetic diffraction peaks and the existence of a q y component of the propagation vector (Fig. 6). The refinement of this pattern considering the ab-plane cycloidal magnetic structure gives a propagation vector k = [0.910(2),0.077(2),0] and a magnetic moment of μ Gd = 6.54(16)μ B , which is relatively close to the free-ion value of 7.00μ B expected for the Gd 3+ ion. With this neutron wavelength, the magnetic diffraction peaks are extended on a broader angular range, allowing a more accurate determination of the q x and q y components of the propagation vector. Thus, the magnetic structure at 5.4 K will be described considering these q x and q y components of the propagation vector, which are slightly smaller than those refined with the neutron pattern recorded with λ = 1.3286(1) Å.

There are now a total of three possible magnetic structures for GdMgSn: cycloidal, square-wave-modulated, and sinewave modulated. We therefore turn to 155 Gd Mössbauer spectroscopy to help determine which of the competing magnetic structures is correct.

Gd occupies the 4e crystallographic site, which has 4mm point symmetry. This ensures an axially symmetric electric field gradient (EFG) tensor, with an asymmetry parameter η = 0 and the principal axis aligned with the crystallographic c axis [39]. Since the hyperfine field B hf at the Gd site derives almost entirely from the local contribution of the Gd moment, B hf will be parallel to the Gd moment, and so the angle (θ ) between the principal axis of the EFG and B hf is a direct measurement of the angle between the Gd moments and the crystallographic c axis.

The 155 Gd Mössbauer spectra of GdMgSn are shown in Fig. 7. Attempting to fit the 5 K spectrum with a sinusoidally varying hyperfine field yielded poor results, whereas a singlesite fit was found to work quite well, and gives θ = 90 • . This result is in agreement with the neutron diffraction results which indicate that the moments lie in the ab plane. As Mössbauer spectroscopy cannot distinguish between a moment pointing parallel or antiparallel to a given direction, a square-wave-modulated magnetic structure will appear as a single gadolinium environment. In addition, since η = 0, all azimuthal directions are equivalent. A cycloidal magnetic structure with the moments rotating in the ab plane is thus indistinguishable from a square-wave-modulated magnetic structure.

Figure 8 shows a clear break from the expected J = 7/2 Brillouin function at temperatures above 40 K, suggesting a magnetic transition. Between 40 K and T N = 48(1) K, the spectra can be refined as either sine-wave modulated or single site. As the spectra in this temperature range are centrally peaked and have no defining features, the two types of fits are equally good. The hyperfine field found with the singlesite fit corresponds to the average value of the hyperfine field distribution of the sine-wave fits.

The 155 Gd Mössbauer spectra allows exclusion of the sinewave-modulated magnetic structure only at low temperatures, so a complementary method is needed. We therefore turn to our recent work on the calculation of 119 Sn hyperfine field distributions in RMgSn compounds to help determine the correct magnetic structure [40]. This method has successfully reproduced the major features seen by 119 Sn Mössbauer spectroscopy in other CeScSi-type RMgSn compounds with R = Nd, Tb, Dy, Ho, and Er. It was also able to discriminate between competing magnetic structure models proposed by neutron powder diffraction in the case of TbMgSn.

Tin does not have a magnetic moment so any hyperfine field observed by 119 Sn Mössbauer spectroscopy is induced by either an external applied magnetic field or a magnetic field produced by a neighboring atom. The method described in Ref. [40] uses the magnetic structure description obtained from neutron powder diffraction to calculate the expected transferred hyperfine field distribution at the Sn site in RMgSn compounds. The results of the calculations for the three candidate magnetic structures are shown in Figs. 9(a), 9(b), and 9(c) and are clearly distinct. The cycloidal structure yields a single peak-the Sn atoms experience a unique magnetic environment-while the square-wave-modulated magnetic structure leads to three peaks with quite different intensities. Finally, the sine-wave-modulated magnetic structure shows a broad distribution of hyperfine fields in the form of a plateau leading to terminal peak.

The temperature evolution of the 119 Sn Mössbauer spectra and the corresponding hyperfine field probability distributions are shown in Fig. 9(h). Comparison of the calculated and measured hyperfine field distributions reveals that at low temperatures the Gd moments in GdMgSn adopt a cycloidal magnetic structure. Above 40 K the probability distribution changes to resemble that calculated for a sine-wave-modulated structure.

We note that an elliptical magnetic structure corresponding to both orientation and magnitude modulation cannot be excluded around 40 K. In fact, above 25 K the hyperfine field probability distributions in Fig. 9(h) have an additional feature around 2 T. Figure 4 also shows that the position of the strongest magnetic diffraction peak shifts above 25 K, indicating an evolution of the magnetic propagation vector. We therefore conclude that the magnetic structure of GdMgSn evolves from cycloidal (Fig. 10) at low temperatures to modulated at temperatures above 40 K by passing through an intermediate elliptical magnetic structure.

We also note that there is no one-to-one correspondence between the hyperfine field distribution calculated from Mössbauer spectra and a distribution of magnetic moments. This is because the hyperfine field distribution records the magnitude of the magnetic moments, making it impossible to directly retrieve the magnetic structure. While we cannot rule out more complex magnetic structures, the proposed ones are the simplest that are simultaneously consistent with neutron powder diffraction and 119 Sn and 155 Gd Mössbauer spectroscopy.

C. Magnetic structure of GdMgPb

The neutron powder diffraction pattern of GdMgPb recorded at 5.4 K (Fig. 11) shows many additional purely magnetic peaks that can be indexed by the propagation vector The refinement of the difference between the neutron diffraction patterns recorded at 5.4 and 60 K using a cycloidal magnetic structure is shown in Fig. 12. As with GdMgSn, the neutron diffraction pattern can be refined using either a planar helimagnetic structure (flat spiral or cycloidal magnetic structure) or a sinusoidally or square-wave-modulated magnetic structure. Again the two magnetic structure models lead to refinements that are virtually impossible to distinguish (Table III).

For the planar helimagnetic structure (cone angle θ c = 90 • ), the magnetic moments are oriented in the ab plane (cycloidal magnetic structure) and have a magnitude μ Gd of 5.26 (12)μ B (Table III). For the sinusoidally modulated magnetic structure the magnetic moments are also oriented in the ab plane with an azimuthal angle φ (relative to the a axis) of 41 (7) • and an amplitude of the sine wave A(k) of 7.46(17)μ B , giving a mean magnetic moment μ Gd of 5.28(12)μ B and 5.86(13)μ B for the sine-modulated and square-modulated structures, respectively (Table III). In both cases, the refined magnetic moment μ Gd is smaller than the expected 7μ B for the Gd 3+ free ion.

The 155 Gd Mössbauer spectra shown in Fig. 13 can be fitted with a single site from 5 K to T N = 49(1) K. This again allows us to exclude the sine-wave-modulated magnetic structure at low temperatures. B hf is plotted in Fig. 14 and follows a J = 7/2 Brillouin function below 40 K and deviates from this trend above 40 K in the same manner that was seen for GdMgSn. We also note that the position of the strongest magnetic peak in the neutron diffraction patterns of GdMgPb (not shown) behaves similarly to that seen in Fig. 4 for GdMgSn. The position of the strongest magnetic peak gradually increases above 20 K, indicating that the magnetic propagation vector changes. As discussed in the Introduction, the magnetic structures of the CeScSi-type RMgX (X = Sn,Pb) compounds tend to be similar for a given rare-earth element. Thus, given the strong similarities in both the behavior of the 155 Gd hyperfine fields and the magnetic structures found by neutron powder diffraction at 5.4 K, we conclude that both GdMgSn and GdMgPb adopt a cycloidal magnetic structure at low temperatures, pass through an intermediate elliptical structure between ∼25 K and 40 K, and finally adopt a modulated magnetic structure between 40 K and T N . To the best of our knowledge GdMgSn and GdMgPb are the first CeScSi-type compounds known to have this kind of magnetic structure transition.

IV. CONCLUSION

The CeScSi-type structure, magnetic ordering temperature, and antiferromagnetic behavior in GdMgSn and GdMgPb have been confirmed by both neutron powder diffraction and Mössbauer spectroscopy ( 119 Sn and 155 Gd). These complementary techniques reveal an incommensurate cycloidal magnetic structure at 5.4 K characterized by an ab-plane orientation of the magnetic moments and propagation vectors k = [0.910,0.077,0] and k = [0.892,0,0] for GdMgSn and GdMgPb, respectively. Similar magnetic structures have been reported for CeScSi-type ErZrSb [7] and TbMgSn [21]. Thus, GdMgSn and GdMgPb are the third and fourth CeScSi-type structure compounds reported to adopt incommensurate cycloidal magnetic structures. Above 40 K, a magnetic structure transition is observed for both compounds and the cycloidal magnetic structure transforms to a modulated one, leading to an additional kind of magnetic structure transition in the CeScSi-type compounds.

FIG. 1 .

 1 FIG. 1. (Color online) Neutron diffraction patterns of GdMgSn (left) and GdMgPb (right) at 60 and 5.4 K, together with the difference between the two patterns. The 60 and 5.4 K patterns have been offset vertically for clarity and their respective baseline positions are shown by the dashed lines at the right.

FIG. 2 .

 2 FIG. 2. (Color online) Refinement of the neutron diffraction patterns of GdMgSn and GdMgPb in the paramagnetic state with λ = 1.3286(1) Å.

FIG. 3 .

 3 FIG. 3. (Color online) Representation of the two Gd sublattices in the CeScSi-type structure.

FIG. 4 .

 4 FIG. 4. Temperature dependence of the intensity (top) and of the 2θ position (bottom) of the strongest magnetic diffraction peak of GdMgSn.

FIG. 6 .

 6 FIG. 6. (Color online) Refinement of the neutron powder diffraction pattern of GdMgSn recorded at 5.4 K with λ = 2.3731 Å. The top row of Bragg markers corresponds to the nuclear contribution and the bottom row corresponds to the magnetic contribution.

FIG. 7 .

 7 FIG. 7. (Color online) Fitted 155 Gd Mössbauer spectra of GdMgSn.

FIG. 8 .

 8 FIG. 8. (Color online) Temperature dependence of the hyperfine field (B hf ) of GdMgSn with a single-site fit. The J = 7/2 Brillouin fit is shown by the solid black line between 5 and 40 K. The dotted line above 40 K shows the expected behavior of the hyperfine field, and the dashed line shows the actual behavior.

FIG. 9 .

 9 FIG. 9. (Color online) (a),(b),(c) Calculated transferred hyperfine field distribution (THFD) for the three possible magnetic structures. (d),(e) Fitted THFD of GdMgSn obtained from the 119 Sn Mössbauer spectra. (f),(g) 119 Sn Mössbauer spectra of GdMgSn and fit to the data (solid red line). (h) Temperature evolution of the 119 Sn Mössbauer spectra and THFD of GdMgSn between 4 and 45 K.

FIG. 10 .

 10 FIG. 10. (Color online) The cycloidal magnetic structure of GdMgSn at 5.4 K. For clarity, we have omitted the nonmagnetic Mg and Sn atoms.

FIG. 11

 11 FIG. 11. (Color online) Refinement of the neutron powder diffraction pattern of GdMgPb recorded at 5.4 K with λ = 1.3286 Å. The top row of Bragg markers corresponds to the nuclear contribution and the bottom row corresponds to the magnetic contribution.

FIG. 12

 12 FIG. 12. (Color online) Refinement of the difference between the neutron powder diffraction patterns of GdMgPb recorded at 5.4 and 60 K with λ = 1.3286 Å. As all peaks are magnetic, the Bragg markers are for the magnetic phase.

FIG. 13 .

 13 FIG. 13. (Color online) Fitted 155 Gd Mössbauer spectra of GdMgPb.

TABLE I .

 I Crystallographic data of GdMgSn and GdMgPb obtained by refinement of the 60 K neutron powder diffraction patterns with λ = 1.3286(1) Å.

		GdMgSn	GdMgPb
	a ( Å)	4.391(4)	4.437(4)

c ( Å)

15

.855

(14)

15.984(18) z Gd 0.341(1) 0.344(1) z X 0.131(2) 0.135(2) R Bragg ; R f 18.3; 10.6 26.3; 23.0 R wp ; R expt 2.75; 1.45 3.46; 1.29 χ 2 3.59 7.14

TABLE II .

 II Results from the various refinements of the 5.4 K λ = 1.3286(1) Å neutron diffraction pattern of GdMgSn.

		Helimagnetic	Sinusoidal/square
	a ( Å)	4.389(3)	4.391(3)
	c ( Å)	15.851(11)	15.856(12)
	z Gd	0.339(1)	0.339(1)
	z Sn	0.131(2)	0.131(2)
	q x	0.927(4)	0.928(6)
	q y	0.088(4)	0.085(3)
	Helimagnetic
	θ c (deg)	90
	θ n (deg)	0
	Magnetic phases (Gd 1-4 )	0; 0; 0.5; 0.5
	μ Gd (units of μ B )	6.11(10)
	Sinusoidal/Square
	A(k) Gd		8.53(14)
	θ (deg)		90
	Magnetic phases (Gd 1-4 )		0; 0; 0.5; 0.5
	μ R magn	10.8	10.8
	R w ; R expt	2.91; 1.43	2.90; 1.43
	χ 2	4.14	4.10

Gd (units of μ B ) 6.03(10) a /6.70

(11)

b R Bragg ; R f 19.6; 12.8 19.2; 12.6 a Mean magnetic moment in the sine-modulated structure μ is calculated from the amplitude A(k) with the relation μ = A(k)2 -1/2 . b Mean magnetic moment in the square-modulated structure is calculated with the relation μ = A(k)π/4.

TABLE III .

 III Results from the various refinements of the 5.4 K neutron diffraction pattern of GdMgPb.

	Parameter	Helimagnetic	Sinusoidal/square
	a ( Å)	4.430(4)	4.430(4)
	c ( Å)	15.978(14)	15.980(15)
	z Gd	0.342(1)	0.342(1)
	z Pb	0.135(2)	0.135(2)
	q x	0.892(4)	0.892(4)
	Helimagnetic
	θ c (deg)	90
	θ n (deg)	0
	φ n (deg)	0
	Magnetic phases (Gd 1-4 )	0; 0; 0.5; 0.5
	μ Gd (units of μ B )	5.26(12)
	Sinusoidal/square
	A(k) Gd		7.46(17)
	θ (deg)		90
	φ (deg)		41(7)
	Magnetic phases (Gd 1-4 )		0; 0; 0.5; 0.5
	μ Gd (units of μ B )		5.28(12) a /5.86(13) b
	R Bragg ; R f	24.4; 17.7	24.5; 17.8
	R magn	15.5	15.8
	R wp ; R expt	3.54; 1.28	3.54; 1.28
	χ 2	7.57	7.59

a Mean magnetic moment in the sine-modulated structure μ is calculated from the amplitude A(k) with the relation μ = A(k)2 -1/2 . b Mean magnetic moment in the square-modulated structure is calculated with the relation μ = A(k)π/4.

ACKNOWLEDGMENTS

Financial support for various stages of this work was provided by the Natural Sciences and Engineering Re-search Council of Canada and Fonds Québécois de la Recherche sur la Nature et les Technologies. We thank J. M. Cadogan, UNSW Canberra, Australia, for many useful discussions. We gratefully acknowledge the assistance of Raghu Rao and Robert Speranzini in arranging for the activation of the 155 Gd Mössbauer source in the National Research Universal (NRU) research reactor, which is operated by Atomic Energy of Canada, Ltd., at Chalk River, Ontario.


Keywords: Electromagnetic compatibility, signal and power integrity, integrated circuits, on-chip sensor

With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. On-chip characterization of noise becomes necessary for model validation and design optimization to reduce redesign costs and time-to-market for IC manufacturers. This paper presents an on-chip noise sensor dedicated to the study of various aspects of electromagnetic compatibility at circuit level, such as power and signal integrity, substrate coupling, conducted emission and susceptibility to electromagnetic interferences. The different architectures of the sensor are presented as well as a demonstration of its measurement performance and benefits through many case studies. Applications of on-chip measurement may be extended towards online diagnosis and self-healing.

I. INTRODUCTION

HESE last years, the concerns about electromagnetic compatibility (EMC) of integrated circuits (IC) (emission and susceptibility issues), power and signal integrity have grown considerably. The need for prediction, during the design stage, of electrical failure risks has become critical for IC manufacturers in order to reduce redesign costs and timeto-market [START_REF] Ben Dhia | Electromagnetic Compatibility of Integrated Circuits -Techniques for low Emission and Susceptibility[END_REF]. Although several tools and prediction methodologies have been developed recently [START_REF] Vrignon | Characterization and modeling of parasitic emission in deep submicron CMOS[END_REF] [START_REF] Steinecke | EMI modeling and simulation in the IC design process[END_REF], accurate measurements of on-chip noise are still critical information for designers for model validation and design optimization.

For ICs emission characterization, on-chip measurement is an efficient method to study fast transient current induced by circuit activity instead of external characterization that is limited by the bandwidth of CMOS analog buffer and electrical parasitic elements of chip and package interconnects. For ICs immunity issues, on-chip measurement is the most efficient way to characterize EMI-induced noise and its effects on a sensitive node of a circuit. Studying noise propagation path and sensitivity of a disturbed function are critical information for IC designers to provide robust designs.

This paper aims at demonstrating the positive contribution of on-chip measurements to characterize accurately and solve power integrity, simultaneous switching noise, ground bounce, crosstalk, near-field and substrate coupling issues. Section II of this paper presents the general requirements of the on-chip noise sensor, its architecture and two different acquisition modes. The third section describes the sensor design and the experimental characterization of its performances. In the last section, a demonstration of its measurement performance and benefits through three cases studies is proposed.

II. ON-CHIP NOISE SENSORS

Most on-chip waveform capturing circuits are based on subsampling cell [START_REF] Larsson | Measuring high-bandwidth signals in CMOS circuits[END_REF] [START_REF] Ho | Applications of on-chip samplers for test and measurement of integrated circuits[END_REF] dedicated to repetitive signal measurements with very small time resolution, comprised between 100 ps [START_REF] Delmas-Bendhia | On-chip sampling in CMOS integrated circuits[END_REF] and 10 ps [START_REF] Takamiya | A on-chip 100 GHz-sampling rate 8-channel sampling oscilloscope with embedded sampling clock generator[END_REF] [START_REF] Zheng | On-chip oscilloscopes for non invasive timedomain measurement of waveforms in digital integrated circuits[END_REF]. Despite excellent time resolution characteristics, the circuit under test must operate in a special mode where a reproducible event is generated, so the noise produced during normal operating mode cannot be characterized. To overcome this issue an asynchronous sensor using a random sampling acquisition is proposed to provide valuable information about non-periodical signals.

A. Synchronous on-chip noise sensor

A first version of the on-chip noise sensor was designed in the early 2000s to address signal and power integrity issues at circuit level [START_REF] Delmas -Ben Dhia | A new method for measuring signal integrity in CMOS ICs[END_REF] [START_REF] Vrignon | On-chip sampling sensors for high frequency signals measurement: evolution and improvements[END_REF]. The sensor is based on a sequential equivalent-time sampling [START_REF] Schoenwetter | Recent developments in digital oscilloscopes[END_REF]. Its architecture and the principle of signal reconstruction are described in Fig. 1. An on-chip sample and hold (S/H) circuit directly probes the voltage along circuit interconnects and operates in subsampling conditions. The probe input impedance is large enough to ensure a non-invasive measurement. The signal acquisition is made over several occurrences of a reproducible phenomenon, and only one sample is taken at each repetition.

An external synchronization signal is used to both trigger off the on-chip event to characterize and activate the S/H cell. The sampling command is shifted from the synchronization signal by a delay cell. The time resolution of the reconstructed waveform is set by the minimum delay step, while its duration is set by the maximum delay produced by the delay cell. Samples are externally stored for waveform reconstruction. A very high virtual sample rate can be reached without severe constraints on hardware bandwidth.

Design of On-Chip Sensors to Monitor Electromagnetic Activity in

B. Asynchronous on-chip noise sensor

In some case as for EMI-induced noise, reconstruction of waveforms based on sequential equivalent-time is difficult. By definition, the EMI characteristics are unknown (amplitude, frequency, and waveform). Waveform reconstruction of the EMI-induced noise relies on acquisitions triggered on a repeatable external interference, which is possible only if the characteristics of the interference are known in advance. However this condition is not always ensured, so the signal is sampled at random instants and the waveform cannot be reconstructed. Nevertheless, even if the sampling cannot be synchronized with the noise, an asynchronous or random sampling can provide valuable information [START_REF] Shimazaki | A recipe for optimizing a timehistogram[END_REF] [START_REF] Declercq | Le signal aléatoire[END_REF]. The proposed sensor reuses the same architecture but operates in asynchronous sampling mode. The S/H cell and the output amplifier are kept but the delay cell is removed. A low frequency trigger commands the S/H cell to randomly subsample the input signal. The value stored at the S/H cell output is a random variable that constitutes the outcome of the instantaneous amplitude of input signal measurement. As explained on Fig. 2, this random acquisition allows the extraction of signal amplitude probability density function (PDF). The PDF provides the likelihood of the input signal having a given amplitude at any time. Whatever the input signal frequency, the PDF of the signal amplitude can be correctly extracted provided that the S/H cell the output amplifier does not distort or filter the sampled signal.

III. SENSOR DESIGN AND CHARACTERIZATION

A. Design of the on-chip noise sensor 1) General architecture Fig. 3 presents the general architecture of the on-chip noise sensor that is split in two parts: the probes and the core. Each of the 8 sensor probes is made of three main elements: an attenuator, a sample and hold cell that operates in sub sampling mode and an output amplifier. The attenuator and the S/H cell form a high impedance probe that ensures a low intrusive voltage measurement. The sensor core aims at selecting one of the 8 probes, generating the sampling command with a controlled delay (in order to reconstruct the signal in time domain) and at providing the output signal through a non-inverting CMOS amplifier. The sensor response is sensitive to voltage fluctuations coupled on its power supply and its substrate reference. The isolation of the sensor to external disturbances and to noise produced by the other blocks of the circuit is a critical requirement. Thus the output amplifier and sensor inputoutputs are supplied by an external and dedicated power supply. At board level, this power supply is separated and carefully decoupled. The S/H cell and the amplifier input stage are supplied by a quiet power supply provided by an internal built-in voltage regulator and powered by sensor power supply. To prevent from interference coupling on the sensor by the substrate, all the devices of the sensor are isolated from the P substrate by a buried N layer and dielectric-filled trenches on the sides.

2) Attenuator design and Sample-and-Hold cell

The attenuator and the S/H cells (fig. 4) are the most critical part of the sensor to ensure a large bandwidth, improve the linearity and reduce the voltage dependence. They are made of isolated low voltage transistors to prevent the impact of external disturbance and reach a bandwidth higher than 2GHz. The attenuator is based on a resistive voltage divider made of polysilicon resistor. Polysilicon capacitors C1 and C2 are added to compensate the parasitic capacitance of the resistors (C R1 and C R2 ) and maintain a flat frequency response. The input impedance of the attenuator is large enough to ensure a non invasive voltage measurement.

The S/H cell is composed of a transmission gate switch and a storage node (switch parasitic capacitors, amplifier input capacitor and an extra storage capacitor). The sizes of the transmission gate transistors are carefully chosen to optimize the bandwidth and reduce the voltage dependence of the onstate resistance. Moreover, a dummy transmission gate compensates the charge injection effect when the switch is turned off.

3) Sensor Delay Cell

The delay computed between nodes A and B (fig. 5) depends on two external analog voltages, "Vanalog" and Vrange, applied to control the delay cell. The delay law versus "Vanalog" features a good linearity. "Vrange" offers the possibility of tuning the delay range to be compatible with the signal to measure.

B. Characterization of the sensor

The sensor operation is affected by imperfections and mismatch in the implementation of its elements, which degrades the output responses. The output amplifier is not perfectly linear so the gain is not constant. Besides, errors in attenuator resistance values can change the gain of the sensor. Moreover, both the amplifier and the parasitic capacitance of the S/H cell produce an offset voltage. The input-output characteristic is measured to check the sensor linearity and then calibrate the sensor. It consists in applying a constant and known voltage on the sensor input and measuring the voltage amplitude of the output samples. A linear relation can be established between sensor output and input. From this relation, both static gain and offset can be extracted to compensate sensor imperfections.

However, this characterization and the measurement repeatability are disturbed by random errors due to intrinsic noise, interference coupling, and accuracy of equipments used to produce the reference voltage and measure the sensor output. In order to evaluate the measurement accuracy, for different input voltage values included in the sensor input voltage range, the output signal is sampled 10 times at various moments and the standard deviation of the output sample distribution is computed. The measurement uncertainty is estimated to 10mV and the time resolution is about 10 ps.

The sensor bandwidth is limited by the cut-off frequency of the equivalent RC filter composed by the attenuator and the S/H cell. The S/H cell transfer function is measured by sampling a sinusoidal signal of known amplitude with a varying frequency. The sensor bandwidth increases with the technology (2.5 GHz in 0.25 µm, 10 GHz in 90nm, 15 GHz in 65nm)

When measurements are conducted in a harsh environment, if a very high accuracy is required, sensor performance has to be evaluated to apply data post processing in order to compensate gain and offset drifts due to very high or very low temperature.

IV. EXPERIMENTS

A. Power integrity characterization

A test chip designed in Freescale CMOS 90 nm technology, which includes a digital core and synchronous on-chip sensors dedicated to power supply voltage fluctuations measurements, has been developed to characterize the evolution of PI vs. time [START_REF] Boyer | Effect of Aging on Power Integrity of Digital Integrated Circuits[END_REF]. The digital core structure is a basic 100-stage shift register, synchronized by a 40 MHz clock. In order to monitor the voltage drops on the power supply of the digital core, the on-chip voltage sensor is placed along the core power supply rail and synchronized on the core clock. It is able to measure the waveform of voltage bounce in time domain with a precise time resolution (up to 15 ps). Its analog bandwidth is equal to 10 GHz in this technology. Rapid droops appears at each clock switching. This event is linked to the rapid current demand from every gates and latches of the core. A damped oscillation with a pseudoperiod equal to 4.5 ns follows the first rapid current impulsion. It is linked to the anti-resonance produced by on-chip capacitor and package inductor. On-chip measurements to characterize power integrity have both interests: offering measurement points to non accessible nodes and suppressing the high frequency attenuation due to I/O pads and package. Comparison between the power supply voltage fluctuations measured by the on-chip sensor and simulated by a standard ICEM model (fig. 7) demonstrates that accurate measurements of on-chip noise is useful for model validation [START_REF] Ben Dhia | IC immunity modeling process validation using on-chip measurements[END_REF].

B. Characterization of propagation of conducted noise along a power supply rail

An asynchronous on-chip sensor has been implemented on the power supply rail of the digital core in a 0.25 µm SMARTMOS technology test chip from Freescale Semiconductor dedicated to the susceptibility characterization. The sensor aims at measuring the amplitude and the statistical distribution of voltage fluctuations induced by conducted EMI [START_REF] Ben Dhia | IC immunity modeling process validation using on-chip measurements[END_REF] injected by DPI on the digital core power supply. This information is critical to study on-chip induced noise propagation and its effects on ICs susceptibility.

Power supply voltage fluctuations are measured either externally with an oscilloscope active probe, or internally with the sensor. The oscilloscope and the active probe present large frequency bandwidths (2.5 GHz) to characterize accurately EMI voltage fluctuations up to 1 GHz. Results illustrated in Figure 8 show the susceptibility threshold of the digital core with the 0.25 V voltage fluctuation criterion applied on the power supply net, obtained with on-chip and off-chip measurements. The most critical frequency band regarding susceptibility issues is above 50MHz. When the EMI frequency is less than 50 MHz, both measurement methods provides the same susceptibility thresholds, i.e. for a given EMI amplitude, the power supply voltage fluctuation is the same off-chip and on-chip. However, above 50 MHz, inside and outside IC measurement methods give divergent results. An over-estimated immunity level with the external measurement is observed. The difference between both susceptibility thresholds reaches 23 dB. The origin of these differences is linked to the different measurement locations. Package and circuit filtering affect differently onchip and off-chip EMI-induced noise. The significant measurement discrepancies between on-chip and off-chip EMI-induced noise can lead to different evaluation of circuit susceptibility. This measurement shows that the on-chip noise sensor provides a more accurate measurement of EMIcoupling across the digital core above 50 MHz. Around 100 MHz, the amount of EMI-induced noise tends to be underestimated by off-chip measurement, while it is overestimated above 200 MHz. Moreover, the complex onchip propagation of conducted EMI can be understood more clearly by on-chip noise sensor measurement.

C. Characterization of digital clock integrity

The on-chip sensor (OCS) can be also used to observe the failures induced in analog or digital circuits by the coupling of electromagnetic disturbances on power supply and ground references. The following example illustrates the characterization of desynchronization issues of a digital circuit by the on-chip sensor. The voltage fluctuations induced on power supply and ground references leads to a degradation of the quality of clock signals, especially by the generation of jitter. If timing constraints on set-up and hold times are violated, failures may arise [START_REF] Chappel | EMI Effects and Timing Design for Increased Reliability in Digital Systems[END_REF].

An on-chip sensor has been placed within the clock tree of the digital core presented in IV.A to characterize its degradation when electromagnetic disturbances are conducted along the power supply network of the circuit. The conditions of time reconstruction of the clock are ensured since the sensor sampling command is synchronized on the clock signal. In order to capture the worst-case degradation of the clock, the electromagnetic disturbance generation is not synchronized on the clock signal and thus on the sensor sampling command. As a large number of clock waveforms are acquired (1500 waveforms) and superimposed, the sensor is equivalent to an oscilloscope with persistence display mode. The dependency of jitter to the electromagnetic disturbance frequency and amplitude can be characterized with the on-chip sensor, as shown in Fig. 10. The previous acquisition is repeated by changing the frequency and the amplitude of the harmonic disturbance. The jitter increases quasi linearly with the disturbance amplitude, but tends to decrease with disturbance frequency. The measured evolution of jitter can be compared to simulations to validate the modeling of jitter generation and digital failure prediction.

D. Near field probe Induced noise characterization

The on-chip sensor constitutes a powerful tool to characterize the physical interaction between a noise source and a circuit, and validate its modeling. The following part shows an original use of the on-chip sensor during near-field injection test. Near-field injection constitutes a promising method for electromagnetic attacks on cryptographic circuits [START_REF] Schmidt | Optical and EM Fault -Attacks on CRT-based RSA: Concrete Results[END_REF] or local fault injection for functional safety evaluation. The method consists in placing a miniature near-field probe in the vicinity of a die and injecting disturbance signals in the probe in order to induce a local voltage fluctuation along circuit interconnects and thus trigger a failure. The prediction of failure triggering relies on an accurate modeling of the physical interaction between the near-field probe and the circuit under test. For this purpose, a test chip has been designed core in a 0.25 µm SMARTMOS technology test chip from Freescale. The circuit contains 32 on-chip sensors placed on various lines and digital buses. The sensor measurements aim at proving that the injection is local, enough powerful to induce failure and validating the model of the coupling between the injection probe and the circuit under test.

The following example presents the measurements of voltage fluctuations induced along parallel silicon lines by a magnetic near-field probe. The lines are identical and separated by an increasing distance. The reference line is noted 0 µm. The on-chip sensor measurements are performed on this line and three other lines separated by 0.455, 120 and 320 µm respectively. The near-field probe is placed at 300 µm above the surface of the die and moved perpendicularly to the lines, as described in Fig. 11. The near-field probe is excited by a 1.4 GHz harmonic signal, which is synchronized on the on-chip sensor sampling command in order to ensure time reconstruction of voltage fluctuation profiles. Fig. 12 compares the evolution of the voltage fluctuation amplitude induced on the four lines according to the near-field probe position. Arrows indicate the probe positions for which the injection is optimal on each line. The induced voltage is optimal on a line when the probe is placed just above. If two lines are separated by a distance greater than the probe resolution, it is possible to distinguish which line is the more disturbed. This paper aims at demonstrating the positive contribution of on-chip measurements to characterize accurately and solve power integrity, simultaneous switching noise, ground bounce, crosstalk, near-field and substrate coupling issues… Several versions of this sensor have been developed over years in different technologies and for various experimental characterizations. Two versions of the sensor have been presented in the paper: synchronous and an asynchronous acquisition principle. The main advantages of this sensor are its small surface, its large bandwidth, its high linearity and robustness to electrical stress, at the price of a simple design.

Through the four different experiments, presented here, we demonstrate the benefit of on chip noise measurements.

For example, for circuit designers, using this type of onchip sensor are of great interest as it provides a precise characterization of noise propagation within the die, helps to identify the sensitive blocks, extract their actual susceptibility level and validate their models. On chip measurements could facilitate failure diagnosis and the modeling of complex parasitic couplings between separated blocks, such as substrate coupling, crosstalk… Prospective of this work will be an extension of the method towards on-line Diagnosis and Self-Healing by developing a self-adaptive technique based on on-chip sensor to design power-supply noise-immune ICs.

Fig. 1 .

 1 Fig. 1. Original synchronous on-chip noise sensor architecture and sequential equivalent-time sampling principle

Fig. 2 .

 2 Fig. 2. Asynchronous sampling of a signal and extraction of probability density function of the signal amplitude [12]

Fig. 3 .

 3 Fig. 3. On chip sensor general architecture

Fig. 4 .

 4 Fig. 4. Schematic of the attenuator and the sample and hold cell

Fig. 5 .

 5 Fig. 5. Schematic of the delay cell 4) Sensor Output Analog output signals are driven off the chip through a noninverting CMOS amplifier, externally stored and processed by a digital acquisition card. The output stage has been optimized to keep a constant gain up to few MHz, reduce parasitic offset and stability issues. The bandwidth of the output amplifier does not affect the sensor bandwidth since the amplifier does not process the sensor input signal, but the S/H output signal (constant value).

  Fig 6 presents the power supply voltage fluctuations produced by the digital core activity measured by the on-chip sensor. Positions of clock edges are indicated.

Fig. 6 .

 6 Fig. 6. Measurement of the power supply voltage bounce of the digital core

Fig. 7

 7 Fig. 7 Comparison between measurement and simulation of the digital core power supply voltage bounce

Fig. 8 .

 8 Fig. 8. Comparison of the susceptibility threshold between on-chip and offchip measurements.

Fig. 9

 9 presents the reconstructed time profile of the clock disturbed by a 500 MHz harmonic signal coupled on the power supply pin. Two types of degradation are measured. First, the logic levels '0' and '1' are affected by a sinusoidal voltage fluctuation with peak-to-peak amplitude equal to 450 mV. If the noise amplitude exceeds the switching threshold VTH of core flipflops, the logic state of the clock may change. The second degradation is the increase of jitter. It is extracted by measuring the distribution of the instants at which the clock crosses the threshold level VTH.

F=500Fig. 9 .

 9 Fig.9. Time profile reconstruction of the clock of a digital synchronous circuits disturbed by a 500 MHz harmonic signal[START_REF] Boyer | Characterizing Circuit Susceptibility with On-chip Sensors[END_REF]

Fig. 10 .

 10 Fig. 10. Measurement of clock jitter evolution vs. amplitude and frequency of a disturbance conducted on power supply [ref2]

Fig. 11 .

 11 Fig. 11. Position of test line structures and probe moving trajectory

Fig. 12 .

 12 Fig. 12. Evolution of the voltage induced on four parallel silicon lines according to the position of a magnetic near-field probe V. CONCLUSION