Nhat-Quang Nhan
email: nhat-quang.nhan@irisa.fr

Matthieu Gautier
email: matthieu.gautier@irisa.fr

Olivier Berder
email: olivier.berder@irisa.fr

Asynchronous MAC Protocol for Spectrum Agility in Wireless Body Area Sensor Networks

A Wireless Body Area Sensor Network (WBASN) is a special-purpose Wireless Sensor Network (WSN) that supports remote monitoring and entertainment applications. The energy consumption plays an important role in the design of this specific sensor network. Unfortunately, the performance of WBASNs decreases in high interference environments such as the Industrial, Scientific and Medical (ISM) band where wireless spectrums are getting crowded. In this paper, an energy-efficient Medium Access Control (MAC) protocol named C-RICER (Cognitive-Receiver Initiated CyclEd Receiver) is specifically designed for WBASN to cognitively work in high interference environment. C-RICER protocol adapts both transmission power and channel frequency to reduce the interferences and thus, the energy consumption. The protocol is simulated thanks to OMNET++ simulator. Simulation results show that, depending on the interference level, C-RICER is able to outperform the traditional RICER protocol in terms of energy consumption, packet delay, and network throughput.

I. INTRODUCTION

WBASNs promise many applications in health care, fitness and entertainments. Unlike WSN where sensor nodes are distributed in a wide area, those in WBASNs are interconnected within a human body and interact with different networks for remote monitoring. The amount of sensor nodes in a WBASN is limited and each sensor node has different sensing function. Hence, the network cannot execute data aggregation. Additionally, the typical network topology of a WBASN is centralized since only the center node acts as a data receiver to collect the sensing data from the other nodes. Therefore, it expects high reliability during data sensing and transmission. Moreover, as sensor nodes in WBASNs are distributed among a human body, they require small-size devices, fast data gathering and processing. However, smaller nodes also imply smaller batteries, which create a trade-off between the energy consumption and network performance of WBASNs [START_REF] Hanson | Body area sensor networks: Challenges and opportunities[END_REF].

Recently, the wireless spectrum in ISM bands is getting crowded. This causes the coexisting interference between the radio users in those open frequency bands including WBASNs. A network operating in high interference environment costs much of energy for the retransmission of data packets. Consequently, the disadvantages of WBASNs in high coexisting interference are high energy consumption, high packet delay, and low network throughput [START_REF] Sydanheimo | Performance issues on the wireless 2.4 GHz ISM band in a multisystem environment[END_REF].

This paper proposes applying the Cognitive Radio (CR) technique [START_REF] Mitola | Cognitive radio: making software radios more personal[END_REF] [START_REF] Haykin | Cognitive radio: Brain-empowered wireless communications[END_REF] to maintain the signal to noise ratio for WBASNs data exchange and therefore overcome the disadvantages of WBASNs in high coexisting interference environment. In this proposition, the WBASN considers to operate in the channel that has less interference among the frequency band when the interference of its current channel reaches a threshold that can cause harmful to the data transmission of the network. To this aim, the WBASN frequently scans for interference level of its current channel to early detect the interference, and only scans the whole frequency band when the switching decision is made. By dynamically scanning and switching among the channels, the WBASN can avoid the coexisting interference. Therefore, it can save energy, reduce packet drop and packet delay. The WSBAN will also include a mechanism that adapts its transmission power when short duration interferences occur.

Since these cognitive tasks are performed by a radio module which is directly controlled by the MAC layer, the design of a cognitive MAC protocol for WBASNs is considered in this paper. Recently, many MAC protocols have been proposed for WBASNs themselves [START_REF] Gopalan | A survey on power-efficient MAC protocols for wireless body area networks[END_REF]. However, the number of protocol that considers CR into this branch of WSNs is very limited [START_REF] Ali | A mac protocol for cognitive wireless body area sensor networking[END_REF]. In contrast, MAC protocols in CR networks have been designed for several applications [START_REF] De Domenico | A survey on MAC strategies for cognitive radio networks[END_REF], but no protocol was specifically designed for WBASNs. The contribution of this paper is a cognitive MAC protocol named C-RICER which takes into account WBASN specifications and includes both transmission power and channel frequency adaptation. The performance of C-RICER is compared to the traditional energy-efficient RICER3b protocol thanks to OMNET++ simulator.

This paper is organized as follows. In Section II, the main characteristics of WBASNs that affect the design of C-RICER are pointed out. Section III introduces the related MAC protocols. The algorithm and protocol of C-RICER are presented in Section IV. Simulation results are showed and analyzed in Section V. Finally, a conclusion is drawn in Section VI.

II. CONTEXT OF WBASN

The main characteristics of WBASNs could be listed in three folds: network topology, energy distribution and hardware support [START_REF] Latré | A survey on wireless body area networks[END_REF].

First, the typical network topology in WBASNs is the centralized topology. The center node is called coordinator and the other nodes are slaves. Most of times, the coordinator is the only receiver to collect data in a WBASN.

Second, the coordinator in a WBASN normally is cell phone or portable device which is easy to recharge or replace the battery. Therefore, the coordinator is the only node which is supposed to have less energy constraint compared with (the priority of energy saving is less than) the slaves. Last, sensor nodes in WBASNs are small-size to ensure the convenience for the patient. Hence, sensor nodes in WBASNs must follow the hardware limitation condition such that only one transceiver is equipped at each sensor (including the coordinator).

The study of C-RICER exploits the centralized network topology for the concept of interference detection. The energy for the cognitive task of C-RICER is mostly consumed at the coordinator. Last but not least, the spectrum agility function of C-RICER considers a very important characteristic of WBASN, where a single transceiver per sensor nodes is used. This single transceiver condition along with energy constraint makes the design of C-RICER in WBASN become more challenging and different from the traditional designs of cognitive MAC protocol [START_REF] De Domenico | A survey on MAC strategies for cognitive radio networks[END_REF].

III. RELATED WORKS

The main idea of C-RICER design is to include the cognitive task in an available energy-efficient MAC protocol in WSN. This section presents the importance of the MAC layer and points out the energy-efficient protocol that is suitable with the context of WBASNs.

In WSN, a great amount of energy is spent in the radio module which is controlled by the MAC layer. Therefore, a good MAC protocol plays a main role in decreasing the energy consumption of the whole network. Traditional MAC protocols can be divided into 2 families depending on how a node gains the medium access: contention-based and reservationbased. Due to the limit of energy and traffic, contention-based is more suitable for WSNs [START_REF] Bachir | MAC essentials for wireless sensor networks[END_REF]. In contention-based family, receiver-initiated protocols [START_REF] Lin | Power-efficient rendez-vous schemes for dense wireless sensor networks[END_REF] seem more suitable for the context of WBASNs. Using a receiver-initiated protocol, the energy is spent at the receiver more than at the transmitter. As mentioned in Section II, with the centralized network topology, the coordinator is the only receiver in a WBASN and has less energy constraint compared with the slaves. Therefore, using receiver-initiated protocols makes energy for data exchange of WBASNs mostly consumed at the coordinator that matches perfectly with the WBASNs context.

A well-known protocol in this family is Receiver Initiated CyclEd Receiver (RICER) protocol. Fig. 1 illustrates RICER3b protocol. In RICER3b, the Destination node with no data packet to transmit wakes up periodically and transmits a short wake up beacon indicating that it is awake. Then it monitors the channel for a response. If there is no response, the node goes back to sleep. On the other hand, a Source node with data to transmit stays awake, monitors the channel, and waits for a wake up beacon from the Destination.

The use of beacons in RICER3b is different from Zigbee. In Zigbee, the beacons are used to create the synchronization between the super-frames of the nodes. Then, the data is later transmitted using CSMA-CA algorithm based on an appropriate back-off timer. In RICER3b, after receiving wake up beacon, the Source node immediately sends back a buzz signal and starts transmitting data. By receiving this buzz signal, the Destination will stay awake to wait for data from the Source node.

RICER3b shows a great energy and delay efficiency among RICER family [START_REF] Lin | Receiver initiated rendezvous schemes for sensor networks[END_REF]. Therefore, RICER3b is utilized as the working algorithm of C-RICER in the low interference channel. Next section will present the algorithm of C-RICER in detail.

IV. C-RICER: A COGNITIVE MAC PROTOCOL

A. Protocol description

The general objective of C-RICER is to early detect the interference in its working channel. In C-RICER, channel sensing is periodically performed at the coordinator, the only node that has less energy constraint in the network. According to the detected level of interference, the WBASN can adaptively switch to the lowest interference channel to prevent the coexisting interference as shown in Fig. 2. The sensing and switching is continuously performed during the operation of C-RICER, not only at the initialization as for Zigbee.

In practice, the evolution of wireless channel interferences could be unpredictable. In some case, the interference appears and disappears for a short period. This phenomenon would make the whole network change its working channel frequently and cost much of energy for channel switching [START_REF] Haiming | An experimental study of the multiple channels and channel switching in wireless sensor networks[END_REF]. To overcome this, C-RICER includes also the use of power adaptation before channel adaptation is considered.

By using this twofold cognitive functions, C-RICER can maintain the performance of the WBASNs in high interference condition, especially in terms of energy consumption. The working mechanism of C-RICER contains two main tasks which are the data exchange task and the cognitive task. The data exchange task is used for data collection while the cognitive task is used to dynamically adapt both transmission power and channel according to the interference level. The mechanisms of those two tasks are presented in the next two subsections.

B. Network data exchange task

The data communication of C-RICER is based on RICER3b protocol with the Destination being the coordinator and the Source being the slave nodes. As shown in Fig. 1, its principle consists of five phases:

1) The coordinator wakes up and sends a wake up beacon.

2) The slave receives the wake up beacon and transmits a buzz signal to indicate the coordinator to wait for data. 3) The coordinator receives buzz and waits data from the slave. 4) The slave sends data and waits ACK from the coordinator. 5) The coordinator receives data and sends ACK to the slave.

C. Cognitive task

The cognitive task of C-RICER contains three main features which are: channel sensing, power adaptation and channel adaptation.

1) Channel sensing: Initially, the very important step for the cognitive task is the detection of interference. In this work, the Received Signal Strength Indicator (RSSI) is used to measure the interference level of a wireless channel. In the context of WBASNs, with the purpose of energy saving, the coordinator is the most suitable node in the network to perform the channel sensing because of several reasons.

First, the coordinator is the only node that has less energy constraint in the network. Focusing to exploit the energy at the coordinator instead of slaves can prolong the network lifetime.

Second, when applying the RICER3b scheme to the centralized topology of WBASNs, a communication is only established after the transmitter has successfully received a wake up beacon message from the receiver. The coordinator is considered as the only receiver in a WBASN. Therefore, when the coordinator does channel sensing, there is no com- munication in that WBASN. The received signal at that time comes only from the interference sources (if existing).

As shown in Fig. 3, because channel sensing and switching cost energy [START_REF] Haiming | An experimental study of the multiple channels and channel switching in wireless sensor networks[END_REF], the coordinator of C-RICER periodically senses for interference of only its current working channel instead of the whole frequency band to reduce the sensing energy. Only when the interference level of its current channel is greater than a threshold value, the coordinator will scan for the interference level of the remaining channels to build a full interference map of the frequency band. The period between two consecutive channel sensing activities is T scan cycle .

2) Power adaptation: As stated in the description of C-RICER, if only the channel adaptation feature is used, the phenomenon such that the interference only appears for a short duration can make the WBASN switches its channel frequently and cost much of energy for channel switching. For that reason, increasing the transmission power following an appropriate algorithm can not only enhance the signal to noise ratio but also reduce the retransmission in the network. Then, even if the transmitter energy consumption increases with the transmission power, the global energy consumption of WBASN can be reduced due to the reduction of the retransmission.

As shown in Fig. 4, the transceiver at each node is proposed to have two specific transmission powers (TxPowers) which are P 1 and P 2 (P 1 < P 2 ). Two interference threshold values T hres 1 and T hres 2 are introduced such that T hres 1 < T hres 2 . Where packet error rate will increase in proportional to the interference levels of T hres 1 and T hres 2 . The value of T hres 2 will be selected at a point such that the interference starting to effect the packet error rate (when P 2 is used), but still acceptable for the transmission of control packets.

After each channel sensing, if the interference level (RSSI) of current working channel is less than T hres 1 , the transceiver of each sensor node will work at its default transmission power P 1 . If the coordinator recognizes that the interference level of current channel is greater than T hres 1 but less than T hres 2 , it will increase TxPower to P 2 . After P 2 is used, the coordinator will adaptively change its scanning cycle by quickly coming back in T rescan cycle seconds to rescan the channel. After scanning, if the RSSI of current channel is reduced and less than T hres 1 , the network will go back to use P 1 . Conversely, if the RSSI level is still higher than T hres 1 , the coordinator scans the remaining channels to build the interference map, the whole network will switch to a new channel that has the lowest interference level among the map. The transmission power is also changed to the default value P 1 . This reduces the use of a high TxPower (P 2 ) for long time which costs energy.

Otherwise, if the RSSI of current working channel is directly greater than T hres 2 , the coordinator also scans the remaining channels to build the interference map, the whole WBASN will switch to the channel that has the lowest interference level in the map immediately without changing transmission power.

The coordinator utilizes the wake up beacon message to broadcast its TxPower information to the slaves. The wake up beacon message is added one dedicated bit which contains the information of TxPower level. The slaves will extract this bit from the wake up beacon message. If this bit is zero, P 1 is used. If not, P 2 is used.

3) Channel adaptation: Based on the interference map, the WBASN will decide to switch to a new channel when interference level of its current working channel is greater than T hres 2 or when the interference level of current channel is still high after rescanning. This subsection presents the algorithm used by the C-RICER coordinator to inform the channel switching information to the slaves.

As mentioned, working with a single transceiver makes the channel switching process of the WBASNs become more complicated compared with the traditional cognitive radio networks, where two transceivers are used at each node, one for data exchange and one for sharing the channel information among the sensors [START_REF] De Domenico | A survey on MAC strategies for cognitive radio networks[END_REF]. Moreover, the wake up mechanism of the slaves depends on their demand to send the data. Slaves with different sensing functions will wake up randomly and will not receive the switching information from the coordinator at the same time. Therefore, a checklist table is used at the coordinator to count for the slaves that successfully received the switching information. The channel switching algorithm is shown in Fig. 5.

At the coordinator, after the switching decision is made, the index of the channel that has the lowest RSSI among the interference map is attached to a message named Channel Switching Message. Right after that, the coordinator periodically broadcasts the Channel Switching Message to all slaves. After sending the Channel Switching Message, the coordinator

….

RSSI of Current Channel < Thres1

High interference Low interference ACK ….

Fig. 5. Channel switching algorithm of C-RICER protocol. waits for ACK message from slaves. With any successfully received ACK from a slave node, the Channel Switching Checklist Table of coordinator is filled at the position of that slave. When this checklist table is full, the coordinator will switch to the new channel.

If there is a packet to transmit, the slaves will wake up and wait for a wake up beacon message from the coordinator. Utilizing this characteristic, if a slave receives any channel switching message from coordinator during this time, it will send back the ACK message before switching to the new channel according to the channel information that is stored in channel switching message.

In some situation, the coordinator does not successfully receive the ACK message from a slave while that slave has already switched to the new channel. Therefore, the coordinator will also switch to the new channel even if its checklist table is not full after a period T wait checklist table . Moreover, a backup channel is also proposed for the slaves that lost the channel information in order to update the current working channel of the WBASN.

V. PERFORMANCE EVALUATION

The MiXiM wireless simulation framework on the foundation of OMNET++ simulator is used for the WBASN performance evaluation. At first, the original RICER3b protocol is re-simulated in MiXiM. Based on the RICER3b protocol, C-RICER has been implemented including new functions such as multichannel simulation, channel sensing, spectrum agility and dynamically changing of transmission power. In this work, a network topology with one coordinator, four slaves and one interference node is set up to simulate a WBASN with the existence of interference as shown in Fig. 6. To limit the simulation time, only two channels are simulated. The simulation parameters are shown in TABLE I. To demonstrate the features of the cognitive task, two simulation scenarios are set up.

A. Scenario 1: Spectrum agility performance

In this scenario, the power adaptation feature is not used to concentrate on the great reaction of channel adaptation feature in high interference environment. The WBASN starts its operation in the interfered channel. An important point in the implementation of a CR network is the setting of the threshold. In a WBASN, the threshold is set according to the network topology and we set it equal to twice the received RSSI from the farthest slave. Therefore, the threshold in this case is selected as 10 -4 mW. This value is reached when the transmission power of the interference node is 1 mW. This means that, the WBASN will immediately switch to a new channel when the transmission power of interference node is greater than or equal to 1 mW. Fig. 7 shows the energy per packet versus the transmission power of interference node. In this figure, the C-RICER pro- tocol is simulated and compared with the traditional RICER3b protocol. The energy consumption is computed for both situations such that the coordinator is included (whole BAN) or not included (slaves only). As shown in the figure, when the RSSI of current working channel increases but its value is less than the threshold (i.e. TxPower equals 1 mW), energy consumption of both protocols increases because the sensors frequently wake up for retransmission due to packet loss. The energy consumption of C-RICER at this time is more than RICER3b because of the periodic scanning for the interference level. However, when RSSI of current working channel reaches the threshold, the WBASN using C-RICER will switch to another non-interfered channel. Therefore, it can maintain the low energy per packet. In contrast, this metric of the WBASN using RICER3b rapidly rises up because it keeps working in the high interference channel. Fig. 8 expresses the average delay per packet of WBASN. From the figure, the delay per packet of RICER3b quickly raises up during the increasing of interference. Conversely, C-RICER can keep its packet delay metric steadily at a small value thanks to its cognitive mechanism.

B. Scenario 2: Power adaptation performance

This scenario simulates the adaptive changing of transmission power feature in a condition such that the interference only appears for a short period. To simulate that condition, the TxPower of the interference node is constantly set to 1.5 mW (the RSSI caused by this interference node is between T hres 1 and T hres 2 ). The interference node is set to work only 3 seconds after the first sensing of the coordinator. The initial working channel of whole WBASN and interference node is channel 1.

Fig. 9 shows the comparison between C-RICER without power adaptation feature (1 TxPower) and C-RICER with power adaptation (2 TxPowers) for this scenario. The horizontal axis represents the increasing of the rescan cycle T rescan cycle , while the vertical axis shows the energy con- sumption per successfully received packets of all slaves in the network. In C-RICER with 1 TxPower, after finishing the channel sensing, it will switch to the new channel. However, C-RICER with 2 TxPowers will change its TxPower to P 2 and rescan the band in the next T rescan cycle seconds. Therefore, when the T rescan cycle is less than the duration of interference (3 seconds), it means that the interference node is still working at the time the coordinator rescans the channel, then the WBASN will decide to switch its working channel. The energy consumption will be the total of the energy for channel switching and the energy for changing TxPower. For that reason, the energy per successfully received packets of C-RICER with 2 TxPowers is higher than that of C-RICER with 1 TxPower in this region.

However, when the T rescan cycle is greater than the duration of interference, the interference disappears at the time the coordinator rescans the band. Therefore, the WBASN will change its TxPower back to P 1 and continue to work in the current channel instead of switching the channel. Moreover, using the high transmission power during T rescan cycle increases the number of successfully received packets. For that reason, the energy per successfully received packets of C-RICER with 2 TxPowers is less than that of C-RICER with 1 TxPower in this region. It is also shown in this figure that the energy per packet of C-RICER with 2 TxPowers also raises up with the increasing of T rescan cycle .

In summary, the value of T rescan cycle should be long enough to cover a short duration or interference, but short enough to ensure the high transmission power is not used for too long to save the energy. As an extension for the future work, the duration of short interference could be predicted using machine learning method. Hence, T rescan cycle could be adaptively selected based on this value.

VI. CONCLUSION

Wireless technology plays an important role in the modern life. However, the densely distribution of personal wireless devices leads to a problem of crowded wireless spectrum in the open frequency bands. The performance of WBASNs then decreases in those bands because of the coexisting interferences. This paper proposes C-RICER , a protocol with cognitive functions to avoid the interference and enhance the performance of WBASNs. The simulation results show that the C-RICER protocol is able to outperform RICER3b under high interference environment, especially in terms of energy consumption.

Recently, in February 2013, IEEE Standards Association has putted an adjustment to the IEEE 802.15.4j standard in terms of physical layer extension to support WBASN services operating in the 2360-2400 MHz band for medical applications [START_REF]Alternative Physical Layer Extension to Support Medical Body Area Network (MBAN) Services Operating in the 2360 to 2400 MHz Band[END_REF]. The proposed C-RICER MAC protocol could be also used by WBASNs to dynamically work in this frequency band. C-RICER can detect and avoid the coexistence with primary users of this band thanks to its cognitive function.

Fig. 1 .

 1 Fig. 1. RICER3b scheme.

Fig. 2 .

 2 Fig. 2. Overview of C-RICER in WBASN.

Fig. 3 .

 3 Fig. 3. Channel sensing strategy.

Fig. 4 .

 4 Fig. 4. Power adaptation strategy.

Fig. 6 .

 6 Fig. 6. Network topology.

  cycle, 2 channels, four slaves and one coordinator TxPower of Interference node (mW) Energy per packet (mJ/packet) RICER3b whole BAN RICER3b slaves only C-RICER whole BAN C-RICER slaves only

Fig. 7 .

 7 Fig. 7. Energy consumption per successfully received packets vs. interference power.

Fig. 8 .

 8 Fig. 8. Average delay per successfully received packet of WBASN.

Fig. 9 .

 9 Fig. 9. The adaptive changing of TxPower feature evaluation.

Coordinator Slave n Send Receive RSSI of Current Channel > Thres1 Channel Switching Message SWITCH TO NEW CHANNEL

	Slave 1
		SCAN_BAND
				…
	White space:	1	2
		Channel switching checklist table:  Slave 1	…	 Slave n
			n slave nodes


Stephane Ganda
email: ganda-stephane.ouedraogo@irisa.fr

Matthieu Ouedraogo

Olivier Gautier
email: matthieu.gautier@irisa.fr

Sentieys

Frame-based Modeling for Automatic Synthesis of FPGA-Software Defined Radio

Software Defined Radio (SDR) is now becoming a ubiquitous concept to describe and implement Physical Layers (PHYs) of wireless systems. Moreover, even though the FPGA is expected to play a key role in SDR, describing a PHY at the Register-Transfer-Level (RTL) requires tremendous efforts. This paper introduces a novel methodology to rapidly implement PHYs for SDR. The work relies upon High-Level Synthesis tools and dataflow modeling in order to infer an efficient RTL control unit for the application. The proposed software-based over-layer partly handles the complexity of programming an FPGA and integrates reconfigurable features. It consists essentially of a Domain-Specific Language (DSL) combined to a DSL-Compiler. An IEEE 802.11a transceiver has been explored via this approach in order to show the flexibility features.

I. INTRODUCTION

Software Defined Radio (SDR) is a concept that has come to maturity [START_REF] Dr | Software radios: Survey, Critical Evaluation and Future Directions[END_REF]. According to the wireless innovation forum [START_REF]Wireless Innovation Forum, Driving the future of radio communications and systems worldwide[END_REF], an SDR is a radio in which some of the physical layer (PHY) functions are software defined. Indeed, these radios are mainly characterized by their ability to support different waveforms. Different attempts to standardized SDR have led to two major works, namely the Software Communication Architecture (SCA) [START_REF] Bard | Software defined radio: the software communication architecture[END_REF] and the Space Telecommunication Radio System (STRS) [START_REF] Reinhart | Space Telecommunications Radio System (STRS) architecture standard[END_REF]. These two frameworks provide the building environment for SDR, however a need for tools to design the PHY is still pointed out. The GNURADIO [START_REF]The free and open software radio ecosystem[END_REF] and the SDRPHY [START_REF] Grayver | SDRPHY -XML Description for SDR Physiczl Layer[END_REF] projects are examples of software frameworks. They both use a block-based model of the PHY applications, namely a dataflow program, to implement such PHYs.

The dataflow Model of Computation (MoC) [START_REF] Edwards | Language for digital embedded systems[END_REF] has encountered a lot of success in the real-time signal processing domain. It describes an application as a set of functional blocks that run concurrently and communicate through FIFO channels. This view of the MoC represents the processing unit of the application, which is usually associated to a control unit. This associated control unit can be modeled as a Finite State Machine (FSM), which provides a behavioral description of the application. In most of the SDR frameworks, the functional description of the blocks are written using highlevel languages such as C/C++ and the application runs over Digital Signal Processors (DSP) based platforms. Blocks can be also written at the register level (RTL) level by using a Hardware Description Language (HDL) and run over Field Programmable Gate Array (FPGA), however this description differs from the initial idea of SDR where the blocks are software defined.

In this paper, a novel software over-layer to specify a PHY and implement it over FPGA platforms is proposed. Indeed, the nascent radio protocols are expected to meet a certain data throughput and the FPGAs include specialized resources such as DSP slices, Block-RAM (BRAM) and clocking resources, which enable achieving such data throughput requirements. The proposed design flow relies upon High Level Synthesis (HLS) tools [START_REF] Edwards | The Challenges of Synthesizing Hardware from C-Like Languages[END_REF] that provide a mean to compile an abstracted description (C/C++) of an application down to its RTL description. To enable the specification of a multi-rate dataflow application running on FPGA, the main contributions describes in the paper are:

• a Domain Specific Language (DSL) [START_REF] Fowler | Domain-Specific Languages[END_REF] which provides the primitives to rapidly prototype the dataflow applications meant for SDR. The DSL is combined to HLS tools to take advantage of their features. • a data frame-based algorithm to automatically generate an appropriate control unit capable of handling the reconfiguration issues of a multi-rate complex dataflow specification. The paper is structured as follows. In Section II a discussion over the chosen dataflow model of computation is held, together with its requirements in terms of control. Section III details the frame-based algorithm to generate the control structure given a high level specification of a dataflow application. Section IV discusses an example through the specification of the IEEE 802.11a standard with the proposed framework. Finally a conclusion is drawn while future work is discussed.

II. IMPLEMENTING DATAFLOW MODELS FOR SDR

A. The Dataflow MoC and Control Modeling for SDR

A MoC is an abstract specification of how the computation is managed. Radio link applications can be modeled using the Synchronous Data Flow (SDF) MoC [START_REF] Lee | Synchronous data flow[END_REF]. This MoC represents a program as a directed graph in which each node, communicating via channels, consumes or produces a predetermined and fixed number of data (tokens) per invocation. An example of SDF signal flow graph is given in Fig. 1, where FB1, FB2, FB3 and FB4 denote functional blocks (FBs) communicating through channels. An SDF implementation requires a static scheduling and SDF was employed in various embedded systems design tools such as the development environments derived from the Ptolemy project [START_REF] Eker | Taming heterogeneity -the Ptolemy approach[END_REF]. A typical SDF-based dataflow architecture is given in Fig. 2 where the FBs depict the computing cores. Fig. 2 can be interpreted as an implementation of the graph in Fig. 1. At the inputs and outputs of the FBs, FIFOs are interfaced to control the streaming flow. An important element that is making the waveform structure consistent is the control logic, which purpose is to orchestrate the data routing and computing in graph. Indeed, it provides the system with specific signals that are used to change the state of the system. This generic overview of the dataflow architecture clearly shows that, for efficiency purposes, enhancements can be performed at three distinct levels, namely the FBs, the communication infrastructure and finally the control unit. In this work, the FBs and the communication infrastructure are synthesized using HLS tools/languages as it will later be explained. An emphasis is given on the controller required to schedule the resulting waveform running on an FPGA device in context of multirate SDR.

On a running platform such as FPGA on which each function is mapped to dedicated resources, an FSM is a good candidate to implement a control unit. Its main task is to handle consistently the traversal of data through the graph. Thus, depending on the current state and the conditions on the inputs and outputs channels, the controller activates or deactivates a set of FBs. This approach is only valid when the properties of the graph remain unchanged. The FSM in this case appears to be relatively simple to implement. In the context of SDR, some part of the graph could be reconfigured at run-time. For instance, most of modern standards [START_REF]IEEE Standard for Information Technology, Wireless Medium Acess Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs)[END_REF] [START_REF]Supplement to IEEE Standard for Information Technology, Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications[END_REF] implement Adaptive Coding and Modulation (ACM) technique in order to enhance the bandwidth efficiency. ACM consists in adapting the modulation and coding schemes according to the environment. Thus, each part of the data frame may be modulated or coded differently. On the receiver side, data should be decoded with the appropriate demodulation algorithm so that the decoding remains consistent. Modern waveforms require a controller that can switch between configurations at run-time.

This example further illustrates the fact that the control requirements are more complex in the context of SDR. Changing some parts of the waveform (i.e. the dataflow) at run-time is quite complex. This complexity in terms of processing and control in modern PHYs led the designers to re-think the overall designing process. The HLS partly addressed these issues by enabling to go straight from specifications to the implementation. Nonetheless, issues relative to control remain while considering HLS.

B. HLS for Rapid Prototyping

A typical FPGA-based development process of a dataflow application is twofold. The first part consists in specifying the system in an abstracted way using High-Level Languages (HLL) such as C/C++ or Matlab. This representation highlights the sub-elements of the system and their interactions. It often considers streaming data as floating-point data types that are refined to fixed points when it comes to implementation. The second part consists in a hardware description of the system. Hardware Description Languages (HDL) such as Verilog or VHDL are used to implement the specification previously written in HLL. The implementation gives a functional description of the system and takes account of the computing and communication resources available. A mainstream trend is to merge these two designing steps into a single one. The HLS bridges the gap between the specification and the implementation. It takes as an input a function specification written in a HLL and generates its RTL description for a specific target platform (e.g. FPGA). The existing HLS tools emphasize on the functional aspects of the application and they propose several design optimization techniques to fulfill the performance requirements without shortcomings.

In the context of FPGA-based SDR, HLS significantly helps with rapid prototyping. As aforementioned, it shortens the design time and improves the overall productivity. Thus, given the requirements in terms of flexibility of SDR and the capabilities of HLS, integrating HLS within an SDR-PHY design flow can yield the development process. A preceding study [START_REF] Bahtnagar | Sentieys An FPGA Software Defined Radio with a High-Level Synthesis Flow[END_REF] consisted in showing the gain for an HLS-based design flow. To this end, a software-based over-layer is proposed to abstract the SDR-PHY designing process and anticipate on SDR requirements. In our design flow, we will consider FBs being specified in HLL and synthesized by HLS tools.

III. A FRAME-BASED DATAFLOW MODELING

Data framing is imposed by most of the modern radio protocols and often specified accurately by the wireless standards [START_REF]IEEE Standard for Information Technology, Wireless Medium Acess Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs)[END_REF] [START_REF]Supplement to IEEE Standard for Information Technology, Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications[END_REF]. A frame is composed of fields, conveying various type of information. This structure enables a consistent data coding and decoding while ensuring the inter-operability of software and hardware solutions released in the market. By considering a unique data frame structure, the designers are given the freedom to implement the solutions to process the frame. The resulting datapath and control are deeply associated to structure of the data frame.

A. High Level Modeling of FPGA-SDR Waveform

The growth of the platforms complexity exhibits the limitations of the current programming languages. Furthermore, these platforms evolve rapidly while the application codes are still written and maintained manually. A mainstream approach to handle such platform evolution is the Model-Driven Engineering (MDE) [START_REF] Douglas | Model-Driven Engineering[END_REF]. It comprises both Domain-Specific Languages (DSL), which formalize the application structure behavior and requirements in a declarative way, and transformation engines and generators to generate multiple artifacts such as source code. The MDE approach ensures a "correct-by-construction" development of the final product.

One of the interests of working with models is the possibility to automate different steps throughout the development process. The principal advantage is the automatic code generation achieved from these models. In addition, they can gradually evolve to cover a larger spectrum of capabilities. The models also give a mean to infer diverse information, such as the control, and shorten considerably the system development time. We have defined a DSL which provides the primitives to model a dataflow waveform. This language is featured with the HLS tools and is detailed later in this paper. It combines both a data-path and data-frame specification to build the processing and the control units for an SDR waveform. Methodologies for automatic hardware synthesis from data frame specifications are not often discussed in the literature. An example is given in [START_REF] Grayver | SDRPHY -XML Description for SDR Physiczl Layer[END_REF], where an XML-based SDR waveform specification flow including frame definition is discussed. It is called SDRPHY and is a proposal for SDR physical layers specification using XML as an entry point by contrast to our approach based on a brand new DSL. XML hardware-specific interpreters are used to convert the XML physical layer description for a specific running platform. Thus, this approach focuses more on the portability of the SDR waveform over various running platforms and the HLS features are not included.

Our solution is quite similar while relying on a DSL. It is also specific to FPGA-based SDR. An algorithm is proposed to infer a control unit from a DSL specification as discussed in the next section.

B. Frame-based SDR Waveform Control Description

A frame is generally considered at distinct levels, namely the bit level, the symbol level, and optionally the sample level. It is mainly characterized by its duration, its source (e.g. an FB) and is composed out of fields. The nature of the data conveyed by each field can be either specific information (e.g. modulation schemes or coding rate), synchronization information (e.g. preamble) or useful data (e.g. data payload). An OFDM frame is given as an example in Fig. 3 where each field is characterized by its duration and the type of transported data.

One can notice that the structure of a frame gathers exploitable information (duration, source, data properties) that can be leveraged to achieve better control performance. The duration of each field helps generating the read and write clock signals during the appropriate slot of time. The oversampling or down sampling mechanisms imply some rate changes that are tracked across the graph. To manage the block-level communication, FIFOs are interfaced between two consecutive blocks. In our approach, these FIFOs are inferred from the specifications. They are implemented by HLS tools by using the FPGA memory resources. In addition, each block within the graph is meant to perform a given action on a specific set of data. Once this action terminates, the blocks may no longer be required then disabled. For instance, some functional blocks may address only synchronization and some others address only data decoding. It is then convenient to control the activation and deactivation of each FB.

The inferred control unit is an FSM working in both transmitter (TX) and receiver (RX) modes. Its overall structure is given in Fig. 4, where dash lines denote parallel states. In TX mode, the controller first waits for a start signal from the upper layers indicating that a data frame is available. In this mode, the controller consists of two major states called super-states. First is the IDLE super-state corresponding to the inactive state of the transmitter. After detecting a start from the MAC layer for example, it transitions from the IDLE to the FRAMING super-state where data coding is sketched. Generally speaking, dataflow transmitters are feed-forward architectures hence less complex to implement as compared to their associated receiver. The FRAMING super-state is declined into three parallel sub-states namely, the CODING state, the INSERT state and finally the BL-RECONF state. In the CODING, typical mapping operations together with filtering operations are performed. The output samples are fed to the DACs (Digital to Analog Converter) prior to carrier frequency modulation. In parallel to the CODING state, an INSERT state is active. This state manages the insertion of specific data in the frame, both at the time and spectral levels. Considering the standards using an OFDM modulation, they require to inject pilot symbols from time to time within the spectrum for coherent detection. Moreover, a data frame often includes constant fields (e.g. preamble) that remain the same in all the transmitted frames. For the purpose of reducing the overall computation, such fields are one-time computed and inserted (at run-time) at the sample level in the frame before DACs. The BL-RECONF state handles the block-level (fine-grained) reconfiguration of the transmitter. As aforementioned, modern standards require certain blocks to be adaptive (ACM) i.e. changing their properties on-the-fly. One approach consists in hard-coding all the configuration of the block once, then using software controlled switch to select the desired configuration at run-time. A second approach is to reconfigure the block when a given configuration is desired. It is a suitable approach which fits the best to the paradigm of SDR and requires indeed partial reconfiguration capabilities.

In RX mode, the FSM is composed of three super-states. An IDLE state, as in TX mode, denotes the inactive state of the receiver. In this state, the receiver monitors the environment seeking for an incoming signal. Once a signal is detected through an RSSI (Received Signal Strength Indicator) for instance, the receiver transitions from the IDLE state to the PRE-SOF state. The PRE-SOF state consists essentially of synchronization tasks as imposed by most of the standards. Once the system enters the PRE-SOF state, a set of synchronization elements has to be detected and computed within a certain delay. If not, the system returns in the IDLE state. These synchronization elements detection and computation are associated to an event that is called Start-Of-Frame (SOF). An SOF detection makes the system transition from PRE-SOF to POST-SOF where a coherent data decoding is sketched. The POST-SOF state is declined into three parallel substates namely, the DECODING state where most of the signal processing is required, the SYNC-TRACK state in which the system keep on tracking synchronization elements and finally the BL-RECONF state to handle the run-time block-level reconfiguration as in TX mode.

In each of the states, a set of dataflow computation is intended. In the context of FPGA, the data-path is once mapped to dedicated resources and ready to operate as soon as the FPGA is powered on. One of the roles of the controller is to distribute the clock signal to activate or deactivate the FBs when required. We leverage the properties of the data frame together with the intrinsic structure of the data-path (dataflow) to build the control unit. First, a data frame F is as a collection of fields i.e.:

F = ∪ N i=1 F i , (1)
where F i denotes the i-th field. Each field F i is characterized by its duration T i its constant or variable nature State of its transported data P ayload:

F i = {T i , State, P ayload}. ( 2
)
The duration T F of the overall frame F is computed as:

T F = N i=1 T i . ( 3
)
The datapath, on both the transmitter and receiver side, is a set of interconnected FBs as illustrated in Figure 2. They are characterized by their latency (L), throughput (T P ), input and output data rates (f in and f out ). For each block, the inputs and outputs rate are known and they can be managed using enable signals. Moreover, each block is activated or deactivated on a per-field basis since computation happens to be specific to a given field. Thus, let F B j be the j-th FB within the dataflow graph:

F B j = {f inj , f outj , L j , T P j }. ( 4
)
Assuming that F B j processes the field F i of duration T i at an input rate of f in and output rate of f out , the block requires being enable a number to time equals to:

k i,j = T i f in . (5)
Thus, each block is affected a time slot to process a field when this field is traversing the graph. They are then activated depending on the ongoing field. To achieve this, the controller decides a starting moment for each block in the graph. This starting time is computed by considering both the graph structure and the properties (latency and throughput) of each block composing it. Indeed, each state is associated to a distinct data-path and once the system enters a state, the processing starts with a specific block that is tagged as a reference block. The activation moment of the remaining blocks in the graph is then estimated based on the latency and the throughput of the blocks preceding them. Blocking reads and blocking writes are also implemented since the blocks are interfaced with FIFOs. This algorithm has been integrated into an SDR PHYs design flow. The flow is implemented as a DSL which addresses rapid prototyping of the PHY. It relies on the principle of the MDE and its details are discussed in the next section.

IV. IMPLEMENTATION OF THE CONCEPT FOR AN SDR DESIGN FLOW

In this section, a design flow that was defined to enable rapid prototyping of FPGA-based SDR physical layers is presented. In addition, a practical example of a radio protocol specification is depicted as proof of concept. This flow relies on a DSL which enables to specify a data frame, its attributes and a data-path. A DSL-Compiler is provided to both infer the control unit of the physical layer and operate the connection between the instantiated blocks. The instantiated FBs are compiled down to RTL with HLS tools that are integrated to the flow.

A. A Dedicated DSL to Model SDR-PHY

The idea to define a new language instead of using an existing language aims first at making the most of the expressiveness given by a specialized language. A DSL can be either internal or external [START_REF] Fowler | Domain-Specific Languages[END_REF]. An internal DSL is a language that is nested within a host language. The host language is generally a well-known General Purpose Language (GPP) such as C++ or Java. External DSLs in opposition enable to explicit any domain by defining a new syntax and an appropriate grammar. They require a lot more efforts to be implemented but they remain much less constrained in comparison to internal DSLs.

An external DSL has been defined to model the PHYs meant for SDR applications running on FPGA devices. The DSL provides the primitives to describe on one side the data frame and on the other side the data-path by considering the data frame attributes. A frame is considered as a collection of fields that are destined to be processed independently by the FBs of the processing unit. A typical specification with the DSL starts by including FBs HLS-based libraries. After that, a set of data rates are defined in order to model the multi-rate constraints within the graph. These definitions are used to impose reading and writing rates to the different blocks. Then, each field of the data frame is described independently by highlighting some of their features like duration or eventually data redundancies for optimization purposes. Constant fields are stamped with the key word #fieldC. They are once computed, in contrast to variable fields that are specified with the key word #fieldV and modulated through the data-path. In RX mode, since the system requires a detection of an SOF to switch from the PRE-SOF to the POST-SOF state in order to further process the data, one of the fields is designated as an SOF. This field is typically a preamble that is appended for synchronization purposes.

The data-path is described by using a set of heterogeneous FBs that are sourced from HLS-based libraries. The instantiation of each block requires specifying both the inputs and the outputs data rates using the rates defined at the beginning of the specification. The idea is to provide a rich description for each block in order to optimally synthesize the corresponding RTL. The HLS tool intended for each block is specified at that time by using the annotations #catapultc or #vivadohls. Indeed, an important development work has been carried out to implement multiple FBs that are gathered in libraries. So far, those blocks are synthesizable either by CatapultC from Calypto or by Vivado-HLS from Xilinx. An ongoing work aims at including native RTL FBs, by using the annotation #rtl. Furthermore, real-time constraints for each block are taken into account. These constraints are the latency, the throughput or the clocking requirements of the block that are further used to implement the control unit of the waveform. The provided DSL-Compiler generates, for each FB, a .tcl script which is used as an interface with the intended HLS tools to synthesize the RTL solution. The compiler is also charged of the consistent gluing of the generated RTL solutions by using RTL wrappers. It also performs some type checking and many other verification in order to ensure consistency in the final waveform.

As discussed in Section III-B both the frame and the datapath are used to infer the control unit and the DSL provides an environment to describe a rich specification of these two aspects of a waveform. An important feature that was added in the DSL is to clearly mention, for each FB, a list of the fields that it is intended to process and their respective source (i.e. another FB) by using the key words processing and from respectively. These information make it possible to track each field within the graph hence activating the FB when required. The DSL-Compiler parses these information and generates the controller.

Another feature that is making this flow specific to SDR is the fact enabling the reconfiguration of FB at run-time. Indeed, all the FBs that are subject to run-time reconfiguration are annotated with the key word adaptive. In practice, they are defined into Partial Reconfiguration Region on the FPGA and interfaced with larger memory resources in order to store the incoming data stream while operating the reconfiguration. Once the system enters the BL-RECONF state, all the blocks that are not impacted by the reconfiguration are held active by the controller while the rest of the graph is being stalled. As soon as the reconfiguration terminates the data coding or decoding is performed normally.

B. A Case Study through the IEEE 802.11a PHY

Remembering the structure of the frame illustrated in Fig. 3, a piece of prototype of an IEEE 802.11a PHY is presented. In Fig. 5, a piece of DSL-based description of an IEEE 802.11a [START_REF]Supplement to IEEE Standard for Information Technology, Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications[END_REF] source code is provided. Constant fields are sourced from local files and mapped to memories. They are multiplexed to the rest of the frame at run-time when required. Variable fields are sourced from upper layers or different FBs. The details of the DSL-Compiler are not in the scope of this paper. Its main task is to parse the DSL and then to infer the desired control unit. The SHORTPB for instance is appended for synchronization purpose. It is a constant field that remains the same for any data frame. Moreover, this field is computed only by the synchronization FBs. It has an overall duration of 8 microseconds that sets a deadline for the FBs intended to process this field. The DATA field conveys the data payload from the upper layer. Both its content and its size vary on a per-frame basis. The exact size of the field is embedded in the frame within its HEADER field. Only a range is provided by the standard and most of the solutions usually consider a fixed size not to bother with the control requirements. The inferred control unit handles this issue by generating a stop signal after the exact DATA field time has elapsed. A complex (consisting of in phase and quarter-phase channel) is built out of the fields and the SHORTPB is designated as Start-Of-Frame.

An adaptive Fast Fourier Transform (FFT) block, as the main block of the IEEE 802.11a PHY, specification is also given in Fig. 5. It corresponds to a set of FFT blocks varying by the size of the FFT. Partial reconfiguration technique is used to configure the desired FFT at run-time. In order to comply with the requirements of partial reconfiguration, i.e. non varying I/O set between two configurations, we have made the FFT input and output non vector type. The samples are then reordered inside the FFT for a given FFT size. Fig. 6 shows a design space exploration for a 256-point FFT, performed with CatapultC in order to obtain different solutions of the same design. The solutions were synthesized for a Virtex 6 FPGA platform by using the Xilinx ISE tool suit and the results are collected after place and route. It is important to mention that as the FPGAs are getting larger, i.e. including more resources; it is now possible to program complex waveforms into a single one. This exploration shows indeed an increasing number of slices depending on the data rate. Hence suitable solution can be chosen for the final design.

V. CONCLUSION SDR is an outstanding concept that requires to be further developed. As the FPGA technology evolves, it turns out to be a good candidate for SDR solutions. The MDE approach is a promising alternative toward the optimization of the development process of an embedded system in general. Our contribution is essentially to bring together both SDR and MDE concepts into an SDR-PHY design flow, with an emphasis on control aspects. The flow is featured with the nascent HLS tools and implements several PHY artifacts from the specifications. This combination enables to achieve good design performance, thanks to HLS tools, and to significantly shorten the required development time.

Fig. 1 .

 1 Fig. 1. SDF signal flow graph example.

Fig. 2 .

 2 Fig. 2. Typical SDF dataflow RTL architecture.

Fig. 3 .

 3 Fig. 3. IEEE 802.11a data frame.

Fig. 4 .

 4 Fig. 4. Transceiver FSM.

Fig. 5 .

 5 Fig. 5. DSL-based IEEE 802.11a PHY.

Fig. 6 .

 6 Fig. 6. Resource estimation versus Datarate of the IEEE 802.11 receiver.