Ultra-Low Power RFIC Solutions for Wireless Sensor Networks iii

Abstract

[EN] Since their emergence, Wireless Sensor Networks (WSN) have been growing continually becoming a key player in many applications such as military tracking, remote monitoring, bio-sensing and home automation. These networks are based on IEEE 802. 15.4 standard which is dedicated to low rate wireless personal area networks (LR-WPANs) in the unlicensed radio band (868 MHz/915 MHz/2.4 GHz). Low power consumption, low cost of implementation and high level of integration are the main challenges of these systems. As radio frequency transceiver is one of the most power hungry block in wireless sensor node, power consumption of radio frequency front-end (RFFE) must be reduced. To deal with, several approaches are possible, either at circuit level by investigating operating modes of transistors and merging functionalities or at system level by searching novel demodulating architectures. This thesis explores the specific requirements and challenges for the design of a very-low power 2.4 GHz down conversion mixer operating in moderate inversion region and consuming 330 µW. A second circuit merging the local oscillator and the mixer was designed and implemented in 65 nm CMOS technology. The self-oscillating mixer (SOM) operates at a radio frequency of 2.4 GHz and consumes 600 µW from a 1 V supply. Finally, a compact demodulator implemented in 65 nm CMOS technology was proposed. It uses a novel architecture to demodulate all analog modulations while consuming just 120 µW from a 0.5 V supply and achieving a sensitivity less than -30 dBm in the case of AM modulation.

[FR] Depuis leur apparition, les réseaux de capteurs sans fil (WSN) n'ont cessé de se développer pour devenir un acteur clé dans de nombreuses applications telles que le suivi militaires, la surveillance à distance, la bio-détection ou la domotique. Ces réseaux basés principalement sur la norme IEEE 802. 15

Acknowledgment

The success of this research work would not have been possible without the support and assistance of many other individuals. First, I would like to thank my advisors, Professor Yann Deval and Associate Professor Thierry Taris, for their support and guidance throughout my time in IMS laboratory. Their vision and scientific recommendations have been both inspiring and challenging. I also thank Professor Corinne Berland and Professor Christian Enz for reading this thesis and providing helpful feedback.

I extend my deep gratitude to all members of IC design team for their valuable assistance. I also thank the former team leader Professor Jean-Baptiste Begueret for his constant support and availability.

The IMS laboratory is fortunate to employ a talented and dedicated staff. Special thanks is due to Simone Dang Van, whose tireless efforts to facilitate administrative tasks. Patrick Villesuzanne and Olivier Mazouffre keep the computer systems and tools running smoothly and play an integral role in the successful fabrication of chips.

My co-workers of the last 3 years, have been a constant source of helpful discussion and distractions. Special thanks to Paolo Lucchi, Sophie Drean, Yoann Abiven, Quentin Beraud Sudreau, Adrien Tuffery, Nejdat Demirel with whom I have shared valuable discussions and many cups of coffee.

Many thanks to the German community with which I was connected the last period of the thesis. I have shared interesting discussions, sometimes philosophical, with Mario Weiß. He was always up for practicing sport and going out. I also thank my roommate Janina Reents for positive changes she has brought with her, this was really helpful.

Vielen Dank an alle. I cannot forget all the people I met in Bordeaux and with whom I have shared many things. Thank you Brahim, Sami, Damien, Thalia, Tugdual, Thomas, Henri and Laetitia for supporting me.

Finally, I want to dedicate this modest work to my home country, Tunisia, to all the people who started the revolution at the end of 2010 and who continue to struggle for a better future. Living this event while being far away was really hard. Special thanks to all my friends there for their constant and helpful support.

Last but of course not least, I thank my parents and my family for their permanent support and especially for their sacrifices which has allowed me to continue my studies. I am really grateful to them. I dedicate this thesis to my dear father that I would have loved to share this moment with him but unfortunately life decided otherwise. He taught me how to stay strong in tough times, I love you Dad.

Chapter 1 Introduction

In recent years, a trend toward a world in which people will be surrounded by networked devices that are sensitive and adaptive to their needs can be foreseen. This trend has been expressed in a vision called Ambient Intelligence (AmI). It is possible to partition this world into three different classes of devices called "Watt nodes", "milli-Watt nodes" and "micro-Watt nodes" [8].

The "Watt nodes" and the "milli-Watt nodes" demand a further improvement in technology scaling to meet the low-power target. In contrast, the design of a "micro-Watt" node requires meeting the limit of miniaturization, cost reduction and power consumption. Therefore, the complexity of this task is not in the number of transistors but in the capability to optimally combine technologies, circuit and protocol innovation to obtain the utmost simplicity of the wireless node. One implementation of these "micro-Watt nodes" can be achieved through wireless sensor networks (WSN). Since their emergence, they keep on growing up, becoming a key player in most industrial applications.

Thanks to their ease of implementation and very low cost, these networks are extensively used in wireless personal or body area networks (WPAN or WBAN) enabling a wide variety of compelling applications. As an example, WSN are used to survey the environment or to monitor energy consumption in residential buildings. The use of WSN enables real-time pricing and adaptive energy usage without user intervention. Several applications require low datarate, very low power consumption and a long lifetime for the battery. In this case the easier management of the wireless nodes has allowed discarding the star-mesh in favor of a more flexible peer-to-peer architecture. Within this evolving scenario, the ZigBee [9] and the other wireless sensor networks standards represent an additional step towards an even more flexible system able to reshape itself dynamically. Due to their nature, these systems do not require any base-station, since they are formed by autonomous shortrange wireless nodes, which monitor and control the environment defining the working area by their spatial distribution. Since the high density of units makes the system more flexible and relaxes the sensitivity of the single receiver, in ZigBee compliant networks the performance is exchanged with the possibility of having long-lasting and cheap devices [START_REF] Cook | Lowpower 2.4-GHz transceiver with passive RX front-end and 400-mV supply[END_REF]- [START_REF] Nguyen | A low-power RF direct-conversion Receiver/Transmitter for 2.4-GHz-Band IEEE 802.15.4 standard in 0.18-CMOS technology[END_REF]. However there is a trade-off between efficiency and cost which settles the density of nodes in a WSN. One of the most critical components making up an efficient sensor node is the wireless transceiver, which transmits and receives data packets in order to provide the communication link between distributed nodes. The goal of this research activity through MIRANDELA project is to comprehensively address the challenges in implementing ultra-low power CMOS RFIC solutions for WSN.

System Requirements

The implementation of wireless sensor networks involve a hardware optimization in order to make dense node deployment possible in practical scenarios, each node must be physically and economically unobtrusive. In order to make these networks a reality, the wireless node should be optimized for three metrics:

• Low cost: The utility of the network depends on high density and ubiquity, which means a large numbers of nodes. In order to make large-scale deployments 6

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

1.1 System Requirements economically feasible, nodes must be very low cost.

• Small size: Embedding the components into the existing infrastructure of daily environments (walls, furniture, lighting, etc.) requires a very small form factor of the entire sensor node. Typically, node volumes less than 1 cm 3 (much smaller than a AA battery) are necessary. A very high level of integration is mandatory if such small dimensions are to be achieved.

• Low power: For large networks with many nodes, battery replacement is difficult, expensive, or even impossible. Nodes must be able to function for long periods, ideally up to 10 years, without running out of power.

Each of these three factors are somewhat intertwined. For example, electronic components are already so small that overall module size is limited by power supply or energy storage requirements. For this reason, reducing power consumption of the electronics is an effective way to shrink size as well. Another example is that highly integrated circuits with few external components can simultaneously reduce both size and cost. One of the most compelling reasons to reduce power consumption is to enable the use of new power supply technologies like energy harvesting [START_REF] Steingart | Micropower materials development for wireless sensor networks[END_REF] and low cost printable batteries [START_REF] Steingart | Dispenser printing of solid polymer-ionic liquid electrolytes for lithium ion cells[END_REF]. These early-stage developing technologies cannot supply much power, so any means of reducing power requirements will hasten the adoption of next-generation power supplies.

A successful implementation of wireless sensor networks require improvements in several disciplines: networking, low power RF and digital IC design, MEMS techniques, energy scavenging, and packaging. Figure 1.1 shows the various specialized blocks of a sensor node. In the implementation of extremely small sensor nodes, each of these blocks becomes crucial. However, among all the functions, the wireless communication component is the most power consuming one and the most challenging issue in implementing a wireless node is the integration of ultra-low power RF transceiver. Therefore, the main target of this research is to reduce the energy dedicated to communication in wireless sensor nodes.

In order to reach this goal, it is important to understand the needs of RF transceivers in WSN.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

RF Transceiver Requirements

This section describes the transceiver requirements [START_REF] Otis | Ultra-Low Power Wireless Technologies for Sensor Networks[END_REF] that are unique to sensor node communications. It is further demonstrated, the radio requirements are very different from traditional low power transceivers (pager receivers, RFID tags, Bluetooth-specification radios, keyless-entry).

Power Consumption

In the design of prototype sensor nodes, the wireless interface consumes the largest fraction of the power and size budget of the node. While the demands of the sensing and digital processing components cannot be ignored, their duty cycle is typically very low. A combination of advanced sleep, power down, and leakage reduction techniques allows to make their average power dissipation virtually negligible [START_REF] Kao | Subthreshold leakage modeling and reduction techniques [IC CAD tools[END_REF]. Thus, the wireless interface for sensor networks is the dominant source of power consumption. Whereas optical communication approaches offer the potential of very low power and small size, line-of-sight and directivity considerations make them less attractive [15].

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Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Datarate

As mentioned, the requirements of a transceiver for wireless sensor networks differ dramatically from a traditional wireless link. Thus, common performance metrics such as energy/bit and bits/s/Hz should be applied with the realization that other factors prevail. For example, a modified metric such as energy/useful-bit is relevant if all sources of power and overhead (for example: synchronization, the impact on energy storage) are included. First we will examine the typical operation mode of the sensor node.

An investigation of the traffic patterns and data payloads reveal that the transceiver operation is fundamentally different than a wireless LAN or Bluetooth-specification radio.

Data packets in sensor networks tend to be relatively rare and unpredictable events. In most application scenarios, each node in the network sees only a few packets/second.

In addition, the packets are relatively short (typically less than 200 bits/packet). This is expected as the payloads normally represent slowly varying and highly correlated environmental data measurements. Combined, this means that the average data rate of a single node rarely exceeds 1 kbit/s.

Range

In this discussion, we will assume that the nodes in the network are placed relatively closely (the average distance between nodes is less than or equal to 10 m). For a given sensitivity, scaling the node to larger ranges would require additional transmit power or increased coding gain (longer transmit times). As the transmitted power increases in low power transmitters, the global transmitter efficiency increases. Thus, in short-distance links, rising the transmitted power is the preferred approach over increased coding gain.

As the transmitted power increases, a linear enhance in the link budget is obtained for a sub-linear increase in the transmitter power consumption. Improving the link budget through coding gain would involve linear or super-linear increases in the receive power consumption due to increased packet length and/or higher received bandwidths. Indeed, at transmitted power levels of -10 dBm and below, a majority of the transmit mode power is dissipated in the circuitry and not radiated by the antenna. However, at high

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

transmit levels (over 0 dBm), the active current draw of the transmitter is high. It is difficult to source high active currents with micro-scale energy scavengers and batteries.

Convenient and efficient transmit power levels for sensor node applications are roughly in the range of -10 to 3 dBm.

Sensitivity

Figure 1.2 plots the theoretical range for a radio with a -70 dBm sensitivity for various RF propagation models at 2 GHz. As shown, the range varies greatly depending on the radio environment. For free space (where the path loss appropriate is R 2 ), a range of 37 m is achieved with a 0 dBm transmit power. However, in indoor environments, a higher exponent (R 3 or R 4 ) is more suited. In that regime, a transmit power of at least 0 dBm is required for a 10 m range. To add a margin for deep fading, the receiver sensitivity for a 0 dBm transmit signal and a 10 m range should be greater than -75 dBm. Thus, for this application, a receiver sensitivity of better than -75 dBm is imposed. Higher sensitivities will allow lower transmitted power levels, subject to the constraints in the previous section.

Turn-On Time

In an environment in which the radio is in idle or off mode most of the time, and in which data communications are rare and packets short, it is essential that the radio start up very quickly. For instance, a typical 1 Mbps Bluetooth specification radio with a 500 µs turn-on time would be poorly suited for the transmission of short packets. The on-time to send a 200 bit packet would be only 200 µs. Start-up and acquisition represent an overhead that is larger than the actual payload cost, and could easily dominate the power budget (given that channel acquisition is typically the most power-hungry operation). Thus, fast start-up and acquisition is essential to minimize this overhead.

An agile radio architecture that allows for a quick and efficient channel acquisition and synchronization is desirable. Complex wireless transceivers tend to use sophisticated algorithms such as interference cancellation and large constellation modulation schemes to improve bandwidth efficiency. These techniques translate into complex and lengthy synchronization procedures and may require accurate channel estimations. Packets are spaced almost seconds apart, which is beyond the coherence time of the channel. This means that these procedures have to be repeated for every packet, resulting in major overhead unsuitable in a low-power environment. Simple modulation and communication schemes are hence the desirable solution if agility is a prime requirement.

Integration/Power Tradeoff

Achieving the goal of a very low power/low cost RF design is complicated by a well documented power/integration (cost) tradeoff. For example, the use of high performance SiGe processes, while offering the designer high f T operation and low bias current levels, eliminates the possibility of integration with low power digital systems. A multi-chip solution would prohibitively increase the cost and area for sensor network applications.

Another common strategy for CMOS RF designers trying to reduce power consumption is to use high quality passive surface mount components [START_REF] Porret | An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver[END_REF]. This solution also prohibitively increases cost and board area, as each surface mount inductor is larger than the entire transceiver chip. Recently published "fully integrated" transceivers typically refer to a

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

transceiver that has simply eliminated the need for external ceramic or surface acoustic wave (SAW) filters. They still, however, require an off-chip quartz crystal and various passive components. To meet the cost and form-factor requirements of this application, a truly fully integrated transceiver is mandatory. In addition to increasing the size, off-chip passives add more complexity and cost to the board manufacturing and package design.

Furthermore, these macro-fabricated components increase the manufactured performance distributions of the radio by adding completely uncorrelated component variations. One method that can be used to achieve a high level of integration is the use of a relatively high carrier frequency. Currently available simple low power radios, as used in control applications, typically operate at low carrier frequencies between 100 and 800 MHz. A high carrier frequency has the distinct advantage of reducing the required values of the passive components, making integration easier. For example, a 2.53 µH inductance is needed to tune out a 1 pF capacitor in a narrow-band system at 100 MHz, requiring a surface mount inductor. For a 2 GHz carrier frequency, the inductance needed is only 6.33 nH, which can easily be integrated on-chip using interconnect metallization layers.

In addition, the critical antenna physical dimensions are linearly related to the carrier frequency. For a given antenna radiation pattern and efficiency, a higher carrier frequency allows a much smaller antenna. A quarter-wavelength monopole antenna at 100 MHz would be 0.75 m long. At 2 GHz, the size shrinks to 37.5 mm, allowing very efficient and inexpensive board-trace antenna. However, the drive to higher carrier frequencies in the interest of high integration is in direct conflict with the need for low power consumption. As the carrier frequency increases, the active devices in the RF signal path must be biased at higher cutoff frequencies, increasing the bias current and decreasing the transconductance-to-current gm/Id ratio. The result is an increased power dissipation at higher carrier frequencies. Thus, an inherent tradeoff exists between integration and power consumption that must be addressed through architectural decisions and the use of new technologies.

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Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Challenges

Challenges

In order to meet the RF transceiver requirements of wireless sensor networks, several challenges have emerged addressing both physical and protocol layer issues. The energy scavenging problem for example is an important technological key issue in wireless sensor networks. In fact, offering a wireless node the possibility to harvest the energy from his environment is an ideal solution to improve the lifetime of the wireless sensor and to avoid costly battery replacement. However, the power efficiency of these energy scavenging sources is sometimes limited and must be enhanced to provide necessary power to the node. Another attractive challenge is the duty-cycle control of radio communication module. This latter is most of time in idle state and large amount of energy could be saved by choosing a proper duty-cycle control.

Energy Constraints

In order to reduce the implementation cost and to allow a flexible method of deployment, the node's battery lifetime must be enhanced. In fact, in many applications, the maintenance cost considerations render frequent replacement of the energy source deterrent. Thus, the node has to scavenge its energy from the environment. The energy storage capability is limited by the storage medium (battery or capacitor) and the size constraints. Single-time charge could work for applications with life cycles below one year, replacing the energy supply could be constraining for some applications and using energy scavenging is often a necessity. The finite power density of state-of-the-art energy sources is illustrated in Table 1.1 [START_REF] Roundy | energy scavenging for wireless sensor nodes with a focus on vibration to electricity conversion[END_REF].

The average power dissipation of the node is severely constrained by the energy scavenging volume of the node. These sources can be broadly grouped into two categories:

energy scavenging sources and energy storage sources. From a volume of 1 cm 3 , an average continuous output power of 100 µW could be supplied by one or a combination of these power sources. If a one year lifetime were acceptable, either a lithium battery or fuel cell would suffice. However, micro fuel cell technology is still in the early stages of research, and is prohibitively complex and expensive. Another active area of research is the thin-film battery technology, which will yield large benefits for sensor node implementations. For desired node lifetimes greater than one year, however, 1 cm 3 does not provide ample storage for the node's 3110 J/year energy requirements. Typical node deployment scenarios would demand a 10 years lifetime (31 kJ). This is a prohibitively large amount of energy to store in a 1 cm 3 volume, requiring the harvesting of energy from the environment. Solar power is a proven and universal method of collecting ambient energy. For outdoor or high-light conditions, this is the obvious solution. However, in dim lighting conditions, the power output drops dramatically. In these environments, an additional energy source is needed. Vibrational converters, air flow generators, and temperature gradient generators all produce 50-400 µW cm -3 , as listed in Table 1.1. Of the three, vibrational converters are the simplest and they have the most potential for wafer-scale fabrication. In conclusion, a 1 cm 3 sensor node can support an average power draw of 100 µW. A combination of solar or vibrational energy scavenging and battery energy storage is likely to yield the most robust and inexpensive solution. In addition to limitations on average power dissipation, the available peak current levels that can be supplied to the electronics are also limited. In fact, the current consumption form is an important metric in wireless sensor networks and it is not surprising that wireless sensor communication components score well on power consumption and utilization of wake-up/sleep modes for duty cycling. However, power consumption is only part of the solution. Four other factors must also be addressed in order to achieve low power in wireless sensor applications [17]. These are peak current, graceful power failure, low-power mesh routing and sleep current.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Peak current

The plot in Figure 1. 3 [17] depicts the current consumption in three typical wireless sensor node states for a commonly used wireless sensor platform. In state one, the microprocessor and transceiver are in sleep mode (10 µA). In state two, the microprocessor is switched on while the transceiver is asleep (10 mA). In state three, both the transceiver and the microprocessor are awake (27 mA). These current draws can be sustained with Figure 1.3: Three current consumption states in a wireless sensor node high-power batteries such as alkaline cells, but they typically exceed the tight energy budgets available with small batteries or energy harvested sources. These energy sources share an important feature; they have a hard time generating the peak current needed to awaken the electronics, even if they can cope with the average current consumption

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

throughout the wake-up/sleep cycles. A coin cell battery, for example, has a typical maximum output power of 15 milliamps, far below the peak value that most wireless communication systems require. In addition, since most microscale energy scavenging and storage devices provide a naturally high impedance, the peak current drive capability is small (less than a few mA). Providing high drive current would require excessively large storage capacitors and complex voltage regulators. The RF datalink circuit design must address this issue by presenting a low peak active current draw.

Graceful power failure

When an energy source has dried out, the electronics cannot communicate and are dead.

This unexpected situation can arise and must be taken into account, either as a normal event, solar cell at midnight as instance or as an exceptional condition (depleted battery).

In both case, the power problem is expected to be forecasted before the energy source has completely dried out. During this last breath, the device should perform a number of actions to inform its environment of the situation, transmit some critical data and put itself in a state that allows fast recovery when the power is restored. To accommodate failing low-power energy sources such as batteries and solar cells, devices must employ a technique known as "graceful power failure". During normal operation, the devices carefully monitor the state of the power circuits. As they encounter declining power levels, they raise different levels of alarms ranging from early warning to near-death. The alarms are escalated and communicated to other parts of the system, thereby enabling the system to be placed in a state consistent with the alarm condition.

Low-power mesh routing

One of the most important differences between wireless sensor communication technology wireless link can do. However, to forward a message received from a neighboring node, the concerned node needs to be in an awake and receiving mode when the original wireless message arrives. Unfortunately, the receiving mode requires so much power that it can drain batteries in a matter of a few days. The most straightforward solution, as specified by most industry standards, is to limit the multi-hop capability to the nodes that are permanently connected to the main power. In such a framework, low-power devices, which are assumed to be in a power-down mode most of the time, are not capable of retransmitting messages from other devices. These low-power devices, known as end-devices, are located at the end or beginning of the communication chain. This framework, which combines mains-powered mesh routing devices and low-power enddevices, works for some applications. Take, for example, an office lighting application utilizing interconnected wireless luminaires and light switches. The luminaires, which are connected to the main power source, house the mesh routing communication nodes.

The switches, which are not mains powered, are a natural place for the end-devices.

Many other applications do not fit well in such a framework. Think of gas detection, fire detection, access control, precision farming, battlefield monitoring, perimeter surveillance and warehouse temperature monitoring. In these applications, mains power is not readily available or even present. Running a power cable in these applications would be cost prohibitive, offsetting the benefit of wireless communication. To address this class of applications, which has been found to be more prevalent than mains-powered, multi-hop applications require a totally different framework. In this framework, known as low-power multi-hop networking or low-power routing, all of the nodes, including the mesh routing nodes, operate in low-power mode. The key to this approach, referred in the literature as "synchronized wake-up", is to coordinate receiving activity in a way that eliminates the need for the mesh routing nodes to continually operate in receive mode, thereby significantly reducing power consumption. Synchronizing "awake" period among nodes they expect a message from a neighboring node. This enables the routing nodes to operate in a nearly powerless sleeping state most of the time, thereby achieving ultra-low-power operation. Clearly, more wake-ups will occur than strictly required to carry the data, as neighboring nodes will not always have data to transmit. However, the additional power required for periodic wake-ups and synchronizations is more than offset by the power saved by eliminating the need for continuous receive mode operation.

sleep current

Wireless chips are usually specified according to their power consumption in receive and transmit mode. Remember, however, that in order to achieve low power, the devices must be duty cycled, moving between alternate sleep and awake states. The longer the required battery life, the longer the device sleeps between wake-up periods. Unfortunately, electronic circuits never really "sleep". Although the powered-down circuits don't yield anything meaningful from a functional standpoint, a small leakage current flows through the transistors. This leakage can amount to several tens of microamps. Sleep current is not usually considered as an important design factor, but it becomes extremely important when designing a circuit that must live for five years or more on a battery, sleeping most of its life. If the design is not optimized for low leakage current, the majority of the power will be spent on sleeping.

Duty-cycle Control in Sensor Networks

Several methods can be used to address the duty-cycle control issue. Most of them can be described as protocol-based. In synchronous networks, a global reference clock is maintained on each node throughout the network. With a global clock, the protocol can assign communication timeslots to each node. The drawback of this solution is that it may be difficult to maintain and distribute the clock in an ad-hoc network where nodes may be joining and leaving the network. In addition, the energy used to distribute and maintain synchronization can be significant. Another type of protocol-based duty-cycle control, which avoids a global time reference, is pseudo-asynchronous "rendezvous". Depending on the protocol, communication may be initiated by either the transmitting node or the receiving one [START_REF] Lin | a comprehensive study of power-efficient rendezvous schemes wireless sensor networks[END_REF]. Figure 1.5 shows an example of a transmitter-initiated protocol.

A timer is used to activate the receiver periodically in order to monitor the channel for communication. If no signal is received, the node returns to sleep mode. When the transmitting node wants to initiate communication it repeatedly sends requests, or beacons, until the receiver wakes up and hears the request, at this time data can be exchanged. Although this method avoids the need for time synchronization between the two nodes, significant energy may be expended both by the receiver (monitoring) and the transmitter (beaconing). More importantly, there is an inherent trade-off between average power consumption and network latency. In order to reduce latency, the protocol must be adjusted for the receiving node to monitor the channel more often, increasing duty-cycle and average power. An alternative to protocol-based duty-cycle control is based on asynchronous wake-up. This method adds an auxiliary receiver called a wake-up WuRx can respond immediately to requests and so latency is effectively eliminated. The energy that was previously dedicated to repeated beaconing on the transmit side and periodic monitoring on the receive side is replaced by the power consumption of the WuRx.

Because of the continuously monitoring of the channel by the WuRx, its active power consumption must be very low. Duty-cycle control based on asynchronous wake-up is an attractive alternative to protocol-based methods for many network scenarios, particularly those with low latency requirements. However, very few published wake-up receiver implementations exist in the literature. In [START_REF] Shih | Wake on wireless: an event driven energy saving strategy for battery operated devices[END_REF], the authors extend the battery life of a personal digital assistant (PDA) by activating it only when an incoming request is received. An IEEE 802.11b wireless LAN transceiver is used for data communications in this prototype, while the wake-up receiver is implemented with a commercial off-the-shelf receiver module consuming about 7 mW in receive mode.

Low-power Design Strategies

Battery life-time is an important performance metric for many wireless networks. In WSN applications for example, there is a growing need to extend the life-time of the network and, as discussed before, energy scavenging techniques and duty-cycle control help to reach this goal. However, this is one part of the solution and a deep investigation on radio communication module (cf. section 1.1) of sensor nodes is mandatory to see where we can attack the power consumption problem. A proper architectural choice is crucial to obtain good levels of performance, costs and power dissipation. Nevertheless, it is only the first step towards the design optimization, which can be reached only by proper choices down to transistor level. Within communication module's blocks, radio-frequency ones are the most promising for power and area saving since they are more expensive and

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

power-hungry than low-frequency parts. Therefore, much effort in optimization process is paid to RF blocks. In this section several design approaches are discussed, in order to find the most effective area and power minimizing strategies proposed in the litterature. To illustrate this purpose some selected examples from the state-of-the-art are reported and described in this section. The proposed architectures specifically highlight the tradeoff between silicon saving and the optimization of power consumption. Figure 1.7 shows a direct conversion receiver architecture proposed in [START_REF] Song | A low-power 2.4-GHz current-reused receiver front-end and frequency source for wireless sensor network[END_REF]. Since the frequency synthesizer is the most power-hungry block in a receiver front-end, reducing its power consumption results in a large saving on the whole receiver power dissipation. Therefore, the proposed solution reduces the working frequency to save power. In a conventional direct conversion [START_REF] Song | A low-power 2.4-GHz current-reused receiver front-end and frequency source for wireless sensor network[END_REF] receiver, the RF input signal and LO frequencies are equal, which allows the translation of the input to DC. In this architecture, the generated LO frequency is halved respect to the RF signal; the frequency synthesizer is then processed by a frequency multiplier to generate the desired RF frequency for direct conversion. Thus, both voltage controlled

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Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Challenges

oscillator (VCO) and the frequency divider work at 1.2 GHz instead of 2.4 GHz, resulting in power saving. This is obtained at the cost of a phase noise worsening, which is anyway maintained in an acceptable range for the application. Power reduction is also obtained thanks to the buffering effect of the frequency multiplier avoiding the need to introduce power-hungry buffers. In this solution, the power optimization is obtained by increasing costs, since two integrated coils are required to generate the desired LO frequency.

Another way to minimize power consumption is to reduce both, bias current and voltage supply. The approach proposed in [START_REF] Cook | Lowpower 2.4-GHz transceiver with passive RX front-end and 400-mV supply[END_REF] focuses mainly on voltage supply minimization.

The architecture reported in Figure 1.8 is based on a passive and differential front-end in order to increase the available voltage swing and to have a good noise figure (NF) and linearity at minimum power. In order to reduce the number of inductors and therefore [START_REF] Cook | Lowpower 2.4-GHz transceiver with passive RX front-end and 400-mV supply[END_REF] the silicon area, the antenna matching network is shared between the transmitter and the receiver. This network, which introduces a passive gain, replaces the traditional LNA, resulting in power saving. Quadrature generation is provided by a back-gate quadrature VCO. This technique reduces power consumption in comparison with the conventional cross-coupling quadrature generation [START_REF] Kim | A very low-power quadrature VCO with back-gate coupling[END_REF]. In transmit mode, the PA and mixer are driven from the high quality factor LC tank of the VCO without buffering and the whole differential VCO output swing is amplified. This design choice helps to reduce power consumption and to improve performances. Avoiding quadrature generation at LO path [START_REF] Kluge | A fully integrated 2[END_REF] architecture utilizes a single oscillator signal and generates the quadrature signals in RF path, where the low-noise amplified signal is split into I and Q components using a passive 2 stage poly-phase-filter (PPF). The down-conversion mixer can be implemented as a passive switching device, lowering not only the power consumption but also the flicker noise in comparison with a Gilbert cell. Thus, the only power consuming element of the receiver front-end is the LNA, which has also to compensate losses introduced by the poly-phase-filter and mixer. The proposed LNA is composed by two stacked stages, sharing the bias current and boosting the gain. Concerning the transmitter, the VCO frequency modulation is performed within the loop. This allows to amplify the modulated signal without any mixing and low-pass filtering needed, which helps to reduce power consumption. In addition, the constant envelope frequency modulation allows to maximize the PA efficiency. In this design strategy, power minimization is reached by using a single VCO and generation quandrature in the RF path. This choice requires a careful design of the LNA, where power consumption can be minimized exploiting the bias sharing technique. In conclusion, even if the power and area minimization require This can be obtained by e.g. sharing the matching network and the oscillator between the transmitter and the receiver. Nevertheless, the most promising solution to save power consumption seems to be bias and device sharing. A careful choice of the operating region for transistors is necessary in order to capture both RF performances and current effieciency [START_REF] Shameli | Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study[END_REF]. Another promising approach to further reduce power consumption is to merge functionalities in RF building blocks [START_REF] Liscidini | Single-stage low-power quadrature RF receiver front-Ultra-Low Power RFIC Solutions for Wireless Sensor Networks end: The LMV cell[END_REF]. This attractive way helps to maximize the power saving while maintaining a good flexibility, which can be exploited to optimize the design and reach a good trade-off between power dissipation and system performances.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

24

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Since the RF transceiver requirements in WSN are quite relaxed in comparison with other wireless networks, they can be satisfied by designing mere circuits and systems.

The need for complex architectures, to demodulate the RF signal, is no longer necessary and new topologies could be imagined to directly extract the useful information. One can imagine the early times of radio receivers with envelope detection module to demodulate AM signals. These systems could be implemented in wireless sensor networks thanks to their simplicity. This approach will be further detailed and discussed in chapter 3.

Thesis organization

This chapter proposes a brief on wireless sensor networks backgrounds. Requirements on system and radio-frequency transceivers are presented with a special focus on power consumption of radio communication module. Challenges related to energy constraints and duty-cycle control in sensor networks are discussed. The main goal of this research is to present solutions at circuit and system levels which help the design and implementation of an ultra-low power receiver for WSN. Chapter 2 introduces some design methodologies dedicated to reduce the power consumption at building block level. Two circuits a mixer and a mixer-VCO, namely Self-Oscillating Mixer (SOM), are presented to illustrate the techniques. Chapter 3 describes the design and implementation of a receiver demodulator

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

using a novel architecture to extract useful information from a RF signal. This system level solution is compatible with basic modulation schemes namely phase modulation, frequency modulation and amplitude modulation. Finally, Chapter 4 concludes with a brief summary of results and discussion of future research directions.

Chapter 2

Circuit Approach

This chapter introduces design methodologies to reduce power consumption in RF circuits. First, techniques to reduce power consumption are discussed.

Since they do not correspond all the time to low voltage operation, approaches

for lowering supply voltage are also proposed. In order to implement these techniques, a mixer and a self-oscillating mixer were carried out in a 130 nm and 65 nm CMOS process respectively.

Analog Techniques for low power/low supply voltage

RF design

Standard CMOS technology has become prevalent in analog and RF circuit design mainly due to the low production cost and potential for integration with accompanying digital circuits. As outlined in chapter 1, cost and integration are two essential considerations in the design of circuits for wireless sensor networks. Thus, scaled sub-micron CMOS technology is a natural choice for implementation of these circuits. In addition, deep sub-micron CMOS opens up new frontiers in low voltage and current circuit design. In this section, design techniques are outlined to fully explore the advantages of modern CMOS devices and achieve minimal power consumption for RF circuits.

Circuit Configurations

Although CMOS scaling has been extremely beneficial for digital circuits, analog circuits have often been hindered by these advances. One of the most difficult problems is the constantly diminishing supply voltage for modern CMOS processes, causing reduced voltage headroom and dynamic range for analog and RF applications. Figure 2.1 shows projected trends in CMOS supply voltage scaling over the next 6 years, as predicted by the International Technology Roadmap for Semiconductors (ITRS) [START_REF]international technology roadmap for semiconductors[END_REF]. Scaling trends are shown for three different digital technology targets. The low power operation digital roadmap is the most aggressive, since supply voltage scaling is one of the main strategies for reducing power consumption in digital circuits [START_REF] Hegde | A voltage overscaled low-power digital filter IC[END_REF]. Trends for high performance and low standby power designs lag by several generations, but are also expected to experience supply voltage scaling below 1 V in the next six years. These digital roadmaps are an important indicator for the state of future analog designs because digital performance drives technology scaling. In order to reap the cost benefits of integration, analog and RF designs must conform to the specifications of digital technologies. One common strategy for dealing with reduced voltage in analog designs is to use special analog process options or high voltage I/O devices for the analog portions of the design. Though effective, this solution raises cost and increases power usage of the analog block. It is clear that future analog and RF designs will be subjected to ever more stringent supply voltage constraints.

In many cases, however, it may be feasible to embrace this trend and reduce the supply voltage as low as possible as a means of achieving minimum power consumption. For low power designs, the minimum bias current is usually determined by the required circuit performances and cannot be arbitrarily reduced. On the other hand, the supply voltage is usually set at a standard value that may not be optimal for the design. If the current levels are optimized, the technique of reducing the supply voltage may result in additional power savings. In the following, possible opportunities for low voltage RF design are discussed.

The Cascode and Folded Topologies

The cascode configuration is widely used in the design of CMOS RFICs thanks to its reasonable high-frequency characteristics in terms of gain, output impedance and reverse isolation. Figure 2.2 shows a simplified illustration of a cascode stage with its principles of operation in dc and ac conditions [START_REF] Manku | A low-voltage design technique for RF integrated circuits[END_REF]. With a stacked architecture, the dc bias current is shared by the two active devices of the same type, which is advantageous as far as power consumption is concerned. However, if both of the metal-oxide-semiconductor (MOS) transistors are operating in saturation, a supply voltage of at least twice of the transistor's overdrive (V GS -V T H ) is required. Typically, the RF performance of a cascode stage degrades significantly as the supply voltage decreases, making it less attractive for low-voltage circuit operations. To alleviate the stringent limitations on the supply voltage, a folded cascode configuration in classical analog circuit design has been adopted by many RF designers. The idea of folded cascade is to decouple the ac and dc paths of the circuit. A simplified illustration is depicted in Figure 2.3 where a decoupling capacitor and two RF chokes are employed. As the equivalent impedance provided by the RF chokes is sufficiently large and the decoupling capacitor is considered as a short circuit at

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Complementary Current Reuse Technique

As indicated in the previous section, the folded cascode topology trades dc power for supply voltage. To achieve low-voltage and low-power circuit operations at the same time, a complementary current-reuse technique is proposed in [START_REF] Hsieh | Design of ultra-low-voltage RF frontends with complementary current-reused architectures[END_REF] with circuit example and design guidelines for down-conversion mixers. A conceptual illustration of a downconversion mixer using the current-reuse technique is shown in Figure 2.4, where the

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

transconductance stage M N performs the voltage-to-current conversion of the RF input signal, small-signal current is then directed to the source of the PMOS differential pair through capacitor C 1 . The commutating stage (M P 1 , M P 2 ) provides frequency downconversion since it is driven by local oscillator (LO) with sufficient swings. Resistor R 1 is employed to provide a bypass current path such that large load resistance R L can be used to boost the conversion gain without introducing excessive voltage drop.

Vdd RF M N R L R L R 1 C 1 M P1 M P2 L 1 LO IF Vdd

Transistor Biasing

Forward-body Bias Technique

In the design of CMOS RFICs for low-voltage operations, the threshold voltage of the MOSFETs is considered one of the fundamental limitations for the supply voltage. For circuits in which the active devices are always on, it is desirable to have transistors with a reduced threshold voltage. For the CMOS process technology, the option of multiple threshold voltages is typically realized by adjusting the thickness of the gate oxide or the doping profile in the channel. However, this complicates the fabrication process and requires higher implementation cost. Alternatively, the threshold voltage can be manipulated by the bias voltage at the body terminal. Taking the n-channel MOSFET

32

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Analog Techniques for low power/low supply voltage RF design

as an example, the threshold voltage is given by:

V T H = V T H0 + γ( |2φ F + V SB | -|2φ F |) (2.1)
Where V SB is the source-to-body voltage, V T H0 is the threshold voltage for V SB = 0, γ is a process-dependent parameter, and φ F is a semiconductor parameter with a typical value in the range of 0.3-0.4 V. In a triple-well CMOS technology, the simplified cross-sectional view of a NMOS device is given in According to [START_REF] Mostafa | A novel low area overhead direct adaptive body bias (d-ABB) circuit for die-to-die and withindie variations compensation[END_REF] and [START_REF] Hokazono | MOSFET design for forward body biasing scheme[END_REF], the upper limit of the FBB voltage for latch-up free operation, in 65 nm CMOS technology with V DD ranges from 0.9 to 1.2 V, is 0.6 V. gate forward bias from 0 V to 0.6 V can lower the threshold voltage from 0.41 V to 0.36 V, which correspond to a reduction of 12 %. Therefore, the circuit power supply voltage could be lowered by the same proportion.

Subthreshold Operation

The main interest in transistor effect is the transconductance operation, which converts an input AC voltage into an output AC current. Hence, the transconductance g m is the first and most important analog parameter of a transistor. The transconductance efficiency, rating the g m to the drain current, is a figure of merit exploited in the design of low power analog circuits. Its maximum occurs in subthreshold operation of MOS device as depicted in Figure 2.8. In RF domain, the performances of a circuit are often correlated to the maximum of the cutoff frequency, f T , defined as:

f T ≈ g m 2π(C gs + C gd ) (2.2)
where g m is the small-signal transconductance and C gs and C gd represent the gate-source and gate-drain capacitances, respectively. Figure 2.8 figures out that the f T is maximum when the transistor operates in strong inversion region (SI), which in turn corresponds to a weak transconductance efficiency.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Technology Scaling

It is clear that MOS device exhibits a maximum of f T in strong inversion region which is more suitable for high frequency applications. Operating in weak inversion region increases the transconductance efficiency but it comes at the expense of lower device f T . However, with scaling down technology, cutoff frequency is increased for all regions of operation and it is no longer necessary to bias devices for the highest possible f T . This trend is depicted in Figure 2.9 which represents the cutoff frequency of 3 different CMOS generations: 130 nm, 65 nm and 28 nm. For a zero overdrive bias (V GS -V T H =0 V), the 130 nm process achieves a f T of 32 GHz, whereas the 65 nm and 28 nm nodes achieve respectively 50 GHz and 90 GHz of f T . Hence the increased bandwidth induced

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

of f T . It can also be noticed that the g m f T /I D ratio is independent of the transistor size for a given technology node. We will further reference the regions of MOS operation according to Table 2.1. U t representing the thermal voltage (kT/q). Table 2.1: Operating regions of the MOS transistor

Region of operation Voltage

Strong Inversion (SI)

V GS >V T H +4U t Moderate Inversion (MI) V T H -4U t <V GS <V T H +4U t Weak Inversion (WI) V GS <V T H -4U t
After investigating the advantages and disadvantages of subthreshold operation in this section, it appears that moderate inversion is an attractive compromise between the speed of strong inversion and the transconductance efficiency of weak inversion. In current technologies, moderate inversion is a realistic target for the realization of RF circuits. Moderate inversion also benefits from lower electric fields in the device, avoiding high field effects that degrade performance and reliability [START_REF] Enz | MOS transistor modeling for RF IC design[END_REF]. In this section, design approaches exploiting low supply voltage/low power techniques and subthreshold biasing were presented and motivated. First, circuit configurations aspects were discussed. Folded topology is suitable for low supply voltage operation, however, to achieve low-voltage and low power circuits at the same time, current reuse technique is more attractive. To further reduce power consumption, transistor biasing was also investigated to choose the optimized region of operation. So, in order to obtain RF performances and low power consumption, a new figure of merit was introduced, this latter includes the transconductance efficiency and cutoff frequency as

g m f T -to-current ratio (g m f T /I D ) and
it reaches a maximum in moderate inversion region. Therefore, a moderately inverted transistor seems to be an obvious choice for ultra low power circuits. Finally, equipped with these low power design methods; a mixer and a self-oscillating mixer are designed in the next sections to investigate these techniques.

Ultra-Low Power 2.4 GHz Down Conversion Mixer

In this section we will detail the first approach of this thesis, the optimized biasing approach. The technique is applied to a mixer to further reduce its power consumption.

First, mixer backgrounds are detailed. Then, the design of the circuit is discussed and finally, post-layout simulations are presented.

CMOS Mixer Fundamentals

The mixer is an essential building block in RF front-ends since it generates the frequency shift:

• In emitters, it upconverts a baseband signal to a useful signal at high frequencies, to take advantage of favorable propagation condition [START_REF] Lee | The Design of CMOS Radio-Frequency Integrated Circuits[END_REF]. In this case, they are called up-conversion mixers, Figure 2.11a.

• In receivers, it translates an incoming RF signal to an Intermediate Frequency (IF), namely the down-conversion operation, for efficient demodulation [START_REF] Lee | The Design of CMOS Radio-Frequency Integrated Circuits[END_REF].

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

improve the sensitivity of the system by lowering the noise contribution of the baseband stage. In Tx part, the high linearity and low 1/f noise of a passive mixer make it a good alternative. The power gain is then reported to the Power Amplifier (PA).

Performance Metrics of Mixers -Conversion Gain:

The "voltage conversion gain" of a mixer is defined as the ratio of the rms voltage of the IF signal to the rms voltage of the RF signal.

The "power conversion gain" of a mixer is defined as the IF power delivered to the load divided by the available RF power from the source (Eq 2.3). If the input impedance and the load impedance of the mixer are both equal to the source impedance, for example, 50 Ω as instance, then the voltage conversion gain (Eq 2.4) and power conversion gain of the mixer are equal when expressed in decibels. at the input (RF) port divided by the SNR at the output (IF) port Eq 2.12. The two-tone second-order and third-order intercept are used to characterize mixer linearity. A two-tone intermodulation (IM) test is a relevant way to evaluate mixer performance because it mimics the real-world scenario in which both a desired signal and a potential interferer (perhaps at a frequency just one channel away) feed a mixer input. The third-order intercept point is the extrapolated point where the fundamental and third-order intermodulation products (IM3) intersect each other. Figure 2.16 summarizes the different linearity performances of the mixer.

CG power = Output power at IF RF available input power = V 2 IF /R L V 2 RF /R S (2.
N F dB = 10 log( SN R RF SN R IF ) (2.
∑ + ∞ ∞ - = ω y n (t) = x n (t).S LO (t) ) ( . ) ( LO n k n k X a Y ω ω ω + = ∑ + ∞ ∞ - ) ( . ² 2 ) ( LO x k y k S a S n n ω ω ω + = ∑ + ∞ ∞ - if x n (t)

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Channel Blockers Channel f LO f 1 f 2 (f 2 -f 1 )-f LO (f 2 -2f 1 )-f LO

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power 2.4 GHz Down Conversion Mixer

Single-balanced and Double-balanced Mixers

Due to the nonlinearity of mixing operation, many spurious can appear at the mixer output. As matter of consequences the topology choice is very important to attenuate this phenomenon. In Figure 2.17a, the single balanced topology -i.e. single RF with differential LO-exhibits some harmonics at f LO in the IF spectrum. In Rx mode, these LO harmonics desensitize the receiver and so must be filtered. Its fully differential or fully balanced counterpart, Figure 2.17b, introduced by Barrie Gilbert [START_REF] Gilbert | A precise four-quadrant multiplier with subnanosecond response[END_REF], theoretically cancels both the LO and RF even order harmonics at the output. In practice, since the RF signal processed by the LNA (and possibly the image-reject filter) is usually single ended, one of the input terminals of the double-balanced mixer is simply connected to a bias voltage. This in turn creates different propagation times -i.e. phase shifts-for the two signal phases amplified by M 1 and M 2 , leading to finite even-order distortion [START_REF] Razavi | RF Microelectronics[END_REF]. Conversion gain and noise figure for these two architectures are expressed in equations Eq 2.7, Eq 2.8 and Eq 2.9.

CG ≈ 2 π g m1,2 R L (2.7) N F SB ≈ π 2 4 {1 + γ 1 g d01 g 2 m1 R S + 2 g 2 m1 R L R S } (2.8) N F DB ≈ π 2 4 {1 + 2γ 1 g d01 g 2 m1,2 R S + 2 g 2 m1 R L R S } (2.9)
where γ: Channel noise factor, g d0 : Open channel conductance and R S =50 Ω.

For a fixed power consumption, the two configurations achieve equal conversion gain but the single balanced architecture exhibits a lower input-referred noise.

Double balanced architecture provides good isolation and do not suffer from LOto-IF feedthrough, however, it requires a balun to perform its differential input.

This, degrades the noise figure of the front-end and adds more complexity.

Therefore, a single balanced topology seems to be more suitable for an ultra-low power system.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Vdd M 1 M 2 M 3 IF RF LO R L R L f LO f LO +f RF f LO -f RF f RF 3f LO 5f LO 5f LO 3f LO f LO I-V Converter
M 1 R L R L f LO +f RF f LO -f RF f RF 3f LO 5f LO f LO I-V

Topology Choice

Focusing on the design of a very low power down converter, the mixer topology is of single balanced type with differential output port. The current-reuse bleeding technique is exploited to further lower the noise figure and enhance the conversion gain of the mixer. An investigation of this technique is first presented in Figure 2.18 and then discussed.

Vdd RF M RF LO + LO - R L I bias R L IF + IF - (

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

The first configuration presented in Figure 2.18a is based on the conventional single balanced current-commuting mixer. In such structure, both the gain (Eq 2.10) and the linearity (Eq 2.11) are directly proportional to the amount of current flowing through the transconductance stage, I bias . On the other hand, the noise figure (Eq 2.12) increases with I bias for a fixed transconductance g mRF [START_REF] Darabi | Noise in RF-CMOS mixers: a simple physical model[END_REF] because of the noise induced by the switching pair and represented by the third term in Eq 2.12 according to [START_REF] Terrovitis | Noise in current-commutating CMOS mixers[END_REF].

V CG ≈ 2 π R L K n I bias (2.10)
IIP 3 ≈ 4 2 3
I bias K n (2.11) N F ≈ 1 + π 2 2g 2 mRF R L R S + πγI bias Ag 2 mRF R S + γπ 2 4g mRF R S (2.12)
where bleeding current source and also contributes to the transconduction of the input signal. For a fixed current I bias , the overall transconductance of the RF stage is no longer "g mRF " but "g mRF + g mbleeding ", with g mbleeding the transconductance of the transistor (M bleeding ). The first circuit developed in this thesis is based on this current-reuse bleeding configuration.

K n = µ n C ox (W/L)

Circuit Design

The complete circuit design consists of both the mixer core and two buffers to drive the signal off-chip. It is implemented in a 130 nm CMOS technology from ST Microelectronics. The design of the down converting part and the buffer stage are reported in this section.

Mixer Core

The mixer core is based on current-reuse bleeding configuration as shown in Both transistors operate in moderate inversion region to maximize the g m f T to drain current ratio. derived in Eq 2.13, Eq 2.14 and Eq 2. 15.

Vdd RF M 1 M 2 M 3 M 4 L g R C R L C L LO + LO - C L R L R C R C R f
N F ≈ π 2 4 {1 + γ 1 g d01 g 2 m1 R S + γ 4 g d04 g 2 m4 R S + 2 g 2 mT R L R S + R S R f } (2.13) Z in ≈ C 0 R f C gsT + C 0 + j{L g ω - g mT R f C 0 (C gsT + C 0 ) 2 ω } (2.14) V CG ≈ 2g mT R L R S L g C gs1 (2.15)
with g mT = g m1 +g m4 ; C gsT = C gs1 +C gs4 and R S =50 Ω.

The same current flows into M 1 and M 4 , it is the bleeding technique, thus allowing the switching stage to act as a pure passive mixer. As a matter of consequences, the noise contribution of (M 2 , M 3 ) can be neglected. The NF only accounts for the RF stage (M 1 , M 4 ), resistive load R L and the feedback resistor R f in Eq 2. [START_REF] Otis | Ultra-Low Power Wireless Technologies for Sensor Networks[END_REF]. The resistor R f , fifth term in Eq 2.13, needs to be as large as possible, with respect to the input matching conditions defined in Eq 2.14, to lower its noise contribution. C 0 models the capacitive loading effect of the switching stage (M 2 , M 3 ) connected to the transductor stage (M 1 , M 4 ). The imaginary part of the input impedance Z in is cancelled by tuning L g in Eq 2.14. R f , in combination with C gsT and C 0 adjusts the real part of Z in to 50 Ω.

Output Buffer

Output buffers are necessary for measurement in order to drive instrumenta- The buffer stage operates from a 0.8 V supply and consumes a total current of 2 mA. The final device types and aspect ratios are summarized in Table 2.2.

Layout and Post-layout Simulations

The final design has been realized in a 130 nm standard CMOS process with 6 metal layers from STMicroelectronics. In this design, the most sensitive parts are the switching pair (M 2 , M 3 ) and the input matching path. The switching part is laid out in a common centroide configuration to make it immune from cross-chip gradients and the extracted parasitic are embedded in the input matching synthesis. The complete chip layout is shown in Figure 2.21. The Their optimum values obtained at a LO power of 5 dBm are 22.7 dB and 9.3 dB respectively. Considering a constrained power budget to address ultra low power applications, it is better suited to account for an LO power which does not exceed 0 dBm, typically -1 dBm. Under these conditions, VCG and SSB NF are 18.7 dB and 11.5 dB respectively. The third-order intercept point (IIP3), -14.9 dBm, was tested by applying a two-tone large signal at 2.4 GHz and 2.401 GHz.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

F OM M ixer,linear = Gain × IIP 3 (F -1) × P DC (mW)
(2.17) post-layout simulations and the measurements of [START_REF] Vidojkovic | A low-voltage folded-switching mixer in 0.18-mu;m CMOS[END_REF] and [START_REF] Do | A weakinversion low-power active mixer for 2.4 GHz ISM band applications[END_REF], the current reuse bleeding topology achieves the second best FOM with -12.2 dB and the lowest power consumption, under 330 µW.

Ultra-Low Power 2.4 GHz Self-Oscillating Mixer (SOM)

As discussed in the previous chapter, this section introduces the second approach of the thesis. To deal with wireless sensor networks requirements and further reduce the power consumption of RF front-end, the approach consists in merging the RF building blocks functionalities. Several options are possible, either combining the LNA and the mixer or merging the mixer and the local oscillator. [START_REF] Sjoland | A merged CMOS LNA and mixer for a WCDMA receiver[END_REF], for example, combines the LNA and the mixer yielding to a Low Noise Converter (LNC). Compared with traditional cascaded LNA and mixer, this approach reduces the power consumption by removing the DC current path flowing into the LNA. Nevertheless, applying the RF signal to the mixer input with a low amplification, results in a low gain and a high NF which degrades the entire receiver performance. So, in this section we will focus on the study and design of Self-Oscillating Mixer (SOM). This option seems to be attractive since in an RF front-end, the local oscillator is the most power hungry building block.

CMOS LC Oscillators Background

Mixer basics have been already developed in section 2.2.1. We need now to introduce some fundamental elements about LC oscillators before investigating the design of the self-oscillating mixer.

f 0 = 1 2π √ LC (2.18)
Under the hypothesis of lossless components, the inductor and capacitor continue to exchange the stored energy in each other and the output voltage will never be attenuated. In practice, the hypothesis of lossless component does not hold on. Figure 2.27 shows a real case of LC resonator which includes series losses for all components (R sL , R sC ) and a parallel loss (R p ). The loss associated with the reactive components is identified by the quality factors:

Q L = ωL R sL (2.19) Q C = 1 ωCR sC (2.

20)

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

C L R p R sC R sL (a) Serie losses C L R p R peq R pL R pC (b) Parallel losses
R pL = Q L ωL (2.21) R pC = Q C ωC (2.22)
The characteristic impedance Z 0 and the quality factor of the complete tank circuit Q T are defined as follows:

Z 0 = L C = 1 ω 0 C = ω 0 L (2.23) R peq = R p //R pC //R pL (2.24) Q T = R peq Z 0 = R peq ω 0 L = ω 0 CR peq (2.25) 1 Q T = Z 0 R p + 1 Q L + 1 Q C (2.26)
The total tank quality Q T is dominated by the lowest quality factor component.

Due to the presence of the tank losses (represented by R peq ) the oscillation vanishes, because part of the energy exchanged in each cycle from the inductor to the capacitor and vice versa is dissipated by R peq . In order to maintain the oscillations, a negative conductance must be added in parallel to the resonator to compensate the tank losses. Negative conductance (or resistance) can be obtained with active circuits providing energy to the LC resonator, at least equal to the energy dissipated by the tank losses in each cycle. The minimum needed negative conductance g mc must be at least equal to the total loss conductance (1/R peq ): conductance is given by: g mc = -g m /2 where g m is the transconductance of the transistor M 2,3 . To guarantee the oscillation start-up the following equation must be satisfied:

|g mc | ≥ 1 R peq = 1 Q T Z 0 (2.
|g mc | = g m 2 ≥ 1 2R peq (2.

28)

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Vdd where 2R peq is the total differential resistance seen across the two LC tanks. The transconductance of each cross coupled transistor must be higher than the corresponding LC tank loss [START_REF] Mazzanti | Analysis and design of injection locked CMOS oscillators for radio frequency quadrature generation[END_REF].

I bias M 1 M 2 M 3 C L R peq V out- V out+ C L R peq -g m c

Oscillation Amplitude

If we assume that the differential current entering into the resonator is a squarewave ranging from -I bias /2 to I bias /2, at the frequency of resonance, higher harmonics of this input current are strongly attenuated by the LC tank and only its fundamental component (I 0 =2I bias /π) is converted into a differential voltage by the equivalent impedance at resonance 2R peq = 2Q T Z 0 . At high frequencies, the current waveform may be approximated more closely by a sinusoid due to finite switching time and limited gain.

In such cases, the tank amplitude can be better approximated as:

V out dif f = 4 π I bias Z 0 Q T = 4 π I bias ω 0 LQ T (2.29) 60

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power 2.4 GHz Self-Oscillating Mixer (SOM)

We can observe the linear dependence between the oscillation amplitude and I bias , Q T , and Z 0 . So to increase the output voltage swing, it is sensible to increase either the tail current or LQ T product. However, increasing the tail current increases power consumption. Therefore, there has been constant research on improving inductor quality factor. High Q inductor also implies a lower g m to start oscillations.

This analysis is true in the current-limited region of the oscillator. However, there is a point where a further enhance in current does not lead to an increase in output voltage swing. This is the voltage-limited region where the output swing is limited by the DC voltage supply. The output voltage saturates to a value close to two times the voltage supply V DD . The bias current at which the oscillator saturates is I biassat :

V sat = 2αV DD = 4 π I biassat Z 0 Q T (2.30)
Therefore,

I biassat = π 2 αV DD Q T Z 0 = αV DD ω 0 LQ T (2.31)
with α < 1

Phase Noise

Another design challenge in voltage controlled oscillators is the phase noise.

Phase noise arises from thermal noise and flicker noise of the cross-coupled pair, MOS varactors, tail transistor, and the LC tank. The injected noise affects the amplitude and phase of the oscillator. Figure 2.29 shows the spectrum of an ideal and a real oscillator. An ideal oscillator only oscillates at the designed frequency and its frequency spectrum is just an impulse at f LO , whereas the real oscillator has a spread-out spectrum due to the bandpass nature of the LC tank. In the time-domain, phase noise produces jitter and amplitude variation. Leeson in [START_REF] Leeson | A simple model of feedback oscillator noise spectrum[END_REF] proposes an analytic expression of phase noise based on a Linear Time Invariant (LTI) model. The phase noise L(∆ω) is specified at an offset frequency (∆ω) from the carrier (ω 0 ) according to Eq 2.32:

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

f f LO f f LO Ideal Oscillator Real Oscillator
L(∆ω) = 2kT R peq F V 2 0 { ω 0 Q T ∆ω } 2 (2.32)
where k is the Boltzmann's constant, T is the absolute temperature, R peq is the equivalent tank parallel resistance, V 0 is the peak oscillation 62

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power 2.4 GHz Self-Oscillating Mixer (SOM)

amplitude, Q T is the tank quality factor. F, the noise factor, is given by [START_REF] Rael | Physical processes of phase noise in differential LC oscillators[END_REF]:

F = 2 + 8γR peq I bias πV 0 + 8 9 g m bias R peq (2.33)
where γ is the device white noise coefficient and g m bias is the current source transconductance. As previously seen, at low bias current, when the amplitude of oscillation is smaller than the power supply, the differential pair acts as a simple current switch driving the resonators and V out is expressed by Eq 2.29. For higher currents, the output voltage saturates close to two times the supply voltage. Combining Eq 2.32 and Eq 2.33, we can obtain:

L current-limited (∆ω) = (2 + 2γ) π 2 kT 16ω 0 LQ T I 2 bias { ω 2 0 Q T ∆ω } 2 (2.34) L voltage-limited (∆ω) = {2 + 4γω 0 LQ T I bias παV DD } kT ω 0 LQ T 4(αV DD ) 2 { ω 2 0 Q T ∆ω } 2 (2.35)
Eq 2.34 and Eq 2. [START_REF] Lee | Current-reuse bleeding mixer[END_REF] show that the phase noise decreases with I bias in the current-limited region and increases in the voltage-limited region.

Therefore, minimum phase noise is achieved at the transition of the two regions, when V out = V sat = 2αV DD and can be expressed as referenced in Eq 2.36:

L min (∆ω) = (2 + 2γ) kT ω 0 LQ T 4(αV DD ) 2 { ω 2 0 Q T ∆ω } 2 (2.36)
For a given technology, V DD and γ are fixed. The tank quality factor Q T can be maximized by an optimum choice of inductor and varactor. To reduce the minimum achievable phase noise of an oscillator, the inductor should be reduced, and the current consumption equally increased (according to Eq 2.31) to fall in the optimum region of operation [START_REF] Mazzanti | Analysis and design of injection locked CMOS oscillators for radio frequency quadrature generation[END_REF].

Self-Oscillating Mixer State-of-the-art

To combine both a mixer and an oscillator, many techniques have emerged in the literature. Self-oscillating mixer presented in [START_REF] Ho | A low-noise self-oscillating mixer using a balanced VCO load[END_REF] (Figure 2.31)

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

achieves the oscillation and mixing functions by stacking an LC-tank on a double balanced current-commuting mixer. Since the mixer output is fully differential, two cross-coupled pairs connected in parallel act as loads for the switching stage. As matter of consequences, the LO signal can easily end up at the mixer output. Another double-balanced oscillator

Vdd Vdd Vdd L tank V tune 2C p 2C p 2C var C 2 C 1 L s L g L shunt V LO + V LO - V bld V IF + V IF - V RF + V RF - M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 8 M 9 M 10 M 11 M 12 L s L g 2C var V bld V LO + Figure 2
.31: Schematic of the self-oscillating mixer proposed in [START_REF] Ho | A low-noise self-oscillating mixer using a balanced VCO load[END_REF] mixer implemented in a 180 nm CMOS technology is reported in [START_REF] Wang | A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology[END_REF] (Figure 2

the V DD is 1 V. 1 1 2 2 V DD1 V DD2 V G R G M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 8 VC C L 1 L 2 R L /2 V G R G R L /2 R s V cont R s V DD2 V DD2 V RF V RF Figure 2
.32: Low-power oscillator mixer from [START_REF] Wang | A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology[END_REF] Through a specific approach of the transconductor stage, some SOM topologies exhibit a low noise amplification. There are referenced as LMV for LNA-Mixer-VCO. In [START_REF] Liscidini | Single-stage low-power quadrature RF receiver front-Ultra-Low Power RFIC Solutions for Wireless Sensor Networks end: The LMV cell[END_REF], the LMV cell (Figure 2.33) exploits the intrinsic mixing functionality of a LC-tank oscillator to provide a compact solution. Sensing the downconverted signal at the output of the VCO unavoidably degrades the oscillator phase noise, so, a capacitor C dif f is introduced to sense the IF signal at the sources of transistors (M 1 ,

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

M 2 ). It closes the loop at RF while presenting a high impedance at IF.

A design trade-off between LNA and VCO must be undertaken in the choice of the aspect ratio of transistor M 0 , which is, at the same time, the VCO bias generator and the core of the low-noise amplifier. This means that the flicker noise injected by M 0 degrades the VCO phase noise.

Therefore, to avoid this trade-off, a low-frequency degeneration circuit must be introduced, attenuating the 1/f noise injected by the LNA core into the VCO. To reduce losses in the IF path, The LMV cell operates in current mode (i.e. introducing a virtual ground as IF output load).

It boosts the overall down-conversion gain to 36 dB. Unfortunately, this technique dramatically increases the power consumption to 5.6 mW.

Vdd Vdd

Q + Q - I + I - L s L g IF Load C diff I bias M0I M0Q M1I M1Q M2I M2Q M3I M3Q M4I M4Q M5I M5Q IF Load C diff I bias I - I + Q - Q + Vin RF M6I M6Q I Path Q Path Figure 2
.33: Low-power oscillator mixer from [START_REF] Wang | A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology[END_REF] The self-oscillating mixer proposed in this thesis is inspired from the work reported in [START_REF] Ho | A low-noise self-oscillating mixer using a balanced VCO load[END_REF]. A LC-tank is stacked on a single balanced mixer through two cross-coupled pairs in a current-reuse configuration. To take 66

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Circuit Design

In this section, a design analysis of the major blocks in the proposed self-oscillating mixer is detailed. First SOM core is described, transistor

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

models are also investigated. Then, the buffer circuit is briefly described.

SOM Core

Before proceeding to the design of the self-oscillating mixer, two transistor types from the design kit are compared according to the figure of merit g m f T /I D . Figure 2.35 shows the g m f T -to current ratio for the two transistor types, Low Power (LP) and General Purpose (GP), and this for various sizes. V DD , is chosen to be 1 V for nominal operation and the required bias current, I bias , is fixed by both startup condition and output voltage swing to perform the mixing operation. The core bias current through tail

Vdd L C C V C bias C L RF V tune Bias RF Bias LO Bias LO C L C V C bias R bias R bias R bias C p C p R L R L C bias C ext L g L s M 1 M 2 M 3 M 4 M
Z in = ω T L s + j{(L g + L s )ω - 1 (C gs + C ext )ω } (2.37)
with ω T =g m /(C gs +C ext )

At the operating frequency, f RF =2.4 GHz, the real part of Z in must be equal to 50 Ω and its imaginary part to zero:

ω T L s = 50 Ω ⇒ L s = 50 (C gs + C ext ) g m (2.38) (L g + L s )ω RF - 1 (C gs + C ext )ω RF = 0 ⇒ L g + L s = 1 (C gs + C ext )ω 2 RF (2.39)
The LC oscillator and the mixer part are connected through the source terminal of the cross-coupled pair. So, a single-ended configuration of the cross-coupled pair does not permit this connection because of differential output of the mixer, however, the same cross-coupled pair can be realized by connecting two cross-coupled pair in parallel as shown in Figure 2.37, where the transistor size is half the original thus permitting a differential connection. The overall small-signal negative resistance provided by the the tank losses and allow oscillations to build up. Therefore, the critical parameter for oscillator startup is the transconductance of the crosscoupled devices. The required g m for startup establishes a lower limit on the current consumption of the SOM. The tank losses was evaluated to 670 Ω at 2.41 GHz, so the necessary g m,crit to start the oscillations is:

|g mc | = g m,crit 2 = 1 R peq ⇒ g m,crit = 2.9 mS (2.40)
To ensure reliable startup, the required transconductance must be at least twice the minimum value. The specified g m provided by the two crosscoupled pair is set to 6 mS. In order to optimize the transconductance for minimal bias current, transistors M 4 -M 7 are designed at the limit between weak and moderate inversion region. Referring to Due to the low bias current, this impedance is not sufficient to perform a

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

large current to voltage conversion at the output of the mixer. To improve the conversion gain, the resistors R L are introduced. In Figure 2 Under input matching conditions, the voltage conversion gain is expressed in Eq 2.41.

V CG ≈ 1 π ω 0 (L g + L s ) R s g m1 R L (2.41) ω 0 = 1 2π (L g + L s )C gs1 (2.42)
where R s is equal to 50 Ω.

The increase of g m1 and R L improves the gain and enlarge the power is strongly inverted and the capacitance is mainly the oxide capacitance (C ox × W× L). The capacitance seen from the gate is hence given by the series of the gate oxide and the depletion oxide capacitances, the latter being smaller than the former. To further reduce the tank losses, it is important to maximize the varactor quality factor Q C . The gate resistance is proportional to the channel length L, the quality factor increases as 1/L; therefore Q C is maximum with the minimum length device. Usually the device is made up of several wide finger in parallel, in order to reduce the gate resistance. On the other hand, the fixed parasitic capacitance takes more relevance by reducing the finger width, thus reducing the achievable tuning range. W f inger =5 µm has been chosen as a tradeoff between varactor quality factor and tuning range. Figure 2.42 shows the Q C and C max to C min ratio of a varactor with W T OT =40 µm simulated for several gate lengths at 2.41 GHz. The minimum Q C largely decreases with increasing the gate length, while the tuning ratio increases. It is worth noticing that a minimum length is mandatory to achieve a high Q C at 2.41 GHz. Figure 2.43 shows the simulated C-V and Q-V characteristics, for a varactor structure with 8 fingers of 5 µm width and minimum length.

74

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Output Buffer

The buffer used in this design is a differential common-source amplifier as shown in Figure 2 Several possible causes can justify the discrepancies between post-layout simulations and measurements. One possible explanation is that the The implemented circuit proposed in this section has demonstrated the feasibility of an ultra-low power self-oscillating mixer by using design techniques such as current-reuse technique and taking benefits from moderate inversion operation. Obtained performances are deserving of respect if we consider the very low power consumption. Since the SOM in [START_REF] Sjoland | A merged CMOS LNA and mixer for a WCDMA receiver[END_REF] is designed to meet stringent noise performances, it requires much more power. Nevertheless, in wireless sensor networks applications, the noise figure of the proposed SOM could correspond to the system specifications;

Vdd M 8 M 9 M 10 M 11 R D R D to pads R s R s R 1 C 1 R 2 C 2 R 2 C 2 R 3 IF + IF - Figure 2

Measurement Results

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

82

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

such NF can ensure an acceptable sensitivity compatible with a low data rate, typically 100 kbit/s with a BFSK modulation scheme [START_REF] Song | A low-power 2.4-GHz current-reused receiver front-end and frequency source for wireless sensor network[END_REF]. To further improve the sensitivity, the SOM can be combined with a LNA for an extra power consumption of a 100 µW according to [START_REF] Taris | A 60 #x00b5;w LNA for 2[END_REF].

Conclusion

In this chapter, design approaches were presented to enable the realization of very low power RF circuits for wireless sensor networks. Two main strategies were investigated to respond to these technical challenges of low power consumption. First, bias technique was adopted and subthreshold

84

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Conclusion

device operation was explored as a method of reducing power consumption in transceiver circuits. A forward body biased transistor permits to reduce its subthreshold voltage and so the use of unusually low supply voltages. A new figure of merit g m f T /I D was also adopted to bias RF devices in order to capture both RF performances and DC power consumption. This FoM achieves its optimum in moderate inversion region so it is appropriate to operate in this region to reduce efficiently the power consumption. Second, at building blocks level, merging functionalities in a RF front-end seems to be attractive to further increase the battery life for wireless sensor's modules. Current-reuse technique was considered to meet this design requirement. Finally, to demonstrate these methodologies, a mixer and a self-oscillating mixer were designed and tested in 130 nm and 65 nm CMOS technologies. Ultimately, the ability to design RF circuits with nominal power consumption below 600 µW was demonstrated. The minimum power consumption achieved was less than 400 µW for the mixer. The

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Chapter 3

System Approach

The previous chapter presented strategies at transistor and building block levels to reduce power consumption in RF front-ends. In this chapter, a system level approach is proposed and described which Then, a demodulator system based on a pulled oscillator is proposed and investigated. Finally a test prototype is realized in 65 nm CMOS technology to demonstrate its feasibility.

Architecture Overview

There are several types of wireless receivers that allow detecting an RF signal. On one hand there are complex receivers that can detect very weak signals but consume a lot of power. On the other hand there are simple radio frequency identification (RFID) systems, which do not even have a power supply; however, they present a poor sensitivity. We can view this variety of receiver architectures on a scale of power consumption and complexity versus performance, which tend to move together on the continuum (Figure 3.1). The middle region between domains of low power passive detectors and high performance traditional wireless receivers is our target region, using architectures with acceptable power and sensitivity.

Passive Detectors

Looking first at the lower bound of the scale, an RFID tag is one of the simplest, and therefore lowest power, wireless receivers. Although passive tags do not have power supply, they are able to derive power from the incoming RF waveform and, after storing sufficient energy, power up their own electronics to decode an incoming signal and transmit back to the reader. The RFID tag remains in sleep mode until it is remotely interrogated by RF energy reader. The latter is typically not powerconstrained in RFID system and can transmit high output power, only regulatory constraints on effective isotropic radiated power (EIRP) must be respected. In the 2.4 GHz industrial-scientific-medical (ISM) band, for example, the reader may freely transmit up to 4 W EIRP for RFID applications [START_REF] Curty | Remotely powered addressable UHF RFID integrated system[END_REF]. However, in WSN applications, wireless links are peerto-peer and the power of the transmitter cannot be ignored. To further understand the effect of the transmitter power in an RFID system, consider the example of an RFID tag designed in the 2.4 GHz band [START_REF] Curty | Remotely powered addressable UHF RFID integrated system[END_REF]. A simple diagram of the system is shown in Figure 3.2, with the reported operating specifications. In active mode, the tag consumes only 1 µW. However, the RF sensitivity is poor, reported at -25.7 dBm on a 300 Ω antenna. In an RFID system, the problem can be overcome by simply transmitting higher power from the reader. This latter must transmit with 34.5 dBm output power at 2.4 GHz to communicate with the tag over a distance of 10 meters. In a peer-to-peer scenario where the transmitter is power-constrained, this power level is clearly much too high. Therefore, despite the attractive low power consumption of the RFID tag receiver, a practical compact front-end design will require much improved sensitivity in order to avoid shifting the burden of power consumption to the transmitter.

Reader

Traditional Architectures

Traditional wireless receivers lie on the other end of the scale from RFID system in Figure 3.1. In order to achieve high sensitivity and data throughput, these complex receivers utilize active devices and have much greater power consumption than passive detectors. The high-level architectures used in these receivers can generally be classified in a few major categories.

The most commonly used architecture utilizes frequency conversion, where the input signal is shifted to a lower frequency to ease implementation of signal processing blocks such as gain and filtering. Selectivity is achieved through careful frequency planning, combining narrowband low frequency responses with high purity oscillators and mixers to perform frequency

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

conversion. In super-heterodyne architecture (Figure 3.3a), for example, two consecutive downconversion operations are used. First, the input RF signal is filtered by a pass-band filter to select the band of concern. Then, the RF signal is amplified by a low noise amplifier (LNA) to ease the noise requirements of the rest of the receiver chain. Next, a mixer performs the downconversion of the RF signal to intermediate frequency (IF) with a high-accuracy, tunable local oscillator (LO1). This IF signal is amplified and filtered with a fixed frequency filter to remove the image frequency and interferes. A second mixer converts the signal to DC using a fixed frequency oscillator (LO2) at the IF frequency. and the only power consuming blocks of the receiver front-end are the VCO and the LNA. This latter has to compensate losses introduced by the poly-phase-filter and mixer. The receiver achieves a sensitivity of -102 dBm whereas consuming 26.5 mW. The LNA and frequency generation are responsible for more than 70 % of this power budget. So, despite their high sensitivity, traditional architectures are not suitable to meet the very-low power specification of compact front-ends. Clearly, the power allocated to the RF oscillator must be drastically reduced.

Compact Front-ends

As an alternative to frequency conversion architectures, the receiver can be implemented with just RF amplification and an energy detector, similar to the first AM receivers. This architecture, also called "tuned-RF" (TRF), eliminates the power-hungry LO altogether (Figure 3.4). There are two main drawbacks with the TRF architecture. First, selectivity must be provided through narrowband filtering directly at RF because the self-mixing operation is insensitive to phase and frequency. Second, high RF gain is required to overcome the sensitivity limitations of the energy detector, usually implemented with a nonlinear element like a diode. The TRF receiver is basically an enhanced version of the simple diode rectifiers used in RFID tags, which were shown earlier to have poor sensitivity. The addition of high frequency gain is expensive from a power perspective, so TRF receivers usually exhibit inferior sensitivity compared to mixing architectures for the equal power consumption. In [START_REF] Otis | An ultralow power MEMS-based two-channel transceiver for wireless sensor networks[END_REF], a TRF architecture is proposed by implementing a two-channel receiver at 2 GHz for wireless sensor networks, consuming about 3.5 mW. The receiver utilizes an OOK modulation scheme and achieves a sensitivity of -78 dBm.

However, more than 80 % of the total receiver power is dedicated to the RF gain stages, divided between the LNA at the antenna and the channelselect amplifiers. The power breakdown illustrates the critical problem with TRF architectures: providing adequate gain at RF usually requires large amounts of power. In order to overcome the gain limitations of the tuned-RF receiver, a novel architecture is proposed in [START_REF] Pletcher | A 2GHz 52 #x003bc;w wakeup receiver with -72dBm sensitivity using uncertain-IF architecture[END_REF], it is called "Uncertain-IF" (Figure 3.5). Signal amplification is performed at intermediate frequency instead of radio frequency, which requires much less power consumption than TRF architectures. Another attractive aspect of the "Uncertain-IF" topology is the minimum power needed for LO signal generation. The major focus lies on how to reduce this amount of power without considering phase noise or frequency accuracy. Of course, these are important considerations for frequency conversion architectures. However, the receiver presented in [START_REF] Pletcher | A 2GHz 52 #x003bc;w wakeup receiver with -72dBm sensitivity using uncertain-IF architecture[END_REF] overcomes these problems at the architecture level, by employing an "uncertain-IF" to ease the phase noise and frequency accuracy requirements. The relaxed specifications allow the use of a freerunning ring oscillator for LO generation. In fact, the LO signal must only be guaranteed to lie within some pre-determined frequency band ±BW if around the RF channel frequency. Then, the exact IF frequency will vary, but the downconverted signal will lie somewhere around DC within BW if .

The signal is amplified at this IF frequency, resulting in substantial power savings. Finally, envelope detection performs the final downconversion to DC. The overall system performances show a power dissipation of 52 µW and a sensitivity of -72 dBm at low data rate, 100 kbit/s. The "Uncertain-IF" architecture may be viewed as super-heterodyne, where

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

the second downconversion is simply self-mixing, obviating the need for a precise LO at the IF frequency. However, a disadvantage of this architecture is its vulnerability to interferers. Any undesired signal within ±BW if of the LO frequency that passes through the front-end filter will be mixed down and detected by the envelope detector. Therefore, a narrow and accurate RF bandpass filter is required to improve robustness to interferers. As another option to enhance gain and sensitivity at the same time, positive feedback or regeneration could be used in the amplifier. This technique was exploited at the beginning of wireless communication era [START_REF] Lee | The Design of CMOS Radio-Frequency Integrated Circuits[END_REF] to increase the gain available from the vacuum tubes at the time. One major drawback of this technique is that the amount of feedback must be tuned and carefully controlled to improve the gain without triggering oscillation. In 1922, E. Armstrong patented the super-regenerative architecture which allows the amplifier to oscillate at RF, achieving a large amount of gain from a single stage. Thus, the need for feedback tuning is no longer necessary. [START_REF] Otis | A 400 mu;W-RX, 1.6mW-TX super-regenerative transceiver for wireless sensor networks[END_REF] exploits the superregenerative technique and demonstrates the utility of this architecture for low-power receivers. Whereas consuming 400 µW, the resulting high gain preceding the detector substantially improves sensitivity, to better 94

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

than -100 dBm. Despite the impressive performance of super-regenerative receivers, the need for a high accuracy local oscillator is mandatory, with performance requirements similar to those of the frequency conversion architectures described earlier. To circumvent this stringent bottleneck, [START_REF] Yan | A 120 #x00b5;w fully-integrated BPSK receiver in 90nm CMOS[END_REF] proposes a new low-power, low-complexity BPSK demodulator (Figure 3 [START_REF] Yan | A 120 #x00b5;w fully-integrated BPSK receiver in 90nm CMOS[END_REF] locked oscillators must operate close to one-half of the receiver RF input frequency, while their free running frequencies are carefully chosen. Due to the inherent frequency selection of injection-locked oscillators, the need for any external or on-chip filtering is relaxed. However, owing to the limited free-running frequency offset of the oscillators, the implemented receiver achieves a sensitivity of -34 dBm. A power consumption of 120 µW is performed. In summary, simple RFID receivers are not sensitive enough for peer-to-peer links, while traditional frequency conversion architectures are inherently limited by LO power consumption. So, to circumvent these limits, several compact architectures have been proposed in the literature.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

One approach is to eliminate squarely the oscillator and focus on envelope detection architectures, in this case, tuned-RF and super-regenerative receivers were revisited. Unfortunately, amplifying the input signal at RF still requires a large amount of power and reducing this latter comes at the expense of the receiver's sensitivity [START_REF] Pletcher | #x003bc[END_REF]. Another option is to relax the specifications on the local oscillator to further reduce its power dissipation. However, the burden of selectivity is shifted from LO to the front-end filter [START_REF] Pletcher | A 2GHz 52 #x003bc;w wakeup receiver with -72dBm sensitivity using uncertain-IF architecture[END_REF]. These proposed compact receivers achieve very low power consumption, few tens to few hundreds of microwatts, while performing reasonable sensitivity. Nevertheless, they are limited to a fixed modulation scheme. In this chapter, we present a new architecture based on a pulled oscillator and able to demodulate three modulation schemes: AM, FM and PM. The principle of the proposed demodulator as well as its system validation are discussed in the next section.

Modulated Oscillator for envelOpe Detection (MOOD) Architecture

In order to understand the method of operation for the proposed architecture, it is useful to review Frequency Shift Keying (FSK) modulation aspects. Binary FSK is a constant envelope modulation typically used to send digital information. The data are transmitted by shifting the frequency of a continuous carrier in a binary manner to one or the other of two discrete frequencies f 1 and f 2 as shown in Figure 3.7. A non-coherent demodulation of FSK signal can be achieved by a filter-type demodulator as depicted in Figure 3.8. The received signal is split between two parallel paths, in each path the signal is first filtered by a band-pass filter to eliminate one of the two discrete frequencies and then it is envelope detected.

Finally, the envelope detector outputs are compared with a comparator

CMP DATA OUT FSK SIGNAL BAND-PASS FILTER 1 BAND-PASS FILTER 2 f 1 f 2 f 0 f 1 f 2 f 0 Figure 3.8: Non-coherent FSK demodulator
which fixes the shift between the two discrete frequencies, is usually in the range of few tens to few hundreds of Hz. Therefore, a narrow and accurate band-pass filter is required to perform an efficient selectivity. Such filters are in general costly and not suited with a low-power/lowcost solution. To circumvent the selectivity limitations of the previous topology, we propose a new architecture for a non-coherent demodulator.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

It is composed by a band-pass filter and an envelope detector as shown inFigure 3.9. The bandwidth of the pass-band filter contains the two important is to attenuate one frequency more than the other and then transform a frequency modulated signal into an amplitude modulated signal which can be detected by an envelope detector. In fact, since the filter frequency response is not centered on the carrier frequency f 0 , the roll-off of gain is not the same for the two frequencies f 1 and f 2 which leads to a strong attenuation of one coding frequency with regards to the other. If ever the filter's frequency response is centered on the carrier frequency f 0 , the FM to AM conversion will not be performed and the signal can not be demodulated, so a frequency tuned band-pass filter is required. The time evolution of the received signal through the proposed demodulator is shown in Figure 3.10. The relaxed selectivity requirements for the band-pass filter and the single signal path of the architecture extremely reduce the complexity, the power dissipation and the cost for the proposed solution in comparison with classical filter-type FSK demodulator and make it eligible to an implementation in a very low power receiver. Another attractive aspect of the proposed demodulator is its compatibility with amplitude and phase modulation. For an AM signal, it is obvious that it can be demodulated by the system since the 98 The operating principle of the proposed demodulator was exposed and discussed; it is useful now to focus on the way in which we can efficiently implement the band-pass filter. One option is to use an LC Voltage-Controlled Oscillator (VCO). LC tank has a frequency response similar to that of a band-pass filter and can be used to transform a frequency variation into an amplitude variation; the basic operation of the proposed demodulator. However, in presence of an injected signal, the oscillator could be either locked or pulled, depending on the magnitude of the

DATA OUT FSK SIGNAL f 1 f 2 f 0 BAND-PASS FILTER ENVELOPE DETECTOR S 1 S 2

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

incoming signal. While locking the oscillator is not constraining for AM signal, on the contrary, this can be profitable, a special care must be taken with FM and PM signals in order not to lock the oscillator and to have a proper demodulation. The phenomenon of injection locking or pulling [START_REF] Razavi | A study of injection locking and pulling in oscillators[END_REF], is a fundamental property of oscillators and should be investigated.

It can be observed in a wide variety of oscillator topologies with the same qualitative behavior. Studied by Adler [START_REF] Adler | A study of locking phenomena in oscillators[END_REF], Kurokawa [START_REF] Kurokawa | Injection locking of microwave solid-state oscillators[END_REF] and others

Z(ω) ≈ R p 1 + j2Q ω-ω 0 ω 0 (3.1)
With R p representing the tank losses and Q the tank quality factor. For the first case study, we consider an injected FM signal I F M :

I inj (t) = I F M (t) = I 0 cos{ω c t + β sin(ω m t)} (3.2)
Where ω c and ω m are the carrier frequency and modulating frequency respectively and β is the modulation index. The instantaneous phase and pulsation are derived as:

φ(t) = ω c t + β sin(ω m t) (3.3) ω(t) = dφ(t) dt = ω c + βω m cos(ω m t) (3.4)
Combining Eq 3.1 and Eq 3.2, the output voltage can be expressed as a superposition of the injected signal and the free-running oscillation:

V out (t) = V inj (t) + V osc (t) (3.5)

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

V out (t) = Z(ω) × I 0 cos{ω c t + β sin(ω m t)} + Z(ω 0 ) × I osc cos{ω 0 t + ϕ 0 } (3.6)
Let us focus now on the module of the output signal V out :

|V out | = |Z(ω) × I 0 cos{ω c t + β sin(ω m t)} + Z(ω 0 ) × I osc cos{ω 0 t + ϕ 0 }| (3.7)
With respect to the triangular inequality we have:

|V out | ≤ |Z(ω) × I 0 cos{ω c t + β sin(ω m t)}| + |Z(ω 0 ) × I osc cos{ω 0 t + ϕ 0 }| (3.8) |V out | ≤ |Z(ω) × I 0 | + |Z(ω 0 ) × I osc | (3.9) |V out | ≤ R p {I osc + I 0 1 + 4Q 2 ( ω-ω 0 ω 0 ) 2 } (3.10)
According to Eq 3.10, it is obvious that the module of the output voltage is modulated by the instantaneous frequency of the injected FM signal.

Therefore, a pulled oscillator transforms any angle modulated signal to an amplitude modulated one, the signal's envelope is no longer constant and its variations can be detected by an envelope detector. Consider now the situation when the injected FM signal locks the oscillator. If the amplitude and frequency of I inj are correctly chosen, the circuit oscillates at ω c instead of ω 0 and injection locking occurs. Under this condition, the output voltage (V out ) and the injected current (I inj ) must bear a phase difference φ out . It can be expressed as follow:

V out cos(ω c t+φ out ) = {I 0 cos(ω c t+β sin(ω m t))+I osc cos(ω c t+φ out )}×Z(ω) (3.11) With the complex exponential notation and after some simplifications, Eq 3.11 becomes:

V out (1 + j2Q ω c -ω 0 ω 0 ) = R p (I osc + I 0 e j(β sin(ωmt)-φout) ) (3.12)
Eq 3.12 can be separated into real and imaginary parts leading to:

V out = R p {I osc + I 0 cos(β sin(ω m t) -φ out )} (3.13) 102
Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

sin(β sin(ω m t) -φ out ) = 2Q I 0 V out R p ω c -ω 0 ω 0 (3.14)
Equation Eq 3.13 provides the output amplitude while equation Eq 3.14

gives the output phase as a function of the injected signal frequency. The oscillator is actually locked and Eq 3.13 and Eq 3.14 have solutions for a given injected frequency ω c . The correct expression for the locking range is found after substitution of V out in Eq 3.14 from Eq 3.13 and can be found in [52][55]. However, a simplified expression can be derived noticing from eq, that for small injected currents (compared to the magnitude of I osc )

V out /R p ≈ I osc . Under this assumption, the double sided locking range is easily derived substituting V out /R p with I osc in Eq 3.14 and requiring the last term to be in absolute value less than 1:

|ω c -ω 0 | ω 0 ≤ 1 2Q I 0 I osc (3.15)
It is clear in Eq 3.13 that under injection locking condition, the amplitude of the output voltage does not depend on the instantaneous frequency of the injected FM signal and thus this latter can not be demodulated because FM-to-AM conversion is not performed. The case of an injected PM signal may be considered as the same of a FM signal since we have a phase variation. So it is useful to study the same previous analytical calculations with an injected AM signal, the output voltage expression is derived under pulling and locking injection cases:

I inj (t) = I AM (t) = I 0 {1 + α cos(ω m t)} sin(ω c t) (3.16) |V out | AM,P ulling ≤ R p {I osc + I 0 (1 + |α|) 1 + 4Q 2 ( ω-ω 0 ω 0 ) 2 } (3.17) |V out | AM,Locking ≤ R p {I osc + I 0 (1 + |α|)} (3.18)
The output voltage depends on the amplitude variation of the injected signal. It is proportional to the modulation index α and achieves its maximum when the oscillator is locked. Therefore, when an injected AM

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

signal is applied, it is advantageous to operate under injection locking condition. From the previous analytical investigations, we can note that the LC oscillator plays a key role in the proposed architecture. When it is pulled, it converts any angle modulated signal at the input into an amplitude modulated one at the output. If it is locked, the latter conversion does not occur and the signal cannot be demodulated, however, this situation is beneficial for input AM signals since the output voltage reaches its maximum under injection locking condition and so a voltage gain can be performed. The proposed architecture may be viewed as a TRF receiver, where a modulated LC oscillator is introduced before the envelope detector to perform FM or PM-to-AM conversion required for the demodulation of angle modulated signals. For an ultra-low power receiver, the Modulated Oscillator for envelOpe Detection (MOOD) architecture holds several advantages over the architectures described in the first section of this chapter. First, LO phase noise and frequency accuracy requirements are significantly relaxed, resulting in consequent power savings. The envelope detector removes all phase and frequency content in the signal; it is only sensitive to the amplitude variation. As discussed earlier, it may be necessary to adjust the LO to ensure that it does not coincide with the RF channel when FM or PM signal is applied. In case of amplitude modulated RF signal, the fact of injecting the oscillator improves the magnitude of the output demodulated signal, this is useful to relax the decision bloc specifications, especially when digital modulation like OOK is used. Another advantageous aspect is the filtering behavior of the LC tank; it relaxes the selectivity requirements of the antenna filter.

However, one drawback of the MOOD architecture is its susceptibility to blockers since they can lock the oscillator and prevent the system to work correctly. Therefore, a narrow and accurate RF filter is required.

NMOS and PMOS cross-coupled pairs, is popular, as it improves phase noise, but it is also impractical for this design because it contains three stacked transistors. In order to enable operation on a low voltage supply, a standard topology is chosen with NMOS cross-coupled pair and NMOS tail device for biasing.

Oscillator Core

The schematic of the final core oscillator with input matching is shown in Figure 3.13.

Vdd L Tank C Tank C v M 1 M 2 M 3 L g L s C ext C bias R bias C v LO + LO - RF V bias V tune I bias

Circuit Design

The core bias current I bias through tail transistor M 1 is controlled by externally applied voltage V bias on the gate of M 1 . The required bias current is determined by both startup and output swing specifications. In order to decrease efficiently the power consumption of the oscillator, a loss budget of the tank must be established in order to determine the necessary negative transconductance provided from the cross-coupled pair which is equal to -1/g m2,3 in small-signal regime. The required g m for startup At the resonant frequency, the LC tank may be modeled as depicted in Figure 3.14, where the tank losses are contained in the conductance G T . The equivalent parallel resistance at resonance may be calculated by treating the capacitor as lossless and calculating the parallel conductance G T for an inductor with finite Q given by the overall tank quality factor:

L C G T -G A
R p,tank = 1 G T = Q tank ωL (3.19)
Figure 3.15 depicts the tank losses R p,tank versus frequency. At resonant frequency 2.4 GHz, the estimated R p,tank is 1290 Ω. Therefore, the minimum g m required for startup is:

g m,crit = 1 R p,tank ≈ 0.77 mS (3.20)
To ensure a reliable startup, the cross-coupled pair is designed to have a transconductance that is at least twice the minimum value. The specified transconductance is therefore fixed at 1.6 mS. Equation Eq 3.19

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Output Buffer

Output buffers are necessary for measurement in order to drive instrumentation with 50 Ω inputs. The only requirement for the buffer is that it should not load the oscillator excessively. An NMOS source follower topology was chosen due to its low input capacitance and flat gain response over a wide range of frequencies. A schematic of the output buffer design is depicted in Figure 3.17. The output impedance of the follower can be approximately considered to be 1/g m4 , requiring:

50 Ω = 1 g m4 ⇒ g m4 =
C b R D R S R 1 R 2 R f C f IN OUT C b R S M 4 M 5 M 6

Envelope Detector

The first step is to determine the nonlinear response of the envelope detector. The detection circuit can be implemented using any nonlinear circuit element, such as a diode. However, in a CMOS process it is convenient to realize the detector with the circuit shown in Figure 3.18 [START_REF] Pletcher | Ultra-low power wake-up receivers for wireless sensor networks[END_REF]. This circuit is a CMOS version of the standard bipolar topology described in [START_REF] Meyer | Low-power monolithic RF peak detector analysis[END_REF], and is basically a band-limited source follower. The

.) 2 R o C f V in V out + - - + V/I i o Figure 3 (
.19: Simple model of envelope detector to calculate conversion gain with higher order harmonics, will be filtered out by C f . Although higher order terms will also generate DC components, these contributions are small compared to the squaring term. The output impedance R o is simply 1/g m1 . Using the model in Figure 3.19, the conversion gain G from the AC input voltage to the DC output response can be calculated. First, the large signal drain current of M 1 in weak inversion is modeled as [START_REF] Gray | Analysis and Design of Analog Integrated Circuits[END_REF]:

I D = I 0 e ( V GS -V th nV t ) {1 -e ( -V DS V t
) } (3.23)

I D ≈ I 0 e ( V GS -V th nV t ) (3.24)
Where I 0 is a constant depending on process and device size, V th is the threshold voltage, V t is the thermal voltage (kT/q), and n is the subthreshold slope factor. The variables V GS and V DS are the gate-source and drain-source terminal voltages, respectively. The approximation of I D holds when the transistor is in saturation, which is valid for this source follower circuit. Next, we find DC output signal i 0 in Figure 3.19 due to an input signal V in =V s sin(ω s t). Expanding Eq 3.23 in a Taylor series and focusing on the second order term: In order to minimize loading on the preceding oscillator, the detector device sizing should be optimized for low input capacitance while still maintaining the device in weak inversion. In deep submicron technologies like 65 nm, minimum channel length should also be avoided due to the high drain-source conductance g ds observed for devices with short channel length. An additional consideration is the output bandwidth, which is determined by the output pole (Eq 3. drives the gates of M 1 and M 2 , the nonlinear bias point shift appears at the drain of the tail current source, converting the RF energy to a DC baseband signal. In order to avoid loading the oscillator excessively, the detector pair must not be sized too large. Devices M 1 and M 2 have an aspect ratio of (15 µm/0.18 µm), with current source device M 3 sized at (5 µm/0.06 µm). A 50 pF capacitor at the output filters any feedthrough from the RF signal or higher harmonics, with a baseband bandwidth of about 700 kHz. Table 3.2 summarizes the final device types and aspect ratio.

i 0 = V 2 in 2 d 2 I D dV 2 in ( 3
M 1 M 2 C f V bias M 3 V in+ V in- V bb

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Baseband Amplifier

Signals at the output of the envelope detector are quite small with about few millivolts, so a baseband amplifier is needed here in order to deliver a measurable signal to the test equipments, in our case it will be an oscilloscope probe. The circuit is based on a basic common source topology with resistive load as depicted in

Results

After the description of the system design parameters, the system simulations and measurement results are presented and discussed in this section.

Complete System Post-layout Simulations

In order to validate the analytical calculations of section 3.2, system simulations were performed using Goldengate simulator in Cadence environment and after extracting parasistic capacitors and resistors. First, the oscillator voltage gain is simulated when an AM signal is applied. Then, system validation results with OOK and FSK modulation are presented.

Figure 3.24 shows the spectrum at the output of a pulled LC oscillator when an amplitude modulated signal is applied. In this case we define the oscillator's voltage gain as the ratio of the highest output sideband level of the AM signal over its input sideband level. This voltage gain versus ∆f is depicted in Figure 3.25. It is clear that the oscillator performs more gain when the RF signal is close to the LO one. As we move away the free-running frequency, the voltage gain drops and follows the frequency response of the LC tank. Therefore, when AM signal is applied, it is better to operate closer to the LO frequency and even inject the oscillator, where the maximum gain is achievable. This helps to improve the sensitivity of the system. To further confirm the comments above, 120 LO frequency is tuned to achieve different simulation setups. Figure 3.27 shows the voltage amplitude V det at the envelope detector's output in the case of OOK modulation and for different distance ∆f between the RF and LO frequencies.

Pulled LC oscillator f RF f LO f RF f G V AM input signal

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Measurement Results

The prototype system was fabricated in 65 nm standard CMOS technology from STMicroelectronics. All measurements were performed with singleended ground-signal-ground (GSG) probe at the input and a differential GSGSG probe to sense the LO output. A bias-T was introduced at the input port for variable DC bias voltage to control the transconductance stage of the oscillator. Oscillation frequency and output power were measured with a Rhode&Schwartz FSUP (20 Hz-26.5 GHz) source analyzer.

The modulated signals were generated by a Rhode&Schwartz signal generator and the time domain measurements were obtained with an Lecroy wavepro 960 2 GHz oscilloscope. Finally, supply and bias voltage were generated by Agilent E3631A DC power supply.

Standalone envelope detector and LO measurements

The LC oscillator and the envelope detector are two main blocks in MOOD system. standalone test blocks are included on the prototype chip for characterization purposes. A die photo of the single envelope detector is depicted in Figure 3.28. The total area is about 0.64 mm 2 . The circuit consumes 1.5 µA from 0.5 V supply. For system functionality, the most moderate inversion region while the supply voltage is varied. This verifies the functionality at low supply voltages. Secondly, the bias current is swept while supply voltage is held constant at a nominal value. This measurement demonstrates the performance for different transistor regions of operation. Figure 3.32 shows the measured oscillation frequency and output power as V DD is swept from 0.5 V to 1 V. The nonlinear device 0,4 0,5 0,6 0,7 0,8 0,9 Note that Figure 3.33 illustrates a linear dependence of output power on bias current, between 200 and 400 µA, confirming that the oscillator is operating in the current-limited regime. This is because the output swing is small enough and is not being limited by the available voltage headroom. In order to measure phase noise, all supply voltage generators were turned off to reduce their noise contributions. Bias voltages are internally generated except for V bias which controls the oscillator tail current. For this measurement, V DDosc and V DDbuf are set at 0.5 V and 1 V respectively. Figure 3.34 illustrates the effect of bais current variation on phase noise at a fixed 1 MHz offset. Spot noise is plotted for Ibias ranging from 200 µA to 1500 µA. The phase noise exhibits a minimum phase noise of -100 dBc/Hz in MI region. Beyond this point, the phase noise increases rapidly since the oscillator operates in voltage-limited regime. To measure the oscillator's tuning range, the varactor drain/source voltage is tuned from 0 V to 2 V.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Results

The oscillator is the main block in MOOD system since it performs, under pulling condition, the FM-to-AM conversion required for demodulation.

So, it is important to examine the oscillator's frequency response when an external signal is applied. For this measurement, the oscillator is held at nominal bias conditions and a continuous wave is injected with a total power of -31 dBm. First, as depicted in Figure 3.36, the frequency of this continuous wave is changed and its power level is measured at the oscillator's output. The output power follows the frequency response of the free-running oscillator with a maximum achievable gain of 6 dB at 1 MHz shift from the free-running oscillation. Beyond this frequency shift, the oscillator is locked. Therefore, the locking range is about 2 MHz. In It is clear that as we get far from the free-running oscillation, a larger amount of power is required to lock the oscillator. This point limits the sensitivity of the overall system.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

The peak-to-peak output voltage increases with modulation depth in all configurations (AM, FM and PM). In AM case (Figure 3.41a), the demodulated amplitude grows linearly as the carrier frequency is close to the LO one. It reaches its maximum when the oscillator is locked.

However, in FM and PM cases, the fact of locking the LO does not help to demodulate the signal. These measurement results confirm the analytical calculations discussed in section 3.2. In Figure 3.40, the carrier power P carrier was varied, whereas the carrier and modulating frequencies were kept constant. An idea about the sensitivity range for MOOD system could be deduced from these results. When an AM input signal is applied, a carrier power level of -20 dBm helps to get 20 mV of peak-to-peak output voltage. On the other hand, the sensitivity is lower in case of FM or PM input signals. Carrier power should be increased to correctly demodulate the signal without reaching the injection level. Figure 3.41 demonstrates the demodulated amplitude for different modulating frequencies f m , carrier frequency and power were held constant. Up to 300 kHz, the peak-topeak output voltage increases linearly with the modulating frequency.

Beyond this point, it falls down. This limited level is fixed by the envelope detector's bandwidth which was measured to 300 kHz.

The implemented prototype proposed in this section has demonstrated the feasibility of an ultra-low power compact RFFE by using an original technique to demodulate a RF signal. This helps to considerably reduce the system power consumption in comparison with frequency conversion architectures. The principle of operation of the proposed demodulator was validated with three analog modulation scheme (AM, FM and PM).

If we consider the very low power consumption of the MOOD system (≈120 µW for the core), its performances are good. The limited sensitivity is caused by the lack of amplification at RF signal and could be improved by introducing a LNA before the oscillator.

132

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Conclusion

In this chapter, an approach at system level was presented and investigated to further reduce the power consumption of radio frequency front-end in wireless sensor networks. First, an overview of the existing solutions in the literature was given. Their advantages and drawbacks were discussed. Then, equipped with this investigation, a Modulated Oscillator for envelOpe Detection (MOOD) architecture was proposed. It is based on a pulled oscillator that converts a frequency modulated signal to an amplitude modulated one. The baseband conversion is performed by the envelope detector. In order to demonstrate the feasibility of this system, a prototype was designed and carried out in 65 nm CMOS technology. A standalone oscillator and envelope detector were included in the test prototype for characterization purposes. The measurement results illustrate the feasibility of an ultra-low power LC oscillator with power consumption of 120 µW. MOOD system was tested under different conditions to investigate its limits. Locking the oscillator helps to achieve a maximum of peak-to-peak output voltage when an AM signal is used. However, the oscillator must stay far from the locking range in case of FM or PM for proper demodulation. The sensitivity of the demodulator is mainly limited by the noise figure of the system, since no low noise amplification is performed. In AM case, the sensitivity is estimated to less than -30 dBm.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Chapter 4

Conclusions

Performance Summary

This thesis investigates the design of ultra low power radio frequency circuits for wireless sensor networks. Such networks require a low power consumption, a low cost and a high level of integration. Accordingly, the implementation of a wireless sensor node needs a careful choice at different design steps: protocol, system, circuit and transistor levels. This thesis focuses on lowering power dissipation of the radio communication since it is the most power hungry part of a sensor node. Moreover, it is also the most promising module to address system challenges.

This research work includes both circuit and system level approaches. First is exploited the subthreshold operation of MOS device. This technique enables the design of very low power circuits using low supply voltages. In the building block approach, the figure of merit g m f T /I D is explored to bias the transistor in moderate inversion region where current efficiency and RF performances can be achieved at the same time. RF for a fixed bias current, as it will be used later in the proposed system to inject RF signals. These efforts lead to a minimum power consumption of 100 µW from a 0.5 V supply. At nominal bias, the circuit achieves an output power of -24 dBm and a phase noise of -100 dBc/Hz at 1 MHz offset.

Regarding the system approach, an original idea is patented with ST Microelectronics, namely Modulated Oscillator for envelOpe Detector (MOOD). It consists in the use of a pulled LC oscillator to convert a frequency or phase modulated signal into an amplitude modulated one and then perform the conversion to baseband with an envelope detector.

138

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Future Work

It has been shown that putting the oscillator under pulling condition helps to demodulate angle modulations. When the oscillator is locked to the injected signal, FM or PM demodulation does not occur. However, this condition is advantageous for amplitude modulation since a maximum of gain, introduced by the oscillator, can be achieved. Using the ultra-low power oscillator designed in the circuit approach, the core of the system has a power consumption of roughly 120 µW. A sensitivity less than -30 dBm could be achieved when an AM signal is applied.

Future Work

The main goal of this research activity is the realization of an ultra low power RF receiver for wireless sensor networks with active power consumption less than 1 mW. To achieve this goal, design methodologies and techniques for low power RF circuits are required. The techniques described and applied in this work are one step towards the realization of a very low power receiver. They have resulted in the development of a system solution that consumes roughly 700 µW for the MOOD based receiver.

It is important to note that the overall gain of the proposed system is supported by the baseband amplifier which consumes more than 50 % of the total power consumption. This amplifier is added for measurement purposes. A future development would consider the introduction of a low noise amplifier to improve the sensitivity of the system. At the high end, an operational amplifier is needed to provide an adequate amplification to the baseband signal. Depending on the input signal level, the LNA gain must be variable to allow the oscillator to work either under pulling condition in case of constant envelope modulation or under locking condition when a variable envelope modulation is applied.

Future development in RF-MEMS may provide exciting alternatives to

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

exciting on-chip passive components. In the proposed LC oscillator, the low quality of the integrated inductors sets the lower bound on power consumption of the oscillator core. The use of MEMS resonator structures in transceiver circuits is an area for future exploration, as these components may help to reduce the power consumption by eliminating the dependence on low Q passives. Another advantageous aspect is to shift the selectivity burden to the RF-MEMS filter and relax the constraints on the oscillator.

3. 14

 14 Simple model of oscillator as resonant tank . . . . . . . . . . . . . . . . . 3.15 Tank losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 Phase noise versus bias current I bias . . . . . . . . . . . . . . . . . . . . . 3.17 Schematic of the output buffer . . . . . . . . . . . . . . . . . . . . . . . . 3.18 Schematic of basic envelope detector circuit in CMOS . . . . . . . . . . . 3.19 Simple model of envelope detector to calculate conversion gain . . . . . . 3.20 Simulated conversion gain of the envelope detector . . . . . . . . . . . . . 3.21 Circuitry of the differential envelope detector (Bias not shown) . . . . . . 3.22 Schematic of the baseband amplifier (Bias not shown) . . . . . . . . . . . 3.23 Simulated baseband amplifier frequency response . . . . . . . . . . . . . . 3.24 Pulled oscillator's output spectrum in presence of AM signal . . . . . . . 3.25 Oscillator's voltage gain versus ∆f . . . . . . . . . . . . . . . . . . . . . . 3.26 Testbench simulation for system validation . . . . . . . . . . . . . . . . . 3.27 Envelope detector's output voltage in OOK setup . . . . . . . . . . . . . . 3.28 Die photo of the envelope detector . . . . . . . . . . . . . . . . . . . . . . 3.29 Measured bandwidth and conversion gain of the envelope detector . . . . 3.30 Die photo of the LC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 3.31 Measured output spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . 3.32 Measured oscillation frequency and output power for different V DD . . . . 3.33 Variation of oscillation frequency and output power for range of I bias . . . 3.34 Oscillator's phase noise for different bias current . . . . . . . . . . . . . . 3.35 Tuning range of the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 3.36 Output power for different frequencies of a continuous wave . . . . . . . . 3.37 Required injection power for different ∆f . . . . . . . . . . . . . . . . . . 3.38 Measurement setup for system validation . . . . . . . . . . . . . . . . . . 3.39 Demodulated amplitude versus f carrier . . . . . . . . . . . . . . . . . . . . 3.40 Demodulated amplitude versus P carrier . . . . . . . . . . . . . . . . . . . . 3.41 Demodulated amplitude versus f m . . . . . . . . . . . . . . . . . . . . . . viii Ultra-Low Power RFIC Solutions for Wireless Sensor Networks List of Tables 1.1 Average power density of various energy storage and scavenging devices [7] 2.1 Operating regions of the MOS transistor . . . . . . . . . . . . . . . . . . . 2.2 Sizes of mixer devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Performance summary and comparison to other CMOS mixers . . . . . . 2.4 Sizes of SOM devices (core and buffer) . . . . . . . . . . . . . . . . . . . . 2.5 Performance summary and comparison to other SOM . . . . . . . . . . . 3.1 Sizes of Oscillator devices (Core and buffer) . . . . . . . . . . . . . . . . . 3.2 Sizes of envelope detector devices . . . . . . . . . . . . . . . . . . . . . . . 3.3 Sizes of baseband amplifier devices . . . . . . . . . . . . . . . . . . . . . . ix

  .4 qui est consacrée aux réseaux sans fil personnels à faible débit et à faible portée (LR-WPAN) dans la bande de fréquences radio sans licence ISM (868 MHz/915 MHz/2.4 GHz). La faible consommation d'énergie, le faible coût de mise en oeuvre et le niveau d'intégration élevé sont les principaux défis de ces systèmes. Le module radio est le bloc le plus gourmand en énergie dans un noeud capteur, sa consommation de puissance doit donc être réduite. Pour ce faire, plusieurs approches sont possibles, soit au niveau circuit en exploitant les modes de fonctionnement du transistor ou en fusionnant les fonctionnalités des blocs qui constituent un front-end radiofréquence. Soit au niveau système en examinant de nouvelles architectures de démodulation. Cette thèse explore les exigences et les défis spécifiques pour la réalisation d'un mélangeur à très faible consommation fonctionnant en zone d'inversion modérée et consommant 330 µW. Un second circuit combinant l'oscillateur local et le mélangeur a été conçu et réalisé en technologie CMOS 65 nm. Le "Self-Oscillating Mixer" (SOM) fonctionne à une fréquence radio de 2.4 GHz et consomme 600 µW sous une tension d'alimentation de 1 V. Enfin, un démodulateur compact a été réalisé en technologie CMOS 65 nm. Il utilise une nouvelle architecture pour démoduler toutes les modulations analogiques, cette approche se base sur la théorie de synchronisation des oscillateurs. Le système proposé consomme uniquement 120 µW sous une alimentation de 0.5 V et permet d'atteindre une sensibilité inférieure à -30 dBm dans le cas d'une modulation AM.

Figure 1 . 1 :

 11 Figure 1.1: Hardware blocks for wireless sensor network implementations

Figure 1 . 2 :

 12 Figure 1.2: Radio range for receiver with a -70 dBm sensitivity

Figure 1 .Figure 1 . 4 :

 114 Figure 1.4: Synchronizing "awake" period among nodes

Figure 1 . 5 :

 15 Figure 1.5: Protocol-based duty-cycle control: transmitter initiated

Figure 1 . 6 :

 16 Figure 1.6: Duty-cycle control with wake-up receiver

Figure 1 . 7 :

 17 Figure 1.7: Direct conversion receiver proposed in [1]

Figure 1 . 8 :

 18 Figure 1.8: Block diagram of the proposed transceiver in[START_REF] Cook | Lowpower 2.4-GHz transceiver with passive RX front-end and 400-mV supply[END_REF]

Figure 1 . 9 :

 19 Figure1.9: Proposed transceiver in[START_REF] Kluge | A fully integrated 2[END_REF]

1. 4

 4 Thesis organizationa careful choice of the transceiver architecture, they can be reached only by combining this choice with proper design strategies. As shown in the state of the art overview, cost minimization requires to reduce the number of integrated coils and external components.

Figure 2 . 1 :

 21 Figure 2.1: ITRS projections for CMOS supply voltage scaling

Figure 2 . 2 :Figure 2 . 3 :

 2223 Figure 2.2: A conceptual illustration of the cascode architecture

Figure 2 . 4 :

 24 Figure 2.4: The complementary current-reused mixer with a current-bleeding technique

Figure 2 .Figure 2 . 5 :

 225 Figure 2.5: Forward-body bias technique

Figure 2 .Figure 2 . 6 :Figure 2 . 7 :

 22627 Figure 2.7 shows the threshold voltage versus back-gate forward bias for NMOS transistor in 65 nm CMOS process. It can be clearly seen that an increase in the back-

Figure 2 .

 2 Figure 2.8: g m /I D and f T for a modern CMOS 130 nm process

Figure 2 . 9 :Figure 2 .

 292 Figure 2.9: Comparison of f T with technology scaling

  Figure 2.11b. Conversion process in time domain is performed by multiplying the RF signal by local oscillator (LO) signal.

Figure 2 .

 2 Figure 2.11: Mixer principle

3 )

 3 CG voltage = IF output voltage (rms) RF input voltage (rms) (2.4) -Noise Figure: The noise figure is defined as the signal-to-noise ratio (SNR)

Figure 2 . 14 :Figure 2 . 15 :

 214215 Figure 2.14: Noise folding mechanism

Figure 2 . 16 :

 216 Figure 2.16: Mixer linearity mechanism

  Current-reuse bleeding mixer

Figure 2 . 18 :

 218 Figure 2.18: Various configurations of active mixers

  and A: LO amplitude. Hence, the transductor current (I bias ) needs to be enhanced without varying the switching current to improve the gain, the linearity and lower the noise figure in a conventional current commuting mixer. It is completed by the circuit of Figure 2.18b [35]. The principle is based on an additional current source, the bleeding transistor (M bleeding ), which steers the current pulled into the RF stage. By means, the DC current flowing into the switching pair is no longer controlled by the transductor stage. As well the tradeoff relying on the biasing current of the RF transistor is completely relaxed. The configuration of Figure 2.18b, can evolve to the topology of Figure 2.18c, which takes advantages of both bleeding and current-reuse techniques. The p-channel transistor (M bleeding ) is used as a

Figure 2 . 19 .

 219 Figure 2.19. The capacitor C f is used to decouple the biasing of M 1 and M 4 .

Figure 2 . 19 :

 219 Figure 2.19: Circuitry of mixer core

16 )Figure 2 . 20 :

 16220 Figure 2.20: Schematic of the source followers

Figure 2 . 22 :

 222 Figure 2.22: Simulated voltage conversion gain and SSB noise figure versus R f at 10 MHz IF. LO power is -1 dBm

Figure 2 . 23 :Figure 2 . 24 :Figure 2 . 25 .

 223224225 Figure 2.23: Input return loss S 11 for various R f

Figure 2 . 25 :

 225 Figure 2.25: IIP3 and ICP1 of Mixer at 330 µW power consumption

Figure 2 .Figure 2 . 26 :

 2226 Figure 2.26: Ideal inductor capacitor resonator

Figure 2 . 27 :

 227 Figure 2.27: Tank serie and parallel losses

27 )

 27 To guarantee oscillations start-up under Process-Voltage-Temperature (PVT) variations the negative conductance is designed with a factor of 1.5 to 3 times larger than the required minimum. There are several circuits able to provide negative conductance (or resistance), leading to a wide variety of oscillator topologies[START_REF] Lee | The Design of CMOS Radio-Frequency Integrated Circuits[END_REF][START_REF] Razavi | RF Microelectronics[END_REF]. Among them, the widely used circuit topology of a CMOS LC tank oscillator is depicted in Figure 2.28. It is commonly preferred for several reasons: * It requires a minimal number of active (and noisy) components, resulting in low phase noise * It requires a minimal number of passive components, and thus low silicon area * It is very easy to insert variable capacitors to tune the output frequency * It is a differential topology providing two anti-phase (180 • shifted) output signals. Differential topology is inherently less sensitive to commonmode noise, such as supply voltage variation and substrate noise, it also intrinsically remove even order distortions. The differential resonator of the Figure 2.28 is composed by two LC tanks where the parallel losses are represented by R peq . When the tail transistor is biased in saturation region the circuit gives the differential negative conductance to compensate the tank losses. The small signal differential

Figure 2 . 28 :

 228 Figure 2.28: Circuit schematic of negative resistance LC CMOS Oscillator

Figure 2 . 29 :Figure 2 . 30 :

 229230 Figure 2.29: Ideal and real oscillator spectrum

Figure 2 . 34 :

 234 Figure 2.34: Block diagram of the proposed self-oscillating mixer

Figure 2 . 35 :

 235 Figure 2.35: g m f T /I D versus V GS for LP and GP transistors

Figure 2 . 37 :

 237 Figure 2.37: Single-ended and differential configurations for cross-coupled pair

Figure 2 .Figure 2 .

 22 Figure 2.38: gm/I D for a (30 µm/0.06 µm) nlvtgp transistor in 65 nm process

  consumption too. The impact of R L on conversion gain and noise figure was investigated and depicted in Figure 2.40. For this SOM, R L is made large, 1.5 kΩ, ensuring a sufficient voltage headroom for the switching pair (M 2 , M 3 ) of the mixer. The overdrive voltage is fixed to zero for

Figure 2 . 40 :

 240 Figure 2.40: Voltage conversion gain and noise figure versus R L

Figure 2 . 41 :

 241 Figure 2.41: Cross section of I-MOS varactor

2. 3 Figure 2 . 42 :Figure 2 . 43 :

 3242243 Figure 2.42: Varactor quality factor and C max /C min versus transistor length

. 44 .

 44 Capacitor C 2 of 10 pF is used for DC blocking and resistor R 2 of 10 kΩ for self-biasing transistor M 10,11 which is placed in saturation region. The transistor size of M 10,11 and the load resistor R D are designed to provide a 1 V/V voltage gain and does not significantly affect the linearity of the SOM. The value of load resistor must also contribute for output matching, it is fixed to 140 Ω. A low-pass filter (R 1 ,

Figure 2 .

 2 Figure 2.45 shows a microphotograph of the implemented SOM in a 65 nm CMOS technology from STMicroelectronics. A single-ended ground-signalground (GSG) probe was used to generate RF input signal and a differential GSGSG probe to sense the IF signal. A bias-T was introduced at the input port for variable DC bias voltage to control the transconductor stage through Bias RF . An external 180 • hybrid is needed at the IF port to convert the differential output into a single-ended signal. Supply and bias voltages were generated by an Agilent E3631A DC power supply. Bias voltages was tuned to get best gain and noise performances, the nominal bias conditions are I bias =600 µA and V DD =1 V. The varactor control voltage is fixed for an oscillation frequency of 2.6 GHz. The input return loss of the circuit is depicted in Figure 2.46. It was measured using an Agilent E8361A PNA network analyzer. At the designed RF input

Figure 2 Figure 2 . 46 :

 2246 Figure 2.45: SOM microphotograph

Figure 2 . 47 :

 247 Figure 2.47: Tuning range of the SOM

Figure 2 . 48 :Figure 2 . 49 :

 248249 Figure 2.48: Voltage conversion gain at different IF frequencies

Figure 2 . 50 :Figure 2 . 51 :

 250251 Figure 2.50: Voltage conversion gain and I bias versus Bias RF

2. 3 Figure 2 . 52 :Figure 2 . 53 :

 3252253 Figure 2.52: Measured input compression point ICP1

  circuit was biased to run in moderate inversion and operation with a supply voltage of less than 1 V was also demonstrated. Post layout simulations show a voltage conversion gain and a single side band noise figure of 18.7 dB and 11.5 dB respectively at an intermediate frequency of 10 MHz. Regarding the self-oscillating mixer, the circuit consumes 600 µW and measurement results demonstrate a voltage conversion gain of 10 dB and a single side band noise figure of 17.5 dB whereas the LO to IF feedthrough is -64 dBm.

  uses a novel architecture to demodulate RF signals. The classical architectures existing in the state-of-the art are first discussed.

Figure 3 . 1 :

 31 Figure 3.1: Receiver design space in terms of power consumption

Figure 3 . 2 :

 32 Figure 3.2: RFID link operating parameters

  Direct conversion or low-IF architecture

Figure 3 . 3 :

 33 Figure 3.3: Traditional receiver architectures

Figure 3 . 4 :

 34 Figure 3.4: Tuned-RF (TRF) architecture

Figure 3 . 5 :

 35 Figure 3.5: "Uncertain-IF" architecture

. 6 )Figure 3 . 6 :

 636 Figure 3.6: BPSK demodulator in[START_REF] Yan | A 120 #x00b5;w fully-integrated BPSK receiver in 90nm CMOS[END_REF]

Figure 3 . 7 :

 37 Figure 3.7: FSK modulation

Figure 3 . 9 :

 39 Figure 3.9: Proposed FSK demodulator

Figure 3 . 10 :

 310 Figure 3.10: Time evolution of the received signal with the proposed architecture

[ 55 ]Figure 3 . 11 :

 55311 Figure 3.11: Simplified behavioral model for injection pulled oscillator

Figure 3 . 13 :

 313 Figure 3.13: Schematic of the oscillator core

Figure 3 . 14 :

 314 Figure 3.14: Simple model of oscillator as resonant tank

Figure 3 .Figure 3 . 16 :

 3316 Figure 3.15: Tank losses

Figure 3 .

 3 Figure 3.17: Schematic of the output buffer

  operation of the circuit in CMOS is similar to the bipolar version if device M 1 is biased in weak inversion, where its drain current is an exponential function of gate-source voltage instead of the weaker nonlinearity of squarelaw behavior in strong inversion. Device M 2 acts as a simple current source to bias M 1 with a constant current. A large filter capacitor C f is connected to node V out . The bandwidth at the output is set by the pole f p,det formed by C f and the output impedance of the detector, which is yields the simple model shown in Figure3.19, where the detector circuit is modeled as squaring function that converts an input voltage V in to an output current i o . The linear term at the fundamental frequency, along

Figure 3 . 20 :

 320 Figure 3.20: Simulated conversion gain of the envelope detector

Figure 3 . 21 :

 321 Figure 3.21: Circuitry of the differential envelope detector (Bias not shown)

Figure 3 . 22 .Figure 3 . 22 :

 322322 Figure 3.22: Schematic of the baseband amplifier (Bias not shown)

Figure 3 . 23 :

 323 Figure 3.23: Simulated baseband amplifier frequency response

Figure 3 . 24 :

 324 Figure 3.24: Pulled oscillator's output spectrum in presence of AM signal

Figure 3 . 25 :Figure 3 . 26 :

 325326 Figure 3.25: Oscillator's voltage gain versus ∆f

Figure 3 . 27 :

 327 Figure 3.27: Envelope detector's output voltage in OOK setup

Figure 3 . 28 :Figure 3 . 29 :Figure 3 . 31 :

 328329331 Figure 3.28: Die photo of the envelope detector

Figure 3 . 32 :

 332 Figure 3.32: Measured oscillation frequency and output power for different V DD

Figure 3 . 33 :

 333 Figure 3.33: Variation of oscillation frequency and output power for range of I bias

Figure 3 . 34 :Figure 3 .Figure 3 . 35 :

 3343335 Figure 3.34: Oscillator's phase noise for different bias current

Figure 3 . 36 :Figure 3 . 37 ,

 336337 Figure 3.36: Output power for different frequencies of a continuous wave

Figure 3 . 37 :Figure 3 .Figure 3 . 38 :Figure 3 . 39 :

 3373338339 Figure 3.37: Required injection power for different ∆f

Figure 3 . 40 :Figure 3 . 41 :

 340341 Figure 3.40: Demodulated amplitude versus P carrier

  Forward body bias is used to further reduce supply voltages of the circuits. Three circuits are designed using the proposed techniques: a current switching mixer, a self-oscillating mixer and a LC tank oscillator. A single balanced topology is selected to implement the mixer since it introduces less noise than a double balanced configuration and do not require a balun to perform the connection with the LNA. The circuit exploits bleeding and currentreuse technique to further improve the performances. The transistor of transconductor stage is biased in moderate inversion region and it has been demonstrated that this operating mode maximizes the mixer's figure of merit in comparison with the ones biased in strong inversion region.A voltage conversion gain and single side band noise figure of 18.7 dB and 11.5 dB respectively are achieved for a power dissipation of 330 µW from a 0.8 V supply. Concerning the self-oscillating mixer, a cross-coupled LC oscillator is stacked on the top of a single ended mixer to share the same bias current, and therefore, to lower the power consuption. The SOM consumes 600 µA from a 1 V supply voltage and performs a voltage conversion gain and a single side band noise figure of 10 dB and 17.5 dB respectively. Finally, a LC voltage controlled oscillator is designed and tested. The cross-coupled pair operates at the limit between weak and moderate inversion region to optimize the current efficiency for minimal bias current. The tail transistor operates in moderate inversion region to achieve at the same time a high current efficiency and maximum gain at

Table 1 .

 1 1: Average power density of various energy storage and scavenging devices[START_REF] Roundy | energy scavenging for wireless sensor nodes with a focus on vibration to electricity conversion[END_REF]

	Power Source	Power Density µW cm -3 Lifetime
	Lithium Battery	100	1 year
	Micro Fuel Cell	110	1 year
	Solar Cell	10-15000	∝
	Vibrational Converter	375	∝
	Air Flow	380	∝
	Temperature Gradients	50	∝

16 Ultra-Low Power RFIC Solutions for Wireless Sensor Networks 1.3 Challenges

	and other well-known wireless technologies is the ability of sensor nodes to forward
	messages from another one located further down in the communication chain. This
	technique, known as mesh routing or multi-hop networking, provides an effective and
	reliable means of spanning large infrastructures, beyond the range of what a single

LO ≠f in DSB ⇒ f LO =f in

  One is the desired RF signal and the other is called the image signal as shown in Figure 2.12. The reason that two such frequencies exist is that the IF is simply the magnitude of the difference between the RF and LO frequencies. Hence, both signals above and below ω LO at (ω LO ± ω IF ) will produce outputs at the same frequency ω IF . The two input frequencies are therefore separated by 2ω IF . In a heterodyne architecture, f in = f LO , the SN R out is half of the SN R in because the noise originating in both the desired and image frequencies are added in IF signal according to the illustration of Figure 2.13. In such a case, the NF is referred as Single Side Band (SSB). In a homodyne architecture, f in =f LO , there is no image frequency and the SN R in is kept the same at IF. This situation is referenced as Double Side Band (DSB).In a mixer, the noise is also replicated and translated by each harmonic of

																										Signal Band	Image Band	4
																										π	4
																										4	π 3	4
	SLO(t)																								π	4	π 5
	+1																									π 3	4 π 5	f LO 3f LO 5f LO
	-1	S	2π/ωLO 4 ) ( = t LO π	cos( ω LO	t	)	3 4 -π		f LO Figure 2.12: Image band f LO 3f LO 5f LO x n (t) f in LO signal is a square wave ... ) 3 cos( + t LO ω S LO (t)	y	n	(	t	)	a	k	e	jk	LO	t	.	x	n	(	t	)
		a 1	e	j	LO ω	t	e + 1 a -	-	j	LO ω	t					a 3	e	j	LO ω 3	t	a -3 +	e	j -	LO ω 3	t
									S	LO	(	t	)	∑ + ∞ ∞ -=	a	k	e	jk ω LO	t	with	a k	=	π 4 k
																										SSB	DSB
																										RF Signal	Image Signal	RF Signal
	Thermal + S RF (t)		Noiseless mixer											Thermal Noise	f in	f LO	Thermal Noise	f LO =f in
	Noise
			S LO (t)
	LO signal is a pure sine wave
																										Thermal Noise	Thermal Noise
																										0	0
																										SNR out =SNR in /2	SNR out =SNR in
																										⇒ NF=3dB	⇒ NF=0dB
												Figure 2.13: SSB and DSB noise figure
	the LO, this mechanism is called "noise folding". Larger gain and lower noise
	contribution are produced by square LO signal [31]. Unfortunately, this latter
	generates harmonics and so "noise folding" as depicted in Figure 2.14.
	-Port-to-Port Isolation: The principle of frequency shift which is a typical
	non linear operation makes the port to port isolation a critical parameter

[START_REF] Wang | A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology[END_REF]

In a typical mixer, there are actually two frequencies that will generate a given intermediate frequency.

SSB ⇒ f

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Table 2 .

 2 2: Sizes of mixer devices Bias RF is set to 360 mV allowing transistor M 1 to operate in moderate inversion region. Bias LO sets the overdrive voltage (V GS -V T H ) of the switching pair (M 2 , M 3 ) to zero for an ideal switch. DC current flowing through M 1 and M 4 is 410 µA.Figure 2.22 shows the voltage

	Device	Size	Device	Size
	M 1 (W/L)	14 µm/0.13 µm	C f	10 pF
	M 2,3 (W/L)	6 µm/0.13 µm	C L	2 pF
	M 4 (W/L)	24 µm/0.13 µm	L g	12 nH
	M 5,6 (W/L) 120 µm/0.13 µm	R L	2 KΩ
	M 7,8 (W/L) 30 µm/0.13 µm	R f	5 KΩ
	C	10 pF	R	5 KΩ

chip size is 0.745 mm 2 including all the pads. Empty space of the chip are filled by decoupling capacitors to filter out the variation of supply voltage. The proposed ULP mixer operates in 2.4 GHz ISM Band. The frequency Figure 2.21: Snapshot of the mixer layout plan used for simulations is: a 2.4 GHz RF signal, a 2.41 GHz LO signal and a 10 MHz IF intermediate frequency. The mixer core consumes 330 µW under 0.8 V supply voltage.

52 Ultra-Low Power RFIC Solutions for Wireless Sensor Networks 2.2 Ultra-Low Power

  2.4 GHz Down Conversion Mixerconversion gain and noise figure for various values of the feedback resistance R f . Both characteristics improve with increasing R f . The feedback resistance

		20						20
		18						18
								NF
	NF (dB)	14 16						VCG	14 16	VCG (dB)
		12						12
		10						10
		1K	2K	3K	4K	5K	6K	7K
					R f	( )

Table 2 .

 2 3 summarizes the performances of the proposed circuit and various low

54 Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Table 2 .

 2 3: Performance summary and comparison to other CMOS mixers

	Ref.	Techology	RF	IF	P LO	VDD	P DC	Gain	NF	IP1dB	IIP3	LO-RF	LO-IF	FOM
		CMOS[nm]	[GHz]	[MHz]	[dBm]	[V]	[mW]	[dB]	[dB]	[dBm]	[dBm]	[dB]	[dB]	[dB]
	This work	130	2.4	10	-1	0.8	0.33	18.7	11.5	-21	-14.9	28	43	-12.2
	[36]	130	2.4	60	-9	1	0.5	15.7	18.3	-28	-9	33	22	-16.3
	[37]	130	2.5	10	-1	0.6	1.6	5.4	14.8	-9.2	-2.8	70.9	54.2	-16.8
	[37]	130	2.5	10	-1	0.8	7.8	15	8.8	-16.9	-9.5	71.1	54.2	-19.1
	[38]	180	2.4	1	-2	1	3.2	11.9	13.9	-	-3	-	-	-15.8
	[39]	180	2.4	30	-2	1.8	1	32	8.5*	-	-14.5	60.5	-	-9.6
	[40]	180	2.4	10	0	0.8	2	14.5	17.1	-22	-11	-	-	-23
	*Double Side Band
		It is not worthy the 3 best FOMMixer: this work, [38] and [39] bias the
		transistor in moderate inversion or close to the subthreshold voltage (V th ). This
		point figures out the interest in operating devices out of the Strong Inversion

Ultra-

Low Power RFIC Solutions for Wireless Sensor Networks (

  SI) mode, typically in WI or MI, to address very low power applications in advanced CMOS technologies. Considering a comparison between our

64 Ultra-Low Power RFIC Solutions for Wireless Sensor Networks 2.3 Ultra-Low Power

  .32). In such configuration, the LO output signal is generated

2.4 GHz Self-Oscillating Mixer (SOM) by a nMOS differential VCO which is directly fed into the source of a switching pair. This topology can operate under very low voltage supply,

Low Power RFIC Solutions for Wireless Sensor Networks and

  inductively degenerated for input matching. The inductances needed for L g and L s are 2.2nH and 4.3nH respectively. Capacitor C ext of 850fF was added to minimize the size of the inductance L g (Eq 2.37). The value of C ext imposes a tradeoff between L g size, gain and noise of the RF transconductor stage.

	5	M 6	M 7
	to buffer
		I bias
	Figure 2.36: Schematic of the proposed self-oscillating mixer core
	transistor M 1 is controlled by an external voltage Bias RF applied to the
	gate of M 1 . Transconductor stage is biased in moderate inversion region

Ultra-

  .39, a comparison between voltage conversion gain with and without R L is shown and this for different IF frequencies. The mixer stage provides a negative gain in dB without R L , less than -12 dB.

		16
		12
		8
	VCG (dB)	-4 0 4		VCG with R VCG without R L =1.5K
		-8
		-12
		-16
		20,0M	40,0M	60,0M	80,0M	100,0M
			IF frequency (Hz)

L Figure 2.39: Voltage conversion gain with and without R L

Table 2 .

 2 .44: Schematic of the differential common source buffer 4: Sizes of SOM devices (core and buffer)

	C 1 ) was introduced to reduce noise contribution of the current mirror
	(M 8 , M 9 ). The buffer operates from a 1 V supply and has a total current
	consumption of 2.1 mA. The final device types and aspect ratios are
	summarized in Table 2.4.

  frequency of 2.55 GHz, the measured S 11 was -11 dB.

	Due to the limited chip space, no pads were allocated to the oscillator's
	LO output and therefore the LO output power and phase noise could
	not be measured. However, the LO frequency could be deduced from
	the IF one with respect to RF frequency. For this purpose, the varactor
	drain/source voltage was tuned from 0 V to 2 V and IF frequency was
	measured. Figure 2.47 shows the frequency range of the oscillator. It
	varies from 2.55 GHz to 2.75 GHz which correspond to a tuning range of
	7.5 %. To measure gain and noise performances, a -30 dBm 2.55 GHz RF
		2,80
			Measurements
		2,75	PLS
	LO frequency (GHz)	2,60 2,65 2,70
		2,55
		2,50
		0,0	0,5	1,0	1,5	2,0
			V	(V)
			tune

2.3 Ultra-Low Power 2.4 GHz Self-Oscillating Mixer (SOM)

Table 2 .

 2 [START_REF] Wang | A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology[END_REF] summarizes the SOM performances and compares its behavior to the state-of-the-art.

Table 2 .

 2 5: Performance summary and comparison to other SOM

		This work	[4]	[5]
	CMOS Technology [nm]	65	130	180
	RF frequency [GHz]	2.5	7.8-8.8	4.2
	Voltage Conversion Gain [dB]	10@IF=10 MHz	11.6	10.9
	SSB Noise Figure [dB]	17.5@IF=25 MHz	4.39 (DSB)	14.5
	ICP1 [dBm]	-20.5	-13.6	-
	LO to RF Leakage [dBm]	-68	-59	-37
	LO to IF Leakage [dBm]	-64	-44	-
	P DC [mW]	0.6	12	3.14

110 Ultra-Low Power RFIC Solutions for Wireless Sensor Networks 3.3 Circuit Design Vdd

  MHz high-pass response. A MIM capacitor was chosen because of its high quality and small backplate parasitics. A low-pass filter (R f ,C f ) is added to reduce the noise contribution of the current mirror. Resistor R S degenerates the source of transistors M 5 and M 6 to improve the current

	20 mS	(3.21)
	For high bandwidth and low input capacitance, transistor M 4 is sized
	to operate in strong inversion. When driving a 50 Ω load, the simulated
	gain of the buffer is roughly -1 dB up to 10 GHz. The output return
	loss is about -20 dB at the operating frequency, 2.4 GHz. The buffer
	operates from a separate 1 V supply to facilitate oscillator core testing
	with a wide range of supply voltages. Since the oscillator DC output level
	varies with the supply voltage, the buffer is AC-coupled to the oscillator
	output through a 10 pF metal-insulator-metal (MIM) capacitor, forming
	a 1 mirror's stability. The total current consumption of each buffer, including
	biasing, is about 3.6 mA from a 1 V supply. The final device types and
	aspect ratios are summarized in Table 3.1.

Table 3 .

 3 1: Sizes of Oscillator devices (Core and buffer)

	Device	Size	Device	Size
	M 1 (W/L)	20 µm/0.06 µm	C bias	5 pF
	M 2,3 (W/L) 15 µm/0.06 µm	C b	10 pF
	M 4 (W/L)	25 µm/0.06 µm	C f	5 pF
	M 5,6 (W/L) 15 µm/0.06 µm	R bias	5 KΩ
	L g	5 nH	R f	5 KΩ
	L s	5 nH	R 1	15 KΩ
	L tank	6 nH	R 2	30 KΩ
	C tank	530 fF	R D	900 Ω
	C ext	450 fF	R S	10 Ω
	C v	5 µm/1 µm

116 Ultra-Low Power RFIC Solutions for Wireless Sensor Networks 3.3 Circuit Design implemented

  22) and may affect the bias design. Finally, the transistor may need to be sized larger to lower flicker noise, if it becomes dominant in the overall receiver noise calculation. It should be emphasized that this G factor is the conversion gain for high frequency signals at the detector input. Any input signals, including noise, at frequencies below the detector output bandwidth will experience the linear transfer function instead, with approximately unity gain (G DC ≈1). with a differential pair biased in weak inversion with 2 µA of current per side for maximum nonlinearity. A schematic of the differential envelope detector is shown in Figure 3.21. When a differential RF signal

	Vdd
	Since the oscillator output is differential, the envelope detection circuit is

Table 3 .

 3 2: Sizes of envelope detector devices

	Device	Size	Device Size
	M 1,2 (W/L) 15 µm/0.18 µm	g m1,2	74 µS
	M 3 (W/L)	5 µm/0.06 µm	g m3	50 µS
	C f	50 pF

Table 3 .

 3 3.

Table 3 . 3 :

 33 Sizes of baseband amplifier devices

	Device	Size
	M 1 (W/L) 20 µm/0.18 µm
	C in	90 pF
	C out	80 pF
	R D	1 kΩ
	Ultra-

Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks1.3 Challenges

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks2.1 Analog Techniques for low power/low supply voltage RF design

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks2.2 Ultra-Low Power 2.4 GHz Down Conversion Mixer

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks2.3 Ultra-Low Power 2.4 GHz Self-Oscillating Mixer (SOM)

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks3.1 Architecture Overview

Zero-IF and low-IF receivers (Figure 3.3b) got round the image problem by mixing the RF signal directly to baseband using quadrature downconversion. As in the super-heterodyne architecture, a local oscillator with high spectral purity and stability is required to drive the mixer. The power consumption of these architectures, along with super-heterodyne, is fundamentally limited by the RF oscillator and synthesizer. The stringent frequency accuracy and phase noise performance typically requires a resonant LC oscillator, usually embedded in a phase-locked loop (PLL).

The limited quality factor (Q) of integrated passives leads to a typical power budget of a few hundred microwatts. In [START_REF] Cook | An ultralow power 2.4GHz RF transceiver for wireless sensor networks in 0.13/spl mu/m CMOS with 400mV supply and an integrated passive RX front-end[END_REF], an illustration of low-IF receiver implementation is described. To further reduce the power consumption, the design eliminates the typical LNA and feeds the RF input directly to the quadrature downconversion mixers. The mixers are implemented as passive switching networks using MOSFET switches, so the mixing circuits consume zero DC current. Following the mixers, the receiver circuits process the baseband signal at the low IF frequency (less than 1 MHz), so these amplifiers consume little power. To perform the downconversion operation, an oscillator is required to drive the LO port of the mixers. The oscillator must operate near the RF channel frequency with high accuracy and stability, while simultaneously driving the gates of the mixer switches with a large amplitude signal. For quadrature operation, the voltage-controlled oscillator (VCO) must also provide both in-phase and quadrature outputs. Therefore, it is not surprising that the LO generation is responsible for more than 80 % of the overall power consumption in the receiver. Despite the use of a large modulation index to eliminate the need for a complete PLL, the VCO itself still consumes more than 300 µW in single-phase, non quadrature mode. Focusing on a low-IF receiver, [START_REF] Kluge | A fully integrated 2[END_REF] proposes an architecture with solely a mere oscillator signal which allows to save power needed to generate and buffer the quadrature design of each component in detail. In implementing each system block, the primary goal of reducing power consumption motivates simplicity in the circuit design. To further reduce power, the entire core system, which is composed by the oscillator and the envelope detector, is optimized to operate from a single 0.5 V supply.

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Circuit Design

LC Oscillator

The goals for this oscillator design are twofold. First, the design should consume minimal power and push the power limits of fully integrated RF oscillators. Secondly, the oscillator should be a test vehicle for the concepts of low voltage and low current design, since we have fixed the supply voltage to 0.5 V. A differential single cross-coupled LC oscillator was chosen for this design taking advantages from differential topology and the use of a single cross-coupled pair to cancel the losses in the tank, the tail device is used to inject the RF signal in order to modulate the oscillations. It is true that the complementary topology [START_REF] Hajimiri | Design issues in CMOS differential LC oscillators[END_REF], using both

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Vdd

This pole is designed to be low enough to filter out any signal at the fundamental and higher harmonics, while still affording enough bandwidth to avoid the baseband signal attenuation. For a typical OOK signal, the detected baseband waveform is a square wave with a given baseband data rate, so the detector bandwidth must be high enough to avoid filtering this desired signal. An AC input signal is applied to the input at V in in Figure 3.18. Since the output bandwidth is much smaller than the input signal frequency, the full signal appears across the gate-source terminal

Device M 1 generates an output current that is an exponential function of the input voltage. The nonlinear transfer function contributes a DC term at the output in response to the AC input signal. In order to calculate a simple expression for the effective conversion gain from input AC to output DC, the exponential can be approximated by using

Taylor series expansion and dropping terms above the second order. This

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks

Substituting for V in and recognizing that I D /nV t =g m :

The second harmonic term will be filtered by the detector output pole, giving a DC output current:

Finally, we arrive at the DC output voltage by multiplying the output signal current by the detector output impedance:

Therefore the voltage conversion gain G from peak AC input amplitude V s to output DC voltage V out is given by:

The derivation above holds for small input signals where the response is dominated by the second order term and higher order effects are not significant. For the purposes of analyzing the detector sensitivity, the signals of interest are small and the simple form of Eq 3.32 is a convenient way to represent the detector response. Using the full Bessel function representation in [START_REF] Meyer | Low-power monolithic RF peak detector analysis[END_REF], a more accurate expression for gain can be derived.

The simulation result is depicted in Figure 3.20. The envelope detector was implemented in a 65 nm CMOS process with (W/L) 1 =(15 µm/0.18 µm) and bias current of 2.5 µA. Interestingly, Equation Eq 3.32 predicts that the gain is independent of the device sizing and transconductance. The

Ultra-Low Power RFIC Solutions for Wireless Sensor Networks