Miguel Mannes Hillesheim
email: miguel.mannes-hillesheim@laplace.univ-tlse.fr

Marc Cousineau

Miguel Vivert

Guillaume Aulagnier

Guillaume Gateau

Eigendecomposition of a Digital Iterative Decentralised Interleaving for Multicellular Converters

Keywords: Auto-organisation, Reconfigurable, Local Decision, Distributed, Scalable, Robustness

The decentralised control of multicellular converters is an alternative to the usual control techniques. Multicellular converters use interleaved carriers to reduce filtering elements and potentially improve transient response. Decentralised interleaving techniques are scalable, avoid a complex interleaving controller for a high number of cells, and simplify reconfiguration cases like phase shading. Circular chain of communication (ring, or daisy chain) approaches have been proposed in the literature and implemented in concrete applications. However, the analytical study of the stability and dynamic response of this system involving several identical phase-delay local controllers connected in a dedicated communication chain with their close neighbours has not been conducted yet. This paper presents a behavioural discrete model for a digitally implemented decentralised interleaving device. The eigenvalue study gives the stability criterion and convergence speed to choose the appropriate parameters of the controllers. A modal decomposition technique dissociates the various types of differential interactions to observe their respective time response. Simulation results demonstrate that the system is unconditionally stable when all differential modes are properly damped. An analytical expression for the final disposition of the carriers in steady state depending on the start-up condition is established. Lastly, a more precise operator to overcome the singular discontinuity of the model is presented and discussed. Experimental validation by FPGA implementation have been done for reconfiguration and start-up cases.

Introduction

Nowadays, multicellular converters are widely used to achieve either high efficiency, high power density or fast transient response to load transients, or in some cases a combination of these performances. They are used for lowand high-power applications, such as inverters, rectifiers and isolated or non-isolated DC-DC converters. Among the different topologies of multicellular converters, some are composed by elementary cells made of switching power transistors and passive components as inductor or capacitor for local energy storage purpose. These cells can be arranged, like building blocks, either in series, in parallel or both. In parallel architectures, such as the multiphase converter shown in Fig. 1(a), each elementary converter handle a part of the output current. This current is shared among the several leg inductors L1 to L3 present in the structure. In series architectures, such as the Modular Multilevel Converter (MMC) shown in Fig. 1(b), each elementary converter handle a part of the input voltage which is share among the capacitors C1 to C3. Their control is complex due to the large number of cells to control, reaching 14 or 16 in parallel topologies such as low-power Voltage Regulator Module (VRM) and even several hundred in the case of high-power HVDC with STATCOM or MMC for the serial case. Due to their modular nature, these redundant architectures are also suitable to deal with fail-operational requirements, offering multiple redundant paths for the power delivery in case of local default. When using a Phase-Shifted Pulse-Width Modulation (PS-PWM) strategy to control a multicellular converter, the several control signals present among the cells are equally distributed in time, as shown in Fig. 1(c). To do so, these converter signals have equally spaced Phase-Delays (PDs), therefore interleaved. Interleaved converters provide an apparent frequency in the input/output passive components equal to the switching frequency multiplied by the number of cells, thus reducing filtering constraints and also allowing for better transient response.

Some scalable/stackable solutions available in the market use master-slave approaches to achieve interleaving during reconfiguration. The master selects each slave PD with respect to the carrier number. When required, the reconfiguration has to detect by the master supervisor that change the positions of all the slave carriers. In any case, losing the master means losing the function. Numerous innovative scalable approaches with decentralised control have been developed for multicellular converter such as VRM [START_REF] Huang | A scalable multiphase buck converter with average current share bus[END_REF][START_REF] Zhang | A novel distributed control and its tolerance analysis for microprocessor power management[END_REF] both for parallelisation [START_REF] Cousineau | Interleaved converter with massive parallelization of high frequency GaN switching-cells using decentralized modular analog controller[END_REF][START_REF] Cousineau | Modular Static Converters with Parallel or Series Architecture And Decentralized Modular Control[END_REF][START_REF] Nasirian | Distributed cooperative control of DC microgrids[END_REF] and for massive cascading [START_REF] Seleme | Decentralized controller for modular multilevel converter[END_REF] of switching-cells. They are applied to regulate the output variable [START_REF] Cousineau | Fully decentralized modular approach for parallel converter control[END_REF][START_REF] Cousineau | Fully masterless control of parallel converter[END_REF][START_REF] Huang | A scalable multiphase buck converter with average current share bus[END_REF][START_REF] Zhang | A novel distributed control and its tolerance analysis for microprocessor power management[END_REF], to balance either the leg currents (by shared wire [START_REF] Huang | A scalable multiphase buck converter with average current share bus[END_REF] or by local comparisons [START_REF] Cousineau | Fully decentralized modular approach for parallel converter control[END_REF][START_REF] Cousineau | Fully masterless control of parallel converter[END_REF][START_REF] Bolloch | New masterless modular current-sharing technique for DC/DC parallel converters[END_REF][START_REF] Xiao | Modular control of parallel isolated micro-converters dedicated to conversion network[END_REF] or the capacitor voltages [START_REF] Cousineau | Modular Static Converters with Parallel or Series Architecture And Decentralized Modular Control[END_REF] and to interleave the cell control signals.

Concerning the specific case of the PWM signal interleaving, some solutions are able to interleave without dedicated communication lines, whether by detection of other modules' switching events [START_REF] Feng | Implementation of an automatic interleaving approach for parallel DC/DC converter without interleaving bus[END_REF], by mitigating the subharmonic oscillation on the output voltage [START_REF] Sinha | Decentralized interleaving of paralleled DC-DC buck converters[END_REF][START_REF] Sinha | Decentralized interleaving of parallel-connected buck converters[END_REF] or in the output current [START_REF] Dutta | Decentralized carrier interleaving in cascaded multilevel DC-AC converters[END_REF]. However, it can lead to noise sensitive applications or prohibitive sub-harmonic oscillation during transient. Others use a dedicated communication line with time-consuming protocols, either by analogue means [START_REF] Perreault | Distributed interleaving of paralleled power converters[END_REF], discrete voltage levels [START_REF] Kudtongngam | Automatic interleaving technique using single interleaving bus for paralleling power converters[END_REF][START_REF] Kudtongngam | Implementation of automatic interleaving and load current sharing techniques using single interleaving bus[END_REF] or high-speed digital communications. Nevertheless, these approaches can have availability issues because the shared line required is a Single Point Of Failure (SPOF). Some applications use a ring architecture to propagate a fixed [START_REF] Zhang | A novel distributed control and its tolerance analysis for microprocessor power management[END_REF][START_REF] Zhang | A novel distributed interleaving scheme to achieve scalable phase design for microprocessor power management[END_REF] or adjustable delay [START_REF] Kohama | Automatic interleaving control for paralleled converter system and its ripple estimation with simplified circuit model[END_REF][START_REF] Kohama | Ripple estimation for paralleled converter system with automatic interleaving function[END_REF], while others use a bidirectional circular chain of local communications using either analogue signals [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF][START_REF] Xiao | Modular control of parallel isolated micro-converters dedicated to conversion network[END_REF], or comparators with digital gates [START_REF] Xiao | Modular interleaved carrier generator using a straightforward implementation method[END_REF], or also fully digital [START_REF] Broadmeadow | Self-organising technique for carrier synchronisation and phase offset distribution in modular, fault-tolerant converters[END_REF][START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF][START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF] solutions. These approaches are costly in communication lines but overcome noise sensitivity, sub-harmonic oscillation, and SPOF issues. A solution with a unidirectional communication set was also proposed in [START_REF] Phan | Modified decentralized control for multiphase converters[END_REF].

The approach shown in [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF][START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF] describes a decentralized carrier interleaving system that provides a good answer to Single Point Of Failure (SPOF) issues by removing the notion of master. Each Carrier Generator (CG) is associated to a Phase-Delay Local Controller (PDLC), and all the PDLCs are connected in between them in a circular chain of communications, as shown in Fig. 2. Then each PDLC adjust its local PD in between its neighbouring PDs to provide a natural and automatic interleaving of the carriers. This circular chain approach is theoretically extensible to an infinite number of elements. If non-active PDLCs are present, they are simply bypassed by making a direct link between their respective neighbours in order to keep the chain of communications closed. A supervisor can be associated with each PDLCs to manage the number of active PDLCs for either efficiency, performance or fault-tolerance concerns. When a reconfiguration is required by the local supervisor, by either inserting or removing an active cell of the converter, this decision is used to bypass or not the local communications, so that the active PDLCs reconfigure automatically their respective PDs. As a result, a centralised decision is no longer required. The challenge related to this system is the PDs' stability analysis and its global convergence time obtained, mainly because of the large number of variables to manage and their coupling, i.e. the multiplicity of feedback loops involved due to the circular chain of communications. The PDs are state variables and must be studied all together. Several differential excitation modes exist. Therefore, the stability of the decentralised interleaving device must be carefully analysed for both start-up and reconfiguration singular cases.

This paper provides an exhaustive analytical study of a digital iterative decentralised interleaving system with an adjustable parameter α, named the convergence coefficient, to guarantee its unconditional stability. Then, several design criteria are exposed to optimize the global transient response. Moreover, the PDLC implementation guidelines are given with recommendations to prevent wrong interleaving and undesired disturbances. Then, experimental validation by FPGA implementation are shown for reconfiguration and start-up cases.

Section 2 recalls the decentralised interleaving principle using a digital method and develops a discrete analytical model. In Section 3, the analytical modal decomposition is presented as well as the stability analysis of the complete system and the dynamic responses to modal disturbances. Section 4 details the target value calculation to avoid wrong interleaving, followed by a reconfiguration and start-up response analysis. The same study is carried out in Section 5 for the particular case of one fixed PD into the system.

Decentralised Interleaving and Analytic Model

This section provides an analytical model of the digital iterative decentralised interleaving system described in [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF][START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF]. A global synchronisation clock signal at the switching frequency is used as a phase reference, i.e. the rising edge of the clock signal is considered as the zero angle position. Each cell interleaving system is composed by two elements: a PDLC and a carrier generator. The PDLC computes the PD of the local carrier with respect to the neighbours PDs, while the carrier generator generates triangular signal with the given PD value with respect to the phase reference, i.e. the global synchronisation clock. During modelling, the PD values treated in this work are normalised, i.e. in between 0 and 1, and the quantisation effects are not taken into account.

The PDLC involves a digital feedback loop to put the local PD in between the PDs of its neighbouring cells. For modelling, all the iterations are considered synchronous, so an iteration is done once all PDs have been updated.

Local Controller Modelling

The PDs are considered causal discrete-time signals, i.e. null for k < 0. The discrete-domain step function is denoted u k . The evolution of one PD is illustrated in Fig. 3

∆ is the correction applied for the next iteration, given by Eq. ( 3) where α is a proportional gain called here the "convergence coefficient". The stability study has to define the α values to ensure convergence.

=

(3)

Eq. ( 4) gives the new PD obtained for the PDLC at the iteration k+1.

= (4)

The block diagram of a PDLC is shown in Fig. 4. Eq. ( 5) is the PDLC's recurrence relation found by successively replacing (3) and ( 2) in (4). The initial value ! appears at the iteration k = 0 by means of the Dirac delta function ", then ! = ! .

= #1 % ! " (5)
Eq. ( 6) is the unilateral Z-transform of the recurrence relation [START_REF] Cousineau | Fully decentralized modular approach for parallel converter control[END_REF]. This is the system's transfer function in the Zdomain. It shows one discrete pole whose value is 1 -α.

#&% = & & #1 % ! & #1 % #&% (6)
Discrete systems theory establishes that the system is stable if the absolute value of the pole is less than 1. Therefore, for the case of a single loop with constant adjacent PDs, the system is stable for the values of α between 0 and 2. The optimal value of α is 1 (z = 0) because it equals the output to the input (target) in only one iteration. If the z pole is equal to -1 (α equals to 2), the damping is null and the response oscillates. The system diverges if the pole absolute value is greater than 1, i.e. if α is negative or bigger than 2.

However, since the local target is a combination of the previous and next PDs, i.e. other state variables, connected through the circular chain, as shown in Fig. 2. Therefore, the study of the system response by only focusing on the behaviour of local loops is not accurate. The stability of the local loop does not guarantee the stability of the overall system.

Overall System Modelling

The study of the system's stability with a generic number N of PDLCs has to be performed. The overall system will be then modelled using a matrix approach. The PD values from θ1 to θN are then represented by a column vector θ (in bold in the following equations).

The circular chain connection architecture is represented using the matrix L, similar to the Laplacian matrix in graph theory. The matrix L for N equal to 6 and θ in ascending order (1 to N) is shown in Eq. [START_REF] Dutta | Decentralized carrier interleaving in cascaded multilevel DC-AC converters[END_REF]. It is an N-order square matrix composed of a negative unitary diagonal surrounded by factors 0.5. This matrix is used to calculate the PD errors εθ1 to εθN present in the column vector εθ derived from θ. The error is calculated with Eq. ( 8), where ' is an additive term that will be discussed latter. The ' vector is considered here constant and will be calculated by the "target operator". Its value does not affect the stability study.

(7) ( = ) ' (8)
From now on, all composing elements of the model are known, remarkably the matrix L for the communication links and the vector ' for the error calculation. Fig. 5 shows a block diagram using a matrix operator with N = 6. This system is linear, and the stability study can be easily performed. This system can be written in a small signal formulation represented by Eq. ( 9) that is comparable with Eq. (5) (monovariable), where I is the identity matrix and θ0 is a column vector filled with the starting values. The local errors are evaluated with Eq. [START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF].

= #* )% + " ' , (9)
( = ) ' , (10)
This system can also be written in a discrete state space representation for simulation and stability study. The PDs are the state variables, and the local errors are placed as output variables for observation. The input u is an unidimensional unit step function. No other connection is required because the system is already in the closed-loop form. So, the natural response found is directly that of a well-known N-order closed-loop system. From Eq. ( 9) and [START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF], the equivalent matrices for space state representation are shown in [START_REF] Hunt | A matrix theory proof of the discrete convolution theorem[END_REF]. These matrices are defined and used in MathWorks MATLAB® to perform all the simulations. It should be noted that the function "ss" is used to define the space-state model and the function "lsim" realises the simulation and gives results.

-= , / = ( (11)

= *

), 8 = ', 9 = ), : = '

The stability can be demonstrated in many different ways, such as passivity, transfer function diagonalization or eigendecomposition. Nevertheless passivity does not reveal the dynamics such as settle time. Table 1 shows a summary of some stability and dynamics study methods for Multiple Input Multiple Output (MIMO) systems. As this system has no zeros, so the eigendecomposition is chosen due to its simplicity. The stability study and settle time will be performed analytically with respect to α. The system's stability and settle time are defined by the state matrix A that depends on the value of α. The matrices A and L are very similar because A is a linear combination of the matrix L and the identity matrix I.

The diagonalisation is also used to reveal the decoupled system dynamics, called the modal responses, and which determine the response of the overall system to external excitations. The system is stable if all the modal dynamics are stable.

Change of Basis and Modal Responses

The matrix L and the feedback loops couple all PDs. A change of basis allows to decompose the original coupled system into independent first-order systems. The matrices L and A are real, symmetric and circulant due to the circular chain architecture. The matrix A has the same properties as L because Eq. ( 12) does not change the characteristics of the matrix. Several interesting properties come from the fact that a matrix is circulant. Circulant matrices of order N are diagonalisable with the Discrete Fourier Transform Matrix (DFT) [START_REF] Hunt | A matrix theory proof of the discrete convolution theorem[END_REF] for N samples. The change of basis matrix ; is the unitary DFT matrix, so ; < ; = *, and ; < is equal to ; * , its conjugate transpose. Thus, the multiplication of ; < with the PD vector θ produces the DFT of the PD.

The state matrix A diagonalisation is described in Eq. ( 13), where ; is the change of basis matrix (eigenvectors), ; < is its inverse, and > 7 is the eigenvalue diagonal matrix of A.

7 = ; > 7 ; < (13)
The matrices A and L are simultaneous diagonalisable, i.e. similar. Therefore A and L have the same change of basis matrix, as shown in Eq. ( 14).

) = ; > ; < (14)
It is clear now that this system can be studied using the eigenvalues and the transformation matrices of L. The matrix L will be deeply studied thereafter. The eigenvectors of L decouple the system, and the eigenvalues reveal its stability. As L is real and symmetric, a real orthogonal representation of its eigenvectors also exists, however the DFT matrix ; will be used here because it has more interesting properties.

System Diagonalisation

A change of basis expressed by the set of Eq. ( 15) is applied to the system. * = ; <? , ' * = ; <? ',

+ * = ; <? + (15)
The system's recurrence relation, described in Eq. ( 9), is rewritten in a diagonal form by Eq. ( 16).

As the eigenvalue matrix > 7 is diagonal, Eq. ( 16) can be rewritten in N independent modal responses as denoted in Eq. ( 17) using the diagonal index i. The N diagonal elements λAii of > 7 are denoted λAi, and λii of > are denoted λi

for i = 0 … N -1. A * @ = λ CA A * @ D A * , @ !A * " @ , E = 0 … G 1 (17)
By analogy of Eq. ( 17) with Eq. ( 5) and ( 6), it can be noticed that the eigenvalues are the modal discrete poles of the linear system, as expected.

Error Disturbance

As all the treated variables are real, a reduced representation with H complex components can be used to represent the carried information. This decomposition matrix, denoted I, is N-by-M and is composed of the H first columns of ;. M is an integer that satisfies the condition in Eq. [START_REF] Nasirian | Distributed cooperative control of DC microgrids[END_REF].

H = J G 1 2 , EK G EL MNN. G 2 1, EK G EL OPOQ. ( 18
)
The columns of I are denoted P#R% with m = 0 … M -1. Each of those has an equivalent row at I * , denoted P * #R%, that has a number of cycles m related to its fundamental frequency. The rows of I * and their respective spectrum with N = 8 (M = 5) are shown in Fig. 6. This number of cycles m will be used thereafter as the modal index. The eigenvectors of the double modes (N = 8, m from 1 to 3) are complex (red lines are imaginary values) and are naturally in quadrature (orthogonal) with their real part. The error vector ( is decomposed with the matrix I * , as shown in Eq. [START_REF] Perreault | Distributed interleaving of paralleled power converters[END_REF]. By taking its absolute value, the components of ( * can be used to visualise the residual perturbation contained in each mode during simulation.

( * S = TUL I * ( S (19)
Each element of ( * is shown in Eq. [START_REF] Phan | Modified decentralized control for multiphase converters[END_REF]. It has to converge to zero as the system goes to steady state.

* V = TUL W * #R% ( S , R = 0 … H 1 (20)

Eigenvalues

All eigenvalues of A have to be identified to ensure the stability of all modal responses and to adjust the convergence speed. Thanks to the eigenvalue properties, the eigenvalue matrix X 7 can be written as a function of the eigenvalue matrix X as shown in Eq. ( 21) and [START_REF] Sinha | Decentralized interleaving of paralleled DC-DC buck converters[END_REF]. The revealed eigenvalues are similar to the case of one single loop [START_REF] Cousineau | Fully masterless control of parallel converter[END_REF], but with the eigenvalues λi playing as a multiplicative factor, instead of the constant -1.

X 7 = Y X (21) λ CA = 1 λ A , E = 0 … G 1 (22)
Eq. ( 22) shows an important point of this approach, that is to say the modes cannot be independently controlled because the feedback matrix L is imposed by the circular chain architecture of Fig. 2 and it uses only a single and common adjustment factor, called the convergence coefficient α. Using different α values for each PDLC invalidates the approach presented here.

Gerschgorin's theorem shows that the eigenvalues of L are real and in between -2 and 0. The eigenvalues of the circulant matrix are indeed known. Eq. [START_REF] Sinha | Decentralized interleaving of parallel-connected buck converters[END_REF] shows the values of this type of matrix for any value of N. Eq. ( 23) can be rewritten in many different ways using complex exponential functions.

λ A = cos 2 ] E G 1, E = 0 … G 1 (23)
Fig. 7 illustrates the M values found with Eq. ( 23) for N odd and even. To regroup double eigenvalues, for i ≥ M, i can be written as i -N. In this way, the duplicated values have the same index. These duplicated values are related to the double modes shown in Fig. 7. If N is even, a last eigenvalue equal to 2 is found for i equal to N/2. In both cases, the first eigenvalue λ ! is null. The study of the system using A is now easer because the diagonal matrices and the eigenvalues of L are known and determined by Eq. ( 23).

Eigenvalues and Stability Concern

The eigenvalues λAi are easily computed as a function of α from Eq. ( 22) and [START_REF] Sinha | Decentralized interleaving of parallel-connected buck converters[END_REF]. To guarantee the stability, the absolute values of all eigenvalues have to be less than 1. Taking into account the greater eigenvalue of L in absolute value (-2) in Eq. ( 23), the convergence factor α has to be between 0 and 1 to ensure stability. This is already a huge difference with respect to the model taking into account a single loop, as seen in Section 2.1, where the system seemed to be stable for α between 0 and 2. The eigenvalues will be studied in the α range where the system is stable, demonstrating how this factor interferes in the response of each mode and consequently in the whole system. The eigenvalues are revealed as a function of α in Fig. 8 for the cases of N ranging from 5 to 8. Several lines are drawn expressing the values of the existing eigenvalues that are related to N. λA0 is related to the common mode and represents the average value of all PDs. As λ0 is null, λA0 does not depends on α and remains constant, equal to 1, because the system is made to control only PD differences. It should be noted that this system is not able to detect if an identical amount of phase shift is added to each PD. As a consequence, this system is not able to impose any PD value because the common mode is not controllable; only relative values are controlled. The average PD values may have any value. If this is an issue, it can be avoided in noise sensitive applications using one fixed PD for instance, but this solution may raise other stability considerations that are treated in section 5 One Fixed Carrier Phase-Delay.

All differential modes are controllable because their eigenvalues depend on the parameter α. The differential modes are double and overlap themselves two-by-two (studied together), from 1 to (N-1)/2. If N is even, the last mode (N/2) is a single mode.

When α is equal to 1 with N even, the last mode N/2 reaches the stability limit. Nevertheless, if N is odd, the value of the last mode does not reach -1, only if N tends towards infinity. Thus, the limit of stability is never reached for α equals to 1 in the case of N odd. Therefore, this system is stable for any value of N if α is strictly less than 1.

Fig. 9 shows the different eigenvalues found for α equal to 1 and 2/3. It shows the trade-off made with the choice of α between stability and the system dynamics. Increasing α from 0 to 0.5 decreases λAi absolute values. When α is greater than 0.5, some eigenvalues become negative and their absolute value increase. Those modes are still stable, but they have an oscillating damped response. The settling time depends on the sample time and on the number of iterations because there is no physical process behind this interleaving system. The sample time is limited mainly by the communication bandwidth. As in a simple first-order system, the number of iterations for convergence can be computed, for example, by the number k of iterations necessary to reduce each differential mode disturbance to 5% of its initial value. Eq. [START_REF] Xiao | Modular interleaved carrier generator using a straightforward implementation method[END_REF] shows the general formula derived from Eq. ( 17), where m is the mode number.

`a%_d = eMf#0.05% eMf TUL#λ ^d% 1, R = 0 … H 1 (24)
Table 2 shows the number of iterations for convergence of the differential modes in the cases of Fig. 9. The mode 4 is in stability limit and oscillates for α = 1. The modes 1 and 2 slow down when α is reduced.

N = 8

Imaginary Axis

α = 1/2 1 2.6 5.3 20
Table 2 shows explicitly the number of iterations required for each differential mode with a given α parameter. With different configurations observed, it is not easy to guess which would be the optimal one. As numerous variables depend on the same parameter, a criterion has to be established to find a trade-off helping to choose α. Each differential mode eigenvalue has to be reduced in absolute value to speed up the response. One option is to improve the worst case by reducing as much as possible the absolute value of the larger eigenvalue. A second option is to improve the response globally such as minimising either the quadratic sum of the X g eigenvalues or the number of iterations k5% of each mode. The results of these three approaches are shown in Fig. 10 for N = 8. The minimum value using the absolute maximum criterion is found with α = 0.87. It is also the point where the absolute values of λ ^ and λ ^ are equal. The minimum value using the X g eigenvalues' least squares criterion is found with α = 0.62. Lastly, the minimum value using the k5% least squares criterion is found with α = 0.78. Each criterion gives different optimum values. For this configuration with N = 8, a convenient value is about 2/3.

In this system, the convergence dynamics depend also on which modes are excited, i.e. if only fast modes are excited, the convergence is faster. For instance, if mode 1 is not excited with α = 2/3, its convergence would be faster than the case where α is close to 1 and all modes are excited. An example will be shown latter.

Modal Response

At this point, the system model is established, and the stability criterion is defined. The dynamic behaviour of the overall system can be simulated and compared with the one predicted. In the simulations performed hereafter, the system starts in its expected equilibrium state with all the carriers well interleaved. Fig. 11 shows a system simulation response with eight PDLCs (N = 8) and α equal to either 2/3 or 1 where each mode is excited individually one after the other, from the common mode (λA0) to the last one (λA4). The vector h, i.e. i1 to iN, is a disturbance summed to their respective PDLC correction ∆ i shown in Eq. (3). The vector h * is the absolute value modal decomposition of h equals to |I * h|. Fig. 11(a1) shows the modal disturbance magnitudes h * and the related time events. Fig. 11(a2) shows the PD θ waveforms. It is possible to distinctly observe the modal excitations being applied successively. The deviations that appear have the eigenvectors' shape (like sine wave) and cycle number shown in Fig. 6. Fig. 11(a3) shows the local error εθ, and Fig. 11(a4) shows its modal decomposition εθ*, to show the total mode disturbance.

The PD values behave as expected. The mode 0 (λA0 = 1) behaves as a pure integrator All differential modes are damped for the case in Fig. 11(a). For the case in Fig. 11(b), λA1 behaves like a non-oscillating first-order system (orange circle in the figure) because the pole value is positive real and less than 1, λA2 cancels the perturbation in a single iteration (yellow circle) because the pole value is zero, λA3 has damped oscillations (purple circle), and λA4 shows the stability limit, so it oscillates without damping because the pole value is equal to -1. This simulation confirms the number of iterations required for convergence revealed in Table 2. For the α = 1 case, * and * take about 10 iterations to be damped, and mode * takes only one. Mode * is not damped, and oscillates without damping after being excited.

Eigenvalues and Stability vs. Number of Active PDLCs

A reconfiguration event is the modification during operation of the number N of active PDLCs. Non-active PDLCs are bypassed and become invisible to active PDLCs. As seen before, all eigenvalues depend on a single convergence factor α, and a trade-off has to be made. On the other hand, when a reconfiguration is made, α remains the same and the eigenvalues have to continue in a convenient range to ensure stability and fast convergence time. The bypassed PDLCs are not taken into account in the stability issues. Fig. 12 shows the pole locations for different values N of active PDLCs with α equal to 2/3 and 1. As shown in the figure, the number of existing modes is a function of N. As N increases, the eigenvalues shift to the right, and the new ones appear on the left. As the eigenvalues change, they stay always in the same range between 1-2α and 1, e.g. [-1/3 1] for α equal to 2/3 and [-1 1] for α equal to 1. As previously demonstrated in Section 3.3, this system is stable for any value of N if α is smaller than 1.

(a1) (b1) (a2) (b2) (a3) (b3) (a4) (b4)
As soon as the state of an PDLC changes, activated to be inserted into or deactivated to be removed from the chain, the remaining PDLCs have to evolve their PDs to reach a new steady-state disposition where all the carriers are correctly interleaved again. One can notice that these simulations of reconfiguration proposed here illustrate a real case of a decentralised interleaving operation. A reconfiguration event excites the different modes, and the convergence towards the correct interleaving must be guaranteed.

Modal Disturb *

Carrier Phase-Delay

Local Error

Modal Error *

The reconfiguration responses are analysed hereafter, first with the removal case, followed by the insertion case and then with specific case studies of start-up.

Fig. 12

Root locus for α equal to 2/3 and 1 and N ranging from 6 to 10

Target Operator Formulation and Wrong Interleaving Discussion

The principle of correction by comparison with the neighbours has been used previously in the literature for different purposes. For instance, in [START_REF] Bolloch | New masterless modular current-sharing technique for DC/DC parallel converters[END_REF] a current balance system equalises the values of several inductor currents with this technique. With this principle applied for the interleaving, it should be noticed the system equalises the PD differences between the neighbours. In the approach presented in [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF], the PD differences and correction are made in a manner relative to the local carrier.

In the approach presented here, the PDs are related to a global phase reference, as shown in Fig. 3. Thus, there is a discontinuity between the last and the first PD, and therefore the operator L does not work for all PDs. Using normalised PD, the discontinuity appears when the PD approaches the value 1 from the negative side, as shown in the Fig. 13(a), but also when the PD approaches 0 from the positive side. Fig. 13(b) shows a well-interleaved system with five carriers (N = 5) where the PD differences are all equal to 0.2 (1/N). The error has to be equal to zero. Fig. 13(c) shows the expected position for the first carrier and the computed average value of its neighbours. These two values are in phase opposition. This system requires then additional operations such as those described in [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF][START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF][START_REF] Phan | Modified decentralized control for multiphase converters[END_REF]. Issues are described in [START_REF] Broadmeadow | Self-organising technique for carrier synchronisation and phase offset distribution in modular, fault-tolerant converters[END_REF] as "ambiguous phase ordering" and "ambiguity in steady state", linked with the error signal calculation. The operators proposed here are able to evaluate the error and compute a new PD value despite the discontinuity. This is a required condition to ensure that the model and results presented in the previous section are valid.

The first operator required is called the "target operator". To illustrate the target operator necessity, the values of the PD column vectors θ and L θ are shown in Eq. ( 25) and Eq. ( 26) respectively, relative to the well-interleaved system shown in Fig. 13(b). = k 0.1 0.3 0.5 0.7 0.9 n o (25)

) = k 0.5 0.0 0.0 0.0 0.5 n o (26)

As anticipated, the L θ operation does not give the null error expected for a well-interleaved system. The PDLCs having a neighbour across the discontinuity (θ1 and θ5) have a local error different from zero. This value can be compensated by an additive term ' introduced earlier, as shown in Eq. [START_REF] Feng | Implementation of an automatic interleaving approach for parallel DC/DC converter without interleaving bus[END_REF]. In this particular case, the required ' value evaluated from a well-interleaved system is given in Eq. ( 27). ' = ) = k 0.5 0.0 0.0 0.0 0.5 n o [START_REF] Zhang | A novel distributed interleaving scheme to achieve scalable phase design for microprocessor power management[END_REF] The sum of all the elements of the ' vector is always null. This vector has always the same shape and can be generalised for any value of N. The PD discontinuity is in between its non-null values, in this case between the 5 th and the 1 st . Their signs define if the PD values are in an increasing or decreasing sequence. In the real system, each D A value is evaluated locally in the i th PDLC taking into account the local and the neighbours' PDs. For this reason, special attention has to be paid to the initial values of the PDs to avoid any mistake in the interleaving. Fig. 14 shows another case where the system is well interleaved but all the PDs are shifted by -0.2 units. It uses the same ' vector described in Eq. ( 27). As shown, the discontinuity position is no longer around zero, and may be smaller than zero. Thus, some PDs values may be now outside the range from 0 to 1. A negative value is obtained because a second operator is required to keep each PD in the range [0, 1]. It is called the "modulo operator" and gives a positive remainder after division by 1 (normalised value, equivalent to 360° or 2π). The modulo operator removes 1 if the value is higher than 1 and adds 1 if the value is smaller than 0.

The updated θ and ' vectors are shown in Eq. ( 29). All PD values in θ are now in the range [0, 1], and ' is updated. Both vectors are circularly shifted of one element to the right with respect to θ and ' in Eq. ( 25) and Eq. ( 27), respectively. Any circularly shifted version of these vectors are valid and give a correctly interleaved system. The amount of zero elements in sequence in the ' vector has to be equal to N -2. = k 0.9 0.1 0.3 0.5 0.7 n o ' = k 0.5 0.5 0.0 0.0 0.0 n o (29)

The whole algorithm implemented in the PDLC is shown in the flowchart of Fig. 15. The first condition prevents undesired disturbances during start-up, when neighbouring PD can be coincident. It can be seen in [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF], during startup, the PD in phase opposition moving while it is correctly in the middle of its neighbours. This condition makes PD in phase opposition fixed only at the beginning, achieving better transient response and avoiding undesired disturbances. When neighbouring PD are different, the target phase-delay is corrected depending on the neighbouring PD order and on the local PD.

The discontinuity handler adjusts the target value. It is trigged when the neighbours PDs are in a decreasing sequence, i.e. p , then a correction is made based on the local PD value. It should be noted the target value can be outside the PD normal range. It happens when the PD has to across the discontinuity. After the control routine, i.e. error calculation and correction, the modulo operator is applied to keep the local PD in the expected range.

With all these precautions, the PD discontinuity around 1 and 0 is overcome and considered as if it does not exist. In the simulations, the ' vector is kept constant and the second operator is applied using post-processing. Fig. 16(a) and(b) show other cases where the phase differences are equal to 2/N. In the case (a), as the number of elements is odd, the system to be well interleaved. In case (b), in contrast, where the number of elements is even, there is an evident interleaving problem because some PDs are coincident. The case (b) can happen during a reconfiguration of the case (a) or if a bypassed PD is not pre-positioned during a reconfiguration, so these two conditions have to be avoided. This issue appears if the phase differences (1/N) are multiplied by any integer in between 2 and N. In the limit case, all PDs are coincident. Countless types of solutions for θ and ' in case (b) can justify this arrangement. Two particular cases are shown in Eq. (30) and Eq. (31). A wrong interleaving with successive PD differences of 2/N is observed in both cases. The first one is not possible because the error operator can only compensate ±0.5 in the ' vector. The second one, however, is possible. This shows the presence of two discontinuities.

To ensure a correct interleaving, the ' vector has to contain only one discontinuity (0.5 and -0.5 values), so special care has to be taken during start-up and reconfigurations. To do so, the PD values have to be in an ascending order and coincident values can be tolerated. The removal of a carrier (or PDLC) during operation is easy because the system normally is already correctly interleaved and so ordered. On the other hand, the PD of a "sleeping" PDLC has to be pre-positioned between the neighbouring PDs to anticipate an insertion, such as it being active but not visible. The start-up disposition of the PDs requires also special care. Examples of these cases will be given in the next section.

PDLC Removal

The simulation of a reconfiguration proposed here illustrates the cases of an PDLC removal (the PDLC is bypassed). The removal is the simplest reconfiguration case because the system is already interleaved and there is no initial value to care about. Fig. 17 shows two reconfiguration simulations starting with nine well-interleaved PDLCs. The phase-delay local controller PDLC3 is disabled and bypassed at the first iteration, then the eight active PDLCs reconfigure and reach another interleaving state. These eight PDLCs have the same dynamics revealed previously. Fig. 17 The simulations show that all differential modes are excited at the beginning. All modes are damped with respect to the values shown in Table 2. In (a), it is clear that the * (the slowest) dominates the response time after all fast modes are damped. In (b), * is damped faster, but mode 4 is in stability limit so * response is clearly not damped and oscillates indefinitely. These two responses correspond exactly to the expected theoretical modal response detailed previously.

To validate the algorithm proposed and verify the required clock periods for convergence, the PDLC flowchart shown in Fig. 15 has been implanted using hardware description (VHDL) in Intel Quartus II software. Quartus generate an appropriated digital circuit able to be "wired" in a FPGA to perform the described operations. The PD values #q% are denoted theta(x)p in these Quartus results. The theta(x)p use a fixed dot representation composed by 1000 entire units which are shown in the results and 4 (2 bits) fractional parts which are hidden. As a result, 1000 is the conversion factor between the implementation representation and the previous one "normalized" used for modelling purposes. As the objective here is to validate the functionality of the proposed PDLC and the number of Fig. 18 shows the Quartus results for the reconfiguration case illustrated and simulated previously in Fig. 17(a). It can be noted, at the beginning, the 9 PDs are equally spaced (delta = 1000/9 ≈ 111) to generate a correct interleaving of the carriers. At t = 20 ns, the PDLC3 is bypassed (en3 = 0), then the reconfiguration sequence starts with the next clock rising-edge. 15 clock periods later (t = 175ns), mode 1, the slowest excited mode, is mostly damped and the PD values are quite close to the steady-state values reached 9 clock periods latter (t = 265ns). In steady-state, the 8 active PDLC's PDs are equally spaced (delta = 1000/8 = 125) and the bypassed PDLC3 theta3p is exactly pre-positioned in the middle of its active neighbours PDLC2 and PDLC4 because its local controllers is bypassed, but stays active. The values obtained using the Quartus functional results are remarkably close to the ones found using Matlab simulation, validating the proposed convergence performance. Fig. [START_REF] Nasirian | Distributed cooperative control of DC microgrids[END_REF] Quartus results for a reconfiguration response with N from 9 to 8 (PDLC3 is disabled).

PDLC Insertion

The simulation of a reconfiguration proposed here illustrates the cases of an PDLC insertion, i.e. a bypassed PDLC becomes visible to its neighbouring PDLCs in the communication chain. This event also excites all the different modes, and the convergence towards the correct interleaving must be guaranteed. Fig. 19 shows two reconfiguration simulations with eight PDLCs. At the beginning, seven PDLCs are well interleaved, then PDLC5 is inserted. Fig. 19(a) shows the reconfiguration response where PD5 is pre-positioned in between its neighbours, and Fig. 19(b) shows the case where its initial value is null. These eight PDLCs have the same dynamics as those revealed previously with α = 2/3 to ensure stability.

The simulations shown in Fig. 19(a) and (b) converge to steady state with phase differences of 1/N and 2/N, respectively. The correct interleaving state is reached in Fig. 19(a) because a is pre-positioned. Consequently, ' keeps the same value. On the other hand, this is not the case in in Fig. 19(b). The null starting value of a disturbs PDLC4's target operator, and that disturbance causes a nonconforming modification in '. After the first iteration, PDLC5's target operator is also disturbed because and 0 cross each other and modify again '. These ' values lead to a wrong interleaving arrangement.

To avoid wrong interleaving arrangements, at the beginning, the vector has to respect a specific shape to generate a proper ' vector. To do so, inactive PDLCs (bypassed) have to keep their PD computations active and correctly positioned. 2. The non-pre-positioned case shown in Fig. 20(b) leads to a wrong interleaving arrangement where 2 discontinuities can be observed (delta = 2 x 1000/8 = 250), i.e. two increasing sequences, such as described in Fig. 16(b). As the number of active PDLCs is even, the PDs are coincident 2 by 2.

Quartus functional results fully validate proposed strategy of keeping of non-active PDLC's PD pre-positioning to handle correctly any type of reconfiguration event. As a result, the discontinuity handler is behaviour is controlled and the ' vector is proper, then the final interleaving state is always correct and can be easily estimated.

Convergence and Steady-State Value

It is well understood now that the steady-state value depends on the target vector ', which, in turn, depends on the vector . The vector ' is constant if the vector is properly chosen at the beginning. In this way, as this system is causal, the value converges in steady state towards the value rr that can be calculated using the Final Value Theorem (FVT) if all differential modes are damped. The mathematical expression to calculate the steady-state value for this discrete system is shown in Eq. (32).

rr = lim →w = lim x→ #& 1% #&% (32)
The expression of #&% shown in Eq. ( 33) can be derived from Eq. ( 9).

#&% = #& * 7% < & + #& * 7% < 8 y#&% (33)
With two conditions: 0 < α < 1 and L,R#'% = 0, i.e. the sum of all elements of ' has to be null, the result in Eq. ( 34) is found by replacing Eq. ( 33) and solving Eq. (32).

rr = + zzz ) ' (34)
where + zzz is a vector in which each element is the average value of + , and ) is the pseudo-inverse of ). It should be noted that L is a singular because one eigenvalue is null and so has no inverse. ) can be evaluated using Eq. (35).

) = ; > ; < (35)
where > is formed from > by taking the reciprocal of all the non-zero elements.

Eq. (34) reveals that, as expected, the steady state depends on the start-up configuration + that provides also ', and, more importantly, on ) that comes from the communication chain configuration L. The steady-state value do not depends on the convergence factor α. If rr is outside the range 0 to 1, the correct result can be obtained by applying the modulo operator to each value.

Convergence Behaviour vs. Start-up Positions

Fig. 21 shows a classical start-up procedure such as described in [START_REF] Cousineau | Triangular carrier self-alignment using modular approach for interleaved converter control[END_REF][START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF][START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF] where one PD is put in phase opposition to the others. The starting values are chosen to avoid values going outside the range 0 to 1 and then to avoid any changes in the ' vector.

The values at the beginning determine the disturbed modes. In this case, the differential modes 1, 2 and 3 are disturbed. In both cases, with α equal 2/3 or 1, the correct steady-state interleaving disposition is reached. The case (b) converges because the mode 4, which is in stability limit, is never disturbed. However, it should be noted that a reconfiguration event can trigger the non-damped mode 4 and produce oscillations. Fig. 22 shows an alternative start-up procedure where the PDs are put in two successive groups. The starting values are also chosen to avoid values going outside the range 0 to 1 and then to avoid any changes in the ' vector.

In this case, only the differential modes 2 and 4 are disturbed. The disturbance in case (a) is damped very fast because mode 1, the slowest, is not disturbed. The responses of modes 2 and 4 have the same convergence time, but different starting values. In case (b), mode 4, in stability limit, is disturbed inducing sustained oscillations, so that the steady state is never reached. The case (a) brings also redundancy during start-up because more than one PD is in phase opposition. It is an important feature for fault tolerant systems and gives more flexibility during start-up. 2. Moreover, the Quartus functional results are again remarkably close to the ones found using Matlab simulation, validating the proposed convergence performances.

One Fixed Carrier Phase-Delay

In some applications [START_REF] Gateau | Digital implementation of decentralized control for multilevel converter[END_REF][START_REF] Grégoire | Real-time simulation of interleaved converters with decentralized control[END_REF][START_REF] Phan | Modified decentralized control for multiphase converters[END_REF], one PD is fixed to overcome instability with α = 1. Other applications have specific requirements to avoid noise issues. For example, one PD is imposed to overcome the impact of the switching noise. This section introduces the eigenvalue study, the time response and its dynamic analysis for the case with one fixed PD. When a PD is fixed, the corresponding row of the LN matrix is null because the computations made inside its PDLC are turned off. The communication chain configuration with six carriers (N = 6), where θ1 is fixed, is denoted L6-1 and expressed in Eq. ( 36).

(36)

The LN-1 eigenvalues are real, ranging between -2 and 0. It is no longer circulant, so the diagonalisation matrix V -1 is not the DFT matrix any more. Then, the concepts of common mode and cycles are no longer valid. The eigenvalues of LN-1 are computable from Eq. (37) for any N value.

λ A = cos ] E G 1, E = 0 … G 1 (37)
The new eigenvalues of A can still be evaluated as a function of α by Eq. ( 20). The eigenvalues λ CA of the differential modes #E = 1 … G 1% are shown in Fig. 24 for N from 5 to 8. There are three major differences in this configuration. Firstly, all the modes are simple; secondly, the common mode is imposed only by the fixed PD; and finally, the most important result, the system is unconditional stable even if α is equal to 1. Table 3 shows the iteration number for convergence for the case with N = 8 and one fixed PD, for α = 1, α = 2/3 and α = 1/2. The last mode, mode 7 in this case, is no longer in stability limit with α = 1. However, mode 1 is almost 4 times slower than the one when PD is not fixed. Table 3 presents the same pattern seen in Table 2, and all the previous observations are still valid, such as the convergence depending on the type of modes that are excited.

Reconfiguration Response

Fig. 25 shows two simulation results using the same conditions described previously, but 1 is fixed to 0. At the first iteration, PDLC3 is removed from the chain of communications. As PDLC1 is fixed, its error is never corrected (blue line), and the other PDs have to change to cancel their own local error. In case (a), * { is quickly reduced to zero while * dominates the response. Indeed, it is much slower than the other modes. In case (b), * and * { have the same convergence speed, but * { has a much higher disturbance at start-up, so it dominates the response. No sustained oscillation is observed, confirming the unconditional stability of this approach. To validate the poor transient response when using a fixed PD, Fig. 26 shows the Quartus functional results for the reconfiguration case illustrated and simulated in Fig. 25(a). As previously described in the non-fixed approach, at the beginning, the 9 PDs are equally spaced (delta = 1000/9 ≈ 111) to generate a correct interleaving of the carriers.

Fig. 26

Quartus results for a reconfiguration case from 9 to 8 where PDLC1 is fixe and PDLC3 is bypassed.

At t = 20 ns, the PDLC3 is bypassed (en3 = 0), then the reconfiguration sequence starts with the next clock rising-edge. 59 clock periods later (t = 615 ns), mode 1, the slowest excited mode, is mostly damped and the PD values are quite close to the steady-state values reached 26 clock periods latter (t = 880 ns). In steady-state, the 8 active PDLC's PDs are equally spaced (delta = 1000/8 = 125) and the bypassed PDLC3 theta3p is exactly prepositioned in the middle of their active neighbours PDLC2 and PDLC4. The Quartus functional results are remarkably close to the convergence time predictions, validating the proposed model.

Conclusions

In this paper, a complete analytical study of a digital iterative decentralised interleaving strategy has been developed. It highlights the existence of several modal responses whose number and dynamics depend on the number of carriers involved in the system. The stability criterion has been established for any number of active Phase-Delay Local Controllers (PDLC) used. A convergence factor has been defined and guidelines have been given to choose an appropriate convergence speed adapted for each application case. Examples have been given to show the resulting modal dynamics for different values of convergence factor.

The robustness of the decentralised interleaving strategy and its ability to quickly converge towards the expected steady state has been demonstrated both for the particular case of system reconfiguration during operation with the removal or the insertion of a PDLC and for the case of system start-up with different phase-delay arrangements. The stabilising effect of using a fixed position for one carrier has been also highlighted. In that particular case, an unconditional stability is obtained at the cost of a loss of dynamic performance, even when using the best value for the convergence coefficient.

Guidelines for the implementation of the PDLC are provided, ensuring correct steady-state disposition. Recommendations for the reconfiguration and start-up dispositions are also provided with an analytical expression of the dispositions reached after convergence. The functional implementation in VHDL on FPGA confirmed all the theoretical simulations made with Matlab and proves the relevance of the proposed method of automatic interleaving.

Finally, this study provides a very useful mathematical answer to handle the difficult stability study and transient response of such a decentralised control architecture involving a circular chain of communications.

Start values k5%_1

Steady state values

Fig. 1

 1 Fig. 1 Topologies of multicellular converters with 3 cells: a) Multiphase, b) MMC's half arm, c) Multiphase converter waveforms.

Fig. 2

 2 Fig. 2 Circular chain of inter-cell communications with four PDLCs and four carrier generators (N = 4)

Fig. 3

 3 Fig. 3 Iterative local PD control phasor diagram: a) phase diagram, b) discrete-time diagram. is the actual local PD, and is the local PD error evaluated by Eq. (2). =(2)

Fig. 4

 4 Fig. 4 Block diagram of the Phase-Delay Local Controller (PDLC) using digital feedback and a carrier generator.

Fig. 5

 5 Fig. 5 Matrix representation of the complete system with N = 6.

Fig. 6

 6 Fig. 6 Rows of I * and their Spectrum (N = 8), real values in blue and imaginary values in red.

Fig. 8 Fig. 7

 87 Fig. 8 Eigenvalues vs. Convergence Coefficient α (N = 5…8)

Fig. 9

 9 Fig. 9 Eigenvalue analysis for N = 8. a) Eigenvalue λ ^_ vs. Convergence Coefficient α, b) Root locus for α equal to 1, 2/3 and 1/2.

Fig. 10

 10 Fig. 10 Optimised Convergence Coefficient α. Minimising criterion: absolute maximum, least squares of λ ^d and least squares of k5%_m.

Fig. 11

 11 Fig. 11 Dynamic modal response (N = 8) a) α = 2/3; b) α = 1.

Fig. 13

 13 Fig. 13 PD representation: a) PD discontinuity around 1 and 0, b) Well-interleaved system with five carriers, c) Expected target and neighbours' average.

Fig. 14

 14 Fig. 14 Correct interleaving obtained using the ' vector (some PDs values are outside the range [0, 1]). Eq. (28) shows the solution for θ and ' related to the Fig. 14. = k 0.1 0.1 0.3 0.5 0.7 n o ' = k 0.5 0.0 0.0 0.0 0.5 n o (28)

Fig. 15

 15 Fig. 15 Phase-Delay Local Controller Flowchart.

Fig. 16

 16 Fig.[START_REF] Kudtongngam | Implementation of automatic interleaving and load current sharing techniques using single interleaving bus[END_REF] Interleaving issue when phase differences are equal to 2/N: a) N odd case (N = 5), b) N even case (N = 6).

  Fig.17shows two reconfiguration simulations starting with nine well-interleaved PDLCs. The phase-delay local controller PDLC3 is disabled and bypassed at the first iteration, then the eight active PDLCs reconfigure and reach another interleaving state. These eight PDLCs have the same dynamics revealed previously. Fig.17(a) shows the reconfiguration response with α = 2/3, and Fig. 17(b) shows the reconfiguration response with α = 1.

Fig. 17

 17 Fig.17shows two reconfiguration simulations starting with nine well-interleaved PDLCs. The phase-delay local controller PDLC3 is disabled and bypassed at the first iteration, then the eight active PDLCs reconfigure and reach another interleaving state. These eight PDLCs have the same dynamics revealed previously. Fig.17(a) shows the reconfiguration response with α = 2/3, and Fig. 17(b) shows the reconfiguration response with α = 1.

  convergence, only Quartus functional results are shown. Feasibility matters, such as propagation delays or maximum clock frequency, are avoided.

Fig. 20 (Fig. 19 Fig. 20

 201920 Fig.20(a) and (b) shows the Quartus results for the reconfiguration case illustrated and simulated previously in Fig.19(a) and (b), respectively, but using α = 1/2. In both cases, the 7 active PDLC's PDs (PDLC5 is bypassed) are equally spaced at the beginning (delta = 1000/7 ≈ 143) to generate a correct interleaving of the carriers. The

Fig. 21 Fig. 22 1 Fig. 23 (

 2122123 Fig. 21 Start-up response (N = 8) with one element in phase opposition (1+7): a) α = 2/3, b) α = 1.

Fig. 23

 23 Fig. 23 Quartus results for start-up case with 8 PDLCs and α = 2/3, a) Phase opposition (1+7), b) By groups (4+4).

Fig. 24

 24 Fig. 24 One carrier fixed: Eigenvalues vs. Convergence Coefficient for N from 5 to 8.

Fig. 25

 25 Fig. 25 Reconfiguration response: PD1 1 is fixed, and PDLC3 is disabled and bypassed (N = 8), a) α = 2/3, b) α = 1.

Table 1

 1 Summary of stability and dynamics study methods.

	Parameter	Passivity	Diagonalisation	Eigendecomposition
	Stability criteria	yes	yes	yes
	Settle time	no	yes	yes (without zeros)
	Difficulty	medium	medium	easy

Table 2

 2 Number of iterations for 5% response (N = 8).

	1
	0.8
	0.6
	0.4
	0.2
	0
	-1	-0.5	0	0.5	1
		Eigenvalue Ai
			gain		k5%_4	k5%_3	k5%_2	k5%_1
			α = 1		+∞	9.6	1	9.6
			α = 2/3		3.7	2.5	3.7	15

Table 3

 3 Iteration number for 5% response (N = 8) with one PD fixed.

	gain	k5%_7	k5%_6	k5%_5	k5%_4	k5%_3	k5%_2	k5%_1
	α = 1	39	9.4	4.1	1	4.1	9.4	39
	α = 2/3	3.4	2.5	2.1	3.7	6.6	15	59
	α = 1/2	1.9	2.6	3.5	5.3	9.1	20	78

Acknowledgments

This work has been supported by the French research agency ANRT and NXP Semiconductors.