Over the last few years, both data center and network traffic increased by several folds (more than six-fold, as stated by CISCO Systems, Inc.) and are still experiencing an ongoing growth. This demand for higher capacity while meeting with higher end-to-end quality service projects a continuous need for improvements in spectral efficiency enhancement techniques; however, a given spectrum band has its limit of volume it can support before reaching saturation levels. This pushes research efforts towards finding other solutions and a promising one is by exploiting the uncrowded millimeter-wave (mm-wave) spectrum through arranging more bandwidth. Signal amplification is one of the most basic and prevalent circuit function in modern RF-and microwave-systems. On the topic of wideband operation, distributed amplifier (DA) has proved to be a suitable and promising candidate with its ultra-wideband (UWB) performance. Meanwhile, the design of integrated circuit (IC) in mm-wave spectrum is becoming a challenging process due to the unavoidable parasitic that affect circuit performance and complicate design process. The reliability of the conventional design techniques through deriving mathematical equations, a simple and direct design process commonly used at low frequencies, starts to diminish. Another proposed design technique is by combining advanced-scripting languages with a proper physical model; this will lead to a smart and efficient technique of designing mmwave IC DAs through a process referred as computer-automated design (CAutoD) process. In this thesis, in particular, we propose for DAs an original ABCD-parameter based chain matrix model, a well-known formalism originating from the passive RF-circuit domain, in addition to a CAutoD methodology built upon it. Following this design technique is considered complete to a much greater extent, since the model gives flexibility in controlling a wider range of correlated design parameters. It is also considered reliable, a crucial criterion for mm-wave design, since the model does not apply simplification or neglect parasitic effects. It is simple, since the designer does not have to deal with the tiny effects (parasitic) that affect DA behavior and, finally, it is considered versatile, since it does not impose restrictions on the design component topologies the designer might be interested to use. Our end-goal is to offer the mm-wave designer a different and interesting technique in which the outcome of the suggested CAutoD process is a set of 3D graphical design exploration (DSE) plots. Designers then can explore different feasible solutions and choose the best design that meet their multiple performance objectives. Its benefit here is demonstrated by exploring the design space of DAs with BWs ≥ 80 GHz where STMicroelectronics (ST) 55-nm CMOS technology process is used, reporting 216 feasible DA options to explore from. Two global optimum DAs amplifying frequencies up to 100 GHz were then implemented as circuit prototypes: a single stage DA with 6.01 GHz/mW of measured gain-bandwidth product over DC consumption (GBP P DC ⁄ ) and a 17.5 THz GBP cascaded DA with 71.96 GHz/mW of GBP P DC ⁄ , being the highest figure of merits, to the authors' knowledge. vi

Chapter 1

General Introduction

The aim of this first chapter is to overview the reader on the subject of this thesis work that is wideband amplification in the millimeter-wave (mm-wave) frequency band . This high frequency band attracts strong interest for its uncrowded characteristic and opportunity to produce high date rate systems such that significant efforts are being dedicated to overcome the challenges faced when designing high-end mm-wave circuits. In particular, integrated circuit (IC) amplifier is a popular topic of study between the research community that is undergoing continuous improvement to break the limits on high frequency of operation, especially when the wideband criterion is targeted from a few GHz to hundred GHz and above. The need for such criterion has lead researcher towards distributed amplification as a promising candidate that offers such great capability and hence a critical circuit to adequately design. This topic also gains widespread interest especially when using complementary metal-oxide-semiconductor (CMOS) technology process for its attractive low-cost, high-volume production features and its ability of high frequency operation with continued device scaling. Nevertheless, a crucial challenge encountered is the lack of appropriate and accurate design techniques at such band where the simple analytical-based approaches, traditionally applied at low frequency spectrum, begin to fail and therefore advocate for a revaluation of design techniques.

The following sections outlines our context starting from a general overview on analog signal amplification and ending by stating our needs for an automated circuit design approach when dealing with mm-wave operating frequencies. Distributed amplification, which is the heart of this work, will be considered in Chapter 2, devoted specifically to introducing wideband amplifiers.

Analog Signal Amplification

Signal amplification is one of the most basic and prevalent circuit functions in modern RF and microwave systems. Amplifier block is found as a first component of any receiver front-end circuitry, on which overall receiver performance depends, as well as the last component of any transmitter front-end circuitry, on which a reliable transmission depends. In addition, an amplifier can be considered for implementation as an intermediate block in a complete system to compensate for any signal degradation encountered through intrastages circuitry.

Those applications share one common goal and it is magnifying a weak signal for further RF-treatment or digital signal processing. From the literature, it is clear that the amplifier design subject and application in fully integrated systems dates back to the early 21th century. Demonstrative implementation inside receivers and transmitters front-ends, and even transceivers have been reported using Si CMOS [START_REF] Alldred | A 1.2 V, 60 GHz radio receiver with on-chip transformers and inductors in 90 nm CMOS[END_REF]- [START_REF] Razavi | A 60-GHz CMOS receiver front-end[END_REF], SiGe BiCMOS [START_REF] Gordon | 65-GHz receiver in SiGe BiCMOS using monolithic inductors and transformers[END_REF]- [START_REF] Floyd | A silicon 60 GHz receiver and transmitter chipset for broadband communications[END_REF] and various III-V technologies such as GaAs and InP [START_REF] Gunnarsson | Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology[END_REF]- [START_REF] Zirath | Development of 60 GHz front-end circuits for a high-data-rate communication system[END_REF], to mention but a few. Those show its widespread interest between RF-and microwave-research community for performance exploration and improvement. While the demos of those systems can be considered old dated, but their added contribution to the community and value stays the same till this day. Their concept can be re-used in recent years for their originality and enhanced by benefiting from the advancement of semiconductor technologies towards smaller nodes for the purpose of operating at higher frequencies [START_REF] Memioglu | A 300GHz 52mW CMOS Receiver with On-Chip LO Generation[END_REF]- [START_REF] Takano | 17.9 A 105Gb/s 300GHz CMOS transmitter[END_REF].

Move Towards Low-Cost Production: CMOS Technology as a Solution

To meet today needs of the consumer marketplace and the radio chipset to be practical for very large-scale production, the cost, size, and power consumption of any circuit solution has to be significantly below what is being achieved today using compound semiconductor technology. Traditionally, analog radio front-end ICs, especially the ones operating at high frequencies, have been designed using III-V compound technologies which have superior performance compared to SiGe BiCMOS and Si CMOS technologies due to their higher electron mobility [START_REF] Hacker | THz MMICs based on InP HBT Technology[END_REF], [START_REF] Rieh | SiGe HBTs with cut-off frequency of 350 GHz[END_REF].

Still, a CMOS implementation promises higher levels of integration and reduced cost. ICs implemented using CMOS technology directly benefit from the higher speed limit of the scaled technology [START_REF]International Technology Roadmap for Semiconductors[END_REF] and with continued device scaling, enable circuit blocks to operate at ever-increasing frequencies. Typical telecommunication applications require not only transceiver and sensing hardware, but also digital circuity to process the acquired data. Silicon CMOS technologies are good candidates for the integration of such systems. These technologies are being considered particularly attractive for their potential of integration with intermediate frequency (IF) and baseband digital signal processing (DSP) functions, together with high performance analog frontends, enabling true systems-on-chip (SoC).

Move Towards High-Frequency Band: Millimeter-Wave Band as a Solution

Over the last few years, both data center and network traffic increased by several folds, and are still experiencing an ongoing growth at an unsustainable rate [START_REF]Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2017-2022[END_REF]. This increasing demand for higher capacity while meeting with the demand for high end-to-end quality service projects a continuous need for improvements in spectral efficiency enhancement techniques, particularly if the medium has to be shared with many users and interchanged data.

However, a given spectrum band has a limit for the volume of data it can support. Improving its throughput using bandwidth portioning and spectral aggregation techniques has already been exhausted, leading to their evolvement arguably providing insignificant enhancements to the recent spectrum bands since the latter have already reached their saturation level due to being over-packed. This pushes us to search for other solutions and one promising alternative is by arranging more bandwidth. The availability of uncrowded spectrum in the millimeter band to exploit from makes it possible to accommodate future significant increase in network traffic and producing multi-gigabit per second data accesses. This motivated research attempts to overcome the limitation on high frequency of operation through advancement in semiconductor technology process, such as technology scaling, for instance, and in the continuous proposal of innovative analog circuits. For what concerns the latter, it necessitates the development of advanced circuit topologies and suitable design techniques capable of meeting with the marketplace requirements. Therefore, mm-wave ICs is gaining a growing interest and receiving focus from recent activities by the research and development (R&D) department of both private and public sectors.

Move Towards High-Frequency Band: Issues Encountered

Operating at millimeter-wave spectrum, however, is seeing continuous efforts in system design to satisfy the demand for high-speed applications.

Generally speaking, synthesizing analog ICs in the high frequency spectrum subjects one to performance degradation cause by reduced quality of passive components and increase in parasitic that impact the highest operating frequency one could reach. Technological-wise speaking, and in this particular case, the attractive low-cost CMOS processes experience high sheet resistance, strict metal density rules and lossy silicon substrate that makes it challenging to achieve high-end mm-wave CMOS circuits.

In terms of design process, designing at mm-wave renders the conventional analyticalequation based design techniques difficult to be applied. The simplicity offered by them starts to diminish since more behavior-dominant parasitic elements comes into role and become difficult to neglect. Since simplicity is desirable in any design process, approximation is adopted, inaccuracy in design parameter sizing increases and hence dependency on electronic computer-aided design (CAD) softwares grows, such as Keysight Advanced Design System (ADS) or Cadence Virtuoso software. Since the demand of wireless and wireline communication is at high pace, the optimum design of any IC component becomes major part.

Move Towards High-Frequency Band: CAutoD Technique as a Solution

To meet the ever-growing demand of quality and competitiveness, iterative physical prototyping is now often replaced by automated prototyping. The introduction of artificial intelligence (AI) algorithms into the design process realizes an intelligent and automatic design, and consequently considerable time and effort could be saved. Meanwhile, designers will not have the concern that whether a specific topology can meet the design specification or whether another parameters set exists that corresponds to better performance.

However, before any code scripting can be performed or any proposal of algorithms and design methodologies can be possible, developing a suitable physical model that can properly simulate a given circuit behavior is considered an essential first step to this process. This model is required to be complete and accurate, besides offering the designer the possibility to have control over all design variables. Having control over all analogcircuit components equates to having the option to propose several design methodologies meeting multiple design objectives such as maximized output, highest speed, and costeffectiveness, and identifying multiple figures of merit. It also equates to obtaining a design solution considered more of a global optimum solution than a local optimum solution. In addition, an important metric when proposing a design model is simplicity. When speaking of mm-wave IC design, especially, the less the designer has to deal with the plethora of tiny parasitic effects, the easier and time-efficient his design task is considered.

Combining both circuit design-model and the widespread of advance scripting languages will lead to a smart and efficient way of designing mm-wave ICs, which is commonly referred to CAutoD process. Such process will give the designer the ability to virtually explore a complete circuit before it is implemented for production.

Thesis Objectives

After demonstrating the big-picture of this thesis work, one can conclude that the theme of this manuscript will be about IC amplifier design, implemented using low-cost CMOS technology, with amplification bandwidth extending into the mm-wave frequency range. In addition, it emphasizes on the need for a simple design process based on computer automation, from proposing a versatile and complete physical model, and appropriate methodology to achieve a desired performance criterion by the analog designer. Combining both is required to provide optimum sizing-values for the circuit design parameters.

Among wide bandwidth amplifiers, our focus will be laid specifically on distributed amplifiers with the following report organization.

Organization of the Report

The remaining of this manuscript is organized as follows.

In Chapter 2, a specific introduction on wide bandwidth amplifiers is provided. Here, insights on the future trend towards operating at millimeter-wave are first discussed followed by a more particular discussion on distributed amplifier device as a promising solution to overcome the upper limit on frequency.

In Chapter 3, an overview of existing design techniques for distributed amplifiers and their limitations for mm-wave usage are described. An original matrix-based design model, based on four-port chain 𝐴𝐵𝐶𝐷-parameter, is then proposed as a reliable and accurate model for this specific active circuit design to reach full CAutoD process.

In Chapter 4, a loss-compensated distributed amplifier, a topology for mitigating the high losses issue of mm-wave frequencies, is described. Based on its concept and using the proposed model of Chapter 3, an algorithmic design methodology is presented that maximizes bandwidth for a given passband flatness. Its outcome is a set of 3D design space exploration (DSE) plots that enables to explore a wide range of possible distributed amplifier solutions.

In Chapter 5, from the resulting DSE plots of Chapter 4, a global optimum 100-GHz bandwidth CMOS-based distributed amplifier is chosen and implemented for on-wafer characterization.

In Chapter 6, a THz gain-bandwidth cascaded CMOS-based distributed amplifier, with the same upper operating frequency of 100 GHz, is presented.

In the previous three chapters, the 55-nm CMOS process provided by STMicroelectronics (ST) was adopted for both illustration, and design exploration and implementations.

Finally, Chapter 7 provides a summary and general conclusion for the work presented in this manuscript.

Introduction to Wideband Amplifiers -Distributed Amplifier for mm-Wave Access

In this chapter, a particular discussion is devoted on amplifiers capable of extending their operating frequency deep in the mm-wave band and proving distributed amplification as a unique solution with ultra-wide bandwidth performance from a few gigahertz until hundredth of gigahertz. This chapter is structured as follows. Section 2.1 explains the motivation behind recent trend followed by analog designers towards realizing ICs in mm-wave band. It also sheds light on broadband amplification as an indispensable component of high demand in the near future. Section 2.2 examines several amplifier circuit topologies proposed in the literature to overcome the limitation on bandwidth, and demonstrates distributed amplification as a promising candidate for ultra-wide bandwidth. Section 2.3 focuses on the history, principle of operation, and technology versatility of distributed amplifiers. Here, a state-of-the-art table in different technology processes is provided for performance tradeoff comparison. Finally, Section 2.4 concludes this chapter and sets the tasks that will be covered in the following chapters.

Future Trends for Millimeter-Wave Applications

The RF spectrum is a finite resource to be shared by all network devices in the world. As years progress, the number of connected devices and data traffic is increasing at a significant rate, as illustrated in Figure 2.1. Those statistical graphics are provided by Cisco corporation [START_REF]Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2017-2022[END_REF] and demonstrate, via Figure 2.1(a), that by the year 2022 the overall amount of connected devices will reach 12.3 billion units, a 43% growth from 8.6 billion devices in 2017. In addition, via Figure 2.1(b), the overall mobile data traffic is expected to grow to 77 exabytes (10 9 gigabytes) per month by 2022, a seven-fold increase over 2017. Both statistics point to a no nearby deceleration in the amount of circulating information, on the contrary, they indicate a continuous surge in telecommunication in the upcoming years. gigabytes) per month, from 2017 to 2022. [START_REF]Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2017-2022[END_REF] Usually, the frequency spectrum is divided into several differently sized small-portions in order to accommodate the multi RF-applications. A demonstrative example of such radio spectrum partitioning, adopted by the United States [START_REF]United States Frequency Allocations: The Radio Spectrum Chart[END_REF], is illustrated in Figure 2.2. Oversharing of the spectrum, however, can lead to unintentional interference. This can happen between signals through overlapping of a given carrier sideband with upper and/or lower sidebands of adjacent carriers, and interference that occurs when frequencies shift slightly. In either case, they make it difficult or near impossible for receivers to pick out the correct signal. This unintentional interference mostly occurs because generating and treating an RF-signal is an imperfect process. Figure 2.2 can also serve as a visual proof for demonstrating the congestion we reached in recent frequency spectrum due to oversharing. Indeed, the common range spanning from few KHz to 30 GHz is over-populated and it is becoming progressively difficult to open room for future devices and applications, and a bottleneck for the support of the many attractive but bandwidth-demanding services of the coming multimedia society.

Figure 2.2: Radio spectrum demonstrating frequency allocations adopted by the United States. [START_REF]United States Frequency Allocations: The Radio Spectrum Chart[END_REF] One common way used to alleviate this issue is by increasing the spectral efficiency, unit of measurement defined by (bits sec ⁄ ) Hz ⁄ . This can be achieved through signal multiplexing techniques; for instance, through orthogonal frequency-division multiplexing (OFDM). Such ways, however, are starting to reach saturation levels in recent years [START_REF] Clarke | Expanding mobile wireless capacity: The challenges presented by technology and economics[END_REF], as shown in Figure 2.3, where capacity growth is slowing down and unable to keep up with the continuous increase in services demand. Due to occurring congestion in the frequency spectrum below 30 GHz, we reached a period in time where trying to push few bits of extra information in just a single Hertz of frequency component is becoming significantly challenging. Figure 2.3 also gives an early intuition that recent years advancement in radio resources management techniques is slowing down in demonstrating a notable improvement compared to the previous years; therefore, advocating the need to look for other solutions for the years to come. Figure 2.3: Comparing data capacity growth to demand growth. [START_REF] Clarke | Expanding mobile wireless capacity: The challenges presented by technology and economics[END_REF] By referring back to Figure 2.2, one could perceive another promising solution and it is exploring the mm-wave band, i.e., beyond 30 GHz, to arrange more bandwidth. As formalized in the Shannon-Hartley theorem, enlarging bandwidths does indeed comply with obtaining higher channel capacity. In theory, there is an unlimited amount of unexploited bandwidth available in the 300 GHz frequency spectrum. It has motivated many research contributions on mm-wave electronics for wireless communication in general and broadband implementation in particular. Indeed, the sufficient broadband spectrum that exists there has sparked interest in a variety of potential applications, such short-range high data-rate wireless personal area networks (WPANs), wireless local area networks (WLANs) with extraordinary capacity, and wireless uncompressed digital-video transmission. This also allows for a variety of applications including gigabit/s point-topoint links, wireless docking for portable devices, and vehicular radar. Millimeter-wave systems find also place in the field of bio-medical devices. Today, imaging devices are largely confined to health-centers and large hospitals. The dynamics of patient-health provider interaction will radically change if these diagnostic tools are available by patient's side rather than at long distances. Examples include large-array low-power ultrasonic imagers and lab-on-chip devices for rapid detection of pathogens or sequencing of DNA [START_REF] Liu | A CMOS Hall-effect sensor for the characterization and detection of magnetic nanoparticles for biomedical applications[END_REF]- [START_REF] Di Carlo | Dynamic single cell culture array[END_REF]. Diagnostic medical imaging is another application that can greatly benefit from large capacity offered by such spectrum. Even in wireline communication, wireline backbones, such as fiber optic communication systems, with data rates of over 100 Gb/s per channel will be required in the near future and for those ultra-broadband systems with a minimum required bandwidth of 50 GHz are key components in such systems [START_REF] Veith | Gigabit-per-second: Ultra-high transmission bitrate for next generation optical transport networks[END_REF]. Therefore, the 30 GHz-300 GHz spectrum spanning about 55 GHz of contiguous bandwidth is identified as the most suitable candidate to accommodate the ever increase of circulating data deduced. It is also appearing as a promising solution for the support of all kinds of bandwidth-demanding services and applications that run at fiber speeds and beyond.

In fact, significant efforts in the development of ICs with frequencies extending into the mm-wave spectrum is already being observed. In parallel, silicon technology is being considered as an attractive design tool for the cost-reduction and miniaturization offered by it. Those efforts can be noticed from the available state-of-the-art research work [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF]- [START_REF] El-Aassar | A Compact pMOS Stacked-SOI Distributed Power Amplifier With Over 100-GHz Bandwidth and Up to 22-dBm Saturated Output Power[END_REF], [START_REF] Liu | An 80GHz travelling-wave amplifier in a 90nm CMOS technology[END_REF]- [START_REF] Yoon | A Fully-Integrated 40-222 GHz InP HBT Distributed Amplifier[END_REF], to give example of few, which highlights the trend being adopted in pushing the limit of high frequency operation and in enlarging bandwidth performance. Through those available researches, diverse circuit techniques are being proposed besides their corresponding design theory and while offering the design tools and methodologies necessary to replicate such performance characteristics.

In this thesis, efforts were concentrated on broadband mm-wave amplification, in particular on a minimum of 50 GHz bandwidth to support future 100 Gb/s capacity and higher. This is elaborated more in the next section (Section 2.2) where several amplifier topologies, each with its own bandwidth limit, are listed and briefly described, where the most promising one is a distributed structure.

Amplifier Circuit Topologies with Wide Bandwidth Characteristic

As telecommunication technology proceeds, expectations from an amplifier increase with it. Today's telecommunication systems require wideband, efficient and high gain amplifiers. Depending on the application, requirements on an amplifier change. Obtaining high-gain and wideband systems has been one of the main areas of focus in wireless and wireline technologies. In RF and microwave amplifiers, transistors are employed as the main component; however, physical constraints of transistors put an upper limit to the gain and bandwidth of a practical amplifier. This fact is observed as gain-bandwidth product (GBP) which stays constant for an amplifier design. For these reasons, special consideration must be given to the problem of designing wide bandwidth amplifiers. Researchers have come up with some topologies to overcome the limitation on bandwidth. Some of those common approaches are listed below; note in each case that an improvement in BW is achieved at the expense of complexity, i.e., more correlated design variables to take into consideration, an added challenge when searching for optimum performance.

Small-to-Large Bandwidth Amplifiers Topologies

The topic of integrated amplifiers is not considered as a newborn research topic. For that, the literature demonstrates plenty of circuit prototypes implemented in several process nodes and each with different performance improvement objectives. In this section, concentration is put solely on the ones with bandwidth improvement as objective. Those topologies are listed starting by the one that offers the smallest bandwidth and ending by the topology that offers the largest one. For each case, a single optimum design example is given. A short description for each design is given accompanied by frequency behavior examination through 𝑆-parameter analysis.

Single-Transistor Amplifier Topology [24]

We begin this listing by what could be arguably considered as the simplest topology one could synthesize and it involves using a single transistor as Gm-cell. It is considered of importance to demonstrate what one could obtain as frequency behavior when using just a simple transistor biased in the active region in order to support the efforts towards more complex topologies. It will also serve as a performance benchmark for the topologies coming after. [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF] demonstrates such amplifier through a prototype implemented in 90-nm CMOS technology. Figure 2.4(a) and Figure 2.4(b) illustrate the circuit schematic and microphotograph, respectively. This amplifier is synthesized as a three-stage amplifier connected in series in order to increase its gain in the given bandwidth: a sign of weak amplification provided by just a single transistor. From Figure 2.5(a), the fabricated amplifier exhibits 10.8 dB of gain with 5 GHz of 3-dB bandwidth around 60 GHz, i.e., 8.3% of fractional bandwidth (FBW). The total power consumption is only 5.5 mW from a 1-V power supply. From

Resistive-Feedback Amplifier Topology [25]

The first suggested topology for obtaining wide bandwidth amplification is through resistive-feedback configuration [START_REF] Park | A very low power SiGe LNA for UWB application[END_REF]. Figure 2.6(a) illustrates the schematic view of this topology. The resistive shunt-feedback provides wideband input matching. Its bandwidth is dominated by the RC time constant at the input/output node. Figure 2.6(b) shows the implemented microphotograph using 0.18-µm SiGe BiCMOS process. The measured 𝑆parameters are plotted in Figure 2.7. From Figure 2.7(a), a gain of 13 dB with 3-dB bandwidth of 10 GHz is obtained, i.e., more than 100% of FBW. While FBW here does seem interesting at first; however, one should note that as we increase in frequency, the inherent parasitic of the transistor start to affect the shunt matching provided by the resistive feedback. This makes it challenging to maintain wideband matching at mm-wave spectrum and support the efforts for more complex topologies. The fabricated amplifier consumes 4 mA from a 2.4-V power supply. From Figure 2.7(b), the input and output return losses are below -5 dB and -10 dB, respectively, within the declared passband. Through this topology, bandwidth enlargement is possible compared to the single-transistor amplifier topology [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF] discussed at the beginning of this section.

Cascode Amplifier Topology [26]

Since design interest is focused on the mm-wave frequency region, parasitic capacitance becomes difficult to neglect. The most unfavorable capacitance that causes gain and bandwidth degradation a single transistor experiences is the input-to-output overlap parasitic, leading to a parasitic Miller capacitance. Arguably, the most widely used technique to mitigate it is by using a conventional cascode topology, where two transistors configuration is used at its simplest form. [START_REF] Sananes | 52-75 GHz wideband low-noise amplifier in 90 nm CMOS technology[END_REF] demonstrates such cascode cell designed at 60 GHz and implemented with a 90-nm CMOS process. Its circuit topology and microphotograph are shown in Figure 2.8(a) and Figure 2.8(b), respectively. Its frequency response through 𝑆-parameters characterization is demonstrated in Figure 2.9. The amplifier exhibits 14 dB gain with a 3-dB bandwidth of 23 GHz around 60 GHz at 32-mW of total power consumption, i.e. 38.3% of FBW. The input and output return losses are below -8 dB within the declared passband region. Through this topology, a near five-fold fractional bandwidth enlargement is possible compared to the single-transistor amplifier topology [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF] discussed at the beginning of this section.

Balanced Amplifier Topology [27]

A common issue between microwave transistors is that they typically are not well matched to 50 Ω (a common standard reference-impedance). In the case of previous amplifiers topologies, matching networks where used. While matching network provides good input and output matching over the desired frequency bandwidth; however, it gives maximum gain only over a relatively narrow bandwidth. The balanced amplifier circuit solves this problem by using two 90-degree couplers to cancel input and output reflections from two identical amplifiers. [START_REF] Deal | Design and Analysis of Broadband Dual-Gate Balanced Low-Noise Amplifiers[END_REF] demonstrates such topology through a family of balanced amplifiers developed to cover an operating range of 4-40 GHz and implemented in a 0.1-µm pseudomorphic InGaAs/AlGaAs/GaAs HEMT production process. Schematic circuit diagram of only one design is presented here in Figure 2.10(a) with its respective microphotograph in Figure 2.10(b). The first 90° hybrid coupler divides the input signal into two equal-amplitude components, with a 90• phase difference, which drive the two amplifiers. The second coupler recombines the amplifier outputs. Because of the phasing properties of the hybrid coupler, reflections from the amplifier inputs cancel at the input to the hybrid, resulting in an improved impedance match; a similar effect occurs at the output of the balanced amplifier. [START_REF] Deal | Design and Analysis of Broadband Dual-Gate Balanced Low-Noise Amplifiers[END_REF] targeted three designs with different frequency bands including 4-9 GHz, 9-20 GHz, and 20-40 GHz, as illustrated in Figure 2.11. The two first designs demonstrate the excellent qualities of balanced amplifiers in terms of matching characteristics, while proving higher FBW than previously discussed designs, 77% and 76% for the 4-9 GH and 9-20 GHz cases, respectively, with a maximum of -15 dB of return loss for the 4-9 GHz and -17 dB for the 9-20 GHz. The 20-40 GHz also proves an extended bandwidth but return loss is not provided; nonetheless, its FBW extends up to 66.7%. Through the two first topologies, a nine-fold fractional bandwidth enlargement is possible compared to the single-transistor amplifier topology [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF] discussed at the beginning of this section. The third topology shows an eight-fold improvement.

Transformer-Coupled Amplifier Topology [28]

Similar to the balanced amplifier concept, the transformer-coupled topology aims at providing a wide bandwidth input-and output-matched impedances. Instead of using a 90degree coupler, the following topology proposes the usage of transformers for input and output matching. Through them, they can simultaneously perform impedance transformation and differential-to-single-ended conversion. [START_REF] Arbabian | A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna[END_REF] demonstrates such circuit realized in a 0.13-µm SiGe BiCMOS process at 60 GHz with two coupled loop inductors as transformers. Circuit schematic is shown in Figure 2.12(a) with its microphotograph shown in Figure 2.12(b). Performance characterization of the amplifier against frequency is illustrated in Figure 2.13. A 3-dB bandwidth of 56 GHz, from 34 to 90 GHz, i.e. 90% of FBW, is obtained with gain of 12.25 dB while consuming a total 𝑃 𝐷𝐶 of 270 mW. Matching is poorer than 6 dB in the lower band from 34 to 50 GHz. By reducing requirements to a reasonable matching better than 6 dB, the passband reduces within 50 to 90 GHz, i.e. still 57% of FBW that is almost seven-fold the one of the reference single transistor. Nonetheless, by relaxing the constraints on matching characteristic and on the basis of solely the stated amplification-passband 3-dB bandwidth (56 GHz), through this topology almost eleven-fold bandwidth enlargement is possible compared to the single-transistor amplifier topology [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF] discussed at the beginning of this section.

Distributed Amplifier Topology [29]

We end this listing by mentioning the topology that offers the widest bandwidth. Ultrawide bandwidth characteristic is possible with distributed amplifier topology. As a short overview, with more in-depth details on its principle of operation provided in Section 2.3, the DA achieves its large bandwidth trough connecting pair of inductive-type segments at both the input and output ports of Gm-cell. Since the Gm-cell experiences input and output parasitic capacitance at high frequencies, the latter combined with inductive-type segments create what is called artificial transmission line (TL). Those artificial lines provide wide bandwidth matching which makes broadband amplification possible. Meanwhile the high gain of the DA results from the cumulative gains of those small Gm-cells. As a demonstrative example, [START_REF] El-Aassar | A Compact pMOS Stacked-SOI Distributed Power Amplifier With Over 100-GHz Bandwidth and Up to 22-dBm Saturated Output Power[END_REF] illustrated the performance capability of a 100-GHz DA, centered around 50 GHz from 4 to 104 GHz, i.e. 200% of FBW, implemented in a 45-nm CMOS SOI process. The meaning of center operating frequency loses somewhat sense with this architecture that can be seen as an accumulation of small sections of Gm-cells, each one showing an extended cut-off frequency due to inductive-type segments. In spite of that, its cut-off frequency can be adjusted through its design parameters, such as transistor size, and thus justifying the possibility to mention here the 50 GHz center frequency. Figure 2.14(a) and Figure 2.14(b) represent both its schematic diagram and fabricated circuit, respectively. From Figure 2.15, the amplifier attains 16 dB of gain while being powered from a 5-V supply. Through this topology, a twenty-two-fold bandwidth enlargement is possible compared to the single-transistor amplifier topology [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF] discussed at the beginning of this section.

Table-of-Comparison for Performances Analysis

The six amplifier topologies that were presented in subsection 2.2.1 are summarized in Table 2.1. The purpose of this table is to review their performance tradeoffs and highlight, as a matter of course, why, in the context of RF spectrum enlargement towards mm-waves, the suitable topology is distributed amplification that will be the subject of further study in this manuscript. Since overcoming the upper limit on the gain and bandwidth of a practical amplifier is the motivation behind the proposal of such designs, the accent is put here on Gain-Bandwidth product (GBP) criterion. Special consideration on minimum bandwidth of 50 GHz is taken into account as it is important for future 100 Gb/s and beyond applications, as discussed previously in Section 2.1. The first three topologies: single-transistor [START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF], resistive-feedback [START_REF] Park | A very low power SiGe LNA for UWB application[END_REF] and cascode [START_REF] Sananes | 52-75 GHz wideband low-noise amplifier in 90 nm CMOS technology[END_REF] amplifiers are the one which present relatively simple design process compared to the remaining topologies, since they involve few components to deal with. They even show attractive low 𝑃 𝐷𝐶 suited for low power consumption applications. However, they do not meet the required minimum bandwidth of 50 GHz and provide the lowest GBP merit, and hence were disregarded. Balanced amplifier topology [START_REF] Deal | Design and Analysis of Broadband Dual-Gate Balanced Low-Noise Amplifiers[END_REF] could demonstrate possible potentials in reaching this bandwidth requirement when pushed towards higher frequencies and it also shows flexibility in its GBP where one can obtain different BWs using the same topology. However, its design necessitates the implementation of two Gm-cells devices, as illustrated in Figure 2.10(a), hence twice the DC power, but with an overall delivered gain equal to that of a single Gm-cell device.

Both transformer-coupled amplifier [START_REF] Arbabian | A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna[END_REF] and distributed amplifier [START_REF] El-Aassar | A Compact pMOS Stacked-SOI Distributed Power Amplifier With Over 100-GHz Bandwidth and Up to 22-dBm Saturated Output Power[END_REF] topologies fulfill the minimum bandwidth requirement. However, as explained in Section 2.1 and illustrated by Figure 2.1, the number of connected devices and data traffic, in other words, data network, is constantly increasing and with no sign of stopping in the future. At one moment in the future, even larger bandwidths will be of need. Hence, a good research practice would be to anticipate the future and be prepared for the system demand. For that reason, distributed amplifier is chosen as topic of further discussion since it is the only topology that presents potential ultra-wide bandwidth performance reaching deep into the millimeterwave spectrum. It also coincides with continuous advancement in technology nodes where smaller nodes are reaching higher frequency limits. It is worth also adding from a practical point of view, that the transformer-coupled amplifier presents inability to start amplifying from very low frequencies, if needed, compared to distributed amplifier. A requirement for fiber optic communications. This lack of ability to amplify starting from DC-level is because in the former topology, the input signal is being fed through a transformer to the input of the transistor, as shown in Figure 2.12(a), compared to being feed through a transmission line segment as in the case of a DA, as shown in Figure 2.14(a).

As a conclusion and on those bases, the remaining of this chapter is dedicated into describing the DA circuit topology and analyzing its basic principle of operation and performances.

What is a Distributed Amplifier?

In Section 2.1, a serious issue of congestion in the lower side of the radio spectrum due to over-sharing was identified. It highlighted the efforts taken by analog designers in moving towards the unexplored millimeter band as a promising solution to respond to the consumer marketplace for high-speed applications and possibility, by expanding the allocation bandwidth, to accommodate further increase in data traffic. Several proposed amplifier topologies for enlarging bandwidth were discussed in Section 2.2 and demonstrated the trend adopted in continuously trying to push the upper frequency limit. Since DA presented the potentials of achieving the largest bandwidth, suitable for today and future needs, this section is dedicated to elaborate more on the subject. For a systematic presentation, it is divided into four subsections. It starts by presenting the history and interest of DA design since 1936. Then, it introduces its structure and principle of operation. The intention here is to give the reader a first step towards understanding how a DA usually functions and what controls its behavior. Several DAs implemented in different IC technology processes are also provided that demonstrate its widespread popularity between research community for performance exploration. Finally, a state-of-the-art table summarizing all IC DAs in different technology processes is presented and discussed.

Walk Through History

The potential of distributed amplification for obtaining gains over wide frequency bands has long been recognized. Historically, distributed amplifier is an ancient concept appearing in the 20th century. It was first explored by British inventor William S. Percival with vacuum tubes to compensate for the parasitic capacitance of electrodes. He later was the first to deposit a single patent on this topic in 1936 [START_REF]Thermionic Valve Circuits[END_REF], shown in Figure 2.16, but without any exhaustive explanation or any trace of further discussion of this idea in the literature. The work became renown with the publication of [START_REF] Ginzton | Distributed Amplification[END_REF] in 1948, where both Ginzton, Hewlett, Jasberg and Noe, based on the concept disclosed by William Percival, discovered that by appropriate distribution of vacuum tubes along artificial transmission lines, it is possible to obtain amplification over much greater bandwidths than would be possible with ordinary circuits. Their objective at that time was to find a practical solution for extremely broadband "video" amplifiers which have flat frequency response from low audio frequencies to frequencies as high as several hundred Megahertz. Due to technology limitation at their generation, practical limitations of electron tubes prevented them to reach frequencies up to 1000 MHz. Nevertheless, [START_REF] Ginzton | Distributed Amplification[END_REF] was considered the first published research work to present the principle in wide-band amplifier design and hence the term "distributed amplifier" was born. Figure . 2.17 illustrates the general principle of distributed amplification using vacuum tubes as amplification elements presented by [START_REF] Ginzton | Distributed Amplification[END_REF], which later was adopted and still being adopted in recent research work. [38]

Implementation using solid-state devices followed with early demonstration presented by [START_REF] Jutzi | A MESFET distributed amplifier with 2 GHz bandwidth[END_REF] in 1969, where an attempt was made in implementing a distributed amplifier with 2 GHz bandwidth using MESFET technology.

In 1982, [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF] was published introducing a new concept of treating the DA as a continuous-structure model. It provided the required analytical approach to represent a DA gain behavior with respect to frequency and the design tools necessary to size one. In [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF], the design concept was enhanced and made suitable for implementing amplifiers with several gigahertz of bandwidth. They demonstrated their idea through a practical example where they realized a DA that covers 1-13 GHz using 1-µm GaAs FET technology.

Even in the early 21 st century, this concept is still being widely adopted between authors, such as [START_REF] Liu | An 80GHz travelling-wave amplifier in a 90nm CMOS technology[END_REF]- [START_REF] Yoon | A Fully-Integrated 40-222 GHz InP HBT Distributed Amplifier[END_REF], while synthesizing DAs at multi-gigahertz frequencies.

Structure and Basic Principle of Operation

Figure 2.18 illustrates the configuration of a conventional distributed amplifier. The core of a DA design consists of what is commonly referred to as a unit cell. A unit cell is composed of a Gm-cell connected to a set of four inductive-type segments, depicted here as having an inductance value of 𝐿 𝐼 2 ⁄ and 𝐿 𝑂 2 ⁄ , on both its respective input and output sides. A set of 𝑁 unit cells are connected together until a desired overall level of amplification is reached within a given passband. Since every Gm-cell is loading each inductive side by its own inherent output and input complex impedances, the overall upper and lower sides of DA are referred to, in this manuscript, as output-and input-loaded lines, respectively. An RF signal (𝑉 𝑆 ) applied at the input end of the loaded input line travels towards the right side, where it is absorbed by the terminating load impedance 𝑍 4 at the opposite end. As it travels down, each Gm-cell samples a portion of the signal at different phase and amplitude, and then transfer it to the output line through its own transconductance. Due to the non-ideality of those Gm-cells, a small portion of both signals is wasted through dissipation caused by the cells resistive loads distributed along the input and output lines.

If the phase delay of the signal at the output-loaded line is identical to the phase delay of the input-loaded line, then the signals on the former line add constructively. The addition will be in phase only for the forward-traveling signal. There is also a backward traveling wave component on the output line, but the individual contributions to this wave will not be in phase, and therefore they at least partially cancel. Any signal which travels backward and is not completely cancelled by the out-of-phase additions, will be absorbed by the termination output impedance, represented by 𝑍 3 in Figure 2.18.

The basic principle behind distributed amplification is the absorption of the bandwidth limiting parasitic capacitances of Gm-cell into artificial transmission lines, which allows high bandwidths. In this approach, the added inductive-type segments combined with the parasitic capacitances are forming artificial TLs on each sides of the DA. The artificial lines will result in high cut-off frequencies, which will determine the new gain-bandwidth behavior of the desired amplifier. For a more in-depth explanation of this statement, the next discussion is dedicated to presenting the mathematical aspect behind the DA concept. However, beforehand, for a clearer and more realistic analysis, the following modifications are carried out. First, the DA is split into two halves, as shown in Figure 2.19. The lower side represents the input loaded line and the upper side represents the outputloaded line. Second, since by the end of this manuscript a FET-based DA will be implemented as a circuit prototype for on-wafer characterization, it is considered suitable to adopt here, in the theoretical part, a FET-based Gm-cell and represent its behavior by its AC-equivalent lumped model. A unilateral assumption is used for its electrical model for the purpose of simplifying the derivation for a better interpretation of the concept. Finally, since in practice the ideal lumped inductors, 𝐿 𝐼 2 ⁄ and 𝐿 𝑂 2 ⁄ , are typically implemented each as physical microstrip, they are replaced here by microstrip transmission (µ-TL) segments of length 𝑙 𝑔 2 ⁄ and 𝑙 𝑑 2 ⁄ , respectively. The combination of the distributed FET parasitic with the segments creates the artificial transmission lines. The input (gate) and output (drain) loaded-lines are represented by their effective series inductance-per-unit-length 𝛿𝐿 𝑔 and 𝛿𝐿 𝑑 , respectively, of their own segments. Their effective shunt capacitance-per-unit-length is a result of a merge between the parasitic capacitances from the FETs and segments, i.e., (𝛿𝐶 𝑔 + 𝐶 𝑔𝑠 𝑙 𝑔 ⁄ ) and (𝛿𝐶 𝑑 + 𝐶 𝑑𝑠 𝑙 𝑑 ⁄ ), respectively. What remains as resistive lumped elements act as per-unit-length series and shunt losses for those equivalent transmission lines.

The previous assumption of equivalent lines is only valid when the spacing between the FETs, i.e., 𝑙 𝑔 and 𝑙 𝑑 , is very small compared to the wavelength of operation (2.1).

𝑙 𝑔 | 𝑚𝑎𝑥 𝑎𝑛𝑑 𝑙 𝑑 | 𝑚𝑎𝑥 << 𝜆 𝑔𝑢𝑖𝑑𝑒𝑑 = 𝑐 √ 𝜀 𝑒𝑓𝑓 • 𝑓 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛 (2.1)
If this condition is satisfied, both lower and upper lines can be approximated each as continuous structure, referred to as artificial gate and drain lines, since FETs are used. Their characteristic impedances and propagation constants are deduced to be (2.2), (2.3) and (2.4), (2.5), respectively, [START_REF] Pozar | Microwave Engineering[END_REF].

𝑍𝑐
By preserving what was declared as initial condition in (2.1) for short length segments between Gm-cells, the gain expression for an 𝑁-cell DA circuit can be derived as follows.

For an incident source voltage, 𝑉 𝑆 , the voltage on the gate-to-source capacitance of the n th FET, 𝑉 𝑐 𝑛 , can be written as (2.6) for a phase reference from the first transistor.

𝑉 𝑐 𝑛 = 𝑉 𝑆 𝑒 -(𝑛-1)𝛾 𝑔 𝑙 𝑔 ( 1 1 + 𝑗𝜔𝑅 𝑔𝑠 𝐶 𝑔𝑠 ) (2.6)
The factor in parentheses in (2.6) accounts for the voltage division between 𝑅 𝑔𝑠 and 𝐶 𝑔𝑠 . For small node FET parameters, (ω𝑅 𝑔𝑠 𝐶 𝑔𝑠 ) << 1; therefore, this factor can be approximated as unity over the passband of the amplifier.

The output current on the drain line can be found by recognizing that each voltagecontrolled current-source contributes to waves of the form (-1 2 ⁄ )𝐼 𝐷 𝑛 𝑒 ±𝛾 𝑑 𝑥 in each direction when perfect matching is assumed from both sides of each node. Since the transconductance of a given Gm-cell is given, by definition, as 𝐼 𝐷 𝑛 = 𝑔 𝑚 𝑛 𝑉 𝐶 𝑛 , the total output current at the 𝑁 th terminal of the drain line is found to be (2.7), [START_REF] Pozar | Microwave Engineering[END_REF].

𝐼 𝑜 = - 1 2 ∑ 𝐼 𝑑𝑛 𝑒 -(𝑁-𝑛)𝛾 𝑑 𝑙 𝑑 𝑁 𝑛=1 = - 1 2 𝑔 𝑚 𝑉 𝑆 𝑒 -𝑁𝛾 𝑑 𝑙 𝑑 𝑒 +𝛾 𝑔 𝑙 𝑔 ∑ 𝑒 -𝑛(𝛾 𝑔 𝑙 𝑔 -𝛾 𝑑 𝑙 𝑑 ) 𝑁 𝑛=1 (2.7)
Using the geometric series summation formula given by (2.8), allows (2.7) to be simplified as (2.9). For a matched input and output ports, i.e., 𝑍𝑐 𝑔 = 𝑍 𝑖𝑛 = Z 4 and 𝑍𝑐 𝑑 = 𝑍 𝑜𝑢𝑡 = Z 3 , the amplifier gain can be calculated as (2.10), [START_REF] Pozar | Microwave Engineering[END_REF].

∑ 𝑥

𝐺𝑎𝑖𝑛 = 𝑃 𝑜𝑢𝑡 𝑃 𝑖𝑛 = 1 2 |𝐼 𝑜 | 2 𝑍𝑐 𝑑 1 2 |𝑉 𝑆 | 2 𝑍𝑐 𝑔 ⁄ = 𝑔 𝑚 2 𝑍𝑐 𝑔 𝑍𝑐 𝑑 4 | 𝑒 -𝑁𝛾 𝑔 𝑙 𝑔 -𝑒 -𝑁𝛾 𝑑 𝑙 𝑑 𝑒 -𝛾 𝑔 𝑙 𝑔 -𝑒 -𝛾 𝑑 𝑙 𝑑 | 2 (2.10)
As mentioned previously, if the phase velocity of the signal at the drain line is identical to the one of the gate line, then the output signals on the drain line add constructively. The addition will be in-phase only for the forward traveling signal. Referring to equation (2.7), the terms in the summation will add only when 𝛽 𝑔 𝑙 𝑔 = 𝛽 𝑑 𝑙 𝑑 , i.e., the phase delays on the gate and drain lines are synchronized.

Applying the synchronization condition of 𝛽 𝑔 𝑙 𝑔 = 𝛽 𝑑 𝑙 𝑑 allows equation (2.10) to be further simplified to (2.11), [START_REF] Pozar | Microwave Engineering[END_REF]. Several interesting aspects of the distributed amplifier can be deduced from the gain expression of (2.11) and (2.12), as follows. From Equation (2.11), for a lossless distributed amplifier, the gain increase as 𝑁 2 . When loss is present, Equation (2.11) specify that gain approaches zero as 𝑁 tends to infinity. This behavior is explained by the fact that the input voltage on the input-loaded line decays exponentially. The same applies for the outputloaded line. Thus, the FET at the end of the amplifier receive no input signal.

𝐺𝑎𝑖𝑛 = 𝑔 𝑚 2 𝑍𝑐 𝑔 𝑍𝑐 𝑑
Those imply that, for a given set of transistor parameters, there will be an optimum value of 𝑁 that maximizes the gain of the amplifier. This can be found by differentiating (2.11) with respect to 𝑁 and setting the result to zero to obtain (2.13).

𝑁 𝑜𝑝𝑡 =

𝑙𝑛(𝛼 𝑔 𝑙 𝑔 𝛼 𝑑 𝑙 𝑑 ⁄ ) 𝛼 𝑔 𝑙 𝑔 -𝛼 𝑑 𝑙 𝑑 (2.13) This result (2.13) depends on the frequency, the Gm-cell parameters and the line lengths through the attenuation constants given in (2.4) and (2.5).

Performance Demonstration through Different Technologies and Topologies

Distributed amplification topic received popularity between amplifier-research community as being a promising candidate for breaking restrictions on upper frequency limit. Owing to that, a noticeable amount of research work was made public demonstrating the versatility of DA in different IC technology processes from Si, SiGe and compound III-V technologies, such as InP and InGaAs. The common objective between those works, as was also stated by the authors, was presenting the possible performances from gain, bandwidth and 𝑃 𝐷𝐶 one is capable of reaching through each technology. In this section, a handful of design examples that illustrates optimum performance in each technology is provided. Those designs are sorted out on the basis of their GBP achievements before their electrical performance are finally summarized in a state-of-the-art table for tradeoffs comparison in subsection 2.3.4. Only single stage DAs are duly presented herein for stateof-the-art relevance, excluding any cascaded DA configurations where achievable gains are inherently higher. Nonetheless, the later are introduced in Table 2.2 and their interest is justified with the discussion that follows it.

A 4-91 GHz Bandwidth Distributed Amplifier in 90-nm Si CMOS [30]

This article presents the design of a CMOS-based DA implemented in silicon 90-nm process node. This technology is benchmarked at 𝑓 𝑡 = 160 GHz and 𝑓 𝑚𝑎𝑥 = 142 GHz. The DA is synthesized with six unit-cells. Figure 2.20(a) illustrates its circuit diagram and Figure 2.20(b) its microphotograph for on-wafer characterization. The fabricated circuit occupies a chip area of 0.6 ⨉ 1.2 mm 2 including pads. The conventional cascode topology with a two-transistor configuration was adopted for the Gm-cell and coplanar waveguide (CPW) was used for realizing inductive-type segments instead of conventional microstrip lines. Authors explain that with their back-end technology, they could guarantee lower losses at high frequency using CPW topology. Referring to Figure 2.21, the measured 𝑆-parameters performance against frequency is shown. Their six-unit cell DA achieves a peak gain of 7.4 dB with a 3-dB bandwidth of 80 GHz. This results in a GBP of 190 GHz. The amplifier consumes 120 mW from a 2.4-V power supply. The measured output and input return losses across the 3-dB bandwidth reaches a maximum of -10 dB. The reverse isolation is better than -20 dB for the whole passband region.

A 92-GHz Bandwidth Distributed Amplifier in 45-nm SOI CMOS [31]

This article presents the design of a CMOS-based DA implemented in silicon-oninsulator (SOI) 45-nm process node. This technology is benchmarked at 𝑓 𝑡 = 350 GHz and 𝑓 𝑚𝑎𝑥 = 300 GHz. The DA is synthesized with three unit cells. Referring to Figure 2.23, the measured S-parameters against frequency are plotted along with the simulated results. The amplifier achieves a 3-dB bandwidth of 92 GHz and a gain of 9 dB with a gain-ripple of ±1.5 dB inside the passband region. This offers an overall gain-bandwidth of 259 GHz. The amplifier consumes 73.5 mW from a 1.2 V supply. The measured input return loss across the entire 3-dB bandwidth is better than -10 dB, but remains better than -15 dB below 70 GHz. The measured output return losses across the 3-dB bandwidth is less than -6 dB but remains better than -10 dB below 84 GHz. The reverse isolation is -15 dB at 88 GHz and better than -20 dB below 70 GHz.

A 110-GHz Bandwidth Distributed Amplifier in 22-nm FD-SOI CMOS [32]

This article presents the design of a CMOS-based DA implemented in fully-depleted silicon-on-insulator (FD-SOI) 22-nm process node. This technology is benchmarked at 𝑓 𝑚𝑎𝑥 = 396 GHz (authors did not provide value for 𝑓 𝑡 ). The DA is synthesized using eleven unit cells. shows its microphotograph for on-wafer characterization. The chip occupies an area of 0.38 ⨉ 1 mm 2 including the pads. The Gm-cell adopted is based on a cascode topology with a two-transistor configuration and the inductive-type segments are conventional microstrip lines. Referring to Figure 2.25, the measured S-parameters against frequency are plotted along with the simulated results. The amplifier achieves a 3-dB bandwidth of 110 GHz and a gain of 8.5 dB. This offers an overall gain-bandwidth of 292 GHz. The amplifier consumes 80 mW from a 2-V supply. The magnitude of the input and output return losses are both better than -15 dB for the whole amplifier bandwidth. Referring to Figure 2.29, the measured S-parameters against frequency are plotted. The DA covers a 3-dB bandwidth of 110 GHz with 11 dB of gain while consuming a total of 450 mW from a 6-V supply voltage. This leads to a GBP of 373 GHz. The passband region experiences a gain-ripple of around ±1 dB from 5 GHz to 110 GHz. The gain peak, in the frequency range from 2 GHz to 5 GHz, is caused by the inductive feed of the DC bias voltages used for on-wafer measurements. The input return loss is below -10 dB from 10 GHz up to 110 GHz with a maximum of -5 dB for frequencies below 10 GHz. The output return loss is below -7.5 dB from 5 GHz up to 100 GHz.

A 170 GHz Bandwidth Distributed Amplifier in 130-nm SiGe HBT [35]

This article presents the design of a HBT-based DA implemented in 130-nm SiGe-BiCMOS technology. This technology is benchmarked at 𝑓 𝑡 = 300 GHz and 𝑓 𝑚𝑎𝑥 = 500 GHz. The DA fabricated consists of five unit cells and the Gm-cell adopted is based on cascode topology with a three-transistor configuration to increase voltage swing and hence output power. Slow-wave µ-TL line topology was used for the inductive-type segments to reduce lines length. The cascode is designed to compensate the transmissionline-losses at high frequencies in order to extend the bandwidth as well as the GBP. Referring to Figure 2.31, the simulated and measured 𝑆-parameters against frequency are plotted. The amplifier provides a gain of 10 dB up to a 3-dB bandwidth of 170 GHz. It consumes a total of 108 mW FoM a 3.6-V supply. This leads to a GBP of 537 GHz. The passband region experiences a gain-ripple of ±2 dB. The input return loss is below -20 dB up to 100 GHz and then it increases with frequency reaching a maximum of -5 dB at 170 GHz. The output return loss is below -20 dB up to a higher frequency of around 140 GHz and then it starts to increase reaching a maximum of -5 dB at 170 GHz. This article presents the design of an HBT-based DA implemented in 250-nm indium phosphide (InP) technology. This technology is benchmarked at 𝑓 𝑡 ≥ 375 GHz and 𝑓 𝑚𝑎𝑥 ≥ 650 GHz. The fabricated DA consists of four unit cells and the Gm-cell adopted is based on cascode topology with a two-transistor configuration with conventional µ-TL topology for the inductive segments. [36]

State-of-the-Art Table on Distributed Amplifiers

Previously described distributed amplifiers, with extra ones reported for their relevance with this thesis work, are listed in the state-of-the-art table, Table 2.2. The purpose of this table is to summarize the design tradeoffs between integrated technologies when addressing the subject of UWB amplification using DAs. In addition, it will serve us as a reference for later benchmarking when characterizing our own fabricated circuit prototypes.

It is true that the GBP is an appropriate figure-of-merit (FoM) to evaluate the level of improvement offered by a given proposal when pushing the limitation on gain and bandwidth, as demonstrated in Section 2.2; however, the amount of delivered gain per milliwatt of consumption is also an important merit to consider for low-power applications. To account for this design tradeoff and ease of comparison, we define the following new figure of merit (2.14):

𝐹𝑜𝑀 1 = 𝐺𝐵𝑃 𝑃 𝐷𝐶 = 𝐺𝑎𝑖𝑛 • 𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ 𝑃 𝐷𝐶 (𝐺𝐻𝑧 𝑚𝑊 ⁄ ) (2.14)
Surface area could also be of particular interest for some analog designers and distributed amplifier are not far from reserving relatively larger on-chip area compared to other amplifier topologies as an expense for its wider bandwidth. To highlight the area efficiency, we also define the following figure of merit (2.15):

𝐹𝑜𝑀 2 = 𝐺𝐵𝑃 𝑃 𝐷𝐶 • 𝐴𝑟𝑒𝑎 = 𝐺𝑎𝑖𝑛 • 𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ 𝑃 𝐷𝐶 • 𝐴𝑟𝑒𝑎 (𝐺𝐻𝑧 (𝑚𝑊 • 𝑚𝑚 2 ) ⁄ ) (2.15)
In this thesis, our emphasis is placed on (2.14). We believe that area reserved by an amplifier, or any integrated circuit in a general context, is highly dependent on the process technology node, where smaller nodes tend to be more efficient in occupied area than larger nodes. In addition, it depends on the design rule restrictions that accompanies a given process, where nodes having stringent density rules can lead to large area than less restrictive nodes. We also believe that the amount of surface area occupied is ultimately influenced by the end-objective of the designer circuit prototype; it depends on what design characteristic the designer opted his efforts on and providing improving for the research community.

Table 2.2 compares results from state-of-the-art FET-and HBT-based DAs. HBT-based DAs, [START_REF] Testa | 170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier[END_REF], [START_REF] Yoon | A Fully-Integrated 40-222 GHz InP HBT Distributed Amplifier[END_REF], [START_REF] Eriksson | InP DHBT Distributed Amplifiers With Up to 235-GHz Bandwidth[END_REF], [START_REF] Arbabian | A 94 GHz mm-Waveto-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition[END_REF], have been reported to provide larger bandwidths, beyond 100 GHz, thereby contributing to a much higher GBP merit. This is due to HBTs impressive cutoff frequencies [START_REF] Hacker | THz MMICs based on InP HBT Technology[END_REF], [START_REF] Rieh | SiGe HBTs with cut-off frequency of 350 GHz[END_REF] compared to their cheaper CMOS counterparts. In addition, due to the bipolar transistor capability in providing much higher transconductance, bipolarbased DAs provide much higher gain for relatively similar 𝑃 𝐷𝐶 , in the hundreds milliwatt, to the other technology processes. This can explain their higher 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit. In terms of surface area reservation, they also present higher 𝐺𝐵𝑃 (𝑃 𝐷𝐶 • 𝐴𝑟𝑒𝑎) ⁄ merit. This is also due to its advantageous transconductance. For instance, for a similar gain of around 10 dB, [START_REF] Testa | 170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier[END_REF] implemented a five unit-cells HBT-based DA while [START_REF] Kim | A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS[END_REF] implemented a nine unit-cells CMOS-based DA.

Analyzing the design tradeoffs between FET-based DAs, III-V technologies [START_REF]112-GHz, 157-GHz, and 180-GHz InP HEMT traveling-wave amplifiers[END_REF], [START_REF] Zech | An ultra-broadband low-noise traveling-wave amplifier based on 50nm InGaAs mHEMT technology[END_REF], [START_REF] Masuda | An over-110-GHz InP HEMT flip-chip distributed baseband amplifier with inverted microstrip line structure for optical transmission system[END_REF], [START_REF] Li | A 2 to 92 GHz distributed amplifier using 70-nm InP HEMTs[END_REF] offer superior GBP merit than silicon semiconductor technologies. This is due to their high electron mobility, but at the expense of much larger 𝑃 𝐷𝐶 , which is why they present low 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit and, hence, could be considered as not appropriate for applications where low power consumption is critical.

Analyzing the performances of the CMOS-based DAs, using the cheap silicon technology, such as in [START_REF] Liu | An 80GHz travelling-wave amplifier in a 90nm CMOS technology[END_REF], [START_REF] Kim | A 92 GHz Bandwidth Distributed Amplifier in a 45 nm SOI CMOS Technology[END_REF], [START_REF] Kim | A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS[END_REF], [START_REF] Plouchart | A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology[END_REF], they do offer comparable gain with bandwidths reaching above 70 GHz. In order to boost their relative low gain and obtain much higher 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ performance, [START_REF] Tsai | A 70GHz cascaded multistage distributed amplifier in 90nm CMOS technology[END_REF] and [START_REF] Arbabian | A tapered cascaded multi-stage distributed amplifier with 370GHz GBW in 90nm CMOS[END_REF] demonstrate the technique of cascading multiple single-stage DAs. This technique helps in rising the GBP merit; for example, for the same 90-nm process node, [START_REF] Arbabian | A tapered cascaded multi-stage distributed amplifier with 370GHz GBW in 90nm CMOS[END_REF] demonstrates an excess of two-fold improvement in their cascaded DA circuit compared to [START_REF] Liu | An 80GHz travelling-wave amplifier in a 90nm CMOS technology[END_REF] that implemented just a single-stage DA circuit.

A final observation worth highlighting is that all of the mentioned state-of-the-art DAs here have adopted a cascode topology for their Gm-cell when synthesizing their unit cell. This is even perceptible through the schematic diagrams of each research work discussed in previous subsection 2.3.3, where the most common configuration is a cascode made of two transistors. This could advocate the easiness that follows from implementing a cascode topology where the purpose of adding the upper transistor is to mitigate the Miller effect that results from the input-to-output overlap capacitance of the lower transistor. It also advocates for its capability in being a suitable solution to provide gain for mm-wave signals.

For this reason, cascode Gm-cell topology will be adopted later when implementing our proper DA circuits, which also would give a fair comparison to the already published stateof-the-art ones. & BWs are reported as declared by authors. £ Ripple limits is determined within the authors declared BW for their reported gain. % Estimated from plots @ Cascaded Multi-stage DA (CMSDA) $ Cascaded single-stage DA (CSSDA) # Flip-Chip DA * Biased using external bias-tee ** Biased using integrated bias-tee

Conclusion

This chapter stressed on the importance and the necessity of providing large bandwidth amplifiers in present time due to its rise in value and need in the upcoming future for higher spectrum capacity and data rates reasons. Several amplifier topologies from small to large bandwidth performance were presented, but the choice of study at the end was placed on distributed amplifier device as it showed to be the only design solution that can provide interesting ultra-wide amplification bandwidth. This mainly due to its capability provide impedance matching over an extremely wide frequency range by creating artificial transmission lines through distribution of Gm-cells between inductive-type segments. Its history, principle and technology-process versatility were also presented. From equation (2.11), design complexity was detected where design variables from number of unit cells and dimensions of both Gm-cell and inductive-type segments are correlated, and need to be studied simultaneously to meet multiple design objectives to find the best design.

On that basis, the following tasks are set to be covered in the next chapters of this thesis manuscript:

 Propose a DA model suited for mm-wave application that is considered complete when it comes to describing frequency behaviors, such as gain response, for instance, by taking into account the whole design parameters the conventional DA can be made synthesized from.

 Propose a design methodology, based on our DA model, that demonstrates optimum sizing of DA design parameters that will then assist us in choosing the highest 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ metric (2.14), a desirable criterion for low-consumption application.

 Finally, validate the proposed design process through on-wafer characterization of both a single-stage and cascaded stages CMOS-based DAs.

In the next chapter, Chapter 3, we begin by discussing the already existing design techniques for DAs and discussing our own newly proposed model.

Chapter 3

Proposition of a Novel Model to Design DAs: the Four-Port Chain (ABCD) Model

In the previous chapter, the topic of DA was introduced. Both its principle of operation and performance abilities with different technology processes were investigated. In this chapter, its design process is discussed. The commonly used techniques are described first, followed by introducing a new design model for DAs that assists in successful realization of CAutoD process and offering a different approach of designing using scripting methods. This chapter is structured as follows. Section 3.1 starts by stating the requirements for what a proposed physical model is believed to fulfil in order for it to be considered complete and general, suitable for mm-wave IC design. Section 3.2 reviews already existing techniques, from models and methods, suggested for distributed amplifier design. Section 3.3 goes through the limitations those techniques impose, in particular when dealing with operating frequencies reaching into the millimeter spectrum. Section 3.4 introduces a novel matrix-based design model using Chain (𝐴𝐵𝐶𝐷) parameters. Finally, Section 3.5 summarizes and concludes this chapter.

Introduction

For the realization procedure of an IC, an initial step to consider beforehand is the design approach; i.e., how a given circuit will be sized to reach the required performance before being sent to the final stage of fabrication and measurement-based characterization. For a mm-wave IC, the design process starts by having a corresponding physical model, will it be by deriving analytical model or through graphical interface using CAD software, that relates the circuit design variables to its performance characteristics. This aids the designer to have a better understanding on how the circuit works and determining which parameters plays what role on the circuit behavior. For instance, since the discussion is dedicate for DA device, referring to Figure 2.18 the recurrent variables in its design are the number of unit cells (𝑁) and Gm-cell size; by proposing a given type of physical model that relates to its 𝑆-parameters, the performance of the DA can be analyzed and used for designing one. The latter parameters set is highlighted since it is popularly used in microwave engineering to describe the electrical behavior against frequency and useful in determining the electrical properties of the circuit at hand such as gain, bandwidth and ports mismatch level.

A detailed inspection of different design techniques that can be used in DA design has been conducted and subsequent Section 3.2 is dedicated to reviewing them. During this inspection process, we took note of criteria we wanted to satisfy as a whole through our own proposed design technique and we listed them here. We deduced that the degree of usability of a design model can be determined through:  First, how complete it is. This is defined by the amount of variables the model takes into consideration and influences its ability in producing optimum design end-results; when the model is constructed from the complete set of design parameters the circuit is made from, its suggested performance starts to be defined as a global optimum solution rather than a local one. In addition, those amounts of variables influence the number of possible design methodologies a designer produces from it to satisfy different desired performance merits.  Second, its versatility. A model can be considered general when it can easily be exchanged between technology processes, in addition to having the ability to be adopted to several proposed topologies. That is to say, if a designer is interested in using a different component topology from the one used when producing a given tool, the model should be able to be adapt to the designer needs.  Third, its complexity. Since this thesis theme is about mm-wave circuits, more parasitic element comes into role and have a dominant impact on the circuit frequency behavior. The attempts to take into account all tiny effects in order for it to be considered accurate to simulate a circuit behavior lead to an excessive complication of the model. This can be observed, for instance, when attempting to derive an analytical-equation based model that represent the frequency behavior for the IC under study through representing first all of its components with their respective complete AC equivalent network.  Finally, its reliability in simulating the circuit behavior. Again, this is crucial since we are dealing with millimeter IC design; simplifying through neglecting those parasitic elements degrades the overall accuracy of the proposed model, devaluating all results of circuit analysis and thereby rendering it unsuitable for higher frequencies usage.

The target in this thesis is set to take into account those criteria and propose a complete model, without any approximation, for mm-wave DA design. Its main purpose is to be used in scripting-based design technique and successful implementation of computer automation to render the design process simple and fast. Our end-goal is to offer the designer a different and interesting technique (other than conventional analytical approaches) in which the outcome of the suggested CAutoD process is a set of 3D graphical design exploration plots (DSE) plots. Designers then can explore through them different possible solutions and choose the best design that meet their multiple performance objectives.

Existing Distributed Amplifier Design Techniques

Several design techniques already exists in the literature and usually each proposal comes as an improvement for precedent works. While they are useful for preliminary sizing, they were deduced to be not complete. Each proposed model is based on certain assumptions that makes its outcome correct within design limitations. In addition, they demonstrate a compromise between reliability, complexity and completeness. Simplicity was deduced to be the most preferable through approximation and elements neglecting, which leads to a less reliable model and, thereby, lower optimum performance distant from being considered a global solution choice. This section starts by presenting the most common approach in representing a DA [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF], since 1982, and progress through the available improvements until recent day's technique is discussed, in which designers rely more often on CAD tools. In the next section, Section 3.3, their limitations are discussed.

Artificial-Line Based Model [40]

The first physical model proposed for DAs dates back to 1982. It is still being referenced by recent publications [START_REF] El-Aassar | A Compact pMOS Stacked-SOI Distributed Power Amplifier With Over 100-GHz Bandwidth and Up to 22-dBm Saturated Output Power[END_REF], [START_REF] Kim | A 92 GHz Bandwidth Distributed Amplifier in a 45 nm SOI CMOS Technology[END_REF], [START_REF]112-GHz, 157-GHz, and 180-GHz InP HEMT traveling-wave amplifiers[END_REF], [START_REF] Arbabian | A tapered cascaded multi-stage distributed amplifier with 370GHz GBW in 90nm CMOS[END_REF], [START_REF] Li | A 2 to 92 GHz distributed amplifier using 70-nm InP HEMTs[END_REF], [START_REF] El-Aassar | A DC-to-108-GHz CMOS SOI Distributed Power Amplifier and Modulator Driver Leveraging Multi-Drive Complementary Stacked Cells[END_REF], [START_REF] El-Aassar | A Cascaded Multi-Drive Stacked-SOI Distributed Power Amplifier With 23.5 dBm Peak Output Power and Over 4.5-THz GBW[END_REF], while explaining the concept of a DA. It is a set of mathematical equations derived from portraying the input and output loaded lines as artificial lines. Due to this assumption, they refer to their DA as a travelingwave amplifier. This concept was already described in details in Chapter 2 (Section 2.3) with equation (2.11) derived to model the DA gain behavior with respect to frequency. It was derived while assuming the µ-TL-type segments a unit cell is made from as an equivalent lumped-element circuit with the intrinsic per-unit-length parasitic quantities, i.e. 𝑅𝐿𝐶𝐺-lumped circuit. In addition, it considers the influence of transistor through its unilateral AC equivalent circuit. To prove the validity of their model, the authors in [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF] implemented a 1 ̶ 13-GHz distributed amplifier using 0.1-mm GaAs process node. Figure 3.1 illustrates the 𝑆-parameter results versus frequency through on-wafer characterization. Indeed, their proposed mathematical gain-model is shown to fit their measured DA gain up to 12 GHz.

Stage-Scaling Based Model [51]

Due to the assumption of artificial lines and identical transistor dimension across all unit cells, the conventional model introduced first is limited only to uniform DAs design. [START_REF] Chen | Design and Analysis of a Stage-Scaled Distributed Power Amplifier[END_REF] demonstrated a modified version of this analytical-based model where each unit cell is now considered independent and, hence, its own µ-TL-type segments and Gm-cell can be sized differently. Their main objective was to offer a methodology to enhance the power added efficiency (PAE) of DAs. This was achieved through a stage-scaling technique for the output-loaded line to utilize more voltage swing while reducing the total current consumption. The design technique and analysis provided by [START_REF] Chen | Design and Analysis of a Stage-Scaled Distributed Power Amplifier[END_REF] are derived for bipolarbased DAs, but can as well be adapted to FET-based DAs. In a stage-scaled DA, the loaded collector-line impedance and the transistor size are scaled simultaneously from unit cell to another. Figure 3.2 illustrates such design example implemented by [START_REF] Chen | Design and Analysis of a Stage-Scaled Distributed Power Amplifier[END_REF]. Both collectorline TL width and cascode transistors sizes are increasing as they approach the last unit cell. It is noticeable for this particular example that the first three stages of the amplifier are not scaled; based on the authors, this is due to the highest T-line impedance achievable onchip which is restricted by the minimum metal width rule of their process technology. In addition, the base-line TL width is kept the same since negligible current is being consumed and hence no significant enhancement in the PAE of the DA. The wave propagation constant, derived by [START_REF] Chen | Design and Analysis of a Stage-Scaled Distributed Power Amplifier[END_REF], describing the output-loaded line is given by (3.1a). It is noticeable how the scaling process is achieved through introducing the design term 𝜂 𝑐,𝑖 (3.1b); where 𝑖 th is the position of the unit cell. It is defined as the ratio between the intrinsic and loaded collector-line characteristic impedance, denoted by 𝑍 𝐶0,𝑖 (3.1c) and 𝑍 𝐶,𝑖 (3.1d), respectively. The terms 𝑅 𝑐𝑙 , 𝐶 𝑐𝑙 and 𝐿 𝑐𝑙 represent the equivalent 𝑅𝐿𝐶𝐺-element circuit of the µ-TL-type segments, and 𝐶 𝑜𝑢𝑡 and 𝐺 𝑜𝑢𝑡 represent the output complex impedance of the Gm-cell device used. Assuming phase synchronization between output and input lines, i.e., 𝛽 𝑐 𝑙 𝑐 = 𝛽 𝑏 𝑙 𝑏 , the total output voltage swing arriving at the load is found to be (3.2). The terms 𝑍 𝐿 and 𝐼 𝑐 are the impedance and DC-current of the last unit cell. The term "𝑘" is the scaling factor for both the transistor size and the dc-bias current between two adjacent unit cells in the direction from the output to the input. The term "𝓏" is the scaling factor of the loaded collector-line impedance seen by the Gm-cell between two adjacent unit cells in the same direction.

𝛾 𝑐,𝑖 = 𝛼 𝑐,𝑖 + 𝑗𝛽 𝑐,𝑖 (3.1a)
𝑉 𝑜𝑢𝑡 = ∑ 1 2 𝐼 𝑐 𝑍 𝐿 (𝑘 2 𝓏) 𝑁-𝑛 2 𝑒𝑥𝑝 (-∑ 𝛼 𝑐,𝑖 𝑙 𝑐,𝑖 𝑁 𝑖=𝑛 ) 𝑁 𝑛=1 (3.2)
Indeed, through the suggestion of (3.2), higher degree of design freedom is possible since more variables are available and each unit cell is treated independently. This also results in the ability to explore a broader range of performance solutions compared to [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF].

Distributed-Line Based Model [52]

The physical model provided by [START_REF] Chaar | A Non-Closed-Form Mathematical Model for Uniform and Non-Uniform Distributed Amplifiers[END_REF] comes as an improvement for both [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF] and [START_REF] Chen | Design and Analysis of a Stage-Scaled Distributed Power Amplifier[END_REF] models. Contrary to traditional ways of treating the unit-cell µ-TL-type segments as equivalent 𝑅𝐿𝐶𝐺-lumped circuit, [START_REF] Chaar | A Non-Closed-Form Mathematical Model for Uniform and Non-Uniform Distributed Amplifiers[END_REF] treats each segment as a real microstrip line with its own distributed effect. Through this change, propagation and mismatch impact between inter-cells are now taken into considered. This provides an extra degree of accuracy when performing preliminary sizing, since a more realistic representation of the TL losses is now considered. In addition, [START_REF] Chaar | A Non-Closed-Form Mathematical Model for Uniform and Non-Uniform Distributed Amplifiers[END_REF] treats the distributed amplifier as a discrete set of cells connected together, contrary to the continuous artificial line concept of [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF] and [START_REF] Chen | Design and Analysis of a Stage-Scaled Distributed Power Amplifier[END_REF]. This treatment is considered a more realistic approach, since in practice the Gm-cells induce amplification at specific discrete positions (nodes) between the input to output loaded-line; therefore, it will lead to a more reliable representation of the DA amplification response. The output port of the Gm-cell is depicted by a voltage-controlled current source with a complex parallel RC-impedance denoted by 𝑅 𝑑𝑠 𝑛 and 𝐶 𝑑𝑠 𝑛 . The Gm-cell is connected in the middle of two µ-TLs-type segments denoted by subscripts '𝐿', for left side, and '𝑅', for right side. The influence of the preceding and subsequent unit cells is taken into consideration in this illustration, as they will affect the total output current generated by the unit cell under study. The latter is done as follows. Equivalent impedances 𝑍 𝑒𝑞𝑢𝐿 𝑛 and 𝑍 𝑒𝑞𝑢𝑅 𝑛 model all the unit-cells seen on the left and right sides, respectively, of the 𝑛 th unit cell under study. Current 𝐼 𝑜𝑢𝑡 𝑛-1 , flowing from the left side, represents the total current wave generated by the preceding cells traveling towards the right side. Impedance 𝑍 𝐿 𝐿𝑛 represents the input impedance seen by the µ-TL-type segment (𝑍 𝑑 𝐿𝑛 ,𝛾 𝑑 𝐿𝑛 ) on its left side towards its right side while being loaded on its right side by impedance 𝑍 𝐿 𝑅𝑛 in parallel with output impedance of the Gm-cell (𝑅 𝑑𝑠 𝑛 , 𝐶 𝑑𝑠 𝑛 ). Impedance 𝑍 𝐿 𝑅𝑛 represents the input impedance seen by the µ-TL-type segment (𝑍 𝑑 𝑅𝑛 , 𝛾 𝑑 𝑅𝑛 ) on its left side towards its right side while being loaded on its right side by 𝑍 𝑒𝑞𝑢𝑅 𝑛 . Impedance 𝑍 𝑅 𝑅𝑛 represents the input impedance seen by the µ-TL-type segment (𝑍 𝑑 𝑅𝑛 ,𝛾 𝑑 𝑅𝑛 ) on its right side towards its left side while being loaded on its left side by impedance 𝑍 𝑅 𝐿𝑛 in parallel with output impedance of the Gm-cell (𝑅 𝑑𝑠 𝑛 , 𝐶 𝑑𝑠 𝑛 ). Impedance 𝑍 𝑅 𝐿𝑛 represents the input impedance seen by the µ-TL-type segment (𝑍 𝑑 𝐿𝑛 , 𝛾 𝑑 𝐿𝑛 ) on its right side towards its left side while being loaded on its left side by 𝑍 𝑒𝑞𝑢𝐿 𝑛 .

Based on this configuration and applying Kirchhoff's laws and microwave TL theory, the total current wave traveling towards the right side of the nth Gm-cell, 𝐼 𝑡𝑤 𝑛 , is expressed as ( In order to determine the amount of current that a given n th unit-cell transmits to the entire right-side unit cells, represented by an equivalent impedance 𝑍 𝑒𝑞𝑢𝑅 𝑛 in Figure 3.3, the transmission coefficient of the right µ-TL-type segment (𝑍 𝑑 𝑅𝑛 , 𝛾 𝑑𝑅 𝑛 ) is introduced to the input current expressed in (3.3), and hence the total output current comes to (3.7);

𝐼 𝑜𝑢𝑡 𝑛 = 𝐼 𝑡𝑤 𝑛 𝑇 𝑑𝑅 𝑛 = -𝐼 𝐷 𝑛 𝟋 𝑅 𝑛 𝑇 𝑑𝑅 𝑛 + 𝐼 𝑜𝑢𝑡 𝑛-1 𝟋 𝑆 𝑛 𝑇 𝑑𝐿 𝑛 𝑇 𝑑𝑅 𝑛 (3.7)
where the transmission coefficient 𝑇 𝑑𝑅 𝑛 stands for the 𝑛 th right µ-TL-type segment (𝑍 𝑑𝑅 𝑛 , 𝛾 𝑑𝑅 𝑛 ) and is calculated using (3.8a);

𝑇 𝑑𝑅 𝑛 = (1 + Г 𝑖𝑛𝑑𝑅 𝑛 )(1 + Г 𝑜𝑢𝑡𝑑𝑅 𝑛 )𝑒 -𝛾 𝑑𝑅 𝑛 𝑙 𝑑𝑅 𝑛 1 + Г 𝑖𝑛𝑑𝑅 𝑛 Г 𝑜𝑢𝑡𝑑𝑅 𝑛 𝑒 -2𝛾
𝐼 𝑜𝑢𝑡 = ∑ -𝐼 𝐷 𝑛 [∏(𝑇 𝑑𝑅 𝑖 𝟋 𝑅 𝑖 ) 𝛿 〈𝑖,𝑛〉 (𝟋 𝑆 𝑖 𝑇 𝑑𝐿 𝑖 𝑇 𝑑𝑅 𝑖 ) 1-𝛿 〈𝑖,𝑛〉 𝑁 𝑖=𝑛 ] 𝑁 𝑛=1 (3.9)
For the gate line analysis, a similar approach to that of the drain line analysis was applied. Based on Figure 3.5, the gate side of the Gm-cell is depicted as an equivalent impedance of series resistor and capacitor, denoted 𝑅 𝑔 and 𝐶 𝑔𝑠 , respectively. One can perceive that the input loaded-line is similar to a transmission line periodically loaded by 𝑁 complex series RC-impedances. Based on this configuration, the approach was focused on determining the voltage 𝑉 𝐶 𝑛 at each gate-source capacitor 𝐶 𝑔𝑠 𝑛 for the 𝑛 th unit-cell when a given voltage source 𝑉 𝑆 is applied (𝑉 𝐶 𝑛 is the control voltage of the controlled current source 𝐼 𝐷 𝑛 in Figure 3.3). This resulted in the non-uniform capacitor voltage-expression (3.10). The parameter linking the output loaded-line, modeled by (3.9), and the input loadedline, modeled by (3.10), is the transconductance (𝑔 𝑚 ) of the n th Gm-cell topology used which relates its output current (𝐼 𝐷 𝑛 ) to its input control voltage (𝑉 𝐶 𝑛 ) as given by (3.12).

𝑉 𝐶

𝐼 𝐷 𝑛 = 𝑔 𝑚 𝑛 𝑉 𝐶 𝑛

(3.12)

Using equations (3.9), (3.10) and (3.12), the designer can now evaluate more accurately the impact of each design parameter the distributed amplifier is made from, as well as treat each unit cell separately and arrive at the end of the design process to an optimum and more realistic performance.

Artificial Neural Network Based Model

Another modeling technique worth mentioning is through artificial neural network. Since in mm-wave spectrum more elements for representing a certain behavior have to be taken into consideration, the process of deriving equations is shortened through machine learning. Artificial neural network is one topology of machine learning that identifies the relationship (function) between a given set of data and already known outcomes. It does this through artificial intelligence algorithms where they tune its function constants until they find the parameter sets that best matches the training set, i.e., already observed input and output data. Figure 3.6 illustrates an example of a simplified neural network structure. It is made of three layers. The left most side represents its input layer, it is made of a total of 𝑖 input pins where design parameter set are fed. The right most side represents the output layer, it is made of a total of 𝑛 output pins; this depends on what the designer is interested in providing as design characteristics. The middle layer is composed of a two-dimensional array of neurons, which are the function constants that will be optimized. After the training stage, the neural network can be used to predict possible characteristic outcomes from a new different input dataset within the possibility of the pre-trained set. Such machinelearning modeling technique has been demonstrated in [START_REF] Luongvinh | Behavioral modeling of power amplifiers using fully recurrent neural networks[END_REF]- [START_REF] Ali | Design and Modeling of RF Power Amplifiers with Radial Basis Function Artificial Neural Networks[END_REF], for instance, for modeling power-amplifier behaviors. Compared to previously mentioned mathematical equationbased modeling techniques, by using neural network technique there is no need for the designer to be concerned with any tiny effects that impact circuit behavior. Thereby, arguably it could be considered as a simple and fast technique to use during a circuit design process, since it can be considered similar to a multi-variable curve fitting approach. However, it should be highlighted the importance of the pre-training process step needed to make the neural network work. For instance, when dealing with the DA circuit, as a beforehand step the designer needs to simulate several already designed 𝑁 unit-cells DAs and use those simulations results for the neural network model training (fitting) process. This means that when the model becomes ready to be used again in a new design task, its prediction relies on how adequately the pre-training circuits set were designed. For us, we are interested in providing a design model that discovers the optimum performance (first criterion, Section 3.1).

Widespread Design Technique: Through CAD Software

The final design technique that could be considered the most preferable and reliable way for DAs, or any electronic circuit in a general context, is through a computer-aided design (CAD) software. Traditionally, circuits are first assembled on a graphical user interface by picking the required components from the design library. Then, a set of desired performance goals are defined and the circuit variables intended to be tuned are enumerated. Through the usage of iterative optimization functionality, the CAD software configures automatically those variables through several iterations until the declared goals are fulfilled or closely achieved. This technique is proven to be the most accurate procedure one can have, since no assumption is made, and the closest one in simulating circuit behavior to real-life measured behavior. Several CAD tools exists, but for RF/Microwave integrated circuit design the most famous ones are Keysight ADS and Cadence Virtuoso softwares. Both tools provide fully-custom integrated design environment to designers of RF electronic products such as mobile phones, wireless networks, satellite communications, radar systems, and high-speed data links. They support every step of the design cycle from schematic entry, layout, design rule checking (DRC), frequency-domain and time-domain circuit simulation, and sometimes electromagnetic field simulation, allowing the designer to fully characterize and optimize an RF design without changing CAD platforms. Figure 3.7 provides a demonstrative example of a DA circuit synthesized on ADS software schematic where the transistor sizes are defined as a single variable, and random optimization is being applied until designer-defined gain (𝑆 21 ) goal is reached.

Design Limitations when Operating in mm-Wave Band

Five different techniques where mentioned for DA design. From mathematical-based approaches, to artificial intelligence-based techniques and through schematic-level design environments using CAD tools. However, a set of limitations have been detected for each technique and are described as follows.

First, neglecting the inter-stage propagation, where spacing between individual Gm-cells is assumed small compared with the wavelength of operation (𝜆 𝑜 ). This is observed in the first model (subsection 3.2.1) and second model (subsection 3.2.2) through their artificial line assumption. While valid for low frequency of operation, it neglects the transmission line theory for the implemented physical TL spacing that takes effect especially when dealing with DAs extending into the mm-wave region.

Second, neglecting the fact that the Gm-cells embedded between the two lines induce amplification at discrete positions rather than the assumed continuous manner. A limitation also observed in the first two models discussed in Section 3.2. This pair of limits lead to constraining design formulas usability, and hence the DSE reliability, to only synthesizing DAs that require TL spacing between consecutive Gm-cells with electrical length (𝛽𝑙) ≪ 𝜋 2 ⁄ , or synthesizing DAs that amplify signals with long wavelengths, in other words DA with smaller bandwidth [START_REF] Pozar | Microwave Engineering[END_REF].

Both assumptions were fixed through (3.9) model (Subsection 3.2.3) where [START_REF] Chaar | A Non-Closed-Form Mathematical Model for Uniform and Non-Uniform Distributed Amplifiers[END_REF] rederived DA physical equation while keeping each TL segment as a real physical µ-TL with its distributed effect. However, even with this improvement, until now both [START_REF] Ayasli | A Monolithic GaAs 1-13-GHz Traveling-Wave Amplifier[END_REF], [START_REF] Chen | Design and Analysis of a Stage-Scaled Distributed Power Amplifier[END_REF], [START_REF] Chaar | A Non-Closed-Form Mathematical Model for Uniform and Non-Uniform Distributed Amplifiers[END_REF], suggested models are still considered as approximate representation of the DA behavior since they are produced based on the assumption of a unilateral two-port AC equivalent model for transistor. This leads to the third design limitation caused by assuming a simple Gm-cell model. The central element of a DA is its Gm-cell; as operating frequencies increase, amplifier designers can no longer benefit from transistor unilateral approximation where Miller effect starts to have a dominant impact. This assumption leads to discrepancy in predicting its behavior, and hence that of the DA, and results in suboptimal Gm-cell sizing. The arguably widely adopted way for improving reverse isolation, as observed in Chapter 2 (subsection 2.3.3) where DAs in different technology processes are presented, is by implementing a conventional cascode configuration. Even then, modeling the DA equivalent circuit becomes complicated since the high-frequency equivalent circuit for a single transistor biased in active region becomes large with a plethora of parameters [START_REF] Tsividis | Operation and modeling of the MOS transistor[END_REF]. It becomes more complicated for a cascode Gm-cell since it involves stacking a minimum of two transistors, rendering analytical expressions based design processes for mm-wave DAs quite cumbersome. This is without considering transistor non-quasi-static behavior that appears when operating deep into mm-wave spectrum. Furthermore, in bulk technology, the transistor is a four-terminal device in which the substrate influence can no longer be disregarded.

Fourth limit, and this is more specific for neural-network based modeling approach, is using a design model constructed from a beforehand step of function fitting to a series of already observed data. While this approach does simplify the derivation process, where one is no longer subjected to the hustle to derive equations and taking into account all tiny effects; however, the degree of optimum performance it predicts for a design characteristic is bounded within how well designed the pre-training circuit set were when used during the fitting pre-process. Another limit for the same modeling approach is its reliability being bounded within the same training data set used in the fitting pre-process. Beyond this set, its predicted outcome becomes more of an extrapolation with a greater degree of uncertainty. For example, when speaking about DA design, if the pre-training data included a set of DAs designed up to 𝑁 𝑚𝑎𝑥 unit cells, using the model for 𝑁 > 𝑁 𝑚𝑎𝑥 has a higher risk of producing meaningless results. Therefore, making the neural network technique more of a statistical modeling technique than previously mentioned ones.

Fifth limit would be neglecting losses that become important at high frequencies and the need for loss-compensated DA topologies. Even if distributed amplification is a promising technique to push the limit of gain-bandwidth-product (GBP) [START_REF] Li | A 2 to 92 GHz distributed amplifier using 70-nm InP HEMTs[END_REF], [START_REF] El-Aassar | A DC-to-108-GHz CMOS SOI Distributed Power Amplifier and Modulator Driver Leveraging Multi-Drive Complementary Stacked Cells[END_REF], [START_REF] El-Aassar | A Cascaded Multi-Drive Stacked-SOI Distributed Power Amplifier With 23.5 dBm Peak Output Power and Over 4.5-THz GBW[END_REF], however, with conventional cascode as Gm-cell, it is difficult to achieve these potentially wideband characteristics because the resistive losses in the loaded lines are large at high frequencies. Different techniques of loss-compensation cascodes were suggested, as in [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF], [START_REF] Moez | A New Loss Compensation Technique for CMOS Distributed Amplifiers[END_REF]. This highlights the various topologies that can be adopted and the approach considered in enhancing the cascode topology, in which extra components are being added to enable the DA to reach wider BWs thereby maximizing its GBP. This undoubtedly adds a new dimension of complexity for mm-wave DA design, pushing DA designers even more towards CAD software.

The sixth and final limit, and it is specific to using graphical schematic environment of CAD tools, concerns the fact that some design variables are not allowed to be automated by their optimization algorithm and hence it relies on the designer to manually do it. For the case of DA design, semiconductor foundries provide for a given process technology a broad range of transistor sizes to explore from. Determining the optimal transistor size to use with the optimal number of Gm-cells (𝑁 𝑜𝑝𝑡 ) in order to maximize DA gain for a desired BW could be considered tricky. For instance, for CAD tools where circuit design is possible only via drawing on schematic diagram, the designer will be obligated to manually manipulate the number of unit cells for each component modification performed on the DA. Designing through CAD software schematic environment is therefore the most accurate technique available, but a time-cost consuming one indeed. It could be argued that with recent progress of CAD tools in extending the capability of their design environment, where they start to offer scripting environment possibilities such as application extension language (AEL) in Keysight ADS and OCEAN language in Cadence Virtuoso, that the design of the DA can be automated. While similar can be said when using, for instance, MathWorks MATLAB computing environment, a scripting language will not be able to achieve DA design automation without having first at-hand a proper physical model. A model that takes into account the complete set of DA variables, including and most importantly its variable 𝑁 as a free variable.

All of those limits, therefore, highlight that the success in the automated design of an IC DA depends crucially on first the appropriate choice of the device model. They emphasize on the need for proposing a new complete and reliable DA model that accommodates any suggested Gm-cell topology and that provides systematic design approaches with less dependence on CAD proprietary optimization tools. This is covered in next Section 3.4.

Proposed Solution: Chain Matrix (ABCD) Based Design Model [73]

After listing both the milestones and limitations in available distributed amplifier design techniques, in this section an original matrix-based technique is introduced. This model is based on 𝐴𝐵𝐶𝐷-parameters and it was proposed for the purpose of providing a more direct way of designing mm-wave distributed amplifiers without imposing restrictions on the designer search for optimum design solution. Compared to the previous models, we concentrate on providing a model that deals with the criteria listed in Section 3.1: Optimum performance by taking into account the complete set of design parameters the conventional DA can be made from, and versatility, complexity and reliability with focus on accurate representation of the DA mm-wave behavior. Referring to Figure 3.8, the Gm-cell can be represented symbolically by its equivalent two-port admittance network. Its self-admittance impacts on the input and output loadedlines are represented by 𝑌 𝐼𝐼 + 𝑌 𝐼𝑂 and 𝑌 𝑂𝑂 + 𝑌 𝐼𝑂 , respectively, where (𝐼) subfix refers to input of Gm-Cell and where (𝑂) subfix refers to input of Gm-Cell. Because any Gm-cell also introduces two different kinds of coupling, leakage from output to input node and amplification from its input to output node, their effect are represented here as two different admittances where 𝑌 𝐼𝑂 admittance is for the former type of coupling and 𝑌 𝑂𝐼 admittance is for the latter type. The choice for such a Gm-cell representation was made to keep the proposed unit cell model (and hence the DA model) suitable for any two-port Gm-cell topology the designer decides to use. In addition, all inductors in Figure 2.18 were replaced by a general two-port series impedance networks, depicted as 𝑍 𝑆 𝐼 and 𝑍 𝑆 𝑂 for input and output side, respectively, for the intention of obtaining a general unit cell model and for the ease it provides when interchanging DA inductive-type segments topology, as will be presented shortly.

From Figure 3.8, one can now observe that when designing a DA, one is dealing at its core with a four-port network unit cell. Because a DA is defined by cascading this fourport network 𝑁 times, an 𝐴𝐵𝐶𝐷-type matrix (3.13), adapted to a four-port representation, is therefore a suitable choice to characterize a single unit cell.

[ 𝑉 1 𝐼 1 𝑉 3 𝐼 3 ] = [ [ 𝐴
The left side of the equality sign represents the input side of the four-port unit cell and the right-most matrix represents its output side. The negative sign of both 𝐼 2 and 𝐼 4 arises to make the output current of one cascaded unit cell equal to the input current of the adjacent one. When speaking of the whole DA, illustrated in Figure 2.18, its 𝐴𝐵𝐶𝐷-matrix model is represented by (3.14); thereby, it becomes a matter of multiplying the matrix of each unit cell together in the same order the DA network is drawn, i.e., left to right.

[ 𝑉 1 𝐼 1 𝑉 3 𝐼 3 ] = ∏ [ [ 𝐴
In order to solve either equation (3.13) or (3.14), it is necessary to identify the boundary conditions at each terminal side of the four-port network. By proper application of Kirchhoff's voltage law at each port, they are found to be (3.15):

𝑉 𝑆 = 𝑍 1 𝐼 1 + 𝑉 1 0 = 𝑍 2 𝐼 2 + 𝑉 2 0 = 𝑍 3 𝐼 3 + 𝑉 3 0 = 𝑍 4 𝐼 4 + 𝑉 4 (3.15)
Here it is assumed the case where only port 1 is stimulated by a microwave signal (Figure 2.18) and all other ports are terminated by a shunted load: 𝑍 2 , 𝑍 3 and 𝑍 4 . Depending on the choice of Gm-cell topology and type of inductive-type segments used, it will be a lumped impedance or a physical TL. Both equations (3.13) and (3.14) can be used to design any DA that follows the conventional cascading topology of Figure 2.18.

By taking the case of series lumped impedance as a first approach for the inductive-type segments, with admittance representation for Gm-cell, the factorized 𝐴𝐵𝐶𝐷-matrix describing the network of Figure 3.8 is found to be the one of (3.16).

[ 𝑉 1 𝐼 1 𝑉 3 𝐼 3 ] = [ 1 𝑍 𝑆 𝐼 0 0 0 1 0 0 0 0 1 𝑍 𝑆 𝑂 0 0 0 1 ] [ 1 0 0 0 𝑌 𝐼𝐼 1 𝑌 𝐼𝑂 0 0 0 1 0 𝑌 𝑂𝐼 0 𝑌 𝑂𝑂 1 ] [ 1 𝑍 𝑆 𝐼 0 0 0 1 0 0 0 0 1 𝑍 𝑆 𝑂 0 0 0 1 ] [ 𝑉 4 -𝐼 4 𝑉 2 -𝐼 2 ]
(3.16)

By further inspecting matrix (3.16), one can note the similarity between its structure and that of Figure 3.8 from which it can be concluded that a DA unit-cell is constructed from three four-port networks cascaded together. At the right side of the equal sign, the leftmost and rightmost 4x4 matrices represent each the 𝐴𝐵𝐶𝐷-matrix of the parallel series-lumped impedances network on the left and right side of the Gm-cell, respectively, and the middle 4x4 matrix, containing the 𝑌-parameters, represents the four-port 𝐴𝐵𝐶𝐷-matrix of the Gmcell topology used. Further inspection of (3.16) also reveals the value of such a representation, both leftmost and rightmost 4x4 matrices are made from smaller submatrices that represents the 𝐴𝐵𝐶𝐷-parameters of the individual input and output segments the unit cell is made from. This demonstrates the simplicity and flexibility in using the proposed model: DA designers now only have to replace those 𝐴𝐵𝐶𝐷submatrices with any other 𝐴𝐵𝐶𝐷-submatrices representing a unit-cell input and output segments topology of their choice. For demonstration, replacing the lumped inductors used in Figure 3 ) each. This also applies for the middle Gm-cell matrix; the designer can choose any Gmcell topology he desires and apply it to the DA model since it is represented in its general form (𝑌-parameter). This is contrary to the conventional ways where they are restricted to a unilateral assumption of a single transistor Gm-cell. A demonstrative example will be provided in Chapter 4 where a method for accurately representing the frequency behavior of a cascode topology as a scalable parameter with respect to transistor size and integrating it with (3.16) (3.17)

In order to obtain the terminal behavior of the DA, the proposed 4x4 𝐴𝐵𝐶𝐷-matrix model is first converted into a 2x2 𝐴𝐵𝐶𝐷-matrix characterizing a two-port network in terms of input and output ports. In the proposed conventional DA design topology, shown in Figure 2.18, both ports 3 and 4 are terminated by matching impedances 𝑍 3 and 𝑍 4 , respectively, to absorb backward-signals and prevent reflections back to the main loaded output and input lines, respectively, as early stated in Chapter 2 (subsection 2.3.2). Interest, thus, falls on both ports 1 and 2, as input and output ports, respectively, leading to the required design matrix (3.18).

[ 𝑉 1 𝐼 1 ] = [ 𝐴 𝐵 𝐶 𝐷 ] [ 𝑉 2 -𝐼 2 ] (3.18)
Applying the previously listed boundary conditions of (3.15), the required 𝐴𝐵𝐶𝐷parameters were deduced to be the ones of (

The two-port network 𝐴𝐵𝐶𝐷-parameters is now easily convertible into any other twoport network parameters, such as impedance, admittance or power scattering matrix. For the case at hand, where characterizing the behavior of the DA at terminals 1 and 2 is desired, 𝑆-parameter conversion [START_REF] Pozar | Microwave Engineering[END_REF] is used. For ease of referencing when implementing the design methodology, they are rewritten hereafter (3.20)

Conclusion

This chapter discussed the available models in the literature and techniques used to design a DA. Each approach presented its own improvement in terms of added parameters for a more flexible design and targeting to represent the DA behavior more accurately. The most complete and accurate design technique of course being through CAD software, such as ADS or Cadence tools, in which the full technology design kit is available from the manufacturing company. In spite of those, limitations exist and were discussed in this chapter, and they can be summarized as follows. When it comes to designing DAs, the designer has one of three options: 1) Proceeding with the mathematical approaches where the designer can directly see the relation between parameters and hence determine directly the optimal set for a design goal. However, this is at the expense of being restricted towards low operating frequencies, in other words designing DA with smaller bandwidths, since assumptions and simplification through neglecting parameters are more often performed to derive them.

2) Using machine learning, such as artificial neural network, or curve fitting techniques where the designer does not have to deal with the tiny effect (plethora of parasitic) that affect the DA behavior or even how it is made, i.e., the DA will be treated as a black box. However, its output prediction during the design process relies on a large set of pre-designed DAs used in the function fitting (pretraining) process and, also, its optimum performance relies on how adequately they were designed, as already described in Section 3.3 (fourth limit).

3) Relying on CAD tool, either on its schematic diagram environment or scripting environment. For the former case, some parameters such as 𝑁 are not readily accessible to optimize and consequently the design process becomes a manual and iterative process that relies on intuition. It is also a tedious one if elements to enhance the DA response are being considered to be modified each time because this pushes the designer to redo the performance investigation manually over and over again from scratch, i.e., starting from 𝑁 = 1, per element modification. Furthermore, when the goal changes for the same topology, even with the experience from the previous design, relatively large simulation works are still not avoidable. For the latter case of exploiting CAD scripting capability, if available by the CAD tool, while it could become possible in this scenario to automate and hence made easier. But, first and most importantly is having at disposal a proper physical model: a (simple) model that considers the entire set of design parameters (complete), gives flexibility in choosing DA components topologies (versatile) and accurate in the simulation outcome it provides the designer (reliable).

As a proposed solution, a novel matrix-based model was proposed for both unit cell and DA based on Chain (𝐴𝐵𝐶𝐷) parameters. No approximation was performed since both the µ-TL-type segments and Gm-cell were represented by their complete 𝐴𝐵𝐶𝐷 parameters. It also presents versatility where the model was provided with no assumption of any kind on neither the topology of Gm-cell nor segments used. This is contrary to what is done in the conventional approaches where a simple unilateral AC-equivalent model was always assumed for the transistor. The latter is considered to be not the case in practice since the designer could be interested in adopting other Gm-cell topologies, such as a cascode Gmcell as was concluded in Chapter 2 (subsection 2.3.3).

In the next chapter, the potential of this model is presented through a scripting a CAutoD methodology example where it is used to explore the different possible CMOS DAs the 55-nm ST technology can provide.

Chapter 4

Model Application -Computer Automated Design for Loss-Compensated Distributed Amplifier

In the last chapter, a four-port matrix-based model using 𝐴𝐵𝐶𝐷-parameters was proposed for DA design. It was considered to be complete since no assumption was made, and versatile since no limitations was imposed on it, neither on the topology of Gm-cell nor on the µ-TL segments. In this chapter, the proposed model is used to explore different CMOS-based DA solutions the 55-nm ST technology could produce. This chapter is structured as follows. Section 4.1 starts by introducing the concept of loss-compensated DA. A topology proposed in the nineties [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] and still commonly used for its simplicity in reducing the high-losses issue in millimeter frequencies and expanding the passband. Based on it and with the use of the proposed DA model (Eq. 3.17), Section 4.2 suggests a systematic algorithmic methodology for realizing a CAutoD process that maximizes the DA bandwidth for a given passband-gain-ripple specification. Section 4.3 discusses this process outcome where a set of 3D DSE plots are obtained that enable one to examine the tradeoffs between gain, bandwidth and power consumption, and the size and number of Gm-cells, and arrive at the optimum desired design. Finally, Section 4.4 summarizes and concludes this chapter.

Loss-Compensated Distributed Amplifier

While the conventional DA is capable of providing us wideband amplification through wideband matching, by dealing with the input-and output-parasitic capacitance of the Gmcell through connecting inductive-type segments, as already analytically analyzed in Chapter 2 (Section 2.3); however, resistive-type losses remain unmanageable by it and become important at high frequencies that they can no longer be neglected. Those latter losses impact on the gain become more evident at mm-wave frequency that they influence the flatness of the DA passband.

Loss-compensated DA topologies are thus proposed, and even a necessity, when it comes to mm-wave application. Loss-compensation is achieved by adding extra components to the DA device, such as inductors [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] or extra transistors [START_REF] Moez | A New Loss Compensation Technique for CMOS Distributed Amplifiers[END_REF], which provides the designer with additional tuning knobs to control the resistive-type losses of the DA. In this work, interest was set on [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] for their interesting idea of making use of the already implemented unit cell Gm-cell contrary to [START_REF] Moez | A New Loss Compensation Technique for CMOS Distributed Amplifiers[END_REF] which requires to distribute additional 𝑁 transistors along each loaded-lines of the DA.

A graphical study of [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] technique influence on both input-and output-loaded lines is carried out first in subsection 4.1.2. Then, an analytical analysis is provided in subsection 4.13. Finally, in subsection 4.1.4, a method for modeling the loss-compensated cascode Gm-cell topology and implementing it in a numerical computing environment, such as MathWorks MATLAB, is demonstrated.

Overview of Publication

The idea of a loss-compensated DA dates back to year 1996. It was first proposed by [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] as a technique to mitigate losses for both the gate and drain loaded-lines. Indeed, from (2.4) and (2.5), the gate-line attenuation constant (𝛼 𝑔 ) and drain-line attenuation constant (𝛼 𝑑 ) are dominated by the Gm-cell input and output resistance, 𝑅 𝑖 and 𝑅 𝑑𝑠 , respectively, as well as microstrip segments resistive part, represented by 𝛿𝑅 𝑔 and 𝛿𝑅 𝑑 , respectively. The proposed technique comes as an improvement for the conventional cascode device, in which two additional inductors, 𝐿 𝑔 and 𝐿 𝑑𝑠 , are added, as illustrated in Figure 4.1. The new loss-compensation circuit improves the high frequency performance of the amplifier device and, when speaking of the whole DA, it makes the gain-bandwidth product larger than that of conventional ones.

Loss-Compensation Technique: Graphical Analysis

Due to the increasing losses on both gate and drain lines with increase of frequency, the DA does not experience a flat gain response inside its passband. This is demonstrated in Figure 4.4, where attenuation constants 𝛼 𝑔 and 𝛼 𝑑 are plotted. For relevant insight, the losses plotted here represent the ones of the 100-GHz DA designed in Chapter 5 which is synthesized using the conventional two-transistor cascode for Gm-cell topology without the compensation inductors 𝐿 𝑔 and 𝐿 𝑑𝑠 . One can note that the total losses (𝛼 𝑡𝑜𝑡𝑎𝑙 = 𝛼 𝑔 + 𝛼 𝑑 ) at 100 GHz is about 14-fold higher than the total losses at the lower end of the spectrum. This emphasizes that when speaking about the overall gain behavior with respect to frequency, the upper-end of the conventional (non-compensated) DA passband tends to be lower than the lower-end of its passband. To comprehend the impact of the compensation inductors, 𝐿 𝑔 and 𝐿 𝑑𝑠 , on both attenuation constants 𝛼 𝑔 and 𝛼 𝑑 , they are first studied here visually by increasing each independently and plotting the latter constants behaviors with respect to frequency. Referring to Figure 4.5, the inductor 𝐿 𝑔 has a noticeable influence on the mm-wave frequencies above 60 GHz with a dominant role on the attenuation constant 𝛼 𝑑 . As 𝐿 𝑔 increases, the losses on both the gate and drain loaded-lines decrease up to a certain frequency limit as attenuation constants above this limit begin to experience a rapid increase. Thereby, one can deduce that an excessive 𝐿 𝑔 value can reduce the cut-off frequency of both lines. For the attenuation constant 𝛼 𝑑 , inductor 𝐿 𝑔 is also observed to cause negative value if excessively increased. The reason for this will be demonstrated in the upcoming subsection 4.1.3, which deals with the analytical side of this analysis. Nonetheless, as a short explanation here, this is the result behind [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] proposed idea where they regulate the real part of the cascode Gm-cell output impedance through introducing a tunable negative term in it. Doing so provides the designer with the ability to have control over the magnitude of the DA attenuation constant with respect to frequency. A negative attenuation constant, thereby, represents an over-compensation of the overall losses. However, deliberately compensating losses more than what is needed to be removed while one end-objective is to maintain a flat gain across a given BW is usually something not performed when designing wideband devices. In other words, one would not remove resistive losses excessively more than would be required to be removed at a given frequency with respect to another, if by the end the intention is to have a proper flat-wideband response for the amplifier device-under-test. This will be our case here, for instance, where the DA will be designed in a way that the magnitude of the DA total losses at high frequency will be made on the same level as the losses at low frequencies, and not over-compensated, in order to have a proper flat passband response. This will be made clearer when discussing Figure 4.7 next and will be further elaborated on when speaking of the loss-compensated DA design concept in Section 4.2. From Figure 4.6, inductor 𝐿 𝑑𝑠 allows the reduction of the losses on the gate loaded line. It is also observed to have an impact on its cut-off frequency where 𝛼 𝑔 is decreasing up to a certain frequency limit and above this limit the loss starts to increase again rapidly. Thereby, one can deduce that an excessive 𝐿 𝑑𝑠 value can reduce the cut-off frequency of the gate line. For the drain line, inductor 𝐿 𝑑𝑠 is observed to have relatively weak influence on 𝛼 𝑑 compared to what was observed in the other plots. When combing both compensation inductors, the overall losses (𝛼 𝑡𝑜𝑡𝑎𝑙 ) needs to be adjusted such that the losses at the (targeted) upper-end of the passband is on the same level as the losses on its lower-end, as illustrated in Figure 4.7. This will result in the DA experiencing a relatively flat wide amplification passband. It is being considered as relatively flat since at the midband around 50 GHz, peak loss is observed to occur. This will translate into a drop of gain in the middle of the DA passband. Increasing either 𝐿 𝑔 or 𝐿 𝑑𝑠 to flatten it even more would be difficult, since, as discussed previously, they have an influence on the cut-off frequency of both gate and drain line, i.e., increasing 𝐿 𝑔 or 𝐿 𝑑𝑠 excessively will lead to shrinkage of the DA bandwidth. On that basis, one can conclude that by using this loss-compensation topology a trade-off exists between the bandwidth and midband gain-drop level, in other words gain-ripple. It is up to the designer to choose between either having a DA that demonstrates wide bandwidth but with a notable midband gain-drop or having a DA with a flat response but at the expense of a smaller bandwidth. In this work, for instance, flatness was given priority when designing single stage DAs where its midband was restricted within 1 dB of gain-drop. A common passband characteristic adopted by similar work when referring to the single stage-stage DAs mentioned in the state-of-the-art Table 2.2 (Chapter 2). .

Loss-Compensation Technique: Analytical Analysis

Previously, the impact of loss-compensation inductors is investigated graphically. Here, mathematically speaking, inductors 𝐿 𝑔 and 𝐿 𝑑𝑠 are found to compensate the losses through resonance with the intrinsic capacitance of the cascode cell: Inductor 𝐿 𝑔 with the gate-tosource capacitance (𝐶 𝑔𝑠2 ) coming from transistor M2 and inductor 𝐿 𝑑𝑠 with the drain-tosource capacitance (𝐶 𝑑𝑠1 ) coming from transistor M1. The following are proven as follows. 4.3c), respectively, the real part of the output impedance of the cascode, seen by the drain loaded-line, is deduced to be (4.3d).

𝑅𝑒(𝑍

𝑑𝑠2 ) = 𝑅𝑒 ( 𝑅 𝑑𝑠2 1 + 𝑗𝜔𝑅 𝑑𝑠2 𝐶 𝑑𝑠2 ) = 𝑅 𝑑𝑠2 1 + 𝜔 2 𝑅 𝑑𝑠2 2 𝐶 𝑑𝑠2 2 (4.3a) 𝑅𝑒(𝑍 𝑔𝑠2 ) = 𝑅𝑒 (𝑅 𝑔𝑠2 - 𝑗 𝜔𝐶 𝑔𝑠2 ) = 𝑅 𝑔𝑠2 (4.3b) 𝑅𝑒 (-𝑗 𝑍 𝑑𝑠2 • 𝑔𝑚 2 𝜔𝐶 𝑔𝑠2 ) = - 𝑔𝑚 2 • 𝑅 𝑑𝑠2 2 • 𝐶 𝑑𝑠2 𝐶 𝑔𝑠2 (1 + 𝜔 2 𝑅 𝑑𝑠2 2 𝐶 𝑑𝑠2 2 ) (4.3c) 𝑅𝑒(𝑍 𝑜𝑢𝑡 ) = 𝑅 𝑔𝑠2 + 𝑅 𝑑𝑠2 1 + 𝜔 2 𝑅 𝑑𝑠2 2 𝐶 𝑑𝑠2 2 (1 - 𝑔𝑚 2 • 𝐶 𝑑𝑠2 • 𝑅 𝑑𝑠2 𝐶 𝑔𝑠2 ) (4.3d)
Indeed, from (4.3d) one can note that by using just the simple conventional cascode Gmcell the resistive losses cannot be reduced as they only depend on the intrinsic parameters of the cascode. It is also clear that the second term between parenthesis ((𝑔𝑚 2 • 𝐶 𝑑𝑠2 • 𝑅 𝑑𝑠2 ) 𝐶 𝑔𝑠2 ⁄ ) operates as a negative term and contributes in decreasing the real part of the output impedance that causes the loss on the drain line. However, circuit designers cannot control this negative term effect freely because it depends solely on the parameters of the transistors which can have unfavorable degradation on the overall gain of the DA. That is why external components are proposed by [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] to be added, in this case extra inductors 𝐿 𝑔 and 𝐿 𝑑𝑠 , in order to have more flexible control over Re(𝑍 𝑜𝑢𝑡 ) with significant change on its value, as demonstrated hereafter. Referring to Figure 4.9, 𝐿 𝑔 and 𝐿 𝑑𝑠 are added to see how they influence the behavior of 𝑅𝑒(𝑍 𝑜𝑢𝑡 ). The former inductor is considered through its impedance 𝑍 𝐿 𝑔 = 𝑗𝜔𝐿 𝑔 in series with 𝑍 𝑔𝑠2 = 𝑅 𝑔𝑠2 + 1 𝑗𝜔𝐶 𝑔𝑠2 ⁄ and the latter inductor is considered through its impedance 𝑍 𝐿 𝑑𝑠 = 𝑗𝜔𝐿 𝑑𝑠 in series with 𝑍 𝑑𝑠1 (𝐶 𝑑𝑠1 in parallel with 𝑅 𝑑𝑠1 ). This results in (

The analysis demonstrated up to now, while insightful for explaining how the compensation inductors influence the losses on gate and drain loaded-lines, it is considered approximate and not fully suited for practical usage when designing in the mm-wave spectrum. Adding more elements for more accurate depiction will cause the information to be lost, since more parasitic will be intertwined, and will result in a more complicated design process since each parasitic needs to be extracted for different transistor sizes. For that reason, the next subsection deals with the modeling aspect of loss-compensated cascode by introducing a simple matrix-based method for implementing the complete Gmcell topology on a coding software such as MathWorks MATLAB.

Implementing Loss-Compensated Cascode Gm-Cell in a Numerical Computing Environment

Compared to conventional ways of using AC equivalent circuit to derive parametric expressions to replicate the cascode Gm-cell frequency behavior for use in circuit design, the method presented hereafter treats the adopted loss-compensated cascode as a matrixbased model. This method is considered an important step since in either DA model (3.14) or (3.17), the Gm-cell is represented in its general form through the middle 𝐴𝐵𝐶𝐷-matrix. In addition, this method will allow the inductors to be implemented as tuning knobs, a necessary step if full computer automation is needed. Since no approximation for simplification purposes is carried out, this method benefits from the complete and accurate representation of cascode behavior, hence of DA behavior. It also benefits from ease of scalability where a collection of matrices can be extracted for several transistor sizes and then depending on the desired cascode size the corresponding transistors matrices are used. This implementation method is illustrated in Figure 4.10 as a flow diagram. When the designer has biased his cascode cell to the desired operating point, a collection of both CS and CG transistor 𝑆-parameter matrices are extracted first for the envisaged sizes and frequency range during DA design process. Since CS transistor in standalone has its gate pin as input port, drain pin as output port and source pin grounded, its corresponding 𝑆parameters will be a two-port matrix extraction. Since CG transistor in standalone has its source pin as input port, drain pin as output port and gate pin as a third port eventually connected to a shunt inductor 𝐿 𝑔 , its corresponding 𝑆-parameters will be a three-port matrix extraction.

Next step involves converting CG transistor three port 𝑆-matrix into a two-port matrix form. This can be done by using (4.6a), where Г represents the reflection coefficient between the added inductor 𝐿 𝑔 and the reference characteristic impedance (𝑍 0 ) the CG three-port 𝑆-parameters was extracted with (4.6b). In case µ-TL topology is used to implement inductor 𝐿 𝑔 , (4.6c) is a suitable option where 𝑍 C , 𝛾 𝑇𝐿 𝐿𝑔 and 𝑙 𝑇𝐿 𝐿𝑔 are the characteristic impedance, propagation constant and length of this inductor. Afterwards, both CS and CG two-port 𝑆-parameters matrices are converted into an 𝐴𝐵𝐶𝐷-matrix format using the conversion provided by [START_REF] Razavi | A 60GHz direct-conversion CMOS receiver[END_REF] and multiplied with 𝐴𝐵𝐶𝐷matrix of the series inductor 𝐿 𝑑𝑠 , as shown in (4.7a). In case µ-TL topology is used to implement inductor 𝐿 𝑑𝑠 , (4.7b) is a suitable option where 𝑍 C , 𝛾 𝑇𝐿 𝐿𝑑𝑠 and 𝑙 𝑇𝐿 𝐿𝑑𝑠 are the characteristic impedance, propagation constant and length of this µ-TL (𝑇𝐿 𝐿𝑑𝑠 ).

𝑆 𝑖𝑗 ′ = 𝑆 𝑖𝑗 + 𝑆 𝑖3 𝑆 𝑖3 Г 1 -
[ Finally, the obtained two-port 𝐴𝐵𝐶𝐷-matrix describing the proposed Gm-cell amplifier is converted to a two-port 𝑌-matrix from using [START_REF] Pozar | Microwave Engineering[END_REF] and now can be joined with proposed DA 𝐴𝐵𝐶𝐷-models, (3.14) or (3.17), by filling up their middle 𝐴𝐵𝐶𝐷-matrix with the adequate 𝑌 𝑖𝑗 parameters. Due to no simplification performed on the transistors and the possibility to represent the complete cascode Gm-cell through (4.7b), DA designers can now benefit from high reliability in accurate behavior representation, one of the desired criterion highlighted in Chapter 3 (Section 3.1). In addition, designers can benefit by using to proposed design methodologies that produce accurate DA sizing outcome, as will be presented later on when speaking of our own algorithmic DA design methodology.

Loss-Compensated Distributed Amplifier CAutoD Process

Before discussing the offered loss-compensated DA algorithmic design methodology, the design concept of the loss-compensated cascode Gm-cell [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF] adopted as a technique that can be used in extending the DA bandwidth while providing control over its mid-band flatness is first examined. Using the proposed cascode 𝑌-matrix based model, (4.7a) or (4.7b), in conjunction with the DA 𝐴𝐵𝐶𝐷-model (3.14), the influence of inductors 𝐿 𝑔 and 𝐿 𝑑𝑠 on DA 𝑆 21 response is first investigated.

Distributed Amplifier Bandwidth Extension and Flattening Concept

The DA under study is the one implemented and measured in Chapter 5, whose design parameters were obtained from the design methodology of the upcoming subsection 4.2.2. Those parameters are only summarized here as follows. The DA consists of five unit cells (𝑁 = 5), where the unit cell is modeled using (3.17) and its inductive-type segments are implemented as µ-TLs using the thickest copper metal available in the BEOL of ST 55-nm used process with 131 µm in length. The middle 𝐴𝐵𝐶𝐷-matrix of (3.17) is filled up with the 𝑌-parameters of the two-port admittance of the loss-compensated cascode consisting made from 31-µm CS nMOS, M1, and 62-µm CG nMOS, M2, biased at a current density of 0.16 mA per CS micrometer width (0.16 mA/µm). During this concept analysis, both 𝐿 𝑔 and 𝐿 𝑑𝑠 were left as ideal components, (4.6b) and (4.7a), and used as tuning knobs. The DA is intended to cover a bandwidth of 100 GHz. Referring to Figure 4.11, for the given 𝑁 and cascode size, the DA gain is determined by its gain level at lower of spectrum -here, it is 7.1 dB. When 𝐿 𝑔 and 𝐿 𝑑𝑠 are set to zero, one can observe the gradual decrease in gain with respect to frequency. The cause of this is related to the high losses both physical µ-TLs and cascode Gm-cell itself experience at mm-wave frequencies, as illustrated in Figure 4.4. By shorting 𝐿 𝑑𝑠 , i.e., 𝐿 𝑑𝑠 = 0 pH, increasing 𝐿 𝑔 rises gain at a certain high frequency component. Indeed, inductor 𝐿 𝑔 is extending the DA BW, enabling it to reach higher frequencies-in this case 100 GHz-by compensating for losses at those frequencies, as demonstrated in Regardless of the achievable extension, however, Figure 4.11 highlights an undesirable behavior between lower and upper passband limits: the mid-band exhibits a gradual gain roll-off. This is due to 𝐿 𝑔 being a loss-compensating technique with a major impact on the magnitude of the attenuation constant 𝛼 𝑔 at frequencies above 60 GHz, as was deduced from Figure 4.5, and insignificant impact on the lower spectrum. To solve this issue causing midband gain drop, the addition of 𝐿 𝑑𝑠 is required. By maintaining 𝐿 𝑔 at the value that peaks DA gain at the higher-end of the spectrum to the same level of gain as the lower-end of the spectrum, in this case 40 pH, increasing 𝐿 𝑑𝑠 leads to lifting the mid-band gain drop, as illustrated in Figure 4.12-here, it is desired to have 1-dB mid-band gain drop. Therefore, to summarize up to now, one can conclude the following: Inductor 𝐿 𝑔 mainly influences upper-end peaking while inductor 𝐿 𝑑𝑠 plays its main role on mid-band, but unfortunately not exclusively. 4.12 also highlights an undesirable behavior: increasing 𝐿 𝑑𝑠 has an influence on the level of peaking produced from 𝐿 𝑔 where it increases it even further and on the position of its gain-peaking frequency where it shifts it towards lower spectrum. To fix it, 𝐿 𝑔 and 𝐿 𝑑𝑠 must simultaneously be decreased and increased, respectively, to maintain the desired midband drop (1-dB) while conserving the acquired high frequency component (100 GHz), as demonstrated in Figure 4.13. Indeed, it is observed that through the usage of 𝐿 𝑔 and 𝐿 𝑑𝑠 , one can extend the BW while flattening the passband gain-ripple

Algorithmic Design Methodology

A step-by-step algorithmic DA design methodology is proposed based on the design concept discussed previously. This methodology uses both DA 𝐴𝐵𝐶𝐷-model (3.14) with the unit cell model (3.17), where the physical μ-TL topology is used for the inductive-type segments, and the presented loss-compensated cascode Gm-cell with its matrix implementation method presented in subsection 4.1.4. For the latter, its inductors 𝐿 𝑔 and 𝐿 𝑑𝑠 are implemented as physical μ-TL and thereby (4.6c) and (4.7b), respectively, will be used during the design process.

The purpose of this methodology is to explore all loss-compensated DAs a given technology process can provide at a given biasing point, by maximizing bandwidth for various combinations of transistor widths and number of unit cells while satisfying a specified passband flatness. It is therefore noted that the initiating point for such method is the designer's choice of bias point beforehand, what follows will be automated and the end outcome will be 3D DSE plots to pick DA solutions from.

The design methodology is summarized as a flowchart in Figure 4.14 and its systematic steps are presented hereafter. The DSE plots outcome of this methodology are discussed in the next Section 4.3. Since 55-nm ST process node is used at the end for fabrication, its process design kit (PDK) is used throughout the design steps for illustration. For the numerical computing environment, in our case MathWorks MATLAB software is used. It should be noted that technology components, such as μ-TL and transistors, were first simulated on Keysight ADS software, since PDK is available on it by semiconductor foundry and, as a second step, their 𝑆-parameters were exported into MATLAB to perform the required conversions and matrix manipulations. Step 1) Extract the 𝑆-parameters for a range of PDK μ-TL lengths at a given thickness and width. They will be used to model the unit-cell segments as well as 𝑇𝐿 𝐿𝑔 (4.6c) and 𝑇𝐿 𝐿𝑑𝑠 (4.7b). Choosing the thickest μ-TL in technology BEOL offers the lowest losses versus frequency, since it will have the lowest sheet resistance, and hence aids DA gain response. For eight-metal version of 55-nm CMOS process, it is the ultra-thick metal M8. For what concerns the width, in this metal layer, the minimum width allowed is 0.6 µm, but to comply with the DC-current handling limits expressed on the Design Rule Manual (DRM), we decided to adopt a width of 1 µm. We also decided to apply the same 1 µm width for all µ-TLs with the aim of having later on a simpler design implementation process where all the lines will share the same width. After that, the two-port 𝑆-parameters are extracted for length ranging from 10 µm up to 400 µm from ADS. Since chain (𝐴𝐵𝐶𝐷) model is used for both unit-cell and cascode models, the μ-TL characteristic impedance (𝑍 𝐶 ) and propagation constant (𝛾) can be obtained using (4.8) when needed, where conversion between two-port 𝑆-parameters to 𝐴𝐵𝐶𝐷-parameters is done on MATLAB.

𝑍 𝐶 = √ 𝐴 • 𝐵 𝐶 • 𝐷 (4.8a) 𝛾 = 1 𝑙 𝑐𝑜𝑠ℎ -1 ( 𝐴 + 𝐷 2 ) √ 𝐴 • 𝐵 𝐶 • 𝐷 (4.8b)
Step 2) At a desired drain current per unit gate width (𝐼 𝑑 (𝐴 𝑤𝑖𝑑𝑡ℎ ⁄ )), extract the 𝑆parameter matrices of both nMOS CS and CG FETs separately for a range of different channel widths, as explained in Figure 4.10, in order to link the loss-compensated cascode as a two-port 𝑌-matrix with the DA model (3.17). Here, the CG FET, M2, channel width is set to be twice the size of the CS FET, M1, in order to have similar magnitude for the cascode Gm-cell input and output capacitive-type reactance. From that, the unit-cell μ-TL segments can be set equal in length, i.e., 𝑙 𝑆 𝐼 2 ⁄ = 𝑙 𝑆 𝐼 2 ⁄ = 𝑙 2 ⁄ , inside (3.17) which will aid us later in having a simpler layout implementation process. Those two design choices were taken in order to equate the loaded input-and output-lines phase delays; a necessity for producing constructive interference on the output line, as was discussed in the basic operation section of a DA in Chapter 2.

In this thesis, the cascode bias was desired to be biased at 0.16 mA per CS micrometer width (0.16 mA/𝜇m) at 𝑉 𝐷𝐷 =1.2 V (nominal value of technology). While this choice of current density does not represent the full capability of ST 55-nm CMOS (𝑓 𝑡 = 160 GHz 𝑓 𝑚𝑎𝑥 = 246 GHz ⁄ at 𝐼 𝑑 (𝐴 𝑤𝑖𝑑𝑡ℎ ⁄ ) = 0.22 mA µm ⁄ ): our choice of current density is to nearly maximize 𝑔 𝑚 while being consumption-efficient since our end goal is concerned about a metric of GBP over 𝑃 𝐷𝐶 . On that basis and as a first step, the CS and CG FETs were inserted as separate standalone devices on ADS schematics from the technology PDK library and their drain current per unit gate width was set to our 0.16 mA/𝜇m choice. As a second step, a sweep for a desired range of widths is performed; in this work, their width was varied for a range of 14 𝜇m≤ 𝑊 𝐶𝑆 ≤ 40 𝜇m and, hence, 28 𝜇m≤ 𝑊 𝐶𝐺 ≤ 80 𝜇m, and their respective 𝑆-parameters were extracted. It should be reminded that for the CS FET it will be a two-port matrix extraction and for the CG FET it will be a three-port matrix extraction, as already described in Figure 4.10. Wider widths are possible, but were disregarded in being mentioned in this discussion. This is because during the time of proposal and testing of this methodology, 𝑊 𝐶𝑆 > 40 𝜇m were observed to offer DAs with BWs ≤ 80 GHz, as will be proven in Section 4.3 (Figure 4.16); thereby, of no interest for us to highlight them here and in the remaining of this manuscript. In addition, DAs with 𝑊 𝐶𝑆 < 14 𝜇m required 𝑇𝐿 𝐿𝑑𝑠 μ-TLs with lengths above our set design limit (400 𝜇m) extracted in Step 1) and hence did not converge, and, for us, were disregarded since they are solutions with excessively large on-wafer areas. After this step, the DA model (3.17) is now ready with its tunable μ-TLs lengths (unit-cells segments, 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 ), transistors width and 𝑁 knobs to perform automated design for a defined matching and passband flatness levels.

Step 3) By fixing the number of unit cells of DA to one in (3.14), i.e. 𝑁 = 1, iterate through each 𝑊 𝐶𝑆 and increase the μ-TL segments length (𝑙 2 ⁄ ) until the input-and outputports reflection coefficient bandwidth stops expanding at a defined targeted maximum level. In (3.20), 𝑍 0 is set to 50 Ω that represents the impedance of both RF probes for the measurement setup. In our case, the maximum acceptable mismatch level defined for a single unit cell input and output ports is set at 𝑆 11𝑚𝑎𝑥 = 𝑆 22𝑚𝑎𝑥 = -10 dB. The scripted methodology at each transistor width is set to increase 𝑙 2 ⁄ until the far-end frequency of 𝑆 11 and 𝑆 22 bandwidth where mismatch level is at -10 dB stops expanding.

Step 4) For a given value of 𝑊 𝐶𝑆 , iterate through 𝑁 and for each combination of (𝑊 𝐶𝑆 , 𝑁) detect the length of 𝑇𝐿 𝐿𝑔 that increases gain at the rightmost side of the frequency spectrum to attain same level of gain of that at the lower-end of the DA passband. The lower-end passband frequency is usually determined by the AC-grounded capacitor used in series with termination resistors 𝑅 3 and 𝑅 4 when implementing the loaded-lines termination loads 𝑍 3 and 𝑍 4 . Both 𝑅 3 and 𝑅 4 were set as ideal 50-Ω resistors since it is desired here to design DAs at 𝑍 0 = 50 Ω, as stated in Step 3. As a first approach during the design process and before starting the layouting process of making the choice of AC-ground topology to synthesis, the capacitors were considered here as a perfect GND connection (i.e. 𝑍 3 = 𝑅 3 and 𝑍 4 = 𝑅 4 ). This is observed to provide equal gain over all frequencies ≤ 10 GHz and with a flat shape, as visible from Figure 4.11. Since it is commonly known that moving higher in frequency benefits IC designers from implementing components of reduced onchip area, we decided to go with 10 GHz as the lower-corner frequency (𝐹 𝑙𝑜𝑤𝑒𝑟 ) of the DA passband. The latter choice will benefit us later on during layout implementation with synthesizing small AC-grounded capacitor for 𝑅 3 and 𝑅 4 compared to if 𝐹 𝑙𝑜𝑤𝑒𝑟 of 1 GHz was to be picked, for instance. Accordingly, for a given (𝑊 𝐶𝑆 , 𝑁), the µ-TL 𝑇𝐿 𝐿𝑔 length is increased until a certain high frequency component gain becomes on the same gain level as at 10 GHz (see Figure 4.11). The frequency at which this peaking first occurs is considered the DA upper-corner frequency (𝐹 𝑢𝑝𝑝𝑒𝑟 ).

Step 5) For a given value of 𝑊 𝐶𝑆 , iterate through 𝑁 and for each combination of (𝑊 𝐶𝑆 , 𝑁) detect the length of 𝑇𝐿 𝐿𝑑𝑠 in order to flatten passband for a desired mid-band gain drop. In this manuscript, the desired mid-band gain drop variable was assigned to a value of 1 dB and the mid-band frequency is determined by (𝐹 𝑢𝑝𝑝𝑒𝑟 + 𝐹 𝑙𝑜𝑤𝑒𝑟 ) 2 ⁄ ; accordingly, for a given 𝑊 𝐶𝑆 and 𝑁, the length of 𝑇𝐿 𝐿𝑑𝑠 is increased until the gain at mid-band is made 1 dB less than gain at 𝐹 𝑙𝑜𝑤𝑒𝑟 (see Figure 4.12). As mentioned in subsection 4.2.1, 𝑇𝐿 𝐿𝑑𝑠 has an influence on gain peaking established by 𝑇𝐿 𝐿𝑔 and vice-versa. The proposed way to counteract it is just to script the algorithm to reduce 𝑇𝐿 𝐿𝑔 in order to maintain gain at 𝐹 𝑢𝑝𝑝𝑒𝑟 on the same level as gain at 𝐹 𝑙𝑜𝑤𝑒𝑟 while increasing 𝑇𝐿 𝐿𝑑𝑠 to maintain mid-band gain drop limited to 1 dB with respect to gain at 𝐹 𝑙𝑜𝑤𝑒𝑟 (see Figure 4.13).

Step 6) Repeat Steps 4) to 5) for all combinations of 𝑊 𝐶𝑆 extracted in Step 2) with the desired range of unit cells. In this manuscript, we extracted 27 transistor widths (14 𝜇m≤ 𝑊 𝐶𝑆 ≤ 40 𝜇m) and explored DA configurations made of 2 ≤ 𝑁 ≤ 9. For 𝑁 > 9, BWs ≤ 80 GHz were obtained and hence were disregarded. This results in the automated DA design program in producing 216 feasible loss-compensated DAs solutions.

Step 7) Final step includes evaluating for each design option, in this case 216 solutions, its power consumption (𝑃 𝐷𝐶 ). This can be accounted for by using (4.9) where 𝐼 𝑑 (𝐴 𝑤𝑖𝑑𝑡ℎ ⁄ ) = 0.16 𝑚𝐴 µ𝑚 ⁄ at 𝑉 𝐷𝐷 = 1.2 𝑉 (defined in Step 2).

𝑃 𝐷𝐶 ≅ 𝑁 • 𝑉 𝐷𝐷 • 𝐼 𝑑 • 𝑊 𝐶𝑆 (4.9)

3D Design Space Exploration Plots: Parameters and Variables

When successfully implementing the proposed design methodology, the DA designer will end up with an outcome of six DSE plots. Each 3D plot illustrates a given characteristic against transistor size on x-axis and number of unit cells (𝑁) on the y-axis. This is in agreement with is in agreement with (2.11) where the gain expression is proportional to transconductance term (𝑔 𝑚 ). The transconductance parameter is defined by the transistor width. Having larger width equates to having higher 𝑔 𝑚 , hence higher gain. This plot also is in agreement with (2.12) where DA gain is clearly defined with the number of unit cells.

Thereby, one can conclude that the small transconductance provided by narrow transistor can be compensated by adding more unit cells to achieve higher gain and this is also equivalent to realizing a DA with big transistors and fewer number of unit cells. It highlights that for each 𝑁 there is a maximum BW attainable that is wider for smaller 𝑊 𝐶𝑆 sizes; however, until a certain limit where even smaller sizes lead to smaller BWs. This could be explained by the inability of smaller transistors from providing enough gain to compensate for important losses at high mm-wave regions. Therefore, this pushed both 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 to be increased even more to elevate the gain at 𝐹 𝑢𝑝𝑝𝑒𝑟 towards the same level of gain at 𝐹 𝑙𝑜𝑤𝑒𝑟 while maintaining the 1-dB mid-band gain drop constraint. As already discussed in Section 4.1 (subsection 4.1.2), this leads to shrinkage of BW where excessive increase of either compensation inductors leads to shift of loaded-lines cut-off frequencies towards lower frequencies.

Decreasing 𝑁 while also decreasing 𝑊 𝐶𝑆 can permit operation at wider BWs but at the expense of lower gain, as shown by Figure 4.15. Therefore, the first parameter to choose from would be the bandwidth required for the DA to cover and, then, as a second step, to choose the desired gain level from the available options obtained for that specific bandwidth. .17 illustrates the variation of DA power consumption against 𝑊 𝐶𝑆 and 𝑁. It shows that a DA constituting of more Gm-cells, i.e., larger 𝑁, leads to higher 𝑃 𝐷𝐶 . The same applies for having a DA made from larger transistors. The highest consumption, hence, would be the design in which the DA is synthesized with both big transistors and large 𝑁 at the same time. One reason for this design point could be for delivering larger gain. For instance, from Figure 4.17, choosing a DA made from 𝑁 = 9 with 𝑊 𝐶𝑆 = 40 µm leads to 70 mW of power consumption but with a high gain close to 12 dB; however, from Figure 4.16, this choice would restrict the design to a passband of only 80 GHz.

As a conclusion, from those three figures, one can conclude that a compromise between those three parameters (gain, bandwidth and 𝑃 𝐷𝐶 ) exists and the choice would depend on the designer application orientation. Having an amplifier that delivers high gain will equates to having a smaller bandwidth and higher 𝑃 𝐷𝐶 and vice-versa. In this work, major interest is laid on the bandwidth as a first choice. This will be further elaborated on in Chapter 5 where a 100-GHz BW DA is needed for on-wafer characterization, and then, as a second step, the choice was made to have high gain with low 𝑃 𝐷𝐶 .

DA Design Parameters: Synthesizing a Unit-cell

In this section, the design parameters needed to obtain the performance characteristics covered previously are presented. The loss-compensated unit cell in discussion is synthesized from µ-TL segments and a cascode Gm-cell with loss compensation inductors implemented as µ-TL (𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 ). Its electrical schematic is presented in For the compensation inductors 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 , referring to Figure 4.20, one can note that larger inductances are needed for DAs built using either smaller transistor sizes or larger number of unit cells. This is due to the small transistor incapability in providing sufficient gain, in other words transconductance, to mitigate the losses at high frequency. This becomes even more drastic when N increases, since total losses of gate and drain are defined by 𝑁(𝛼 𝑔 𝑙 𝑔 ) and 𝑁(𝛼 𝑑 𝑙 𝑑 ), as shown in (2.11).

Conclusion

This chapter started by introducing the idea of loss-compensation for DAs where it showed to be a promising topology for extending and flattening the passband response. The necessary graphical and mathematical analysis of its function was provided. It was shown to influence the passband response through regulating both the input (gate) and output (drain) loaded-line losses (Figure 4.7). In addition, a technique for modeling this cascode device in a matrix-form and use it in MATLAB was demonstrated that enables a complete representation of the cascode device (Figure 4.10) and designing one through scripting.

Based on this concept and using the 𝐴𝐵𝐶𝐷-matrix model provided in Chapter 3, a stepby-step algorithmic methodology was provided for the designer to implement in any scripting language he desires and explore the possible DA design solutions a given technology node can offer. For demonstration, in this work, the 55-nm CMOS ST process was used and 216 possible feasible DAs with BW ≥ 80 GHz were resulted to explore from.

Owing to this design process, graphical plots were produced that presented in an interesting 3D view the behavior of gain (Figure 4.15), bandwidth (Figure 4.16) and 𝑃 𝐷𝐶 (Figure 4.17) with respect to both the transistor size and number of unit-cells used. Using them, the designers can now study and analyze the correlation between each design parameter and arrive at the optimum design point, as also demonstrated through Figure 4.19 for choice of µ-TL segments length and Figure 4.20 for choice of compensating inductor 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 .

In the next chapter, this DSE plots were used to choose a 100-GHz CMOS DA that offers the highest FoM of 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ for implementation and on-wafer characterization.

Chapter 5

100-GHz Single Stage CMOS Distributed Amplifier

In the last chapter, using both the DA (3.14) matrix-based model with its unit-cell (3.17) representation, a systematic algorithmic methodology was proposed. Its aim is to explore, through scripting computer-automated algorithms, the possible amplifier gains and bandwidths obtainable from a given process node for any desired range of 𝑁 and transistor size (𝑊 𝐶𝑆 ). A design process was determined to be challenging to perform especially when using CAD tools in which 𝑁 has to be manipulated manually. For demonstration, the 55nm ST technology was used and the methodology was coded to automatically size CMOSbased DAs for a range of 2 ≤ 𝑁 ≤ 9 and 14 𝜇m≤ 𝑊 𝐶𝑆 ≤ 40 𝜇m. A total of 216 feasible solutions were obtained with design space solutions covering 80 GHz ≤ BW ≤ 130 GHz and ≈0 dB ≤ Gain ≤ 12 dB. In this chapter, focus is put on DA solutions that amplify up to 100 GHz and choosing the one that demonstrates global optimum 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit for on-wafer implementation and characterization. This chapter is structured as follows. Section 5.1 starts by describing the 55-nm ST technology process used. Section 5.2 covers the circuit design part. It demonstrates how the obtained 3D DSE plots from Chapter 4 were used to pinpoint the global optimum 100-GHz DA that satisfies our defined FoM criterion. Section 5.3 covers the circuit implementation part of the latter DA. Here, a new stacked parallel plate shunt capacitor [START_REF] El-Chaar | Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave Systems in Low-Cost Highly Integrated CMOS Technologies[END_REF] with high quality factor at mm-waves and high self-resonance frequency (𝑆𝑅𝐹) reaching 368 GHz is introduced. Section 5.4 discusses the experimental results of the fabricated DA circuit. A comparison with the performance of the state-of-the-art CMOS DAs, from Chapter 2, is presented in Section 5.5. Finally, Section 5.6 concludes and summarizes this chapter. .

STMicroelectronics 55-nm Node Process Technology

The technology process adopted in this work is introduced first since it will aid in providing a better visualization for when discussing integrated components and circuit realization. In this work, the eight-metal version of the 55-nm ST process is used. As illustrated in Figure 5.1, this process uses copper metallization with eight metal layer backend and aluminum metallization with the top-most metal later (AP) used for pads probing. Its back end of line (BEOL) is composed of one ultra-thick top metal layer (M8) on top of two thick metals (M7 and M6), in order to sustain high current densities and to reduce sheet resistance for high-quality passive circuit design in Analog/RF applications. Beneath them, five thin lower layers (M5-M2 and M1) are available for dense interconnections and contact with silicon devices. Under optimal bias conditions, nMOS transistors offer a unity-gain cutoff frequency (𝑓 𝑡 ) and maximum power-gain cutoff frequency (𝑓 𝑚𝑎𝑥 ) of 160 GHz and 246 GHz, respectively, suited for mm-wave applications.

100-GHz Single-Stage CMOS DA: Circuit Design

This section concentrates on explaining how we chose the optimum values for 𝑁 and 𝑊 𝐶𝑆 to design a CMOS-based DA with high 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit. For this optimum design point, it also demonstrates how we determined the required dimensions for the inductivetype segments and the loss-compensation inductors, 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 , to synthesize its unit cell.

At the beginning of this manuscript, we stated our interest for DAs that cover a minimum BW of 50 GHz for the opportunity to offer futuristic 100 Gb/s and above data-rates systems. In order to benefit from meaningful results for performance analysis with already available works and gain better perspective on the DA model capabilities, our choice is designated on bandwidth performance similar to the evaluated DAs from the literature presented in Chapter 2. It is noticeable that related works on silicon-based DA provided amplification up to around 100 GHz. Therefore, for a fair comparison, we decided to implement an amplifier device with similar passband. It should be noted that even higher BWs are possible for realization using 55-nm process, reaching as high as 130 GHz as indicated by Figure 4.16, but were ignored in the scope of model validation.

To determine the possible options for such BW criterion, the first step is to sort the available solutions from Figure 4.16 for an upper-corner frequency of 100 GHz. Since the available solutions do not present exact values of 100 GHz but around it, we decided to relax our search margin with a spread of ±2 GHz, i.e. we picked DA solutions that present 98 GHz ≤ BW ≤ 102 GHz. This led us to obtain a narrower DSE range of 35 possible options to choose from instead of the 216 options, as shown in Figure 5.2, with their respective gain and the required values of 𝑁 and 𝑊 𝐶𝑆 . As a second step, from this new set of 35 solutions, we analyze how DC efficient is each DA option when delivering its own insertion gain. This can be performed through Figure 5.3, where 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ performance for each of the 35 DAs is plotted with the required values of 𝑁 and 𝑊 𝐶𝑆 . It is visible, in our case, that this performance varies between 7.2 GHz/mW and 8.4 GHz/mW, with the relatively lowest values being for the DA options delivering higher gain. From here, the final step now depends on the application purpose of the DA; either the most 𝑃 𝐷𝐶 -efficient DA with degradation in gain or the highest gain with a degradation in 𝑃 𝐷𝐶 . Since our interest by the end of this thesis work is to publish our research efforts in order to assist in future mm-wave DA designs, our search was focused towards DAs that demonstrate comparable gain to the already published single-stage CMOS DAs; this is in order to highlight the added value from using our design technique. Doing so leads us to an even more restricted range and from it, we chose the DA that offers high 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit.

Referring back to the sate-of-the-art Table 2.2, the minimum gain published for single-stage CMOS DA is 7 dB; consequently, from Figure 5.2, our options were restricted to only four options (highlighted in green): a six unit-cells DA with 26 µm ≤ 𝑊 𝐶𝑆 ≤ 28 µm and a five unit-cell DA with 𝑊 𝐶𝑆 =31 µm. Since it was of our interest here to also implement a 𝑃 𝐷𝐶 -efficient amplifier, choice was directed on DAs offering high 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ between those four options; thereby, from Figure 5.3, our choice is now limited to either choosing a DA with 𝑁 = 6 and 𝑊 𝐶𝑆 = 26 µm or a DA with 𝑁 = 5 and 𝑊 𝐶𝑆 = 31 µm, respectively, where both offer ≈7.4 GHz/mW of 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ .

To choose from those two options, we opted for the DA with the smallest core area. This requires pre-knowledge of how the DA will be implemented. In this work, all inductors are implemented as conventional microstrip lines; by referring to Figure 4.18, it is clear that 𝑇𝐿 𝐿𝑑𝑠 has a dominant role in defining the physical height of the unit cell and hence of the DA. Thereby, from the DSE plot in Figure 4.20(b), that gives the required lengths for 𝑇𝐿 𝐿𝑑𝑠 , it was deduced that the five unit-cells DA option offers 31% less core area than its six unitcells counterpart since its loss-compensation inductors are smaller in value.

As a result, the DA solution made from 𝑁 = 5 unit-cells with 𝑊 𝐶𝑆 = 31 µm is determined to be our global optimum choice for circuit implementation and on-wafer characterization. Figure 5.4 shows the loss-compensated DA preliminary schematic diagram with its design parameters summarized in Table 5.1 and its design characteristics in Table 5.2. This DA will provide a simulated gain of 7 dB up to 100 GHz with a 𝑃 𝐷𝐶 of 30 mW. It is composed of five loss-compensated cascode Gm-cells, placed at a distance of 2 • (𝑙 2 ⁄ ) from each other; where the unit-cell segment length (𝑙 2 ⁄ ) is 131 µm. Transistor M1 is set to 31 𝜇m width and M2 twice that, i.e. 62 𝜇m. To compensate the high losses at 100 GHz while maintaining 1-dB of midband gain drop, a 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 of 43 µm and 129 µm, respectively, are needed as indicated by Figure 4.20. To prevent voltage drop across the termination resistors 𝑅 3 and 𝑅 4 when biasing the DA, the latter are AC-grounded through bypass capacitors 𝐶 𝑆 . In addition, 𝑇𝐿 𝐿𝑔 is AC-grounded through a capacitor 𝐶 𝑔 . It is worth highlighting how the circuit design process was simple, fast and direct. Owing to our matrix-based DA model (3.14), with its unit-cell model (3.17), and the possibility it offers for automating 𝑁 and 𝑊 𝐶𝑆 through MATLAB, analog designers can just directly pick their optimum design point in an interesting graphical way for any FoM they please. There is no need to change 𝑁 manually and run optimization for each time a design parameter is modified in order to search for possible improvement in performance. In the next Section 5.3, the layout aspect is covered and Section 5.4 covers the experimental results of the on-wafer measurements.

100-GHz Single-Stage CMOS DA: Circuit Implementation

This section discusses the layout implementation side of the previously chosen circuit. In subsection 5.3.1, the microstrip line topology used for implementing all type of inductors making the DA from unit-cell segments, 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 is presented. In subsection 5.3.2, a new high quality stacked parallel plate shunt-capacitor, used to implement 𝐶 𝑆 and 𝐶 𝑔 , is introduced. In subsection 5.3.3, the MOS transistor interconnection that are used when implementing are presented. Finally, subsection 5.3.4 is devoted to presenting the final implemented layouts of both unit-cell and DA with their own on-chip microphotographs.

Microstrip Transmission Line

For the TL, we have taken advantage of the accurate and flexible models that are provided in the PDK since they are based on pre-measurements from the semiconductor foundry. Its topology is presented in 3D view in Figure 5.5(a). Metal 1 (M1, in green) is the ground floor, metals 2 to 7 (M2 to M7) are used for complying with the local density rules and are connected to the ground while metal 8 (M8) is the signal strip. illustrates the attenuation constant (𝛼 𝑇𝐿 ) of the TL with respect to frequency for different widths ranging from 1 µm to 18 µm (limit imposed from PDK). For a fixed inductance of 76 pH, which represent the needed value to synthesize the unit cells segments, it is noticeable that the smaller the width, the lower 𝛼 𝑇𝐿 . It might seem that any µ-TL configuration has negligible loss impact; however, it must be noted that a DA is made of two inductive segments cascaded 𝑁 times, as evident in Figure 2.18. This means that the input microwave signal will propagate through a total of 2⨉N physical segments, in other words it will experience 2•N times the losses, on both the loaded input and output lines of the DA. Therefore, having the smallest width for TL can benefit from having the smallest length that aid in reducing surface area of the DA when implemented and it contributes in lowering the overall losses of the DA.

Since the 5-unit cells DA that we chose consumes 30 mW from a 1.2-V supply (25 mA), and on the bases of the DC-current handling limits expressed on the Design Rule Manual (DRM), we adopted for a width of 1 µm. We also decided to apply the same 1 µm width for all µ-TLs with the aim of having later on a simpler design implementation process where all the lines will share the same width.

High Quality and 𝑺𝑹𝑭 Stacked Parallel Plate Shunt Capacitor [61]

A common issue when synthesizing circuits at mm-wave is having at hand suitable passive components that demonstrate high quality (𝑄) factor. As made clear from the capacitor 𝑄-factor formula (𝑄 = 1 (𝜔 • 𝑅 • 𝐶) ⁄ for 𝜔 < (2 • 𝜋 • 𝑆𝑅𝐹); where ω is the angular frequency, 𝑅 is the equivalent parasitic resistor, 𝐶 is the equivalent parasitic resistor and 𝑆𝑅𝐹 is the self-resonance frequency), its 𝑄-value is constantly experiencing decrease with increase of operating frequency, thereby highlighting, in a general context, that capacitors may become a bottleneck for high performance mm-wave ICs. In this work, referring to Figure 5.4, capacitors 𝐶 𝑆 and 𝐶 𝑔 are used to provide DC decoupling and AC grounding for the termination resistors and inductor 𝑇𝐿 𝐿𝑔 , respectively.

As a solution, we proposed an on-chip passive stacked parallel plate shunt-capacitor (SPP-SC) [START_REF] El-Chaar | Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave Systems in Low-Cost Highly Integrated CMOS Technologies[END_REF], constructed without additional process steps and with focus on mm-wave performance. To prove its mm-wave performances, the proposed SPP-SC is compared with other state-of-the-art capacitor topologies found in the literature in addition to a woventype MOM capacitor already available in the 55-nm ST process design kit. The odd metal plates are linked together by a stack of via array placed on each side of the capacitor distributed in the longitudinal direction; this is to lower the resistive and inductive parasitic, where path towards ground for current density is shorter. It also contributes in confining the electric field within the plates, which contributes to the increase of capacitance and prevent coupling with adjacent components. The even metal plates are linked together from the front by a stack of via array and the stack is considered as the access side. The multi-plate structure offers several parallel paths, thus minimizing AC current density and lowering even more the aforementioned parasitic. Both via and structure configurations give rise to a capacitor with an overall high 𝑄 and 𝑆𝑅𝐹 merits, as will be demonstrated when discussing its on-wafer measurements.

Stacked Parallel Plate Shunt Capacitor

𝐶 0 ≅ ɛ 0 • 𝑊 • 𝐿 • ∑ ɛ 𝑟 𝑛 𝑡 𝑛 𝑆𝐹-1 𝑛=1 = 𝑊 • 𝐿 • 𝐶 𝑑 (5.1)
From Figure 5.6(b), design equation (5.1) can be deduced and used as a first approach, before layout implementation, to size the required the design variables: physical dimensions (𝐿 x 𝑊) and stacking factor (𝑆𝐹), to obtain a desired intrinsic capacitance (𝐶 0 ) value. The term 𝑆𝐹 is the number of metal plates desired and made available from a given technology node. Terms ɛ 𝑟 𝑛 and 𝑡 𝑛 are the relative permittivity and thickness of each dielectric layer, respectively, and ɛ 0 is the permittivity of free space. From (5.1), the benefit of the proposed topology can also be perceived: as 𝑆𝐹 increases with process node advancement, higher capacitance density per unit area (𝐶 𝑑 ) is expected.

Referring to the state-of-the-art work on high-frequency passive capacitors [START_REF] Seo | A 150 GHz Amplifier With 8 dB Gain and +6 dBm Psat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines[END_REF]- [START_REF] Shi | Millimeter-Wave Passives in 45-nm Digital CMOS[END_REF], similar works presented capacitors on the order of 300 fF at most. On that bases, and since by the end our main objective is to compare with what already exists by fixing a parameter and showing the added values, the capacitance 𝐶 0 in (1) is set to 300 fF. To demonstrate the proposed capacitor performance, the 300-fF SPP-SC is designed as follows. The entire metal stack of 55-nm node, i.e. 𝑆𝐹 = 8, is used to maximize to total 𝐶 𝑑 (≈0.91 fF µm 2 ⁄ )

for smaller dimensions and, also, to lower parasitic. Referring to Figure 5.6, reducing 𝑊 contributes to lower capacitor self-resistance, since GND connections from each side will be closer to the capacitor input; however, since the metal layers of our capacitor share equal dimensions, we were restricted by our Design-Rule-Manual (DRM) rules of the stringent thin-metal layers (M1-M5) length (𝐿). Thereby, 𝐿 is restricted up to 10.8 µm, what led to a wider width (𝑊) of 30.6 µm, accepted by the DRM, in order to preserve 𝐶 0 at 300 fF, (1). Figure 5.7 illustrates the microphotograph of final capacitor for on-wafer measurements.

On-wafer Characterization and Simulation Results

The 𝑆-parameters of the capacitor was measured via on-wafer probing using Anritsu 2port VectorStar ME7838D VNA setup. Conventional Thru-Reflect-Line (TRL) calibration method [START_REF] Engen | Thru-Reflect-Line: An Improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer[END_REF], with a 630-μm line and an open reflect, was then applied. The microphotographs of the TRL structures are shown in Figure 5.8. The de-embedded capacitor can be represented as the electrical equivalent model illustrated in Figure 5.9; where 𝑅 0 , 𝐿 0 and 𝐶 0 are the intrinsic resistance, inductance and capacitance, respectively, and 𝐶 eff is an effective capacitance that represents 𝐿 0 in series with 𝐶 0 . To characterize those elements, 𝑆to 𝑍-parameter conversion is first performed [START_REF] Pozar | Microwave Engineering[END_REF]. Intrinsic resistor 𝑅 0 is determined from the measured capacitor equivalent input-series resistance (𝑅 in ), (5.2a). Intrinsic capacitance 𝐶 0 (5.2b) is determined from the measured capacitor equivalent input series-capacitance (𝐶 in ) using (5.2c) and the intrinsic inductance 𝐿 0 is determined from (5.2d) where 𝜔| 𝑄=0 is the angular frequency at 𝑆𝑅𝐹 since m{𝑍 11 }| 𝑄=0 = 0.

𝑅 𝑖𝑛 (𝜔) = ℜ𝑒{𝑍 11 }

(5.2a)

𝐶 0 = 𝐶 𝑖𝑛 | 𝜔≈0 (5.2b) 𝐶 𝑖𝑛 (𝜔) = 𝐶 𝑒𝑓𝑓 (𝜔) = - 1 𝜔 • 𝑚{𝑍 11 }
(5.2c)

𝐿 0 = 1 (𝜔| 𝑄=0 ) 2 • 𝐶 0 (5.2d) 𝑄(𝜔) = - 𝑚{𝑍 11 } ℜ𝑒{𝑍 11 } (5.2e)
Figure 5.10 illustrates the measured and simulated RLC-elements against frequency for the implemented 300-fF SPP-SC. The capacitor experience a relatively constant 𝑅 in against frequency with a measured average magnitude of 0.37 Ω. The increase of resistance at frequencies below 6 GHz is attributed to the lower limit of TRL defined by the 630-𝜇m line. Since 𝑅 in is shown here to have a flat variation in the measurements frequency range, it can safely be considered as a lumped 𝑅 0 . The slight difference in extracted resistance between EM simulation and measurement results could be attributed to limitation in our equipment to accurately quantify very low losses. The proposed topology provides a relatively constant value of 𝐶 𝑖𝑛 within the frequency range considered, signifying that the 𝑆𝑅𝐹 are all beyond our measurement limit (100 GHz). Measured intrinsic capacitances 𝐶 0 of 285 fF is obtained for the calculated 300-fF. The slight difference between what was calculated (5.1) and measured could be due to process variation in dielectric layers permittivity (ɛ 𝑟 ). The measured 𝑄-factor is plotted in Figure 5.11 using 𝑄(𝜔) from (5.2e). 𝑄-value of 14.7 is obtained at 100 GHz. It must be noted that the drop of 𝑄-value here is dominated by the increase of frequency rather than resistance, since from Figure 5.10 it is clear that 𝑅 𝑖𝑛 , at any given frequency, remains almost the same. The proposed capacitor also contributes to a high 𝑆𝑅𝐹 merit, as demonstrated in Figure 5.11, where measured 𝑄-factor is extrapolated using MathWorks MATLAB and 𝑆𝑅𝐹 is then extracted at frequency in which 𝑄 = 0 (since m{𝑍 11 }| 𝑄=0 = 0). The 300-fF capacitor is estimated to reach an 𝑆𝑅𝐹 of 368 GHz. Using those values, 𝐿 0 is then obtained using (5.2d) and summarized within Table 5.3 with the other intrinsic elements modeling the SPP-SC in addition to the values extracted from EM simulation. A slight difference in the extracted values of 𝐿 0 exists between measurement and simulation. This is due to the measured 𝐿 0 being determined from an extrapolation of a measured 𝑄-factor with evident distortion caused by the measured lowvalue resistance fluctuation against frequency, as illustrated in Figure 5.10. 5.12 (next page) compares de-embedded to both lumped modeled (Figure 5.9) and EM simulated 𝑆 11 parameters for all 300-fF SPP-SC. A very good agreement is obtained. This indicates how accurate the proposed physical model is up to 100 GHz.

Performance Comparison with State-Of-the-Art Capacitor Topologies

After introducing the capacitor topology with its on-wafer performance, a comparison with state-of-the-art capacitors is performed here. As part of AC-grounded components, radial stub [START_REF] Seo | A 150 GHz Amplifier With 8 dB Gain and +6 dBm Psat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines[END_REF] is used for its ease of design but reserves large chip area. Slow-wave stub [START_REF] Franc | High-performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Band-pass Filters[END_REF] is proposed that benefits from length reduction; however, wider footprint is required resulting in comparable area. Metal-Insulator-Metal (MIM) capacitor is one topology that can offer high capacitance density due to its special high-𝑘 dielectric layer but suffers from high dielectric losses at mm-waves. In [START_REF] Ghadiri | High-Quality-Factor Active Capacitors for Millimeter-Wave Applications[END_REF], a 120-fF MIM capacitor demonstrated a 𝑄value of 3.8 at 100 GHz. Also, the majority of low-cost CMOS technologies lack MIM capacitor options. Metal-Oxide-Metal (MOM) capacitor is an alternative option that uses existing metals in the process backend-of-line (BEOL) but experiences lower 𝑄-values due to its structure consisted of narrow thin metal wires. For instance, a 129-fF woven-structure MOM capacitor provides a 𝑄-value below 3.2 at 100 GHz, [START_REF] Quémerais | CMOS 45-nm 3D metaloxide-metal capacitors for millimeter wave applications[END_REF]. In [START_REF] Shi | Millimeter-Wave Passives in 45-nm Digital CMOS[END_REF], for a common multi-stack interdigital capacitor, the same value of 120-fF provided a 𝑄-value of 2.5 at 100 GHz. In addition, MOM capacitors experience a rapid 𝑆𝑅𝐹 reduction when higher capacitance value is desired which could be attributed to the substantial increase in its parasitic-inductance caused by its wire-type topology. It is also worth mentioning the simulation efforts where they require large processing resources since condensed meshing process is required for their closely spaced wires when optimizing ICs in full 3D-EM simulators. Other approaches referred to as active capacitors such as implementing gate oxide capacitors [START_REF] Ghadiri | High-Quality-Factor Active Capacitors for Millimeter-Wave Applications[END_REF] exist to improve 𝑄-factor and area-efficiency, but they need a DC bias and are strongly process and temperature dependent. Table 5.4 compares the measured capacitor performance with results from state-of-theart capacitors. To the authors' knowledge, this work demonstrated a capacitor that offers the highest 𝑆𝑅𝐹 and 𝑄 merits while providing large capacitance values for mm-wave frequency range. In terms of occupied area, it is true that the SPP capacitors reserved larger area between the stated ones [START_REF] Ghadiri | High-Quality-Factor Active Capacitors for Millimeter-Wave Applications[END_REF]- [START_REF] Shi | Millimeter-Wave Passives in 45-nm Digital CMOS[END_REF], but this is attributed to the characterized SPP in this work having larger 𝐶 0 . For the case of [START_REF] Shi | Millimeter-Wave Passives in 45-nm Digital CMOS[END_REF] 350-fF capacitor compared to the 285-fF SPP, the former presented compact area which is largely related to [START_REF] Shi | Millimeter-Wave Passives in 45-nm Digital CMOS[END_REF] using an 11-metal version of a 45-nm node compared to the 8-metal version of a larger 55-nm node used in this work and, also, at the expense of a lower 𝑆𝑅𝐹.

As a conclusion, measurements showed attractive performance from excellent quality factor and high 𝑆𝑅𝐹, making it suitable for analog systems operating until 100 GHz and possibly even up to 368 GHz, proving eligibility for both broadband and high data-rate ICs.

Performance Comparison with 55-nm Woven-Structure MOM Capacitor

In the design kit of the technology at hand, a common woven-structure MOM capacitor is available for usage as a parameterized cell (PCell). Figure 5.13 illustrates its topology where it makes use of existing metals (M2-M4) in the process BEOL. To justify even further the need for our proposed SPP-SC topology, a comparison with the mm-wave performance of this PCell MOM capacitor is also performed. For a fair comparison, the value of 300-fF capacitance was fixed for both topologies, and both resistance, capacitance variation against frequency and quality factors were plotted in Figure 5.14. The 300-fF PDK woven-structure MOM capacitor reserved area of 30.6 µm ⨉ 6.23 µm, a lower area relative to the SPP capacitor due to the woven-structure topology providing higher capacitance density per area (1.5 fF µ𝑚 2 ⁄ ) From Figure 5.14(a), for the same capacitance value of 300-fF, the SPP-SC demonstrated flat capacitance variation against frequency, which signify an 𝑆𝑅𝐹 well above 100 GHz (close to 368 GHz as determined from Figure 5.11), whereas the wovenstructure PDK MOM demonstrates a rapid increase in capacitance which signify its 𝑆𝑅𝐹 is close to 100 GHz. From Figure 5.14(b), the SPP-SC delivers a self-resistance much lower than that of the PDK MOM capacitor and hence a much desirable quality factor at millimeter wave regions. At 100 GHz, the former capacitor has 0.33 Ω of self-resistance and 𝑄 = 14.7, whereas the latter capacitor has 3.1 Ω of self-resistance and 𝑄 = 0.53.

Through this analysis, we validated even more the efforts taken to propose a different capacitor than the already available ones for the purpose of gaining better overall performance when designing our 100-GHz DA and any mm-wave ICs in a general context.

MOS Transistor Interconnection

The transistor connection is crucial in mm-wave design. In order to reduce the resistive losses that can load the DA and hence degrade its passband, we have adopted the topology illustrated in Figure 5.15 during layout implementation. The CG-FET uses the one of

Standalone Unit-Cell Layout and Microphotograph

A single unit cell is implemented as a standalone device for the purpose of validating the proposed model (3.17) frequency behavior with measurements through 𝑆-parameters characterization.

Referring to the design parameters determined in Section 5.2 (Table 5.2) and the electrical schematic provide in Figure 5.4, and using both the microstrip line topology, the proposed SPP capacitor topology for implementing 𝐶 𝑔 as a decoupling capacitor and the transistor interconnection introduced in subsection 5.3.1, 5.3.2 and 5.3.3, respectively, the unit cell can be synthesized as shown in Figure 5.16. Due to the high 𝑆𝑅𝐹 and quality factor of a single SPP-SC capacitor, as was determined in Figure 5.10, we were able to provide a strong AC-ground at the upper end of the 43-µm 𝑇𝐿 𝐿𝑔 facing the DC-input side and with 𝑆𝑅𝐹 well above 100 GHz. Figure 5.17 illustrates the microphotograph of this unit cell as a standalone circuit. Extra DC pads were attached on top for biasing gate-pin of the CG transistor (M2) through external power supply. For the drain pin of transistor M2 and gate pin of transistor M1, biasing is provided through the RF-pads by the probes of the VNA. Figure 5.17: Microphotograph of the fabricated standalone unit cell in 55-nm process for onwafer characterization.

100-GHz Single-Stage DA: Layout and Microphotograph

In order to achieve the targeted 7 dB of gain up to 100 GHz, we need to connect five replicas of the same unit cell, Figure 5.4, together as suggested by the design method. 5.5 summarizes all of its design parameters values used during layout implementation. All µ-TL were implemented using thickest metal available in technology, M8, with same width of 1 µm, as explained in subsection 5.3.1. The μ-TL segments are done with length 𝑙 2 ⁄ of 131 μm. Both 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 are implemented with length of 43 μm and 129 μm, respectively. Both termination impedances 𝑍 3 and 𝑍 4 are realized as series RC loads. Both 𝑅 3 and 𝑅 4 are implemented using technology component as N+ silicided polysilicon resistors, and were AC-grounded through a 1-pF bypass SPP capacitor (𝐶 𝑆 for both 𝐶 3 and 𝐶 4 ) to have a DA passband starting from 10 GHz; as was already stated in Chapter 4 design algorithm (Step 4), we decided to go with the highest 𝐹 𝑙𝑜𝑤𝑒𝑟 of 10 GHz instead of 1 GHz, for instance, since they showed equal gain; but choosing higher frequency will benefit us from having a bypass capacitor with a small on-chip area, hence smaller DA. After finishing the design layout implementation and before sending to fabrication, one last simulation (as a validation step) was performed on ADS schematic to make sure that everything is in order. 𝑅 3 and 𝑅 4 had to be refine hand-tuned to 53.5 Ω to slightly readjust the passband midband gain drop to be precisely at 1-dB limit. This step is not always necessary and can vary from one designer to another. But, it could be considered as a possible quick solution when slight readjustment is required at the end-stage before sending to fabrication instead of, for instance, increasing 𝑇𝐿 𝐿𝑑𝑠 that will affect the height of the DA (even if 𝑇𝐿 𝐿𝑑𝑠 was slightly increased) and forces the designer to redo the synthetization process once more followed by DRC/GAG validation procedure.

100-GHz Single-Stage CMOS DA: Experimental Results

In this section, simulation and measurement results of the amplifier device are presented and compared. The measurement setup is first introduced in subsection 5.4.1. The 𝑆parameters analysis of both the unit-cell and DA are discussed in subsection 5.4.2. In subsection 5.4.3, a performance analysis of the implemented DA is carried out. Here, stability and group delay analysis are presented in addition to power capabilities analysis from 1-dB gain compression point (P1dB), saturation power (P sat ) and third order intercept point (IP3). Finally, a comparison with state-of-the-art CMOS DAs is carried out in Section 5.5.

Vector Network Analyzer Description

All 𝑆-parameters measurements are performed via on-wafer probing using the VNA setup shown in Figure 5.21. This setup consists of an Anritsu 2-port VectorStar ME7838D mm-wave system available with the MS4640B series Vector Network Analyzer (VNA) and the 3739C test set to control two MA25300A mm-wave modules, each connected to Cascade Microtech Infinity GSG 50-μm pitch probes. Both MS4640B and 3739C devices cover frequencies < 54 GHz then transition towards MA25300A modules occurs to cover ranges above 54 GHz. For biasing, two external bench power supplies are used, Keysight B2901A to bias the gate pins of cascode CG FETs and Keysight B2902A to provide bias along the loaded gate-and drain-line of the DA through RF probes. VNA calibration using line-reflectreflect-match (LRRM) technique was performed before measurements to remove probing RF impact. 3.17), to both ADSbased simulation and measurement of a single unit-cell and DA, respectively. Great agreement is obtained between ADS and 𝐴𝐵𝐶𝐷-model results. This indicates how reliable the proposed model is when used as design tool, this support the forth criterion. Unit-cell pads were de-embedded from measurements but the DA pads were not for a better representation of the latter behavior when used as standalone IC in real-world applications. Biased at 𝑉 DD =1.2 V, the unit cell consumed an overall measured current of 5 mA and the DA consumed 25 mA-same consumptions when calculated during design process using (4.9). This resulted in a measured 𝑃 𝐷𝐶 of 6 mW and 30 mW, respectively. The DA achieves an average insertion gain 𝑆 21 of 6.7 dB. A peak gain of 8 dB is observed at 91 GHz resulting in an in-band ripple of ±1.3 dB when referenced to mid-band gain and, hence, a coverage range from 𝐹 𝑙𝑜𝑤𝑒𝑟 of 16.7 GHz up to an 𝐹 𝑢𝑝𝑝𝑒𝑟 of 100 GHz. This gives an amplified passband BW of 83.3 GHz and leads to a GBP of 180 GHz. The slight difference (3.3 GHz) at the upper side of the frequency spectrum, where the measured DA reaches higher frequencies compared to the simulated one, could be attributed to a slight overestimation of the parasitic the transistors used are made from. The increase of gain at frequencies < 10 GHz is attributed to the small bypass capacitor (𝐶 𝑆 ) used to cover down to 10 GHz (a decision we made in Step 4 of our design methodology in subsection 4.2.2). This can be improved by either using larger 𝐶 𝑆 (MIM capacitors in this case could be considered for their larger capacitance density) or shorting both 𝑅 3 and 𝑅 4 directly to GND as illustrated in Figure 4.1. The latter option will offer a DA with a flat gain starting from DC level, but at the expense of higher 𝑃 𝐷𝐶 since DC-current will pass through those resistors (caused by the DC-voltage bias along the output loaded-line for 𝑅 3 and along the input loaded-line for 𝑅 4 ). The dip in gain between 𝐹 𝑙𝑜𝑤𝑒𝑟 and 10 GHz is caused by an overestimation of loaded-lines termination resistances during implementation. Both input and output matching levels, S 11 and 𝑆 22 , respectively, are better than -10 dB starting from 4.35 GHz. The amplifier maintains input matching up to 100 GHz while the output matching remains < -10 dB up to 91.6 GHz with a slight dip back at 99 GHz. The reverse isolation S 12 is less than -50 dB below 1 GHz and reaches a maximum of -10 dB at 100 GHz. The overall good agreement between simulation and measurement results validates the design process.

S-parameters Analysis: Unit-Cell and DA Model Validation

Implemented DA Performance Analysis

After demonstrating the benefits this matrix-based model offers from ease and direct design process, and the reliability it provides where good agreement was obtained between simulations and measurements, focus here is placed on analyzing the performance of the fabricated 100-GHz CMOS-based DA. Both group-delay, stability and large-signal performance analysis is performed hereafter. It should be pointed out that those three design characteristics were not part of the CAutoD algorithm presented in Chapter 4 and what is demonstrated in this subsection is just an illustration of what we would obtain if we decided to go with a DA design process that focuses solely on extending and flattening passband. The same three analysis were not applied to the standalone unit-cell since from Figure 5.22(a) this device does not provide amplification and hence it has no interest for practical usage.

Group Delay Performance Analysis

Figure 5.23 shows the DA group-delay behavior besides its 𝑆 21 phase. Inside its passband ranging from 𝐹 𝑙𝑜𝑤𝑒𝑟 of 16.7 GHz to an 𝐹 𝑢𝑝𝑝𝑒𝑟 100 GHz, determined previously, the group delay experiences a measured ±5 ps variation up to 80 GHz and then increases quickly as it approaches the upper side 100 GHz. This is because amplifier S 21 phase is linear against frequency until 80 GHz and becomes non-linear as it approaches passband steep roll-off at higher frequency end.

Stability Performance Analysis

The DA 𝑘and |𝛥|-factor derived from measurements and compared to simulation can be seen in Figure 5.24. The DA is unconditionally stable for the whole measured passband except at frequency of 100 GHz where it becomes conditionally stable with 𝑘 = 0.85. This decline is attributed to a higher measured S 12 reaching an utmost of -10 dB compared to -17 dB in simulation and a wider S 21 -passband. This led to a higher

Large-Signal Performance Analysis

While the main scope of this thesis is to come up with a different and new design technique for mm-wave DAs, the large signal performance are worth mentioning to gasp the performance of the UWB amplifier device. The following analysis is presented hereafter where the power delivery capability of the former device is analyzed. Due to limitation in our measurement equipment, the provided data in .25 shows the simulated output power and gain as a function of input power at 10 GHz, 60 GHz and 90 GHz. The maximum output power at the three frequencies is 9.5 dBm, 9.1 dBm and 6.3 dBm, respectively. At 10 GHz and 60 GHz, the gain exhibits similar behavior while at 90 GHz, the gain is compressed slightly earlier. Figure 5.26 shows the simulated OP1dB, P sat and IP3 as a function of frequency. The average P 1dB , P sat and OIP3 over the entire frequency band are 2.4 dBm, 8.6 dBm and 12.5 dBm, respectively. The maximum P sat of 9.5 dBm and OIP3 of 14.3 dBm were achieved at frequencies below 40 GHz. Table 5.6 compares the simulated P 1dB results to the ones we were able to measure at 10 GHz, 30 GHz, 60 GHz and 90 GHz. Both OIP3 and P sat measurements were not possible to provide due to lack of coupler equipment to send two tones to perform the former measurement and the incapability of our VNA in providing more than 0 dBm for the latter measurement. One can note that measured results are well correlated with simulation and are considered acceptable performance for such a CMOS-based small-signal distributed amplifier.

Comparison with State-of-the-Art CMOS-Based DAs Performances

In Chapter 2, state-of-the-art DA performances in different process nodes and technologies was introduced. It was concluded that indeed HBT-based DA can outperform FET-based DAs due to the HBT superiority in providing higher transconductance. Since this is commonly known and for a fair comparison, here our characterized DA is compared to only CMOS-based DAs. Table 5.7 summarizes our measured results to the other startof-the-art silicon DAs. & BWs are reported as declared by authors. £ Ripple limits is determined within the authors declared BW for their reported gain. % Estimated from plots @ Cascaded Multi-stage DA (CMSDA) $ Cascaded single-stage DA (CSSDA) * Biased using external bias-tee ** Biased using integrated bias-tee This work demonstrates comparable gain while being the most power-efficient DA. As a result, this work reports the highest GBP P DC ⁄ figure of merit for single-stage CMOS DA of 6.01 GHz/mW, to the authors' knowledge. It is true that our presented DA does not provide the highest GBP between the stated CMOS DAs; for instance, [START_REF] Po-Han Chen | A high performance DC-80 GHz distributed amplifier in 40-nm CMOS digital process[END_REF] provides a GBP of 450 GHz. However, one can benefit from our low 𝑃 𝐷𝐶 to cascade three of our DA stage until [START_REF] Po-Han Chen | A high performance DC-80 GHz distributed amplifier in 40-nm CMOS digital process[END_REF] P DC of 90 mW is reached. This would lead to a higher GBP of 843 GHz and, hence, a GBP P DC ⁄ of 9.37 GHz/mW; highlighting once more, that thanks to our model and algorithmic scripted method, we were able to squeeze out the last drop of possible performance improvement from each design parameter when design the single stage DA. It is true that cascading leads to increase in total area; however, in this case, layout improvements such as pads rearrangement would have been considered. In addition, it is worth mentioning the contribution a smaller technology node (e.g. 40-nm [START_REF] Po-Han Chen | A high performance DC-80 GHz distributed amplifier in 40-nm CMOS digital process[END_REF] and 22-nm [START_REF] Testa | 110 GHz travelling-wave amplifier in 22 nm FD-SOI CMOS[END_REF]) can bring in area reduction compared to the 55-nm adopted in this work, which could explain their higher GBP (P DC • Area) ⁄ merit.

Conclusion

In this chapter, the 𝐴𝐵𝐶𝐷-model was put to practice where it was used to realize a 100-GHz single-stage loss-compensated CMOS DA using ST 55-nm CMOS technology. Both the circuit design and layout implementation aspects of the design process were covered. It showed how we were able to directly determine the optimum number of unit cells and transistor size, besides other design parameters, needed to satisfy our desired FoM of high 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ with reasonable gain. It demonstrated how the design process can be rendered simple and fast by using the proposed methodology and scripting, and interesting through 3D-DSE plots.

During the design process, a lack of high-quality capacitor suitable for mm-wave design was detected. As a solution, a viable passive capacitor topology is demonstrated and characterized. An accurate design equation (5.1) is also provided with at most 5% of discrepancy with the characterization performed. Measurements showed attractive performance from excellent quality factor and high 𝑆𝑅𝐹, making it suitable for analog systems operating until 100 GHz and possibly even up to 368 GHz, proving eligibility for both broadband and high data-rate ICs. Furthermore, it is fabricated without extra mask costs (unlike MIM capacitor) and easy to simulate in a time-efficient manner in full 3D-EM simulators if compared to MOM capacitor, since it does not involve a mesh of closely spaced thin metal wires. Finally, it is a promising topology in advanced technology nodes since higher capacitance density is expected with metal stack increment.

When comparing overall behavior of the unit-cell and DA, Figure 5.21, to both ADSbased simulation and measurements, good agreement was obtained validating therefore the accuracy of the model. In addition, when compared to the state-of-the-art CMOS DAs (Table 5.7), optimum 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ performance was obtained owing to the capability of the proposed model in presenting the complete DA and taking all of its design parameters into consideration during the automated sizing. Joining the latter two criteria contributes to maximizing the performance that could possibly come from each design parameter.

an analytical-based study was provided that demonstrates a trade-off between 𝑁 and 𝑀 to reach a certain gain while being 𝑃 𝐷𝐶 -efficient. Herein, we decide to make use from the outcome of our previously described algorithmic methodology to choose new set of adequate design-variables sizes in order to have the optimum GBP per single stage. This proposition will aid in maximizing the cascaded DA overall GBP, which in return will have advantageous influence on having a much higher overall 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit.

The circuit design part for a 100-GHz bandwidth criterion was already covered in Chapter 5 (Section 5.2). It was determined that 35 DA options were only able to satisfy such criterion, from the whole 216 DAs design space of Figure 4.11, with their respective optimum values for 𝑁 and 𝑊 𝐶𝑆 .

Since our aim here is to show that maximizing GBP is possible through our model, we decided to pick the optimum design option that offers the highest gain. Referring to Figure 5.2, the DA with 𝑁 = 6 and 𝑊 𝐶𝑆 = 28 µm offers gain of 7.7 dB over 100 GHz of passband, higher compared to the previous option of 𝑁 = 5 and 𝑊 𝐶𝑆 = 31µm (7 dB). Of course, from Figure 5.3, it is visible that the former option offers relatively lower 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ than the latter due to its higher 𝑃 𝐷𝐶 (32.3 mW instead of 30 mW, determined from Figure 4.17). However, when cascading the DAs, the higher gain will benefit us from having a much higher overall GBP and therefore will lead to an even greater 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ performance, as will be proven here shortly after.

For the chosen design option of 𝑁 = 6 and 𝑊 𝐶𝑆 = 28 µm, the segments length (𝑙 2 ⁄ ) was determined to be 125 µm from Figure 4.19 and the values of its loss-compensating µ-TL-type inductors, 𝑇𝐿 𝐿 𝑔 and 𝑇𝐿 𝐿 𝑑𝑠 , are found to be 54 µm and 155 µm from It should be highlighted how the re-design process was easy and determining the required design variables was immediate without any re-calculation of any kind. This would have not been the case if the previously methods mentioned in Chapter 3 (Section 3.2) were used nor would it have been the case if CAD tools that only offers schematic design environment where change of FoM is followed by re-doing the manual exchange of 𝑁 from the scratch and consequently followed by a re-optimization process per exchange.

What remains is determining the number of cascaded stages (𝑀) needed. From state-ofthe-art Table 2.2, it is noticeable between cascaded DAs that the commonly adopted gain ripple is ±3 dB over the passband. For this reason, we can benefit from our 1-dB restriction imposed during our design process, as was already specified in the algorithmic design methodology (Step 5), and cascade the single-stage DA six times, i.e., set 𝑀 = 6. This will lead to a preliminary simulated gain of 46.2 dB ±3 dB. For a 100-GHz passband, this will result in a GBP of 20.42 THz. Of course, 𝑃 𝐷𝐶 will also be 6-fold higher, but when calculating the overall 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ of the cascaded DA, one will obtain 105.5 GHz/mW; proving the previous statement, that cascading does indeed increase 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit. Such value is determined to be the highest between the recorded values in the literature, based on state-of-the-art

THz GBP Cascaded CMOS DA: Circuit Implementation

This section discusses the layout implementation part of the previously chosen circuit. Since we will implement a DA circuit similar to the one implemented in Chapter 5, but just with different values for 𝑁 and 𝑊 𝐶𝑆 , both discussions on microstrip line topology and shunt SPP capacitor topology were already covered in Section 5.3 and are not re-written here. Only the extra difference is highlighted where the output loaded-line of the DA here is biased through a newly proposed integrated wideband bias-tee whereas the former DA of Chapter 5 was biased from the external VNA through its RF-probes.

Integrated Wideband Millimeter-Wave Bias-Tee [68]

In a general context, realizing wideband active ICs is accompanied with additional design efforts to produce suitable components used to synthesize them, mainly ones capable of providing wideband characteristic. For instance, in Chapter 5 an issue with having high 𝑄-factor and 𝑆𝑅𝐹 shunt capacitor components, suited for the mm-wave band, was detected and was resolved by proposing our own SPP topology. Another challenge encountered is when the wideband IC is required to be synthesized with its own bias tee. This requires the implementation of a compact, low power-overhead and wideband RF-choke. For the case at hands, for instance, the bias-tee has to be able to provide RF-choke capability covering frequencies reaching the highest operating frequency of the DA, i.e., 100 GHz. This is considered challenging since parasitic at high frequency become dominant and can disrupt the performance of the bias tee and, consequently, have negative influence on the behavior of the device itself.

Already Existing Techniques for Realizing Wideband Bias-Tees

There already exists traditional techniques to realize a bias-tee and they are summarized as follows. The most common technique to realize a wideband and compact biasing network is by using integrated resistive elements as RF-chokes [START_REF] Kimura | Loss-compensated distributed baseband amplifier IC's for optical transmission systems[END_REF]. With this approach, a series resistance is used between power-supply equipment and on-wafer device to inhibit RF signals from leaking outwards and any possible interaction between both two. This approach also benefits from allowing the lower-corner frequency of the IC to extend downwards to DC levels (0 Hz). However, this approach is not suitable when DC power efficiency is important since it causes a voltage drop across the resistor and thus 𝑉 𝑑𝑑 must be increased to preserve the same operating point of the biased circuit. External bias-tees with large inductance are commonly used, such as in [START_REF] Kim | A 92 GHz Bandwidth Distributed Amplifier in a 45 nm SOI CMOS Technology[END_REF], [START_REF] Plouchart | A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology[END_REF] and [START_REF] Ellinger | 60-GHz SOI CMOS traveling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz[END_REF], to mitigate this issue owing to their attractive low DC-resistance while providing high reactance that chokes RF signal. This technique, however, requires the use of a bulky and expensive offchip inductor not suited for fully integrated systems. Embedding a large spiral inductor as part of the design to avoid cost penalty, such as in [START_REF] Huang | A high-gain low-noise distributed amplifier with low DC power in 0.18-µm CMOS for vital sign detection radar[END_REF], is suited for relatively small operational bandwidths where they can be positioned below 𝑆𝑅𝐹 [START_REF] Pulijala | Spiral inductors for V-band wireless ICs[END_REF], but this integrated solution may become problematic when dealing with several tens of gigahertz bandwidth. This is due to the parasitic elements having larger influence at high frequencies and hence affecting the behavior of the wideband bias-tee. Most often, this happens to the bias-tee 𝑆𝑅𝐹 where the overall parasitic can alter it and subsequently alter the passband behavior of the device being designed. Shifting this 𝑆𝑅𝐹 outside such wide passband by reducing those parasitic is considered challenging especially when the intended circuit to be biased operates up to 100 GHz.

As a solution, a compact fully integrated bias-tee with low DC-overhead and wideband performance is proposed. Compared to conventional approach where bias-tees, the ones that use inductor components as RF-choke, are designed to reduce the overall parasitic and push their 𝑆𝑅𝐹 outside the device passband, i.e., above the highest operating frequency of the biased device, here the bias-tee is designed by taking advantage of the parasitic capacitance and pushing its 𝑆𝑅𝐹 below the passband of the biased device.

For the sake of simplicity in demonstrating the proposed bias-tee idea, its design concept and process are first introduced followed, as a second step, by a practical example where a 100-GHz bandwidth standalone bias-tee is implemented and its simulation versus measurement is discussed.

Proposed Wideband Bias-Tee: Design Concept

.1 illustrates the complete biasing network configuration. The left side represents the DC-power supply, the right side represents the intended RF-circuit to be biased and the middle network represents the lumped-element circuit of the proposed biastee. The bias-tee here is a two-port RF network, with port-1 towards DC-power supply side and port-2 towards the RF-circuit side. When compared to the practical implementation in Figure 6.6 where each single-stage DA is biased from its output-loaded line, it is noticeable that the termination resistance 𝑅 and DC-decoupling capacitance 𝐶 (𝑅 3 and 𝐶 3 , respectively, on Figure 6.6) are considered as part of the bias-tee. Conventionally, the bias-tee reactance-type RF-choke is designed such that its 𝑆𝑅𝐹 is pushed above the biased circuit highest operating frequency (𝐹 𝑢𝑝𝑝𝑒𝑟 ) while providing sufficiently high inductive reactance across its passband. This is usually achieved by optimizing the structure on the basis of 𝐿 𝑆 while attempting to diminish RF-choke parasitic 𝐶 𝑆 . Our proposed way, however, takes advantage of the 𝑆𝑅𝐹 instead of suffering from it. This is done by making use of RF-choke parasitic capacitance 𝐶 𝑆 and considering it now as a design parameter while pushing bias-tee overall resonance frequency below the biased circuit lower-corner frequency (𝐹 𝑙𝑜𝑤𝑒𝑟 ). For this reason, the bias-tee of the proposed approach could be viewed as having a "capacitive-reactance RF-choke", i.e. the passband of the device is operating in the capacitive region established by 𝐶 𝑆 . Referring to Figure 6.1, shunt capacitor 𝐶 𝑎 is added as a filtering capacitor to protect the integrated mm-wave circuit against any perturbation that comes from DC power supply and its wiring. In practice, offchip capacitors are also implemented all along the DC-path and probe coming from external power supply. In addition, large on-wafer integrated capacitors are also added at pad-level to enhance protection. Those have no effect on bias-tee as long as 𝐶 𝑎 acts as a perfect ACground in the DA frequency range of interest. Capacitors 𝐶 𝑎 and 𝐶 own parasitic are not considered herein, being negligible as compared to 𝐿 𝑆 -𝐶 𝑆 tank elements and would be, for instance, if the SPP capacitor introduced in Chapter 5 (Section 5.3) is used. Finally, the purpose of adding 𝐿 𝑒 , a small value inductor, is to remove excess imaginary part of the bias tee input impedance seen by the device being biased. This will be better explained when discussing equation (6.5).

In a first approach, 𝐿 𝑆 and 𝐶 𝑆 are being considered as independent parallel components. Equation (6.1) demonstrates the impedance of the 𝐿𝐶-tank. Emphasis was put intentionally here on the parasitic capacitance 𝐶 𝑆 as a design parameter, instead of 𝐿 𝑆 , as it is noticeable how capacitor 𝐶 𝑆 can be benefited from to create high impedance RF-choke. Later on, when dealing with the practical example of designing a 100-GHz bandwidth bias-tee for the DA, an empirical relationship between both is provided as an example that designers can adopt to choose adequately the RF-choke parameters. reduced as much as possible while 𝑅 𝑖𝑛 ′ be made as close as possible to the real part of the output impedance of the device being biased-in this case, to the single-stage DA. Up to this point, an additional relationship for 𝐶 𝑆 and 𝐿 𝑆 is necessary to pursue the proposed biastee design; it can be obtained through practical implementation considerations, as done next.

100-GHz Bandwidth Bias-Tee: Circuit Design Process

The design process of our wideband bias-tee, suitable for the DA discussed in Section 6.1, will be covered here. Beforehand, this process requires pre-knowledge of the bandwidth lower-limit of the device tackled. In our case, we will target by the end of this chapter a DA that will start amplifying from an 𝐹 𝑙𝑜𝑤𝑒𝑟 of 5 GHz until an 𝐹 𝑢𝑝𝑝𝑒𝑟 of 100 GHz. The RF-choke used is a microstrip spiral inductor realized using the eighth metal layer of ST 55-nm technology. It is chosen here since it is widely known to offer an equivalent parallel 𝐿 𝑆 -𝐶 𝑆 tank at high frequency without the need to add explicitly extra lumped components. However, for this choice, 𝐶 𝑆 becomes a parameter correlated to 𝐿 𝑆 and, thereby, requires as a first step to be modeled analytically. Figure 6.2 gives the simulated 𝑓 𝑡𝑎𝑛𝑘 and DC self-resistance of the spiral inductor metallic winding -this will be referred back to when discussing measurement results-, using ANSYS' HFSS, as a function of its self-inductance 𝐿 𝑆 . By curve fitting the collected 𝑓 𝑡𝑎𝑛𝑘 to 𝐿 𝑆 , an empirical expression is formulated in (6.3). The design parameter 𝐶 𝑆 can be represented analytically as (6.4).

𝐶 𝑆 = 1 ((2𝜋 • 𝑓 𝑡𝑎𝑛𝑘 ) 2 • 𝐿 𝑆 ) (6.4)
Equation ( 6.3) is optional, but simplifies the design task by relating 𝐶 𝑆 to any implemented spiral design through its 𝑓 𝑡𝑎𝑛𝑘 . Another possible way could be to execute multiple 3D EM simulations and extract 𝐶 𝑆 for each spiral inductor winding turns. This will result in discrete values for 𝐶 𝑆 instead of continuous ones as provided by the use of equations (6.3) and (6.4).

After having modeled the 𝐿 𝑆 -𝐶 𝑆 tank, the bias-tee circuit design can now begin as follows. As stated previously, the proposed idea for wideband performance is to place the resonance frequency of the overall bias-tee (𝑓 𝑟𝑒𝑠 𝐵𝑖𝑎𝑠-𝑇𝑒𝑒 ) at most at the targeted 𝐹 𝑙𝑜𝑤𝑒𝑟 of the device. Since we will deal with an 𝐹 𝑙𝑜𝑤𝑒𝑟 of 5 GHz, both 𝐶 𝑎 and 𝐶 are set to 2 pF to insure enough AC-ground while not reserving too much area when being implemented as close as possible to the DA stage. Resistance 𝑅 is set to 50 Ω that represents the DA 𝑅 3 termination resistor, as already mentioned at the beginning of this subsection. By sweeping 𝐿 𝑆 from 1-nH up to 10-nH, the input reactance against frequency can thus be calculated from equation (6.2b) and for each 𝐿 𝑆 -value, 𝑓 𝑟𝑒𝑠 𝐵𝑖𝑎𝑠-𝑇𝑒𝑒 corresponds to when 𝑋 𝑖𝑛 ′ (𝜔 𝑟𝑒𝑠 𝐵𝑖𝑎𝑠-𝑇𝑒𝑒 ) = 0 Ω. Figure 6.3 summarizes those values of 𝑓 𝑟𝑒𝑠 𝐵𝑖𝑎𝑠-𝑇𝑒𝑒 with respect to 𝐿 𝑆 . One can observe that a minimum of 5.6 nH is needed for a resonance frequency of the bias-tee below 5 GHz. We decide to choose a slightly higher 6-nH inductance to be cautious against process variation. is acting as a negative reactance for 𝐿 𝑆 ≥ 5.6 nH proving, therefore, when used with the DA later on, that its passband will experience an equivalent capacitive behavior with small magnitude. In order to obtain wideband low input reactance up to the intended 𝐹 𝑢𝑝𝑝𝑒𝑟 , for better port matching purposes, and since the negative part of the reactance is quite small, it can be compensated at higher frequencies by simply adding a low-value inductor, 𝐿 𝑒 . By doing so, one arrives at the complete bias-tee of Figure 6.1, providing an input impedance 𝑍 𝑖𝑛 , described by equation (6.5).

𝑍 𝑖𝑛 = 𝑍 𝑖𝑛 ′ + 𝑗𝜔𝐿 𝑒 = 𝑅 𝑖𝑛 ′ ≈ 𝑅 (6.5) The effective input resistance 𝑅 𝑖𝑛 ′ is observed to decrease against frequency as a consequence of using 𝐶 𝑆 , as indicated by (6.2a) and (6.2d). A deducible solution would be to increase 𝑅 so that the average of 𝑅 𝑖𝑛 becomes 50 Ω. However, based on the refine handtuning performed at the end of the design process with the previous single-stage DA implemented in Chapter 5, the resistor 𝑅 was left here untouched until the end process before sending the cascaded DA to fabrication. Table 6.3 summarizes the required design parameter determined previously and needed to implement such bias-tee suitable to cover the passband of a DA amplifying from 5-GHz up to 100 GHz. In the next part of this subsection, simulation and measurements of the implemented bias-tee as a standalone device are presented.

.5 illustrates a 3D view of the implemented bias-tee that represents the electrical model of Figure 6.1. The 𝐿 𝑆 -𝐶 𝑆 tank with 𝐿 𝑆 of 6 nH and 𝐶 𝑆 of 27.6 fF was implemented as a microstrip spiral inductor covering a surface area of 82 µm x 82 µm with the minimum spacing allowed by the DRM of 0.6 µm between metallic windings to conserve area. The 39-pH inductor 𝐿 𝑒 is implemented using µ-TL of 50-µm in length. Both 2-pF shunt capacitors, 𝐶 𝑎 and 𝐶, where implemented using SPP-topology introduced in Chapter 5 [START_REF] El-Chaar | Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave Systems in Low-Cost Highly Integrated CMOS Technologies[END_REF] since this high-quality capacitor topology demonstrated to be the most suitable for such applications at mm-wave band Figure 6.6 compares the simulated and de-embedded measured results. The simulation was performed on ANSYS 3D EM simulator HFSS. The discrepancy at frequencies below 6 GHz is attributed to the lower limit of TRL defined by the 630-μm line (Figure 5.8). A slight shift exits at lower frequencies, which could be caused by a slightly higher inductance than the anticipated 𝐿 𝑆 of 6 nH. In overall, great agreement is obtained between both results validating the design process and concept. The proposed bias-tee is capable of delivering an RF-choke bandwidth of around 100 GHz since isolation between DC-and RF-port is ≤ -20 dB up to 100 GHz (the intended 𝐹 𝑢𝑝𝑝𝑒𝑟 of the DA). As additional note, referring back to Figure 6.2, the price of such a bias-tee is a small DC resistance of about 6.3 Ω. It is considered an attractive property for such a wideband performance since it will lead to a smaller DC-power overhead compared to using a resistor-based bias-tee, for instance, that provides similar wideband performance but for a much higher DC-power overhead. Up to now, the new bias-tee topology was discussed and its design concept was validated through measuring a 100-GHz standalone device version of it. In the next subsection, the layout implementation of single stage DA, of Section 6.1, with such bias-tee is presented.

100-GHz Single-Stage DA: Layout and Microphotograph

All the needed components to implement the six unit-cells single-stage DA piece of the complete cascaded DA are now available. Figure 6.7 presents the final electrical schematic diagram of our loss-compensated single-stage 6-unit cells CMOS-based DA of 7.7-dB amplification and Figure 6.8 its microphotograph. Table 6.4 summarizes all of its design parameters. All TL are implemented using thickest metal available in technology, M8, with same width of 1 µm, as explained in Chapter 5, subsection 5.3.1. The μ-TL segments are done with length 𝑙 2 ⁄ of 125 μm. Both 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 are implemented with length of 54 μm and 155 μm, respectively. Both termination impedances 𝑍 3 and 𝑍 4 are realized as series RC loads. Both 𝑅 3 and 𝑅 4 are implemented using technology component as N+ silicided polysilicon resistors, and were AC-grounded through a 2-pF bypass SPP capacitor (both 𝐶 3 and 𝐶 4 ) which will lead to a DA passband starting from 5 GHz while being compact in area. Supply voltage for the drain pin of each M2 FET is provided through the newly proposed integrated bias-tee topology (Figure 6.5) connected to the output loaded-line of the singlestage DA. The biasing of all gate pins is provided through resistive RF-choke implemented using high-resistivity polysilicon resistor (𝑅 𝑔 ) of 10-kΩ. This is possible since we are dealing with FET and hence there is no impact on overall 𝑃 𝐷𝐶 . A 600-fF decoupling SPP capacitor (𝐶 𝑔 ) was added on each 𝐿 𝑔 terminal pin facing the DC pads for AC-grounding.

Six-Stage Cascaded 100-GHz DA Layout and Microphotograph

The final design step remaining is to realize the cascaded DA. In order to obtain 46.2 dB of gain, the single-stage DA of Figure 6.8 is cascaded six times (𝑀 = 6). Figure 6.9 demonstrates the final layout of the implemented cascaded DA. The core area of the DA is 2.3 mm 2 and the total area is 3.5 mm 2 including pads. To prevent biasing interference between consecutive DAs where the drain-line of a preceding DA is connected to the gate-line of the subsequent DA, a 2-pF MOM capacitor was added in series as a DC-decoupling capacitor. Series DC-decoupling capacitors were also added at both the input and output sides of the cascaded DA to prevent any influence from VNA RF-probes on the biasing point of both first and sixth single-stage DAs, respectively. Due to high gain delivered by the integrated amplifier, any influence from the outside word -in this case external biasing equipment-can interfere with the behavior of the DA and could render it unstable. For that reason, 400-pF AC-grounded capacitor was added on each side of the DA on DC-pad that provides 𝑉 𝑑𝑑 to filter any incoming low-frequency noise. Wovenstructure MOM capacitors, already available in the PDK, were used for both roles (DCdecoupling and AC-grounding on DC-pads) due to its capability in providing high capacitance density per unit area, hence considered advantageous for not wasting additional silicon area. Finally, GSG-type pads with 50-μm pitch are connected to the cascaded DA input and output RF-ports. After finishing the design layout implementation and before sending to fabrication, one last simulation (as a validation step) was performed on ADS schematic to make sure that everything is in order. Termination resistor 𝑅 3 was hand-tuned to 57 Ω while taking into consideration the resistive drop caused by the implemented bias-tee (Figure 6.4) and fixing any slight imperfection in midband gain-drop to preserve precisely the 3-dB limit. Concerning resistor 𝑅 4 , it was left at 53.5 Ω since this part is similar to the one used in the implementation of single-stage DA of Chapter 5 without a bias-tee.

In the next Section 6.3, the performance analysis of the presented cascaded CMOSbased DA is discussed.

THz GBP Cascaded CMOS DA: Simulation Results

In this section, simulation results of the amplifier device are presented. Measurements were not possible to provide at that time due to silicon wafer still being in the fabrication stage. The 𝑆-parameter analysis of the cascaded DA are first discussed. Then, performance analysis is performed from stability and group delay analysis. Regarding power capability analysis from P1dB, P sat and IP3, they are not possible to simulate due to insufficient processing resources when performing large-signal harmonic balance simulation on ADS of such a DA with great deal of non-linear components. A comparison with state-of-the-art DAs is performed in the next Section 6.4.

𝑺-parameter Analysis

.10 illustrates the simulated 𝑆-parameter results versus frequency for the cascaded DA. While the design process was performed using the simulation capability of our 𝐴𝐵𝐶𝐷-model on MATLAB, however, the final simulation of the complete cascaded DA device is performed on ADS software. This is due to some design blocks, such as biastee, being added as touchstone files (.s2p) whereas our DA model does not possess such functionality. Biased at 𝑉 dd =1.5 V instead of 1.2 V, to compensate for the bias-tee self-resistance, each single-stage DA consumes 27 mA and the overall cascaded DA consumes a total of 162 mA. This results in a 𝑃 𝐷𝐶 of 40.5 mW and 243 mW, respectively. The DA achieves an average insertion gain 𝑆 21 of 45.3 dB with in-band ripple of ±3 dB and, hence, a coverage range from 𝐹 𝑙𝑜𝑤𝑒𝑟 of 5 GHz up to an 𝐹 𝑢𝑝𝑝𝑒𝑟 of 100 GHz. This gives an amplified passband BW of 95 GHz and leads to a GBP of 17.5 THz. Due to bias-tee power overhead and the DA starting from 5 GHz instead of DC-level, the new 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit is found to be 71.96 GHz/mW. Both input and output matching levels, S 11 and 𝑆 22 , respectively, are better than -10 dB starting from 5 GHz up to 100 GHz. The reverse isolation S 12 reaches a maximum of -93 dB at 100 GHz. This high isolation can be explained from using cascode topology as Gm-cell for the unit cells and since we are cascading single-stage DAs 𝑀times, the overall reverse isolation is also multiplied by the number of cascaded stages the same way as the overall gain is.

Group Delay Performance Analysis

Stability Performance Analysis

The cascaded DA 𝑘and |𝛥|-factor derived from simulation can be seen in Figure 6.12. It is unconditionally stable for the whole passband. This DA demonstrates 𝑘-values ≥ 100 and |𝛥|-values ≤ 0.1. This high stability is attributed to the device S 12 being interestingly very low, as illustrated in Figure 6.10, compared to single-stage DA of Chapter 5 (Figure 5.21(a)). The decline of both 𝑘and |𝛥|-factors as frequency increases is due to the same reason of S 12 increasing until -93 dB at 100 GHz.

Comparison with State-of-the-Art DAs Performances

In Chapter 2, a comparison between state-of-the-art DA performances in different process nodes and technologies was introduced. In order to highlight that it is possible using CMOS technologies to obtain high gains with UWB performances reaching frequencies as high as 100 GHz, since the former is usually considered as a weak technology due to its low transconductance, the characterized cascaded DA is mentioned with all the different DAs of Table 2.2. This performance comparison is summarized in Table 6.5 (next page).

It is observed that for a comparable bandwidth, our DA demonstrated to offer the highest gain recorded while being power efficient, hence possessing the highest 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ between the stated DAs. In addition, even though our cascaded DA reserves a relatively higher total area of 3.5 mm 2 ; however, a comparison between all 𝐺𝐵𝑃 (𝑃 𝐷𝐶 • 𝐴𝑟𝑒𝑎) ⁄ values shows that our DA contributed to the highest one. This indicates an efficient usage of per silicon area to deliver the stated 45.3 dB of gain and re-validates once more the ability our model can give us in squeezing the most from each deign component the DA is made from to maximize the latter gain performance.

Through this performance comparison, we can conclude that while it is true what is said that CMOS technology do provide low transconductance compared to the other mentioned process technologies; however, with adequate and proper choice of optimum design parameters provided thanks to our model, CMOS technologies can be aided even more in proving their abilities in mm-wave circuit design applications. & BWs are reported as declared by authors. £ Ripple limits is determined within the authors declared BW for their reported gain % Estimated from plots @ Cascaded Multi-stage DA (CMSDA) $ Cascaded single-stage DA (CSSDA) # Flip-Chip DA $ Simulated performances * Biased using external bias-tee ** Biased using integrated bias-tee

Conclusion

Through this chapter, a 45.3-dB cascaded DA using ST 55-nm CMOS technology was introduced. Results demonstrated the highest 𝐺𝐵𝑃 and 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ characteristics of 17.5 THz and 71.96 GHz/mW, respectively. The highest recorded FoMs in the literatures. Owing to the proposed 𝐴𝐵𝐶𝐷-matrix based model and through the provided design methodology in Chapter 4, the optimum design parameters were able to be determined in order to provide the highest gain per DA-stage possible while being power efficient.

Throughout this chapter, a bias-tee topology with UWB performance was also introduced where it is based on a newly proposed technique for pushing the resonance below the lower-end of the wide passband compared to the traditional way of pushing it towards the higher-end of the wide passband. The latter becomes quite difficult especially if we are speaking about futuristic BWs ≥ 100GHz. Our proposed bias-tee showed to be efficient in power-consumption where it demonstrated lower power-overhead compared to resistive-based bias-tee and simpler in designing compared to the conventional inductivebased bias-tee since parasitic capacitance was part of the design instead of a component suffering from it. As a proof-of-concept, the proposed topology was designed for the intended DA and was characterized as a standalone device, which showed its capability in providing RF-choke functionality reaching 100 GHz of bandwidth.

Chapter 7

General Conclusion

In this thesis, we contributed in improving the design process of mm-wave distributed amplifier in integrated circuits. We did so by focusing on various aspects of its design requirements as follows. 1) Proposing a reliable and versatile design model that represents the distributed amplifier complete frequency behavior, offering the possibility for scriptingbased design technique. 2) Providing an algorithmic methodology that can be used in the framework of automated designing to explore the wide space of possible distributed amplifier solutions a given process technology can offer. In addition, 3) proposing integrated passive components specifically designed to address the issue of wideband ACgrounding and device biasing. Our efforts have been validated by using STMicroelectronics 55-nm process as a technology to explore from and discover the feasible CMOS DAs and, by the end, arrive at implementing a single-stage and cascaded CMOS DA options that amplify frequencies up to 100 GHz and demonstrate global optimum performances.

First, different DA design techniques were investigated from mathematical-based approaches, to artificial intelligence-based techniques such as neural-network and through schematic-level design environments using CAD tools; however, each technique presented its own weakness. It ranged from the assumption of a continuous loaded-lines structure, which restricts the highest frequency of operation where the model can still be considered valid. The assumption of a simple unilateral Gm-cell AC equivalent circuit, where in reality a more complex representation is needed when dealing with high frequencies since parasitic become dominant. In addition, when speaking especially of mm-wave frequency bands, loss-compensated Gm-cells become necessary to be adopted in order to mitigate the parasitic losses and provide amplification at those bands, but they introduce extra design variables. This complicates the circuit design process where more variables, besides the one of the DA, needs to be taken into consideration. Depending on the Gm-cell topology chosen by the designer, those variables can change between one DA to another which highlights, therefore, the need for a general DA model. The most preferred design technique is often determined to be through CAD environments, such as Keysight ADS or Virtuoso Cadence software. For CAD environments where only schematics diagram simulation is provided, the DA is drawn first and as a second step, optimization is applied until a specific performance goal is achieved. This technique lacks the capability to optimize the number of unit-cells (𝑁) which falls on the designer task to manually do it and, consequently, perform re-optimization per 𝑁 changement. Since the DA structure has several degrees of freedom, a large volume of simulation work is necessary for a specific topology and goal, hence affecting the simplicity of such design process. For CAD environments where scripting capabilities are provided, this optimization process can be made easier through automation, however, of course, whatever the scripting language used, this requires first having at hand a proper physical model. On those basis, a matrix-based design model based on 𝐴𝐵𝐶𝐷 parameters, famously used in describing passive circuitry, was introduced that does not employ restrictions on any kind of design parameter, that considers a complete and general Gm-cell representation, and that offers the possibility to consider all design parameters as possible tunable variables, including 𝑁. Efforts were dedicated on providing a model for successful implementation of CAutoD process for DAs through scripting.

Secondly and as a practical example, the basic principle-of-operation of a losscompensated DA was presented as a topology that can aid in the possibility to extend the amplification passband response deep into the mm-wave frequency range. Based on its concept, a systematic algorithmic methodology, with the help of the 𝐴𝐵𝐶𝐷-based model, was offered that maximizes passband for any combination of unit cells and transistor size. As a result, its outcome was 3D DSE plots that offer the designer an interesting graphical overview of the possible tradeoffs between all the design characteristics of interest (in this case gain, bandwidth and P DC ). Our CAutoD method also provided the optimal and accurate dimensions needed for design parameters set such as transistor width, 𝑁, TL segments length, and, in this particular case of loss-compensated cascode, the inductive-type elements 𝐿 𝑔 and 𝐿 𝑑𝑠 , to synthesize the suitable design option.

Finally, two CMOS-based DAs using ST 55-nm process were designed and implemented for on-wafer characterization. The first amplifier was a single-stage 100-GHz bandwidth DA that demonstrated high 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ that served for model validation purposes. The second amplifier was a cascaded 100-GHz bandwidth DA that demonstrated 17.5 THz 𝐺𝐵𝑃 and 71.96 GHz/mW 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merits, the highest recorded characteristics compared to the state-of-the-art literature. During the design process, two new design components were introduced that can contribute in synthesizing high quality and broadband mm-wave ICs. The first component was an AC-ground capacitor that offers the highest 𝑆𝑅𝐹and 𝑄merit while providing large capacitance values at high frequency range. For instance, for a 300-fF capacitance, an 𝑆𝑅𝐹 of 368 GHz and 𝑄-value of 14.7 at 100 GHz were obtained. The second component being a new bias-tee topology based on the idea of benefiting from the parasitic and pushing below its SRF below the lower-end operating frequency of the DA. The latter demonstrated promising wideband performance reaching 100 GHz.

Through our work, we prevision that by the usage of our model and method we could assist analog designers in their future design process where it facilitates the alternation between layout-and design-stages where more focus can be dedicated on layout and the challenges it brings to mm-wave circuitry, and proposing enhanced components, as was done here. In addition, to give the opportunity to discover the optimality a given technology node can yield, and explore and suggest enhancements that can break the limits and further advance the performance of future mm-wave distributed amplifiers.

Figure 2 . 1 :

 21 Figure 2.1: Global (a) growth of connected devices and (b) mobile data traffic in exabyte (10 9gigabytes) per month, from 2017 to 2022.[START_REF]Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2017-2022[END_REF]

Figure 2 . 4 :Figure 2 . 5 :

 2425 Figure 2.4: Single-transistor amplifier topology. (a) Schematic circuit diagram.(b) Microphotograph.[START_REF] Ko | A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines[END_REF]

Figure 2 . 6 :Figure 2 . 7 :

 2627 Figure 2.6: Resistive-feedback amplifier topology. (a) Schematic circuit diagram.(b) Microphotograph.[START_REF] Park | A very low power SiGe LNA for UWB application[END_REF]

Figure 2 . 8 :Figure 2 . 9 :

 2829 Figure 2.8: Cascode amplifier topology. (a) Schematic circuit diagram. (b) Microphotograph.[START_REF] Sananes | 52-75 GHz wideband low-noise amplifier in 90 nm CMOS technology[END_REF]

Figure 2 . 10 :Figure 2 . 11 :

 210211 Figure 2.10: Balanced amplifier topology. (a) Schematic circuit diagram. (b) Microphotograph.[27]

Figure 2 . 12 :Figure 2 . 13 :

 212213 Figure 2.12: Transformer-coupled amplifier topology. (a) Schematic circuit diagram.(b) Microphotograph.[START_REF] Arbabian | A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna[END_REF]

Figure 2 . 14 :Figure 2 . 15 :

 214215 Figure 2.14: Distributed amplifier topology. (a) Schematic circuit diagram. (b)Microphotograph.[START_REF] El-Aassar | A Compact pMOS Stacked-SOI Distributed Power Amplifier With Over 100-GHz Bandwidth and Up to 22-dBm Saturated Output Power[END_REF]

Figure 2 . 16 :

 216 Figure 2.16: Thermionic valve circuit -William S. Percival's 1936 patent.[START_REF]Thermionic Valve Circuits[END_REF]

Figure 2 . 17 :

 217 Figure 2.17: First schematic diagram of distributed amplifier using vacuum tubes from 1948.[38]

Figure 2 . 18 :

 218 Figure 2.18: Conventional distributed amplifier made of 𝑁 unit cells.

Figure 2 . 19 :

 219 Figure 2.19: Simplified equivalent-circuit representation of a FET-based distributed amplifier.

Figure 2 . 20 :

 220 Figure 2.20: Six unit-cells 90-nm Si CMOS-based distributed amplifier. (a) Schematic diagram. (b) Microphotograph. [30]

Figure 2 .

 2 Figure 2.21: Measured 𝑆-parameters of the 90-nm Si CMOS-based distributed amplifier. [30]

Figure 2 .

 2 22(a) shows the schematic diagram of the device and Figure2.22(b) shows its microphotograph for onwafer characterization. The fabricated circuit occupies a chip area of 0.5 ⨉ 0.8 mm 2 including pads. The Gm-cell adopted is based on a cascode topology with a two-transistor configuration and the inductive-type segments are conventional microstrip lines.

Figure 2 . 22 :

 222 Figure 2.22: Three unit-cells 45-nm SOI-based distributed amplifier. (a) Schematic diagram.(b) Microphotograph.[START_REF] Kim | A 92 GHz Bandwidth Distributed Amplifier in a 45 nm SOI CMOS Technology[END_REF]

Figure 2 .

 2 Figure 2.23: Measured (solid lines) and simulated (dotted lines) 𝑆-parameters of the 90-nm SiCMOS-based distributed amplifier.[START_REF] Kim | A 92 GHz Bandwidth Distributed Amplifier in a 45 nm SOI CMOS Technology[END_REF]

Figure 2 .

 2 24(a) shows the schematic diagram of the device and Figure2.24(b)

Figure 2 . 24 :

 224 Figure 2.24: Eleven unit-cells 22-nm FD-SOI-based distributed amplifier. (a) Schematic diagram. (b) Microphotograph. [32]

Figure 2 . 25 :

 225 Figure 2.25: Simulated and measured 𝑆-parameters of 22-nm FD-SOI-based distributedamplifier.[START_REF] Testa | 110 GHz travelling-wave amplifier in 22 nm FD-SOI CMOS[END_REF]

Figure 2 .

 2 26(a) shows the schematic circuit diagram of the DA. The cascode topology with a two-transistor configuration and conventional µ-TL line for the inductive segments were adopted as unit-cell Gm-cell.

Figure 2 .

 2 26(b) shows the microphotograph of the fabricated chip of 1-157 GHz DA. It consists of eleven unit cells and the die size is about 1 ⨉ 2.2 mm 2 including pads.

Figure 2 . 26 :Figure 2 . 27 :

 226227 Figure 2.26: Eleven unit-cells 100-nm InP-based distributed amplifier. (a) Schematic diagram.(b) Microphotograph of the 1-157-GHz version.[START_REF]112-GHz, 157-GHz, and 180-GHz InP HEMT traveling-wave amplifiers[END_REF]

Figure 2 .

 2 28(a) illustrates the schematic circuit diagram. The Gm-cell adopted was based on cascode topology with a two-transistor configuration and conventional µ-TL line was used for the inductive-type segments.

Figure 2 .Figure 2 . 28 :

 2228 Figure 2.28: Eight unit-cells 50-nm InGaAs-based distributed amplifier. (a) Schematic diagram. (b) Microphotograph. [34]

Figure 2 . 29 :

 229 Figure 2.29: Measured 𝑆-parameters of 50-nm InGaAs-based distributed amplifier.[START_REF] Zech | An ultra-broadband low-noise traveling-wave amplifier based on 50nm InGaAs mHEMT technology[END_REF]

Figure 2 .

 2 30(a) andFigure 2.30(b) illustrate the schematic circuit diagram and the microphotograph of the implemented DA. The chip occupies an area of 0.85 ⨉ 0.45 mm 2 including pads.

Figure 2 . 30 :

 230 Figure 2.30: Five unit-cells 130-nm SiGe-based distributed amplifier. (a) Schematic diagram.(b) Microphotograph.[START_REF] Testa | 170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier[END_REF]

Figure 2 . 31 :

 231 Figure 2.31: Simulated and measured 𝑆-parameters of 130-nm SiGe-based distributedamplifier.[START_REF] Testa | 170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier[END_REF]

Figure 2 .

 2 32(a) andFigure 2.32(b) illustrate the schematic circuit diagram and the microphotograph of the implemented DA. The chip occupies an area of 0.546 ⨉ 0.602 mm 2 including pads.

Figure 2 . 32 :

 232 Figure 2.32: Four unit-cells 250-nm InP-based distributed amplifier (a) schematic diagram and(b) microphotograph.[START_REF] Yoon | A Fully-Integrated 40-222 GHz InP HBT Distributed Amplifier[END_REF]

Figure 2 . 33 :

 233 Figure 2.33: Simulated and measured 𝑆-parameters of 250-nm InP-based distributed amplifier.[36]

Figure 3 . 1 :

 31 Figure 3.1: Experimental performance of a 0.1-mm GaAs node distributed amplifier at 2-14 GHz frequency range. [40]

Figure 3 . 2 :

 32 Figure 3.2: Schematic diagram of the stage-scaled distributed amplifier. [51]

Figure 3 . 3 :

 33 Figure 3.3: Equivalent circuit of the output loaded-line side of the n th unit cell. [52]

Figure 3 . 4 :

 34 Figure 3.4: Distributed amplifier output loaded-line equivalent circuit representation. [52]

Figure 3 . 5 :

 35 Figure 3.5: Distributed amplifier input loaded-line equivalent circuit representation. [52]

Figure 3 . 6 :

 36 Figure 3.6: Simplified representation of an artificial neural network

Figure 3 . 7 :

 37 Figure 3.7: ADS schematic view of a distributed amplifier being optimized to satisfy a defined gain response goal.

Figure 3 . 8 :

 38 Figure 3.8: Four-port equivalent network for a unit cell.

Figure 4 . 1 :

 41 Figure 4.1: Schematic circuit of the proposed loss-compensated distributed amplifier. [50]

Figure 4 . 2 :Figure 4 . 3 :

 4243 Figure 4.2: Measured 𝑆-parameters of the loss-compensated DA IC with eight unit-cells. [50]

Figure 4 . 4 :

 44 Figure 4.4: Attenuation constants of the conventional DA without loss-compensation technique.

Figure 4 . 5 :

 45 Figure 4.5: Influence of loss-compensating inductor 𝐿 𝑔 on (a) gate-line attenuation constant (𝛼 𝑔 ) and (b) drain-line attenuation constant (𝛼 𝑑 ).

Figure 4 . 6 :

 46 Figure 4.6: Influence of loss-compensating inductor 𝐿 𝑑𝑠 on (a) gate-line attenuation constant (𝛼 𝑔 ) and drain-line attenuation constant (𝛼 𝑑 ).

Figure 4 . 7 :

 47 Figure 4.7: Total attenuation constant (𝛼 𝑇𝑜𝑡𝑎𝑙 ) behavior with and without loss-compensation technique.

Figure 4 . 8 :

 48 Figure 4.8: Non-loss compensated cascode gm-cell: (a) symbolic representation and (b) simplified AC-equivalent circuit.

Figure 4 . 9 :

 49 Figure 4.9: Loss compensated cascode gm-cell: (a) symbolic representation and (b) simplified AC-equivalent model.

Figure 4 . 10 :

 410 Figure 4.10: Flow diagram for converting the loss-compensated cascode Gm-cell into a 𝑌matrix representation.

Figure 4 . 11 :

 411 Figure 4.11: 𝑆 21 response versus frequency when 𝐿 𝑑𝑠 = 0 pH and 𝐿 𝑔 increases.

  Figure 4.5.

Figure 4 . 12 :

 412 Figure 4.12: 𝑆 21 response versus frequency when 𝐿 𝑑𝑠 increases and 𝐿 𝑔 =40 pH.

Figure 4 . 13 :

 413 Figure 4.13: 𝑆 21 response versus frequency when 𝐿 𝑑𝑠 and 𝐿 𝑔 are tuned to maintain simultaneously the extended bandwidth of 100 GHz and 1-dB mid-band gain drop at 50 GHz.

Figure

  Figure 4.12 also highlights an undesirable behavior: increasing 𝐿 𝑑𝑠 has an influence on the level of peaking produced from 𝐿 𝑔 where it increases it even further and on the position of its gain-peaking frequency where it shifts it towards lower spectrum. To fix it, 𝐿 𝑔 and 𝐿 𝑑𝑠 must simultaneously be decreased and increased, respectively, to maintain the desired midband drop (1-dB) while conserving the acquired high frequency component (100 GHz), as demonstrated in Figure4.13. Indeed, it is observed that through the usage of 𝐿 𝑔 and 𝐿 𝑑𝑠 , one can extend the BW while flattening the passband gain-ripple

Figure 4 . 14 :

 414 Figure 4.14: Flowchart presenting our DA CAutoD procedure using proposed DA and losscompensated cascode models.

  Subsection 4.3.1 covers the three DSE plots that represent parameter of interest from gain, bandwidth and 𝑃 𝐷𝐶 . Subsection 4.3.2 covers the remaining DSE plots that represent the required designvariables from µ-TL segments length and compensation µ-TL-type inductors 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 lengths. 4.3.1 DA Design Parameters: Gain, Bandwidth and 𝐏 𝐃𝐂

Figure 4 .

 4 Figure 4.15 illustrates the variation of DA gain against 𝑊 𝐶𝑆 and 𝑁. One can observe that when either of those two parameters increase, the overall DA gain increases.

Figure 4 .

 4 Figure 4.15: 3D DSE plot showing possible DA gain with respect to 𝑊 𝐶𝑆 and 𝑁.

Figure 4 .

 4 Figure 4.16: 3D DSE plot showing possible DA 1-dB bandwidths with respect to 𝑊 𝐶𝑆 and 𝑁.

Figure 4 .

 4 Figure 4.16 illustrates the variation of DA bandwidth against 𝑊 𝐶𝑆 and 𝑁.It highlights that for each 𝑁 there is a maximum BW attainable that is wider for smaller 𝑊 𝐶𝑆 sizes; however, until a certain limit where even smaller sizes lead to smaller BWs. This could be explained by the inability of smaller transistors from providing enough gain to compensate for important losses at high mm-wave regions. Therefore, this pushed both 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 to be increased even more to elevate the gain at 𝐹 𝑢𝑝𝑝𝑒𝑟 towards the same level of gain at 𝐹 𝑙𝑜𝑤𝑒𝑟 while maintaining the 1-dB mid-band gain drop constraint. As already discussed in Section 4.1 (subsection 4.1.2), this leads to shrinkage of BW where excessive increase of either compensation inductors leads to shift of loaded-lines cut-off frequencies towards lower frequencies.

Figure 4 .

 4 Figure 4.17: 3D DSE plot showing possible DA P DC with respect to 𝑊 𝐶𝑆 and 𝑁.

Figure 4

 4 Figure 4.17 illustrates the variation of DA power consumption against 𝑊 𝐶𝑆 and 𝑁. It shows that a DA constituting of more Gm-cells, i.e., larger 𝑁, leads to higher 𝑃 𝐷𝐶 . The same applies for having a DA made from larger transistors. The highest consumption, hence, would be the design in which the DA is synthesized with both big transistors and large 𝑁 at the same time. One reason for this design point could be for delivering larger gain. For instance, from Figure4.17, choosing a DA made from 𝑁 = 9 with 𝑊 𝐶𝑆 = 40 µm leads to 70 mW of power consumption but with a high gain close to 12 dB; however, from Figure4.16, this choice would restrict the design to a passband of only 80 GHz.

  Figure 4.18. Those parameters (length of segments, 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 ) are plotted independently with respect to 𝑊 𝐶𝑆 and 𝑁, as shown in Figure 4.19 and Figure 4.20.

Figure 4 . 18 :

 418 Figure 4.18: Schematics of DA unit cell with loss-compensated cascode Gm-cell.

Figure 4 .

 4 Figure 4.19 presents the length needed for µ-TL segments (𝑙 2⁄ ) needed for obtaining a DA with reference impedance (𝑍 0 ) around 50 Ohms. It is noticeable that when the size of transistor increases, the length of segments increases. It is interesting to note the linear dependence of segments length against 𝑊 𝐶𝑆 . This is consistent with loaded lines characteristic impedance equation (2.2) and (2.4) discussed in Chapter 2, which states that inductance of segments must increase when the Gm-cell input and output capacitances are increased in order to maintain a required DA characteristic impedance. We remind here that the length of the µ-TL segments is determined by setting 𝑁 =1, what explains a 2D plot.

Figure 4 .

 4 Figure 4.19: DA 2D DSE plot showing μ-TL segments lengths to achieve widest matching BW for ‖𝑆 11𝑚𝑎𝑥 ‖ = ‖𝑆 22𝑚𝑎𝑥 ‖ = -10 dB

Figure 4 . 20 :

 420 Figure 4.20: 3D DSE plot showing possible lengths for (a) shunt µ-TL (𝑇𝐿 𝐿𝑔 ) and (b) series µ-TL (𝑇𝐿 𝐿𝑑𝑠 ), with respect to 𝑊 𝐶𝑆 and 𝑁.

Figure 5 . 1 :

 51 Figure 5.1: (a) Simplified cross-section of metal stack and (b) transistor 𝐹 𝑡 and 𝐹 𝑚𝑎𝑥 as a function of drain current per unit gate width for nMOSFET available with ST eight-metal version 55-nm process.

Figure 5 . 2 :

 52 Figure 5.2: Insertion gain of thirty-five DA design options, with respect to 𝑁 and 𝑊 𝐶𝑆 , that offer 98 GHz ≤ 𝐵𝑊 ≤ 102 GHz.

Figure 5 . 3 :

 53 Figure 5.3: 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ merit of thirty-five DA design options, with respect to 𝑁 and 𝑊 𝐶𝑆 , that offer 98 GHz ≤ 𝐵𝑊 ≤ 102 GHz.

Figure 5 . 4 :

 54 Figure 5.4: Preliminary schematic diagram of the five unit-cells loss-compensated DA (biasing not shown). Both 𝐶 𝑠 and 𝐶 𝑔 are shunt capacitors to insure AC ground connections.

Figure 5 . 5 :

 55 Figure 5.5: (a) Isometric 3D view of the microstrip line. (b) Its attenuation constant when implementing a 76-pH inductor for different width and length.

Figure 5 .

 5 Figure 5.5(b)illustrates the attenuation constant (𝛼 𝑇𝐿 ) of the TL with respect to frequency for different widths ranging from 1 µm to 18 µm (limit imposed from PDK). For a fixed inductance of 76 pH, which represent the needed value to synthesize the unit cells segments, it is noticeable that the smaller the width, the lower 𝛼 𝑇𝐿 . It might seem that any µ-TL configuration has negligible loss impact; however, it must be noted that a DA is made of two inductive segments cascaded 𝑁 times, as evident in Figure2.18. This means that the input microwave signal will propagate through a total of 2⨉N physical segments, in other words it will experience 2•N times the losses, on both the loaded input and output lines of the DA. Therefore, having the smallest width for TL can benefit from having the smallest length that aid in reducing surface area of the DA when implemented and it contributes in lowering the overall losses of the DA.

Figure 5 .

 5 Figure 5.6(a) depicts the physical structure of a 300-fF SPP-SC synthesized within existing masks using the 8-metal version of 55-nm process and Figure 5.6(b) illustrates a symbolic view of its concept on how the process BEOL stack is used.

Figure 5 . 7 :

 57 Figure 5.7: Microphotograph of the fabricated 300-fF SPP-SC.

Figure 5 . 8 :

 58 Figure 5.8: Microphotograph of the fabricated Thru-Line-Reflect calibration kit.

Figure 5 . 9 :

 59 Figure 5.9: SPP-SC equivalent electrical model. (𝑅 0 , 𝐿 0 , 𝐶 0 ) represents intrinsic lumpedelements of the capacitor and (𝑅 𝑖𝑛 ,𝐶 𝑖𝑛 ) represents the measured input-impedance.

Figure 5 . 10 :

 510 Figure 5.10: Measured and HFSS EM-simulated equivalent input series-resistance (𝑅 𝑖𝑛 ) and capacitance (𝐶 𝑖𝑛 ) of de-embedded 300-fF SPP-SC. (Solid line: Measured. Dashed line: EM Simulated)

Figure 5 . 11 :

 511 Figure 5.11: Estimated SRF for 300-fF SPP-SC capacitor, extracted at 𝑄 = 0 through extrapolating the measured 𝑄-factor.

Figure 5 . 12 :

 512 Figure 5.12: Equivalent electrical model validation through 𝑆 11 parameter plot of 300-fF

Figure 5 . 13 :

 513 Figure 5.13: Cross section of a Metal 2/Metal 4 woven-structure MOM capacitor in 55-nm PDK

Figure 5 . 14 :

 514 Figure 5.14: Measured (a) equivalent input capacitance, and (b) equivalent input resistance and 𝑄-factor for 300-fF SPP-SC and woven-structure MOM capacitor in 55-nm process.

Figure 5 .

 5 Figure 5.15: Isometric 3D view of the interconnection used. (a) CG-FET. (b) CS-FET.

Figure 5 . 16 :

 516 Figure 5.16: Isometric 3D representation of a single unit cell with loss-compensated cascode as Gm-cell attached to a 600-fF AC grounded SPP capacitor 𝐶 𝑔 .

Figure 5 .

 5 18 (next page) presents the final electrical schematic diagram of our losscompensated CMOS-based DA. Table

  the gate pin of each M1 FET and the drain pin of each M2 FET are provided through RF-probes by the measurement setup. The gate pins of M2 FETs are biased together by an external bench power supply delivered from G-DC-G pads and through resistor-type RF-chokes (𝑅 𝑔 ) implemented using high-resistivity polysilicon resistor of 10-kΩ. This is possible since we are dealing with FET and hence there is no impact on overall 𝑃 𝐷𝐶 . A 600-fF decoupling SPP capacitor (𝐶 𝑔 ) was added on 𝐿 𝑔 terminal pin facing the DC pads for AC-grounding.Finally, GSG-type RF-pads with 50-μm pitch are connected to DA input and output ports. Both the final DA layout view and microphotograph are shown in Figure5.19 and Figure5.20, respectively. The DA presents a core are of 0.52 mm 2 and total area of 0.83 mm 2 including pads.

Figure 5 . 18 :

 518 Figure 5.18: Circuit schematic of the 5 unit-cells 100-GHz CMOS-based DA.

Figure 5 . 19 :

 519 Figure 5.19: Layout view of the implemented 5 unit-cells 100-GHz CMOS-based DA.

Figure 5 . 20 :

 520 Figure 5.20: Microphotograph of the fabricated 5 unit-cells 100-GHz CMOS-based DA in 55nm process for on-wafer characterization.

Figure 5 .

 5 Figure 5.21: Bias-tee simulated and measured isolation (𝑆 21 ) versus frequency between DCand RF-ports.

Figure 5 .

 5 Figure 5.22(a) and Figure 5.22(b) compare the 𝑆-parameter results versus frequency obtained from MATLAB-based 𝐴𝐵𝐶𝐷-model simulation, (3.14) with(3.17), to both ADSbased simulation and measurement of a single unit-cell and DA, respectively. Great agreement is obtained between ADS and 𝐴𝐵𝐶𝐷-model results. This indicates how reliable the proposed model is when used as design tool, this support the forth criterion. Unit-cell pads were de-embedded from measurements but the DA pads were not for a better representation of the latter behavior when used as standalone IC in real-world applications.

Figure 5 . 22 :

 522 Figure 5.22: 𝑆-parameters simulation and measurement results versus frequency. (a) Single unit cell. (b) DA.

Figure 5 . 23 :

 523 Figure 5.23: Group delay simulation and measurement results versus frequency. Simulations were performed on ADS software

  |S 12 S 21 | product which causes 𝑘-factor to degrade since 𝑘 = (1 -|S 11 | 2 -|S 22 | 2 + |𝛥| 2 ) (2|S 12 S 21 |) ⁄ [20].

Figure 5 .

 5 Figure 5.24: DA 𝑘and |𝛥|-factor versus frequency. Simulations were performed on ADS software.

Figure 5 .

 5 25 and Figure 5.26 are simulation-based results.

Figure 5 . 25 :

 525 Figure 5.25: Simulated output power and gain at 10 GHz, 60 GHz and 90 GHz

Figure 4 .

 4 20(a) and Figure 4.20(b), respectively.

Figure 6 . 1 :

 61 Figure 6.1: Lumped model representation of the proposed bias-tee topology

Figure 6 . 2 :

 62 Figure 6.2: Plot of 𝐿 𝑆 -𝐶 𝑆 tank 𝑓 𝑡𝑎𝑛𝑘 frequency and its DC self-resistance against different values of self-inductance (𝐿 𝑆 ).

Figure 6 . 3 :

 63 Figure 6.3: Plot of bias-tee overall resonance frequency against different values of selfinductance (𝐿 𝑆 ).

Figure 6 .

 6 Figure 6.4 shows the bias-tee 𝑋 𝑖𝑛 ′ variation with respect to frequency. Above 5 GHz, 𝑋 𝑖𝑛 ′

Figure 6 . 4 :

 64 Figure 6.4: Bias-tee equivalent input reactance (𝑋 𝑖𝑛 ′ ) versus frequency for different values of 𝐿 𝑆 .

Figure 6 . 5 :

 65 Figure 6.5: 3D isometric view of the implemented 100-GHz bandwidth bias-tee.

Figure 6 . 6 :

 66 Figure 6.6: Bias-tee simulated and measured isolation (𝑆 21 ) versus frequency between DC-and RF-ports.

Figure 6 . 7 :

 67 Figure 6.7: Circuit schematic of the 6 unit-cells 100-GHz CMOS-based DA with integrated bias-tee.

Figure 6 . 8 :

 68 Figure 6.8: Layout view of the implemented 6 unit-cells 100-GHz CMOS-based DA with integrated bias-tee.

Figure 6 . 9 :

 69 Figure 6.9: Layout view of the implemented 6-stage cascaded 100-GHz CMOS-based DA.

Figure 6 . 10 :

 610 Figure 6.10: 𝑆-parameter simulation results versus frequency of cascaded DA.

Figure 6 .

 6 Figure 6.11 shows the DA group-delay behavior besides its 𝑆 21 phase. The group delay experiences a flat variation inside passband up to 70 GHz and then increases quickly as it approaches 𝐹 𝑢𝑝𝑝𝑒𝑟 of 100 GHz (the cut-off frequency of the DA where sharp roll-off occurs). This is because amplifier S 21 phase is linear against frequency until 70 GHz and becomes non-linear as it approaches passband steep roll-off at higher frequency end.

Figure 6 . 11 :

 611 Figure 6.11: 𝑆-parameter simulation results versus frequency of cascaded DA.

Figure 6 .

 6 Figure 6.12: DA 𝑘and |𝛥|-factor versus frequency. Simulations were performed on ADS software.

TABLE 2 .

 2 1: PERFORMANCE COMPARISON BETWEEN WIDE BANDWIDTH AMPLIFIER TOPOLOGIES.

	Ref.	Amplifier Topology	Gain (dB)	Bandwidth (GHz)	𝐏 𝐃𝐂 (mW)	Chip Area (mm 2 )	GBP (GHz)
	[24]	Single Transistor (Cascaded)	10.8	5	5.5	0.39	17
	[25]	Resistive-feedback	13	10	9.6	0.88	45
	[26]	Cascode	14	23	32	0.22	115
			20	5	187.5	12.16	50
	[27]	Balanced	17	11	187.5	12.16	78
			22	20	187.5	8.6	252
	[28]	Transformer-Coupled	12.25	56	270	0.15	229
	[29]	Distributed	16	100	N/A	0.73	640

TABLE 2 .

 2 2: STATE-OF-THE-ART PERFORMANCES COMPARISON FOR DISTRIBUTED AMPLIFIERS

	Ref.	Process Techno.	Gain (dB)	Ripple £ (dB)	BW & (GHz)	Supply (V)	P DC (mW)	GBP (GHz)	𝑮𝑩𝑷 𝑷 𝑫𝑪 ( 𝑮𝑯𝒛 𝒎𝑾 )	Total Area (mm 2 )	GBP P DC • Area GHz mW • mm 2 ) (
		90-nm
	[30]	Si	7.4	-3 %	80	2.4*	120	188	1.57	0.72	2.18
		CMOS
		90-nm
	[41]	Si	7 @	+9 % ,-3	70	N/A	122	157	1.29	0.72	1.8
		CMOS
		90-nm
	[42]	digital	14 @	±1.5 %	73.5	1.2*	84	368	4.38	1.72	2.54
		CMOS
	[43]	40-nm digital CMOS	15 $	+5 % ,-3	80	(1, 1.7)**	90	450	5	0.31	16.13
		120-nm
	[44]	SOI	11	±1.2	85	2.5*	210	302	1.44	1.28	1.13
		CMOS
		120-nm
	[45]	SOI	7.8	±1.3	82	2.6*	130	201	1.55	1.05	1.47
		CMOS
		45-nm
	[31]	SOI	9	±1.5 %	92	1.2*	73.5	259	3.52	0.45	7.82
		CMOS
		22-nm
	[32]	FD-SOI	8.5	-3 %	110	2*	80	292	3.66	0.38	9.63
		CMOS
		130-nm
	[46]	InP	14.5 #	±0.7	94	3*	N/A	499	N/A	2.75	N/A
		HEMT
		100-nm
	[33]	InP	7	+2.5 %	111	N/A	N/A	248	N/A	2.2	N/A
		HEMT
		70-nm
	[47]	InP	21 @	±3 %	80	2**	300	898	3	2.47	1.21
		HEMT
		50-nm
	[34]	InGaAs	11	±1	105	6*	450	373	0.83	1.69	0.5
		mHEMT
		250-nm
	[48]	InP	12.8	+7 % ,-2 %	180	N/A	110	724	6.58	0.32	20.57
		HBT
		250-nm
	[36]	InP	10	-3	182	4*	105	575	5.47	0.33	16.57
		HBT
		130-nm
	[35]	SiGe	10	±2 %	170	3.6*	108	537	5	0.38	13.16
		HBT
		130-nm
	[49]	SiGe	24 @	+2.5 % ,-1 %	95	N/A	247	1506	6.09	0.65	9.37
		HBT

N/A = not available.

  𝜈 𝑐,𝑖 𝑅 𝑐𝑙,𝑖 𝐶 𝑜𝑢𝑡 𝑘 𝑁-𝑖 + 𝑍 𝑐,𝑖 𝐺 𝑜𝑢𝑡 𝑘 𝑁-𝑖 )

	=	1 2𝑙 𝑐,𝑖	𝜂 𝑐,𝑖 𝜂 𝑐,𝑖 ( 2 -1
			+ 𝑗𝜔√𝐿 𝑑,𝑖 (𝐶 𝑐𝑙,𝑖 +	𝐶 𝑜𝑢𝑡,𝑖 𝑙 𝑐,𝑖	)
				𝜂 𝑐,𝑖 =	𝑍 𝑐0,𝑖 𝑍 𝑐,𝑖	(3.1b)
			𝑍 𝑐0,𝑖 = √	𝑅 𝑐𝑙,𝑖 + 𝑗𝜔𝐿 𝑐𝑙,𝑖 𝐺 𝑐𝑙,𝑖 + 𝑗𝜔𝐶 𝑐𝑙,𝑖	≈ √	𝐿 𝑐𝑙,𝑖 𝐶 𝑐𝑙,𝑖	(3.1c)
			𝑍 𝑐,𝑖 ≈ √	𝐿 𝑐𝑙,𝑖 𝐶 𝑐𝑙,𝑖 + 𝐶 𝑜𝑢𝑡,𝑖 ⁄ 𝑙 𝑐,𝑖	(3.1d)

  3.3); 𝐼 𝑡𝑤 𝑛 = -𝐼 𝐷 𝑛 𝟋 𝑅 𝑛 + 𝐼 𝑜𝑢𝑡 𝑛-1 𝟋 𝑆 𝑛 𝑇 𝑑𝐿 𝑛 (3.3) where 𝟋 𝑅 𝑛 represents how much current generated by the n th current source, 𝐼 𝐷 𝑛 , is incident on the right TL, and is calculated from (3.4); 𝟋 𝑅 𝑛 = 𝑍 𝑅 𝐿𝑛 𝑅 𝑑𝑠 𝑛 (1 + 𝑗𝜔𝑅 𝑑𝑠 𝑛 𝐶 𝑑𝑠 𝑛 )𝑍 𝑅 𝐿𝑛 𝑍 𝐿 𝑅𝑛 + (𝑍 𝑅 𝐿𝑛 + 𝑍 𝐿 𝑅𝑛 )𝑅 𝑑𝑠 𝑛 (3.4)and 𝟋 𝑆 𝑛 represents the splitting current factor between the right part of the n th Gm-cell, just before the right TL (𝑍 𝑑𝑅 𝑛 , 𝛾 𝑑𝑅 𝑛 ), and the dissipated part in the transistor drain impedance, as given by (3.5);Finally, the term 𝑇 𝑑𝐿 𝑛 is the n th left µ-TL-type segment (𝑍 𝑑𝐿 𝑛 ,𝛾 𝑑𝐿 𝑛 ) transmission coefficient which takes into account the multiple reflections that occur at its boundaries. 𝑇 𝑑𝐿 𝑛 can be calculated using (3.6a) on the basis of Figure3.3;

	𝟋 𝑆 𝑛 =	𝑅 𝑑𝑠 𝑛 (1 + 𝑗𝜔𝑅 𝑑𝑠 𝑛 𝐶 𝑑𝑠 𝑛 )𝑍 𝐿 𝑅𝑛 + 𝑅 𝑑𝑠 𝑛	(3.5)
	𝑇 𝑑𝐿 𝑛 =	(1 + Г 𝑖𝑛 𝑑𝐿𝑛 )(1 + Г 𝑜𝑢𝑡 𝑑𝐿𝑛 )𝑒 -𝛾 𝑑 𝐿𝑛 𝑙 𝑑 𝐿𝑛 1 + Г 𝑖𝑛 𝑑𝐿𝑛 Г 𝑜𝑢𝑡 𝑑𝐿𝑛 𝑒 -2𝛾 𝑑 𝐿𝑛 𝑙 𝑑 𝐿𝑛	(3.6a)
			Г 𝑖𝑛 𝑑𝐿𝑛 =	𝑍 𝐿 𝐿𝑛 -𝑍 𝑑 𝐿𝑛 𝑍 𝐿 𝐿𝑛 + 𝑍 𝑑 𝐿𝑛	(3.6b)
			Г 𝑜𝑢𝑡 𝑑𝐿𝑛 =	𝑍 𝑑 𝐿𝑛 -𝑍 𝑅 𝐿𝑛 𝑍 𝑑 𝐿𝑛 + 𝑍 𝑅 𝐿𝑛	(3.6c)

  𝑍 𝑖𝑛 is the input impedance of the whole DA and 𝑅 𝑆 is the internal resistance of the signal source. The term 𝑇 𝑔𝐿 𝑖 (𝑇 𝑔𝑅 𝑖 ) is the transmission coefficient of the µ-TL-type segment (𝑍 𝑔 𝐿𝑛 ,𝛾 𝑔 𝑍 𝑅 𝑅𝑛 ) can be applied to input-loaded line segments input-impedances, the only difference lies in the Gm-cell inherent impedances where previously, for the output side, we were dealing with (𝑅 𝑑𝑠 𝑛 , 𝐶 𝑑𝑠 𝑛 ) in parallel and here, for the input side, we are dealing with (𝑅 𝑔 𝑛 , 𝐶 𝑔𝑠 𝑛 ) in series.

	𝑛 = 𝑉 𝑆 ( 𝑍 𝑖𝑛 + 𝑅 𝑆 𝑍 𝑖𝑛 𝑍 𝐿 𝐿𝑛 -𝑍 𝑔 𝐿𝑛 ) ( 1 + 𝑗𝜔𝑅 𝑔 𝑛 𝐶 𝑔𝑠 𝑛 1 𝑍 𝐿 𝐿𝑛 + 𝑍 𝑔 𝐿𝑛 ; Г 𝑜𝑢𝑡 𝑔𝐿𝑛 = -) ∏ [𝑇 𝑔𝐿 𝑖 𝑇 𝑔𝑅 𝑖 1-𝛿 〈𝑖,𝑛〉 ] 𝑛 𝑖=1 𝑍 𝑔 𝐿𝑛 -𝑍 𝑅 𝐿𝑛 𝑍 𝑔 𝐿𝑛 + 𝑍 𝑅 𝐿𝑛 where Г 𝑖𝑛 𝑔𝐿𝑛 = -Г 𝑖𝑛 𝑔𝑅𝑛 = -𝑍 𝐿 𝑅𝑛 -𝑍 𝑔 𝑅𝑛 𝑍 𝐿 𝑅𝑛 + 𝑍 𝑔 𝑅𝑛 𝑍 𝑔 𝑅𝑛 -𝑍 𝑅 𝑅𝑛 ; Г 𝑜𝑢𝑡 𝑔𝑅𝑛 = -𝑍 𝑔 𝑅𝑛 + 𝑍 𝑅 𝑅𝑛	(3.10) (3.11a) (3.11b)

𝐿𝑛 ) ((𝑍 𝑔 𝑅𝑛 ,𝛾 𝑔 𝑅𝑛 )) which is determined by using the same equations as (3.6a) ((3.8a) respectively) with the boundary reflection coefficients given in

(3.11)

. The same description given to the output-loaded line segments input-impedances (𝑍 𝐿 𝐿𝑛 , 𝑍 𝑅 𝐿𝑛 , 𝑍 𝐿 𝑅𝑛 ,

  .8 with physical TLs transforms equation (3.16) into equation (3.17); where the input-side series µ-TL segments are represented by (𝑍 𝑐,𝑆 𝐼 , 𝛾 𝑆 𝐼 ) with length (𝑙 𝑆 𝐼 2 ⁄ ) each and the output-side series µ-TL segments are represented by (𝑍 𝑐,𝑆 𝑂 , 𝛾 𝑆 𝑂 ) with length (𝑙 𝑆 𝑂 2 ⁄

  or (3.17) is given.

		𝑉 1
	[	𝐼 1 𝑉 3	]
		𝐼 3		𝑐𝑜𝑠ℎ (𝛾 𝑆 𝐼	𝑙 𝑆 𝐼 2 )		𝑍 𝑐,𝑆 𝐼 𝑠𝑖𝑛ℎ (𝛾 𝑆 𝐼	𝑙 𝑆 𝐼 2 )	0	0
	=	𝑠𝑖𝑛ℎ (𝛾 𝑆 𝐼 0 𝑙 𝑆 𝐼 2 ) 𝑍 𝑐,𝑆 𝐼 ⁄	𝑐𝑜𝑠ℎ (𝛾 𝑆 𝐼 0	𝑙 𝑆 𝐼 2 )	0 𝑐𝑜𝑠ℎ (𝛾 𝑆 𝑂	𝑙 𝑆 𝑂 2 )	0 𝑍 𝑐,𝑆 𝑂 𝑠𝑖𝑛ℎ (𝛾 𝑆 𝑂	𝑙 𝑆 𝑂 2 )
		[	0			0		𝑠𝑖𝑛ℎ (𝛾 𝑆 𝑂	𝑙 𝑆 𝑂 2 ) 𝑍 𝑐,𝑆 𝑂 ⁄	𝑐𝑜𝑠ℎ (𝛾 𝑆 𝑂	𝑙 𝑆 𝑂 2 ) ]
									1 0 0 0
								• [	𝑌 𝐼𝐼 1 𝑌 𝐼𝑂 0 0 0 1 0	] •
									𝑌 𝑂𝐼 0 𝑌 𝑂𝑂 1
	[ 𝑠𝑖𝑛ℎ (𝛾 𝑆 𝐼 𝑐𝑜𝑠ℎ (𝛾 𝑆 𝐼 𝑙 𝑆 𝐼 2 ) 𝑍 𝑐,𝑆 𝐼 𝑙 𝑆 𝐼 2 ) ⁄ 0 0	𝑍 𝑐,𝑆 𝐼 𝑠𝑖𝑛ℎ (𝛾 𝑆 𝐼 𝑐𝑜𝑠ℎ (𝛾 𝑆 𝐼 𝑙 𝑆 𝐼 2 ) 𝑙 𝑆 𝐼 2 ) 0 0	0 0 𝑐𝑜𝑠ℎ (𝛾 𝑆 𝑂 𝑠𝑖𝑛ℎ (𝛾 𝑆 𝑂 𝑙 𝑆 𝑂 2 ) 𝑍 𝑐,𝑆 𝑂 𝑙 𝑆 𝑂 2 ) ⁄	0 0 𝑍 𝑐,𝑆 𝑂 𝑠𝑖𝑛ℎ (𝛾 𝑆 𝑂 𝑐𝑜𝑠ℎ (𝛾 𝑆 𝑂 2 ) ] 𝑙 𝑆 𝑂 𝑙 𝑆 𝑂 2 )	[	𝑉 4 -𝐼 2 -𝐼 4 𝑉 2	]

  3.19):

	𝐷 =	-(𝑍 3 𝐷 32 + 𝐵 32 ) (𝐶 14 + 𝛥	𝐷 14 𝑍 4	)	+ 𝐷 12	(3.19d)
	where
	𝛥 = (𝐴 34 +	𝐵 34 𝑍 4	) + 𝑍 3 (𝐶 34 +	𝐷 34 𝑍 4	)
	𝐴 =	-(𝑍 3 𝐶 32 + 𝐴 32 ) (𝐴 14 + 𝛥	𝐵 14 𝑍 4	)	+ 𝐴 12	(3.19a)
	𝐵 =	-(𝑍 3 𝐷 32 + 𝐵 32 ) (𝐴 14 + 𝛥	𝐵 14 𝑍 4	)	+ 𝐵 12	(3.19b)
	𝐶 =	-(𝑍 3 𝐶 32 + 𝐴 32 ) (𝐶 14 + 𝛥	𝐷 14 𝑍 4	)	+ 𝐶 12	(3.19c)

  . 𝑆 21 represents DA insertion gain, 𝑆 12 its reverse isolation, and 𝑆 11 and 𝑆 22 represent reflection coefficients seen at the input and output ports, respectively. 𝑍 0 denotes the characteristic impedance reference (usually 50 Ω) for ports 1 and 2.

	𝑆 11 =	𝐴 + 𝐴 +	𝐵 𝑍 0 𝐵 𝑍 0	-𝐶𝑍 0 -𝐷 + 𝐶𝑍 0 + 𝐷	(3.20a)
	𝑆 21 =	𝐴 +	𝐵 𝑍 0	2 + 𝐶𝑍 0 + 𝐷	(3.20b)
	𝑆 12 =	2(𝐴𝐷 -𝐵𝐶) 𝐴 + 𝐵 𝑍 0 + 𝐶𝑍 0 + 𝐷	(3.20c)
	𝑆 22 =	-𝐴 + 𝐴 +	𝐵 𝑍 0 𝐵 𝑍 0 + 𝐶𝑍 0 + 𝐷 -𝐶𝑍 0 + 𝐷	(3.20d)

  Now it is clear how the compensation takes place through resonances: 𝑍 𝑑𝑠 interacts with 𝑍 𝑑𝑠1 and 𝑍 𝑔 interacts with 𝑍 𝑔𝑠2 , where both together contribute into reducing the frequency impact on the degrading part of 𝑍 𝑜𝑢𝑡 . Through (4.5a) it is found that inductor 𝐿 𝑑𝑠 resonates specifically with the parasitic capacitor 𝐶 𝑑𝑠1 and through (4.5b) inductor 𝐿 𝑔 resonates specifically with the parasitic capacitor 𝐶 𝑔𝑠2 .

							4.1) becoming
	(4.4).
			𝑍 𝑜𝑢𝑡 =
	𝑍 𝑑𝑠2 +	(𝑍 𝑑𝑠1 + 𝑗𝜔𝐿 𝑑𝑠 ) (𝑍 𝑑𝑠1 + 𝑗𝜔𝐿 𝑑𝑠 ) + (𝑍 𝑔𝑠2 + 𝑗𝜔𝐿 𝑔 )	{(𝑍 𝑔𝑠2 + 𝑗𝜔𝐿 𝑔 ) +	𝑍 𝑑𝑠2 • 𝑔𝑚 2 𝑗𝜔𝐶 𝑔𝑠2	}	(4.4)
		𝑍 𝑑𝑠1 + 𝑗𝜔𝐿 𝑑𝑠 =	𝑅 𝑑𝑠1 1 + 𝑗𝜔𝑅 𝑑𝑠1 𝐶 𝑑𝑠1	+ 𝑗𝜔𝐿 𝑑𝑠	(4.5a)
		𝑍 𝑔𝑠2 + 𝑗𝜔𝐿 𝑔 = 𝑅 𝑔𝑠2 +	1 1 + 𝑗𝜔𝐶 𝑔𝑠2	+ 𝑗𝜔𝐿 𝑔

TABLE 5 .

 5 1: SINGLE-STAGE DA DESIGN PARAMETERS DETERMINED FROM CAUTOD PROCESS

	N	M1 (µm)	M2 (µm)	TL Segments (𝒍 𝟐 ⁄ ) (µm)	𝐓𝐋 𝐋𝐠 (µm)	𝐓𝐋 𝐋𝐝𝐬 (µm)
	5	31	62			131	43	129
		TABLE 5.2: SINGLE-STAGE DA PRELIMINARY DESIGN CHARACTERISTICS
	Gain (dB)	Bandwidth (GHz)	𝐏 𝐃𝐂 (mW)	Gain Ripple (dB)	GBP (GHz)	⁄ 𝐆𝐁𝐏 𝐏 𝐃𝐂 (𝐆𝐇𝐳 𝐦𝐖 ⁄	)
	7	Up to 100	30		±1	224	7.46

TABLE 5 .

 5 3: EXTRACTED INTRINSIC LUMPED ELEMENTS OF 300-𝑓F SPP-SC.

	Capacitor	𝑹 𝟎 (Ω) Meas. EM Sim.	𝑪 𝟎 (𝐟𝐅) Meas. EM Sim.	𝑳 𝟎 (𝐩𝐇) Meas. EM Sim.
	300-fF	0.37	0.25	285	298	0.66	0.55
	Figure

TABLE 5 .

 5 4: PERFORMANCE COMPARISON BETWEEN WIDE BANDWIDTH AMPLIFIER TOPOLOGIES.

	Ref.	Topology	Process Node	Stack Layers	𝑪 𝟎 (fF)	𝑺𝑹𝑭 (GHz)	𝑸 &%	Area (mm 2 )	𝑪 𝒅 (𝒇𝑭 µ𝒎 𝟐 ⁄	)
	[62]	Stub	65-nm	9	348	150	N/A	10053	0.035
	[64]	MIM	65-nm	7	120	194	3.8	N/A	N/A
	[65]	MOM	45-nm	7	129	160	< 3.2 £	129 #	1
	[65]	MOM	45-nm	7	215	110	0.5	196 #	1.1
	[66]	MOM	45-nm	11	120	140	2.5	32 #	3.75
	[66]	MOM	45-nm	11	350	75	< 0 *	92 #	3.8
	This Work	SPP	55-nm	8	285	368	14.7	331	0.86

TABLE . 5

 . .5: DA CIRCUIT DESIGN PARAMETERS FOR LAYOUT IMPLEMENTATION

	N	M1 (µm)	M2 (µm)	TL Segments (𝒍 𝟐 ⁄ ) (µm)	𝐓𝐋 𝐋𝐠 (µm)	𝐓𝐋 𝐋𝐝𝐬 (µm)	𝐑 𝟑 (Ω)	𝐑 𝟒 (Ω)

TABLE 5 .

 5 6: DA SIMULATED AND MEASURED 𝑂𝑃 1𝑑𝐵 ESULTS

			Frequency (GHz)
	𝐎𝐏 𝟏𝐝𝐁	10	30	60	90
	Simulation (dBm)	4.3	4	2.4	-1.1
	Measurement (dBm)	4.6	3.4	2	-1.6

TABLE 5 .

 5 7: STATE-OF-THE-ART PERFORMANCE COMPARISON FOR CMOS-BASED DISTRIBUTED

	AMPLIFIERS

Table 2 .

 2 2. Those design parameters in order to implement such cascaded DA are summarized in Table 6.1 with the design characteristics in Table 6.2. Next Section 6.2 covers the layout implementation of the cascaded DA.

TABLE 6 .

 6 1: CASCADED DA DESIGN PARAMETERS DETERMINED FROM CAUTOD PROCESS

	M	N	M1 (µm)	M2 (µm)	TL Segments (𝒍 𝟐 ⁄ ) (µm)	𝐓𝐋 𝐋𝐠 (µm)	𝐓𝐋 𝐋𝐝𝐬 (µm)
	6	6	28	56	125		54	155
		TABLE 6.2: CASCADED DA PRELIMINARY DESIGN CHARACTERISTICS
		Gain (dB)	Bandwidth (GHz)	𝐏 𝐃𝐂 (mW)	Gain Ripple (dB)	GBP (THz)	⁄ 𝐆𝐁𝐏 𝐏 𝐃𝐂 (𝐆𝐇𝐳 𝐦𝐖 ⁄	)
		46.2	Up to 100 193.54	±3	20.42	105.5

  By ignoring 𝐿 𝑒 at first, and if 𝐶 𝑎 is chosen large enough to be safely assumed as an ACconnection to ground for the whole passband, the bias-tee equivalent input impedance is derived first from 𝑍 𝑖𝑛 ′ in (6.2).

	𝜌 = 1 -( 𝜔 𝑡𝑎𝑛𝑘 𝜔	2 )	(6.2c)
	𝛥 = (𝐶 + 𝜌𝐶 𝑠 ) 2 + (𝜔𝜌𝐶𝐶 𝑠 𝑅) 2	(6.2d)
	Impedance 𝑍 𝑖𝑛 ′ is in the form of 𝑅 𝑖𝑛 ′ ± j|𝑋 𝑖𝑛 ′ |. For matching purpose, |𝑋 𝑖𝑛 ′ | should be
	𝑍 𝑡𝑎𝑛𝑘 (𝜔) =	-𝑗 𝜔𝐶 𝑆 (1 -( 𝜔 𝑡𝑎𝑛𝑘 𝜔	)	2	)	(6.1a)
	𝜔 𝑡𝑎𝑛𝑘 =	1 √𝐿 𝑆 𝐶 𝑆	(6.1b)
	𝑅𝑒{𝑍 𝑖𝑛 ′ (𝜔)} = 𝑅′ 𝑖𝑛 (𝜔) = 𝑅	𝐶 2 𝛥	(6.2a)
	𝐼𝑚{𝑍 𝑖𝑛 ′ (𝜔)} = 𝑋 𝑖𝑛 ′ (𝜔) = -	1 𝜔	•	𝐶 + 𝜌𝐶 𝑠 + 𝜔 2 𝜌𝐶 𝑠 𝐶 2 𝑅 2 𝛥	(6.2b)

TABLE 6 .

 6

	3: 100-GHZ BANDWIDTH INDUCTIVE BIAS-TEE DESIGN PARAMETERS
	𝐋 𝐬	𝐂 𝐒	𝐂 𝐚	𝐂	𝐋 𝐞
	(nH)	(𝐟F)	(pF)	(pF)	(pH)
	6	27.6	2	2	39
	6

.2.1.4 100-GHz Bandwidth Bias-Tee: Simulation vs Measurement Results

TABLE 6 .

 6 4: SINGLE-STAGE DA CIRCUIT DESIGN PARAMETERS FOR LAYOUT IMPLEMENTATION

	N	M1 (µm)	M2 (µm)	TL Segments (𝑙 2 ⁄ ) (µm)	TL Lg (µm)	TL Lds (µm)
	6	28	56	125	54	155

TABLE 6 .

 6 5: STATE-OF-THE-ART PERFORMANCES COMPARISON FOR DISTRIBUTED AMPLIFIERS

	Ref.	Process Techno.	Gain (dB)	Ripple £ (dB)	BW & (GHz)	Supply (V)	P DC (mW)	GBP (GHz)	𝑮𝑩𝑷 𝑷 𝑫𝑪 𝑮𝑯𝒛 ( 𝒎𝑾 )	Total Area (mm2)	GBP P DC • Area GHz mW • mm 2 ) (
		90-nm
	[30]	Si	7.4	-3 %	80	2.4 *	120	188	1.57	0.72	2.18
		CMOS
		90-nm
	[41]	Si	7 @	+9 % ,-3	70	N/A	122	157	1.29	0.72	1.8
		CMOS
		90-nm
	[42]	digital	14 @	±1.5 %	73.5	1.2 *	84	368	4.38	1.72	2.54
		CMOS
	[43]	40-nm digital CMOS	15 $	+5 % ,-3	80	(1, 1.7) **	90	450	5	0.31	16.13
		120-nm
	[44]	SOI	11	±1.2	85	2.5 *	210	302	1.44	1.28	1.13
		CMOS
		120-nm
	[45]	SOI	7.8	±1.3	82	2.6 *	130	201	1.55	1.05	1.47
		CMOS
		45-nm
	[31]	SOI	9	±1.5 %	92	1.2 *	73.5	259	3.52	0.45	7.82
		CMOS
		22-nm
	[32]	FD-SOI	8.5	-3 %	110	2 *	80	292	3.66	0.38	9.63
		CMOS
		130-nm
	[46]	InP	14.5 #	±0.7	94	3 *	N/A	499	N/A	2.75	N/A
		HEMT
		100-nm
	[33]	InP	7	+2.5 %	111	N/A	N/A	248	N/A	2.2	N/A
		HEMT
		70-nm
	[47]	InP	21 @	±3 %	80	2 **	300	898	3	2.47	1.21
		HEMT
		50-nm
	[34]	InGaAs	11	±1	105	6 *	450	373	0.83	1.69	0.5
		mHEMT
		250-nm
	[48]	InP	12.8	+7 % ,-2 %	180	N/A	110	724	6.58	0.32	20.57
		HBT
		250-nm
	[36]	InP	10	-3	182	4 *	105	575	5.47	0.33	16.57
		HBT
		130-nm
	[35]	SiGe	10	±2 %	170	3.6 *	108	537	5	0.38	13.16
		HBT
		130-nm
	[49]	SiGe	24 @	+2.5 % ,-1 %	95	N/A	247	1506	6.09	0.65	9.37
		HBT
	This Work $	55-nm CMOS Si	45.3	±3	95	1.5 **	243	17487	71.96	3.5	20.56

N/A = not available.

Chapter 6

THz Gain-Bandwidth Product 100-GHz Cascaded CMOS Distributed Amplifier

In the last chapter, a demonstration on how we can use the proposed model to realize a single-stage DA with high 𝐺𝐵𝑃 𝑃 𝐷𝐶 ⁄ characteristic was presented. There, both circuit design and implementation sides of the design process were covered. In addition, performance analysis and comparison with state-of-the-art CMOS-based DAs was performed where ours demonstrated better overall performance. In this chapter, the model is reused in combination with device cascading technique to demonstrate its potentiality in realizing a CMOS-based DA with the highest THz GBP characteristic possible when compared to the literature. This chapter is structured as follows. Section 6.1 covers the circuit design part of the design process from determining the new set of required design variables (𝑙 2 ⁄ , 𝑁, 𝑊 𝐶𝑆 , 𝑇𝐿 𝐿𝑔 and 𝑇𝐿 𝐿𝑑𝑠 ) in addition to a new design variable (𝑀) which defines the cascading factor. Section 6.2 covers the design implementation part of the design process. Here, a new integrated inductive bias-tee [START_REF] Chaar | Integrated Wideband Millimeter-Wave Bias-Tee -Application to Distributed Amplifier Biasing[END_REF] is presented that offers wideband characteristic. Section 6.3 discusses the simulated results of the implemented cascaded DA. A comparison with the performances of state-of-the-art DAs in different technologies and process nodes is presented in Section 6.4. Finally, Section 6.5 concludes and summarizes this chapter.

THz GBP Cascaded CMOS DA: Circuit Design

From the state-of-the-art presented in Table 2.2 (Chapter 2), and reminded in Section 6.4 of this chapter, the idea of cascading DA was introduced by [START_REF] Tsai | A 70GHz cascaded multistage distributed amplifier in 90nm CMOS technology[END_REF], [START_REF] Arbabian | A tapered cascaded multi-stage distributed amplifier with 370GHz GBW in 90nm CMOS[END_REF], [START_REF] Li | A 2 to 92 GHz distributed amplifier using 70-nm InP HEMTs[END_REF], [START_REF] Arbabian | A 94 GHz mm-Waveto-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition[END_REF], as a technique to obtain higher overall gain covering the large passband where the gain of a single-stage 𝑁-unit cells DA is multiplied by the number of cascaded stages (𝑀). In [START_REF] Alaji | Cascaded tunable distributed amplifiers for serial optical links: some design rules[END_REF],