Friederike Brendel

Thomas Zwick

Julien Poëtte

Béatrice Cabon

Sideband Stabilization in the Presence of LO Phase Noise: Analysis and System Demonstrator

Keywords: frequency jitter, phase noise, phase-locked loop, radio-over-fiber systems, mode-locked lasers

We present a technique allowing the stabilization and tuning of a modulation sideband in the presence of high carrier frequency jitter and increased carrier phase noise. This technique is of particular interest in communication systems where oscillators providing the carrier signal cannot be stabilized by a conventional phase-locked loop, such as systems relying on low-cost optical LO generation techniques. The results obtained in simulation are validated by measurements carried out on a modular system demonstrator.

I. INTRODUCTION

T HE trend in modern radio communication systems has been moving towards carrier signals at millimeter wave (mm-wave) frequencies. Signals at such high frequencies can be generated through the frequency multiplication of a lower frequency signal, or by optical heterodyning, where a signal at an arbitrary frequency can be generated by detecting the interference of two or more phase-locked optical laser modes, separated by the desired carrier frequency, by means of a photo-detector (PD). An electrical double sideband (DSB) spectrum is created at the PD if the laser pump current is varied with a modulation signal. Any instability present in the heterodyne carrier signal translates into an instability present in the desired output signal of the system, namely the information-carrying sidebands, which is why the transmission quality is strongly dependent on the purity of the carrier. It thus ultimately depends on how well the phases of the optical modes can be locked together.

We have previously demonstrated the impact of phase noise in an mm-wave communication system where the carrier signal is provided by heterodyning the optical modes of a free-running passively mode-locked laser diode (MLLD) [START_REF] Brendel | Low-cost analog fiber optic links for in-house distribution of millimeter-wave signals[END_REF]. Such laser diodes are potentially low-cost devices which are easy to integrate, but they exhibit rather high frequency jitter and/or phase noise (-55 dBc/Hz at 10 kHz offset from the carrier, and a carrier variation of ≈600 kHz) [START_REF] Van Dijk | Phase Noise Reduction of a Quantum Dash Mode-Locked Laser in a Millimeter-Wave Coupled Opto-Electronic Oscillator[END_REF]. Furthermore, the precision of frequency adjustment in the manufacturing process is limited to a few hundred MHz to a few GHz. Unlike a voltage-controlled oscillator (VCO), the MLLD does not give access to a physical quantity which can be used to fine-tune the oscillation -which hinders the construction of stabilization ig. 1: Impact of phase noise on EVM. Dashed line: ideal case, no phase noise. loops and is therefore problematic in the design of high data rate communication systems.

A communication system has to adhere to a well-defined spectral mask. Limited long-term stability in frequency, frequency jitter, or imprecise selection of the band center frequency can cause leakage into adjacent channels. At the receiver, requirements on the carrier recovery mechanisms must be tightened. Furthermore, increased phase noise will spoil the signal quality even at a stable center frequency. Error vector magnitude is a common figure of merit for transmission quality defined in most communication standards (see e.g. [START_REF]IEEE Standard: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs) Amendment 2: Millimeter-wave-based Alternative Physical Layer ExtensionIEEE Std 802[END_REF]). Georgiadis has investigated the relationship between the signal-to-noise ratio (SNR), the root-mean-square (rms) phase error σ rms and the EVM for the case where the peak symbol power equals the average symbol power [START_REF] Georgiadis | Gain, phase imbalance, and phase noise effects on error vector magnitude[END_REF]:

EV M rms = 1 SNR + 2 -2 cos (σ rms ). (1)
As can be seen from figure 1, σ rms = 0 introduces a constant error floor even for very high SNR values (the dashed line corresponds to σ rms = 0). It is thus paramount for any communication system to minimize σ rms by stabilizing the transmit (Tx) signal in both frequency and phase. Typically, phase-locked loops (PLLs) are employed to stabilize the inherently unstable signal of a VCO [START_REF] Egan | Frequency Synthesis by Phase Lock[END_REF]. The PLL principle relies on the fact that there exists a monotonous relationship between the physical quantity influencing the oscillation (e.g. the capacitance in an LC tank in a VCO) and an electrical signal controlling this physical quantity (e.g. the voltage). The PLL principle has been extended to include laser oscillators and opto-electronic components in optical PLLs [START_REF] Buckman | Stabilization of millimeter-wave frequencies from passively mode-locked semiconductor lasers using an optoelectronic phase-locked loop[END_REF]. If, however, the design of the oscillator does not allow access to such a physical quantity (as in the case of various laser-based techniques, where the oscillation cannot be fine-tuned by varying the laser pump current), the construction of a conventional PLL is not feasible. Other techniques commonly employed in the context of laser physics like optical active mode-locking [START_REF] Avrutin | Monolithic and multi-GigaHertz mode-locked semiconductor lasers: Constructions, experiments, models and applications[END_REF] or optical feedback loops ( [START_REF] Van Dijk | Phase Noise Reduction of a Quantum Dash Mode-Locked Laser in a Millimeter-Wave Coupled Opto-Electronic Oscillator[END_REF], [START_REF] Merghem | Low noise performance of passively mode locked quantum-dash-based lasers under external optical feedback[END_REF]) tend to be complex and allow at most a stabilization of frequencybut no tuning capability.

In this work, we present a full analysis of a novel stabilization and tuning architecture allowing the stable transmission of a sideband signal in the presence of long-term carrier instability (jitter or drift) and increased phase noise; its key principle was presented in [START_REF] Brendel | A Novel Technique for Sideband Stabilization in the Presence of Carrier Phase Noise in RoF Systems[END_REF]. Here, we show a complete system demonstrator encompassing full heterodyne up-conversion, and we enclose a thorough Laplace analysis of the resulting noise suppression. The paper is organized as follows: In section II, the stabilization technique is introduced. We discuss the capture ranges of the proposed architecture in section III. The loop response to phase noise is evaluated in terms of the phase power spectral density. Simulations and measurements on the test hardware according to section IV are compared in section V. The results are discussed in section VI, and we will conclude the work in section VII.

II. STABILIZATION PRINCIPLE

The proposed architecture is depicted in figure 2. The bold letters A-D are intended for an easy comparison between the block diagram and the hardware implementation shown in figure 3. For a discussion of the inclusion of an optical subsystem, refer to [START_REF] Brendel | A Novel Technique for Sideband Stabilization in the Presence of Carrier Phase Noise in RoF Systems[END_REF]. The key ideas are the following:

• The complete stabilization structure incorporates a PLL modified by a loop mixer and a band-pass filter, as well as an up-conversion stage where the DSB spectrum is created and a carrier-recovery stage on the Tx's side. the loop for the reference phase ϕ ref as input signal:

ϕ ref 3R f IF nMϕ' IF ϕ ref f LO g3=f IF OUT f LO g3=f IF ϕ LO g3=ϕ' IF ϕ RF = f RF = OUT UP=CONVERSION STAGE BPF K K AMP 3 TXMSignalMIN CARRIERM RECOVERY K V K m K P A B C D
G F (s) = K P • Z LPF (s) • K V s , (2a)
G R (s) = 1 N , (2b)
where K P is the phase-detector gain, Z LPF is the loop filter transfer function, K V is the sensitivity of the VCO, and N is the frequency divider value [START_REF] Egan | Frequency Synthesis by Phase Lock[END_REF]. Here, these functions must be modified to include additional components: the loop mixer and the band-pass filter BPF 1 , as well as an amplifier AMP 1 necessary in order to provide sufficient RF power to the PLL.

1) Effect of a mixer: Regarding the phase or the frequency of a signal, the mixing process is a linear translation. Through mixing process, the sidebands are formed at the sum and the difference of the input frequencies. Assuming up-conversion in an ideal mixer:

ϕ RF,USB = ϕ LO + ϕ IF , (3a)
ϕ RF,LSB = ϕ LO -ϕ IF , (3b)
for the USB and the LSB, respectively. In the phase-locked loop, most computations involve changes from steady state and are evaluated at an offset from center frequency. The center frequency itself (shifted by mixing) is not relevant [START_REF] Egan | Frequency Synthesis by Phase Lock[END_REF]. If the PLL acts on a mixing product, the phase-frequency detector must compare the sideband phase to the reference phase. This approach is justified as long as it does not put loop stability at risk, i.e. as long as we design the loop for sufficient phase margin. In the following, the LSB is selected in order to keep the operating frequency of the PLL as small as possible. The mixer's conversion loss (negative gain) can be represented in the respective transfer function by a factor K m .

2) Low-pass equivalent for band-pass filtering: The effect of the band-pass filter on the loop transfer functions will affect the loop response to phase noise. It is in general possible to find a low-pass equivalent representation for a band-pass filter in a PLL as long as the modulation deviation is small [START_REF] Egan | Frequency Synthesis by Phase Lock[END_REF]. In our case, the situation is even simpler as we already design the band-pass filter starting out from a low-pass prototype. The low-pass prototype is designed to follow an attenuation characteristic of G 2 eqLPF ( f ). In terms of the filter transfer function

Z eqLPF , G 2 eqLF ( f ) = Z eqLPF ( j f ) 2 .
3) Effect of RF amplifiers: An amplifier in the loop can, in a first approximation, be represented by a gain factor K a . In a phase-locked loop optimized for CW operation, the amplifiers operate at a fixed frequency, which is why the gain can be thought of as constant.

4) Modified transfer function:

The signal is tapped after the mixer ("OUT"). All components thereafter are considered part of the reverse transfer function. The mixer becomes a part of the forward transfer function.

G F (s) = (-1) • G F (s) • L WD • (-1) • K m , (4a) G R (s) = K a1 • Z eqLPF (s) • G R (s). (4b)
The factor L WD reflects the fact that only half of the VCO power is routed back to the loop; a Wilkinson divider with a nominal split of L WD = 0.5 is employed at the branching point. The factor (-1) represents the phase reversal in the LSB which is compensated for by reversing the polarity of the charge pump with a gain of K P (again, factor -1).

We then define the closed-loop transfer functions where we refer to H LP (s) as the low-pass transfer function, and to H HP (s) as the high-pass transfer function:

H LP (s) = G F (s) 1 + G F (s)G R (s) , (5a)
H HP (s) = 1 1 + G F (s)G R (s) . ( 5b
)
Note that the proposed principle is not identical to conventional sliding IF phase-locked loops, where a stable translation oscillator is used to shift the (usually down-converted) signal within a variable IF range. Such a system does not accept increased phase noise or jitter on the LO because it is not the mixing product which is fed back within the loop structure. The principle shown here can be used for any type of noisy LO generation, in particular for those optically generated in the millimeter wave range, where few means of stabilization are available.

III. CAPTURE AND HOLD-IN RANGES

The PLL is supposed to lock the modulation sideband generated at the loop mixer from the output signal of the IF oscillator and the recovered LO signal. The capture range refers to the range of frequencies for which the unlocked PLL can become locked to the reference after a certain capture time which will we denote T cap . Once locked, it is required to counter-act the phase and frequency deviations of the modulation sideband. The range of frequencies for which the PLL can track the variations of the controlled signal is referred to as hold-in range.

The perturbations we deal with are the phase and frequency deviations of the modulation sideband. These deviations depend on both the IF oscillator and the LO used in the upconversion stage. We consider the following the following cases:

• Case 1, phase noise: The LO center frequency is stable.

The variation of the modulation sideband frequency is mostly influenced by the IF oscillator. Through mixing, the phase of the modulation sideband experiences a sudden shift. • Case 2, frequency jitter: The LO center frequency is not stable. A slow variation of the sideband frequency will occur which is due to the variations of both the IF and the LO oscillator frequency. At the loop mixer, both frequency and phase of the modulation sideband experience a sudden change.

For the following, we assume that the PLL comprises a charge-pump phase-frequency detector (PFD). In locked state, a PLL featuring a charge-pump PFD does not have a residual frequency error, nor a steady-state phase error [START_REF]Best Phase-locked loops -Design, Simulation, and Applications[END_REF].

Capture range: Whether or not the PLL will lock is determined by two aspects. The first is sufficient phase margin. While a very large phase shift might be produced at the mixer, it primarily concerns the center frequency of the signal to be controlled (here: f LOf IF ). It is important to note that this phase shift at the absolute center frequency does not enter into the loop model. The phase margin is calculated at the unity gain offset modulation frequency from the center frequency of the controlled signal. The notion of phase margin is essentially independent from the absolute frequency or phase of the controlled signal and can be considered separately in loop design. The second aspect is the actual capture range of the PLL. If a PFD is used, the average output signal of the PLL varies monotonically with the frequency error. Theoretically, the capture range is infinite [START_REF]Best Phase-locked loops -Design, Simulation, and Applications[END_REF]. In practice, it is limited by the frequency range of the controlled (IF) oscillator. As a consequence, the PLL will always lock -if the phase margin condition is met -and the frequency error will settle to zero. Likewise, the range of possible phase error allowed for stable operation is the full 360 • range for a PFD [START_REF]Best Phase-locked loops -Design, Simulation, and Applications[END_REF]. The residual phase will also settle to zero. In case 1, we can therefore be sure that the PLL will lock.

In case 2, the change in LO frequency must be slow compared to the time span necessary for capture, assuring that the PLL can actually follow the frequency variation of the sideband, as T cap is not infinitesimally short. It depends on several parameters [START_REF]Best Phase-locked loops -Design, Simulation, and Applications[END_REF],

T cap = 2 • ∆ f 0 • NC 1 K P K V , (6)
where ∆ f 0 represents the difference between the reference frequency and the scaled-down initial frequency of the controlled signal (here, the modulation sideband), and C 1 is the loop filter capacitance that loads the PFD. In equation ( 6), we have neglected the gains of the loop amplifier, the band-pass filter, and the loop mixer. All values considered, T cap can be estimated in the range of hundreds of ns to 1 µs.

Hold-in range: The hold-in range is obtained by calculating the frequency where the phase error is at its maximum. In case 1, the use of a charge-pump PFD results in a hold-in range which is theoretically infinite [START_REF]Best Phase-locked loops -Design, Simulation, and Applications[END_REF] as any phase error can be corrected by the PLL. As for the real capture range, the real hold-in range is limited by the operating range of the controlled oscillator.

In case 2, the charge-pump PFD will correct the frequency error of the locked PLL. As the LO frequency changes over time, two conditions must however be fulfilled in order to exploit the hold-in range of the PLL. First, the LO frequency must not reach a value that would result in a difference frequency outside the IF oscillator's frequency range. Second, the control mechanism of the PLL must be fast enough to follow the frequency variations. The decisive factor is the loop bandwidth. It can easily be designed to cover several hundreds of kHz to several MHz.

We thus expect the PLL to lock and stay locked if T cap is small compared to the rate of the frequency variation of the LO (≈ ms), and as long it does not exceed the frequency range of the IF oscillator.

IV. PLL DEMONSTRATOR

A modular demonstrator was implemented for a first demonstration of the concept. We emphasize that the choice of components was linked to their off-shelf availability but leaves room for optimization which we will consider in the parametric analysis in the following section V. The demonstrator is shown in figure 3. The carrier signal is provided by a commercial signal generator (Anritsu 68377B). The DSB spectrum is created in a mixer identical to the mixer in the loop (not shown in the figure for limited space) and fed into the demonstrator at "Tx Signal IN" (input C). Table I gives a summary of the relevant parameters.

The main component of the PLL is a chip (ADF4108) comprising a low-noise digital PFD, a charge pump, and programmable dividers for both the RF input signal (value N) and the reference signal (value R). The reference signal is delivered by a signal generator, allowing the use of different reference frequencies, and selectable comparison frequencies f PFD for the PFD. The surface-mount VCO-IF delivers signals at frequencies from 1.77 to 1.83 GHz at an output power of 3 dBm. Its phase noise for offset frequencies > 1 MHz is 161 dBc/Hz. With a charge pump voltage of 5 V, and a target control voltage of the VCO-IF of about 2 V, the loop filter could be realized as a passive RC network and was designed for third order and a loop bandwidth of f BW = 210 kHz at a phase margin of ϕ m = 27 • . The surface-mount I/Q-modulator is a vector modulator operating in the range from 1.5 to 2.5 GHz with a maximum output power of 7.1 dBm and an output noise floor of -158 dBm/Hz (its output is "IF signal OUT"). The mixer in the loop is a surface-mount double-balanced MMIC mixer operating in the range from 1.8 to 5 GHz. A DSB spectrum is created with principal spectral components at 3.2 GHz (LSB), 5 GHz (carrier), and 6.8 GHz (USB); the LO-to-RF suppression of about 30 dB is enough for both the carrier recovery path (where we actually need the LO component in the spectrum) and in-loop up-conversion (where it can be filtered). BPF 1 is designed in the low-pass domain with a maximally flat Butterworth response of the following characteristics: passband edge f cut-off = 50 MHz, stopband edge 100 MHz, passband attenuation L ar = 0.5 dB at f cut-off , stopband attenuation L A at the stopband edge -40 dB.

The measured filter loss at the band-pass center frequency f BPF = 3.2 GHz is -3.4 dB, and the measured phase shift is θ BPF1 = 0.65 • . Its influence on phase margin is negligible in the direct vicinity of the center frequency.

The carrier recovery stage consists of two amplifiers with gains K a2,dB = 22 dB (OP1dB = 8 dBm, NF = 1.86 dB) and K a3,dB = 8 dB (OP1dB 17.5 dBm, NF = 8 dB), as well as the band-pass filter BPF 2 designed as a coupled line bandpass filter centered at 5 GHz. It is sufficient to consider the insertion loss of the band-pass filter BPF 2 (K BPF2,dB = -5 dB) and its phase shift θ BPF2 = 21 • introduced at 5 GHz instead of its transfer function. We can do so because its bandwidth of approximately 200 MHz is large compared to the loop bandwidth. The carrier recovery stage is designed to provide a drive power of ≈ 10 dBm at the LO port of the loop mixer.

F LF ref F eqLF /N K p /R K a1 VCO-IF LO S ϕ,BPF (f) S ϕ,AMP (f) S ϕ,PFD (f) S ϕ,ref (f) S ϕ,L*V (f) K v (-1)K m System OUT S SYS (f) L WD A D
Fig. 4: Circuit equivalent for phase noise analysis, corresponds to dashed box "modified PLL architecture" in figure 2.

V. LOOP RESPONSE TO NOISE A. Phase power spectral density simulations

Phase noise can be understood as the modulation of the carrier frequency by a random noise waveform. It is common practice to treat this phase modulation as a zero-mean stationary random process quantified by its two-sided power spectral density (psd) function S ϕ ( f ). Its rms phase error σ rms is obtained through integration,

σ rms = +∞ -∞ S ϕ ( f )d f . (7)
After demodulation, S ϕ ( f ) includes both negative and positive frequencies. In phase noise measurements, it is common to consider only the positive frequencies and hence, the single sideband (SSB) psd L ϕ ( f ). The usual way to determine the loop's total response is to determine an appropriate closed-loop transfer function H i (s) from a source i to the output. Starting from the component's psd S ϕ,in,i ( f ), the resulting psd at the output S ϕ,out,i ( f ) can be determined according to

S ϕ,out,i ( f ) = S ϕ,in,i ( f ) • |H i ( j f )| 2 , ( 8
)
where the Laplace variable of equation ( 5) is s = 2π f . The noise waveform is a voltage or a current, so the squared closedloop transfer function appears in the output psd which can then be obtained by summing up the various noise contributions of oscillators, mixer, amplifiers, and filters,

S ϕ,TOT ( f ) = ∑ i S ϕ,out,i ( f ). ( 9
)
This procedure is reflected in the component noise equivalent circuit as depicted in figure 4. Each component is assumed ideal and the noise contribution is inserted as a noise source with the respective phase noise psd S ϕ,in,i . The noise contribution of the loop filter and the phase noise originating in the N-and R-dividers have been neglected. It is then necessary to determine the influence of the different components.

Reference phase noise (described by Leeson's model [START_REF] Leeson | A simple model of feedback oscillator noise spectrum[END_REF]) will be scaled down by the reference divider value, and transformed by the low-pass transfer function to the output of the loop:

S ϕ,out,ref ( f ) = S ϕ,ref ( f ) • 1 R 2 |H LP ( j f )| 2 . ( 10
)
It is preferable to pick a high reference frequency f r if the reference phase noise can be scaled down by a high value of R.

The chip phase noise will be scaled by the charge pump gain and transformed to the output of the loop, again by the low-pass transfer function:

S ϕ,out,PFD ( f ) = S ϕ,PFD ( f ) • 1 K p 2 |H LP ( j f )| 2 . ( 11
)
Both amplifier noise and the contribution of the noise figure of the band-pass filter can be modelled as flat. Their noises will be transformed by the loop according to

S ϕ,out,y ( f ) = S ϕ,y ( f ) • N 2 • |H LP ( j f )| 2 . ( 12
)
The VCO signal passes through the power divider and suffers a conversion loss by the loop mixer,

S ϕ,VCO ( f ) = |L WD | 2 • |(-1) • K m | 2 • S ϕ,VCO ( f ). (13)
Both S ϕ,VCO ( f ) and S ϕ,LO ( f ) are described by Leeson's model 5: Simulations. Dashed curve corresponds to the sideband phase psd when PLL is inactive. Bold black curve corresponds to the simulated curve for the PLL demonstrator as prepared. [START_REF] Leeson | A simple model of feedback oscillator noise spectrum[END_REF]. In the carrier recovery stage, the LO signal is amplified, filtered and attenuated by the mixer's LO-to-RF isolation:

S ϕ,LO ( f ) = |K a3 | 2 • |K a2 | 2 • |K BPF2 | 2 • |exp ( jθ BPF2 )| 2 • |K LO-RF | 2 • S ϕ,LO ( f ). (14)
From equation ( 14), we see that by carefully selecting the amplifiers and the filter, it is possible to design the carrier recovery stage such that it is quasi-transparent with respect to LO phase noise. The loop mixer and the mixer in the up-conversion stage can therefore be operated under similar conditions. When the recovered LO signal and the VCO-IF signal pass through the mixer, the phase psd's at the mixer's RF output will be convoluted to give:

S ϕ,L * V = S ϕ,LO ( f ) * S ϕ,VCO ( f ). (15)
Through the loop, this combined phase noise will be transformed by the high-pass transfer function,

S ϕ,out,L * V = S ϕ,L * V • |H HP ( j f )| 2 . ( 16
)
For the electrical measurements, the noise figure of the recovered LO is determined by the signal generator's noise floor. This noise will be transformed through the loop in the high-pass transfer function:

S ϕ,out,SYS ( f ) = S ϕ,SYS ( f ) • |H HP ( j f )| 2 . ( 17
)
When we add the results of equations ( 10) -(17) in equation ( 9), we obtain the over-all response of the loop to phase noise. In simulation, we can now vary the different parameters in order to state more precisely the requirements on the PLL. It is assumed that the phase noise of the LO is a given parameter which cannot be altered by the system designer. At a given noise level, the optimum loop bandwidth is found at the intersection of the f -2 slope and the noise floor. The loop bandwidth sets the minimum phase-frequency detector frequency for stable operation (usually a factor of 10 must be maintained [START_REF] Egan | Frequency Synthesis by Phase Lock[END_REF]). The simulation results are shown in figure 5: In figures 5(a), we observe how in-loop phase noise scales with the divider value N (values: 50, 100, 200, 400, 800, 1600). Inband phase noise can be suppressed by selecting the smallest possible divider ratio N, i.e. the highest possible f PFD . Figure 5(b) shows a variation of the charge pump gain (for K P = 0.32 mA/rad, 0.48 mA/rad, 0.79 mA/rad, 1.24 mA/rad, 1.59 mA/rad). We conclude that the charge pump gain should be chosen for sufficient damping of the transfer function at the loop bandwidth. A high-Q reference oscillator whose nominal frequency is as high as possible is crucial for in-loop phase noise suppression. The reference phase noise is then scaled down by the R-divider. For high VCO input capacitances and high f PFD , the loop filter can be implemented as an active filter that will not load the charge pump capacitively.

While the lower limit of integration in equation ( 7) does not have a severe impact on the accumulated phase error, the upper limit does matter. At large offsets, the amount of additional phase noise that has to be accounted for when pushing the upper integration limit higher, is highly dependent on system noise. Figure 5(c) shows the influence of the system noise figure F total (steps of 5 dB up to 55 dB). Adhering to those design rules which can be extracted from this parametric analysis, the PLL can be improved under the assumption that the LO phase noise and the VCO-IF phase noise stay the same. With the same chip, the PFD frequency can be increased to f PFD = 50 MHz, allowing a minimum divider value of N = 64 for stabilization at 3.2 GHz. The charge pump gain is set to I P = 0.79 mA/rad. A third order active loop filter in the so-called "standard feedback" topology was simulated (Nomenclatura as in [START_REF] Banerjee Pll Performance | Simulation, and Design[END_REF]: C 1 = 0.63 pF, R 1 = 6.55 kΩ, C 2 = 19.7 pF, R 3 = 38 Ω, C 3 = 134 pF). The possible improvement of the total phase psd can be observed in figure 5(d), where the integrated phase error can be reduced from 1.52 • to about 0.21 • .

B. Measurements of the single sideband phase psd and EVM

The phase noise performance of the loop itself is evaluated using an electrical LO. Here, it is supplied by a signal generator (Anritsu 68377B) at a frequency of 5 GHz. Different levels of LO phase noise can be tested by using Gaussian noise (GN) frequency modulation (FM). This function of the generator requires the specification of a maximum FM deviation ∆ f . The FM rate is set such that the modulating frequency f m follows a Gaussian distribution between 0 Hz and 1 MHz, so that the modulation index β = ∆ f / f m is also Gaussian distributed. The modulation appears as phase noise on the generator's CW output signal while the center frequency is fixed. This way, the phase noise characteristics of the LO can be controlled. Figure 6(a) shows a comparison between the simulated curves and the measured results of the PLL without additional phase noise (∆ f = 0 Hz) which coincide well and thus validate our loop noise model. We distinguish four different regions of interest: at large offsets (I), the noise floor is largely determined by the chip noise scaled by the divider ratio N; up to the loop cut-off frequency (210 kHz approx.), the curve is largely determined by the oscillator noise resulting from the mixing of the LO and IF oscillators when free-running (II); the overshoot can be attributed to the loop filter function (III); and the plateau within the loop bandwidth is, to a large extent, scaled reference noise (IV). The instability measured in the laser-based system used for comparison corresponds to a a phase noise that can be In the immediate proximity of the center frequency, the PLL suppresses the phase noise by as much as 40 dB. At an offset of 10 kHz, a suppression of 20 dB is achieved. Locally, the overshoot in the loop filter function causes the phase noise level to rise which is definitely an issue that needs improvement in a rigorous PLL re-design. In figure 7, the results of a data transmission experiment are shown. Here, the PLL was active (phase noise resulting from ∆ f = 80 kHz) and the I/Q ports of the demonstrator were fed by a digital baseband signal at 18 Mbps at a quadrature-phaseshift-keying (QPSK) format according to IEEE 802.11a [START_REF][END_REF]. The measured SNR for the modulated signal with the active PLL was about 26.5 dB. With an integrated rms phase error of 1.52 • , this results in an EVM value of 6% according to equation (1) which was confirmed by measurement (see grey circle). As can be observed from figure 7, the floor value for higher SNR values is at about 3%. We conclude that the EVM is still limited by the SNR. With the PLL inactive and still under the condition of emulated phase noise at ∆ f = 80 kHz, the EVM was not reliably measurable but ranged in the order of 40% (for this reason, not shown in fig. 7).

VI. DISCUSSION

In the same figure, we have plotted the curve for σ rms = 0.21 • which results in EVM values close to the theoretical maximum (σ rms = 0 • ), <1%, when design improvements are made according to section V-A. At such small EVM values, other imperfections such as the I/Q imbalances of modulator and demodulator will most likely limit the transmission. Further improvement can thus only be expected if the SNR of the system can be improved.

So far we have neglected the possible occurrence of time delays in the loop. In the event where a time delay T d is included at some point in the architecture, we might run into problems regarding loop stability. If T d occurs within the loop, the phase shift does not depend on the phase difference of the IF and the LO signal, mixed at the loop mixer. Instead, phase shifts proportional to the respective noise modulation frequency will be produced by T d . It is thus wide loop bandwidth which worsens the situation. In general, it is assumed that a delay is not critical as long as it is much smaller than the reciprocal of the loop bandwidth, which is in our case, 4.76 µs [START_REF] Egan | Frequency Synthesis by Phase Lock[END_REF]. An SMA connector implies a time delay of about 50 ps, while a transmission line exhibits a time delay of 5 ps/mm []. Adding up cables and connectors present in the measurement of the demonstrator, the overall delay ranges at most in the ns range and will be negligible compare to 1/ f BW . Further reductions in the lengths of the signal paths can be envisioned by integrating the components on one board (as opposed to this modular approach).

VII. CONCLUSION

In a communication system in which an information signal is frequency-converted by mixing it with a high frequency carrier, it is this up-converted signal we wish to stabilize or tune. If the signal modulation results in a DSB spectrum, the stability of the carrier is secondary as long as at least one of the sidebands is stable. Based on this consideration, a PLL can be modified to operate on a sideband signal. Its most striking feature is that it can provide a stable modulation band in the presence of high carrier instability as manifested in frequency jitter and phase noise. This is valid for any type of LO generation, including optical techniques resulting in LO frequencies in the millimeter wave range. We have shown a first proof of concept based on the system demonstrator presented in this paper. Electrical measurements have shown the feasibility of the loop, and the measurement results could be reproduced in the simulation. By simulation, the requirements on the loop's performance could be refined. If the design rules presented in section V-A are respected, the resulting rms phase error can be decreased from 1.52 • to 0.21 • . The loop's IF synthesizer capability makes it possible to fully compensate for the drift of the LO frequency and to tune the sideband frequency to a nominal center value as required by the standard spectral masks. The phase noise could be suppressed within the loop's bandwidth by 40 dB.

F

  . Brendel was and T. Zwick is with the Institut für Hochfrequenztechnik und Elektronik at the Karlsruhe Institute of Technology, D-76131 Karlsruhe, Germany email: brendel@kit.edu. J. Poëtte and B. Cabon are with the Institut de Microélectronique, Electromagnétisme et Photonique, F-38016 Grenoble cedex 1, France. Manuscript received x, 2012; revised x, 2013.

Fig. 2 :

 2 Fig. 2: Transmitter architecture: Stabilization principle. Letter A-D correspond to points A-D in figure 3.

TABLE

  order C 1 = 5.6 pF, C 2 = 220 pF, C 3 = 1.5 pF, R 1 = R 2 = 2.7 kΩ Reference f r = 200 MHz Loop bandwidth f BW = 210 kHz Phase margin ϕ m = 27 •

Fig. 3 :

 3 Fig. 3: Photo of PLL Demonstrator. Not shown in the picture: up-conversion stage (Anritsu 6877B and mixer at input C). Compare points A-D to letters A-D in figure 2.

  Fig.5: Simulations. Dashed curve corresponds to the sideband phase psd when PLL is inactive. Bold black curve corresponds to the simulated curve for the PLL demonstrator as prepared.

  Comparison of simulated (dashed line) and measured (solid line) phase power spectral densities. No additional phase noise.

  Hz SSB phase psd in dBc/Hz PLL inactive, ∆f = 80 kHz PLL active, ∆f = 80 kHz (b) Measurements, PLL active and inactive. GN modulation with ∆ f = 80 kHz. Phase noise suppression of 40 dB in the proximity of the center frequency.

Fig. 6 :

 6 Fig.6: Measurements with and without GN modulation, PLL active and inactive.

  , simulation σ rms =1.52°, simulation measurement σ rms = 1.50°σ rms = 0.21°F ig. 7: EVM analysis emulated choosing ∆ f = 80 kHz. Figure 6(b) shows two SSB phase psd curves measured on the LSB for the active and the inactive PLL.