Dr Nicolas Zerounian

Dr Clement Tavernier

Dr Clément Tavernier

Dr Didier Celi

Mr Nicolas Derrier

Mr Franck

Dr. Alain Chantre

Eloy Ramirez

Amad Driss

Eric Tea

Xing Liu

Lei Cao

Anne-Sophie Grimault-Jacquin

Sebastien Gallois-Garreignot

Loic Loisel

Zahi Essa

Floria Blanchet

El-Mehdi Bazizi

Pierre Boulen

Vincent Fiori

Vincent Quenette

Romuald Roucou

Olivier Saxod

Amina Sidhoum

Julien Singer

Papa Benoit Sklenard

Momar Souare

Assawer Soussou

Pascal Tannhof

François Waquant

Alban I Zaka

Cecilia Mezzomo

Giancarlo Castañeda

Natalia Ruiz

Birahim Diagne

Davide Garetto

The present work investigates the technology development of state-of-the-art SiGe and SiGeC HBTs by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT device very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, better understanding of charge transport, and facilitate the development and optimization of SiGe and SiGeC HBT devices.

The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.

In this work we will work with the successive evolutions of B3T, B4T B5T technologies. For each new device f MAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz respectively.

Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for f MAX and the carrier transport in extremely scaled HBTs.

Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation. viii Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.

Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase f MAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of f MAX . ix Résumé "Recherche et développement de transistors bipolaires avancés par le biais de la modélisation technologique" Le travail porte sur le développement et l'optimisation de transistors bipolaires à hétérojonction (TBH) SiGe et SiGeC par conception technologique assistée par ordinateur (TCAD). L'objectif est d'aboutir à un dispositif performant réalisable technologiquement, en tenant compte de tous les paramètres : étapes de fabrication technologiques, topologie du transistor, modèles physiques. Les études menées permettent d'atteindre les meilleures performances, en particulier une amélioration importante de la fréquence maximale d'oscillation (f MAX ). Ce travail est la première approche développée pour la simulation des TBH SiGeC qui prend en compte l'impact de la contrainte et de la teneur en germanium et en carbone dans la base; conjointement pour les simulations des procédés de fabrication et les simulations électriques. Pour ce travail, nous avons développé et implémenté dans le simulateur TCAD des méthodes d'extraction de f MAX prenant en compte les éléments parasites intrinsèques et extrinsèques. Nous avons développé et implémenté un modèle pour la densité effective d'états en fonction de la teneur en germanium et en carbone dans la base. Les modèles pour la bande interdite, la mobilité et le temps de relaxation de l'énergie sont calibrés sur la base de simulations Monte-Carlo. Les différentes analyses présentées dans cette thèse portent sur six variantes technologiques de TBH. Trois nouvelles architectures de TBH SiGe:C avancés ont été élaborées et proposées pour des besoins en basse et en haute performances. Grace aux résultats obtenus, le meilleur compromis entre les différents paramètres technologiques et dimensionnels permettent de fabriquer un TBH SiGeC avec une valeur de f MAX de 500 GHz, réalisant ainsi l'objectif principal de la thèse.

Introduction

Since the 1990s, thanks to the rapid progress of the technology used for manufacturing silicon germanium based heterojunction bipolar transistors (SiGe HBTs), this has gradually replaced the III-V compound devices technology for their typical applications [Böck]. This is mainly due to the high performances reached by SiGe based devices, and the compatibility between the SiGe and silicon materials which allows to build them in a conventional substrate beside to CMOS circuits (BiCMOS technology), keeping similar cost of manufacturing.

BiCMOS technology offers high volume production and generates an attractive market for applications in the millimeter wave range. Recent studies have shown that this market is in the strong growth, and this trend will continue in coming years [Dotfive]. To meet this demand several semiconductor manufacturers have among their objectives to increase performances of the SiGe and SiGeC HBT devices.

This objective calls for devices operating with f MAX of about 500 GHz, a challenging task to achieve, where important improvements are needed, leading to the increase of the involved costs. Finding a suitable process for the fabrication of an integrated circuit is a long and costly operation. IC processing takes a relatively long time: a test run may involve hundreds of different process steps and the execution of a process in the clean room may take several weeks.

Moreover, the optimization of a process requires a large number of such runs in which each time the value of a relevant process is changed. The development time for a process can be considerably reduced if results are predicted with an efficient and reliable modeling. In the past, such predictions have been made solely on the basis of experience, but this procedure may lead to an inefficient practice of trial and error if the results are not accurate enough.

The simulation of one or more process steps with a computer offers a valuable tool to improve the reliability of these predictions. Process and device simulations thus offer an attractive and cheap alternative for lengthy test runs and experiments in clean room.

This work stems from the harmonious work between in semiconductor research in private company and in academic world to achieve individual devices and integrated circuits with higher operating speed, enabling realization of new applications at very high frequency. This work has been carried out in collaboration with the TCAD Modeling Department of STMicroelectronics at Crolles, and the research team EPHYCAS (études physiques de composants aux hautes fréquences) of the Institut d'Electronique Fondamentale at the Université Paris-Sud, Orsay.

In this work existing HBT architectures are investigated by means of TCAD in order to reinforce the agreement with the electrical measurements of this technology and with the support of the early technology process development done in the ST manufacturing unit at

Crolles.

The capabilities of the existing architecture are evaluated to extend the operating conditions to 300 GHz and beyond. The influence of each region of the device is investigated in order to evaluate how much each part of the process/architecture contributes to performance and to push further the limit of this technology by TCAD means. This work is carried-out in synergy with the technology development team and a TCAD-based solution will be manufactured.

The fourth phase of the project consists in the development of a new HBT architecture able to bridge the step in frequency towards 500 GHz in strong collaboration with the process development team.

Chapter 1 1 Silicon Bipolar and Silicon-Germanium-Carbon Heterojunction Bipolar Transistors

The invention of the bipolar transistor at the Bell Telephone Laboratories by Shockley in 1948 [Shockley 49] [Weiner 73], and the demonstration of its practical feasibility and its amplifying action by Bardeen and Brattain in 1949 [Bardeen 49], marked the beginning of the microelectronics industry. The advantages of this three-terminal device over the vacuumtube diode were: the smaller size, much less power consumption, better electrical performance, better reliability and lower prices. Initially, germanium was predominantly the material used during the fabrication and later silicon took over almost completely.

The natural advantages of silicon are: highly earth abundant, excellent thermal properties, diamond lattice structure, nontoxic and highly stable, excellent mechanical properties, highquality dielectric easily grown on, etc. It has made it the most important material of the semiconductor industry. Silicon has been one of the most studied materials, technical and technological expertise has been acquired through many decades. However comparing compound semiconductors and heterostructures for RF and microwave circuit applications, the use of germanium comes to play; thanks to silicon-germanium compound the siliconbased technology can be even more improved.

Nowadays SiGe technologies are considerably developed enabling the improvement of the performances without abandoning the silicon technology. The main characteristics of the SiGe material with respect to silicon are its lower energy bandgap and the possibility to control it by varying the germanium content. The addition of germanium into silicon technologies to build SiGe heterojunction bipolar transistors enable to practice bandgap engineering. To make possible the design of energy band discontinuities and spatial gradient in the base, leads the improvement of the statics and the dynamics properties of the transistor [ Kasper 93] [ Arndt 98].

Later, the bandgap engineering has been enhanced by using carbon in very thin base SiGe HBTs. Incorporation of carbon in SiGe diminishes the mechanical stress generated by germanium [Lanzerotti96], promoting the mechanical stability of the strained layer, this thanks of the carbon lattice constant which is much smaller than that of silicon or germanium. The mains interest of carbon is to limit the diffusion of boron dopant atoms and make possible the confinement of dopant atoms in a thinner base layer which improves the transistor performance [Osten97].

SiGeC HBTs are generally integrated with MOS transistors in the BiCMOS technology. This co-integrates bipolar and CMOS devices in such way as to combine the advantages of both creating new circuit options and leads to high performance circuits. In the current marketplace a large number of commercial products using SiGe HBTs are available, and today market options for SiGeC HBTs include:

 Automotive [ Demirel 11] [ Lehmann 11]  Microwave Power Circuits [Joseph 11] [Xiao Ying 09] [ Van Noort 08]  High-speed interconnects [ Tillack 11]  High Speed Wireless Communication [ Rucker 10] [Viswanathan 08]


 Space [Lan Luo 11]  Imaging [Ojefors 11]

Bipolar Junction Transistor Theory

The bipolar transistor is a three-layer semiconductor device consisting of either two n-type and one p-type or two p-type and one n-type layers of material. The former is called an npn transistor, while the latter is called a pnp transistor. In a npn transistor (most HBTs) the three semiconductor regions are: emitter (n-type), base (p-type), and collector (n-type). As it will see shortly, charge carriers of both polarities (electrons and holes) participate in the bipolar transistor operation, which is the reason for the name bipolar. The npn transistor consists of two pn junctions, the emitter-base junction and the collectorbase junction. In normal operation the emitter-base junction is forward-biased while the collector-base junction is reverse biased, which means that the potential barrier between emitter and base is reduced while it is increased between collector and base. As a result a large number of majority carriers will diffuses across the forward-biased np junction into the p-type material, leading to the emitter current as depicted in Figure 1.2. Since the sandwiched p-type material is very thin and lesser doped compared to the heavily doped emitter, a large fraction of electrons injected from the emitter reach and cross the collector reverse-biased junction creating the collector current. Reaching the n-type material electrons become majority carriers. Only a small percentage of all electrons flowing through the base-emitter junction can recombine with the less numerous holes in the base, forming the very small base current.

Terminal Currents

To illustrate transistor current components in an npn bipolar transistor operating in the forward active mode, let's examine what happens inside. Below we will describe the various components of emitter, base and collector currents illustrated in Figure 1.3. The resulting base current is therefore the following:

rB rG pE B I I I I    (1.2) c) I C , Collector current components:
The collector current I C is mainly defined by the larger number of majority carriers (electrons) diffused through the base region toward the collector, that is:

rB nE nC B E C I I I I I I      (1.

Trous

I pe

Holes I pe

In the following paragraphs we describe the transistor currents based on the semi-classical Boltzmann transport equation (BTE) and the drift diffusion approach is presented later in section 1.3.

Collector Current

The dependences of the injected minority-carrier concentrations on the applied junction voltages can be obtained by using the Boltzmann expressions for the carrier concentrations and the behavior of the quasi-Fermi levels in the device.

The current density is proportional to the product of the carrier concentration and the gradient of the quasi-Fermi level. Intrinsic carrier concentration in silicon is defined by: (1.4) with N C and N V the conduction band and valence band density of states, respectively, and E G the bandgap. In the case of the SiGeC base layer of the HBT this is:

(1.5) Collector current can be expressed according to the drift-diffusion model. Let us consider a homogeneously doped base region within the transistor. In this region the electric field is relatively small and negligible outside the space-charge-region (SCR) and the diffusion term only of the electron current is: (1.6) The relation between electron concentration and the applied junction voltage is:

(1.7) Substituting (1.7) into (1.6) gives:

(1.8)
where is defined by (1.9) thus the collector current as a function of emitter area and base width is:

(1.10)

Base Current

Similarly to the situation in a diode, the hole current flows from the base (p-type region) to the emitter (n-type region) due to a gradient in the hole concentration between emitter and base. This concentration gradient is caused by recombination of electron-hole pairs in the emitter layer and at the interface. In the case of base current the current density is:

(1.11)

The relationship between hole concentration and the applied junction voltage is:

(1.12)

After of substituting (1.12) into (1.11) and with we obtain the expression for base current as a function of emitter area and emitter width (thickness of the emitter layer W E ):

(1.13)

Current Gain

The levels of I C and I B in the common emitter configuration are related by the current gain which is defined by the following equation:

(1.14) for a SiGeC HBT this is:

(1.15)

In a SiGeC HBT the current gain is highly depending on the germanium percentage mainly because of the exponential dependency on the bandgap difference between the emitter and the base. In this case, this is poorly influenced by the base and the emitter thickness, and modestly influenced by the doping levels of the base and emitter layers. There is a trade-off between the current gain and the base resistance which limits the frequency response.

Doping of the base should be high enough for a low base resistance, without out-diffusion of p-dopant into the emitter, and the base layer should be thin enough for a small transit time through it.

Collector-emitter breakdown voltage (BV CEO )

The The critical electric field depends on the material doping level e.g. for = 10 5 V.cm -1 the breakdown voltage in common base is around of 5 V.

As shown in Figure 1.4, the BV CEO value is the voltage where the base current is zeroed.

This is an important parameter for the transistor design since its value limits the maximum voltage that can be applied to the transistor in common emitter. There is a trade-off between the BV CEO and the current gain as showed in Figure 1.5, the former is inversely proportional to the latter. The best BV CEO value cannot be obtained simultaneously with the higher current gain value. For the SiGeC HBT devices studied in this work BV CEO is about 1.5 V. High BV CEO requires low collector doping and thick collector SCR, and low collector transit time requires the opposite configuration.

BV CEO

Current

Gain

High-Speed Devices

BV CEO

High-Voltage devices

SiGeC HBT vs Si Bipolar Transistor

The bandgap engineering used in the design of SiGeC HBTs is the key of considerable static and dynamic performance enhancements. The effect of SiGe on the base-bandgap and transport properties can be advantageously used in the bipolar transistor to provide a higher collector current and reduce the carrier transit time. As SiGeC alloy has a lower bandgap than Si, a bipolar transistor could be created with SiGeC in the base to obtain much higher values of current gain. To understand the differences between the SiGeC HBT and the Si BJT the band diagrams of both are compared in Figure 1.6. In a SiGeC HBT band diagram, the valence band is much more impacted than the conduction band, therefore there is a stronger difference in this band with respect to Si BJT.

According to the band alignment between Si and SiGeC, the valence band produces step discontinuities (step of about 50 to 250 meV depending on the Ge fraction) while the conduction band produces very small spikes discontinuities (less than 30 meV).

For a fixed applied voltage at the emitter-base junction, SiGeC base leads to lower the energy barrier for electrons, which enables a higher carrier injection. Hence collector current is stronger than in the case of a silicon bipolar transistor at the same bias as is plotted in The effect of the bandgap discontinuity in the emitter-base junction was described by Kroemer who showed that if the bandgap in the emitter was wider than that of the base, the minority carriers moving from emitter to the base will see a lower barrier than the minority carriers injected from the base to the emitter, inducing an exponential augmentation in the current gain [Kroemer 57].

The grading of germanium in the thin base can generate large electric fields. If we use a linear Ge profile with a peak of 10%, in a 50 nm of base width, this yields 75 meV over 50 nm i.e. 15 kV/cm of electric field; such quantity can accelerate the minority carriers up to 1x10 7 cm/sec (saturation velocity). This means that the frequency response will be considerably improved because of the electrons transit time reduction.

High Frequency AC Operation

The two main figures of merit related to the dynamic characteristics in transistors are the transition or unity gain cut-off frequency (f T ) and the maximum oscillation frequency (f MAX ), with f MAX more sensitive to extrinsic parasitic elements [Shi & Niu 2005]. In the last part of this section we will describe the different methods of extraction for f MAX which we develop for the AC simulation. These techniques are also used for determinate f T .

Two Port Modeling

Typically a HBT device is connected to different parasitic elements as resistances and capacitances. In order to calculate the transistor performance, the dependence on the parasitic elements must be calculated. It can be made including the parasitic elements in the circuit analysis. Nevertheless, this approach requires a new analysis each time that one element is changed. In order to simplify this procedure, the HBT device behavior is modeled as a two-port equivalent network. Figure 1.8 shows the two port network used during our HBT SiGeC mixed-mode simulations. The two-port network model is used for circuit analysis to separate portions of larger circuits. This is as a black box where the properties are defined by a matrix of numbers. In a two-port network, one port denotes the device input access and the other the output access.

In our simulations we define the elements to be analyzed by the two port network. Thus depending on the study to be performed, or to compare the accuracy of results, a simulation region is defined.

In Figure 1.9 if the black dashed box is considered, only the intrinsic HBT is simulated and the parasitic elements need to be added at the end of the electrical simulation. These elements are extracted by TCAD simulations from dedicated structures combining the different metal layers of the back-end and allow the de-embedding of the device characteristics during the measurements analysis.

Intrinsic device simulation window Usual simulation window

Typically for a more complete simulation the set-up is established as schematically shown by the red dashed box of Figure 1.9, where most important parasitic are already taken into account by the TCAD simulation of the complete HBT device. The small signal analysis carried out by the electrical simulator calculate for each bias (V i )

and for each frequency the conductance (A) and capacitance (C) matrices which can be linked to the admittance parameters:

(1.23)

Admittance parameters can be converted to the other two-port parameters as S, Y, Z or Hparameters.

Carrier Transit Time

Total transit time is related to the variation of total minority carriers charge in the device with a variation in the collector current with the emitter-collector voltage constant:

(1.24)

The contributions from emitter to collector regions to the total transit time can be obtained by (1.32)

Definition of the Maximum Oscillation Frequency

The maximum oscillation frequency is the frequency where the unilateral power gain is equal to 1. The highest transistor ac power gain is achieved when the output is terminated with an impedance that is the conjugate of the output impedance. Using nodal analysis in Figure 1.10 we obtain the collector and base currents:

(1.33)

(1.34) For the case of a conjugate-matched load the power gain is define by, ( Substituting and solving the equation for will result in the following:

(1.40)

In the above equation we can see that f MAX is strongly dependent on the base resistance and on the base-collector junction capacitance . From equation (1.40) we can deduce a trade-off between f T and f MAX . If the base width is made smaller; the base transit time is reduced. This leads to the enhancement of f T but degrades f MAX because the increase of .

Extraction Methods for f MAX

When the device is represented by a two-port network it can be characterized by several power gains that depend on its adaptation as input and output, among the different definitions for the extraction of f MAX available in literature we found: the Mason unilateral gain (MUG or U), the transducer power gain (GT), the maximum available gain (MAG), and the maximum stable gain (MSG). In our studies we use the Mason unilateral gain (1.41) which is the most widespread in literature. It can be extracted from relatively lower frequencies.

(1.41)

Chapter 1. Silicon Bipolar and SiGeC Heterojunction Bipolar Transistors

20

Below it is presented briefly the methods that we used to develop advanced TCL-based scripts to extract f MAX from the small-signal simulations generated by our TCAD tool.

f MAX Extraction with a Full Frequency Sweep

For an ideal extraction of f MAX , U could be a function of frequency with a flat level at low frequencies and falling off with a -20dB/decade slope at higher frequencies as illustrated in This method is time consuming and its result can deviate from the real f MAX value at high frequencies. As the previous method, this is computationally expensive because the large frequency range.

f MAX Extrapolation at a Fixed Frequency

In this method only one frequency point is required. In this method for each DC operating point only one frequency is compute. The script developed, first find one point at which the gain has dropped from the flat low frequency region. Next, assuming that the -20dB/decade slope has been reached, the script extrapolates from this point the frequency value for U = 0dB as shown in Figure 1.14. This is similar to previous method in the fact that after to localize the -20dB/decade region f MAX is obtained by extrapolation. In all cases, we assume that the gain-bandwidth product is constant or the fall-off is with a -20 dB/decade slope. For one measurement frequency in the fall-off region, we can write: where the measurement frequency or the defined frequency for extrapolation. This technique is only valid if is located in the -20dB/decade slope region.

Definition of the current gain cut-off Frequency

The transition frequency f T represents the frequency where the AC current gain h 21 in common emitter configuration (sometimes appearing as h fe or β ac ) drops to unity i.e. 0dB, this is depicted in Figure 1.15. This is an important figure-of-merit for the characterization of the high-frequency properties of the transistor.

AC Current Gain Determination

To calculate f T first we must to know the AC current gain h 21 . This is obtained from a simple equivalent circuit of the intrinsic transistor in common-emitter configuration. The equivalent circuit, called hybrid-π, is used to best represent the transistor high frequency region behavior in Figure 1.17.

Figure 1.17 Equivalent circuit model used for the h21 derivation.

SCR

From a node equation we obtain the collector and base currents:

BE BC BE m C v C j v g i    . (1.45) (1.46)
The AC current gain is obtained by combining (1.45)

m Diff BE BC g h j C C C    (1.48)
The magnitude of common-emitter AC current gain versus frequency is shown in Figure 1.18. The transition frequency f T exists if, at a given DC operating point exists a frequency domain where the small-signal common-emitter current gain h 21 can be written where is the low frequency small-signal current gain, is the -3 dB cutoff frequency. The transition frequency f T , also indicates the frequency at which the current gain is less than unity and the transistor is no longer useful as an amplifying or a switching device. From the -20dB/decade slope in Figure 1.18 it follows that the frequency at which h 21 drops to unity, is given by (1.52)

The AC current gain can also be obtained through two ports network, for Y-parameters this is given by:

(1.53)

The methods to determinate the cutoff frequency, are similar to those explained for f MAX extraction. The characteristics of U are equivalents to h 21, both have a constant value at low frequency followed by a -20dB/decade fall-off region.

Carrier Transport in Extremely Scaled SiGe HBTs

In this section we investigate about the important phenomenon of electrons and holes transport and the most important models to describe it. Such models are an essential and necessary tool to perform accurate TCAD simulations for SiGeC HBT devices. The simulations performed during our studies are based in many of the equations present here;

consequently the results achieved are directly linked to some models of this section.

Transport Phenomena in Bipolar Devices

A bipolar transistor formed a complex physical system. In presence of an external force as electric field, carrier concentration gradients or thermal gradients, the free carriers are displaced and a current results. Because of this external force free carriers are no more in equilibrium and must interact with different scattering mechanisms; producing a unique and complex system of electrical behavior. Such system makes the understanding and the prediction of the transistor behavior a major challenge. A first approximation is the arrangement of mobile charges within the transistor energy band and can be seen as a gas of non-interacting charged particles which execute Brownian motion (Figure 1.19). Fixed charges also play an important role in the bipolar device; despite they cannot participate in current. Small movements in its position yield the dielectric response.

Additionally those charges are also responsible for polarization effects.

To model the behavior of the bipolar transistor we have to use a set of equations describing the interactions of free carriers with the different scattering mechanisms and an adequate method to solve these equations. For this reason, it is necessary to use different models which make possible to describe the physical phenomena. Device engineers needed analytic techniques and software tools, to support their design efforts. Therefore physical

Electric Field Collision (a) (b)

Collision

Collision models need to be simplified to reduce the computation costs in the numerical simulations.

The modeling of transistor behavior became an important field which has, and continues to make, a considerable contribution to the progress of transistor development.

Hierarchically, transport models can be arranged on one side in microscopic models and macroscopic models and on the other side as semi-classical models and quantum models [Jüngel 01] [Ramirez- Garcia 11]. Transport models can vary considerably in ease and accuracy of solution: these can be physically very sophisticated but difficult to solve and time expensive or easy and fast to solve but with inaccurate results. Figure 1.20 shows different levels of modeling from the most accurate with few physical assumptions but the most difficult to solve, to the less accurate with many physical assumptions but the most practical to solve. In semiconductor structures whose dimensions are in the nanometer scale with quantummechanical properties, the limitation of the classical drift-diffusion and of the Boltzmann transport theories are surpassed and must be replaced by quantum-mechanical models.

The quantum approach is used in a vast field of research activity for high-speed electronic and optoelectronic nanometer devices as superconductors, molecular conductors, carbon nanotubes, the high electron mobility transistor (HEMT), the modulation doped field effect transistor (MODFET), injections laser diodes, single electron GaAs nanostructures and quantum dot lasers.

On the other hand the relatively large size of a practical device and the high complexity of quantum transport, this is an open boundaries multi-particle interacting system with various types of scattering, leads to calculations which are not computationally attractive [Schöll 98].

Moreover, extracting measurable quantities from such results is a non-trivial task.

The Semi-Classical Boltzmann Transport Equation (BTE)

In presence of an electric field the energy distribution of electrons and holes is affected and they are no longer in thermal equilibrium (0 K). Consequently their distribution over energy is Semiconductor BTE-based equations are used in most of the current device models, where the dimensions of device geometry are greater than 100 nm (de Broglie wavelength).

The Boltzmann transport equation is used to describe the statistical distribution of particles in a gas or fluid. BTE provides a description of an electronic system in terms of single particle distribution functions ƒ(r, k, t) which is the probability that at time t and position r a particle has a momentum k [Jüngel 09]. This can be written as (1.54) where f is the distribution function of occupation of states, with being the rate of change of f at fixes values of r and k. The distribution function is equal to the sum of three terms: a collisions term with account for its interactions with scattering phenomena, a force term with account with the effect of an external driving force on particles, and a diffusion term with account with the effect of diffusion on particles from one region in space to the other.

(1.54)

A large number of difficulties exist to solve directly the Boltzmann equation since it is an integro-differential equation, analytical solutions rarely exist except for a few simple and usually unrealistic cases [Chen 95]. To obtain result drastic approximations must be make.

Using entropy arguments it is possible to derive functional form for ƒ(r, k, t) but this requires a lot of computing power and it is far from being of practical value to a transistor designer [Snowden 98]. The major benefit of the BTE is that it provides a platform from which approximations can be made to derive more tractable equations. This technique is very useful to develop conceptual models as it closely matches the model with the microscopic behavior of the semiconductor. Additionally it is relatively easy to include high order physical effects such as the full band structure and a wide range of scattering models. Though very computationally intensive and complex the method is probably the only one viable for examining accurately high energy carrier phenomenon as impact ionization or ballistic transport.

The Monte Carlo Method

Hydrodynamic Transport Model

The hydrodynamic transport model (HD) is the model which we use in our simulations, since its high documented and the accuracy is almost similar to most advanced models, while its computation time is far better.

For devices with base width less than de Broglie wavelength, which is our case, nonstationary phenomena neglected in the drift-diffusion model, impact the transistor electrical behavior. In drift-diffusion formulation it is assumed that in presence of a high electric field free carriers instantly reach the drift velocity and that the temperature is close to that of lattice. These assumptions are valid for slowly varying spatially electric field, but in small dimensions devices, as state-of-the-art HBTs, abrupt changes can occur in the transistor base. Under these conditions we must take into account free carriers acceleration and calculate carriers' temperature as an independent variable.

In addition, if the electric field variation is of the order of the mean free path new phenomenon such as velocity exceeding the steady-state drift velocity (velocity overshoot) and absence of any collisions during short periods (ballistic transport) is considered in HD. In the case of extremely scaled HBT electron transport within the base-collector depletion region is quasi-ballistic and with presence of velocity overshoot [ Hong 09].

Even if the Boltzmann equation could be solved, it would generate the full momentum distribution of free carriers at every point of the device. Most of time, such a detailed view is not necessary. To generate a set of equations easier to solve, it exists a mathematical technique which make possible to extract features of an equation or function. Having a function g(k) we define the nth moment (M n ) as:

(1.55)

The first moment of (1.55) gives the median value, the second the variance. If more moments are calculated, more complete is g(k). In the case of Boltzmann equation the first three or four moments generate a set of equations called the hydrodynamic (or energy balance) equations [Gough 94]. This system of equations can be solved using numerical methods to find the energy and carrier density in all regions of the device.

On the other hand the more precise calculation of the temperature, the velocity and of the carrier concentration is necessary for an accurate analyze of hot-carrier effects. This phenomenon is due to free carriers with a temperature greater than lattice temperature or with a kinetic energy greater than the equilibrium value. It should be noted that if temperature and energy are qualitatively similar, they are equivalents concepts only near equilibrium [Schöll 98].

Since the work of Stratton [Stratton 62] and Bløtekjaer [Bløtekjaer 70], there have been many

variations of the hydrodynamic model. As the equations structure of hydrodynamic model is similar to drift-diffusion model, this can be numerically solved by an exponential-fitting scheme [Mahan 90]. The full formulation includes the so-called convective terms [Benvenuti 91].

Let us consider now the Boltzmann equation for charge carrier transport in semiconductors:

(1.56)

Where:

ƒ(r, k, t) is the probability of finding a particle at position r, with momentum k at time t, the group velocity, the external force on a charge particle q placed in and electric field E, the scattering operator.

In addition to the Poisson equation:

( The term is the equilibrium energy density and the lattice temperature.

For Fermi-Dirac statistics, , with (1.70)

(1.71)
where is the Fermi integral of order ½.

Drift-Diffusion Transport Model

The drift-diffusion model (DD) is the most commonly used for simulating semiconductor devices and is the base of our explanations of the bipolar transistor currents in section 1.1.1.

The drift-diffusion equations are obtained by taking the two first moments of the Boltzmann equation. This is the most basic and one of the simplest of all device transport models. Because of the large number of assumptions introduced [Baccarani 77], the drift-diffusion model is only appropriate for fairly long devices where the electric field is small compared to the mean free path, i.e. devices with applied voltages much smaller than 1 V and length scales not much smaller than 1 µm.

Conclusion

This chapter has reminded first the DC electrical behavior of the bipolar transistor. A discussion was done about the BiCMOS technology and the need of high-speed transistor for RF and millimeter wave applications. This is possible with the introduction of the germanium and after of the carbon into the base of the transistor to make possible heterostructures and HBTs in the widely used, reliable, Si-based microelectronic technology.

Like compound semiconductor technologies, bandgap engineering is possible, and npn SiGeC HBTs benefit of material properties to reach high operating frequency. The main interests of SiGeC alloys are the lower bandgap energy compared to silicon, and the possibility to control the bandgap by varying the germanium and carbon content. In heterojunction bipolar transistors (HBT), a compositionally graded SiGeC layer builds the base of the device, grown on a thin Si buffer layer to constitute the collector region, and followed by a Si-cap layer for the emitter.

This chapter is dealing with definition of physical parameters necessary for HBT modeling.

Description of SiGeC strained alloys requires a set of material parameters that can have been developed independently in the literature. This chapter provides and discusses a synthesis set of parameters such as several mass, bandgap energy, band discontinuity, mobility and relaxation time in SiGeC strained alloy and discuss their implementation in the commercial software used for device modeling. No physical calculations based on Quantum mechanics and condensed matter physics have been made in the frame of the present work.

Most of the time, weakly out of equilibrium carrier populations are addressed and classical near band edge approximation is done (involving parabolic or non-parabolic anisotropic bands).

Film Growth and Material Properties of SiGeC Alloys

At 300 K, the different lattice constant of silicon (5.43Å) and germanium (5.65Å), leads to a 4.2x% lattice mismatch with x being the germanium content. Despite of this relatively large mismatch and of difficulties to form a heterojunction, a thin layer of SiGe is grown on Si thanks to the strained layer epitaxy. The strained material gets different properties than the relaxed SiGeC alloy and enables the use of bandgap engineering.

Band discontinuities are well defined if the in-plane lattice constant is preserved across the interface in a pseudo-epitaxy of the SiGeC alloy on the silicon wafer. Strain can be uniaxial, biaxial or hydrostatic; uniaxial or biaxial strain splits the bands, hydrostatic strain shift the energetic position of the band as is depicted in Figure 2.1. The schematic illustration of strained Si 1-x Ge x C y crystal lattices in Figure 2.2 depicts the growth and properties of strained layers. In the case of the epitaxial growth of a SiGeC alloy on a silicon substrate, the modification of the Ge content and of the C content leads to layers with a lattice constant larger or smaller than that of the Si substrate. If the epitaxial layer has a larger lattice constant (a layer ) than the lattice constant of the silicon substrate (a sub ), the layer is with a biaxial compressive strain. Otherwise a biaxial tensile strain is obtained when the epitaxial layer has a smaller lattice constant than silicon substrate.

Since the lattice constant of SiGeC alloys with low carbon content is higher than that of silicon, the SiGeC layer in the HBT is under a biaxial compressive strain. This leads to anisotropic transport properties, and transport parameters of both electron and hole charge carriers will be affected.

Properties of pure Silicon, Germanium and Carbon relaxed crystals are shown in Table 2.1.

Compositional and strained layers influence significantly the transport of charge carriers through the device. The rigorous modeling of carriers transport must consider these parameters to simulate their impact on the device behavior. In advanced tools as Monte Carlo (MC), the effects induced by the stress and the composition of the material are inherently taken into account in the band structure and in interaction models.

Band structure

The electronic structure of semiconductor is fundamental for SiGeC layer modeling. The state of an electron in a solid is determined by its energy and wave function, and the sum of energies establishes the band structure of the solid. The band structure leads to the value and the behavior of transport parameters such as the mass, the density of states, the mobility and the energy relaxation time of carriers. It determines the static and dynamic properties of the carriers in the material. Some consequences in varying layer composition and strain may have opposite effect on these parameters. For instance with the reduction of the effective mass and of the density of states (see section 2.3.3), the collector current diminishes too but at the same time it leads to the increase of the carrier mobility.

Predictive simulation of SiGeC HBT with the base layer biaxially strained on Si, requires to take into account the combined effects of the ternary alloy specific properties, and of the biaxial stress induced by the lattice mismatch.

Electron and Hole Effective Masses

The experimental determination of the effective mass of electrons and holes is quite complex since it implies expensive and difficult cyclotron resonance studies [ Cressler 03].

For this reason an experimental set of effective mass values as a function of doping and of germanium percentage is not available in literature. Effective masses are key parameters for the TCAD simulator. In Sdevice simulator the effective masses define the mass density of states and the mobility which impact all the electrical characteristics of the transistor.

For the percentages generally used for germanium and carbon (up to 30% and 2%, respectively), SiGeC strained alloys have physical properties that are close to those of pure silicon and can be analyzed as Si-like alloys.

Electron Effective Masses

In order to clarify the different definitions found through the literature for the effective mass in this section we presented the definitions for: 1/ the density of states (DOS) effective mass The biaxial compressive strain effect on and is illustrate in Figure 2.4 where the longitudinal ellipsoids have flatter bands and the transverse have a larger curvature.

The band structure of the SiGe alloy includes six degenerate conduction band minima located along the (100) or Δ axes for Ge content lower than 0.8. This produces a repopulation of electrons between the transverse and longitudinal valleys [Pejcinovic 89].

This is important because when an applied electric field is aligned along a (100) axis, the effective mass induces variation of the SiGe mobility compared to the mobility in silicon.

Thus in the in-plane direction, perpendicular to the direction of the growth, the heavy longitudinal electron mass leads to a lower electron mobility. On the other hand in the out-ofplane direction, the effective mass is reduced, and a higher electron mobility is expected and, therefore, higher current densities.

(a) (b) Table 2.2 shows the value of electron effective masses for silicon and SiGe relaxed alloy. It cannot be seen an important variation for and . This is explained by values of and close from each other in both materials. In fact to generate a stronger impact, the SiGe layer should be in uniaxial or biaxial strain.

Hole Effective Masses

Hole masses in silicon are divided into three components: heavy holes (HH), light holes (LH) and split-off holes (SO).The curvature of their respective band structures is compared to the case of SiGe in

Effective Density of States

The density of states (DOS) function measures the number of available electronic states at each energy level, for the conduction band is given, and in the frame of parabolic band, by

[Sze 03]: 2.3
assuming that all available states in the conduction band can be represented by an effective density of states N C depending on temperature, a mathematical simplification can be made using Boltzmann approximation (Equation 2.7). By similar arguments an equivalent expression N V is found for the valence band (Equation 2.8).

The

Effective Density of States Models

In this section, new MC-based analytical models for effective DOS in SiGeC devices are presented. These models are elaborated for simulation purposes with SiGeC strained and relaxed layers. N C and N V are given as an analytical function of the germanium and carbon content, temperature and strain-related effects. The study of for SiGeC alloys is far insufficient in literature and TCAD device simulators are lack of accurate effective DOS models for this kind of devices.

The MC-based calculation for the effective DOS approach used in present work was also used by Sasso, Rinaldi, Matz, and Jungemann [ Sasso 10], but theirs models not take into account critical dependencies as the strain-related effects and ignore the carbon content.

Others models are a simplified approximation, lying in a constant ratio between the product of the effective DOS for silicon-germanium and silicon Strain related effects are defined by a strain-compensation parameter described in [Michaillat 09]:

2.5

If z<0 the material is under compressive strain and if z>0 it is under tensile strain while for z=0 the alloy is exactly strain-compensated.

The Figure 2.11 shows the value of z as a function of Ge and C content, and underlines for instance that carbon content of about 1.1% can compensate the strain induced by 20% of Ge. The reduction of the diffusion mechanism on the effective alloy potentials, which results from the decrease of the density of states at low energy induced by the biaxial strain, is modeled by a multiplicative factor depending on [Michaillat 10.2]:

2.6

If the strain parameter is zero, value is unity. When the strain increases tends asymptotically to the limit value . is introduced in equations 2.9 and 2.10 and allows to takes into account the fluctuations of the alloy scattering due to the biaxial strain. The calibrated values for and are reported in Table 2.4.

N C z > 0 z < 0 0,01 0,01 2.7 1.3 N V z > 0 z < 0 0,05 0,05 3,2 2,1
The SiGeC models for effective DOS of the conduction and of the valence bands are formulated as a function of the silicon effective DOS through the well-known expression

Bandgap

The energy gap of a semiconductor is the difference between the conduction and valence energy bands. Si and Ge are both indirect bandgap semiconductors, their bandgap energies are 1.12 eV and 0.66 eV respectively. In SiGeC alloys bandgap energy depends on germanium and carbon percentages and to a lesser extent on temperature and doping level (if doping level is high).

Band Offsets

Band discontinuities occur in the conduction band and the valence band due to the addition of Ge in Si and mainly by the strain. Biaxial strain is known to alter both the conduction and valence bands of Si. For a pseudomorphic growth of SiGe along the [001] direction on Si substrates, the biaxial strain causes a tetragonal distortion which shifts and splits the conduction and valence bands modifying strongly the material's energy bandgap.

All the publications dealing with the subject conclude in a unanimous way that the band gap reduction due to the Germanium is most strongly reflected on the valence band than on the conduction band [ The values of were modeled by People [People 86] by the relationship:

2.11

where denotes the Ge content in the epilayer and , denotes the Ge content in the substrate.

SiGeC Bandgap Model

In our simulations the bandgap reduction with Ge and C content is modeled using the Bean formula [ Bean 92], which describes the variation of the bandgap for SiGe alloys compressively strained. The opposite effect on the strain of SiGeC due to C content is added and the bandgap is approximated with:

y c x c x c x c T T E T y x E g g 4 3 1 2 1 1 2 0 ) , , (          2.12
Where Eg 0 defines the bandgap of Si bulk at room temperature, is the Ge concentration and the linear term represents the C concentration. Parameters of the analytical formula are shown in Table 2.6.

The effective bandgap taking into account the reduction due to bandgap narrowing (detailed later) is simply calculated from the previous standard bandgap as: The variation of the bandgap with germanium and carbon percentage, following the equation 2.12 is illustrated in Figure 2.15 and Figure 2.16. A few carbon content is able to compensate a larger Ge content. For a germanium content of 25% and a carbon content of 0%, compared with silicon the bandgap reduction is 220 meV, and for 25% of germanium and 1% of C the reduction is only of 170 meV.

bgn g eff g E T y x E E   ) , , ( ,

2.13

Bandgap Narrowing in SiGeC HBTs

In literature two terms are used concerning the heavy doping effects on the bandgap: the real bandgap narrowing (BGN) and the apparent bandgap narrowing (aBGN). About this Based on these studies we are going to clarify the two terms since they play an important role for SiGeC HBTs simulation. The use of two values must be consistent with the bandgap model discussed previously; otherwise, it can produce false results [ Shi 03]. The two terms depict the same phenomena: the reduction of the bandgap energy. The division of this reduction on the valence and on the conduction band is also discussed.

At high impurity concentrations (>10 19 cm -3 ) the band structure of silicon is noticeably distorted. As a consequence, its physical properties differ from the standard values considered for lowly doped material. Since HBTs contain highly doped regions, notably emitter and base, heavy doping effects have not negligible impact on the device performance.

Impact on Carrier Statistics

In order to explain the existence of the two BGN and the impact of the distribution of the BGN between the conduction band and the valence band, a brief review of the Fermi-Dirac and of the Boltzmann statistics is done.

Unlike to the Boltzmann statistic, the Fermi-Dirac statistic can take into account degeneracy effects. This becomes important at high doping levels. In HBTs, the two statistics will give different number of carriers and different results.

With the Fermi-Dirac distribution the number of carriers occupying a conduction band state or a valence band state at thermal equilibrium can be written as

2.14

When the states in either case have energy of several kT away from the Fermi level, then this equation can be reduce to the following Boltzmann distribution for electrons in the conduction band and for holes in the valence band, respectively

2.15

The number of electrons or holes is named the intrinsic carrier concentration

Electron and Hole Mobility in Heavily Doped SiGeC strained Layers

For the present work, we used the anisotropic analytical models based on low-field MC

Contributions to the Mobility

Mobility is an important transport parameter to consider as it affects directly the collector current, the base current, the base transit time, the base resistance with recombination and the leakage currents. Mobility results from scattering mechanisms, and it is defined as the ratio of the average or the drift velocity of moving carriers under low value of applied electric field. For devices operating at the room temperature or above, the main scattering events involved in mobility regime are:

-Phonon scattering

SiGeC Mobility Models

In our simulations we used analytical mobility models based on MC simulations for SiGeC alloys [Michaillat 09, 10.1, 10.2]. These models give a response for low electric field that happens mainly in ohmic regions of the HBT, and in the neutral region of the base where the electric field is low and until non-local phenomena such as carriers' overshoot velocity occur.

These models are valid for materials with carbon content up to 2% and with germanium content up to 50%. Compared to the isotropic mobility for relaxed SiGeC alloys, these models treat separately the in-plane and the orthogonal components of the anisotropic mobility tensor relevant to the biaxial strain.

In order to implement these models in HBT simulations we have tested the different mobility components and compared the results with the literature data. We have found a good agreement for all components except for the silicon electron mobility which we have calibrated. In following sections a deeper description of those models will be given.

Phonon scattering

In an undoped semiconductor, scattering caused by collisions between carriers and phonons is the dominant mechanism.

Impurity scattering and new mobility model for SiGeC alloys

The scattering of carriers by impurities plays an important role in determining the behavior of HBT, this is primarily due to the large number of impurities presents in the emitter and base layers.

Compared

120 0 0 3 3
The term is the saturation mobility which modulates the carrier mobility at high doping concentrations, it is different for silicon and germanium as expressed in 2.27 through the terms and . The mobility model in equation 2.28 includes the combined effects of germanium and carbon incorporation in silicon, namely: Mobility degradation caused by the alloy scattering, strain anisotropy of SiGeC layers in biaxial compression, and strain compensation when the lattice parameter of SiGeC is the same to that of the silicon substrate.

2.27

Energy Relaxation Time

In the hydrodynamic equations of the device simulator the energy relaxation time noted for electrons is introduced in Eq. 2.28 which is a sub-equation of the collision formula 1.62 of chapter one. The same expression is valid for holes interchanging the subscript n with subscript p [Sentaurus 12]

2.29

The relaxation time of the carrier energy is a parameter that quantifies the time required for a population of excited carriers to return to equilibrium. Thus, the relaxation time characterizes the ability of the material to dissipate the energy of carriers through inelastic interactions of carrier-phonon or impact ionization types. This parameter is therefore a property of transport

Effect of Transport Models on the HBT Behavior

The influence of transport modeling on device behavior is shown by comparison between two sets of hydrodynamic simulations. We compare two distinct models of transport parameters: the SiGe default models of the physic based device simulator (SDevice), and the SiGeC specific models implemented in the same simulator.

The simulated device is the SiGeC npn HBT of the B3T technology and it will be deeply depicted in chapter 3. The base epitaxy is formed by a Si/SiGeC stack with a thickness of about 40 nm which 20 nm of SiGeC base. The Ge graded profile increases from the emitter side up to collector side, varying from 20 to 30%. The C content is less than 1% within the same region.

The use of a hydrodynamic simulator incorporating an exact description of the electrical parameters, enables taking into account the germanium, carbon and dopant profiles.

Otherwise the unique characteristics of SiGeC HBT will be ignored leading to incorrect results. The hydrodynamic numerical method implemented in the device simulator used in this work has already been explained in previous chapter. The high frequency behavior represented by f T and f MAX in Figure 2.25 and Figure 2.26 was also significantly enhanced with the use of SiGeC advanced models. In the case of f T , is the default device simulator model leads to underestimation while the SiGeC specific models give results closed to measurement due particularly to the electron mobility µ n . For f MAX a higher difference is found between both models with the default model underestimating the f MAX value. This is explained by the hole in-plane mobility which is higher when considering the positive impact of the strain obtained with SiGeC models, helping to reduce the base resistance and to profit to f MAX . The f T peak is of 255 GHz for I C = 14 mA and Vbe = Vce = 0.86 V, the f MAX peak is of 352 GHz for I C = 7.63 mA and Vbe = Vce = 0.83 V.

Conclusion

In this chapter we studied the electrical simulation and the transport modeling of SiGeC HBTs. We carried out a work of synthesis leading to the selection, implementation and development of models which could not exist until now. It was shown how the predictive simulation of SiGeC HBT devices with the base layer biaxially strained on Si, requires taking into account the combined effects of the ternary alloy specific properties, and the biaxial stress induced by the lattice mismatch. In our simulations we worked with the first anisotropic analytical models based on low-field MC simulations for SiGeC alloys.

It was shown the importance of transport properties in electrons and holes as the effective masses, density of states, bandgap, mobility and energy relaxation time. We demonstrated how effective masses of electrons and holes are key parameters to largely explain the transport in strained SiGeC alloys. It was demonstrate the main components of electrons and holes effective masses and their respective models were studied. It was also demonstrate the differences between the effective masses for conductivity calculations and the masses for density of states calculations.

In this chapter we presented new MC-based analytical models for effective DOS in electrons and holes. We elaborated these models for SiGeC strained and relaxed layers simulation purposes. It was seen how the existing effective DOS models not take into account critical dependencies as the strain-related effects and ignore the carbon content.

We analyzed the impact of the germanium content and the incorporation of C atom of the strained base layer on major physical parameters and how it affects the electrical parameters and improves significantly the transport of charge carriers through the device leading to anisotropic transport properties.

It was reminded the impact of carrier statistics and the bandgap narrowing models and how this can produces important issues and false results during its implementation. At the end of the chapter the benefit of the SiGeC transport model is underlined in comparison with the SiGe default models of the physic based device simulator, leading in the last case to underestimation of the real HBT performances.

Chapter 3 3 TCAD Simulation of Advanced Terahertz

SiGe and SiGeC HBTs

Simulation Context and Objective

Technology Computer Aided Design (TCAD) has become an important tool for the development and optimization of new semiconductor technologies. Accurate TCAD uses dedicated models for the technology process to simulate each process step and dedicated models to simulate the device physical and electrical behavior.

Over the years, models have been enhanced jointly with the technological progress, using new materials, structures and reducing the overall device dimensions for higher operation speed. The accurate device modeling mainly depends on two aspects: 1) the ability to describe the real device structure, 2) the physical model used to simulate the electrical behavior of the device.

For the first aspect, the structure can be completely drawn according to structuraldimensional characterization of the real device. This can result of the modeling of the fabrication processes as deposit/growing, etching, implantation, annealing through the TCAD simulation. For the second aspect, the results could be accurate or not depending on the ability of the physical models used to take into account for instance all the complex behavior of the charge transport through the HBT layer. The design flow starts with a precise layer stack determination obtained with 1D process simulation. The lateral dimension of the HBT is simulated with a 2D process simulation. Finally, some other aspects to consider for right results such as extrinsic capacitances are included. The main objective is to model 1D and 2D process in the advanced ST technology where vertical and lateral dimensions of the HBT core is pushed to sub-micron and nanoscale.

The simulated device was released in the framework of the Dotfive European project

[Dotfive] where one objective is obtaining a HBT which reaches a maximum oscillation frequency (f MAX ) of 500 GHz. The simulation of each processing step of the process flow leads to an accurate prediction of the active dopant distribution, stress distribution and device geometry of the SiGeC HBT.

In this chapter, we explain the TCAD simulation project for B3T devices, which constitutes the baseline for more advanced TCAD platforms B4T and B5T in the next chapter. The description of the device technology named B3T is done, illustrated with structures obtained from process simulation. Models used for diffusion of doping species versus layer composition are discussed, followed by the introduction of the simulation process flow. The methodology used for calibrate model parameters is exposed and simulation results are compared to measurements made in real devices. The impact of some technological parameters (boron doping level, carbon and germanium contents) on doping profiles or on electrical performances is analyzed. Finally, simulation results are compared to fabricated B3T devices.

B3T Technology

B3T is a bipolar process technology derived from the latest high-speed 0.13-µm BiCMOS

B3T process fabrication

The front end of line of the B3T fabrication process is shown in Figure 3.2. The main steps of this HBT fabrication process is also illustrated in On a p-type silicon substrate, the process starts with the deposition of a thin oxide layer to keep out dirt, followed by an arsenic implantation to form the n+ buried layer. After the removal of the oxide a lightly doped n-type layer is deposited to form the collector. The active area of the transistor is then isolated and defined by the formation of the shallow trench isolation (STI) (Figure 3.4). To contact the collector buried layer and avoid a highresistivity area between the buried layer and the contact area a n+ implantation (SINKER) is performed (Figure 3.4). This is followed by the CMOS well implantation, the definition and opening of the bipolar area. The pedestal oxide layer is deposited, followed by a P doped poly-base and a stack of oxide/nitride layers (Figure 3.5). Once etched selectively, the pedestal oxide is used to prepare the intrinsic base region and the connection with the extrinsic poly-base layer. The base growth is followed by the emitter spacers' formation (Figure 3.9) and the polyemitter deposition (Figure 3.10). The final device is defined by the poly-emitter and poly-base patterning (Figure 3.11), and finalized with the spike activation and the cobalt silicidation. Then, tungsten plugs and via are processed, and the subsequent BiCMOS 6 levels metal back end of line is addressed to high-frequency circuits.

Spike activation anneal

Simulated Structure

The Figure 3.12 illustrates the 2D device structure generated with the TCAD tool. As detailed in previous sections, the HBT results from a double-polysilicon FSA (Fully Self-Aligned), with a boron-doped SiGe:C base, and one arsenic-doped mono-emitter. The collector module is formed by a n+ buried layer, a collector epitaxy and a selectively implanted collector (SIC). The Figure 3.13 focus the view on the core of the HBT, showing more finely the different region of Si, SiGe:C, oxide, nitride and poly.

B3T Mask Layout

Each photolithography step required to manufacture a 0.13µm technology (CMOS devices, HBTs, passive components, interconnect) needs one specific mask. The front end of line for B3T-HBTs requires 8 mask levels. A brief description of these levels follows, in appearance order of the manufacturing process:

• Nburied: At the start of process, it defines regions in which implantation of the collector buried layer will be performed.

• DeepTrench: This mask allows the implementation of deep trench isolation (DTI) for isolating the device from adjacent semiconductor devices.

• Sinker: This photolithography step defines the regions of the collector wells (implantation dose under the contacts).

• BipOpen: It opens up the gate polysilicon in areas where will be fabricate bipolar transistors.

• SIC: This mask defines the zone where will be carry out the selective implantation of collector. It is not used if SIC implantation is performed in the emitter window.

• Polybase: It serves to limit the lateral extent of the extrinsic base (polybase) of the device. • PolyEm: This is the last specific mask of the HBT processing; it defines the emitter polysilicon. This mask must not extend outside the polybase and must include the emitter window. It has to be wide enough to accommodate the emitter contact and must to leave the polybase surface large enough to place the base contacts.

B3T TCAD Project

The development of this TCAD simulation platform is based on the STMicroelectronics advanced BiCMOS technology for SiGe and SiGeC HBTs. The objective is to control process parameters, leading to simulation results with static and dynamic characteristics of the NPN HBT, the figures of merit and first order parameters commonly used for performance comparisons. not take into account all the process steps. In our approach the dopant position is defined not only by the 1D profile but also by all process steps which should lead to obtain a behavior closest to the real device behavior. All this leads to an accurate prediction of the active dopant distribution, of the stress distribution and of the device geometry. The correct simulation of the process fabrication is assured by SiGeC specifics process models which describe the diffusion of boron and arsenic in SiGe and SiGeC alloys.

Today it is possible to find several models for a same phenomenon and no model for some phenomena. For instance the transport model for the particle flux of dopants in the process simulator counts on seven different models, while there is not a defined model for the arsenic diffusion in SiGeC alloys. Besides the accuracy of each model is limited and each model requests basic parameters that depend on measurement and on the ability to extract them.

Many models are only valid and work for a specific device and under specific conditions after a TCAD calibration. Such models cannot work when operating conditions are out of the domain used during calibration. Such calibrated models are not predictive tools and are not useful to detect device problems or to improve the device technology. Nevertheless, such calibrated models are very useful for device optimization because of the so many parameters on which we can acts to reach specific performances.

The architecture and the process flow of the HBT is quite complex. The diffusion of doping species (boron, arsenic) in and out of the strained SiGeC layer, and of polycrystalline materials (emitter, extrinsic base layer), during the process, has not been precisely studied experimentally. Then different TCAD parameters must be added to model diffusion according to the semiconductor physics.

Composition and Dopant Diffusion Modeling

Carbon Content

Carbon is valence isoelectronic to both germanium and silicon and may crystallize in a diamond structure. There is a conduction band offset between silicon and SiC enabling bandgap engineering and the exploration of different types of strain Since its lattice constant is considerably smaller than that of silicon (3.57 Å) carbon incorporation in substitutional site on SiGe is of great importance to compensate the compressive strain in SiGe layers grown on silicon [Schmidt 98] and thus relax the critical thickness constraint on SiGe layers.

Carbon incorporation in SiGe alloys

The finest boron profile is reached only with carbon incorporation. For high doped devices requested for high dynamics performances such f MAX , the widening of the doped base layer due to the increase of the boron doping level is limited with carbon deposition in the same time.

Silicon, germanium and carbon form crystals purely covalent in which the atoms of the lattice are not electrically charged, and are randomly distributed [Logan 64]. At thermodynamic equilibrium, the solubility limit of carbon in silicon is very low. However SiGeC alloy layers having carbon content exceeding 1% is commonly done by low temperature epitaxy. Indeed, the C incorporation limit is far more significant in the first deposition layers, and the nonequilibrium thermodynamics growth of the crystal let to maintain the same limit value at the surface within the volume of the sample to achieve high concentrations of carbon [Tersoff 95]. Indeed, the introduction of the carbon in SiGe has a double impact on the bandgap. It induces a lowering of the conduction band reducing the value of the bandgap. But, in opposite, due to the partial reduction of the layer biaxial strain on the silicon substrate, the bandgap value is increased. This strain effect is more important than the effect of the carbon on the conduction band [ Brunner 97], thereby the bandgap of SiGeC alloys increases with C content [Hull 99].

Carbon Diffusion Effect on the Base Width

The SIMS profiles in Figure 3.16 and Figure 3.17

Dopant Diffusion in SiGeC Alloys

Unlike of III-V and II-VI alloys, the atoms in column IV of the periodic table are chemically similar and physically compatible. Thus, obtaining group-IV semiconductor alloys can be done more easily avoiding common problems of heterogeneous compounds such as partial miscibility of atoms, atomic order in small and large scale in the material, or the phase stability of alloys during the thermal treatment.

As previously mentioned the use of carbon to trap self-interstitials is one of the techniques used to reduce the impurities diffusion. Many quantitative studies have shown that a substitutional carbon atom can capture on average a little more than one interstitial atom of silicon [Cacciato 96] [ Cowern 96] [ Cristiano 97]. Consequently in silicon, the formation of the complex will cause a significant decrease of the interstitial concentration reducing the dopant diffusion.

Along with oxygen carbon is one of the most investigated electrically inactive impurity in silicon, this because it is present in significant concentrations after the crystal growth our experiments (less than 2%) we will interested to substitutional carbon , for this quantities the effect is negligible.

In our simulations the carbon diffusion depend on the percentage of germanium and carbon, it is given by: 3.1 In thermodynamic equilibrium, the two carbon configurations are examined separately. The limits of solubility in thermodynamic equilibrium and diffusivity of the two types of carbon are summarized in Table 3.1. silicon. This describes the interaction with carbon interstitial point defects ( ), such that:

3.3

The dissociative Franck-Turnbull mechanism is the second equilibrium relation to consider. It depends on vacancies:

3.4

The limit of solubility of the two carbon configurations is low and remains well below the impurity concentrations usually used in microelectronics. This low value is close to the detection limit of the characterization tools.

The reactivity flow of point defects in thermodynamic equilibrium is defined by: 3.5

3.6

The points defects and and are compared in Figure 3.18. 1.E-04

1.E-02

1.E+00

D(Cs)x[Cs eq] D(Ci)x[Ci eq] D(V)x[V eq] D(I)x[I eq]
During the diffusion of carbon in silicon in thermodynamic equilibrium the flow of point defects is bigger than the flux of carbon. When the carbon diffuses by kick-out and Frank-Turnbull mechanisms, the rejected point defects are instantly replaced due to the high mobility of interstitial and vacancies. Then the carbon diffusion in silicon is carried out with same mechanisms as other impurities (e.g. boron), it has no effect on the point defects concentration. This is defined by: 3.7

Non-equilibrium diffusion of carbon can occurs with concentrations up to several orders of magnitude higher than those of the limit of solubility. This kind of diffusion confers to carbon specific action properties on point defects and their concentrations. Indeed, the high concentration of substitutional carbon creates a significant imbalance of the "kick-out" phenomena. The equation 3.3 leads to increase the concentration of interstitial carbon and a high sub-saturation of interstitial point defects, such as: and 3.8

Thus, when an enough concentration of substitutional carbon is reached the following inequality is obtained:

3.9

Boron Diffusion in SiGe and SiGe:C Alloys

The shape of the boron doping profile is determinate by its diffusion on SiGe alloys and the

Modeling of Boron Diffusion in SiGe and SiGeC Alloys

The modeling of the dopants diffusion mechanism is quantified by a single parameter called the fraction of interstitial, . The fraction of interstitial is the ratio of the diffusion using interstitial mechanisms to the total diffusion, in steady state conditions. When impurity diffusion is only due to the interstitial mechanism is equal to 1, while equals 0 for impurity diffusion only due to vacancies.

The modeling of the boron diffusion in SiGe alloys is assumed to be purely an interstitial diffusion mechanism. Thus the fraction of interstitial mechanism for boron is equal to 1 and its diffusion is expressed by combining the concentration of their point defects and the effect of the coupling boron-germanium : In SiGeC alloys the boron diffusion is given by:

( ) [ ] ( ) ( ) [ ] (0)
  ' 1 1 ) 0.042 ( BGe Ge B I I g Ea SiGe X Q Q Q E K      

3.19

where is defined in equation 3.1.

B3T Simulation and Calibration

The B3T calibration work is performed comparing the simulated device to the real device.

The different simulation parameters and their impact on dopant profiles, on geometric structures and on electrical characteristics are analyzed and compared to measurements.

Simulated dopant profiles are compared to secondary ion mass spectrometry (SIMS) measurements, geometric structures are compared to TEM pictures and simulated electrical results are compared to the device characterization results.

The calibration process is a methodology which can involves more than thirty parameters which most of the time are dependent upon one another. Consequently the modification of one parameter can impact all the others.

The Process Simulator

In the Sentaurus process simulator (Sprocess), the different fabrication steps are introduced in a Sprocess command file. This file is the main input for the process simulator, containing all the process steps and it can be edited according to user specifications. For instance, the following command is used for the NBuried implantation:

The mask coordinates are parameterized using the Emitter Window variable "W".

Etching and Deposition Simulation

The etching and deposition speeds and directions are obtained from experimentally determined rates and geometric considerations. The simulation is performed by MGOALS algorithms in the process simulator [ Sprocess 12]. Both operations are simulated using geometric shapes and mathematical formulations. In 1D and 2D simulations, meshes are generated after every geometry operation of etch and deposition.

In the MGOALS library the starting structure is analyzed for the interfaces that will change during the operation. Afterwards, the geometry-changing operations are performed and finally the entire structure is re-meshed. During re-meshing, nodes in the silicon region are retained as much as possible in their original locations. In most cases, a high percentage of the nodes are retained after re-meshing which minimizes interpolation errors.

The MGOALS algorithm places mesh points as instructed by the user. Afterwards, the elements are created using a modified Delaunay-meshing algorithm. The meshes generated within are refined adaptively, statically, or as a combination of adaptive and static refinements. The refinements are specified within four major types of refinement box: field based (adaptive meshing), mask based, uniform (standard) and interface.

All these refinements are user controllable. In addition, the MGOALS mesh engine enforces mesh smoothing to limit the changes in element size from one element to the next one. This smoothing is important for accuracy and for convergence especially at intrinsic base and boundaries.

Mesh refinement is a two-step process. First, the refinement box is defined. Second, the mesh is refined when the next re-mesh occurs either with an explicit grid re-mesh command call or during standard geometry modifications, or native layer formation.

All refinement boxes have refinement criteria that add mesh and constraints that can be used to limit where the mesh refinement occurs. One type of refinement criteria is available for each type of box, and it essentially defines the box type. The refinement criteria and, therefore, the refinement box type are static or adaptive depending on the simulated region.

For instance for the L spacers we use a standard static refinement box. On the other hand we use the adaptive refinement for STI and for poly-base which accurately capture the entire evolution of a static mesh and is less time consuming.

In 2D, MGOALS uses either an analytic method or a fast level-set method to perform boundary-modifying operations. In general, the analytic method is faster, uses less memory, and more accurate. However, it cannot handle deposition step in concave regions or etching step of convex areas when there are boundary collisions and self-intersections.

a) Etching

In the case of etching three main specifications are required: the mask specification for the etch type, the material to be etched and the amount of material to be removed. Etching may be considered as a negative deposition in the topographic simulation, because nodes are removed from the structure instead of being created.

In 2D, all etch types have been implemented within the process simulator using three

b) Deposition

For deposition, the analytic method, the fast level-set method, and the full level-set method are available. In 2D, the analytic method is the preferred method, and the level-set method is used when the analytic method is not possible when a front collision is detected.

In a newly deposited region, constant field values can be initialized. For isotropic deposition, a piecewise linear solution fields can be defined as a function of the distance from the original surface.

To define the deposition type, the parameter anisotropic, isotropic, fill, or fourier must be specified. To specify the thickness of the deposited layer for isotropic and anisotropic deposition, the parameter thickness may be specified, or the rate and time parameters.

Besides the deposition type and thickness, the material to be deposited must be also specified.

Diffusion

During the fabrication process, the diffusion and the distribution of dopants through the The process simulator uses the Alagator language which allows the modification of diffusion models. This language had been used for implement and modified the SiGeC diffusion models.

Oxidation

The thermal oxidation of silicon is performed in three steps in the process simulator: -1-Diffusion of oxidants (H 2 O, O 2 ) from the gas-oxide interface through the existing oxide to the silicon-oxide interface, -2-reaction of the oxidant with silicon to form new oxide and -3motion of materials due to the volume expansion, which is caused by the reaction between silicon and oxide.

The equation of oxidant diffusion is solved using the generic partial differential equation (PDE) solver of Sentaurus Process. For the simulation of thermal oxidation, there are two requirements: The silicon or polysilicon region which is in contact with the gas or an oxide region, which, in turn, is in contact with the gas and the diffuse command which specifies a reactive atmosphere.

If silicon or poly-silicon are in contact with gas at the beginning of a thermal oxidation, an initial oxide layer is created automatically. The default thickness of this layer is 1.5 nm but it can be modified according to user preferences.

1D Process Simulation

One-dimensional simulations are performed in order to obtain accurate layer profiles of dopants under the emitter window. The base epitaxy is formed by a Si/SiGe:C/Si stack with a total thickness of about 50 nm. Boron doping and carbon incorporation is done during the epitaxy only in the central part of the SiGe layer. Ge content follows a graded profile, with 20% to 30% from the emitter side to the collector side of the SiGe base. The SiGe thickness is typically of 20 nm. During the growth and the final thermal annealing, the diffusion of doping species gives broader layers than those deposited. All aspects are simulated, according to the process flow. The growth of the base is finished with a silicon cap layer, which forms the mono-emitter, after deposition and diffusion of As doped poly-silicon. The process simulation is calibrated with SIMS measurements which provide emitter-base and collector-base junction accurate delineation. Figure 3.20 gives a comparison between the SIMS profile of an HBT and the simulation of the corresponding process flow.

We could remind that C content lower than 1% allows to block the boron diffusion, enabling a higher doping level in a thinner base layer [ Lanzerotti 96] [ Rucker 97]. Such a thin base helps improving the HBT electrical performance.

2D Process Simulation

The 2D simulation of the transistor is also performed to accurately calculate collector and sinker profiles formed by implantation-diffusion in silicon. Figure 3.21 shows the final structure obtained from TCAD according to the B3T technology process flow. The 1D and 2D simulations are gathered for the species and doping profiles, and this structure will be used for electrical simulation. The correct definition of the lateral profile (junction widths, doping levels in the connection region) is of the same great importance than the vertical layer profile. One of the limitations for the increase of f MAX is linked with the peripheral part of the emitter junction, the part of the base resistance between the extrinsic and the intrinsic base layers. For 2D process simulation, the whole HBT architecture is build. High-speed HBT are often in CBEBC configuration. For 2D electrical simulation, only half of the structure is considered and the middle of the emitter window is a symmetry axe.

In the 2D process simulation we consider all the process steps in order to be as close as possible to the real process seen by the HBT we study. The combination of the different masking steps and the different deposition and etch steps leads to the simulation of the HBT architecture. For the 2D architecture calibration, the most important steps are the definition of the emitter window by an etching step and the thickness of the different oxide and nitride deposition and etching steps.

The 2D simulation file includes four important doping profiles:

a) The NBuried profile is generated by a high dose arsenic implantation followed by a 0.3 micron epitaxy to form a highly doped layer beneath the active zone of the device and reduces the collector resistance.

b) The Sinker profile is defined at the collector contact zone and is a highly doped phosphorus implantation set to minimize the resistance between the NBuried layer and the surface contact.

c) The SIC implantation is an arsenic profile implanted by a dedicated masking step or in the emitter window before the emitter poly deposition in fully-self aligned HBTs to reduce the collector vertical resistance and optimize the High-Speed (HS) HBT. In the 2D process simulation both the 2D implantation and diffusion of this profile are simulated.

d) The extrinsic base profile is formed by the diffusion of a highly doped boron implantation in the base poly and the 2D diffusion of the boron in the active silicon is important for the base resistance of the device.

The last step of the 2D process simulation is dedicated to the generation of the contacts used in the device simulation. The emitter contact is set on top of the polysilicon emitter, the base contact is set at the poly base surface and the collector contact is set at the Sinker.

Electrical Simulation

After the accurate 1D and 2D process simulation towards a predictive TCAD simulation, the physical models of the electrical simulation are upgraded to account for the impact of the SiGeC strained layer on the different electrical characteristics of the device. Figure 3.23

shows the structure simulated electrically, with a meshing density adapted to HBT.  The f MAX (I C ) curve for the good evaluation of the dynamic device parameters and parasitic capacitances and resistances.

Collector Current Calibration

The first curve to calibrate is the collector current as a function of emitter/base bias voltage.

For this calibration, parameters to consider are following:

a) Emitter area: The collector current is directly proportional to this parameter. This is defined by the emitter window patterning, the emitter spacers and the TEOS oxide cap.

b) Base doping: This is fixed by the parameters of base epitaxial layer (i.e. doping levels of carbon, boron, arsenic and germanium) and is specified in the 1D process command files. Nevertheless, the area of the emitter junction is of the same importance for the collector current magnitude. c) Emitter/Base junction: This is controlled by the boron and arsenic doping levels, its diffusion in SiGeC alloys and the thickness of the base and Si cap. d) Germanium content: In a graded profile the most dominant region of the germanium epitaxy is that close to the emitter. This determines the collector current slope and has an important impact on all electrical properties of the transistor.

Base Current Calibration

The epitaxial boron layer leads to a very thin base region. The base current is mainly due to the recombination of few holes at the emitter interface, that have managed to cross the valence band discontinuity of the emitter-base junction. Consequently it is fixed by the recombination velocity of holes at the emitter contact. This parameter is tuned in the device command file of the simulator. At high current injection, the extrinsic base resistance can have an impact as it is only controlled by the 2D diffusion of boron from the base poly.

Transition Frequency Calibration

The calibration of this curve is performed taking into account the following regions: The collector implantation being well controlled, the NBuried layer and arsenic diffusivity in the 2D process command file are the key calibration parameters.

BV CEO Calibration

The collector-emitter breakdown voltage (BV CEO ) curve is calibrated studying carefully the base/collector doping profile and the model parameters driving the number of carriers generated by impact ionization at high collector bias voltage. This is defined by the avalanche generation within the hydrodynamic transport model of the simulator Sdevice

Impact of process parameters

In this section, the impact of the boron doping level, carbon and germanium percentages on B3T technology is analyzed. We have selected these three parameters because of their The analysis is performed for high doping levels in the emitter and base, which are used in state of the art HBTs. Process parameters are tested on a typical B3T SiGeC HBT with an emitter window of 0.25 um and with an emitter width of 130 nm, at room temperature.

Effect of the boron doping level

Boron Diffusion Effect on the Base Width

It should be noted that, in B3T devices, the highly-doped base avoids the risk of base punchthrough in very small thicknesses (base width W B ) and reduces the base resistance. One consequence of the boron doping level is the effective base width. As shown in Figure 3.24, a higher doping level produces a larger base thickness, this occurs because boron profile becomes wider and the positions of the junctions are shifted toward the emitter and the collector region. Diffusion direction is highlighted with arrows in the figure. A significant increase of f T can be obtained with low base doping in SiGe HBT, with high current gain maintained with heterojunction, and low transit time in narrow base layer.

We have observed for the boron doping values studied that, the reduction of its values had a positive impact, even with the rise of base resistance. The benefit of the increase of f T is higher than the increase of the base resistance for the increase of f MAX for B doping values down to 5×10 18 cm 3 where f MAX starts to decrease.

Carbon Content

Carbon Diffusion Effect on the Base Width

The 1D doping profile of Figure 3.28a shows the reduction of the boron diffusion with the addition of carbon. For a same B doping level (5×10 19 at/cm -3 ), the increase of the C content leads to a higher boron peak and to a narrower base. Figure 3.28 shows this effect for three different contents of carbon. Thus a content of 0.01% leads to a base width of 28 nm (Figure

Influence on Frequency Performance and Current Gain

Impact of carbon on the electrical characteristics is directly linked to its impact on the boron profile. Thus an increase of the carbon content leading to a sharp boron profile, impacts electrical characteristics in a similar way than variation on the doping level.

Results shown in Figure 3.29 and Figure 3.30 for a boron doping level of 5.10 19 at/cm 3 illustrate the improvement of f T , f MAX and of the current gain when the carbon content increases. For a carbon increase from 0.01% to 0.1%, f MAX increases by 24%, and the gain increases by 32% (Figure 3.29). It should be noted the rise for f T from 253 to 274 GHz when the C percentage rise from 0.05 to 0.1% respectively. In B3T technology the percentage of carbon used has allowed to reach 350 GHz and 260 GHz of f MAX and f T respectively. The increase of the HBT performances is allowed by the selective epitaxial growth (SEG) of the SiGe:C base, with the constraint of an adequate growth rate to incorporate carbon into substitutional site and not in interstitial site. Compared to SiGe epitaxy, the growth rate needs a higher temperature, but it leads to the increase of substitutional incorporation.

On the other hand when carbon content is too high, no more beneficial impact is observed

Germanium Profile Effect

Germanium profile has an important role in the improvement of the HBT behavior; Silicon-Germanium material epitaxy brings the bandgap engineering for silicon based bipolar technology. Sandwiched into silicon, the strained SiGe base layer gives better carrier transport properties, providing a new degree of freedom for designing bipolar transistors, with higher values of cut-off frequency and f MAX .

The bandgap engineering is applied in HBT by means of triangular, trapezoidal or rectangular germanium profile. B3T technology works with a graded germanium profile which has basically a trapezoidal shape. This type of profile creates a gradient in the conduction band which accelerates electrons injected from the emitter to the collector, leading to a shorter base transit time. The Ge profile is obtained by epitaxy following a stairstep pattern with three steps from 20 to 30%. We call the first step GeE (emitter side), the second GeB (base) and the third GeC (collector side).

Effect of Germanium Percentage at the Emitter Side (GeE)

Figure 3.31 shows the influence of different Ge percentages (GeE) on the Gummel plot, and on the transition frequency f T . The germanium fraction at the emitter side GeE varies from 10 to 25% with 25% for GeB and 30% for GeC. The increase of GeE leads to an increase of the current gain, of the collector current density at fixed V BE , and of the f T values.

Effect of Germanium Percentage in the Middle (GeB)

For GeB it varies from 20 to 30% with GeE and GeC constant at 20 and 30%, respectively.

Figure 3.32 shows the increase of f MAX with the increases of GeB, reaching its maximum value for GeB = 30%.

Current gain is also improves with the increasing GeB. The best value is also obtained for GeB = 30%. The effect of GeB on f T is negligible with a weak improvement for GeB = 25%.

The base wide of HBT remains constant and thus the impact on base transit time is weak. The reduction on the germanium percentage at the middle of the base has a low impact on the electrical characteristics. Variations on GeE and GeC are more useful to generate the gradient in the conduction band.

Effect of Germanium Percentage at the Collector Side (GeC)

For the last study the GeC percentage is varied from 25 to 35% with GeE and GeB constants at 20 and 25%, respectively. The Figure 3.33 and Figure 3.34 illustrate the impact on Gummel plot and on f T and f MAX . The best results for f MAX , f T and the current gain are obtained with GeC = 30%, above this value the electrical characteristics are degraded. Results obtained show the importance of controlling doping profiles on HBTs. The germanium profile has an important role in the improvement of the device behavior. Small changes in Ge profile can produce a significant improvement on device operation. Thus SiGeC base leads to a better carrier transport properties, giving a new degree of freedom for designing bipolar transistors, with higher values of f T and f MAX .

GeC=25 to 30%

a)

GeC=30 to 35% b)

Electrical Results

Static Characteristics

Mixed-mode simulations performed on the HBT final structure are compared to experimental measurements. The comparison is shown on main figures of merit: Gummel plot in Figure 3.35, I-V characteristic in Figure 3.36, unity current gain transition frequency in Figure 3.37;

and maximum oscillation frequency in Figure 3.38. At a first instance, TCAD simulations are compared with measurements of a B3T technology device with an emitter window of 0.25 um and a base thickness of 20 nm. In order to obtain result for the layers close to the 1D SIMS profile, the process parameters which have been tuned for this calibration are the boron diffusion coefficient, the silicon cap thickness, Ge percentages at the collector and emitter side and the C percentage.

Dynamic Characteristics

Confidence has been brought by the simulation of a device of the same technology but with an emitter open window of 0.5 um. The simulate device take into account the extrinsic contribution of main parasitic elements including the emitter/base capacitance, the collector/base oxide capacitance and the emitter, base and collector resistances. Furthermore the emitter/base back-end and collector/base back-end capacitances are introduced from measurements. Figure 3.37 illustrates f T versus I C for two different devices of B3T technology, one with an emitter window of 0.5 um, the other with 0.25 um. For first device the peak of f T is 270 GHz and for the second device it is of 260 GHz, in second device f T is impacted because the increases of R E . For W = 0.25 µm the f T peak is of 255 GHz for I C = 14 mA and V BE = 0.86 V. Finally the base-emitter and base-collector capacitances are represented in Figure 3.39 versus the reverse voltage V EB and V CB , respectively, for a B3T technology device with an emitter window of 0.25 um. Values obtained for C BC and C BE at V CB = 0 V and V EB = 0 V are 17.2 fF and 25.5 fF, respectively.

Conclusion

This chapter explains the B3T TCAD simulation project for B3T devices. This project constitutes the baseline for more advanced TCAD simulations as B4T and B5T described in the next chapter. B3T takes into account the impact of the strain, of germanium and carbon content into the base, both into the process and into the electrical simulations. Static and dynamic characteristics of a B3T HBT can be simulated and major figures of merit and first order parameters commonly used are extracted for performance comparisons.

The different features developed for the B3T process were implemented toward the transistor down-scaling, while maintaining the specificity of the ST self-aligned process technology. For this simulation project we introduced new layout rules, new base doping profiles, new SIC profile, new poly-base patterning, and new spike annealing temperature. These simulations take into account each step of the process flow leading to an accurate prediction of the active dopant distribution, of the stress distribution and of the device geometry.

The impact of the boron doping level, of the carbon and of the germanium percentages on the B3T technology were analyzed. We demonstrated how these three parameters have a strong impact on electrical characteristics of SiGeC HBTs and how adequate values are able to improve significantly the transistor performance, and how wrong values can degraded it.

Diffusion models used for the dopant diffusion in SiGeC alloys were detailed showing the importance of using carbon to trap self-interstitials in order to reduce the impurities diffusion.

The best trade-off between f MAX and f T is reached with 350 GHz and 254 GHz, respectively, with a germanium percentage of 20, 25 and 30% at the emitter side, in the middle of the base and at the collector side, respectively.

In the end we compare mixed-mode simulations with measurements showing that the final HBT structure is validated. The simulated device takes into account the extrinsic contribution of main parasitic elements including the emitter/base capacitance, the collector/base oxide capacitance and the emitter, base and collector resistances.

Chapter 4 4 Optimization towards f MAX 500 GHz

This chapter presents three different architectures of advanced SiGe:C HBTs. In these architectures we take advantage of the good results obtained from B3T TCAD simulation kit which it is used as the baseline of models and simulations. The goal of the two first architectures is to propose alternatives which could be used for applications with lower performance requirements. The third architecture is to analyze promising solutions for the increase of frequency performances for the development of most advanced devices.

At first instance a low cost HBT architecture is presented. For this architecture, the impact of the collector-base capacitance is analyzed as well as the collector doping level. Later a study is performed to investigate one problem detected concerning the emitter spacers deposition during the process fabrication.

The RF performances of the three architectures are compared and the most efficient of them (B4T transistor) is used as the baseline for developing a more advanced device. The B4T architecture has been manufactured and it is deeply studied in this chapter. We analyze the impact of the main fabrication steps in order to find the keys process parameters that allow to increase f MAX without degrading other important electrical figures of merit.

At the end of this chapter the results are used to elaborate a TCAD simulation platform taking into account the best trade-off of different key process parameters. This project allows to demonstrate that it is possible to achieve a SiGe:C HBT with f MAX of 500 GHz.

High Speed SiGe and SiGeC HBTs Technologies

In order to evaluate how the STMicroelectronics B4T technology presented later in this chapter can lead to high performances, this section enumerates the different advanced HBT technologies carried by ST competitors. It underlines the choice made by different advanced technologies in order to achieve very fast HBTs.

IHP

One

IBM

Typically HBT built at IBM uses a fully self-aligned technology (FSA) with a non-selective epitaxy process and a phosphorus in-situ doped mono-emitter.

New Architectures Exploration

High-performance in a low-cost HBT architecture

In this "low-cost" architecture, dimensions are reduced and some steps used in the standard Major changes in this structure are the reduction of the dimensions and the replacement of typical shallow trench isolations (STI) with an oxide layer between the extrinsic base and the collector region with an adjustable thickness (CB-Ox). For the study, the simulation project is implemented with the variation of CB-Ox and with selective epitaxy growth region (SEG) totally or partially doped. When partially doped, it is possible to choose the size of the doped area, which it is especially useful to analyze the influence of the doping on the transistor electrical behavior.

CB-Ox

Collector-Base Capacitance Study

In addition to f T , the collector-base capacitance (C BC ) and the base resistance (R B ) are the two influent parameters on f MAX . C BC is the sum of two capacitances in parallel: the collectorbase junction capacitance and the collector-base oxide capacitance shown in Figure 4.7.

The analysis investigates the impact of the CB-Ox capacitance in order to find the reasonable thickness of the oxide layer leading to a low base-collector oxide capacitance and consequently an higher f MAX . The obtained results are applicable not only for the low cost architecture but also for all B3T based advanced devices. In comparison to architectures show later in this section, the result of the increase of the BC oxide is benefic because the reduction of C BC leads to the 50nm 150nm 100nm Junction Capacitance CB-Ox Capacitance improvement of f MAX . In fact these results along with others obtained later will be used to achieve a HBT with a 500 GHz f MAX .

a) Undoped Collector Epitaxy

In these simulations, the typical selective implanted collector (SIC) is replaced by an undoped (≈ 1.10 13 at/cm 3 ) selective epitaxy growth (SEG) region which the thickness goes along with the CB oxide thickness. Simulation results show the decrease of the total capacitance with the increase of the oxide thickness for the same surface. Thus for the lower value of the CB-oxide thickness (50 nm) a capacitance of 15.5 fF/um is obtained, while for the highest value (150 nm) a capacitance of 9.4 fF/um is found. The total capacitance (C T ) is the sum of the CB junction capacitance ( ) and the CB-oxide capacitance ( ).

Table 4.1 gives the division of the capacitance between the oxide part and the junction part for each thickness of the collector-base oxide. According to this result the increase of the CB-oxide thickness from 50 to 150 nm helps to reduce the CB capacitance by nearly 40%

for an undoped SEG device. This is explained by the increase of the depletion region thickness, thanks to the thick CB-Ox and the epitaxied collector.

b) Doped Collector Epitaxy

In the previous section, the collector epitaxied region was mainly undoped (≈ 1.10 13 at/cm 3 ). Now following results will shows how much the capacitance is increased with a thinner space charge region and a higher doping level of the collector.

During the epitaxial growth the collector starts with a high constant doping level of about 5.10 19 at/cm 3 . The growth is followed by the undoped collector region. This is done with a fixed CB TEOS oxide thickness of 150 nm around the collector area. If the thickness of the doped collector goes from 50 nm to 150 nm, the undoped thickness additionally varies from about 150 nm to 50 nm, respectively.

Spacers poly formation issue

Spacers role in low cost architecture

In the current process flow, the spacer task is to protect the thin TEOS oxide cap during etching as depicted in Figure 4.12. This spacer is amorphous silicon made. The width of the TEOS oxide cap defines the contact region between the poly-emitter and the intrinsic base According to the standard fabrication process for the emitter spacers formation, illustrated in Figure 4.13, the problem appears in two ways:

1) The lateral shrinking does not match the typical thickness of the amorphous-poly layer.

The anisotropic standard etching process is not enough to remove the amorphous-poly layer 2) The amorphous-poly not remains thick enough after its etching, therefore the TEOS thin oxide will be unprotected and cannot control the emitter size. If the TEOS thin oxide is overetched a short circuit can be produced between the emitter and the extrinsic base contacts. To solve this problem, the simulation allows to compute the thickness of the amorphous-poly for adequate emitter spacers. The latter should allow a good electrical link between intrinsic and extrinsic parts of the base, should avoid the blockage of the access to the intrinsic base and avoid the over-etch of the TEOS oxide cap, which could leads to the fabrication of unserviceable devices.

Spacers Etching Shape

We remind that two parameters define the emitter spacers process step: the amorphouspoly thickness with a specific shape when it is deposited in the emitter windows, and the amorphous-poly etching leading to the anisotropic reduction of the thickness. More precisely the slope of the amorphous-poly layer molding the emitter window edge determinates the spacer shape. A correct spacer is obtained if the amorphous-poly thickness, after its etching, remains thick enough to protect the TEOS oxide cap, and thin enough to allow a good current flow from the base; this is achieved with a round vertical spacer shape as illustrated in If the spacer side is not vertical enough, the emitter junction width will be dependent only on the etching process. For a low spacer slope, if 5% over-etching occurs, the spacers of transistors on the silicon wafer will be consumed starting with them located close to the wafer border, and the emitter contact will be larger. For a vertical spacer, if 5% over-etching occurs, the emitter width will remain constant.

Geometry Dependence

The geometrical dependency of the amorphous-poly in the formation of the emitter spacers is studied. Taking into account this dependency we give a solution in order to gain control over the amorphous-poly slope to obtain precise emitter spacers. When the different dimensions are analyzed by TCAD simulations it is found that if the emitter-base oxide thickness (Y) is less than W'/2, and if the amorphous-poly thickness (Z) is bigger than W'/2, then X = Y+a. This causes the amorphous-poly to block access to TEOS oxide impeding the subsequent etching of this.

In order to obtain vertical spacers, the amorphous-poly deposition thickness must be smaller than the lower value between Y and W'/2, which leads to obtain an X value equal to or less than Z.

Buried Collector Architecture

The second simulated structure is shown in Figure 4.18. This architecture is based on the B3T technology, most of the process steps were used obtaining a very similar B3T structure with the particularity of a strong increase of the collector-base oxide thickness (CB-Ox).

CB-Ox

Parallel to the CB-Ox layer, a selective epitaxy growth (SEG) is carried out for the collector module. Because of the increase of CB-Ox and of the collector SEG, the highly doped part of the collector (Buried Collector) is notably separated from the base generating a slightly longer path for carriers. The typical nitride layer used between the poly-emitter and the extrinsic base is replaced with a thick oxide layer which allows a better isolation. The result of the different changes generates a hybrid-architecture between B3T and the low cost structure. For the low cost B3T architecture f MAX is about 220 GHz while f T peak value is 190 GHz. For the buried collector B3T device, f MAX is 280 GHz and f T is 210 GHz. Best performances were obtained for the B4T architecture described below, with f MAX and f T of 400 GHz and 260 GHz, respectively. The low cost and buried collector architectures should reaches better dynamic performances with the optimization of the doping profiles.

Performances comparison

B4T Architecture

Compared to low cost architectures, B4T leads to better performances and it is chosen to In the following section, the architecture is extensively discussed. We analyze different key process parameters allowing the enhancement of f MAX without penalizing the other electrical characteristics.

ST B4T devices and Simulation

Electrical Results

To bring confidence in our TCAD based device architectures exploration the reference TCAD platform is firstly validated with recent silicon material from STMicroelectronics. The excellent agreement between measurements and simulations confirms that advanced models for specifics SiGeC alloys, in combination with an all step-process simulation, are accurate for predicting the electrical performance of HBT SiGe:C devices.

The best performance of B4T+ device is mainly explained by the emitter wide reduction and the width of internal spacers and of the polysilicon emitter. This enables a very short distance between cobalt silicide on the polysilicon base and the internal device. Thus extrinsic contributions to the base resistance are diminished and this is reduced as showed in Figure 4.26. On the other hand the emitter resistance R E is increased but without a significant impact on the transistor performance. The lateral shrinking of the collector area allow to reduces the base-collector capacitance while the reduction of the emitter inside spacer and poly-emitter width allow to decreases the extrinsic base resistance. Simultaneously the influence of the carbon content is analyzed due to its huge impact on the boron profile. In state of the art devices, boron is incorporated jointly with carbon to obtain the steepest doping profile and the best performances. In this study the carbon content is varied from 0 to 2%.

As expected from the analysis made previously in chapter 3 through our simulations the boron-carbon doping level appears as one of the most influential parameters for the performance optimization of SiGeC HBT. With results shown in Figure 4.27 and in Figure 4.28, the best carbon content is about 0.5%.

This content is important for high doping level of B, too low carbon content does not block enough the boron diffusion. In this case, the neutral region of the base is thicker, leading to a lower f T (higher base transit time) and in consequence a lower f MAX . The neutral region is between the space charge regions of the two junctions. 142 High C contents do not help to increase f T or f MAX . The f T decrease with increasing doping level is lesser at high C content than low C content. For a f T less doping dependent, the C content should be about 1% with values between 300 GHz and 360 GHz. The f MAX increase is not linearly dependent on the doping level. Excepted to get highest values, doping levels of 4-5.10 19 cm -3 are enough to reach high f MAX .

The important impact of the carbon content on f MAX can be also seen on the reduction of the base resistance (R B ) when the doping level increase, as it can be seen in Figure 4.29. The increase of f MAX is due to the decrease of the base resistance. Even if R B is low for low carbon content, f MAX (and f T ) suffers from the thicker neutral base layer. It should be noted that the high carbon content leads to the increase of the base resistance due to the degradation of the longitudinal mobility of holes. In the case of the current gain, Figure 4.30 shows how it is mostly impacted by the variation of the B doping level with high current gain obtained with low doping level. At low doping level, the diffusion is low with or without C. The current gain are not significantly degraded for C contents close to 0.1%, while for C content higher than 1% it was strongly impact. At high doping level the boron diffusion is higher, reducing the distance between the heterojunction and the pn junction, even pushing the latter into the Si emitter. It leads to the decrease of the current gain, and only the optimized level of 0.4-0.5% C content gives a good trade-off for the B diffusion.

Gain

Typical carbon content for B3T technology is lower than 0.1%. We varied this quantity and noted an improvement of electrical characteristics for higher values than 0.1%. Unlike of the B doping level, C content not degraded significantly the BV CEO characteristic. This permits to use high B doping levels, with reduced R B value in thin neutral base layer to obtain high f MAX values.

The CB capacitance is reduced with high levels of boron doping as shown in Figure 4.32a. This is consistent with the increase of f MAX for the same B doping levels however f MAX values are lower than those expected with high B doping level. We can conclude that carbon content can be lower than 1%, enabling small neutral base thickness even at high boron doping level, and the best performance for f T and for f MAX is achieved with a C content of about 0.5%.

Germanium Impact

The analysis of the germanium impact on B4T devices is done with different Ge percentages in the 1D profile layer stack. As presented in the previous chapter, the germanium profile is divided into three regions with constant germanium fraction. The first region close to the emitter side is with a Ge fraction GeE, the second region in the middle of the base is with a Ge fraction GeB higher than GeE, and the third region close to the collector is with a higher fraction GeC. The effect of the Ge fraction on the electrical characteristics (f T , f MAX and the current gain) is shown in Figure 4.33. Best results are obtained with GeE and GeC percentages of 15% and 35%, respectively. In the case of GeE and GeB the best trade-off is achieved for GeE around 15% and GeB around 29%. Results show that 15% for GeE associated with the highest GeC value are able to give enough current gain, enough Ge grading through the base for a fast electron transit time and enough Ge fraction for a high longitudinal mobility of holes. GeB can be about 25% between GeE and GeC. Capacitances are decreased when the base connection length is smaller, enabling high f T values, but if this length is lower than 20 nm, large drawback is observed on the total base resistance and thus on f MAX . The good electrical link between the intrinsic and the extrinsic layer of the base depends on the not too small base connection. But an increase of the connection length much larger than 20 nm does not give enough benefits on R B to compensate the capacitance increase. Then, maximum values of f MAX only require a connection length of about 20 nm. It should be note that the decrease of the emitter width gives a benefit for f T quite similar than that obtained in the B3T technology. It is also find an improvement of the current gain which is increased by 20% compared to the B3T technology.

The implantation energy and the dose of the SIC is simultaneously studied within results of At the end of the device fabrication process the last activation annealing is performed. This allows the activation of a large part of doping species in all regions of the transistor. This is done with a very fast annealing at high temperature where the shape of the temperature with the time is triangular and is commonly known as "spike".

As fast as the spike can be, these annealing conditions still induce the diffusion of species, less than it could be with longer annealing. In some Figure 4.38, it can be seen the moderate impact of the spike temperature on performances, but low temperature is in favor of high f MAX .

Figure 4.38 shows also the impact of the poly etch and the collector-base oxide thicknesses.

The best trade-off is found with a poly etch of about 0.1 um and a CB-Ox thickness of about 25 nm. Also the current gain is considerably improved with the reduction of the poly etch, and a maximum is observed for CB-Ox thickness of 25 nm. The first step was to build an advanced HBT architecture which allows the increase in frequency operation, by optimizing the geometry, distances, thicknesses, and by reducing parasitic elements (section 4.2). This architecture should be consistent with the current fabrication process and do not present drawbacks which could jeopardize its fabrication (section 4.2.2 ).

Amorphous-Poly

CB-Ox

(a) (b) (c) (d) (e) (f)
The second step was to obtain better doping profiles in the transistor regions. It should improve the carrier transport and at the same time it should contribute to reduce resistance and capacitance parasitics.

The third step was to use specific models developed for SiGeC alloys. As it was seen in chapter 2, a physics-based TCAD simulation tool requires to take into account the specific properties and the combined effects of the strained ternary alloy. The use of these models leads to a realistic and predictive simulation tool for SiGeC HBTs.

Finally we study and optimize the main process parameters already observed in previous technologies (section 3.6). From results obtained in these studies we develop the B5T-TCAD simulation project which takes into account the best trade-off of different parameters tested. This has leaded us to achieve a SiGeC HBT with f MAX exceeding 500 GHz, accomplishing thus the main objective of ours studies and demonstrating the feasibility of the project.

First parameters to take into account are the boron doping level and the carbon content (section 4.5.1.1). For the boron the doping concentration is 8.5×10 19 at/cm 3 and the carbon percentage this is fixed at 0.5%, according to results analyzed in the previous section that leads to best values for both f T and f MAX .

In the case of the germanium content, the best trade-off is a composition of the base layer with 3-steps of 15%, 26% and 30% for GeE, GeB and GeC, respectively. Others values obtained are 170 nm for the emitter window, 25 nm for the base connection length, a 1080°C spike temperature and an etching of 200 nm for the amorphous-poly. With this configuration a f T value of 295 GHz and a f MAX value of 554 GHz is achieved as it can be seen in Figure 4.39. The I-V characteristic shown in The main key process parameters and frequency values of the devices studied are compared in Table 4.5 equivalent results can be find in [ Lacave 11]. The f T and f MAX performances for B5T devices are compared in Figure 4.42 with B4T and B3T technologies.

While the f T enhancement is moderate among the three transistor technologies with a maximum value of ~ 260 GHz for B3T and B4T+ and ~ 280 GHz for B5T, f MAX is improved by 17% from B3T to B4T+ and by 18% from B4T+ to B5T. The high operating speed of B5T device can open up new areas of application; can be used for circuit reliability reducing the impact of temperature and voltage variations at lower frequencies, or can be used for low power applications with reduced collector current.

Conclusion

This chapter described the path to follow for the optimization of f MAX . In order to obtain this target we proposed different architectures of advanced SiGe:C HBTs to increase the frequency performances.

Among the results obtained for the low cost architecture we found that the increase of the CB-oxide thickness from 50 to 150 nm helps to reduce the CB capacitance by almost 40%

for an undoped SEG device. It was shown the dependence of CB capacitance with the increase of the doping level and how C BC is reduced when the SEG of the collector doped region is smaller, due to the increase of the CB depletion region.

In this chapter we solved a process problem detected for the emitter junction. We showed that if the spacer side is not vertical enough, the emitter junction width will be dependent We can conclude that carbon content lower than 1% keeps thin enough the neutral base layer even at high boron doping level, and best performances for f T and f MAX are achieved for C percentage of about 0.5%. Results show that 15% of Ge content at the emitter side associated with the highest Ge content at the collector side of the base is a good trade-off for high current gain, enough Ge grading through the base for fast electron transit time and appropriate Ge fraction for high hole mobility. The best f MAX result is obtained for the higher implantation energies and for the intermediate values of the SIC dose. In the case of f T , the best result is obtained for a SIC energy around 250 keV. The best trade-off between f T and f MAX was found with a poly etch of about 0.1 um and a CB-Ox thickness of about 25 nm.

Conclusion

In The chapter four of the thesis showed the path to follow to the f MAX enhancement. Here we proposed different architectures of advanced SiGe:C HBTs with this objective. A highperformance low cost architecture was elaborate to focus on the reduction of the collectorbase (CB) capacitance and to study the possibility of yield a low cost transistor with high performances. We found that the increase of the CB-oxide thickness from 50 to 150 nm helps to reduce the CB capacitance by almost 40% for an undoped SEG device in this architecture. In this chapter we demonstrate that for advanced HBT SiGeC architectures if the spacer side is not vertical enough, the emitter junction width will be dependent only on the etching process. Latter leads to block the access to the TEOS oxide cap on top or to a short circuit can between the emitter and the extrinsic base contacts. Based on TCAD studies we proposed a solution to this problem.

In chapter four we analyze the carbon effect on the transistor performance concluding that carbon content lower than 1% keeps thin enough the neutral base layer even at high boron doping level, and best performances for f T and f MAX are achieved for C percentage of about 0.5%. We found the best trade-off of different parameter studied in order to enhance the transistor frequency behavior.

Appendice

Transport de charge dans les semiconducteurs

Les modèles de transport peuvent varier considérablement en termes de facilité et de précision de la solution. Ils peuvent être physiquement très sophistiqués mais difficiles à résoudre et coûteux en temps de simulation ou facile et rapide à résoudre, mais avec des résultats inexacts. La Figure 1.20 résume les différents niveaux de modélisation et de théorie du transport. Les modèles de la densité d'états ont été implémenté dans le simulateur, ainsi que tous les modèles dédiés au matériau SiGeC : la bande interdite, la mobilité des électrons et des trous et le temps de relaxation de l'énergie.

Le modèle de bande interdite

Composition et modélisation de la diffusion des dopants

Contrairement aux alliages III-V et II-VI, la similarité entre atomes de la colonne IV permet l'obtention d'alliage plus facilement en réduisant fortement ou en évitant les problèmes d'hétérogénéité liés à la miscibilité partielle des atomes, aux différences d'ordre atomique à petite et grande échelle dans le matériau, ou bien induit par la stabilité de phase des alliages lors de traitements thermiques.

Simulation et calibrage des dispositifs B3T

Le calibrage de la technologie B3T consiste à ajuster les paramètres de modélisation par comparaison entre les résultats de simulation et de mesure des dispositifs réels. Les différents paramètres de la simulation sont analysés en fonction de leur impact sur les profils de dopage, sur les structures géométriques et sur les caractéristiques électriques.. Les profils de dopage simulés sont comparés aux profils obtenus par spectroscopie massique d'ions secondaires (SIMS), les structures géométriques sont comparées aux images obtenues par transmission électronique (TEM) et les résultats électriques sont comparés aux caractéristiques statiques et dynamiques des TBH fabriqués.

Influence du niveau de dopage (bore)

Dans les dispositifs bipolaires avancés, l'épaisseur de la base SiGeC peut être très réduite

Comparaison des performances

Un transistor bipolaire SiGeC avec f MAX de 500 GHz

A partir des résultats obtenus dans les études précédentes, nous développons une plateforme de simulation pour la technologie B5T qui prend compte des meilleurs compromis des différents paramètres testés. Cela permet d'atteindre une valeur de f MAX supérieure à 500 GHz, accomplissant ainsi l'objectif principal de l'étude et démontrant la faisabilité du projet.

xiii 3 TCAD

 3 Simulation of Advanced Terahertz SiGe and SiGeC HBTs ....................71 3.1 Simulation Context and Objective ........................................................................... 3.2 B3T Technology...................................................................................................... 3.2.1 B3T process fabrication ...................................................................................... 3.2.2 Simulated Structure ............................................................................................ 3.2.3 B3T Mask Layout ................................................................................................ 3.2.4 B3T TCAD Project .............................................................................................. 3.3 Composition and Dopant Diffusion Modeling .......................................................... 3.3.1 Carbon Content .................................................................................................. 3.3.1.1 Carbon incorporation in SiGe alloys ................................................................ 3.3.1.2 Carbon Diffusion Effect on the Base Width ..................................................... 3.3.2 Dopant Diffusion in SiGeC Alloys ........................................................................ 3.3.3 Boron Diffusion in SiGe and SiGe:C Alloys ......................................................... 3.3.4 Modeling of Boron Diffusion in SiGe and SiGeC Alloys ....................................... 3.4 B3T Simulation and Calibration ............................................................................... 3.4.1 The Process Simulator ........................................................................................ 3.4.1.1 Etching and Deposition Simulation .................................................................. a) Etching ............................................................................................................ b) Deposition ....................................................................................................... 3.4.1.2 Diffusion .......................................................................................................... 3.4.1.3 Oxidation ......................................................................................................... 3.4.2 1D Process Simulation ........................................................................................ 3.4.3 2D Process Simulation ........................................................................................ 3.4.4 Electrical Simulation ............................................................................................ 3.4.4.1 Collector Current Calibration ........................................................................... 3.4.4.2 Base Current Calibration ................................................................................. 3.4.4.3 Transition Frequency Calibration ..................................................................... 3.4.4.4 BV CEO Calibration .......................................................................................... 3.5 Impact of process parameters ............................................................................... xiv 3.5.

3.6. 2 4

 2 Dynamic Characteristics ................................................................................... 3.7 Conclusion ............................................................................................................ Optimization towards f MAX 500 GHz ............................................................117 4.1 High Speed SiGe and SiGeC HBTs Technologies ................................................ 4.1.1 IHP ................................................................................................................... 4.1.2 IMEC ................................................................................................................. 4.1.3 IBM ................................................................................................................... 4.1.4 Freescale .......................................................................................................... 4.2 New Architectures Exploration .............................................................................. 4.2.1 High-performance in a low-cost HBT architecture ............................................. 4.2.1.1 Collector-Base Capacitance Study ................................................................ a) Undoped Collector Epitaxy ............................................................................ b) Doped Collector Epitaxy ...........................................................................

  .................................................................................................. 133 4.4 ST B4T devices and Simulation ............................................................................ 134 4.4.1 Electrical Results .............................................................................................. 135 4.5 Impact of the process parameters and optimization towards 0.5 THz f MAX ............. 138 4.5.1.1 Boron doping level and Carbon Content ........................................................ 140 4.5.1.2 Germanium Impact ........................................................................................ 144 4.5.1.3 Influence of process parameters I: Emitter Window, Base Connection, SIC Energy and Dose. ......................................................................................... 146 4.5.1.4 Influence of process parameters II: SPIKE, Collector-Base Oxide and Amorphous Poly Etching. .............................................................................. 150 4.5.2 Simulated SiGeC HBT device working at 500 GHz: B5T ................................... 152 4.6 Conclusion ............................................................................................................ 155 Conclusion .........................................................................................................157 Bibliography ......................................................................................................159 Appendice .........................................................................................................173 Résumé de la thèse ...........................................................................................173 "Recherche et développement de transistors bipolaires avancés par le biais de la modélisation technologique" ..................................................................173 1 Fonctionnement du transistor bipolaire a hétérojonction SiGe/SiGeC et le transistor bipolaire au silicium .............................................................................................. 174 1.1 Fonctionnement à haute fréquence....................................................................... 174 1.2 Extraction de la fréquence maximale d'oscillation f MAX .......................................... 175 1.3 Transport de charge dans les semiconducteurs .................................................... 175 2 Modélisation du transport des charges dans les TBH SiGe et SiGeC ..............

3. 6

 6 Résultats électriques ............................................................................................ 4 Optimisation vers f MAX de 500 GHz ....................................................................... 4.1 Comparaison des performances ........................................................................... 4.2 Architecture B4T ................................................................................................... 4.2.1 Résultats électriques ......................................................................................... 4.3 Influence des paramètres technologiques et optimisation vers f MAX de 500 GHz. .. 4.4 Un transistor bipolaire SiGeC avec f MAX de 500 GHz ............................................

  RF and microwave circuits [Parisa 11] [Sumei 11] [Lei Wang 11]  Cryo-Electronics [Cressler 10] [Ramirez-Garcia 09] [Cressler 93.1]  Low Noise RF [Kenneth 11] [Gang Liu 10] [Pacheco 10]

Figure 1 .

 1 1 shows a schematic representation of a npn Si bipolar transistor structure, with the typical dopant profiles and the transistor biased to operate in the active mode.

Figure 1 . 1

 11 Figure 1.1 Basic npn Si bipolar transistor structure. Above, typical dopant profiles for emitter, base and collector. Below, transistor biased to operate in the active mode.

Figure 1 . 2

 12 Figure 1.2 Energy band diagram for (a) a npn Si bipolar transistor with no applied bias, (b) for a npn Si bipolar transistor biased in forward active mode.

Figure 1 . 3

 13 Figure 1.3 Emitter, collector and base current components of a npn BJT in the forward active mode.

  collector-emitter breakdown voltage in common emitter configuration with an open base (BV CEO ) is an important parameter for the optimization of the bipolar transistor. It is linked with the avalanche multiplication process in the base-collector SCR under open base condition. With the base-emitter junction forward-biased, the electron current (Figure 1.3) enters into the base-collector depletion region. Because of the high electric field in this region the avalanche multiplication phenomenon can occur and generates electron-hole pairs such as holes required for the base recombination are produced by the impact ionization (no current is required from the open base contact ). Under these conditions we factor for electrons. The breakdown collector-emitter breakdown voltage can be written in the following form: (1.18) where is the breakdown voltage in common base with the base open circuit. This is given by: (1.19)

Figure 1 . 4

 14 Figure 1.4 Statics Characteristics, collector-emitter breakdown voltage BV CEO for Vbe= 0.7 V at 300K.

Figure 1 .

 1 Figure 1.5 Trade-off between current gain β and breakdown voltage BV CEO

Figure 1 . 6

 16 Figure 1.6 Comparison of the band diagrams of a SiGeC HBT (solid line) and a Si bipolar transistor (dashed line). (a) The band structure for a Si bipolar transistor (BJT) and a rectangular Ge base profile (HBT). (b) The band structure for a Si bipolar transistor (BJT) and a linearly Ge graded SiGe HBT.

Figure 1 . 7 .

 17 Figure1.7. In addition, it is possible to optimize device profile introducing a graded germanium epitaxy. With a Ge concentration higher in the collector side than the emitter side, and a constant acceptor doping level, we obtain a gradient in the conduction band, which acts as a built-in electric field, accelerating electrons from the emitter to collector. This allows reduction of the transit time of the carriers in the neutral base improving the frequency performance[Hurkx 94].

Figure 1 . 7

 17 Figure 1.7 Gummel plot comparison characteristics of two equivalents transistors SiGe HBT and Si BJT.

Figure 1 . 8

 18 Figure 1.8 Two port network used during our simulations to study the small-signal properties of the SiGeC HBT with its parasitic components.

Figure 1 . 9

 19 Figure 1.9 Schematic view of the standard HBT device with the reduced simulation window (in black), the standard simulation window (in red) and the different parasitic elements needed for the mixedmode HBT electrical simulation.

Figure 1 .

 1 9 also shows the parasitic elements to be taken into account during the simulation; where Cpe is emitter/base back-end capacitance, Cpc the collector/base back-end capacitance, Coxe the internal part of the emitter/base oxide (or spacer) capacitance and Coxc the internal part of the collector/base oxide capacitance. R ex , R bx and R c are the components of the total emitter, base and collector resistance.

a

  regional analysis [Sze 07] [Zerounian 04]: (1.25) The first and second terms, and are the transit time for the neutral emitter and the emitter-base junction, respectively, and given by (1.26) , is the neutral base transit time, this is highly influenced by the base width (1.28) For a homogenously doped base the factor is equal to 2. A non-uniformly doped base creates a built-in electric field and the value of vary between 2 and 4. The fourth term in equation (1.25), is the base-collector transit time, (1.29) The fifth term is the collector transit time and represents the RC parasitic circuit formed with the collector resistance and the base-collector junction capacitance, (1.30) The sixth and last term is the transit time associated with emitter-base and base-collector junction capacitances and the emitter dynamic resistance and is given by (1.31) In equation (1.25) the sum of the four first terms and represents the forward transit time . The total transit time can also find in literature as a function of :

Figure 1 .

 1 Figure 1.10 Schematic circuit used for f MAX derivation. (a) High frequency input impedance, and (b) output impedance in the common emitter configuration.

Figure 1 .

 1 11 shows the measured MAG, MSG, and Mason's U versus frequency for a SiGe HBT biased near peak f T [Zerounian 00] [Cressler 03].

Figure 1 .

 1 Figure 1.11 Mason's U, MAG and MSG extraction methods, K is the Rollett's stability factor, this is a one way to get an indication of whether there is a stability problem to obtain the power gain [Cressler 03].

Figure 1 . 12 .

 112 Figure 1.12. In this method the script developed perform a frequency sweep over a wide range of frequencies for each DC operating point. The user can set up the frequency sweep range defining the start and the end frequencies. For more accurate results the frequency sweep should start at a low frequency where U is constant.

Figure 1 .

 1 Figure 1.12 Bode plot showing the full frequency sweep for f MAX extraction

FrequencyFigure 1 .

 1 Figure 1.13 Bode plot showing the full frequency sweep and extrapolation for f MAX extraction

Figure 1 .

 1 Figure 1.14 Bode plot showing the one point method. Only one frequency is used in the 20dB/decade slope region for each DC operating point.

Frequency

Figure 1 .Frequency

 1 Figure 1.15 Bode plot of h 21 versus frequency for the definition of the transition frequency f T

Figure 1 .

 1 Figure 1.16 Variation of f T with collector current in a SiGeC HBT.

Figure 1 .

 1 Figure 1.18 Magnitude of common-emitter AC current gain versus frequency

Frequency

Figure 1 .

 1 Figure 1.19 Typical electron Brownian-motion due to collisions in a semiconductor (a) In absence of an electric field (b) in presence of an electric field.

Figure 1 . 1 . 3 . 2

 1132 Figure 1.20 Hierarchy overview of the semiconductor transport theories

  not specified by the Fermi-Dirac function; but by a non-equilibrium distribution function determined through the semi-classical Boltzmann equation [Balkansky & Wallis 00].

2 2

 2 AC electrical behaviors have been also introduced with the extraction of the transition frequency of the current gain (f T ) and of the Mason's gain (f MAX ), implemented in the TCAD simulation platform. The last part of this chapter introduces the different levels to model the electron transport into semiconductors: The quantum-mechanical transport model, the semi-classical Boltzmann transport equation, the energy-based hydrodynamic transport model, the simplest drift-diffusion transport model. A brief discussion includes the Monte-Carlo method to solve transport equations. The specific properties of strained SiGeC materials used in HBT, of moment-based models are detailed in the next chapter. Chapter Transport Modeling in SiGe and SiGeC HBTs: from material and physics to devices

Figure 2 . 1

 21 Figure 2.1 Upper part of figure illustrates schematically the surfaces of constant energy in k space for the conduction band in case of different strain. The lower part shows the degeneracy of conduction and valence band for different induced strain in Si structures [Duschl 00][Jorke 00].

Figure 2 . 2

 22 Figure 2.2 Schematic representation of Si 1-x Ge x C y growth and different types of strain [Hållstedt 04].

, 2 /

 2 the longitudinal and transverse effective mass ( , 3/ the conductivity effective mass The is the effective mass of a parabolic band that has the same density of states to the thermal energy than the real band [Richard 04] and it is given by [Fischetti 96]: 2.1 where is the DOS effective mass in the conduction band n, and is the DOS at the energy . The transverse and longitudinal effective masses are the two effective masse components which derived from the non-isotropic shape of the constant energy surface of the conduction band edge in the E-k diagram [Sah 91]. The conductive effective mass is one more parameter extracted from the simplification of the band energy with effective mass calculation. This is obtained from the sum of the inverse of the individual masses, as each band maxima or minima. For anisotropic minima containing two transverse and one longitudinal effective masses one has to sum over the effective masses in the different minima along the equivalent directions. For instance in silicon the resulting effective mass is given by [Zeghbroeck 11]: The conductivity effective mass is used to calculate mobility and diffusion constants [Sze 07]. Another example is the calculation of the shallow impurity levels using a hydrogen-like model [Zeghbroeck 11]. Due to the valley splitting and the anisotropy among the bands, different orientations correspond to different when an electric field is applied [Song 12]. For SiGe HBTs, due to the anisotropic transport properties in the strained SiGeC layer, and the bipolar transport characteristics (involving both electrons and holes) we have to take into account both conduction directions, [001] and [100]. For SiGe strained alloys grown on <001> silicon substrate Fischetti and Laux calculated the conductivity electron effective mass using non local empirical pseudo-potentials, their results are shown in Figure 2.3..

Figure 2 . 3

 23 Figure 2.3 Conductivity electron effective mass, normalized with the free electron mass, for SiGe alloys grown on <001> silicon substrate [Fischetti-Laux 96].

Figure 2 .

 2 Figure 2.4 (a) Schematic representation of normal, equivalent, conduction band iso-energy surfaces in silicon (b) Biaxial compressive strain effect on and the longitudinal ellipsoids bands become flatter and the transverse acquires a larger curvature [Chen 01].

Figure 2 .

 2 Figure 2.5 (a) Constant-energy surfaces for electrons in unstrained SiGe alloy, the ellipsoids are located at about three-fourths of the distance from the Brillouin zone center;(b) Band structure for Si and SiGe alloy. Vertical axis is energy, horizontal axis is electron or hole momentum in (111) and (100) k-space directions [Bean 92].

Figure 2 .

 2 Figure 2.6 shows the Miller indices of some important planes in the HBT device after the selective epitaxial growth (SEG) of the SiGeC base. While sets the electrons behavior on the direction <001>, sets their behavior on the direction <010>.

Figure 2 . 6

 26 Figure 2.6 Miller indices of some important planes in the HBT device after the selective epitaxial growth (SEG) of the SiGeC base.

  rest mass, coefficient is set to 0.1905, is the silicon bandgap at zero Kelvin and is the bandgap as a function of the lattice temperature.The Sentaurus formula is only valid when the electrons are close to the minimum of the conduction band. Moreover it ignores the Ge and C content and strain effects, and ignores the variation of doping concentrations (N D and N A ). Thus if N D and N A become comparable or greater than N C and N D , respectively, the Fermi-level is erroneously driven deeper into the conduction or valence band[Li 2006].

  Figure 2.7. The biaxial compressive strain splitting of the valence band leads to a preferential occupation of the heavy hole band [Van de Walle 00]. It reduces the HH and splits off band energies with respect to the LH band.

Figure 2 . 7

 27 Figure 2.7 Schematic deformation of valence bands and SiGe alloys under compressive strain [Cressler 03].

Figure 2 . 8

 28 Figure 2.8 Conductivity hole effective mass, normalized with the free electron mass, for SiGe alloys grown on <001> silicon substrate [Manku 91].

Figure 2 .

 2 Figure 2.9 shows the strong dependency on energy of the hole DOS effective mass in SiGe strained alloys. This dependency is important for values higher than 65 meV [Fu 93].

Figure 2 .

 2 Figure 2.9 (a) DOS effective mass for the heavy hole band in SiGe alloys (hDOSmass). (b) DOS effective mass for the light hole band. (normalized with the free electron mass) [Manku 91].

Figure 2 .

 2 10 illustrates a comparison between the band structure and the magnitude of effective DOS value. We consider two energy bands with different curvatures, with the same quantity of states along the horizontal k-axis in a fixed energy interval. Thus the effective mass and the density of states are linked together. The band with the larger curvature and therefore the smaller effective mass has fewer states within the energy interval, while the band with the larger effective mass (flatter band) gives more effective states within the same energy interval.

Figure 2 .

 2 Figure 2.10 Bands with different curvatures, curvature shape determines the numbers of states in a fixed energy interval.

  [Hueting 96], or fix the valence band effective DOS to that one of bulk silicon[Pejcinovic 89], or assume that this is linearly dependent on the mole fraction[People 86].On the other hand, numerical device simulators (such as Sentaurus) uses a simple parabolic band model by default, which ignores the Ge and C content and strain effects, and limits the effective mass (m*) and DOS to constant quantities ignoring the variation of doping concentrations (N D and N A ). Thus if N D and N A become comparable or greater than N C and N D , respectively, the Fermi-level is erroneously driven deeper into the conduction or valence band[Li 2006].The other possibility to model the effective DOS is to calculate it from scalar effective mass data but it is much more laborious. It needs to extract a bunch of scalar values from literature (for example from Manku and Natan [Manku 91], the only data we found for both electrons and holes) and to introduce it into the device simulator with great attention to avoid error. However the studies of Manku and Natan are only for SiGe alloys.In order to perform accurate TCAD simulations, better effective DOS models for electrons and holes are needed. The models presented here are calibrated with Full-Band Monte Carlo simulations rely on strain-dependent SiGeC tight-binding band structures [Michaillat 09] [Michaillat 10.1]. These models are suitable for the implementation in different hydrodynamic TCAD simulators. Due to the dependency of DOS on bandgap [Buffler 98], the model of the Ge content dependency is based on the Bean formula [Bean 92], which describes the variation of the bandgap in SiGe alloys compressively strained on silicon. Also, the additional effect of the molar fraction of C in SiGeC alloys is approximated, and associated with Ge according towith the following relationship 2.4 Where is the germanium content, is the carbon content and the coefficients to are defined according to Palankovski, Gonzalez and Kosina [Palankovski 99]. Their values are reported in

Figure 2 .

 2 Figure 2.11 Values of as a function of Ge and C content

[ 3 [

 3 Sze 07] which includes the density of state effective mass for electrons ( Singh 06].Based on the early theoretical calculations in SiGe strained alloys done by People[People 85] [People 86] and considering that the 6-fold conduction band degeneracy of Si is lifted, resulting in a 2-fold (out-of-plane) and 4-fold (in-plane) band splitting noted as and[Pejcinovic 89], the final expression for the effective DOS in the conduction band is then: Δ 2.9The electrons effective DOS model is depicted in Figure2.13 at different lattice temperatures of strained Si 1-x-y Ge x C y as a function of Ge content x.

Figure 2 .

 2 Figure 2.12 Electrons effective density of states at different lattice temperatures of strained Si 1-x- y Ge x C y as a function of Ge content x. Symbols refer to MC simulations, lines represent our analytical electrons DOS model.

Figure 2 .

 2 Figure 2.13 depicted the holes effective DOS model at different lattice temperatures of strained Si 1-x-y Ge x C y as a function of Ge content x.

Figure 2 .

 2 Figure 2.13 Holes effective density of states at different lattice temperatures of strained Si 1-x-y Ge x C y as a function of Ge content x. Symbols refer to MC simulations, lines represent our analytical holes DOS model.

  People 86] [Bean 92] [Cressler 98] [Maiti 01] [Ashburn 03]. For example for 10% germanium, the valence band offset is 0.073 eV, compared with 0.019 eV for the conduction band offset [Ashburn 03]. Strain effect on the alloy results in a reduction of the fundamental gap but it not modifies the indirect nature in this. Band splitting was depicted by People [People 85] [People 86] who described it in terms of the deformation potentials and the strain tensor.

Figure 2 .

 2 Figure 2.14 Band alignments for (a) Ge 0.2 Si 0.8 /Si on (001)-Si, (b) Ge 0.5 Si 0.75 /Si heterostructures on (001)-Si.

Figure 2 .

 2 Figure 2.15 Bandgap model of SiGeC compressively strained on silicon, as a function of the germanium and carbon percentages.

Figure 2 .

 2 Figure 2.16 Temperature dependence of the SiGeC bandgap model for SiGeC alloys compressively strained on silicon. Germanium varies from 0 to 35%, carbon content of 1%.

  topic several studies have been published [Van Vliet 93] [Sokolic 94] [Gonzalez 97] [Luo 07].

Figure 2 .

 2 Figure 2.17. The values for the real BGN are taken from [Wagner 84-88] and from [Dumke 83] and are based on photo-luminescence experiments. The experimental data for the apparent BGN are taken from [Dumke 83.2] and [Swirhun 88].

Figure 2 .

 2 Figure 2.17 Experimental data for BGN (real BGN) and apparent BGN [Jain-Roulston 91].

  simulations for SiGeC alloys]. These models were developed for doped ternary SiGeC alloys, relaxed or biaxially strained on relaxed silicon. They describes homogeneous and stationary transport of both electrons and holes; the band structure description is made by a numerical Full-Band method. Modeled mechanisms include ionized impurity scattering, alloy scattering, carrier phonon scattering and impact ionization. For the extraction of material parameters and the determination of analytical models for SiGeC, transport parameters include the Ge and C relative concentrations, the type of active doping species, the lattice temperature, the magnitude of the external electric field and the biaxial stress effects.Real BGNApparent BGN

  in-plane and orthogonal components of the mobility. In conventional vertical HBT, these two components are essential for a correct device simulation. In the base layer, the collector current (electrons) and the base current (holes) flow perpendicular to each other: the collector current flows vertically through the base and the base current flows laterally along the emitter-base junction. Thus the main component for the electron mobility is while it is for holes. The expression of the strain effect on the electron mobility is 2.24 where is or depending on the values of , , and , which are different for the in-plane and out-plane mobilities. The term is the already discussed compensation parameter which serves to determinate whether the material is under strain and the type of strain. The parameters for hole mobilities are shown in

  modeled by equation 2.23 with specifics values for and depending on mobility component or 2.25 The reduction of the mobility due to the alloy scattering depends on germanium and carbon contents, and it results mainly on the decrease of the density of states at low energy induced by the biaxial stress, modeled by equation 2.6. The effect of the germanium and the carbon content on mobility is depicted in Figure 2.20 and Figure 2.21.

Figure 2 .

 2 Figure 2.20 Electron mobility comparing effects of alloying and doping in relaxed SiGe alloys. Symbols refer to MC simulations; lines represent the used analytical mobility model.

Figure 2 .

 2 Figure 2.21 Electron mobility components; out-of-plane, in-plane as a function of Carbon content.

Figure 2 .

 2 Figure 2.22 Minority-Electron mobility as a function of acceptor concentration. (a) Comparison between mobility models (b) Michaillat calibrated model vs Reggiani model for Si.

  Ge and C impact and final expression of mobilityEquation 2.28 is the final expression for the SiGeC mobility. Previous terms are combined through a Matthiessen's rule. The dependence on the germanium and the carbon fraction is based on an extension to the model of Palankovski[Palankovski 04]. Figure2.23 shows the variation of the electron and hole mobilities in function of acceptor concentrations, for a carbon content of 0.1%. We should underline that simulations include the reduction of the mobility at high doping level, but also the reduction by the biaxial strain. The percentage of Ge and C are the typical quantities used in the fabrication of advanced HBT.

Figure 2 .

 2 Figure 2.23 Electron and Hole mobilities as a function of germanium content, for a C content of 0.1%.



  The equivalent models used by default in the device simulator for the SiGeC HBT device are:  The Klaassen mobility model [Klaassen 92.1] [Klaassen 92.2], which unifies the description of majority and minority carrier silicon bulk mobilities. This describes also the temperature dependence of the mobility and takes into account electron-hole scattering, screening of ionized impurities by charge carriers, and clustering of impurities. The carrier energy relaxation time is assumed by the simulator as the same value as that of bulk silicon. By default, this is constant and is set to 0.3 ps for electrons and 0.25 ps for holes [Sdevice 11].  Bandgap model provide mole fraction dependencies based on Bean formula [Bean 92]. In this the bandgap is given for a SiGe pseudomorphic layer grown on a silicon substrate. Electrical results are shown in Figure 2.24, Figure 2.25 and Figure 2.26. The Gummel characteristic of the simulated SiGeC HBT (Figure 2.24) shows a considerable difference on the collector current I C between the simulator default models and the implemented SiGeC models. This is due mainly to the different mobilities in SiGeC alloys in relation to silicon bulk; the collector current is over estimated by a factor of about two by the default simulator models.

Figure 2 .

 2 Figure 2.24 Gummel plot for Vcb = 0 V at 300 K. Overlays among measurements, simulator default models and SiGeC alloy models.

Figure 2 .

 2 Figure 2.25 Comparison of experimental results and simulated characteristics for f T at Vcb = 0 V .

Figure 2 .

 2 Figure 2.26 Comparison of experimental results and simulated characteristics for f MAX at Vcb = 0 V .

  The SiGeC transport models used in our simulations allow considering the influence of Ge and C doping profiles on the electrical behavior of SiGeC HBT devices. Simulation results indicate that the use of standard transport models which ignore the specific properties of SiGeC alloys should induce significant errors on electrical characteristics of HBT SiGeC devices. The use of advanced transport models for SiGeC HBTs in TCAD simulation should help to obtain more physical and realistic results, better understanding of charge transport in the device, and facilitate HBT device development and optimization.

  technology from STMicroelectronics BiCMOS9MW [Chevalier 05] [Chevalier 09]. It features 260 GHz / 350 GHz for f T / f MAX and has demonstrated the capability for complex circuits manufacturing [Chantre 10] [Avenier 09]. The major changes in the B3T architecture relative to the previous BiCMOS9MW are: New layout rules, new base doping profiles, new SIC alignment (Selectively Implanted Collector) after the emitter opening, new SIC dose after poly-emitter deposition, new poly-base patterning, and new spike annealing temperature reduction. The goal of this technology is to develop transistors with the highest f MAX .An important feature in the development of the B3T process is to scale down the size of the transistor, while maintaining the specificity of the ST self-aligned process technology. This technology should maintain efficient emitters in spite of the increase of resistances in series due to the dimension reduction. This requires to improve also poly-silicon emitters and selfalignment techniques. In B3T technology the self-alignment is an effective tool which makes possible structures below the limits of photo-lithography. This can be introduced into production lines without excessive costs.The Figure3.1 shows the transmission electron microscopy of the cross section of the core of the HBT. The 274 nm wide SiGe:C boron doped base is grown on the Si collector. The 120 nm emitter-base junction width (W E ) is few nanometers under the 174 nm line drawn for dimensional measurement. The emitter peripheral region is isolated from the base (SiGe:C layer and the extrinsic lateral poly-silicon layer) with silicon dioxide (light grey) and silicon nitride forming a L-shape. The dark region is the tungsten plug for the emitter. It can be noted the very small lateral dimension obtained with very deep UV lithography steps.

Figure 3 . 1

 31 Figure 3.1 TEM cross-section of the simulated device (B3T Technology). Fully Self Aligned SiGeC HBT with emitter width (WE) of 120 nm.

Figure 3 . 3 toFigure 3 . 2 B3T

 3332 Figure 3.2 B3T Technology process flow. Major fabrication steps in the process flow, from the P substrate passing by the SiGe:C base epitaxy up to the cobalt silicidation.

Figure 3 . 3

 33 Figure 3.3 Implantation of the N+ buried layer and Collector epitaxy. This figure and following figure show the cross-section of the HBT process.

Figure 3 . 4

 34 Figure 3.4 Shallow trench isolation (STI in dark region) and N+ Sinker implantation (between the two STI). The left edge of the figure is the central axis of the HBT.

Figure 3 . 5

 35 Figure 3.5 Deposition of the pedestal oxide (dark), the polybase and the nitride.

Figure 3

 3 Figure 3.6 Emitter Window patterning (thick protecting layers, anisotropic etching). patterning (thick protecting layers, anisotropic etching).

Figure 3 . 7

 37 Figure 3.7 Oxide etching to define the intrinsic base region (self-alignment of the two junctions) and Selective Implantation of the Collector (SIC) owing to this nitride uncovered region (left side of the figure).

Figure 3 .

 3 Figure 3.8 Intrinsic SiGe:C boron doped base epitaxy, and Si-cap.

Figure 3 . 9

 39 Figure 3.9 Emitter inside spacers formation.

Figure 3 .

 3 Figure 3.10 Poly-emitter depositions and annealing.

Figure 3 .

 3 Figure 3.11 Poly-emitter & polybase patterning.

Figure 3 .

 3 Figure 3.12 Structure generated with the 2D simulation. Brown areas indicate oxide regions, orange areas the N type doping, blue areas the P type doping. Because of symmetry, only one half of the structure is simulated.

Figure 3 .

 3 Figure 3.13 Structure obtained at the end of the electrical simulation with its main parts. Brown areas indicate oxide regions, orange areas the N type doping, blue areas the P type doping.

•

  EmWin: This mask is the most important in the HBT processing, it enables opening of the emitter window and the device self-alignment. The emitter window will be located inside the polybase mask and within an active region. The minimum width of the emitter window is limited by the resolution of the deep UV photolithography equipment. The wavelength used is 193 nm for the B3T technology.

Figure 3 .

 3 Figure 3.14 shows the TCAD simulation flow implemented in order to obtain simulation results for advanced HBT very close to the real device. The design flow starts with a precise layer stack determination obtained from 1D process simulation. The lateral dimension of the HBT is simulated with a 2D process simulation. Finally, some other aspects to consider for right results such as extrinsic capacitances are included. The main objective is to model 1D and 2D process in the advanced ST technology where vertical and lateral dimensions of the HBT core is pushed to sub-micron and nanoscale.

Figure 3 .

 3 Figure 3.14 HBT TCAD Simulation flow. Main steps during the transistor simulation, 1D and 2D process simulation, device simulation and figures of merit: f T , Gummel plot and f MAX .

  Germanium and carbon and the strain of the SiGeC layer help to reduce boron diffusion but accelerate arsenic diffusion. Diffusion parameters are carefully tuned in a calibration work as well as the base layer epitaxial parameters (Ge and C content and thickness of each epitaxial step) to reproduce the electrical characteristics of HBTs. In our simulations the process simulation are based on state of the art process models (such as ion implantation, oxidation, etching, diffusion) within Sprocess simulator [Sprocess 11] and on the implementation of specific diffusion models for SiGeC alloys [Pakfar 03].

   [Zaumseil97]. The presence of carbon in the SiGe base layer helps to reduce considerably boron diffusion and allows the formation of thin and highly doped base. SiGeC bipolar transistors have very low base widths and their dynamic performance is improved significantly compared to SiGe HBTs [Sibaja 11]. Reducing the diffusion coefficient of boron is such that often it is said of "blocking" the diffusion of boron.The blockage effect of carbon on the transient enhanced diffusion, due to the point defects generated by ion implantation of boron, attracted the research interest on carbon diffusion in the 1990s [Lanzerotti96] [Cacciato 96] [Gossmann 96].

For

  concentration lower than 1%, carbon is only located in substitutional sites of the Si or SiGe crystal lattice . For higher concentrations, the excess of carbon is in interstitial site into the crystalline lattice, and does not contribute to the compensation of the lattice mismatch. For a C incorporation superior to 2% nano-crystals of silicon carbide are formed [Guedj 98] [Liu 98]. These constitute crystal defects which can lead to polycrystalline layer and which will always be avoided in silicon devices. If the carbon atoms are placed in interstitial sites they introduce recombination centers and traps which degrade the device performance. At low concentration, the effect of substitutional carbon in SiGe alloys is to increase the material bandgap, and to compensate the biaxial strain of SiGe layers on relaxed silicon substrate. Several publications have focused on the experimental study of the bandgap of SiGeC layers as a function of their substitutional C content [Regolini 94] [Chang 96] [Yuki 01] [Brossard 06]. Figure 3.15 shows the carbon substitutional effect ( ) on SiGeC layers. reduces lattice strain of the SiGeC layer. For increased C concentration, the main SiGe X-ray diffraction peak shifts toward the Si peak, putting in evidence the strain compensation.

Figure 3 .

 3 Figure 3.15 X-Ray diffraction diagrams of SiGeC layers grown with different C concentrations [Brossard 06].

  show the results obtained by Lanzerotti[Lanzerotti 97] and Osten[Osten 98] for SiGeC layers. They prove as the incorporation of low carbon concentration within the SiGe region of SiGe HBTs can significantly suppress boron outdiffusion. The SIMS profile without carbon reveal a strong boron out-diffusion. The SIMS profile with substitutionally incorporated carbon atoms stops the boron outdiffusion nearly completely. They observed reduction in B diffusion effect in both secondary ion mass spectroscopy and electrical characteristics.

Figure 3 .

 3 Figure 3.16 SIMS profiles showing the suppression of boron diffusion by carbon incorporation (a) whitout carbon, (b) with a C content of 0.5% (c) with a C content of 0.9% [Lanzerotti 97].

Figure 3 .

 3 Figure 3.17 SIMS profiles of boron before and after the formation of a phosphorous implanted poly-Si emitter annealed at 950 °C for 30 sec. Buried, box-shaped 30 nm thick Si 0.8 Ge 0.2 layer without (left) and with 10 20 cm -3 carbon background (right) [Osten 98].

[

  Goesele 00]. Carbon can be placed in substitutional site ( , or interstitial site in the silicon lattice ( ). The diffusion of carbon in pure silicon has been modeled by Rucker, Scholz and Cowern [Rucker 99] [Scholz 99] [Cowern 02]. Its action on the substitutional impurity profiles, on accelerating the effective diffusion of vacancy dopants and on reducing the phosphorus and boron diffusion, is demonstrated [Rucker 99.2]. For the levels used during

  SiGeC interstitial and vacancy concentration, and are the point defects at equilibrium thermodynamic, and are the silicon and carbon interstitial concentration, and are the vacancy an interstitial strain parameters, is the germanium content, and are the concentration of interstitials and vacancies in carbon, is the layer strain, is the material bandgap, and are represent the influence of material electric parameters for interstitials and vacancies respectively, and and define the change in the concentration of interstitials and vacancies in SiGe alloys, related to silicon [Pakfar 03]. The diffusion of carbon in silicon involves the mechanisms kick-out and dissociative Franck-Turnbul [Werner 98] [Scholz 99].

Figure 3 .

 3 Figure 3.18 Flux in thermodynamic equilibrium of point defects and of substitutional and interstitial carbon. The different curves represent the product of the diffusivity and concentration in equilibrium of interstitials (purple), vacancies (blue), substitutional carbon (black) and interstitial carbon (red symbols).

  suppression of out-diffusion by carbon incorporation [Jones 97] [Lanzerotti 96]. To understand the diffusion mechanism of boron in SiGe and SiGeC alloys, let us to show how this operates in silicon. Dopants are impurities which will diffuse by interacting with native point defects, such as vacancies (V) or Si self-interstitials (I), which are always present in the crystal. When these impurities are positioned on a site dedicated to silicon, they can ionize and become electrically active. The reactions involving diffusion mechanisms and thus responsible for forming the mobile dopant-point defect complexes are: impurity in a substitutional position, and the impurity in an interstitial position. In the case of boron the diffusion is occurring via interstitials and can take place in two ways as represented in Figure3.19. The simple interstitial mechanism consists to the local deformation of atomic bonds obtained by coupling between an intrinsic interstitial atom and the impurity where both diffuse as an pair. The kick-out mechanism has particular importance since it is the predominant diffusion mechanism of boron in silicon. In this mechanism the impurity atom is kicked out from a lattice site and diffuse as an isolated interstitial .

Figure 3 .

 3 Figure 3.19 Schematic representation of the interstitial mechanism (a) Simple interstitial (b) Kick-out

  of the number of mobile boron atoms through the crystal, and is the Ge fraction. If we consider the expression of elongation as ε = , the boron diffusion becomes:3.17 with the variation of the boron activation energy depending on SiGe film parameters following:

  the change in the concentration of interstitials in the SiGe alloy, related to silicon [Pakfar 03].

  different methods: analytic, fast level-set, and general time-stepping level-set, which are described in MGOALS boundary-moving algorithms. The etch types can be anisotropic (etch in the vertical direction only), isotropic (etch rate is uniform in all directions), directional (in a specific direction), polygonal (according to a polygon specified by the user), crystal (Angledependent etching where etch rate is dependent on the crystallographic direction) [Sprocess 12].

  various thermal annealing cycles, are modeled by the simulator taking into account the following effects:  Dopant (de)activation  Dopant-defect interaction  Chemical reactions at interfaces and in bulk materials  Material flow  Moving material interfaces  Internal electric fields

Figure 3 .

 3 Figure 3.21 2D Key process parameters: a) L-shape oxide spacer width, b) L-shape oxide spacer thickness, c) Nitride spacer, d) Base-collector oxide and e) External to internal base connection.

Figure 3 .

 3 Figure 3.22 TEM picture of the high speed B3T SiGeC HBT (left) vs. TCAD simulation (right).

Figure 3 .

 3 Figure 3.23 TCAD cross section of a SiGe HBT elaborated under B3T technology process flow. a) Process meshing; b) Electrical meshing of final structure, 1D and 2D simulations are gathered for electrical simulation.

a)

  Low current densities: In this region f T is driven by the capacitances. Both parasitic capacitances and junction capacitances can have important effects. To obtain more accurate results in comparison with measurement the collector-base and emitter base capacitances are calibrated with experimental results. A better view of this part of the curve can be found when considering the normalized curves 1/(2f T )=f(1/I C ). b) Low current densities: In this region f T is driven by the capacitances. Both parasitic capacitances and junction capacitances can have important effects. The value of f T in this region is the consequence of the obtained capacitances during the electrical simulation A better view of this part of the curve can be found when considering the normalized curves 1/(2f T )=f(1/I C ). c) Maximum f T : This can be tuned by considering the base width and the Germanium epitaxial profile, both introduced in the 1D command file of the process section. d) High current densities: The f T drops at high current injection because the Kirk effect and it is controlled by the collector resistance and it is highly correlated to the BV CEO curve.

[

  Sdevice 12]. From hydrodynamic simulations the driving force is equals to the effective field obtained from the carrier temperature from equations: from the energy conservation equation under time-independent, homogeneous conditions. The parameters and are fitting coefficients with default value of 1.

  strong impact on electrical characteristics [Salmon 98] [Hållstedt 04] [Hashim 99]. It is shown how these three parameters at adequate values can improve significantly the transistor performance, but also how wrong values can degraded it.We remind that the incorporation of substitutional carbon in pure silicon and SiGe suppress the boron thermal and transient enhanced diffusion (TED). A HBT is a very sensitive probe to analyze such phenomenon in the thin base.

Figure 3 .

 3 Figure 3.24 1D simulation profiles comparing the effect of boron doping level increases.

Figure 3 . 2

 32 Figure 3.25 a) Simulated 1D profile for three different boron doping levels; b) Base width resulting from a doping level of 2.10 19 at/cm 3 ; c) Base width for B doping of 5.10 19 at/cm 3 ; d) Base width for B

Figure 3 .

 3 Figure 3.26 Impact of the boron doping level on B3T technology, figures of merit at V CB = 0 V. a) Gummel plot; b) Maximum oscillation frequency for three different boron doping levels (peaks at V CE ~ 0.85 V).

Figure 3 .

 3 Figure 3.27 Impact of the boron doping level on B3T technology, figures of merit at V CB = 0 V. a) Boron increases effect on f T ; b) Boron increases effect on collector-emitter breakdown voltage (BV CEO ).

3 .

 3 28b), while 0.05% leads to 25 nm (Figure3.28c) and 0.1% reduced the base width to 20 nm (Figure3.28d).

Figure 3 .

 3 Figure 3.28 Impact of the carbon content on boron diffusion and base width. a) 1D representation for three different boron doping levels b) 2D simulation for C percentage=0.1%; c) for C percentage = 0.05%; d) for C percentage = 0.01%.

Figure 3 .

 3 Figure 3.29 and Figure 3.30 show the increase of f MAX and f T with C fraction, and shows the main influence of C in static characteristics. The increment of carbon content increases the lattice scattering inducing a faster breakdown, carbon content values go from 0.01% (C content --) to 0.2% (C content ++).

Figure 3 .

 3 Figure 3.29 Effect of for three different carbon percentages on HBT SiGeC figures of merit for a B doping level of 5.10 19 at/cm 3 , at V CB = 0 V, a) Maximum oscillation frequency; b) Current gain.

Figure 3 .

 3 Figure 3.30 Impact of C percentage increases on electrical characteristics of B3T technology, a) Transition frequency at V CB = 0 V, b) Variation in base and collector currents due to the avalanche multiplication effect.

Figure 3 .

 3 Figure 3.31 Impact of germanium percentage increases on electrical characteristics of B3T technology. a) Gummel plot; b) Transition frequency (f T ) at V CB = 0 V.

Figure 3

 3 Figure 3.32 Effect of germanium percentage increases in the middle (GeB) on electrical characteristics of B3T technology a) f T , b) f MAX , at V CB = 0 V.

Figure 3 .Figure 3 .

 33 Figure 3.33 Effect of germanium percentage increases at collector side (GeC) on electrical characteristics of B3T technology. a) SiGe:C HBT 1D profile; b) Gummel plot.

Figure 3 .

 3 Figure 3.35 Statics characteristics, gummel plot for Vcb = 0 V at 300 K. TCAD simulations validated with two different devices of B3T technology, one with an emitter window of 0.5 um, the other with 0.25 um. The emitter width of both devices is 130 nm.

Figure 3 .

 3 Figure 3.36 Statics characteristics, collector-emitter breakdown voltage BV CEO for Vbe = 0.7 V at

Figure 3 .

 3 35 to Figure 3.38 show the scalability of our simulations. The precision achieved by the calibrated platform establishes the baseline for further architecture exploration.

Figure 3 .

 3 Figure 3.37 Dynamic characteristics; transition frequency (f T ). TCAD simulations are validated with two different devices of B3T technology, one with an emitter window of 0.5 um, the other with 0.25 um. The emitter width of both devices is 130 nm, Vcb = 0 V at 300 K.

Figure 3 .

 3 Figure 3.38 Dynamic Characteristics, f MAX . TCAD simulations are validated with two different devices of B3T technology, one with an emitter window of 0.5 um, the other with 0.25 um. The emitter width of both devices is 130 nm.

Figure 3 .

 3 Figure 3.39 Base-emitter and base-collector capacitances TCAD simulations for Vcb = 0 V at 300 K, B3T technology with an emitter window of 0.25 um and emitter width of 130 nm.

  device fabricated at IHP (Germany) in 2003, achieved 200/185 GHz of f T / f MAX with breakdown voltage BV CEO = 2 V. HBT already includes carbon in the SiGe base, and isolation is without deep trenches (DTI). It uses a high-dose ion implantation for the collector after the formation of shallow trenches (STI) [Heinemann 03]. In 2007, in a 0.13 µm technology, IHP has presented a HBT featuring f T / f MAX values of 255 / 315 GHz. For this device the effective emitter area is 0.17 x 0.53 µm 2 and breakdown voltages were BV CEO = 1.8 V, BV CBO = 5.6 V, and BV EBO = 1.9 V. In such device the emitter area was completely enclosed by elevated extrinsic base regions. The self-aligned design leads to reduce the device parasitics R B , C BC and R C enabling highest RF performance [Rücker 07].

Figure 4 . 1

 41 Figure 4.1 Schematic cross section of IHP SiGeC HBT using 0.25 µm BiCMOS technology [Heinemann 10].

Figure 4 . 2

 42 Figure 4.2 TEM cross-sectional view of IMEC SiGeC HBT 0.13 µm technology [IMEC].

  IBM has been recognized by its high-performance devices early from 2000. Notably in 2002 they attained 207/285 GHz of f T / f MAX for a HBT with an emitter area of 0.12×2.5µm² [Jagannathan02]. In 2003 with a similar device shown in Figure 4.3, they reach values for f MAX of 338 GHz owing to a 120 reduction of the base resistance, but penalizing f T which dropped to 180 GHz [Jagannathan03].

Figure 4 . 3

 43 Figure 4.3 Cross Section of IBM SiGe HBT architecture (0.25um) [IBM 1]

Figure 4 . 4

 44 Figure 4.4 Schematic cross section of Freescale SiGeC HBT using 0.18µm BiCMOS technology [John 07].

  B3T process technology are suppressed. This device is developed in order to focus on the reduction of the collector-base (CB) capacitance and to study the possibility of yield a low cost transistor with high performances. The resulting structure of the TCAD simulation is showed in Figure 4.5 and Figure 4.6.

Figure 4 . 5

 45 Figure 4.5 One-active architecture. The collector base oxide thickness (CB-Ox) has a value of 150nm.

Figure 4 . 6

 46 Figure 4.6 Lateral dimensions of the low cost architecture. Brown areas indicate oxide regions, orange areas the N type doping, blue areas the P type doping.

Figure 4 Figure 4 . 8

 448 Figure 4.7 2D simulations of low cost architecture and the CB total capacitance; a) CB-Ox of 50 nm b) CB-Ox of 100 nm c) CB-Ox of 150 nm and illustration of the collector-base total capacitance components: CB junction capacitance (left) and the CB-Ox capacitance (right).

Figure 4 .

 4 Figure 4.9a shows the low cost HBT architecture illustrating the location of the undoped region and of the CB TEOS oxide. Figure 4.9b gives the CB capacitance in function of three

  Figure 4.9b gives the CB capacitance in function of three collector-base oxide thicknesses of 50, 100 and 150 nm.

Figure 4

 4 Figure 4.9 a) Low cost HBT architecture showing the placement of the non-doped region and the CB TEOS oxide. b) CB oxide capacitance in function of the collector-base oxide thickness.

Figure 4 .

 4 Figure 4.10 shows the dependence of the CB capacitance with the increase of the thickness of the doping region. It can be seen how the C BC is reduced when the SEG of collector doped region is smaller, due to the increase of the thickness of the undoped collector.

Figure 4 .Figure 4 .

 44 Figure 4.11 shows the reduction of the collector-base capacitance with the doping level of the collector with a fixed 50 nm thick undoped region. Three doping levels of 10 17 , 10 18 and 10 19 at/cm 3 , are represented. The CB TEOS oxide thickness is always at the fixed value of 150 nm. At lower doping level, the depletion region can easily extend into the doped collector, increasing the effective depletion thickness. Best results were obtained for f T and for f MAX with the low value of the doping level, with 195 GHz and 240 GHz, respectively.

Figure 4 4. 2 . 2 . 2

 4222 Figure 4.12 TCAD representation of the spacer role in the low cost structure. a) Thin TEOS oxide before etching; b) Amorphous-poly spacer and thin TEOS oxide after etching; c) Poly-silicon deposition for emitter formation.

Figure 4

 4 Figure 4.13 2D representations of the spacer issue during the elaboration of the low cost architecture. a) Emitter open window, b) Amorphous poly deposition c) Spacer definition by amorphous poly etching.

Figure 4 .Figure 4

 44 Figure 4.14 Spacer etching process. a) Slope of the amorphous-poly deposition which determinates the spacer shape. b) Spacer shape obtained after an anisotropic etching for a TEOS oxide thickness of 80nm and an amorphous-poly thickness of 80nm, the poly slope at the middle of the emitter window is kept during the anisotropic etching.

FigureFigure 4 .

 4 Figure 4.16 Spacer etching process. a) Ideal spacer shape obtained with a high amorphous-poly slope. Over-etching consumes only the upper part of spacer. b) Because a low slope the emitter contact distance will be dependent only on the etching process. Over-etching consumes the amorphous-poly in all directions.

Figure 4 .Figure 4 .

 44 Figure 4.17 shows different dimensions involved in the spacer formation and the triangle formed by them. This triangle allows us to define the slope during the deposition process; to obtain the triangle dimensions the following dimensions are defined:

Figure 4 .

 4 Figure 4.18 Buried Collector architecture obtained after the 2D simulation. Green areas indicate the not doped regions. It is possible to identify the extrinsic emitter and Sinker (dark orange), and the extrinsic base (blue).

Figure 4 .

 4 Figure 4.19 compares f MAX and f T values for the three architectures studied. The three structures have the same emitter window (200 nm) and the same emitter junction width (110 nm).

Figure 4 .

 4 Figure 4.19 Comparison of dynamic performances for the three architectures. a) Low cost B3T. b) Buried collector B3T and c) B4T, at V CB = 0 V.

  develop a device able to give maximum oscillation frequencies beyond 400 GHz. This simulation project uses the same physical model developed for the B3T technology and is based on the full description of all fabrication process steps of the B4T technology developed at STMicroelectronics [Chantre 10]. This is a fully self-aligned HBT with a selective epitaxial growth of the boron doped SiGe:C base layer. The collector is formed by a n+ buried layer, an epitaxial low-doped layer on it and a selectively implanted collector (SIC). The emitter is arsenic-doped and covered by the poly-emitter. A cross sectional cut of this architecture can be seen in Figure 4.20. The color scale of the doping level shows in red the emitter region with a large part on the top in polysilicon. The base appears in blue, and the intrinsic layer in only extended by 0.11 µm in the view. Under the base, the collector shows the shape of the doping due to the SIC.

Figure 4 .

 4 Figure 4.20 B4T architecture generated at the end of electrical simulation. Because of symmetry, only one half of the structure is simulated.

B4T

  TCAD platform is based on the accurate results provided by B3T technology simulations. This technology is the outcome of a detailed analysis of main device trade-offs and process capabilities. The collector doping was modified, as well as the base profile, the process thermal budget and device layout rules. The B4T structure can be seen in the TEM picture of Figure4.21. In this case, the CMOS integration limitations were avoided implementing an only HBT process fabrication [Chantre 10].

Figure 4 .

 4 Figure 4.21 Comparison of dimensions between BiCMOS9MW and B4T SiGeC HBTs.

Figure 4 .

 4 22 and Figure 4.23 compare the simulated electrical characteristics to the measured results through the main figures of merit: Gummel plot, maximum oscillation frequency (f MAX ) and unity current gain transition frequency (f T ).

Figure 4 .Figure 4

 44 Figure 4.22 shows the Gummel plot for a transistor with an emitter width of 110 nm. The maximum current gain is about 2000 at V BE close to 0.72 V. The collector-emitter breakdown voltage B VCEO is 1.5 V at V BE = 0.7 V and it is shown in Figure 4.23. In both statics characteristics an excellent agreement was achieved between measurements and simulations.

Figure 4 .

 4 Figure 4.23 Statics Characteristics, collector-emitter breakdown voltage BV CEO for a B4T transistor, V BE = 0.7 V at 300 K.

Figure 4 .

 4 Figure 4.24 Dynamic characteristics of f MAX and f T . Overlays between TCAD simulations and measurements for a B4T transistor, V CB = 0.5 V at 300 K.

Figure 4 .

 4 Figure 4.26 Base resistance as a function of collector current for B4T (W E =110nm) and B4T+ (W E =90nm) devices.

  Figure 4.27 shows the weak dependence of carbon and boron content on f T : Except for too low C content where the base thickness (W B )becomes large with high doping level, the carbon helps to reduce the doping level W B and thus of f T . This low negative impact provides a space to increase f MAX up to 480 GHz as shown in Figure4.28 with the increase of the base doping level.

Figure 4 .

 4 Figure 4.27 Carbon percentage and boron doping concentration effect on f T . SiGeC HBT with an emitter width of 90nm from B4T technology.

Figure 4 .

 4 Figure 4.28 Carbon percentage and boron doping concentration effect on f MAX . SiGeC HBT with an emitter width of 90nm from B4T technology.

Figure 4 .

 4 Figure 4.29 Carbon percentage and boron doping concentration effect on R B . SiGeC HBT with an emitter width of 90 nm from B4T technology.

Figure 4 .

 4 Figure 4.30 Carbon percentage and boron doping concentration effect on current gain. SiGeC HBT with an emitter width of 90nm from B4T technology.

Figure 4 .

 4 Figure 4.31 Energy band diagram of a graded-base SiGe HBT. The introduction of Ge and C into the base region generates a hole repelling effect owing to energy gap between the emitter and the base.

Figure 4 .

 4 Figure 4.32 Carbon percentage and boron doping concentration effect on base-collector and baseemitter capacitances. SiGeC HBT with an emitter width of 90 nm from B4T technology.

Figure 4 .

 4 Figure 4.33 Germanium impact on electrical characteristics in a SiGeC HBT with an emitter width of 90nm from B4T technology. GeE and GeC percentages effect on (a) f T , (b) f MAX and (c) current gain. GeE and GeB percentages effect on (d) current gain, (e) f T , and (f) f MAX (maximum values extracted for V CB = 0 V).

4.5. 1 . 3

 13 Influence of process parameters I: Emitter Window, Base Connection, SIC Energy and Dose.The lateral shrinking is a crucial aspect to increase f MAX and keeping good values for other electrical characteristics. In order to continue along the same path we have reduced the emitter window, illustrated in Figure4.34, and its effect on B4T transistor is analyzed. This shrinking is performed on W (the emitter window width), and due to the ST self-alignment process, it not impact the base connection length shown in Figure4.34.

Figure 4 .

 4 Figure 4.34 2D simulations of B4T architecture showing the emitter window (W) and base connection distance.

Figure 4 .

 4 Figure 4.35 Emitter Window and Base Connection effect on electrical characteristic in a SiGeC HBT with an emitter width of 90nm from B4T technology. Impact on (a) f T , (b) f MAX (c) current gain, (d) emitter-base capacitance, (e) collector-base capacitance, and, (f) base resistance.

Figure 4 .

 4 Figure 4.36. Best f MAX results are found for the higher implantation energy values and for the intermediate values of the SIC dose. In the case of f T , the best results are obtained for a SIC energy around 250 keV and intermediate values of SIC dose. Enhancement of f MAX is due to the reduction of collector capacitance. The current gain is improved with the reduction of the SIC implant energy which leads to an increases in collector current.

Figure 4

 4 Figure 4.36 SIC effect on electrical characteristic in a SiGeC HBT with an emitter width of 90nm from B4T technology. Effect on (a) f T , (b) f MAX (c) current gain, (d) emitter-base capacitance, and, (e) collector-base capacitance.

Figure 4 .

 4 Figure 4.37 Amorphous-poly to be etched and collector-base Oxide of a B4T transistor.

Figure 4 . 2

 42 Figure 4.38 Parameters effect on B4T device. Poly etch and BC-Ox on a) f MAX , b) f T c) Current Gain. Spike annealing and selectively implanted collector (SIC) on (d) f T , (e) f MAX , and (f) current gain.

Figure 4 .

 4 40 leads to a BV CEO of about 1.57 V. The maximum current gain is 1800 as plotted in Figure4.41. For the f T peak, the bias is I C = 13 mA and V BE = V CE = 0.89 V, and for the f MAX peak, I C = 11 mA and V CE = 0.88 V.

Figure 4 .

 4 Figure 4.39 Simulated dynamic characteristics: f T and f MAX vs. I C for B5T technology for V CB = 0.5 V.

Figure 4 .

 4 Figure 4.40 Simulated statics characteristics: breakdown voltage (BV CEO) for B5T technology for V CB = 0 V at 300 K.

Figure 4 .

 4 Figure 4.41 Simulated statics characteristics: Gummel plot and current gain for B5T technology for V CB = 0 V at 300 K.

Figure 4 .

 4 Figure 4.42 TCAD simulations: comparison of f T and f MAX vs. I C for B3T, B4T and B5T technologies for V CB = 0.5 V at 300 K (V CE ~ 1.35 V).

  etching process. Based on TCAD studies we showed how to obtain vertical spacers. The amorphous-poly deposition thickness must respect a specific law and we explained how to calculate this thickness.

  this dissertation, the theory, technology development and technology modeling of state-ofthe-art SiGe and SiGeC heterojunction bipolar transistors have been investigated. The results of this work should help to obtain more physical and realistic simulations, better understanding o charge transport, and facilitate the development and optimization of SiGe and SiGeC HBT devices.In the first chapter of the thesis, the SiGe SiGeC heterojunction bipolar technologies and their operating principles were introduced. First chapter dealt also with the high frequency AC transistor operation, we presented the extraction techniques on which we based to developed TCL-based scripts to extract f MAX and f T from the small-signal simulations.Second chapter dealt with the transport modeling in SiGe and SiGeC HBTs and its electrical simulation. This work involved setting up physical models adapted to SiGeC strained alloys, notably, based on previous work, we presented new MC-based analytical models for effective DOS in electrons and holes. We elaborated these models for SiGeC strained and relaxed layers simulation purposes. It was seen how the existing effective DOS models not take into account critical dependencies as the strain-related effects and ignore the carbon content.Second chapter was an important work of synthesis leading to the selection, implementation and development of models which could not exist until now. We demonstrated the impact of carrier statistics and the bandgap narrowing models and how this can produces important issues and false results during its implementation. At the end of the chapter the effect of the SiGeC transport model was made evident with the comparison of two distinct set of models for transport parameters: the SiGe default models of the physic based device simulator, and the SiGeC specific models implemented by us in the same simulator.The chapter three explained the B3T TCAD simulation project for B3T technology devices.The final result of this project is the B3T simulation Kit elaborated to simulate the static and dynamic characteristics of this type of devices and to extract major figures of merit and first order parameters. The simulation Kit takes into account the impact of the strain, of germanium and carbon content into the base, not only in the process simulation but also in the electrical simulation. Each step of the process flow is also simulated leading to an accurate prediction of the active dopant distribution, of the stress distribution and of the device geometry.In chapter three the boron doping level, of the carbon and the germanium percentages on B3T technology were analyzed. We demonstrated how these three parameters have a strong impact on electrical characteristics of SiGeC HBTs and how adequate values can improve significantly the transistor performance, and wrong values can degraded it. The diffusion models used for the dopant diffusion in SiGeC alloys were explained showing the importance of use of carbon to trap self-interstitials in order to reduce the impurities diffusion. At the end of chapter the mixed-mode simulations on the HBT final structure are validated comparing with experimental measurements.

Résumé de la thèse "1 1 . 1

 thèse11 Recherche et développement de transistors bipolaires avancés par le biais de la modélisation technologique" Ce travail explore le développement technologique de transistors bipolaires à hétérojonction SiGe et SiGeC au moyen de la conception technologique assistée par ordinateur (TCAD). L'objectif est d'obtenir un dispositif avancé très proche du dispositif réalisable, en agissant non seulement au niveau des étapes technologiques, mais aussi en rendant compte assez fidèlement son comportement physique, sa géométrie et ses performances électriques. Les études menées permettent l'obtention du meilleur fonctionnement électrique pour les dispositifs analysés, en particulier avec une fréquence maximale d'oscillation de 500 GHz. Cette valeur correspond à l'objectif fixé par le projet Européen DotFive dans lequel ce travail s'inscrit pour STMicroelectronics, et les évolutions de sa filière BiCMOS avancée. Les résultats de ce travail aide à obtenir des simulations plus physiques et réalistes, à avoir une meilleure compréhension des mécanismes de transport des charges dans la structure, et de faciliter le développement et l'optimisation des transistors bipolaires a hétérojonction (TBH) SiGe et SiGeC. Le premier chapitre du manuscrit présente le principe de fonctionnement du transistor bipolaire et du TBH SiGe ou SiGeC. Ce chapitre traite également son fonctionnement à haute fréquence, en y décrivant des méthodes d'extraction de la fréquence maximale d'oscillation (f MAX ) et de la fréquence de transition du gain en courant (f T ), deux facteurs de mérite qui seront exploités pour l'étude des performances. Le premier chapitre se termine par la description du transport dans les dispositifs bipolaires, notamment le modèle hydrodynamique utilisé lors des simulations. Le deuxième chapitre analyse les modèles physiques spécifiques aux alliages SiGe et SiGeC contraints sur silicium et utilisés dans la base des TBH, et la simulation électrique de ces dispositifs. Ce chapitre est aussi un important travail de synthèse menant à la sélection, à la mise en oeuvre et au développement des modèles dédiés à la simulation des TBH SiGeC. Le troisième chapitre décrit la plateforme de simulation TCAD développé pour la technologie B3T afin d'obtenir un modèle de TBH (résultats de simulation) très proche du dispositif fabriqué par STMicroelectronics. Dans ce chapitre l'ensemble des étapes de fabrication des TBH de la technologie B3T sont décrites, ainsi que la méthodologie développée pour simuler ces dispositifs. Le dernier chapitre détaille les architectures de TBH développées durant la thèse. Les structures proposées sont d'une part une version faible cout (moins d'étapes technologiques) et de moindre performance, et à l'inverse des structures à hautes performances nécessitant un cout de production plus élevé. Il est discuté et étudié particulièrement la technologie B4T qui a été réalisée en salle blanche. L'impact des principales étapes de fabrication est analysé afin de trouver les paramètres clés pour accroitre f MAX sans dégrader les autres caractéristiques électriques. A la fin du chapitre, les résultats obtenus sont utilisés pour élaborer une nouvelle plateforme de simulation qui tient compte des meilleurs compromis entre les différents paramètres des procédés de fabrication pour obtenir un TBH SiGeC avec une valeur de f MAX d'au moins 500 GHz. Fonctionnement du transistor bipolaire a hétérojonction SiGe/SiGeC et le transistor bipolaire au silicium L'ingénierie de bande interdite utilisée dans la conception des TBH SiGe ou SiGeC est la clé de l'amélioration des performances statiques et dynamiques de tels dispositifs. Comme l'alliage SiGe ou SiGeC contraint en compression a une bande interdite plus petite que celle du silicium, un transistor bipolaire avec une base SiGe ou SiGeC conduit à des valeurs beaucoup plus élevées du gain en courant. D'autres avantages (mobilité électronique…) favorisent les performances du TBH npn à base SiGe. Fonctionnement à haute fréquence Les caractéristiques dynamiques d'un transistor disposent de deux principales figures de mérite que sont la fréquence de transition du gain en courant (f T ) et la fréquence maximale d'oscillation (f MAX ). Dans cette section nous décrirons l'une des méthodes d'extraction pour f MAX qui a été développée et implémentée dans le simulateur TCAD pour l'étude des résultats de simulation en régime dynamique.

1. 2

 2 Extraction de la fréquence maximale d'oscillation f MAX Bien que f MAX soit la fréquence de transition du gain de Mason U, l'extraction de f MAX peut être faite à une autre fréquence fixée, sur l'hypothèse de décroissance du gain suivant -20dB/décade. Ainsi pour chaque point de polarisation la simulation en régime dynamique est faite pour une zone limitée en fréquence. Dans le script développé nous trouvons un point dans la zone de décroissance à -20dB/décade et à partir de ce point par extrapolation nous obtenons la valeur de la fréquence pour U = 0dB comme le montre la Figure 1.14.

Figure 0 . 1

 01 Figure 0.1 Diagramme de Bode pour la méthode d'extraction de f MAX à un point.

Frequency 2 . 2 LFigure 0 . 3

 2203 Figure 0.3 Modèles pour la densité d'états pour les alliages Si 1-x-y Ge x C y. Les symboles représentent les simulations Monte Carlo, les lignes notre modèle, pour les électrons (a) et les trous (b).

  Dans nos simulations, la réduction de bande interdite selon le taux de Ge et de C est modélisée avec la formule de Bean [Bean 92], en particulier pour les alliages SiGe contraint en compression. En fonction de la température, avec un coefficient c 4 pour l'influence du carbone, l'expression de bande interdite devient: forte influence sur les caractéristiques électriques [Salmon 98] [Hållstedt 04] [Hashim 99]. On montre comment ces trois paramètres peuvent améliorer considérablement les performances du transistor, mais aussi peuvent les dégrader.

( 10 à

 10 25 nm), sans nuire à l'efficacité de la jonction base-émetteur, et il est possible de fortement doper la base pour maintenir une faible valeur de résistance de base (R B ) et pour éviter le risque de perçage. Une conséquence du niveau de dopage de bore et du profil de dopage est la largeur effective de la base W B . Pour les faibles niveaux de dopage, le profil de dopage est plus étroit dans la base SiGeC, les frontières des jonctions émetteur-base (EB) et base-collecteur (BC) sont plus proches, et la valeur de W B , est faible. Au contraire, pour les niveaux plus forts de dopage, le profil de dopage plus étalé éloigne les jonctions BE et BC, conduisant à un W B plus grand. Le niveau de dopage du bore a aussi une incidence directe sur la mobilité électronique ce qui influence les caractéristiques électriques du dispositif. technologie B3T, utilisé comme point de départ pour étendre le modèle à d'autres architectures. Les deux premières architectures proposées et investies sont des solutions faibles coûts qui pourraient être utilisées pour des applications avec des exigences en performances limitées. La troisième architecture (B4T) a pour objectif l'amélioration des performances dynamiques, notamment la fréquence maximale d'oscillation pour attendre les 400 GHz. Nous étudions l'architecture B4T et analysons l'impact des principales étapes de fabrication afin de trouver les paramètres du procédé de fabrication qui permettent d'augmenter f MAX sans dégrader les autres caractéristiques électriques. Les résultats obtenus sont utilisés pour élaborer une plate-forme de simulation TCAD en tenant compte du meilleur compromis des différents paramètres clés du procédé.

  Figure 4.19 compare les trois architectures étudiées et les résultats électriques obtenus pour f MAX et f T . Les trois structures ont la même fenêtre d'émetteur (200 nm) et la même largeur de jonction d'émetteur (110 nm). Pour la première architecture à faible coût sans tranchée d'isolation STI (Figure 4.19a) f MAX vaut environ 220 GHz et la valeur maximale de f T est de 190 GHz. Pour la deuxième architecture à faible coût (Figure 4.19b) f MAX est de 280 GHz et f T de 210 GHz. Les meilleures performances ont été obtenues pour l'architecture B4T avec le couple f T /f MAX de l'ordre de 260/400 GHz.

Figure 0. 5

 5 Figure 0.5 Comparaison des performances dynamiques pour les trois architectures développées ; a) et b) Architectures à faible coût; c) B4T.

Figure 0 . 6

 06 Figure 0.6 Comparaison des résultats électriques TCAD et mesures expérimentales a) Courbes de Gummel et gain en courant; b) f T et f MAX .

  Les premiers paramètres à prendre en compte sont le niveau de dopage de bore et la teneur en carbone. D'après les résultats analysés dans les études précédentes, pour le bore, le niveau de dopage est établi à 8,5 × 10 19 at/cm 3 , pour le carbone le pourcentage est fixé à 0,5%. Dans le cas de la teneur en germanium, le meilleur compromis trouvé est une composition avec trois marches d'épaisseurs différentes: 15%, 26% et 30% pour GeE, GeB et GeC, respectivement. D'autres paramètres optimaux sont une largeur d'émetteur de 170 nm, une largeur de liaison entre la base intrinsèque et extrinsèque de 25 nm, une température de recuit final de 1080°C et une gravure de 200 nm du poly-silicium amorphe. Avec cette configuration nous avons obtenu un pic de f T de 295 GHz et un pic de 554 GHz pour f MAX. Les performances en f T et f MAX des dispositifs B5T sont comparés avec les technologies B3T et B4T sur la Figure 4.42. Alors que l'amélioration de f T est modérée entre les trois technologies avec une valeur maximale de ~260 GHz pour B3T et B4T et ~280 GHz pour B5T, f MAX s'est améliorée considérablement avec 17% entre B3T et B4T et 18% entre B4T et B5T.

Figure 0. 8

 8 Figure 0.8 Comparaison des résultats f T et f MAX pour les technologies B3T, B4T et B5T pour V CB = 0.5V à 300 K.

  1 Effect of the boron doping level ......................................................................... 3.5.1.1 Boron Diffusion Effect on the Base Width ...................................................... 3.5.1.2 Boron Doping Level Impact on Electrical Characteristics .............................. 3.5.2 Carbon Content ................................................................................................ 3.5.2.1 Carbon Diffusion Effect on the Base Width ................................................... Influence on Frequency Performance and Current Gain ............................... 3.5.3 Germanium Profile Effect .................................................................................. 3.5.3.1 Effect of Germanium Percentage at the Emitter Side (GeE) .......................... 3.5.3.2 Effect of Germanium Percentage in the Middle (GeB) ...................................

	3.5.2.2

3.5.3.3 Effect of Germanium Percentage at the Collector Side (GeC) ....................... 3.6 Electrical Results .................................................................................................. 3.6.1 Static Characteristics ........................................................................................

  ..... 4.2.2 Spacers poly formation issue ............................................................................ Geometry Dependence ................................................................................. 130 4.2.1 Buried Collector Architecture ............................................................................ 131 4.2.2 Performances comparison ................................................................................ 132 4.3 B4T Architecture .

4.2.2.1 Spacers role in low cost architecture ............................................................. 4.2.2.2 Spacers issue ............................................................................................... 4.2.2.3 Spacers Etching Shape ................................................................................. xv 4.2.2.4

  Le modèle de bande interdite ................................................................................ 2.4 Modèles de mobilité des électrons et des trous dans les couches contraintes SiGeC fortement dopées .................................................................................................. 2.5 Le modèle du temps de relaxation de l'énergie .....................................................3 Influence des paramètres technologiques sur la technologie B3T ......................... 3.1 Composition et modélisation de la diffusion des dopants ...................................... 3.2 Simulation et calibrage des dispositifs B3T ........................................................... 3.3 Influence du niveau de dopage (bore) ................................................................... 3.4 Influence du carbone ............................................................................................

..... 176 2.1 Masses effectives d'électrons et de trous.............................................................. 176 2.2 Les modèles de densité effective d'états .............................................................. 176 xvi 2.3 3.5 Influence du profil de germanium .......................................................................... 3.5.1 Effet du pourcentage de germanium côte émetteur (GeE) ................................ 3.5.2 Effet du pourcentage de germanium côte collecteur (GeC) ...............................

Table 2 .1

 2 Properties of Si, Ge and C at room temperature.

	Parameter	Si	Ge	C	Unit
	Eg	1.12	0.66	5.47	eV
	a	5.43	5.66	3.57	Å
		2.33	5.32	3.52	g/cm 3
	ε	11.90	16.20	5.70	-

Table 2 . 2

 22 Effective masses of electrons for Si and SiGeIn the Sentaurus device simulator the DOS effective mass for silicon is modeled by the

	[Sentaurus 12] with M C = 6,	and	calculated from
	the relationship:
			2.2

Table 2 .3.Table 2 . 3

 223 SiGeC Effective Mass Parameters

	Parameter	Value	Unit
	c1	-0.96	eV
	c2	0.43	eV
	c3	-0.17	eV
	c4	0.3	eV

Table 2 .4 SiGeC Strain Parameters

 2

Table 2

 2

		5	x 10	19
							MC T=500K
	) -3 (cm	4					MC T=400K MC T=300K MC T=200K
	DOS	3					SiGeC Model
	Holes Effective	1 2
		0	0	0.05	0.1	0.15	0.2	0.25	0.3
				Germanium Content
	.5 SiGeC Effective Mass Parameters
	ELECTRONS				HOLES
	Parameter			Value			Parameter	Value
	MC1			4			MV1,MV2,MV3	1
	MC2			2
	ΔEC[eV]			0.6			ΔEV1, ΔEV2	0.3
	Ce			0.16			Ch		0.47

Table 2 .6

 2 Advanced Models Parameters of the SiGeC bandgap

	Parameter	Value		Unit	Reference
	Eg,0	1.17		eV	[Sentaurus 10]
		4.73x10	-4	eV/K	[Sentaurus 10]
		636		K	[Sentaurus 10]
	c1	-0.96		eV	[Palankovski 99]
	c2	0.43		eV	[Palankovski 99]
	c3	-0.17		eV	[Palankovski 99]
	c4	3.40		eV	[Pakfar 03]

  model to consider degeneracy effects. If the use of the Boltzmann statistic with the real BGN model will give surely wrong results for HBTs, the Boltzmann statistic and the apparent BGN will not replace exactly the right modeling with the Fermi-The experimentals values of the BGN (real BGN) and of the apparent BGN are shown in

	Dirac statistic.	2.16
	which can be write as 2.4.3.2 BGN and Apparent BGN Models
			2.17
	The above equation can be used for low-doped semiconductors. For high-doped
	semiconductors, depending on carrier statistics, we must use the effective intrinsic density
	corrected with the BGN
			2.18
	or
			2.19
	In equation 2.18 the degeneracy effects for high doping concentrations of Fermi-Dirac
	statistic are expressed through the terms	and , which are given by
			2.20
			2.21
	where	is the Fermi integral of order 1/2 [Grundmann 06].
	Thus for simulations using the Fermi-Dirac statistic, the bandgap model must not
	incorporate the degeneracy effects, and only the real BGN model should be used. If the
	Fermi-Dirac statistic is used with the apparent BGN model, degeneracy effects are wrongly
	taken twice into account.

Nevertheless, if the Fermi-Dirac statistic is not available, the Boltzmann statistic can be used, working well for low doped semiconductors, and employed at high doping level, using the apparent BGN

of biaxial strain: Anisotropic Mobility Strain

  Phonon scattering is complex in materials such as Silicon and Germanium, due to inter and intra valley scattering [Eastman 60] [Tripathi 03] [Hebling 09].The temperature dependence of electron and hole mobilities is shown in Figure2.19 for various impurity concentrations. Mobilities are illustrated only for the case of Si 0.74 Ge 0.25 C 0.01 . properties of SiGeC alloy in biaxial compression yield an anisotropic mobility with a lateral and a vertical component to the layer. For the high symmetry growth on the [001] direction this can be quantified by a mobility tensor[Bufler 97.1] [Manku 92]

	2.5.2.2 Impact
	To summarize this mechanism on the mobility, the well-known power dependence on
	temperature is used
						2.22
	where	denotes the carrier mobility limited by phonons at 300 K under the influence of the
	strain. If	was derived from MC simulations at room temperature, the coefficient is an
	empirical parameter obtained from experimental studies [Michaillat 10.2]; it is different for
	Silicon and Germanium [Landolt-Bernstein 82] [Prince 92]. The	strain dependency will
	be discussed later.
		(cm 2 /Vs)	500 600 700 800 1000 900	Ge content=25% Ge content=25% Ge content=25% Ge content=25% C content=1% C content=1% C content=1% C content=1%	N=1e21 N=1e15 N=1e18 N=1e19
		Mobility	300 400
		Electron	200
			200	300	400	500	600
					Temperature (K)
			600
			500
						N=1e15
		/Vs)	300 400	Ge content=25% Ge content=25% Ge content=25% Ge content=25% C content= 1% C content= 1% C content= 1% C content= 1%	N=1e18 N=1e19
		2 (cm	200			N=1e21
		Mobility	100
		Hole
			200	300	400	500	600
				Temperature (K)

Figure 2.19 SiGeC mobility model. Electron and hole mobilities versus temperature: comparison at different doping concentrations at Ge content of 25% and C content of 1%.

Table 2 .7 and Table 2.8.

 2

Table 2 .7

 2 Parameters for the in-plane and out-plane hole mobilities.

		cm 2 /Vs		cm 2 /Vs	cm 2 /Vs	cm -3	cm -3
	Si		2.2	42	104	3.10 17	3.10 17	0,70	0,70
	Ge	1800	2,3	42	134	9.10 16	9.10 16	0,65	0,60
			60	70	170	3,4	3

For typical values in HBT (Ge 10-30% and C lower than 0.2%) the SiGeC layer is always in compressive strain.

Table 2 .8

 2 Parameters for hole mobilities, longitudinal and transverse components.

Table 2 .9 and Table 2.10.

 2

	In order to obtain the same behavior than the Reggiani model [Reggiani 99] [Reggiani 02]
	we calibrated the values of ,	and	We calibrated with Reggiani model, because
	in this a wider range of operating conditions has been investigated and the doping
	dependence of bulk mobilities for both majority and minority carriers has been widely
	developed. The calibrated model is compared with Reggiani's model in Figure 2.22. It should
	be mentioned that the change of mobility as a function of doping for silicon does not impact
	the others mobility components since each one is independently calculated:

to mobility in silicon reported in literature, the default values of the SiGeC model extracted by Michaillat [Michaillat 10.2] leads to an overestimation of the electron mobility when Ge and C content are zero as shown in Figure 2.22a. This generates an overestimation of the collector current as well as imprecise values for the other electrical characteristics.

Table 2 .9

 2 Parameters for the in-plane and out-plane electron mobilities.

		cm 2 /Vs		cm 2 /Vs	cm 2 /Vs	cm -3	cm -3
	Si		2.4	10	65	1.1 17	8,5.10 16	0,78	0,75
	Ge	3500	1,6	450	100	1.10 17	6.10 16	0,70	0,80

Table 2 .

 2 10 Parameters for electron mobilities, longitudinal and transverse components.

  of carriers at high energies. It can be calculated by Monte Carlo simulation from stationary results in a homogeneous material. In order to simulate the charge transport at high energies, it is necessary to integrate a numerical description of the band structure. In our simulations the model used for the relaxation time of the carrier energy was extracted usingThe effects of carbon content (up to 2%) and doping concentration on the simulated relaxation time are negligible[Michaillat 10.2]. Therefore, the carbon content is not included on the modeling of the relaxation time[Michaillat 10.2].

	In expression 2.30, the parameter	controls the influence of the germanium percentage.
	the indirect method developed by Palankovski [Palankovski 99]. For SiGeC alloys it was
	modeled by the Michaillat model [Michaillat 10.2] as a function of the ratio between the
	carrier temperature	and the lattice temperature , as follows:
			2.30

Table 3 . 1

 31 Parameters of the Arrhenius law for concentrations and diffusivities of substitutional and interstitial carbon in thermodynamic equilibrium.

	Parameter	Pre-exponential Factor	Activation Energy (eV)
			4.10 24 cm -3	2.3
			2.10 25 cm -3	4.52
	D( )		1.99 cm -2 .s -1	3.1
	D( )		0.44 cm -2 .s -1	0.88
	Reactions 3.3 and 3.4 define the balance between populations of carbon in interstitial and in
	substitutional sites and of point defects. The	atom diffuses rapidly in silicon by direct
	interstitial mechanism, while the	diffuses four times slower because it uses reactions kick-
	out and Frank-Turnbull. The kick-out is the dominant diffusion mechanism of carbon in

  on transistor performances. As already claimed in different articles, if the C content exceeds typically more 2%, it can degrade transistor's behavior [Osten 98] [Lanzerotti 96] [Bouhouche 09]. Carbon atom placed in substitutional sites can create nano-crystalline SiC clusters, recombination centers and generate significant leakage currents [Boucaud 94].

Table 4 .

 4 1 CB capacitance calculated for a non-doped silicon epitaxy region for three different CB oxide thickness at V BC = 0 V.

	CB Oxide	Extracted Capacitance
	Thickness	Vbc=0 (fF/um)
	(nm)	Total	CB-Oxide	Junction
	50	15.9	0.985	14.915
	100	11.17	0.629	10.541
	150	9.54	0.546	8.994

TEOS Oxide cap Spacer Poly Emitter Chapter 4. Optimization Towards f MAX 500 GHz 128

  due to the narrow emitter window. Thus the free access to the TEOS oxide cap on top is blocked.

Table 4 .

 4 2 shows the dynamic performances among the different BiCMOS technologies at STMicroelectronics. One of the main difference of B4T in relation to B3T technology is the lateral scaling performed on B4T, it includes: a reduction of the distance from sinker to

	From BiCMOS9MW
	to B4T Technology

Table 4 . 2

 42 Comparison of emitter window size and dynamic performances (f T and f MAX ) among

	BiCMOS9MW, B3T, B4T and B4T+.

Table 4 .

 4 3 and Table4.4 show critical 1D and 2D process parameters used during the process simulation. We should identify the parameters which play the most important role in the enhancement of f MAX for B4T technology, and determinate if exist undesirables effects due to the reduction of dimensions. The use of 3D surface plots permits a better observation of the impact of the different parameters on electrical characteristics.We carried out those experiments on a B4T+ device with W E = 90 nm. All design masks are updated, the spike annealing temperature and SIC dose are established at 1080°C and 4.10 13 at/cm 2 , respectively. The emitter is As-doped and the dose is kept constant at a value lower than 8.10 13 at/cm 2 . Each test was carried out keeping the other process parameters constants.

Table 4 .

 4

	3 List of the 1D key process parameters
	1D PARAMETERS	DESCRIPTION
	Silicon Cap thickness	Define s the emitter size
	Dose of boron
	implantation	Defines the B peak
	Ge percentage collector
	side	Defines the Ge profile
	Ge percentage in the
	middle	Define sthe Ge profile
	Ge percentage emitter
	side	Defines the Ge profile
	C percentage	Reduces the Boron diffusion
	Emitter doping	Defines the emitter profile

Table 4 .4

 4 List of the 2D key process parameters 4.5.1.1

Boron doping level and Carbon Content In

  order to analyze the behavior of the boron doping level on B4T technology several simulations are performed varying this parameter from 10 17 up to 10 20 at/cm 3 .

Table 4 .5

 4 Comparison of process parameters and frequency values for the technologies studied

							1800
		10 -2					1600
							1400
	I C ,I B (A)	10 -6 10 -4					600 800 1000 1200	Current Gain
		10 -8				Ic	400
						Ib	200
		0.5 -10 10	0.6	0.7	0.8	0.9 Gain	1 0
				V BE (V)

MicroscopicModels

Figure 3.20 SIMS profiles compared with the simulated data of arsenic, boron, germanium and carbon of B3T technology.

le rôle le plus important dans l'amélioration de f MAX , et un jeu de valeurs a été dégager pour atteindre de très grandes valeurs pour f MAX sans nuire aux autres caractéristiques électriques du dispositif.Parmi l'ensemble des paramètres étudiés, l'étude s'est focalisée sur l'influence du niveau de dopage en bore dans la base, du taux de carbone et de germanium sur les caractéristiques électriques du TBH. Ces trois paramètres sont très importants pour l'amélioration des performances du transistor, ainsi que les limites que l'on peut leur donner sans que cela entraine des dégradations importantes du comportement électrique. Ainsi, concernant le pourcentage de carbone sur l'obtention de bonnes performances pour le transistor, on peut conclure qu'il doit rester inférieur à 1%, avec un optimum d'environ 0,5% pour les valeurs maximales possibles de f T et f MAX .En finissant par le développement d'une architecture de TBH désignée B5T, l'étude a montré comment obtenir une valeur de f MAX supérieure à 500 GHz, remplissant les objectifs du contrat porteur financier de la thèse.

Acknowledgments

This research work is the result of a collaborative effort between the Institut d'Électronique Fondamentale at the Université Paris-Sud and STMicroelectronics in the framework of the DotFive project, supported by the European Commission through the Seventh Framework Program for Research and Technological Development. I would like to express my deepest appreciation and sincere gratitude to Pr. Frederic Aniel, Les modèles physiques utilisés ont été amélioré, permettant une meilleure description du transport de charge dans la structure. Pour l'environnement de simulation TCAD, il a été mis en place les modèles physiques adaptées aux alliages SiGeC contraints sur Si. Nous avons proposé de nouveaux modèles analytiques pour la densité effective d'états pour la base SiGeC. Nous avons montré l'influence des modèles, en particulier ceux liés à la réduction de bande interdite en fonction du dopage, qui peuvent conduire à de mauvais résultats s'ils sont mal utilisés. Dans cette étude, différentes architectures de TBH avancés ont été proposées pour objectif d'accroitre les performances en fréquence. Par exemple, une architecture haute performance faible coût a été étudiée profitant de la réduction de la capacité collecteur-base (CB). Avec une augmentation de l'épaisseur de l'oxyde collecteur-base de 50 à 150 nm, la capacité CB est réduite de 40%. Le développement et de la validation des différents scripts de l'environnement de simulation étaient au coeur du travail à accomplir. Nous avons élaboré des kits de simulation pour les technologies avancés de TBH, pour permettre de simuler les caractéristiques statiques et dynamiques et d'extraire les figures de mérite et les paramètres usuels du transistor. Les techniques d'extraction de f MAX et de f T ont été exposé, techniques sur lesquelles ont été élaboré les scripts en langage TCL pour l'environnement de simulation. Ces simulations sont les premières qui prennent en compte l'impact de la contrainte liée au taux de germanium et au taux de carbone dans la base, non seulement pour la simulation des procédés de fabrication, mais aussi pour la simulation électrique. Tous les résultats de simulation ont été validés avec des mesures expérimentales.

Chaque étape du procédé de fabrication est simulé conduisant à une prédiction précise de la distribution des dopants actifs, de la distribution de la contrainte et de la géométrie du dispositif.

Les modèles de diffusion utilisés pour la distribution des dopants dans les alliages SiGeC ont été expliqués, montrant l'importance du carbone pour réduire leur diffusion. Sur la base de travaux antérieurs, un important travail de synthèse a été accompli pour les modèles adaptés aux alliages SiGeC contraints, et leur mise en oeuvre pour le simulateur de type hydrodynamique. Cela concerne la bande interdite, les masses effectives de densité d'état, les mobilités et les temps de relaxation en énergie des porteurs.

Dans cette thèse nous avons étudié les principaux paramètres des procédés de fabrication et leur impact sur les performances du TBH. Nous avons identifié les paramètres qui jouent

Masses effectives d'électrons et de trous

Le modèle du temps de relaxation de l'énergie

Le temps de relaxation de l'énergie des porteurs est le temps moyen requis pour qu'une population de porteurs excités revienne à l'équilibre. Ce temps de relaxation caractérise la