Tobias Habermann

Jonas Kühle

Martin Kumm
email: martin.kumm@cs.hs-fulda.de

Anastasia Volkova
email: anastasia.volkova@univ-nantes.fr

Hardware-Aware Quantization for Multiplierless Neural Network Controllers

Keywords: neural network controllers, machine learning, hardware-aware quantization, quantization-aware training

Deep neural networks (DNNs) have been successfully applied to the approximation of non-linear control systems. These DNNs, deployed in safety-critical embedded systems, are relatively small but require a high throughput. Our goal is to perform a coefficient quantization to reduce the arithmetic complexity while maintaining an inference with high numerical accuracy. The key idea is to target multiplierless parallel architectures, where constant multiplications are replaced by bit-shifts and additions. We propose an adder-aware training that finds the quantized fixed-point coefficients minimizing the number of adders and thus improving the area, latency and power. With this approach, we demonstrate that an automatic cruise control floating-point DNN can be retrained to have only power-of-two coefficients, while maintaining a similar mean squared error (MSE) and formally satisfying a safety check. We provide a pushbutton training and implementation framework, automatically generating the VHDL code.

I. INTRODUCTION

Deep Neural Networks (DNNs) are now applied in practically every domain of human activity. Their size varies depending on applications, from small models having several hundreds or thousands of parameters for regression tasks and control, up to huge compositions of models with billions of parameters for natural language processing. While energyefficiency and acceleration is of interest for any DNN, in this paper we will focus on inference for small feed-forward neural networks with applications in control. Indeed, Neural Network Controllers (NNCs) are typically implemented with just a few hidden layers and their goal is to serve as a cheaper, faster and more robust substitute to classic numerical control algorithms [START_REF] Julian | Policy compression for aircraft collision avoidance systems[END_REF]- [START_REF] Wu | Squeezedet: Unified, small, low power fully convolutional neural networks for realtime object detection for autonomous driving[END_REF]. A typical approach is to use High Level Synthesis (HLS) to generate Field-Programmable Gate Array (FPGA) implementations, which do not necessarily take advantage of the structured nature of DNNs or satisfy the high-throughput and low-power needs of embedded controllers in safety-critical applications. With this work, our goal is to remedy for that and propose a new push-button tool for an automatic generation of FPGA-based inference circuits for small but efficient and fast DNNs.

The most costly operations in the realization of feed-forward DNN are the multiplications. In this work we leverage the fact that DNN weights are constants, known a priori, hence generic multiplications can be replaced by additions, subtractions and bit-shifts. These multiplierless implementations yield smaller, faster and less power-hungry implementations. However, simply deducing a multiplierless implementation upon straightforwardly-quantized weights/biases is not satisfactory: constants that are close to each other, in absolute value, can have a significantly different hardware implementation cost. Take for example, integers 31 and 32: multiplying by 31 costs one addition (31x = 2 5 x -x) while multiplication by 32 is a simple bit-shift (32x = 2 5 x), which can be hardwired at negligible cost. As a consequence, in [START_REF] Gustafsson | Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication[END_REF] It has now become a common approach to re-train the floating-point (FP) DNNs after a quantization to low word length fixed-point (FxP) representation, in order to improve the network's accuracy [START_REF] Gholami | A survey of quantization methods for efficient neural network inference[END_REF]. During a typical re-training, the weights and biases are kept in the chosen, and often uniform, low word length and can take any value, which is not necessarily hardware-friendly. In the previous work [START_REF] Faraone | AddNet: Deep neural networks using FPGAoptimized multipliers[END_REF], a quantizationaware training was proposed, in which FP neural networks are retrained for FxP coefficients that are selected from a restricted set of numbers that are well-suited for reconfigurable multipliers.

Building up on this idea, we propose a novel hardwareoriented training scheme, in which FxP weights and biases are selected from the sets of hardware-friendly numbers wellsuited for multiplierless implementations with very few adders per quantity. This adder-aware strategy yields significantly faster architectures, as the computations are done fully in parallel.

II. NEURAL NETWORK CONTROLLERS

The application of DNNs to control systems is an emerging domain showing excellent results. Neural networks have demonstrated two main advantages over classic methods: speed and robustness. As shown in case of autonomous driving [START_REF] Bojarski | End to end learning for self-driving cars[END_REF], [START_REF] Chen | Deepdriving: Learning affordance for direct perception in autonomous driving[END_REF], NNCs can learn how to optimize all decision steps simultaneously, instead of multi-step linking of a classic object detection and control algorithms. Most importantly, NNCs often allow to compress the numerical schemes classically used for control. For instance, in case of aircraft collision avoidance systems, [START_REF] Julian | Policy compression for aircraft collision avoidance systems[END_REF] showed that teaching a small DNN to approximate the result of a Markov decision processing reduces the memory footprint for the implemented system by -Fig. 1: Shift-and-add based MCM circuit for multiplication with constants 19 and 43 a factor of 1000, compared to classic approaches, and even surpasses the original in robustness.

One crucial property of the NNCs is the inference speed, as these control tasks would be implemented in real-time embedded systems. For instance, [START_REF] Wu | Squeezedet: Unified, small, low power fully convolutional neural networks for realtime object detection for autonomous driving[END_REF] focuses on providing small DNN models for fast object-detection, reducing the typical size of DNNs to several, up to 10, dense/convolutional layers with ReLU or tanh activation functions.

Although utilizing DNNs in safety-critical applications can demonstrate considerable performance benefits, assuring the safety and robustness of these systems is indispensable. Moreover, it has been demonstrated that their behavior can be unpredictable due to adversarial perturbations in their inputs. Hence, a formal set-based verification tool, such as Neural Network Verification (NNV) [START_REF] Tran | Nnv: The neural network verification tool for deep neural networks and learning-enabled cyber-physical systems[END_REF], should be employed to guarantee the safety of the implemented neural controller.

III. MULTIPLE CONSTANT MULTIPLICATION

One efficient way for realizing MCM circuits is to transform the required multiplications into several additions, subtractions and bit-shifts (shift-and-add, for short). Fig. 1 shows an example of an MCM operation with the two constants 19 and 43. Arrows denote bit-shifts, and each adder can be assigned to a constant factor. For example, the first adder computes 5x by adding x to x bit-shifted by two, leading to x + 2 2 x = 5x. Similar, 19x is computed as 2 2 (5x) -x = 19x. Instead of two multipliers, this MCM implementation only requires the hardware equivalent of three adders.

Determining the circuit with the least amount of adders for a given set of constants is known as the MCM problem. Several heuristics [START_REF] Dempster | Constant Integer Multiplication Using Minimum Adders[END_REF]- [START_REF] Kumm | Pipelined Adder Graph Optimization for High Speed Multiple Constant Multiplication[END_REF] and optimal approaches [START_REF] Aksoy | Search Algorithms for the Multiple Constant Multiplications Problem: Exact and Approximate[END_REF]- [START_REF] Garcia | Truncated Multiple Constant Multiplication with Minimal Number of Full Adders[END_REF] have been presented to solve it.

To reduce the hardware complexity of our NN controller, we can simply apply these algorithms to the quantized weights of our NN controller. However, the complexity (in terms of adder count) strongly depends on the coefficient value. For example, the multiplication with the factor 43 is known to require three adders. The multiplication with 42 (or 44) would require only two adders. Quantizing a real number to those cheaper numbers was previously proposed as addition-aware quantization [START_REF] Gustafsson | Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication[END_REF].

We go one step further and make use of the robustness of the neural network: we quantize the weights of the NN controller to a set of cost-n numbers, for which the adder count does not exceed n adders. However, such quantization induces potentially large errors, perturbing the algorithm's output. We remedy for that by re-training the system with a new process called adder-aware training (AAT).

IV. ADDER-AWARE TRAINING

The quantization of DNNs is an active research area, where various different techniques were explored in recent years [START_REF] Gholami | A survey of quantization methods for efficient neural network inference[END_REF]. The subject can be split into two main streams. First, the post training quantization (PTQ) where the trained FP DNN is quantized to FxP formats. And second, the quantization-aware training (QAT) where the FP DNN is quantized and then is retrained. In most cases, PTQ is faster and its advantage is that it does not require a training dataset, which is often unavailable. However, the results are not as good as with QAT methods.

In this work, our goal is to leverage the power of MCM and implement hardware inference using the optimized multiplierless circuits. Based on the general observation of the exceptional robustness of DNNs w.r.t. quantization, we postulate that weights and biases can be quantized to very simple low-precision numbers, that can be implemented with only a few adders. By fixing the hardware cost of each weight to be 0, 1 or 2 adders, we restrict the set of possible values that can be taken and, hence, the QAT should be adapted accordingly. We integrated our work in the open-source Modular Quantization Aware Training (MQUAT) framework, which is based on the ideas proposed in [START_REF] Faraone | AddNet: Deep neural networks using FPGAoptimized multipliers[END_REF]. It provides a framework for QAT on limited sets of possible numbers for weights and biases.

The general proposed training flow is roughly illustrated in Fig. 2. Our framework takes the following information as inputs: the FP32 DNN model, the training and validation sets, the hyperparameters, e.g., learning rate and number of epochs, and the description of the hardware-cost restriction for all weights, layer-or channel-wise. The pre-trained FP32 DNN is re-trained by first finding a proper integer and fractional bit distribution for each unit to quantize. Then, the training process is started, where all weight updates are applied to the full precision weights but calculated based on the quantized DNN. After each backward pass, where weights and biases are updated in FP32, the DNN's coefficients are quantized. When the quantization function Q is a simple rounding, this process is a classic QAT. In the proposed AAT, we transform this function into a more complex algorithm, in which FP32 weights are rounded to the closest numbers that are realizable with the restricted adder cost.

First, we set up two types of quantization: a channel-wise quantization, in which each channel in a layer has its own FxP format, and a layer-wise quantization, in which all channels in the layer share the same format and, in consequence, the same shift-and-add graph. Channel-wise quantization allows tailoring the quantized channels better to the original ones and utilizes the whole potential of a much faster fully-parallel implementation of the DNN. Layer-wise quantization is interesting for resource-saving strategy but is typically slower, since it requires a sequential sharing of adders.

Due to the highly discrete nature of the target sets, from, which each coefficient value is selected, the convergence of the adder-aware training is not guaranteed. As the numerical experiments shall demonstrate, when the training reaches the user-given number of re-training epochs, the mean squared error (MSE) loss of the quantized DNN can be too high. In this case, a higher hardware cost, which increases the size of the coefficient set K, should be considered.

The quantization function Q(v) itself becomes a selection procedure, in which for each FP constant v, we search for an element k in the coefficient set K such that min k∈K |k -v|. It might happen, that the coefficient set K has to be shifted to provide a lower quantization error.

There are several coefficient sets K ∈ K possible that are constructed according to the target adder-cost and the target word length: The cost-0 set contains coefficients that are all powers of two, i.e., implementable uniquely with bit-shifts. For example, for 5-bit representation K 5 0 = {-32, -16, . . . , 0, . . . , 16, 32}. Formally, the set of all sets for cost-0 l-bit numbers K l 0 always contains just one coefficient set and is defined as

K l 0 = {±(2 n ) : ∀n = 0 . . . l} ∪ {0} K l 0 = {K l 0 } .
The cost-1 sets for l-bit collects all coefficient sets obtained through a sum of two cost-0 l-bit coefficients. Similarly, the cost-2 set of all sets for l-bit representation collects all coefficient sets that can be represented through a shifted sum of two individual sums of two cost-1 l-bit coefficients. We define the set of sets K l 1 and K l 2 with the help of the set of base combinations sets B l 1 , B l 2 and a clipping function clip l (x) = min(2 l , max(-(2 l ), x)) in the following way:

B l 1 = {{1, k a + k b } : ∀K ∈ K l 0 , ∀k a , k b ∈ K} B l 2 = {{1, k a + k b } : ∀K 1 ∈ K l 1 ,∀K 0 ∈ K l 0 ,∀k a ∈ K 0 ,∀k b ∈ K 1 } ∪ {{1, k a + k b , k c + k d } : ∀K ∈ K l 0 , ∀k a , k b , k c , k d ∈ K} K l 1 = {{±clip l (b • 2 n ) : ∀n = 0..l, ∀b ∈ B} : ∀B ∈ B l 1 } K l 2 = {{±clip l (b • 2 n ) : ∀n = 0..l, ∀b ∈ B} : ∀B ∈ B l 2 }
In the quantization function Q we encode the search for the best fitting set K ∈ K l n , for the target FP value v according to the absolute error between the value v and the candidate set. For a channel-wise quantization, each channel per layer has its own cost-n set. For the layer-wise quantization, a target set K is shared between each layer. The target set is selected based on the sum of absolute differences between the coefficients and the elements of the candidate set.

V. EXPERIMENTAL EVALUATION

A. Hardware Architecture Generator

We have integrated our VHDL code generator for the proposed multiplierless fully-parallel feed-forward DNNs in the open-source core generator framework FloPoCo1 [START_REF] De Dinechin | Designing custom arithmetic data paths with flopoco[END_REF]. Given a tensor-flow model in Python and the quantized coefficients, it generates the hardware architecture. Each channel is computed by first using a multiplierless approach for partial products, and then by adding all signals in a compressor tree. For partial products of a negative weight, the product with the positive weight is computed in a multiplierless way and the result is subtracted in the compressor tree. All the data paths are automatically truncated and resized to an internal FxP format. We leave the complex task of error-analysis and impact of the truncations upon the accuracy of the neural network out of scope of this paper. Instead, we compute all the signals exactly, but truncate the outputs of the activation layers to a user-given value.

B. DNN-based Adaptive Cruise Control

We evaluate the proposed approach on an NNC that implements an adaptive cruise control (ACC) task. This example comes from the NNV toolbox demonstration [START_REF] Tran | Nnv: The neural network verification tool for deep neural networks and learning-enabled cyber-physical systems[END_REF] for safety verification of NNCs and has been used for the ARCH competition [START_REF] Lopez | Verification of closed-loop systems with neural network controllers[END_REF]. An ACC is a system used in cars to keep a save distance between itself (the ego car) and the leading car. The ACC is provided with the current velocities and positions of both cars and has to calculate the acceleration of the ego car to keep a pre-defined safe distance. The ideal solution for the control problem is computed via a differential equation, which actually provides the training and validation data for the DNN model that approximates the solution of the equation. We consider the ACC3 model from the ARCH competition, which is a simple feed-forward network with 3 hidden layers, each having 20 neurons with ReLU activation function, and one last additional layer having one linear neuron to match the output format. We evaluate the MSE on the validation data set provided by the differential equation during our adder-aware training. However, a small MSE does not necessarily mean that the controller is actually safe. Hence, in addition, we will also use the safety verification provided by the NNV toolbox to analyze the quantizations of the trained model.

C. Experimental results and discussion

The proposed adder-aware training was integrated into the open-source tool MQUAT, which is written in Python and based on Tensorflow. In all experiments we used the standard Adam optimizer in Tensorflow with a learning rate of 10 -6 , amsgrad=True with 35 training epochs using the standard MSE loss. The training and validation dataset each have 210k examples. The generated hardware implementations are synthesized using Vivado v2018.3 for the xczu19eg-ffvb1517-1 FPGA. The run times are reported for training on a machine with a GeForce RTX 2060 Super GPU with 8GB GDDR6 RAM, i7-4790 CPU and with 16 GB of system memory.

In our first experiment, our goal is to compare the PTQ and the QAT approaches for the chosen ACC3 DNN. Fig. 3 illustrates the MSE of the PTQ (in blue) and the QAT (in yellow) of the reference FP32 network to different FxP word lengths (from 3 to 16). The red borders indicate quantized instances that are proven unsafe by the NNV, and bars marked with an arrow have an MSE >0.5, making the networks unexploitable. It is easy to see that retraining the network after the quantization is extremely important, not only permitting to maintain the MSE for low-precision coefficients but even improving it. The PTQ yields a comparable MSE and a safe controller with 14 bits word length. However, if we apply the quantization-aware training and lower gradually the word length, we can go as low as 8 bits, which we take as a baseline for comparison with our approach.

To obtain a state-of-the-art multiplierless reference, we applied the MCM algorithm RPAG [START_REF] Kumm | Pipelined Adder Graph Optimization for High Speed Multiple Constant Multiplication[END_REF] to the baseline 8 bit model. The upper part of Table I illustrates that 165 adders are required in total to implement the baseline controller, which is high but expected, as the weights and biases were not specifically designed for a multiplierless hardware. Simply rounding the coefficients to the closest cost-0, cost-1, etc. numbers (using [START_REF] Gustafsson | Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication[END_REF]) yielded unsafe controllers with an MSE larger than 1, confirming our intuition that re-training for adder-aware weights and biases is crucial. Fig. 4 illustrates the results when applying the proposed adder-aware training for the cost-0, cost-1 and cost-2 coefficient sets. AAT was applied either per channel (p. c.) or per layer (p. l.). The red boxes indicate low-precision instances that, regardless of a very low MSE, are certified unsafe by the NNV tool. Our first observation is that for a word length of just 5 bits our tool finds coefficients of a safe cost-0 controller with an MSE lower than the reference FP32 DNN. This MSE improvement is probably due to a smaller over-fitting in the low-precision DNN. Interestingly, we observed in all our experiments that even if a lower-cost implementation is of a good quality, a higher-cost result is not necessarily as good. For instance, for 5 bit coefficients, only the cost-0 channel-wise and cost-2 layer-wise results are stable, and for word length 6 bits, the MSE for cost-0 is lower than for cost-2 channel-wise. These effects could be explained by the non-deterministic nature of the stochastic gradient descent algorithm used for training, and that falling into local minima is highly probable in ultra low precisions over restricted coefficient sets.

Surprisingly, the larger word sizes (like 12 and 16 bits in Fig. 4) perform worse than the lower precisions (like 9, 6 or 5 bits). The reason for this could be that the chosen pre-trained QAT DNNs for AAT also had a bigger word length leading to a worse fit of the coefficient distribution.

Our conclusion is that a thorough design-space exploration is needed to find the lowest coefficient word length that provides a safe implementation at the lowest adder cost. This is without a doubt possible using the proposed tool, since the running times are reasonable for a one-time analysis. Table II illustrates the running times for layer-wise and channel-wise PTQ and QAT approaches applied on the ACC3 DNN for quantizations of 4, 8 and 16 bits. The classical FP32 to FxP is used as the baseline and shows that the timings are comparable to those of the proposed approach. We can note, that our performance is stable across the word lengths and varying from roughly 4 to 6 minutes for cost-0 coefficients up to 18 minutes for cost-2 coefficients.

In the following, we aim at comparing the resource benefits for different target cost settings, and therefore permit ourselves Multiplications are the resource dominating part of an NNC but not the only part. Hence, we performed synthesis experiments for variants of full NNC implementations. Table III collects the synthesis results for the baseline 8 bit network, implemented in two flavors (generic multipliers with and without DSPs, and directly applying the shift-and-add approach [START_REF] Kumm | Pipelined Adder Graph Optimization for High Speed Multiple Constant Multiplication[END_REF] upon coefficients), as well as our multiplierless architectures.

We can observe that the cost-0 architecture divides the number of LUTs by 2.73 compared to the baseline implemented with generic multipliers (without using DSPs) and by 2.59 compared to the state-of-the-art shift-and-add baseline. The reduced complexity also translates to reduced delays: the cost-0 solution is 1.91 and 1.22 times faster than the generic and multiplierless baselines, respectively. As the adder cost predicted, we do not observe a large resource increase going to cost-1 and cost-2 instances. The MSE of our implementation (last column of Table III) was evaluated from the VHDL simulation and is shown to be even less than the FP reference.

VI. CONCLUSION

We proposed a novel technique for an adder-aware training of small feed-forward DNNs aiming fast parallel inference on FPGAs. Our key idea is that DNNs can be successfully retrained for low-precision coefficients well-suited for a multiplierless implementation with a given target cost. We demonstrated effectiveness of our approach on an NNC implementing automatic cruise control, for which the resource requirements could be divided by 2.59 w.r.t. a state-of-the-art multiplierless hardware implementation obtained with quantization-aware training. Future work includes a thorough analysis of errors due to roundings and incorporation of intermediate truncations, extension to convolutional neural networks and sequential implementations using layer-wise results.

Fig. 2 :

 2 Fig. 2: The proposed training flow. Function Q is a quantization strategy algorithm.

Fig. 3 :

 3 Fig. 3: MSE results for the ACC3 with PTQ and QAT for different FxP word lengths. All results with an MSE higher than 0.5 are marked with an arrow. All unsafe controllers have a red border.

Fig. 4 :

 4 Fig. 4: MSE results for the adder-aware training of the ACC3 controller for different FxP word lengths and target channelor layer-wise costs. All results with a higher MSE than 0.5 are marked with an arrow. Unsafe controllers are marked red.

  Gustafsson et al. proposed an Addition Aware Quantization approach, in which floating-point numbers are quantized s.t. their multiplierless implementation cost is small.

TABLE I :

 I MCM cost for the baseline and proposed approaches

	Experiments		#adders per layer 1 2 3 4	total #adders
	8 bit baseline		59 46 58 2	165
		cost-0 / channel	0	0	0	0	0
	5 bit proposed	cost-1 / channel 14 10 12 1 cost-2 / channel 15 14 14 1	37 44
		cost-1 / layer	1	1	1	1	4
		cost-2 / layer	2	2	2	1	7

TABLE II :

 II Quantization time in seconds for classic FP32 to FxP quantization, for the ACC3 DNN.

	Proposed adder-aware training	Baseline
	layer-wise		channel-wise	channel-wise
	K l 1	K l 2	K l 0	K l 1	K l 2	PTQ	QAT
	4 bit 387 564 356 355 1133 1312 2546
	8 bit 387 567 358 370 1116 52	1265
	16 bit 391 578 361 373 1139 51	1265

TABLE III :

 III Synthesis results for the baseline and proposed parallel architectures ignore the unsafety of certain 5 bit instances. Before doing any synthesis, we can observe in the lower part of TableIthe adder cost of the proposed 5 bit instances. The possibility to re-train the network for the cost-0 coefficients, obviously, significantly simplifies the architecture. Training for the cost-1 coefficients still divides the number of used adders by more than 4 w.r.t. the 8 bit QAT baseline. One can also note, that using the cost-2 coefficients does not necessarily lead to doubling the total number of adders, as some channels will still have lower adder cost. Finally, training for the safe cost-1 and cost-2 controllers layer-wise, even if demonstrated possible and pertinent w.r.t. cost, results in a non-parallel architecture, hardware implementation of which we leave to future work.

	Design	Experiment	#LUT #DSP delay (ns)	MSE
	baseline (8 bit)	generic mult generic no DSP shift-and-add [12]	44328 69058 42128	388 0 0	12.489ns 11.842ns 7.952ns	0.0272 0.0272 0.0272
	proposed (5 bit)	cost-0/channel cost-1/channel cost-2/channel	16236 18726 19546	0 0 0	6.532ns 6.954ns 7.657ns	0.0831 0.0425 0.0324

to

available online at http://flopoco.org


Guillaume Pellecuer
email: guillaume.pellecuer@umontpellier.fr

Jean-Jacques Huselstein

Thierry Martiré

Franç Ois Forest

André Chrysochoos

Mourad Jebli

IGBT Wirebonds Ageing: A New Test Bench Development for Dedicated Modules Assemblies

Keywords: wirebonds ageing, power cycling, specific samples design, test benches development

Wirebonds ageing in power modules used in electric vehicles is a main concern for the development of reliable inverters. The development of a specific test bench to study the evolution of their properties over time has allowed conclusions to be drawn on the possibility of accelerating or not accelerating ageing tests without distorting the mechanisms actually involved in ageing. Through the use of specifically developed test bench in terms of electrical and thermal properties the studied wirebonds samples are more easily thermally controllable, equipped with measuring devices and the energy consumption at a given cycle is divided by ten compared to a classical bench. The entire process of designing and producing the specific samples and the associated test bench and a description of the first results obtained to demonstrate the relevance of the approach is given.

INTRODUCTION

The power semiconductor modules are key elements in the structure of a converter and their reliability has a strong influence on the reliability of the whole system. In the case of electric traction applications, the thermal environment or the power losses in the semiconductor chips lead to so-called passive or active thermal cycling. This phenomenon is one of the main causes of ageing and degradation of these components, especially in the upper connections called wirebonds [START_REF] Ciappa | Selected failure mechanisms of modern power modules[END_REF][START_REF] Ramminger | Crack mechanism in wire bonding joints[END_REF].

The chips used in this context are mainly integrated into power modules (Figure 1) to constitute elementary conversion functions. This assembly must be able to maintain electrical insulation of the active parts and ensure the mechanical support of the different elements of the structure. The result is a multi-layer stack of different materials that are sensitive to thermal cycling. The different layers have significant differences in terms of thermo-mechanical properties, leading to the development of large mechanical stress fields at the interfaces and especially at the upper connections, known as wirebonds. Under these conditions, the reliability of the modules is directly related to thermo-mechanical fatigue of wirebonds [START_REF] Pellecuer | Toward a multiphysical approach to connection ageing in power modules[END_REF][START_REF] Czerny | Thermo-mechanical analysis of bonding wires in IGBT modules under operating conditions[END_REF].

Figure 1. Power module with wirebond view

To study the ageing of connections in power modules, test benches were used. IES-GEM (Institut d'Electonique et des Systè mes -Groupe Energie et Materiaux) has developed a PWM test bench that can actively cycle (Figure 2) the component [START_REF] Smet | Aging and failure modes of IGBT power modules undergoing power cycling in high temperature environments[END_REF][START_REF] Forest | Use of opposition method in the test of highpower electronic converters[END_REF][START_REF] Forest | Fast power cycling protocols implemented in an automated test bench dedicated to IGBT module ageing[END_REF]. It allows ageing tests to be carried out on modules by applying electro-thermal stresses like those experienced by these components in real operation and the structure of the converter is a single-phase PWM (Pulse Width Modulation) inverter with two arms operating in opposition. This converter structure has the advantage of being able to apply realistic operating conditions while drawing only the losses of the active components (IGBT (Insulate Gate Bipolar Transistor), diodes) on the power supply [START_REF] Forest | Use of opposition method in the test of highpower electronic converters[END_REF][START_REF] Vallon | Introduction à l'étude de la fiabilité des cellules de commutation à IGBT sous fortes contraintes[END_REF]. Each test bench allows two generic modules (two IGBTs and two diodes) to be tested.

Figure 2. Thermal cycles of IGBT chip

The use of PWM test benches has many advantages, such as ageing under realistic conditions. However, the implementation of PWM test benches is tedious, time consuming, energy consuming and it is very difficult to perform on-line measurements like 𝑉 𝐶𝐸 monitoring for example [START_REF] Smet | Evaluation of vce monitoring as a real-time method to estimate aging of bond wire-IGBT modules stressed by power cycling[END_REF]. Moreover, as the objective is to focus on the top part of the chip with its connections, the use of commercial power modules as a test sample is not the simplest solution. The entire assembly must be stressed in order to observe only a small part of it, and the large number of bondings on each chip does not allow the behaviour of a single wire to be correctly characterized.

The idea developed here is therefore to create test samples dedicated to the study of connections, with low power consumption and with the possibility of carrying out on-line measurements characterizing the state of damage of the fastener. The ageing of the bonding wires associated with such samples will have to be similar to that caused by conventional tests, consequently the stresses applied to the wires and their attachments will have to be maintained. Some twenty samples were manufactured and tested to validate the approach from design to production of such samples and the operation of the ageing benches.

DESIGN AND PRODUCTION OF SAMPLES

Using a IMS

The basic principle of our approach has consisted in using a thermally "bad" substrate in order to generate thermal cycling much more easily. For this purpose, we have chosen an IMS (Insulated Metal Substrate) with an epoxy insulating layer, on which MOSFET (Metal Oxide Semiconductor Field Effect Transistor) chips were soldered and used as heat sources in linear mode. The Drain-Source voltage is imposed by the power supply and a current control allows to generate a power cycling. In addition the device was placed on a heat sink with controlled air flow. This IMS presents a high thermal resistance between the lower and upper metallizations, allowing a considerable reduction in power consumption compared to the PWM bench, for a given thermal cycling of the chips (55W instead of 400W as in the previous PWM test bench [START_REF] Forest | A Power Cycling Test Bench Dedicated to the Test of Power Modules in a Large Range of Cycling Frequency[END_REF], for a sample with four chips compared to one module, for 𝑇 𝑗 = 50C, 𝑇 𝑟 = 80℃ and 𝑓 = 1Hz) [START_REF] Gurpinar | Design, analysis and comparison of insulated metal substrates for high power wide-bandgap power modules[END_REF]. We have taken 1Hz as the cycling frequency to illustrate the operation of the bench as this is a frequency commonly encountered in the accelerated cycling of wirebonds in semi-conductor power modules.

IMS assembly: -1.5mm aluminium with 𝑘 = 238𝑊. 𝑚 -1 . 𝐾 -1 -100µm of FR4 epoxy insulation with 𝑘 = 0.55𝑊. 𝑚 -1 . 𝐾 -1 -35µm of copper with 𝑘 = 400𝑊. 𝑚 -1 . 𝐾 -1

Figure 3. 3D view of an IMS sample

Figure 3 shows a 3D view of a sample drawn with SOLIDWORKS ® . The test sample consists of four MOSFET chips each with three bonding wires:

-A 250µm power wirebond (source) through which the main current will flow. -A 250µm measuring wirebond (source), allowing a measurement of the electrical resistance of the main wire, but also to evaluate, if necessary, the ageing of a wire through which no current is flowing. -A 125µm gate wirebond for the control, the MOSFET chip being used here as a current generator.

A shunt, associated with each chip, allows the main current to be measured and regulated. Since the system operates in linear mode with a constant 𝑉 𝐷𝑆 voltage, the current regulation allows the losses in the chip to be perfectly controlled. Unlike the PWM test bench, in which the losses depend on the chip (conduction and switching) and therefore have a dispersion, the losses here are identical for all chips. Two temperature measurements are made using PT1000 type platinum probes on the top of the IMS. These two measurements are considered here as the 𝑇 𝑟𝑒𝑓 reference temperature for imposing thermal cycling. Two connectors are used to connect the drivers board to the power board, the regulation and measurement conditioning circuits are also located on the drivers board.

Electrothermal modelisation

The feasibility of this solution was verified by electrothermal finite element simulations on COMSOL Multiphysics ® software. The concept of enforcing a constant voltage and regulating the drain current of the MOSFET to control the heat source can be implemented in the circuit simulator included in the finite element software. A voltage condition is imposed (Potential and Ground) and a time-varying chip electrical conductivity is calculated to obtain the desired current. Figure 4 shows an example of a simulation with four alternating currents in the chips and the resulting thermal profiles, for a cycling frequency of 1Hz.

As the sample is intended to be mounted on a finned heat sink, a forced convection thermal condition is applied to the fins. Figure 5 shows an example of a simulated thermal mapping during alternate cycling of the four chips. Isthmuses in the conductive copper layer are visible around the chips and allow each MOSFET to be considered as thermally isolated because for low frequencies, it is necessary to limit the propagation of heat so that the cycling of one chip does not impact the cycling of its neighbours. There are two possible solutions to overcome this problem: to separate the chips by large spaces or to make these isthmuses. The latter solution has the advantage of increasing the number of chips per substrate. The isthmuses must considerably increase the thermal resistance between chips linked to the conductive layer while presenting a sufficiently low electrical resistance. Simulations have shown local current densities of 15A/mm 2 in the copper for the currents which is quite acceptable.

Figure 5. Heat map of the sample

These simulations also validated the feasibility of cycling at 0.1Hz, 1Hz and 5Hz with temperature profiles 𝑇 𝑗 = 50°C and 𝑇 𝑟 = 80°C, to reproduce test conditions similar to those applied to power modules (to allow the comparison). The chips are exposed to the same thermal profile, but a phase shift between them is deliberately introduced. This allows the currents to be balanced and thus limits the ripple of the current seen by the power supply.

Making samples

Figure 6. Substrat IMSchip zoom

Figure 6 shows the resulting substrate and a closer look at one of the chips. The components (shunts, PT1000, chips, copper pads and connectors) are soldered using a tin-lead solder. The bonding wire connections are the main focus of the study. It is therefore interesting to take a closer look at the transferring technique of these wires. This step is carried out using a "Heavy Wire Bonder HB30" machine, available within the 3DPHI platform (Figure 7).

Figure 7. Heavy wire bonder HB30

The procedure consists of positioning the wire with a tool onto the pad where it is to be welded. The combination of a force applied to the wire during plating and mechanical vibrations created by a transducer allows the welding to be performed. The applied force is adjustable, as well as the application time and the welding power (amplitude/frequency of the ultrasonic waves). The dissipated energy causes the wire to soften in a similar way to that obtained by raising the temperature. The wire is then guided to a second pad to make a new weld. A knife is used to cut the wire once the bond has been made [START_REF] Sedlmair | Which ultrasonic frequency is best for wire-bonding[END_REF][START_REF] Fischer | Unconventional applications of wire bonding create opportunities for microsystem integration[END_REF]. The wire diameter used for our samples is 250μm for power and measurement while a wirebond with a 125μm diameter is used for the grid wirebond.

Figure 8. Configuration of bonding placement

The transfer of bonding wires can be done with or without emitter repetition (two legs, or one leg, Figure 8). The study of these two configurations will make it possible to analyse the possible influence of the stresses developed in one bonding foot on the second foot and to evaluate the impact on ageing. The welding parameters are identical to those used by power module manufacturers. Power: 6W -Time: 150ms -Force: 450mN.

DEVELOPMENT OF A TEST BENCH DEDICATED TO SAMPLES

A test bench for electrothermal cycling of the samples has been developed, its synoptic diagram is given in Figure 9.

Figure 9. Schematic diagram of the test bench

The shaded area in Figure 9 is the test sample. The other blocks correspond to the driving and control functions implemented in the test bench. The control system is implemented in a STM32F4 microcontroller from STMicroelectronics ® which controls the current for the four channels using four PWMs. The LabVIEW ® supervision interface allows, via the microcontroller UART (Universal Asynchronous Receiver / Transmitter), the monitoring of current measurements, contact resistance measurements and temperatures for regulation. Moreover, the power parameters can also be adjusted via the control of the input current from the user. A temperature regulation based on the control of the air flow in the fins via a buck converter/fan assembly is implemented in the STM32F4. The STM32F4 also counts and saves the number of cycles on each channel. In addition, the LabVIEW ® interface also makes a backup. The supervisory interface also allows the voltage and current of the main power supply to be monitored via Ethernet communication and the information on the current drawn to be used to detect a shortcircuit fault and shut down the power supply. Contact resistance measurements, taken by the microcontroller, are stored in a file. A MATLAB ® "App designer" interface allows to read this file, to filter the measurements (sliding average) and to display the results as curves. This interface allows to follow the evolution of the contact resistance in real time.

The test bench is designed to allow the variation of many cycling parameters such as frequency 𝑓 , current amplitude 𝐼 𝑚𝑎𝑥 and 𝐼 0 , duty cycle 𝐷 𝑡 , supply voltage 𝑈 𝐸 and reference temperature of the cycle 𝑇 𝑟𝑒𝑓 .

Variation ranges:

-𝑓: 0 to 10Hz.

-𝑈 𝐸 : 0 to 60V.

-𝐼 𝑚𝑎𝑥 and 𝐼 0 :from 0 to 5A.

-𝐷 𝑡 : from 0 to 50%.

-𝑇 𝑟𝑒𝑓 : between 50℃ and 100℃.

Figure 10. 3D Implementation of the test bench

Figure 10 shows an overview of the test bench designed using Solidworks ® . This includes the IMS board, which is described in detail in the previous section. The driver board, which contains the measurement and control circuits for the four sample channels is plugged into the driver board via two 10-pin connectors. A support PCB (controller board) houses the microcontroller board and provides the interface between the monitoring tool and the driver board. The buck converter used to control the variable speed fan is located on the latter board.

The cooling system consists of a fan, an air box and a finned heat sink to which the IMS board is attached. The air box also serves as a support for the controller board.

Finally, a protective casing is fitted to the IMS board to prevent damage of the bonding wires during the various steps of board assembly and disassembly.

Principle of power control and measurement

In order to impose the chip temperature variations via their losses, the choice was made to regulate the drain current with a constant 𝑉 𝐷𝑆 voltage (neglecting the shunt voltage). This regulation is analog (driver board), its schematic diagram is shown in Figure 11.

Figure 11. Schematic diagram of the current control

The current set point, generated by the microcontroller, is imposed by a high-frequency PWM signal whose duty cycle, which is an image of the set point, is variable in time. A lowpass filter is used to extract the low frequency component of the signal that has the desired current shape. The current measurement is carried out using a 0.2 shunt. A proportional integral PI (Propotionnal, Integral) controller is inserted into the loop and directly controls the MOSFET through a gate resistor (Figure 12).

Figure 12. Analog control of drain current

In Figure 12, control signal 1 is the PWM set point from the microcontroller board. Signal 2 is the filtered signal. To avoid using a symmetrical power supply, an offset is added to each operational amplifier. The 8V level appearing at the output of the filter is caused by this offset. It is then compensated by the offset of the PI controller. Signal 3 is the controlled current. The setting parameters are the frequency 𝑓, the low frequency duty cycle 𝐷 𝑡 , the amplitude 𝐼 𝑚𝑎𝑥 and the low value 𝐼 0 .

The driver board also contains the conditioning circuits for all the measurements. The data from these circuits is then sent to the microcontroller board via the analog/digital conversion inputs.

Eleven measurements are made on each sample: -The currents in each channel: 𝐼 1 , 𝐼 2 , 𝐼 3 , 𝐼 4 .

-The voltage drops across the wirebonds in each channel: 𝑈 1 , 𝑈 2 , 𝑈 3 , 𝑈 4 . -The two reference temperatures: 𝑇 𝑟𝑒𝑓1 , 𝑇 𝑟𝑒𝑓2 .

-The supply voltage: 𝑈 𝐸 . The controller board is the main element of the bench. It includes the various power supplies required for the operation of the test bench, the fan buck converter and supports the microcontroller board.

Air cooling system

To control the thermal profile of a chip, a power profile must be imposed, but also the "low" temperature of the profile called 𝑇 𝑟 (Figure 2). This ensures reproducible thermal behaviour. For this purpose, the 𝑇 𝑟𝑒𝑓 temperature, measured using two PT1000 platinum probes placed on the IMS board, is digitally controlled. For the considered cycling frequencies, the 𝑇 𝑟𝑒𝑓 and 𝑇 𝑟 temperatures are directly proportional to each other.

The system (Figure 13) consists of a heat sink with the sample screwed to it, a fan operating at variable speed for thermal regulation and an air box for airflow ducting. The measurements from the PT1000 are conditioned by a circuit on the driver board and an equation resulting from the polynomial interpolation of the sensor conditioning circuit response set in the supervisory interface, is used to obtain the temperature. The measurement of the reference temperature corresponds to the average of the two measurements made by the probes.

Figure 13. 3D view of the air cooling system

A buck converter allows the control of the fan. The adjustment of its speed allows the control of the temperature measured on the IMS board. The fan works in air extraction mode. As the heat flow to be extracted is low, holes are provided at the back of the box to increase the air flow drawn in by the fan and thus facilitate the control. The fan does not have a linear speed/voltage characteristic and below a voltage threshold, and therefore speed, the fan stops. In order to be able to impose speeds below this threshold, the duty cycle is set to its minimum value and an ON/OFF modulation is introduced, with a period less than the mechanical time constant of the fan motor. The pseudo duty cycle 𝑡 𝑂𝑁 /𝑡 𝑂𝐹𝐹 is controlled by the supervisory interface which sends the two orders (PWM and 𝑡 𝑂𝑁 / 𝑡 𝑂𝐹𝐹 ) to the microcontroller which generates the PWM.

Figure 14. Two modes of fan control

The two fan operation modes are shown in Figure 14. The control mode above the limit speed, is as shown in Figure 14 (a) and below the limit speed, the control mode is the one shown in Figure 14 (b). The transition between the two modes is linear. This means that once the minimum HF (high frequency) duty cycle is reached for normal operation, the LF (low frequency) duty cycle is gradually reduced to slow down the fan and to comply with the control commands. The frequency of the ON/OFF modulation is set to 2Hz, whereas the value of the switching frequency which is 100kHz. Therefore, the buck converter filter has no influence on the low frequency modulation.

The air box was produced by 3D printing (PRO3D ® additive manufacturing process technology platform of the University of Montpellier). The material used is ABS plastic which can withstand temperatures above 100°C. Under normal bench operating conditions, the maximum temperature to which the air box can be subjected is approximately 80°C. The protective casing was also manufactured by 3D printing.

Live contact resistance measurement

The objective being to have feedback on the ageing of the contact area, we chose to carry out a live electrical resistance measurement [START_REF] Tang | Reliability and on-line evaluation of IGBT modules under high temperature[END_REF]. The second bonding wire in Figure 15 was provided for this purpose. It is used to measure the voltage drop across the power bonding wire at a given current. The resistances thus measured include that of the wire, its attachment to the chip and an active part of the metallization between the two attachments. In the event that only the contact area degrades, the detected change in resistance would be the marker.

Figure 15. Schematic of contact resistance measurement

Figure 15 shows the wiring geometry chosen to make this measurement. The voltage drop across the bonding wire is small and difficult to measure with the currents flowing through the chips (1 to 2A). Indeed, the resistance of the wires is about 10mΩ, which leads to voltages of 10 to 20mV. Furthermore, the measurement must be reproducible, and the resistivity of aluminium is temperature dependent. The measurement cannot therefore be made during cycling and must be carried out during a sequence of measurements which interrupts the cycling.

During this measurement sequence, the voltage generated by the power source is lowered to the minimum possible (3V instead of 12V) and a current of 5A is imposed in each chip (leading to a voltage drop of about 50mV) for a very short time (20ms), in order to avoid a temperature rise of the chip. Considering the low energy dissipated during this measurement and the low thermal capacity of the chip-soldercopper assembly, the junction temperature 𝑇 𝑗 varies only slightly during the measurement and is equal to the regulated temperature 𝑇 𝑟𝑒𝑓 . The measurement is performed every three hundred cycles for each channel. The supervisory interface starts the measurement sequence by sending the corresponding voltage set point to the controllable power supply and informs the microcontroller, which in turn imposes a DC current in each channel to discharge the output capacitors of the power supply and then generates the current set points, channel by channel, to obtain the current of 5A for 20ms.

Acquisitions are made at 1kHz on the relevant analogue/digital conversion inputs and can store fifteen pairs of voltage drop and current value. The result is sent to the LabVIEW ® interface for resistance calculation (the fifteen values are averaged to have a reliable measurement) which is then stored in a text file for the cycling follow-up. After each measurement, the number of cycles is stored in the flash memory of the microcontroller to save the information in case of power failure. The measurement does not require extreme accuracy, but it must be able to detect a change in contact resistance at the plating-bonding interface. It is the relative change in resistance that is meaningful in relation to the progressive degradation of the wirebond.

Supervisory interfaces

The main supervision interface is implemented with LabVIEW ® software. It allows to impose and adjust the cycling parameters (for current and temperature control) and to visualise the currents in the chips as well as the temperature measured by the platinum probes or cycling information (number of cycles and resistance measurements). Figure 16 shows a view of the supervision window. * For the sake of visibility, only half of the supervisory interface is shown, allowing a single test bench to be controlled. The interface allows two benches to be controlled independently in the same way.

The supervisory interface controls two benches with a controlled voltage source for their power supply. In the middle of the control window are the source control parameters and short-circuit fault indicators. The microcontroller monitors the current of each channel for each bench, while the overall monitoring of the power supply current is done by the LabVIEW ® application. In the event of a problem, the power supply is automatically switched off. The current drawn by the two benches, as well as the voltage and power drawn by each bench are also displayed.

A second interface, for the real-time display of resistance measurements, was created using the MATLAB ® tool "Appdesigner" (Figure 17). The use of MATLAB ® signal processing tools allows for flexibility in the processing of data from resistance measurements.

It allows the variation of the wire resistance to be displayed for the four benches that have been manufactured. For the display, a sliding average is taken over the last one hundred measured values. The resistance value, thus obtained, is compared with the average of the first one hundred measurements. From this, the resistance change (in %) is calculated, and this is the value displayed on the graphs.

REALIZATION OF THE TEST PLATFORM

Four test benches with one IMS per bench were built to test four IMS samples corresponding to sixteen bonding wires. Several types of samples were made during four test campaigns, depending on the information gathered during the tests. Figure 18 shows an overview of the bond wire ageing platform.

Figure 18. Test platform for ageing of samples

The platform, which comprises four test benches, is operational and has made it possible to test some twenty IMS samples corresponding to eighty wirebonds, in three measurement campaigns, under cycling conditions that will be detailed in the following section. A thermal camera is also used at the beginning of each cycle to check the thermal profile.

Example of 1Hz power cycling protocol

The first objective is to verify the representativeness of the samples thus produced. To do this, we decided to carry out several ageing campaigns, with a cycling frequency of 1Hz and a chip temperature 𝑇 𝑗 varying between 80°C and 130°C.

The cycling parameters are selected as follows:

-𝑈 𝐸 = 12𝑉 -𝐷 𝑡 = 0.5 -𝐼 𝑚𝑎𝑥 = 1.8𝐴 -𝐼 0 = 0.5𝐴 All the results presented here were obtained with these thermal cycling parameters (Figure 19). Only the currents flowing in chips 1 and 3 are shown on the left-hand graph for visibility reasons. Using the infrared thermal camera, the electrical parameters to be applied to obtain the desired thermal profile were determined. These parameters are shown on the graph representing the currents. The calculation (Eq. ( 1)), with Figure 19 parameters, gives an average power consumption of 55.2W for one IMS (four chips), it is important to remember that the benches previously used [START_REF] Forest | A Power Cycling Test Bench Dedicated to the Test of Power Modules in a Large Range of Cycling Frequency[END_REF] consumed nearly 400W for the same work.

max 0 4 ( ( 1
) )

E t t P U D I D I =    + -  (1)

Figure 19. 1Hz cycling protocol

For the temperature measurement, each circle visible on the heat map in Figure 19 defines an integration area on the chip. The result is the average of all the temperatures measured on each pixel present in the circle. The few thermal imbalances observed on the graphs are probably due, on the one hand, to the uncertainty of the observation areas used for the measurements and, on the other hand, to differences in the quality of the welds.

Not all modules can be observed with a thermal infrared camera and we considered this thermal profile to be reproducible at fixed electrical test conditions.

Test results for 1Hz power cycling protocol

The 1Hz cycling protocol was applied to about twenty IMS samples, i.e. about eighty chip-bonding pairs were tested. The objective was to validate the proper working of the test benches and to analyse the relevance of an electrical measurement to characterise mechanical damage. For these different samples, many parameters were analysed such as the effect of an emitter repetition or the impact of the silicone gel... A comparison was made between welds made by a manual machine and an automatic machine. Indeed, some samples were soldered by the MICROCHIP ® company (ex MICROSEMI ® ), which has a perfect knowledge of power module soldering techniques. Figure 20 shows examples of the obtained results.

𝑅 𝑏 is the resistance value after 𝑁 𝑓 cycle and 𝑅 𝑏0 the resistance value at the beginning of life. The curves represent the contact resistance measurement show a progressive increase in resistance. This increase becomes very significant at the end of the life cycle where a thermal runaway occurs due to poor current distribution in the connection, thus creating local heat sources that accelerate the destruction of the connection. These graphs show some trends in the fatigue of power modules by showing a clear dependence of the variation of the electrical resistance of the wire on the damage. Lemaitre and Chaboche defined a damage D relative to the current variation [START_REF] Lemaitre | Mechanics of Solid Materials[END_REF] (Eq. ( 2)).

𝑆 𝐷 is the damaged area, 𝑆 the total area, 𝑅 the resistance, 𝜌 the electrical resistivity, L and S are the length and the area of the contact. Finally, the damage can be written as:

0 bb b RR D R - = (4)
The evolution of resistance (𝑅 𝑏 -𝑅 𝑏0 )/ 𝑅 𝑏 , shows a trend that would confirm this equation justifying the relevance of this type of measure. Each sample was analysed by SEM (scanning electron microscopy) to assess the failure modes. Two failure modes were observed, namely metallization degradation and bond wire lift off. Figure 21 shows the top of a chip before and after ageing.

Figure 21. SEM failure analysis of wirebonds

These tests are encouraging, but the results obtained on the bonding wires of these samples are far from those observed on industrial modules with longer lifetimes. The use of MOSFET chips with a much larger semiconductor chip and solder thickness than an IGBT module partly explains this difference [START_REF] Surendar | Effect of solder layer thickness on thermo-mechanical reliability of a power electronic system[END_REF]. The objective of this study is therefore to set up test benches capable of highlighting the thermomechanical mechanisms responsible for the ageing of wirebonds. From this point of view, the test bench described here perfectly meets the expectations in terms of facilitating the management of thermal cycles and the ability to perform measurements in real-time.

The results obtained with this tool perfectly reflect the thermomechanical mechanisms responsible for the ageing of the connections. Indeed, the resistance variation remains during a large number of cycles during the implementation of the visco plasticity cycle characteristic of these connections. Thermomechanical modelling work shows significant viscoplastic deformations of the bond wires from the beginning of the loading, trending towards a stabilised cycle. This small but real increase in plastic deformation during each cycle suggests damage to these connections. This progressive damage finally creates a thermal runaway due to the distribution of the current density in the bonding foot zone which progressively reduces with increasing damage. This thermal runaway, which accelerates the lift-off of the wires can be seen very clearly on the curves in Figure 20 [START_REF] Pellecuer | Toward a multiphysical approach to connection ageing in power modules[END_REF][START_REF] Pellecuer | Fatigue thermomé canique des connexions dans les modules de puissance à semiconducteurs[END_REF].

There are several positive aspects to note, such as the possibility of producing specific samples with limited resources, the minimization of power consumption or the possibility to precisely control the test conditions. In addition, many benches can be run in parallel, allowing tests to be carried out over a period of weeks and a large amount of data to be collected. The implementation of the measurement monitoring (in this case, contact resistances) is relatively easy and can take a number of different forms, as specific samples can be designed at wish. Although they do not fully meet our expectations compared to data collected with industrial modules, these tests indicate a good reproducibility of applied thermal stresses and ageing modes, both in nature and in time evolution.

CONCLUSION

We have proposed the creation of specific test samples as well as all the necessary steps for their realisation and the creation of the associated test bench. We have chosen to measure the resistance of the bonding in order to evaluate in real time the evolution of the damage of the connection. The first results suggest that such a measurement is a good option for analysing bonding wires fatigue. However, these samples are only of interest if they can accurately represent, from the viewpoint of ageing, the bonding technology found on commercial modules. The curves, obtained over a campaign of twenty IMS samples, have enriched a study on the modelling of the thermomechanical mechanisms responsible for the ageing of wirebonds and show the interest of the approach presented in terms of ease of control of the cycling parameters as well as the robustness of the real-time measurements of the mechanical damage state. These curves are important for future research work on the development of numerical damage laws using the cohesive zone technique in order to establish, numerically, a representative model in terms of the ageing mechanism of the connections. From this point of view, the test bench thus created meets expectations. However, as one would expect, longer lifetimes are observed than those obtained on conventional modules, for similar thermal cycling. This difference can be explained by the use of thicker MOSFET chips, which limit the mechanical stresses in the attachment area. However, the objective here was not to analyse the representativeness in terms of lifetime, but to validate the interest of the test bench and the relevance of the observed quantities to highlight the failure mechanisms. From this point of view, the interest of this approach remains. The simplicity of implementation, the easiness of measuring the various quantities (voltage, current, temperature, resistance, etc.), the reproducibility of the stresses applied and the longterm energy savings are all advantages that make this solution attractive.

Figure 4 .

 4 Figure 4. 1Hz cycling simulation example (*) *For the sake of visibility, the currents on the left-hand side of the figure above does not correspond to the real currents injected to obtain the thermal profiles on the right-hand side (Actual: Dt = 0.5, Imax = 1.8A, I0 = 0.5A).

Figure 16 .

 16 Figure 16. Half LabVIEW ® supervisory interface (*)

Figure 17 .

 17 Figure 17. Matlab ® supervisory interface

Figure 20 .

 20 Figure 20. Evolution of contact resistance

ACKNOWLEDGMENT

The authors would like to express their gratitude to the company MICROCHIP ® (ex MICROSEMI ® ) for the donation of the chips and their help with the wiring of various samples.

The authors would also like to express their gratitude to the technological platform of the University of Montpellier PRO3D for the realization of the 3D printing supports.

The authors would also like to express their gratitude to the technology platform 3DPHI for help in making samples.