Michel Minondo

André Juge

Hervé Jaouen

Frederic Paillardet

Jean-Pierre Blanc

Lionel Vogt

Eric Nercessian

Nicolas Pelloux

Stephane Le Tual

Stmicroelectronics

Gilles Gouget

Clément Charbuillet

Kanika Sharma

Jean Remy

Benoit Legoix

Vincent Quenette

Frederic Dauge

Benoit Morel

Benjamin Dormieu

Pascal Fonteneau

Michel Buczko

Sebastien Jan

Keywords: Analog and RF, Double-gate FETs, Fully Depleted Silicon-on-Insulator (FDSOI), UTBB, Inversion Coefficient, Transconductance efficiency, gm over ID, Transadmittance efficiency, Low-Power, Low-Voltage, HF, mm-Wave, NQS, LNA, LNA-MIXER

STMicrolectronics for their collaboration

Résumé

Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l'art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l'impact de la grille arrière, à l'aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l'inversion modérée jusqu'à 110 GHz.

Mots-clés : Analogique et RF, Double Grille, FDSOI, UTBB, Coefficient d'inversion, Efficacité de la transconductance, gm sur ID, Efficacité de la transadmittance, faible puissance, faible tension, HF, spectre millimétrique, NQS, LNA, LNA-MIXER. The UTBB FDSOI MOSFET is considered as a planar low-cost and a straightforward solution to continue shrinking the CMOS transistor for low power and high-speed Very-Large-Scale Integration (VLSI) circuits [6]. The advantages of the UTBB FDSOI MOSFETs include: steep subthreshold slope (close to the room temperature Boltzmann limit of 60 mV/dec for long channels) thanks to the better control of the channel potential [7], low channel doping and excellent control of shortchannel effects (SCE). Both FinFET and UTBB FDSOI MOSFETs allow excellent channel control for high digital performances [8][9] [10]. However, analog and RF performances are affected unevenly.

List of Figures

List of tables and diagrams

Because of a crowded up-to-5 GHz spectrum with many interferers, some applications such as automotive radar started to tackle the mm-Wave spectrum looking for more bandwidth [11]. Other applications are under active investigation and design in mm-Wave spectrum such as low-power portable radars demonstrated in [12] and high data rate Wireless USB-like communication prospected in [13]. The aforementioned nanoscale CMOS device architectures display very high transit frequencies practically beyond the Millimeter-Wave (mm-Wave) spectrum and can be clearly used for these mm-Wave applications [14][15]. To be ready to take full advantage of the advanced nanoscale CMOS devices, the computer-aided design (CAD) tools have to be updated with accurate descriptions of their behavior in all operation conditions. Therefore, FinFET and UTBB FDSOI MOSFET models for high frequency (HF) and low-voltage (LV) applications are required. The simulation of advanced high precision mixed-mode analog circuits including A/D converters, switched-capacitor circuits, and RF amplifiers requires accurate device models in a large frequency spectrum including mm-Wave. Actually, at high frequency operation, the input signal may have rise or fall times comparable or smaller than the transit time of the transistor. Though all standard compact models, including the advanced Leti-UTSOI2 model, are mainly low frequency quasi-static models with no or simplified high frequency effects.

As mentioned above, low power consumption is one of the main challenges for

IoT widespread especially at high frequency operation for RF or mm-Wave communication. High performance rechargeable batteries have already granted a certain degree of autonomy. Moreover, CMOS technology evolution has allowed substantial reduction of power consumption needs in the digital part of the Integrated Circuits (ICs) [16][17]. To further reduce power consumption in the light battery powered devices, high frequency front-end subsystems design has to take into consideration power consumption. Particularly, with the increasing off leakage current that determines the systems stand-by power consumption, power management techniques have to be used and bias conditions have to be lowered. Furthermore, with the very high transit frequencies achieved today in submicron CMOS technologies, the operating point can be moved towards Weak Inversion (WI) and Moderate Inversion (MI) regimes in order to achieve low drive currents, higher gains and still acceptable operation frequencies [18]. Moderate Inversion operation is increasingly important for low-voltage and low-power CMOS applications since it allows for high transconductance efficiency and low VDSAT while maintaining high bandwidth.

Thesis Outline

After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, in Chapter 1 we go through the list of the advantages of the state-of-the-art UTBB FDSOI technology. We also present two modeling approaches as a basis of our research work. We then describe the existing compact models for quasi-static UTBB FDSOI MOSFET. Chapter 5 provides a study of the NQS behavior of the UTBB FDSOI MOSFET with a special focus on moderate inversion. Frequency dependence of small signal characteristics derived from experimental S-parameters are analyzed and reveal that the transconductance efficiency (gm/ID) concept, studied in Chapter 3 and already adopted as a low frequency Analog figure-of-merit (FoM), can be generalized to high frequency. We report that the normalized frequency dependence of the generalized FoM transadmittance efficiency (ym/ID) only depends on the mobility and inversion coefficient (IC). In addition, we used this novel approach to extract essential parameters such as the mobility, the critical NQS frequency fNQS and the transit frequency fT.

Chapter 6 discusses a sizing methodology where the previously developed charts and models are used in a simple 35 GHz LNA circuit design. The goal is to provide with an application example where operation in MI is profitable as long as both high frequency performance and power consumption matters.

Finally, an overall summary of this dissertation is presented along with future research suggestions in the Conclusion.

Chapter 1

State of the Art In order to overcome MOSFET off-state leakage current, the gate control over the channel potential distribution has to be enhanced. High-k materials were introduced since 45 nm technology node to help increasing the gate capacitance with less tunneling leakage and consequently enhance Gate control [19]. All enhancement techniques that were used in previous nodes hit their limit when approaching the 20 nm technology node. The mobility degradation due to scattering limited the doping concentration in the channel and the lattice maximum stress limited the mobility enhancement in strained channels [20][21]. With above limitations, novel device architectures with multiple gates were foreseen to continue device scaling. The first published work on the double-gate MOSFET, [2], shows significant SCE reduction in FDSOI MOSFETs while adding a bottom or back gate. With this architecture, the influence of the drain electric field on the channel is reduced. However, the first manufactured double-gate MOSFET was the fully depleted lean-channel transistor (DELTA) which is similar to FinFET but without the top hard mask [4]. Two leading technology contenders have been adopted and are in production today: the symmetric DG FinFET and the asymmetric DG UTBB FDSOI. The two basic differences between the two technological solutions are the gates and the channel orientation, and the two gates connection. FinFET is basically a double-gate in which the two gates are connected together. However, in a UTBB FDSOI MOSFET, the two gates are not connected and can be bias differently. Otherwise FinFET and UTBB FDSOI look the same as depicted in Fig. 1.1 and provide comparable digital performances [22]. The RF behavior of FinFET is however affected by a large level of parasitic elements [14]. An important propriety of DG MOSFETs (i.e. FinFET, UTBB FDSOI, etc.) namely volume inversion (VI) has been discovered in 1987 [26]. Volume inversion occurs in very thin silicon films controlled by two gates which is the case for a UTBB FDSOI MOSFET where inversion carriers are not confined in the Si/SiO2 interface, as predicted by classical semiconductor physics, but rather in all volume of the silicon film. This phenomena will be illustrated using our TCAD simulations in Chapter 2 and evidenced using our measured data in Chapters 2, 3, and 5. The quantum confinement in the thin Si film is at the origin of the VI effect [27]. Although volume inversion phenomena is demonstrated, its modeling is frequently overlooked and charge-sheet approximation is forced [28][29]. Accurate results are obtained with modeling the quantum confinement effect using offsets applied on gates voltages or vertical dimensions in [30] and [31], and using the concept of inversion layer centroid in [32].

State of the Art

Moreover, multiple inversion charges (front and back) and vertically variant carrier mobility are considered to retrieve the total charge and the effective mobility [30][33].

Actually the calculation of the electron concentration in the presence of confinement needs to solve Poisson's and Schrödinger's equation self-consistently but this is frequently ignored.

UTBB FDSOI technology

FDSOI technology started to draw attention in the middle of the 80s because of its multiple advantages over the partially-depleted SOI [7]. Several SOI wafers fabrication processes were developed and used for SOI CMOS such as the Separation by IMplanted OXygen (SIMOX) and ELTRAN [35][36]. In our research work, the UTBB FDSOI wafers are fabricated using a UNIBOND substrate made with Smart Cut technology reported by LETI in 1995 [37]. The UNIBOND process involves several steps as shown in Fig. 1.5. After oxidation, hydrogen is implanted into a Si donor wafer.

The donor wafer is bonded to another wafer to form the future BOX. Smart Cut step is the operation of splitting off the donor wafer at a temperature of 500 to 600 °C.

Planarization of the surface ends this process and results in a UTBB FDSOI wafer where the MOSFET will be formed and a recycled donor wafer. ) The channel is rotated by 45° from the <100> plane [43]. FDSOI technology allows co-integration of both bulk and SOI devices on the same die thanks to BOX opening for the bulk parts with a dedicated mask [44]. Carrier mobility is enhanced due to weaker surface electric field and low doping concentration in the Si film. With thin Si film, no punch-through current exists and consequently MOSFETs can be made shorter with no need to dope the Si film, and with the inherited advantage of higher electron mobility. The UTBB FDSOI MOSFET is first introduced at the 28 nm technology node [3],

V bG = -3 V V bG = 0 V V bG = 2 V V bG = 5 V
and demonstrated using efficient ARM processor architecture based chips operating at high frequency [45]. Scaling of the UTBB FDSOI technology to the 14 nm technology node is also demonstrated [START_REF] Weber | 14nm FDSOI technology for high speed and energy efficient applications[END_REF]. The key feature of a FDSOI MOSFET in comparison to the partially depleted SOI (PDSOI) is that the depletion region occupies the whole thickness of the silicon film all the way to the Si/BOX interface. Consequently, the floating-body effects of the PDSOI are bypassed in the FDSOI devices.

One major advantage UTBB FDSOI has in comparison to bulk technology is the possibility to control the threshold voltage (VTH) using the back gate voltage for both Nand P-type MOSFETs with a modulation factor of ~80 mV / 1V [START_REF] Makipaa | FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?[END_REF]. Fig. Moreover, same bulk technology design flows are applicable to UTBB FDSOI as both technologies are planar [START_REF] Skotnicki | Competitive SOC with UTBB SOI[END_REF]. Fig. 1.9 shows the difference between the UTBB FDSOI MOSFET and an advanced bulk MOSFET cross sections. Halos and channel implants are no more required in UTBB FDSOI thanks to the BOX isolation. Unlike bulk MOSFET, UTBB FDSOI is not subject to the turn on of parasitic pn-p-n (or n-p-n-p) thyristors causing latch-up in bulk. As UTBB FDSOI has no parasitic thyristors, consequently there is no need for special circuit layout or process to prevent latch-up. Moreover, UTBB FDSOI are ideally isolated from the substrate thanks to the BOX and laterally from each other using shallow-trench-isolation (STI) as shown in Fig. V GS (V)

I D /(W/L) (A) V bG = -4 V V bG = -3 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 3 V V bG = 4 V V bG = 5 V
In comparison to advanced bulk technologies, FDSOI presents lower DIBL with an enhancement of more than 40 mV/V in short channels as shown in Fig. 1.10. Chapters. This FoM can be used to gain insight into the transfer characteristic of a MOSFET in its semi logarithmic form for all levels of inversion as it is expressed as:

= ln

(1.1)
The plateau of the gm/ID plots (i.e. maximum gm/ID), which represents the weak inversion region, is inversely proportional to the subthreshold slope. The 28 nm FDSOI technology provides near ideal subthreshold slope (1.07) versus 65 nm bulk (1.13) and 28 nm bulk (1.17). The downscaling from 65 nm to 28 nm bulk clearly shows the electrostatic control issue, which results in higher leakage. Moreover, the short channel effects, responsible of the departure from the ideal square law current expression are worst for 28 nm bulk as shown in the inset of Fig. 1.11. The velocity saturation and series resistances are responsible for the decrease of gm/ID at high current density and departure from the ~1/√ID trend. The main advantage of 28 nm bulk versus 65 nm bulk is the higher gm/ID in strong inversion region thanks to a higher Cox.µ0, which results into a lower current for same transconductance value (analog applications), and a higher ION current (digital applications). Besides a better subthreshold slope, the 28 nm Buried oxide isolation is known to give birth to temperature increase because of self-heating effect [START_REF] Su | Measurement and modeling of self-heating in SOI nMOSFET's[END_REF], however, thanks to a thinner BOX in the UTBB FDSOI, thermal effects influence on device parameters are limited in comparison with standard SOI [START_REF] Makovejev | Selfheating in 28 nm bulk and FDSOI[END_REF]. Similar to SOI devices, UTBB FDSOI MOSFET displays excellent radiation hardness to the detrimental alpha particles, neutrons, and other particles that generate electron-hole pairs after Si penetration [START_REF] Roche | Technology downscaling worsening radiation effects in bulk: SOI to the rescue[END_REF]. ) where additional elements are added such as source to drain capacitance. Actually, this equivalent circuit is used for small-signal simulations where linear relations between current and voltage are assumed, and is called the small-signal equivalent circuit.

BULK 65nm L = 1 um V DS = 1.2 V BULK 28nm L = 1 um V DS = 1.2 V FDSOI 28nm L = 1 um V DS = 1 V
With better understanding of the MOSFET physics along with higher computing power availability, compact modeling became a more efficient alternative and an important research area. Years later, the equivalent circuit approach is still inevitable for two main reasons. On the one hand simple lumped element circuits are helpful for analog hand calculation based design and for a better insight into MOSFET physics.

On the other hand, equivalent circuits are used to complement and augment low frequency compact models by describing external parasitic elements or complex distributed effects. Though, because of the several nodes in an equivalent circuit and the large SPICE simulator computation time involved, scalable compact models are the industry models of choice for the device core. A practical modeling approach in semiconductor industry is the simultaneous use of the two approaches in RF modeling. Sub-circuits are built using passive elements network on top of intrinsic or core MOSFET models that have been qualified for DC and low frequency operation. The high frequency behavior of MOSFETs is captured using additional lumped elements to end up with complex sub-circuits.

Lumped elements are commonly added to each MOSFET terminal. The gate and substrate are modeled using passive RC network while simple series resistances are added to the source and drain. In general, this approach takes advantage of industry standards, such as the threshold voltage (VTH) based BSIM4 model from UC Berkeley and the surface potential based PSP model originated from Philips and Pennsylvania State University (currently supported by LETI and NXP), as far as bulk MOSFETs are concerned. The aforementioned approach will be adopted in addition to an equivalent circuit in our work for its efficiency in an industrial usage. The equivalent circuit will be proposed as an alternative for the core compact model in order to gain practical insight into the contributors to the small signal behavior.

For UTBB FDSOI MOSFET, several core models have been proposed but four main industry level compact models exist.

UTBB FDSOI compact models

Early compact models assume a depleted back interface with huge limitations when back gate voltage is high (forward back gate bias or FBB). In an asymmetric double gate MOSFET, the resolution of Poisson equation with boundary conditions is not an easy task. Depending on the number of the introduced boundary conditions, numerical resolution of one [START_REF] Sahoo | A Computationally Efficient Generalized Poisson Solution for Independent Double-Gate Transistors[END_REF] or two [START_REF] Lu | An analytic potential model for symmetric and asymmetric DG MOSFETs[END_REF] coupled equations is used after a calculation to separate between hyperbolic (i.e. zero potential) and trigonometric (i.e. zero field) possible modes. Fig. 1.13 shows the regions of the front and back gates voltages plane where the equations to be solved are trigonometric or hyperbolic [START_REF] Taur | Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs[END_REF]. This calculation relies on Lambert functions usage [START_REF] Dessai | Solution space for the independent-gate asymmetric DGFET[END_REF]. The problem has been also written in a more suitable formulation of three coupled complex equations [START_REF] Ortiz-Conde | Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET[END_REF], but this does not lead to an analytical solution for the surface potentials in the film and box interfaces. A summary of the surface potential calculation models for an asymmetric DG MOSFET is given in Table 1- [29]. The three positions are the upper and lower sides of the silicon film, and the lower side of the BOX. The potential distribution is numerically solved using Newton iteration method. Under the gradual-channel approximation, the potential distribution in the channel is described by the potential at the source side and the drain side.

Consequently, the charges at the source and drain sides are obtained. Surprisingly, the charge-sheet approximation is claimed to be valid even with thin silicon films where carriers are distributed within all the volume of the silicon film. The total charges are calculated by the integration of the charge distribution along the channel. Current is then deduced from the integrated inversion charge using a bulk-like mobility model with three scattering effects: Coulomb, Phonon, and Surface Roughness. Capacitances are then determined by a charge derivation.

UFDG

UFDG model from university of Florida is claimed to be physically based and generic model for symmetric (e.g. FinFET) or asymmetric (e.g. UTBB FDSOI) DG

MOSFETs [START_REF] Kim | Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices[END_REF]. The model can also be used for single gate MOSFETs with thick BOX [START_REF] Trivedi | Scaling fully depleted SOI CMOS[END_REF]. 2D Poisson's equation in the channel region is solved while assuming a secondorder polynomial function for the electric potential and using four bias dependent boundary conditions [START_REF] Yeh | Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology[END_REF]. The carrier-energy quantization is then taken into account using a potential offset [START_REF] Lixin Ge | Physical Modeling and Analysis of Carrier Confinement and Transport in Siliconon-Insulator and Double-Gate CMOS Devices and Circuits[END_REF]. The diffusion current in WI is then calculated by integrating the electron density in the Si film. In Strong Inversion (SI), where the quantum effect is more important, an iterative and self-consistent solution of the 1D Schrodinger's and

Poisson's equations is developed. Spline polynomial functions are used in MI to continuously link the physically based WI and SI models. Quantum confinement in the thin Si film and volume inversion are taken into account for thin Si films [START_REF] Ge | Mobility enhancement via volume inversion in double-gate MOSFETs[END_REF]. The transport is modeled as quasi-ballistic using velocity overshoot derived from Boltzmann transport equation and its moments [START_REF] Ge | Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits[END_REF]. Main parasitic elements are included.

Terminal charges are calculated by an integration of the channel current. Short channel effects are modeled and main parasitic elements such as series resistances, overlap capacitances, and gate resistance are included. Self-heating effect is also proposed in UFDG model.

Leti-UTSOI2

Leti-UTSOI2 (or UTSOI2) is a surface potential based compact model describing the ultra-thin fully depleted SOI MOSFET with a lightly doped silicon film [START_REF] Poiroux | UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs[END_REF]. UTSOI2 physical core is suitable for any independent double gate transistor with low-doped channel, and in particular for UTBB-FDSOI architectures.

In UTSOI2, explicit formulations of the front and back surface potentials (ψs1, ψs2) are used to calculate the drain current (ID) and the intrinsic mobile charge (Qinv).

While iterative resolution of Poisson's equation is used in HISIM STOB, in UTSOI2 an accurate and direct calculation of interface potentials is used. As in [START_REF] Ortiz-Conde | Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET[END_REF] and after integration of Poisson's equation along with the boundary condition, three coupled equations are obtained [START_REF] Poiroux | UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs[END_REF]. The key point in UTSOI2 is that to solve the three equations there is no need to know a priori if the solution is in the hyperbolic or trigonometric mode depicted in Fig. 1.13. The three equations are transformed into one equation that is solved analytically using three successive corrections based on 2 nd order Taylor development as for PSP bulk model.

Partitioning of inversion charge between source and drain is classically calculated using front interface potential. However, for asymmetric DG MOSFET where more than one interface is available, the classical way is not relevant. In UTSOI2, following the solution proposed in [START_REF] Dessai | Solution space for the independent-gate asymmetric DGFET[END_REF], charges are obtained from the drain current calculation. Short and narrow channel effects, series resistance, overlap capacitance, fringing capacitance and backplane related parasitic capacitances are all accounted for.

The UTSOI2 satisfies continuity requirements for currents and capacitances as well as for their higher order derivatives. It is compliant with all MOSFET standard models criteria such as DC and AC symmetry and robustness in all operation conditions [START_REF] Li | Benchmark Tests for MOSFET Compact Models With Application to the PSP Model[END_REF].

Conclusion

This Chapter briefly reviews the evolution of the MOSFET architecture from single-gate to double-gate in the last few decades. In order to mitigate the short channel effects that result from advanced MOSFET downscaling, two gates control of the channel appears to be a straight-forward solution. DG UTBB FDSOI architecture exhibits several advantages for digital applications and outperforms bulk and FinFET in Analog and RF applications thanks to the reduced parasitic elements [START_REF] Sakurai | Fully-depleted SOI CMOS circuits and technology for ultra-low power applications[END_REF][47] [14].

In this research work, focus is limited to the UTBB FDSOI MOSFET manufactured in 28 nm and 14 nm technology nodes.

In Section 1.3, two main modeling approaches are discussed. The combination of a core, based on either a compact model or an equivalent circuit, along with lumped extrinsic elements within a sub-circuit is the most accurate approach for an industrial usage [77][78]. This approach is used in this work.

The last Section of this Chapter describes the existing compact models for DG UTBB FDSOI MOSFET. The list is limited to the compact models that are ready for an industrial usage and that include all important physical effects. Leti In recent low power and high performance circuits such as those implemented in FDSOI for IoT market, one needs to operate MOSFETs from weak to strong inversion levels [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF]. It is worth pointing that moderate inversion region has been found to be a good compromise while power consumption and speed are valued equally [START_REF] Mangla | Figure-of-merit for optimizing the currentefficiency of low-power RF circuits[END_REF][25] [15]. The MI provides higher transconductance for lower current, and still acceptable bandwidth for low power and low voltage applications. The importance of the moderate inversion region and the related modeling issues are pointed out for bulk earlier in [START_REF] Tsividis | Moderate inversion in MOS devices[END_REF].

In order to fully benefit from the advantages of the FDSOI technology, MOSFET compact models should accurately reproduce transistor behavior in all regions of operation especially in low inversion. For hand calculations, although classical WI exponential law and SI square law models can be carefully used, the gm/ID charts developed in the next Chapter are more convenient to predict UTBB FDSOI MOSFET capability in all levels of inversion. Moreover, for an industrial usage and as seen in the previous Chapter, UTSOI2 is the first available independent double-gate compact model able to describe accurately the UTBB MOSFET in all bias conditions, including strong forward back bias [START_REF] Poiroux | Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies -Part I: Interface Potentials Analytical Model[END_REF]. UTSOI2 model was validated against numerical simulations and measurements for DC operation showing excellent predictability and scalability properties [30]. However, its RF capabilities have been only highlighted in [START_REF] Barbé | 4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors[END_REF] and clearly ask for more in depth analysis. Noting that digital FoMs such as ION and IOFF are not sufficient to assess analog behavior of a MOSFET. Moreover, analog applications such as amplification need accurate prediction of continuous and higher order MOSFET metrics and FoMs in all levels of inversion.

Therefore, two different quasi-static models will be considered for low frequency operation and will be both used as starting blocks for the augmented high frequency non-quasi-static model: (1) an equivalent small signal circuit, and (2) UTSOI2 model. This Chapter will focus on the description and modeling of the DC and low frequency behavior of the UTBB FDSOI MOSFET. In particular, the special double gate operation will be presented and compared to the bulk single gate operation using measured data. The ability of the proposed models to describe the DC and the small signal low to medium frequency operation will be studied with a focus on low voltage bias conditions.

TCAD simulations will also be performed on two different decks using Sentaurus standard process and device simulator from Synopsys, Inc. : (1) a simple deck without the raised source and drain and using a constant carrier mobility in order to capture first order effects, and (2) a calibrated deck with raised source and drain, and advanced thin layer mobility model with enhanced carrier effective mass [START_REF] Reggiani | Physically-based unified compact model for low-field carrier mobility in MOSFETs with different gate stacks and biaxial/uniaxial stress conditions[END_REF]. The 28 nm FDSOI technology calibrated TCAD deck will be crucial for back gate impact assessment in both low frequency and high frequency operations.

Synopsys Sentaurus TCAD tool is calibrated at a temperature of 300 K. NMOS and PMOS measurements of four lengths (e.g. L = 30 nm, 40 nm, 100 nm, and 1 µm) and In order to match gm in Moderate Inversion, fixed charge traps (Nhk = 5 × 1012 cm -2 ) on the shared interface between high-k HfO2 dielectric and the interfacial oxide layer (SiO2) are considered.

The Chapter is organized as follows. In Section 2.2, the DC and low frequency operation of the UTBB FDSOI MOSFET is described using measurements and TCAD simulations, especially for low inversion levels. In Section 2.3, the simple bulk long channel model is compared to the DG counterpart showing deep similarities, and a small signal equivalent circuit is proposed for simple device assessment. In the same Section, the measured structures are described along with the characterization steps.

Having in mind an industrial usage, in Section 2. is used to adjust simultaneously the threshold voltage of the N and P types MOSFETs while keeping the channel undoped [START_REF] Fenouillet-Beranger | Fully-depleted SOI technology using high-k and singlemetal gate for 32 nm node LSTP applications featuring 0.179 um2 6T-SRAM bitcell[END_REF]. The source and drain regions are raised using epitaxial step in order to reduce series resistance. A heavily doped Si layer underneath the BOX is introduced in order to suppress the depleted zone under the BOX, further

to reduce the coupling between the source and the drain regions, which eliminates high frequency analog performance degradation, and finally to allow VTH control [40][88] [START_REF] Fenouillet-Beranger | Efficient multi-V T FDSOI technology with UTBOX for low power circuit design[END_REF]. Well-type implantation is used for the ground-plane or back gate region under the BOX and the ground plane [3].

For the 28 nm UTBB FDSOI technology the maximum front gate voltage that is recommended for thin oxide MOSFETs is VDD = 1 V. The minimal recommended length is 30 nm and commonly called nominal length, while minimum possible length is 28 nm and also characterized in this research work. In [START_REF] Park | A unified currentvoltage model for long-channel nMOSFETs[END_REF], the derivative of the gate to channel capacitance Cgc with respect to VGS is used to extract a threshold voltage. Actually, in bulk, we have the following relation:

≡ = • = = -Ψ = 1 - Ψ (2.1) -1 -0.5 0 0.5 1 0 0.2 0.4 0.6 0.8 1 V GS (V) C gc (n.u.) V bG = -10 V V bG = -5 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 5 V V bG = 10 V -1 -0.
V bG = -10 V V bG = -5 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 5 V V bG = 10 V
where Qinv, Cox, Vox, and ψs are respectively the inversion charge, the oxide capacitance, the oxide voltage drop, and the surface potential. If we derive (2.1) with respect to VGS, we get:

= - Ψ (2.2)
This quantity becomes equal to zero at the inflection point of the surface potential plot with respect to VGS and corresponds to the inversion charge rise. Therefore, the maximum of the Cgc derivative determines the VGS at which an accelerated increase of the capacitance occurs, which is in turn a consequence of the inversion start in the channel. The derivative of Cgc for a UTBB FDSOI MOSFET is shown in Fig. 2 This is a demonstration of the volume inversion in the silicon film of the UTBB FDOI. V GS (V)

∂C gc /∂V GS (F/V) V bG = -10 V V bG = -5 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 5 V V bG = 10 V -0.5 0 0.5 1 1.5 2 0 0.5 1 1.5 2 2.5 x 10 -14
V GS (V) )

Cgc (F) V bG = -7 V V bG = 0 V V bG = 7 V
V GS = 1 V V GS = 0.9 V V GS = 0.8 V V GS = 0.7 V V GS = 0.6 V V GS = 0.5 V V GS = 0.4 V V GS = 0.3 V V GS = 0.2 V V GS = 0.1 V V GS = 0 V

I-V characteristic

The C-V characteristic at low or zero VDS provides insight into the device electrostatic. However, for DC operation, a positive VDS is applied between the drain and source of the MOSFET to produce a lateral electrical field that enhances the current through the channel. Fig. 2.9 shows measured input characteristics ID-VGS for various back gate voltages VbG in a logarithmic scale. The logarithmic scale is convenient to highlight the operation in the weak and moderate inversion regimes. The first observation is that all ID-VGS plots have similar shapes with a shift towards negative VGS values while VbG is increased. An important figure of merit is the slope of this input characteristic in its logarithmic scale, which is nothing other than the gm over ID as we have:

!" = $ ln $ = 1 = (2.3)
If we plot the gm over ID characteristic with respect to the normalized current ID.L/W for various VbG in a log-log scale, we get the interesting invariance property shown in Fig. 2.10. This property will be assessed in Chapter 3 using measurements with respect to geometry, back gate voltage, temperature, drain to source voltage, and process variations. For SI, all the plots tend to the square law characteristic which varies as the inverse of the square root of the current. For WI, a plateau is measured with a level as -10 -5 0 5 10

-0.3 0 0.3 0.6 0.9 V bG (V) V TH (V)
high as 36 V -1 , which corresponds to a near ideal slope factor of 1.08. The fixed value in WI corroborated the exponential evolution of the drain current with respect to VGS. Apparently, similar observations can be made as for the C-V characteristics exploitation regarding the impact of the back gate voltage. In order to have a closer insight into the threshold voltage evolution based on I-V characteristics, the gm over ID is used as in [START_REF] Flandre | Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold[END_REF]. In bulk, the derivative of the gm over ID is used to extract a threshold voltage noting that we have in WI and using (2.2):

-0. V GS (V) )

I D /(W/L) (A) V bG = -4 V V bG = -3 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 3 V V bG = 4 V V bG = 5 V
V bG = -4 V V bG = -3 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 3 V V bG = 4 V V bG = 5 V SI trend NMOS WI trend SI WI = % & ' ( ) * + , = $ ln $ = 1 -. Ψ (2.4)
Consequently we get:

' , = 1 -. Ψ (2.5)
In bulk, this quantity is proportional to the quantity expressed in (2.2), and also determines the inversion charge rise when set to 0. The derivatives of the gm over ID with respect to VGS are shown in Fig. 2.11. Surprisingly, we don't observe two local maximums for high VbG as observed in Fig. 2.4, and the extracted threshold voltages are not exactly the same as those extracted using the capacitance derivatives (i.e. up to 90 mV mismatch as reported in Table 2-1 knowing that DIBL cannot be the root cause of this difference at V DS = 50 mV). It should be noted that, for low VbG (particularly for VbG ≤ 0 V) and based on (2.2) and (2.5), the following equality is verified:

-. • ' , = - 1 • (2.6)
Therefore, this demonstrates that the VTH extraction methodology proposed by Flandre [START_REF] Flandre | Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold[END_REF] for advanced MOSFETs cannot be applied to an asymmetric DG MOSFET especially at positive back gate voltages where apparent mobility is highly affected by the front and back gates control.

For low VbG, where the inversion charge is closer to the front interface like in the bulk case, the inflexion point of the surface potential is rather closely tied to the electrostatic behavior of the device. However, for high VbG with a stronger volume inversion phenomena, the equality in (2.6) is no more valid and the mobility contributes also to the observed difference in the threshold voltage values extracted using the C-V derivative based method with respect to the gm/ID derivative based method. TCAD simulations on a calibrated deck (raised source and drain for lower series resistance, Tsi = 7 nm, and advanced mobility model using the thin layer mobility with enhanced carrier effective mass [START_REF] Reggiani | Physically-based unified compact model for low-field carrier mobility in MOSFETs with different gate stacks and biaxial/uniaxial stress conditions[END_REF]) are run and the results are shown in Fig. 2.12 and Fig. 2.13. As expected, the inversion charge concentration depicted in Fig. 2.12 (b)-(d) is higher at the front of the Si film for low VbG and higher at the back of the Si film for high VbG. At some specific front and back gates voltages, the volume inversion phenomena is enhanced. The ID-V GS is also reproduced accurately in Fig. 2.12 (a). The extraction of the threshold voltage using both the Cgc and gm/ID derivatives provided similar conclusions than those based on measurement data. This is depicted in Fig.

V GS (V) ∂(g m /I D )/∂V GS (V -2 ) V bG = -4 V V bG = -3 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 3 V V bG = 4 V V bG = 5 V
measured one. However, as illustrated in Fig. 3.1, the gm over ID invariance evidenced using measurement data in Fig. 2.10 is not reproduced using TCAD simulations most probably because of the TCAD transport model limitations. The gm over ID invariance is studied in detail in Chapter 3. Both electrostatic and transport contribute to the gm over ID characteristic as:

= /0 = 1 + 1 2 2 (2.7)
noting that = • 2, where v is the average velocity of the charge carrier. In order to assess the transport contribution to the gm over ID characteristic, we propose to use a simple mathematical expression based on (2.7) and given as:

1 2 2 = - 1 (2.8)
This mathematical operation is applied to measured data for various VbG values.

Inversion charge Qinv is extracted using a careful integration of the Cgc-VGS characteristics. V GS (V)

∂(g m /I D )/∂(V GS ) (V -2 ) (b) -1 -0.5 0 0.5 1 -0.5 0 0.5 1 1.5 2 2.5 3 x 10 -11 V GS (V) C gc (F) & ∂C gc /∂V GS (F/V) C gc ∂C gc /∂V GS (c)
in (b). We clearly observe the impact of the VbG on carrier velocity. As for the gm over ID at high currents, the transport quantity which is equal to the derivative of ln(v) with respect to VGS has its minimum at higher velocities. Therefore, for intermediate VbG values, thanks to the volume inversion strength, the maximum apparent carrier velocity is higher. The term "apparent" stands for the fact that the transport metrics we extract (i.e. carrier velocity or mobility) using drain current characteristic represents an average on all carriers in the silicon film (i.e. in all its volume). Thanks to a lower vertical field, while volume inversion is taking place, more carriers in the Si volume are contributing to the transport and this is observed as an increase of the mobility in various publications such as in Ohata [START_REF] Ohata | Mobility comparison between front and back channels in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors by the front-gate split capacitance-voltage method[END_REF] and Rudenko [START_REF] Rudenko | Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides[END_REF]. Moreover, we will demonstrate using a novel method based on high frequency NQS effect that mobility is practically unchanged over all levels of inversion (cf. Section 5.7). Our interpretation is also corroborated in Chapter 3 while studying the invariance of the transconductance efficiency (cf. Fig. 3.6). ) .L/W (A)

v bG = -3 V v bG = -2.5 V v bG = -2 V v bG = -1.5 V v bG = -1 V v bG = -0.5 V v bG = 0 V v bG = 0.5 V v bG = 1 V v bG = 1.5 V v bG = 2 V v bG = 2.5 V v bG = 3 V (a)
∂Q inv /∂V GS .(1/Q inv ) (V -1 ) v bG = -3 V v bG = -2.5 V v bG = -2 V v bG = -1.5 V v bG = -1 V v bG = -0.5 V v bG = 0 V v bG = 0.5 V v bG = 1 V v bG = 1.5 V v bG = 2 V v bG = 2.5 V v bG = 3 V (b)

DC and low frequency small-signal operation modeling and characterization

The accuracy of circuit simulations mainly depend on the quality of the involved models. High quality models are physics based and verified against measurements for various geometries and bias conditions. For DC and low frequency operation of the UTBB FDSOI MOSFET, two modeling approaches are used in this work. On the one hand simple hand calculation expressions or charts along with an equivalent small signal circuit are used to predict main bias currents/voltages, and small signal FoMs of the transistor, and on the other hand the newly proposed UTSOI2 compact model, which is suitable for an industrial usage. The advantage of the first approach is its simplicity and suitability for analog design context, in that it helps to get insight into the behavior of the MOSFET without the complexity of a compact model. However, this simple approach is not adapted for large circuit simulations where scalability and variability models are required. The second approach is the most adapted for an industrial usage provided that the quasi-static compact model is augmented and completed for high frequency accuracy. This second approach is proposed and validated in our work, while the first approach is used for simplicity when relevant. .L/W (A)

0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 v GS (V) (1/v).∂v/∂V GS (V -1 ) v bG = -3 V v bG = -2.5 V v bG = -2 V v bG = -1.5 V v bG = -1 V v bG = -0.5 V v bG = 0 V v bG = 0.5 V v bG = 1 V v bG = 1.5 V v bG = 2 V v bG = 2.5 V v bG = 3 V (a)
(1/v).∂v/∂V GS (V -1 ) v bG = -3 V v bG = -2.5 V v bG = -2 V v bG = -1.5 V v bG = -1 V v bG = -0.5 V v bG = 0 V v bG = 0.5 V v bG = 1 V v bG = 1.5 V v bG = 2 V v bG = 2.5 V v bG = 3 V (b)
In this Section, first the long channel DC model is discussed to pave the road towards the dynamic small signal model using equivalent circuits. Next, the main physical effects involved are briefly described. Finally, the DC and low frequency operation is assessed through several MOSFET metrics and FoMs.

Long channel DC modeling -a threshold voltage based approach

In Fig. 2.10, UTBB FDSOI I-V characteristic in SI is shown to be very close to the square law derived for early bulk technologies in the case of a long channel for which mobility reduction, velocity saturation, and series resistance have lower impact.

In WI, I-V characteristic follows an ideal exponential law with constant slope in logarithmic scale. Having these observations in mind, we propose to re-derive the square law I-V model for the bulk case using a special mathematical approach. Then the validity of the square law is discussed for the UTBB FDSOI case. In particular, we show that the square law model is valid in SI provided that the threshold voltage expression is adapted for a double gate architecture. In the case of the bulk N-type MOSFET shown in Fig. 2.16, which is somehow comparable to the case of FDSOI with infinite silicon film thickness, the drain current is expressed using the drift and diffusion contributions as [START_REF] Pao | Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors[END_REF]:

= 3 -4. . 6 7 + 4-. 7 = -43 7 (2.9)
where µ is the carrier mobility at x (x = 0 at the source side).

Qi is the inversion charge at x

Ψs is the surface potential at x UT is the thermal voltage

V is the quasi-Fermi level

Since ID is constant at any location x along the channel, deriving (2.9) one obtains:

7 = 7 . μ. 7 + . μ 7 . 7 + . μ. 7 = 0 (2.10)
If we consider a constant mobility in the channel, the differential equation (2.10) becomes:

7 . 7 + . 7 = 0 (2.11)
The inversion charge Qi, which is the algebraic sum of the gate and depletion charges, can be obtained by linearizing the maximum depth of the depletion region as a function of the quasi-Fermi level V(x) [START_REF] Colinge | Physics of Semiconductor Devices[END_REF]. The inversion charge is given in SI by: = 7 = -: -.; -0. 7 < (2.12)

where Cox and VTH are respectively the oxide capacitance per unit area and the threshold voltage, and n is the slope factor approximated using the capacitive divider based expression:

0 = 1 + =>? (2.13)
where Cdep is the depletion capacitance.

The inversion charge expression (2.12) can be derived using Gauss's law at the interface and from the interface to a region deep in the Si bulk, and assuming the thickness of the inversion layer is negligible (charge sheet approximation).

Using (2.12) in (2.11), we obtain the following differential equation:

-0. 7 + -.; -0. . 7 = 0 (2.14)
If we define: @ = -.; -0. , (2.14) becomes:

@ A + @. @ AA = 0 (2.15)
This linear second order differential equation can be solved using a new variable defined as:

-= @ A = B@ B7 (2.16)
Deriving (2.16) gives:

@ AA = B- B@ - (2.17)
The differential equation (2.15) becomes:

B- - = - B@ @ (2.18)
After integration one obtains:

-= 1 @ . & C D = B@ B7 (2.19)
where K1 is an integration constant which is determined using the following boundary conditions: V(x=0) = VS = 0 and V(x=L) = VD, where L is the channel length. Using the boundary conditions, a second integration of (2.19) (steps are not shown) provides the expression of X as a function of the location x, which leads to:

7 = -.; 0 E1 -F1 - 7 G H1 -1 - 0. -.; IJ (2.20)
Same expression is obtained if one choses, as a solution for (2.15), the following expression:

@ = K • L1 -M7 (2.21)
Using (2.20) for x = 0 (at the source side), the drain current expression (2.9) becomes:

= 3 G 4 N -.; - 0. 2 P (2.22)
The latter equation describes the linear region operation of the MOSFET, which is a parabolic dependence of the drain current on the drain voltage. ID reaches a maximum when the drain voltage is equal to VDSAT. Using ∂ID/∂VD = 0 and assuming that VS = 0, VDSAT is given by:

Q. = -.; 0 (2.23)
And replacing VDSAT in (2.22) gives the drain saturation current commonly known as the square law:

= 3 G 4 -.; 20 (2.24)
The previous bulk inversion charge derivation cannot be applied as such to an asymmetric double gate such as UTBB FDSOI MOSFET, where the buried oxide capacitance and the back Si/SiO2 interface state can have a considerable impact on the front inversion charge. Moreover, in the state of the art UTBB FDSOI technology, the silicon film is undoped or lightly doped while in bulk the channel is doped. Actually even the charge sheet approximation is no more relevant if we consider a thin silicon film as stated earlier in Chapter 1.

In the following, we will show that similar WI and SI bulk models can be derived in the case of UTBB FDSOI, provided that the threshold voltage is adapted to the asymmetric double gate architecture. The details on the calculations based on [START_REF] Reyboz | Continuous model for independent double gate MOSFET[END_REF] are given in Appendix A. Inversion charges formulations using equivalent threshold voltages, comparable to the bulk case, are finally retrieved. The front and back threshold voltages expressions using physical dimensions, capacitances, and applied voltages are given as:

.

;R A = 0 R • -. • ln 2 • 0 R • R • -. S • 0 • T -0 R -1 • U A -0 R • -. • ln V tanh >Z • U A -A 2 • -. >Z • U A -A 2 • -. [ (2.

25)

.

; A = 0 • -. • ln 2 • 0 • • -. S • 0 • T -0 -1 • A -0 • -. • ln V tanh >Z • U A -A 2 • -. >Z • U A -A 2 • -. [ (2.26)
where:

V G ' (VbG') is the voltage difference between the front (back) gate voltage and the corresponding front (back) flat band voltage.

ns1 and ns2 are coupling factors equivalent to front and back slope factors, respectively.

Cox1 and Cox2 are the front and back oxide capacitances per unit area.

tsi is the silicon film thickness.

q and ni are the electron charge and the intrinsic doping, respectively.

Csi is the silicon film capacitance per unit area.

Ceq is the equivalent capacitance per unit area of the series Cox1, Csi, and Cox2.

Refer to Appendix A for the expressions of the involved parameters.

The derivation in Appendix A and the threshold voltage expressions reproduced above show that a threshold voltage based approach is still valid at least at certain bias conditions. Threshold voltage expressions (2.25) and (2.26) are valid when the other interface is still in WI. When the other interface is strongly inverted, the threshold voltage is no more dependent on the other gate voltage as the other interface screens this effect. The case of both front and back interfaces inversion can be handled using coupling effects between the two interfaces. The generalization of this coupling effects is used by Lime [START_REF] Lime | A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation[END_REF], with a coupling charge expression given as:

% = • Ψ R -Ψ (2.27)
The drain current is calculated using same general expression as in (2.9). The only difference is that the inversion charge has two components: front and back.

The above approach is proposed in [START_REF] Reyboz | Continuous model for independent double gate MOSFET[END_REF] along with some modeling and physical limitations. Moreover, the WI and SI assumptions considered in above derivations are not valid in Moderate Inversion. Alternatives to this approach, using the surface potential or the inversion charge, are proposed in the literature as discussed in Chapter The drain current expression is complex in an asymmetric double gate MOSFET, and cannot be easily used for hand calculations in analog and RF design.

However, we have shown that a threshold voltage based approach similar to bulk can be used to get a first insight, especially in SI and WI regimes. In MI where the simple models fail or for the case of short channels, measured charts (cf. Chapter 3) can be used to estimate the analog performance of the device. In particular, the UTBB FDSOI transconductance efficiency charts are shown to be predictable and generally invariant. This invariance, discussed in Chapter 3, can be used to predict the transconductance provided that W/L and level of inversion (i.e. IC) are given.

Moreover, with the additional chart of IC with respect to the gate voltage overdrive VGS -VTH noting that a bijective relation exists between the two inversion metrics, one can predict drain current provided that W/L, VTH, and gate voltage are provided. This can allow designers to predict MOSFET DC properties without the need of an analytical model including in MI which is difficult to capture.

For accurate integrated circuits simulations, model extraction is first based on I-V and C-V characteristics. Analog FoMs are compared with respect to measurements in DC and small signal low frequency operation. At the same time, in order to allow a simpler access to the different contributors to the small signal frequency operation, equivalent circuits are proposed. For higher frequency operation, the core device using either UTSOI2 model or the lumped small-signal equivalent circuit is gradually enriched to capture new parasitic and distribution / delay effects. One should be careful while using this simple equivalent circuit. Besides the lack of charge conservation in this equivalent circuit, it is only valid within the following assumptions:

• Transistor is used for amplification with the input signal entering to the gate terminal. The equivalent circuit cannot and should not be used to model a switch operation.

• The transistor configuration is common-source (CS).

• The coupling effect between drain and gate terminals is reciprocal which is rarely verified in saturation. In other words, one should verify that:

= = (2.28)
The last assumption is equivalent to assuming Cgdi = Cdgi and it is important but not always verified even at low frequency operation as shown in Fig. 2.19. In saturation for example, a variation of the drain terminal voltage will not produce any change on the gate terminal charge because of pinch-off and consequently the intrinsic capacitance is equal to zero Cdgi = 0. However, a variation of the gate terminal voltage will produce a variation on the channel charge, which will produce a variation on drain charge through channel conduction, and thus Cdgi ≠ 0. Fig. 2.19 shows the gate to drain transadmittance Y21 defined as the ratio of the two complex phasors representing the small current at the drain terminal and the small voltage at the gate terminal. Y21 expression is given by:

\ R ≡ ] ^_`ab%, d (2.29)
Because of the reciprocal drain-gate capacitance in Fig. 2.18, the simple equivalent circuit provides different results compared to a compact model where charge conservation is verified. The difference is even observed at low frequency and is maximum at high frequency. Therefore, the difference between the two capacitances Cgdi and Cdgi must be taken into account and modeled. At high frequency operation the reciprocal Cgdi and Cdgi assumption is no more valid and these two coupling quantities diverge more because of non-quasi-static effects. This will be discussed in Chapter 4.

In general, the electrostatic couplings between the MOSFET terminals are not reciprocal, and for the dynamic operation modeling, 16 transcapacitances are required to agree with the charge conservation rule. Recent MOSFET compact models such as UTSOI2 account for the charge conservation, and the 16 transcapacitances are provided as part of the simulators DC OP information as discussed in Section 2.5. The modeling of the non-reciprocal Cgd and Cdg capacitances effect can be done by adding an imaginary part Cm to the transconductance gm (i.e. in parallel to it in an equivalent circuit). The proposed equivalent circuit is augmented using a mutual capacitance between the drain and the source terminals. The mutual capacitance is defined as [START_REF] Tsividis | Operation and modeling of the MOS transistor[END_REF]:

= = - = = -= (2.30)
The new quasi static equivalent circuit is shown in Fig. The parameters of the equivalent circuit in Fig. 2.18 are extracted using measurements and compared with the calculated Leti-UTSOI2 counterparts as a first model validation step. This allows a quick sanity check of the Leti-UTSOI2 extracted parameters, and a verification of the consistency between the equivalent circuit parameters and Leti-UTSOI2 parameters. The equivalent circuit parameters are extracted using two measurement sets and compared:

• The ID-VG and ID-VD characteristics derivatives are used to extract the transconductances gm1 and gm2 as well as the conductance gds, and C-V measurements are used to extract the required capacitances.

• The S-parameters measurements discussed in Chapter 4 are de-embedded and transformed into Y-parameters before parameters extraction using the simple analytical expressions summarized in Table 4-1.

The comparison between the two last characterization sets helps to validate the measurements and to assess the dynamic operation through basic model parameters.

In particular the transconductance is compared based on DC (i.e. derivative if I-V characteristic) and S-parameters measurements (i.e. real part of Y21-Y12 at low frequency). In saturation, the model fine tuning requires an estimate of the structure environment thermal resistance in order to account for the self-heating effects that is inevitable in DC operation besides its low effect in comparison to classical SOI technologies. A summary diagram of the proposed extraction steps for DC and AC is given in Table 2-2. Some of the listed steps (i.e. related to long channel) are executed twice to take into account the interaction between the several effects such as the impact of the series resistance on the mobility. Low field mobility is extracted using

Normalization

In the following Section, when convenient, measured and simulated quantities are normalized as described in Table 2-3, unless otherwise stated.

I-V and C-V operations assessment

The DC and C-V operation is compared against measurements of short and long (L = 30 nm and 2 µm respectively) NMOS and PMOS devices. To be consistent with RF operation assessment, multi-finger structures are used. When convenient, such as in the case of capacitances plots, NMOS convention gate voltage overdrive Vgt = TYPE.(VGS -VTH) is used.

I-V operation assessment

Accurate transfer characteristic ID-VGS simulation is a critical condition for rigorous analog and RF modeling. Not only is the drain current accuracy required but also its first (transconductance) and second derivatives to estimate parasitic signal distortions in RF operation. Subthreshold slope is accurately captured in weak inversion for both long and short channels. In strong inversion, series resistance impact, length modulation as well as mobility saturation effects (noticeable even at low |VDS|) are correctly reproduced.

Model is also correctly describing the complex moderate inversion region. Smith chart and polar chart. The S-parameters are converted into Y-parameters and shown in Fig. 2.34 with respect to frequency. Both the proposed equivalent circuit and UTSOI2 provided comparable results. Considering the quasi-static assumption, both models are equivalent provided that intrinsic and extrinsic elements are extracted and accurately accounted for. The equivalent circuit parameters can be retrieved using measurements and can also be predicted using invariant charts that will be assessed in next Chapters. The comparison of the simulation of both equivalent circuit and UTSOI2 models to measured data shows a huge discrepancy at high frequency as discussed in the following. The DC and low frequency models are used to assess the high frequency behavior through Y-parameters. An equivalent of the transconductance at high frequency is the mutual transadmittance defined as:

C-V operation assessment

e = \ R -\ R (2.31)
where Y21 and Y12 are respectively the gate to drain transadmittance and the drain to gate transadmittance. At low frequency, the imaginary part of the complex ym tends to zero. Consequently, the modulus or the real part of ym is equal to the transconductance gm at low frequency. Re(y m ) (S)

Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V

Operating point information

Operating Point (OP) information is a set of parameters usually provided by SPICE simulators describing a device in steady-state condition. For a MOSFET, the information represents the unique equilibrium state at which the transistor settles when related bias conditions (i.e. DC voltages or currents) are held constant. The OP information is including terminal voltages and currents as well as small signal low frequency parameters (e.g. gm, gds, Cgd and Cgs). The DC OP analysis is an intermediate step towards further simulator analysis (e.g. AC, Transient, and Noise). Phase(y m ) (deg)

Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V
The DC OP information is used by analog designers for sizing purposes, in particular to know the state of the transistor and its operation regime. The feature is convenient in providing quickly the required information within the circuit context, without the need for characterizing the device separately. The OP Info feature was proposed in early SPICE simulators and has not changed since.

OP information inaccuracy for sub-circuit based MOSFETs

In this Section, we will present our proposal to enhance the simulators DC OP information feature. This proposal is already adopted by major EDA vendors.

Today, in a DC simulation, the OP information provided by circuit simulators only represents elementary components (i.e. intrinsic or core MOSFET, parasitic resistors and capacitors, etc.) separately. As the majority of RF MOSFET models are implemented using sub-circuits with various elements, almost no accurate information is retrieved for such complex RF devices based on simulators outputs. Moreover, simulators provide some parameters such as Cgs broken down into its components (i.e.

overlap capacitance, fringe capacitance, etc.). For bulk PSP standard model for instance, simulators provide more than 200 parameters as the OP information while executing a simple operating point analysis. The majority of these parameters are useless for analog designers and most likely important for model developers.

Therefore, designers run separate simulations to extract reliable information regarding steady-state conditions while working with RF MOSFETs. These attempts to find accurate OP information most likely distract designers from their design job. We propose a practical solution in the simulator side for all MOSFET types in such a way that the standard elementary information is replaced by the accurate equivalent one.

Enhancement proposal

We have worked on a proposal to help the simulator retrieve the required information for real devices. This solution is also used in our work to quickly assess high frequency MOSFET FoMs while simulating a Low Noise Amplifier (LNA) circuit (c.f Chapter 6).

A survey of various design groups within STMicroelectronics was carried out in order to define the required information for analog design. We came out with a specification, which is proposed to CMC for standardization. The proposed list is shown in The cost of the proposed solution is some additional simulation CPU time (tens of milliseconds per device). However, the feature is only required in analog circuits where only a few devices need to be sized and their OP information to be accurately known. Consequently, in classical analog circuits, the additional CPU time is negligible and acceptable as a cost for accurate OP information.

V GS V NMOS: V GS = V G -V S PMOS: V GS = V S -V G External gate-source DC voltage (with NMOS convention) V DS V NMOS: V DS = V D -V S PMOS: V DS = V S -V D External drain-source DC voltage (with NMOS convention) V SB V NMOS: V SB = Vs -V B PMOS: V SB = V B -V S External source-bulk DC voltage (with NMOS convention) Transconductances & MOSFET Conductance g m A/V ∂(I D )/∂(V G ) DC transconductance g mb A/V ∂(I D )/∂(V B ) DC bulk or back gate transconductance g ds A/V ∂(I D )/∂(V D ) DC output conductance MOSFET Transcapacitances C gd F -∂(Q G )/∂(V D ) AC Gate-Drain transcapacitance, including overlap capacitances C gs F -∂(Q G )/∂(V S ) AC Gate-Source transcapacitance, including overlap capacitances C gb F -∂(Q G )/∂(V B ) AC Gate-Bulk transcapacitance C ds F -∂(Q D )/∂(V S ) AC Drain-Source transcapacitance C dg F -∂(Q D )/∂(V G ) AC Drain-Gate transcapacitance C db F -∂(Q D )/∂(V B ) AC Drain-Bulk transcapacitance C sd F -∂(Q S )/∂(V D ) AC Source-Drain transcapacitance C sg F -∂(Q S )/∂(V G ) AC Source-Gate transcapacitance C sb F -∂(Q S )/∂(V B ) AC Source-Bulk transcapacitance C bd F -∂(Q B )/∂(V D ) AC Bulk-Drain transcapacitance C bg F -∂(Q B )/∂(V G ) AC Bulk-Gate transcapacitance C bs F -∂(Q B )/∂(V S ) AC Bulk-Source transcapacitance MOSFET Capacitances C gg F ∂(Q G )/∂(V G ) AC Gate capacitance (including overlap) C dd F ∂(Q D )/∂(V D ) AC Drain capacitance C ss F ∂(Q S )/∂(V S ) AC Source capacitance C bb F ∂(Q B )/∂(V B ) AC Bulk capacitance Derived parameters V TH V -
The background specific simulation involves DC and AC analysis types, and is run using the isolated device. The DC simulation is a simple sweep of VGS in order to extract the threshold voltage at a constant predefined current density. Three other VTH definitions are also used:

• gm_max based method where a linear extrapolation on ID-VGS characteristic from the maximum gm location is used.

• maximum δCgs/δVgs based method originating from a unified chargecontrol MOSFET model [START_REF] Park | A unified currentvoltage model for long-channel nMOSFETs[END_REF].

• maximum δ(gm/ID)/δVgs based method proposed in [START_REF] Flandre | Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold[END_REF] for bulk case.

The small signal AC simulation, with an applied small signal having a unit magnitude, is run at a default low frequency of 100 kHz, which can be modified by the user. Four instances of the same device are used with a small signal applied on each terminal in order to retrieve the 16 capacitances, the conductance, and the transconductance. The corresponding formulations are:

f = f = g h i2 f i = g h , 7 ≠ e = - = - g h |2 | = -g h , 7 = e (2.32)
where Cxy and Cxx are, respectively, the transcapacitances between x and y terminals and capacitance at terminal x. Im(ix) is the imaginary part of the AC current at terminal

x, and vy is the AC voltage applied at terminal y with a magnitude of 1.

= = - l&m/ h = i2 i = -l&m/ h = , n moo/h&B T! mT& U = p = - l&m/ h = |2 U | = -l&m/ h = ,
n moo/h&B T! qr/s !l qmts mT&

(2.33)
where VBS = VbG in the case of DG MOSFET.

= = = - l&m/ h = |2 = | = -l&m/ h = , n moo/h&B T! Blmh0 (2.34)
In SI, the saturation voltage is estimated using:

Q. u = 2 ' , (2.35)
(2.35) is used to estimate VDSAT for two geometries L = 2 µm and L = 100 nm. The result is shown in Fig. 2.39 and Fig. 2.41, respectively. For the long channel with less velocity saturation (e.g. L = 2 µm), the expression provides close results in SI to the definition of VDSAT proposed by Leti-UTSOI2. This is also evidenced in Fig. 2.40 using ID-VDS output characteristic. For WI, the expression underestimates the VDSAT, and a correction can be proposed in this region of operation: V DS (V)

Q.vu = 3 ' , ≈ 3-. ( 2
I D (A) V GS = 0.5 V V GS = 0.7 V V GS = 0.9 V V GS = 1 V Leti-UTSOI2 V DSAT for V GS = 1 V 2/(g m /I D ) for V GS = 1 V

Conclusion

The measured I-V and C-V characteristics of the UTBB FDSOI MOSFET have helped to gain more insight into the operation of an asymmetric double gate MOSFET.

In particular, the impact of the back gate voltage on the threshold voltage is assessed using both characteristics. Volume inversion phenomena is evidenced using measurements and reproduced using TCAD simulations on a simple and optimized decks. The electrostatic behavior, assessed through C-V simulations, is reproduced accurately using both simple and optimized decks. However, the transport model (i.e. V DS (V)

I D (A) V GS = 0.5 V V GS = 0.7 V V GS = 0.9 V V GS = 1 V 2/(g m /I D ) for V GS = 1 V Leti-UTSOI2 V DSAT for V GS = 1 V
mobility) is questionable as the invariance of the gm over ID characteristic is not reproduced using TCAD simulations. In the following, measurements will be our main reference and source of observation. TCAD simulations will be used carefully and compared with measurements. In recent low power and high performance circuits, it is crucial to operate MOSFET transistors all the way from weak to strong inversion levels [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF]. Furthermore, moderate inversion region has been found to be a good compromise while power consumption and speed are valued equally [START_REF] Mangla | Figure-of-merit for optimizing the currentefficiency of low-power RF circuits[END_REF][25] [15]. To benefit from the full potential of recent technologies especially in deep weak and strong inversion, efficient analog first-cut designs still rely on hand calculations. The traditional hand calculations involve simplified MOSFET transistor models that are assumed to be valid in the weak and the strong inversion regimes.

Unfortunately, the usual strong and weak inversion approximations fail to predict drain current (ID) in moderate inversion and there is no similar model that is simple enough for hand analysis and satisfactorily predictive in particular for multiple gate transistors [START_REF] Taur | A continuous, analytic drain-current model for DG MOSFETs[END_REF] [START_REF] Roy | Compact Modeling of Anomalous High-Frequency Behavior of MOSFET's Small-Signal NQS Parameters in Presence of Velocity Saturation[END_REF]. The situation is becoming worse with advanced and downscaled technologies where effective mobility, velocity saturation and series resistances are dominant at lower inversion levels. Consequently, the classical saturation and strong inversion approximation square law is only valid near to the onset of strong gm over ID invariance assessment inversion and inappropriate elsewhere. The transistors are therefore operated with less efficiency when traditional methods are used and this might lead to overdesign [START_REF] Daniel Foty | Starting Over: gm/Id-Based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies[END_REF].

The above out-of-date hand calculations practices are preventing analog designers from taking full advantage of modern technologies (high transconductance efficiency and low VDSAT). In order to address the weakness of the traditional procedures, where questionable concepts such as the early voltage, the gate voltage overdrive and the classical square law are used, the transconductance efficiency (gm/ID) based design methodology has been proposed [START_REF] Silveira | A g m/I D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA[END_REF]. The gm over ID approach relies on the fundamental and universal aspect of the transconductance efficiency versus normalized drain current curve in single gate MOSFETs. Such a plot is considered to be invariant regardless of threshold voltage and length considering short channel effects are negligible [START_REF] Silveira | A g m/I D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA[END_REF] [START_REF] Bucher | Scalable GM/I based MOSFET model[END_REF]. Should one be wary of taking the invariance assumption at face value while working with double gate MOSFETs?

The objective of this Chapter is to check the extent to which the gm over ID based design methodology referred to above is valid for advanced asymmetric double gate transistors such as the Fully Depleted SOI (FDSOI) Ultra-Thin Body and Box (UTBB) MOSFETs. The gm over ID design methodology is briefly explained in Section 3.2. In Section 3.3, TCAD simulations remind the back gate effect on the front gate transconductance efficiency already discussed in Chapter 2. The normalization of both transconductance efficiency and current for a double gate transistor is described in Section 3.4. In Section 3.5 the experimental setup is described and the transconductance efficiency versus the inversion coefficient (IC) chart invariance is assessed using obtained experimental data. Finally, a discussion on gm over ID invariance is presented in Section 3.6.

g m over I D based design methodology

The concept of transconductance efficiency (gm/ID) was introduced by Pullen [START_REF] Pullen | Transconductance efficiency[END_REF] and used in the context of the EKV MOST model [START_REF] Vittoz | Micropower Techniques[END_REF] [START_REF] Enz | An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications[END_REF]. The low-power design methodology using gm over ID versus normalized drain current was first demonstrated for an analog circuit design in [START_REF] Silveira | A g m/I D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA[END_REF]. The gm over ID analog design procedures were promoted by Binkley and other researchers since then [START_REF] Daniel Foty | Starting Over: gm/Id-Based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies[END_REF] [START_REF] Binkley | Design-oriented characterization of CMOS over the continuum of inversion level and channel length[END_REF]. gm/ID is strongly related to analog circuits performances (e.g. common source amplifier gain is directly linked to gm/ID). It is also an indication of the device operating region as it is equal to the derivative ∂ln(ID)/∂VG which is constant in weak inversion and decreasing in moderate inversion and strong inversion. Finally, gm/ID vs. normalized DC drain current curve is a tool for transistor dimensions calculation.

Using gm over ID based charts, the methodology allows accurate hand calculations in all MOSFET inversion levels including moderate inversion that is complex to model. The transistor geometry ratio (W/L) is determined once two values of the triplet (gm/ID, gm, ID) are calculated. ID, gm and Length are first chosen based on circuit design specifications (power consumption, higher gain or speed). In this first step, dedicated intrinsic gain and transit frequency versus normalized drain current charts with length as a parameter may be used as guides. Then gm over ID versus normalized drain current chart is used to determine the inversion level and calculate the required width. The gm/ID vs. gate voltage overdrive VG-VT curve is used to ensure MOSFET is in saturation.

The optimum inversion coefficient determined using recently proposed figure of merit gm.fT/ID can be used for an acceptable tradeoff between performance, power consumption, and speed [START_REF] Mangla | Figure-of-merit for optimizing the currentefficiency of low-power RF circuits[END_REF] [15]. The gm over ID methodology allows de facto the designer to consider level of inversion as an input rather than a consequence of the sizing. ) To gain further insight into the special behavior of the gm1/ID for a UTBB MOSFET, experimental data will be used in Section 3.5. The observed gradient mobility from front to back channel reported in [START_REF] Ohata | Mobility comparison between front and back channels in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors by the front-gate split capacitance-voltage method[END_REF][93] brings about additional ingredient to check out as gm/ID is linked to both electrostatic and transport according to:

Invariance unpredictability using TCAD

V bG = -4 V V bG = 0 V V bG = 5 V
= ln = 1 + 1 2 2 (3.1)
where Qinv and v are the mobile charge density and mobile velocity respectively.

Moreover, the invariance demonstrated using the model proposed in [START_REF] Sallese | A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism[END_REF] for the case of a symmetric DG MOSFET calls for a generalization to the asymmetric DG MOSFET studied here.

Transconductance efficiency and current normalizations

In this Chapter, the drain current is normalized to get an inversion coefficient (IC). The latter is defined as the square shape DC drain current I□ normalized by a technology current Ii comparable to the process dependent current defined in [START_REF] Binkley | Design-oriented characterization of CMOS over the continuum of inversion level and channel length[END_REF]: V G (V)

0 0.5 1 1.5 2 0.5 1 1.5 2 2.5 x 10 -14 V G (V) C gg (F) V bG = -4 V V bG = 0 V V bG = 5 V 0 0.5 1
dC gg /dV G (F/V) = □ = / 3/G (3.2)
where I□ is the square shape drain current ID/(W/L), i = 1 for the front gate technology current and i = 2 for the back gate technology current. Indeed, two technology currents can be defined for an asymmetric double gate MOSFET. IC will be used as the x-axis of the normalized MOSFET transconductance efficiency plots presented in Section 3.5.

The inversion coefficient concept was introduced by Vittoz [START_REF] Vittoz | Micropower Techniques[END_REF] and used in EKV model context [START_REF] Enz | An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications[END_REF]. In the transconductance efficiency versus normalized current I□ chart, as depicted in Fig. 3.3, the technology current Ii is located at the intersection of the weak inversion asymptote (Boltzmann limit) and the saturation strong inversion square law asymptote for a long MOSFET [START_REF] Vittoz | Micropower Techniques[END_REF]. Inversion coefficient concept is helpful to easily identify the MOSFET operating level of inversion. An analytical expression for the technology current similar to the one given in [START_REF] Binkley | Design-oriented characterization of CMOS over the continuum of inversion level and channel length[END_REF] cannot straightforwardly be derived for a double gate MOSFET as mobility, subthreshold slope and gate capacitance vary significantly with front and back gate voltages. Indeed, as has been proposed in [START_REF] Reyboz | Continuous model for independent double gate MOSFET[END_REF], the mobility is dependent on a coupling )

NMOS & V D = 1 V PMOS & V D = -1 V SI trend NMOS WI trend SI trend PMOS
inversion charges and a coupling charge associated to the coupling electrical field. An equivalent gate capacitance cannot be explicitly derived since two channels coexist. In [START_REF] Karatsori | Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control[END_REF] an equivalent gate capacitance is determined given the location of the effective conductive path, which in turn depends on front and back gate voltages. We propose to define an equivalent expression of the technology current which is related to both gates:

= 2 • M , U • -. (3.3)
where βi (i = 1 or i = 2) are two functions of both front and back gate voltages. In saturation and in the case of front channel inversion with back channel in weak inversion the β1 becomes equal to n1.Cox1.µ1 provided that the front coupling factor n1 in [START_REF] Reyboz | Continuous model for independent double gate MOSFET[END_REF] is rather considered in strong inversion too. Cox1 and µ1 are front oxide capacitance and front channel mobility respectively.

In asymmetric double gate transistors, two transconductance efficiencies can be defined according to the gate used for the input signal. Consequently, for a long channel, front and back transconductance efficiencies are normalized to their maximum values 1/(n1.UT) and 1/(n2.UT) respectively, which is reached in weak inversion. The analyzed figure of merit becomes: FoMi = ni.UT.gmi/ID where gmi is front or back transconductance. Although gm/ID ratio reaches its maximum in deep weak inversion, the normalization factor (and consequently ni value) is extracted at a higher level of current just before the onset of the moderate inversion. Ii is defined as the square shape current where the strong inversion asymptote and the weak inversion plateau intersect.

The normalization parameters for each gate Ii and ni are taken to be intrinsic and unvarying constants for a MOSFET type. Consequently, the transconductance efficiency and ID can simply be obtained from the normalized charts by multiplying the corresponding normalized quantities (values on y-axis and x-axis) by 1/(ni.UT) and

Ii.(W/L) respectively.

Experimental results

This work was carried out using UTBB FDSOI MOSFETs implemented in a commercial 28 nm technology processed at STMicroelectronics. More details on the process can be found in [3]. The gate length and gate width of both measured N- As shown in Fig. 3.3, at a temperature of 25°C, the high subthreshold slope of the UTBB FDSOI transistors provides a maximum value of gm1/ID of about 36 V -1 for both NMOS and PMOS which corresponds to a near ideal subthreshold slope.

The extracted n1 and I1 values for long NMOS and PMOS in saturation with grounded back gate are given in Table 3-1. It should be noted that I1 is not located in the center of the moderate inversion but rather in its upper part at one decade before the strong inversion region. The ratio of NMOS and PMOS technology currents compares to the ratio of electron and hole mobility. Both weak and strong inversion asymptotes overpredict transconductance efficiency at the technology current I1 by more than 60%.

V bG = -4 V V bG = -3 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 3 V V bG = 4 V V bG =
4 4 R = R + + • R ≈ 2 • R = 1 (3.4)
where Csi, Cox2 and µ2 are silicon film capacitance, back oxide or box capacitance and back channel mobility respectively. Unlike the front transconductance efficiency case, the front gate voltage has a considerable impact on the volume inversion and Front gate and back gate transconductance efficiency curves support that transconductance efficiency is maximized when charge carriers are not confined near the two interfaces but rather occupy the silicon film volume with a weaker transversal electrical field. This optimistic condition is obtained for certain combinations of front and back gate voltages (VG, VbG). In order to sustain this convenient state, front and back gates are swept simultaneously with a fixed voltage offset. This configuration can more easily be realized in design rather than sweeping the gates with a multiplication factor. Fig. 3.9 shows experimental transconductance efficiency curves where an ideal subthreshold slope is achieved for all offset values. (deep strong inversion). Such behavior is not significant for longer devices. The short channel impact will be assessed in the following section. )

V G = -0.3 V V G = -0.225 V V G = -0.15 V V G = -0.075 V V G = 0 V V G = 0.075 V V G = 0.15 V V G = 0.225 V V G = 0.3 V SI trend WI trend
V bG = 0 V V bG = V G V bG = V G + 1 V V bG = V G + 2 V V bG = V G + 3 V V bG = V G + 4 V V bG = V G + 5 V

Short channels

As shown in the previous plots for long transistors, transconductance efficiency is constant and maximum in weak inversion, decreases rather slowly in moderate inversion, and decreases as the inverse square-root of IC in strong inversion.

At the onset of strong inversion, transconductance efficiency is 70 % lower than its maximum value. Strong inversion degradation ceases when carrier's velocity saturates completely and a ~1/IC dependence is obtained. An additional degradation with respect to the linear asymptote (~1/IC) occurs when series resistance and mobility degradation add to velocity saturation for short channel transistors.

The long transistor unique chart can be used in weak and moderate inversion to predict transconductance efficiency for all transistors with a length greater than 120 nm while error is kept lower than 5 %. To assess back gate voltage effect for a short channel MOSFET, the normalized gm1 over ID is shown in Fig. 3.13 for L = 30 nm. The transconductance efficiency in weak inversion varies within 20 % across the entire range of back gate voltage conditions (from -4 V to 5 V). This spread is due to the short channel effects and the relative sensitivity of the subthreshold slope to back gate voltage. In Fig. 3.14, transconductance efficiency versus IC chart is measured for different temperatures.

For short channel MOSFET, the chart varies with a low rate (less than 0.1 % per degree Celsius).

V bG = -4 V V bG = -3 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 3 V V bG = 4 V V bG =

Drain to source voltage

The concept of gm/ID invariance should only be used in saturation regime and it is worth assessing the limit of drain potential below which the invariant breaks down in the onset of strong inversion. This information is useful in modern low-voltage lowpower design since high transconductance efficiency is obtained in moderate inversion with lower drain to source saturation voltage VDSAT.

Sensitivity to manufacturing process variations

To check how sensitive transconductance efficiency versus inversion coefficient chart is to manufacturing process variations, foundry process based UTSOI model [START_REF] Ghouli | Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model[END_REF], has been used to plot three normalized transconductance efficiency characteristics versus IC. The characteristics correspond to the typical (TT), fast (FF) and slow (SS) corners. As shown in Fig. 3.16, the three corners charts practically

V D = 0.05 V V D = 0.15 V V D = 0.25 V V D = 0.35 V V D = 0.45 V V D = 0.55 V V D = 0.65 V V D = 0.75 V V D = 0.85 V V D = 0.95 V V D = 1.05 V V D = 1.2 V SI trend WI trend SILIN trend
overlay and a maximum error of 4.5 % is obtained in deep strong inversion and less than 1.6 % error is made across the range of weak and moderate inversion (inset in Fig. 3.16).

Discussion on g m over I D invariance

The transconductance efficiency clearly benefits from volume inversion apparent mobility comprehended as enhanced back channel mobility in [92] [93]. The optimum transconductance efficiency for a double gate MOSFET is obtained thanks to an enhanced mobility at low transverse field corresponding to a pronounced volume inversion. This is characterized by a higher carrier density in the center of the silicon film and a weak transverse electrical field. In this case, both effective mobility and gate capacitance are high and the corresponding technology current is boosted. For a back gate voltage of 2 V, a maximum transconductance efficiency is obtained at IC = 4 in Fig. 3.6 where fT.gm/ID figure of merit found to be optimal [82][110]. On the one hand, enhanced volume mobility helps to regain transconductance efficiency when back channel is inverted first (high VbG) with lower front capacitance. On the other hand, the high capacitance, when only front channel inversion occurs, helps to partially recover the effect of degraded mobility on transconductance efficiency (low VbG). Consequently, gm/ID vs. IC charts for different back gate voltages (from VbG = -2 V to 2 V) can be approximated using a universal chart with an acceptable error of 4%. The back gate voltage degree of freedom offered in asymmetric double gate transistors does not prevent design using gm1/ID vs. IC chart especially in moderate inversion.

The transconductance efficiency versus IC chart determined using a typical long channel MOSFET at 25 ºC shows negligible sensitivity to temperature and process variations. The chart is invariant and rather insensitive to drain to source voltage as long as the transistor is in saturation. The minimum channel length for the chart invariance assumption is L = 120 nm. For NMOS, velocity saturation effects become significant in moderate inversion for L < 100 nm and chart cannot be used. However, a short channel chart might be considered as back gate voltage and temperature still have a relatively low impact at shorter MOSFETs. For PMOS, less subject to velocity saturation effects, shorter transistors can be sized using a unique PMOS chart.

Conclusion

In this Chapter, the universal aspect of the relationship between the transconductance efficiency (gm/ID) and the inversion coefficient (IC) has been investigated. We have shown that a unique chart can be exploited for the asymmetric As previously shown in Fig. 2.35, at high frequency operation the amplification capability of the transistor tends to decrease and the quasi-static models are enable to reproduce this behavior. Not only the mutual transadmittance ym acquire an imaginary part, but also the real and imaginary parts decrease in magnitude and the phase shift increases. This phenomena is observed for all geometries and bias conditions, in particular for long channel devices. The phase shift of ym means that the voltage excitation at the gate terminal lags behind the generated current at the drain terminal.

This delay is due to the distributed effects that are taking place in the MOSFET structure and that are not modeled neither in the equivalent circuit of Fig. 2.

nor in

Leti-UTSOI2 compact model. In this Chapter, the RF and mm-Wave characterization method is briefly described and modeling solutions are proposed for the intrinsic and extrinsic parts of the UTBB FDSOI structures. The proposed model is finally validated using measurements up to 110 GHz. In the high frequency measurements, a network is referred to as an n-port structure where a port means an electrical connection allowing power to be transmitted, and every port is terminated by a certain impedance. In practice all ports are terminated using 50 Ω resistors. 2-port measurements are more common mainly for economic reasons. In the last years, multi-port VNA along with multi-port test sets were introduced for multi-port DUT characterization [START_REF] Ruttan | Multiport VNA measurement[END_REF].

RF and mm-Wave characterization

In this work, the standard 2-port measurement setup shown in Fig.

De-embedding:

In order to get rid of the detrimental structure pad parasitic elements and extend the reference plane to the inner DUT, another important operation is executed after measurements. This operation is called de-embedding and is taking the measured S-parameters as a starting point for mainly two mathematical operations. The main pad parasitic elements are in parallel with the pads as depicted in Fig. The calibration and de-embedding procedures do not get rid of the extrinsic parasitic elements of the DUT itself such as the gate resistance, the series source and drain resistances, the overlap and inner fringing capacitances, and the bulk or back gate resistance. All these series and parallel parasitic elements have detrimental impact on the MOSFET high frequency performance, especially gate resistance [START_REF] Schwierz | RF transistors: Recent developments and roadmap toward terahertz applications[END_REF].

All these remaining parasitic elements need to be modeled carefully.

In order to extract the equivalent circuit parameters, the following expressions are used:

Small signal component Expression

Gate resistance in SI (R G )

{ = {& \ RR |R Gate to drain capacitance (C gd ) = = - g \ R } Drain to gate capacitance (C dg ) = = - g \ R } Transconductance at low frequency g m = {&~\ R -\ R • = |\ R -\ R |
Front gate to source and bulk capacitance (C gs +C gb )

+ U = g~\ RR • } -= Output conductance (g ds ) = = {&~\ + \ R •
Drain to source and back gate capacitance 180°+90° noting that phase continues to decrease even beyond the -180° and discontinuities in the plots are only due to the phase axis unit convention). The critical frequency depends on VGS and consequently on the channel inversion level. For long channel devices, the critical frequency is lower for lower inversion levels. However, for short channel devices, the ym phase decreases faster for stronger levels of inversion (i.e. Fcrit is lower for SI) as shown in Fig. 4.5 although subtle. Two distribution effects are competing in a MOSFET structure: (1) the non-quasi-static (NQS) effect due to the longer channel [START_REF] Sallese | A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation[END_REF], and (2) the longitudinal distribution effect due to the longer gate fingers [START_REF] Jindal | Noise associated with distributed resistance of MOSFET gate structures in integrated circuits[END_REF]. These two effects are represented in Fig. 4.6. Phase(y m ) (deg) Phase(y m ) (deg)

(C sd +C bd ) = + U= = g \ } -= Mutual capacitance (C m ) C m = C dg -C gd

High frequency operation modeling

|y m | (S) V GS = 0.4 V V GS = 0.5 V V GS = 0.6 V V GS = 0.7 V V GS = 0.8 V V GS = 0.9 V V GS = 1 V
V GS = 0.4 V V GS = 0.5 V V GS = 0.6 V V GS = 0.7 V V GS = 0.8 V V GS = 0.9 V V GS = 1 V
V GS = 0.3 V V GS = 0.4 V V GS = 0.5 V V GS = 0.6 V V GS = 0.7 V V GS = 0.8 V V GS = 0.9 V V GS = 1 V
The two competing effects (1) and ( 2) will be modeled gradually in the following Sections. For DC and low frequency operation, no gate resistance is required as the gate leakage current is very low (i.e. typically lower than 10 nA/µm 2 ). However, for high frequency operation, the gate resistance should be taken into account, noting that high dynamic (AC) current is generated at the gate terminal. Moreover, the gate resistance in series with the gate capacitance will contribute a pole in the transadmittance function, and this will decrease the transadmittance modulus as shown in Fig. 4.4.

Simplified front and back Gates models

For high frequency operation, it is required to have a scalable model for the front gate resistance RG similar to the PSP standard model [START_REF] Smit | PSP 103.3 User's manual[END_REF] and for the back gate

{ = 1 € • '{ ƒ" ƒ + { … . 3 • † × G + { ƒ . 1 G × 3 • = 1 € • { ƒ" ƒ + { …. + { ƒ. (4.1)
where Rcontact is the one side gate finger access contacts resistance, Rsh is the horizontal sheet resistance and Rint is the interface vertical resistance. Wf and Nf are the gate finger width and the number of fingers, respectively. η is equal to 3 for a singleside connected gate and is equal to 12 for a double-side connected gate.

{ U = { U … × 1 ‰ U "ƒ> (4.2)
In order to extract RG and RbG related parameters, de-embedded S-parameters are transformed into Y-parameters and the two expressions (4.3) and (4.4) are used in high frequency operation:

{ = {& \ RR |R (4.3)
On the one hand (4.3) is used to calculate the effective high frequency front gate resistance. On the other hand the following expression is used to extract the back gate resistance. The expression is the well-known Mason's Unilateral Gain that is sensitive to RbG:

-= |\ R -\ R | 4. {&m/ \ RR . {&m/ \ -{&m/ \ R . {&m/ \ R (4.4)
Transconductance is extracted in DC using drain current derivative and also in RF using the modulus or real part of the mutual transadmittance ym = Y21-Y12. It is important to point out that in low-frequency, the two quantities must be equal and should diverge at high frequency operation as the effective transconductance and consequently gain decreases with frequency increase.

Although the proposed model in Fig. 4.8 reproduces accurately the high frequency behavior for short channel devices with mitigated NQS effects, the model fails to reproduce high frequency measurements for a long channel device. Fig. 4.9

shows the measured and simulated real part of the transadmittance with respect to frequency. The gate resistance in series with Cgg adds a pole to the transadmittance but the critical frequency dependence on VGS is not captured correctly. The gate resistance tuning provides enhanced trend only for a given inversion level as shown in Fig. 4.10 where SI decrease is captured up to 10 GHz but not predicted for lower inversion levels. Moreover, the modulus of the current gain HDG shown in Fig. 4.11 is not predicted with a quasi-static model for high frequency operation although the transit frequency extracted using the slope at low frequency is correctly captured using same curves. A model valid for non-quasi-static operation is therefore required. In particular, the NQS effect will add poles and zeros to the transadmittance characteristic and thus will mitigate the accelerated decrease observed in the simulations shown in Fig. 4.9 [START_REF] Sallese | A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation[END_REF].

Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V
Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V

Channel segmentation

At high frequency operation, charge carriers inertia in a long channel limits the device performance and induces admittance and transadmittance phase shifts. The channel can be viewed as a transmission line at high frequency and should be modeled accordingly. An accurate and physically based charge model for NQS effects has been proposed by Sallese [START_REF] Sallese | A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation[END_REF] based on Bessel functions. Other NQS formulations based on spline collation method are also proposed [START_REF] Wang | Quasi-static and nonquasi-static compact mosfet models based on symmetric linearization of the bulk and inversion charges[END_REF] [START_REF] Aarts | A PSP-Based Small-Signal MOSFET Model for Both Quasi-Static and Nonquasi-Static Operations[END_REF]. However, the proposed models are valid for small signal analysis only (i.e. no time domain transient) or difficult to efficiently implement on top of the proposed models unless a simplification is used (need of additional nodes). Several simplified NQS models are also proposed in the literature to capture the first order and used in standard models such as the relaxation time approximation (RTA) based method or the widely used Elmore model [START_REF] Zhu | Accurate RTA-Based Nonquasi-Static MOSFET Model for RF and Mixed-Signal Simulations[END_REF] [START_REF] Elmore | The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers[END_REF].

However, these simplified models are only valid up to a maximum of 1 to 2 fT. The segmentation of the channel proposed in [START_REF] Scholten | A large signal non-quasi-static MOS model for RF circuit simulation[END_REF] is adapted to the UTBB FDSOI architecture and used for NQS modeling. The method is valid for small signal as well

V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V
as large signal analysis, in frequency and time domains. The MOSFET device channel is split into several segments. Each segment is modeled using UTSOI2 or the equivalent quasi-static circuit. Only 5 elements provided accurate results with respect to measurements and chosen as a tradeoff between accuracy and computational time.

The decomposition is shown in Fig. 4.12 where all segments have same model

Complete front and back gates model

Clearly, low and high frequency MOSFET behavior is strongly impacted by its parasitic elements. Unfortunately, the majority of standard models of CMOS MOSFET including UTSOI2 do not completely include extrinsic elements such as gate and substrate resistances required for high frequency operation. Only simplified and fixed parasitic elements are occasionally used but inappropriate in a scalable MOSFET layout. The augmented model in Fig. 4.13 predicts correctly MOSFET behavior of UTBB FDSOI MOSFET provided that fringe capacitance in series with the gate resistance are both tuned in order to reproduce an additional pole to the transadmittance function. In Chapter 5, it is evidenced that the two distribution phenomena represented in Fig. 4.6 are competing and should be modeled. The two phenomena namely channel NQS and gate distribution effect are confused in some research works noting that the consequence of the two effects on the Y-parameters are comparable. On the one hand the NQS effect adds zeros and poles to the transadmittance characteristic as demonstrated in [START_REF] Sallese | A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation[END_REF]. On the other hand, according to Fig. 4.7, the gate contacts resistance and the horizontal salicide resistance (i.e. Rcontact + RshT) in series with the top fringing capacitance (i.e. from gate salicide top area to the source and drain contacts) form a series RC circuit and consequently contributes a pole in the transadmittance characteristic. Another pole is also added by the series combination of the physical gate resistance RG (i.e. Rcontact + RshT + RintT) and the gate capacitance Cgg. This explains why channel NQS effect is sometimes modeled using an RC gate network provided that a parallel RC circuit is added to emulate the NQS zeros [START_REF] Mohamed | Compact modeling of nonquasi-static effect in bulk MOSFETs for RF circuit design in sub-THz regime[END_REF].

The model in Fig. 4.13 reproduces correctly the low frequency gate capacitance Cgg (i.e. Im(Y11)/2πF)and gate resistance Rgg (i.e. Re(1/Y11)) especially in SI for a long channel as depicted in Fig. 4.14. However, at high frequency, an additional pole is required to capture the Rgg decrease especially for WI regime. Moreover, an additional gate capacitance contribution is required in order to capture the capacitance increase at high frequency. The constant additional capacitance will be also beneficial for the WI regime where extrinsic capacitors dominate. This additional pole is generated using an extrinsic fringing finger-length dependent capacitance Cfrls+Cfrld between the top salicided area of the gate and source/drain contacts. Based on the measured Rgg and Cgg characteristics in Fig. 4.14, the decrease in the gate time constant Rgg.Cgg tends to saturate because of a pole-zero compensation phenomena at high frequency.

The additional modeled pole (i.e. the one generated with the additional Cfrls+Cfrld capacitance) will be compensated using a parallel RC circuit. A capacitance Cdge will be added in parallel to the Rcontact + RshT resistance. Another parallel RC circuit is also added to mitigate the pole generated by the series Rg and Cgg. The series and parallel RC based front gate network developed using the pole-zero compensation technique is also convenient to model the gate distribution effect of short channels where the channel NQS effect contribution is mitigated. In summary, besides the NQS effect modeled using segmentation of the channel, the gate distributed effect must be modeled using series and parallel RC network. The front gate network is summarized in Fig. 4.15. In addition to the overlap capacitances included in the core MOSFET model, the gate network accounts for the lateral fringing capacitance (i.e. CfrwS+CfrwD) which is mainly dependent on the MOSFET width (i.e. finger length) [START_REF] Dormieu | Revisited RF Compact Model of Gate Resistance Suitable for High-K/Metal Gate Technology[END_REF].

Rgg (Ω) Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V

RF and mm-Wave FoMs assessment

In order to validate the proposed model in Fig. 4.16, characterization based on DC and HF measurements has been performed starting with the flow described in Chapter 2 for a DC and low frequency model with a simplified front and back gates as shown in Fig. 4.13. The front and back gates networks parameters are then optimized on several geometries with various form factors (Wf/L). The gate network also accounts for the number of the access sides (1 or 2) depicted in Fig. 4.17 as it highly impacts the gate distributed effect. In particular, connection to the gate terminal from two opposite sides tremendously reduces the gate distribution effect and this is taken into account.

Device performance is also impacted by device layout. In particular, the number of fingers and the back gate access through dedicated straps are also accounted for as seen in the previous section. where the phase shift is shown with respect to frequency although the gate distribution effect, optimized for a larger width, is overestimating the phase shift in WI. However starting from the MI, the phase shift is accurately predicted even beyond the antiphase shift (i.e. phase < -180°). Re(y m ) (S) F (Hz) Moreover, the transit frequency fT is correctly captured in saturation mode for both long and short channels as shown in Fig. 4.25 with respect to the inversion coefficient IC defined in the previous Chapter. The high frequency performance is reproduced for all levels of inversion in particular for L < 1 µm although, for L = 1 µm the performance in WI is decently captured but not useful for RF applications.

Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V (a)
Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V (a)
Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V
Im(y m ) (S) Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V
Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V

Mason's gain and maximum oscillation frequency FoM

fT alone is not sufficient to assess MOSFET performance at high frequency operation as it does not account for the impact of some important parasitic elements such as the gate resistance. fmax however, defined as the frequency at which the extrapolated Mason's gain given by expression (4.4) drops to unity, is a more suitable FoM for RF analog applications such as microwave amplifiers. Both front gate and back gate resistances impact is accounted for and evidenced using fmax FoM vs. Id.

Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V Slope < -
Mason (n.u.) Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V
Mason (n.u.) Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V

Conclusion

In this Chapter we demonstrate that the proposed high frequency non-quasistatic model is well-suited for modeling UTBB FDSOI NMOS and PMOS RF and mm-Wave devices. Characterization conditions include length scaling down to nominal (RFIC) thanks to the geometry down-scaling. As seen in Chapter 1, critical issues related to short-channel effects have been mitigated using innovative architectures coupled with new materials [14]. The new architectures allow for higher level of integration and higher frequency operation of the CMOS technology. For analog and RF applications, the UTBB FDSOI technology has proven to be relevant, especially when power consumption matters [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. UTBB FDSOI MOSFETs exhibit high analog and RF performances thanks to the reduced parasitic capacitances and resistances.

Moreover, the independent back gate allows threshold voltage and channel mobility controls [41][127].

In this Chapter, the UTBB FDSOI MOSFET transconductance efficiency is generalized and studied at high frequency for different channel inversion levels. The an onset frequency of the channel NQS effect is defined and compared with transit frequency in Section 5.5. The mobility in the silicon film is assessed using a novel method based on high frequency measurements after the compensation of the distributed gate effects in Section 5.7. Finally, discussion and conclusion are presented in Section 5.8 and 5.9, respectively.

Device description and characterization

Measured UTBB FDSOI MOSFETs were processed at STMicroelectronics. Si film, BOX and equivalent gate oxide thicknesses are 7 nm, 25 nm and 1.3 nm, respectively. More details on the process can be found in [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. DC and C-V

Frequency dependence of the Transadmittance efficiency in long channel UTBB FD SOI MOSFETs

In [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF], we have shown that the invariance of the transconductance efficiency, a wellknown feature of bulk MOSFETs, remains valid for UTBB FD SOI MOSFETs despite these devices are controlled by two independent gates. This finding was not expected and constituted a major result per se. Besides the detrimental impact of the high channel inversion level upon the transconductance efficiency, this trend is amplified with NQS operation, as shown in reporting the measured transadmittance efficiency modulus versus IC and operation frequency (F) (cf. Fig. 5.1). On the other hand, a compact modeling approach to NQS operation of bulk MOSFETs was derived in [START_REF] Sallese | A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation[END_REF], and a full dimensionless representation of a normalized transadmittance with respect to a normalized frequency led to a unique curve in the frequency domain [START_REF] Porret | A compact non-quasi-static extension of a charge-based MOS model[END_REF] that could be used as a powerful abacus.

In this respect, we propose to investigate the front and back gates high frequency NQS behavior, and verify if this fundamental result still holds for UTBB FDSOI MOSFETs.

As for the gm/ID figure of merit [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF], we define the transadmittance efficiency as:

•• = e = e '' -e '' (5.1)
where ymi is the mutual transadmittance defined as the difference between the gateto-drain and drain-to-gate transadmittances, i.e. ydg and ygd respectively, ID is the DC drain current and IC is the inversion coefficient defined as [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]: where L, W and Ispec are respectively the MOSFET length, width, and the 28 nm FDSOI technology current estimated for the front gate at Ispec = I1 = 0.7028 µA when assuming W=L [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF].

= 3 G • ?> (5.
The transadmittance efficiency is a generalization of the transconductance efficiency defined at low frequency operation. At high frequency, the front or back gate transconductance is an imaginary number with a magnitude and phase. Since gmi represents the mutual interaction between the gate and drain [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF], ymi keeps the same meaning even for high frequency (note that ymi reverts to gmi at low frequency). It should be noted that the capacitive coupling attributed to Cgd, which dominates yDG at high frequency, is ignored in the definition of ymi, as yGD ≈ -jωCgd [START_REF] Tsividis | Operation and modeling of the MOS transistor[END_REF] in the low frequency limit. Then, gmi and ymi assess the gate control of the intrinsic MOSFET channel. At low frequency (quasi-static operation) we have [START_REF] Tsividis | Operation and modeling of the MOS transistor[END_REF]:

= l&m/ e = |e | (5.3)
At any frequency, the ymi/ID FoM determines the gain and phase shift for a given DC current ID. The evolution of the Transadmittance efficiency versus frequency provides a very valuable insight in terms of power performances and efficiency at high frequency in presence of NQS effects.

As shown in Fig. 5.1, at high frequency, the NQS operation degrades the efficiency expected at low frequency, and in particular for weak and moderate inversion (IC < 10). This is also illustrated in This FoM is more realistic than the previously defined fT.gm/ID in [START_REF] Shameli | Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study[END_REF] since it does not assume that the transconductance vanishes beyond fT and does not underestimate performance in WI. In WI, fT is underestimating the onset of non-quasi static operation, i.e. the high frequency capability, since FNQS is a NQS critical frequency defined in Section 5.5. Actually, if we replace fT by the NQS critical frequency FNQS defined either in relations (5.19) or (5.20), the resulting FoM is higher in WI. Moreover, in contradiction to the previously reported conclusions such as in [START_REF] Shameli | Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study[END_REF], the optimum is now located in SI for long channels, and no longer in moderate inversion. For shorter devices, the optimum is still located in MI, as already reported using the fT.gm/ID FoM. Exact small signal analytical expressions for NQS operation are presented in [START_REF] Sallese | A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation[END_REF] for single gate bulk MOSFETs and simplified in [START_REF] Porret | A compact non-quasi-static extension of a charge-based MOS model[END_REF] to derive a compact model.

The critical frequency Fcrit expression, which corresponds to the first pole of the frequency characteristic of the device, as a function of the inversion coefficient IC concept redefined in [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF] for a DG UTBB FDSOI MOSFET is:

F ˜ ƒ = 1 2™ 15 4 • 4-. G • 2 + 6 + 3 oe + 1 4 + 4 ' oe + 1 4 ˆ• 1 + 2 + 3 oe + 1 4
(5.5)

≈ 15 4™ × 4-. G • √ in SI (5.6)
where µ and UT are respectively the effective mobility and the thermal voltage. (5.6) is an approximation of (5.5) while neglecting smaller terms in strong inversion, with less than 1 % error on Fcrit for IC > 2.

The model reported in [START_REF] Porret | A compact non-quasi-static extension of a charge-based MOS model[END_REF] proposed a frequency normalization scheme using the first pole obtained from the first order approximation of the NQS model of bulk MOSFETs.

It should be noted that Fcrit is proportional to the effective mobility and UT, inversely proportional to the square of gate length and accounts for the dependence of NQS on the inversion coefficient IC. This critical NQS frequency will be used for frequency normalization hereafter.

The transadmittance efficiency in saturation is derived from [START_REF] Porret | A compact non-quasi-static extension of a charge-based MOS model[END_REF] as :

e R = R ¢ ˜ ƒ , (5.7)
where gm1 is the low frequency front gate transconductance, ID is the DC drain current, F is the operation frequency, Fcrit is given in (5.5), and ξm is a NQS small-signal function based on the first kind Bessel functions. Defining the critical time as:

£ ˜ ƒ = 1 2™ • ˜ ƒ (5.8)
An approximation of (5.7) using the first pole of ξm becomes:

e R = R 1 1 + ¤}£ ˜ ƒ (5.9)
where ω is the angular frequency (=2πF).

In Fig. 5.5, a normalized magnitude of the transadmittance efficiency (|ym1|/ID)norm is shown for various values of IC versus the normalized frequency Fnorm1:

˜ R = ˜ ƒ
(5.10)

In addition, a further normalization of |ym1|/ID is applied using the low frequency transconductance efficiency gm1/ID as follows:

' |e R | ˆ ˜ = ' |e R | ˆ/ R / (5.11)
All normalized moduli plotted in Fig. 5.5 from weak to strong inversion are almost superposed as a result of the frequency normalization in (5.10) (despite the very high frequency disturbance of the parasitic elements). The invariance is also evidenced for the phase in Fig. 5.6 up to a phase shift as large as 270°. These results are of prime importance for modeling NQS effects in UTBB SOI FETs. For the first time, a simple but powerful analytical model can predict the gate transconductance, magnitude and phase, during highly non static operation of the intrinsic channel and in all the regions of operation. Additional normalizations in terms of the inversion coefficient and critical frequency were used to derive a kind of abacus, paving the way to a simple and efficient HF design methodology where device parameters, biasing conditions and frequency are treated on the same ground.

Impact of distributed effects along the gate on NQS

In this Section and Section 5.5, we will investigate the breakdown of the normalized transadmittance efficiency invariance shown in Section 5.3. In particular, we will study the impact of both the distributed effects along the gate and mobility variation (Section 5.7) on the critical frequency Fcrit used for normalization.

A closer look at the curves in the constant mobility normalization depicted in Fig. 5.6 reveals that in SI regime the transadmittance efficiency decreases earlier than in WI while frequency increases. This means that the transadmittance efficiency lags behind the gate voltage excitation in an enhanced manner. This enhanced phase shift in SI can be explained by a decrease in the mobility or an additional delay caused by the gate distributed effect. In our previous normalizations (Fig. 5.5 and Fig. 5.6), the delay generated by the 1 µm gate finger length (gate width) was not taken into account.

At high frequency, the gate can be considered as a transmission line because of the limited electromagnetic wave velocity along the gate finger length. An estimation of the time constant of the distributed gate finger is given by [START_REF] Hasani | Analysis and modeling of a MOS transistor with long gate finger for millimeter wave band applications[END_REF]:

£ = { (5.12)
where Rgg and Cgg are gate resistance and average gate capacitance respectively. It should be noted that Cgg depends on the level of inversion, which could explain the lower critical frequency in SI case when gate distributed effect is important. Conversely, in weak inversion Cgg is lower and a higher critical frequency is expected. According to [START_REF] Razavi | Impact of distributed gate resistance on the performance of MOS devices[END_REF][117], we have:

{ = { † (5.13)
where η is equal to 3 for a single-side connected gate and is equal to 12 for a doubleside connected gate. Rg is the resistance of the MOSFET finger at low frequency (i.e.

without the distributed effect) and extracted in SI. If we consider the additional pole due to the gate distributed effect, the total time constant can be expressed as:

£ ƒ ƒ = £ ˜ ƒ + £ (5.14)
This time constant includes both distributed effects occurring along the channel (i.e.

NQS) and through the gate. Thus, the new critical frequency is given by:

ƒ ƒ = 1 2™ • :£ ˜ ƒ + £ < (5.15)
Finally, neglecting the higher order term in the denominator and using the same approach, the transadmittance efficiency expression given in (5.9) becomes:

e R ≈ % 1 1 + ¤}:£ ˜ ƒ + £ < (5.16)
In order to include the distributed gate delay in the normalization scheme, a new frequency normalization is also used, still considering a constant mobility. The normalized frequency considering both non static transport (channel and distributed gate) is now given by:

˜ = ƒ ƒ
(5.17)

Considering the error on the frequency prediction at a given phase shift, for L = 1 µm, the normalization using Fnorm2 (not shown here) results in a discrepancy of the predicted frequency for a 45° phase shift of less than 15 % (5 % enhancement versus Fig. 5.6) as gate distributed effects are less important in comparison to NQS effect. This residual discrepancy could be explained by a mobility varying versus IC, which would be estimated at about 15 % between WI and SI for a long channel (i.e. L = 1 µm). Conversely, the error on the phase shift prediction for a given frequency is less than 6 %.

For L = 300 nm, the normalization using either Fcrit or Ftot leads to similar conclusions as for the L = 1 µm case. Fig. 5.7 shows the phase shift for L = 300 nm MOSFET versus frequency. Based on the apparent critical frequency, the dominant distributed effect is the channel NQS. In Fig. 5.8, the frequency is normalized using Fnorm1 to account for the channel NQS effect. Clearly, the gate distributed effect is evidenced since a higher inversion coefficient is responsible for earlier more pronounced phase shift. This behavior cannot be attributed to the channel where higher IC moves the phase shift to higher frequencies. In Fig. 5.9, a second normalization is introduced using Ftot instead of Fcrit in order to account for the gate distributed delay. As a result, the discrepancy of the predicted frequency for a 45° phase shift is reduced to less than 14 % as shown in Fig. 5.10. It should be noted that the error on the predicted phase at a given frequency is less than 6 %. Again, the remaining mismatch could be explained by a variation in the mobility with the gate voltage. This point will be briefly investigated in 5.7. For shorter devices, the distributed RC gate delay can dominate the channel NQS effect. This is evidenced on the phase delay versus the real frequency for the 28 nm and 1 µm channel lengths displayed respectively in Fig. 5.11 and Fig. 5.3. In the short device, the inversion level (IC) seems to have minimal impact on the critical frequency, see Fig. 5.11, and the two counter effects almost compensate each other.

Moreover, for P type MOSFET, the curves almost merge in Fig. 5.12. The gate distributed delay seems to slightly take over since the phase shift happens earlier when IC is increased, which should not be if the channel would still be the bottleneck in terms of delay. To follow up with the normalization scheme, we calculate the 'intrinsic channel normalization frequency' Fnorm1 from relation (5.10) and plot the phase shift accordingly in Fig. 5.13. Whereas for 'long' channels, this first normalization almost condenses the bunch of curves in a single one (see Fig. 5.6 and Fig. 5.8), here it spreads out in very different characteristics. The gate distributed effect could explain this dispersion. Fig. 5.14 shows the phase shift for the 28 nm channel length device when using the

Onset of NQS effects

Significant NQS effects pop up when the operation frequency reaches the critical frequency Fcrit defined in (5.5). In particular, a phase shift greater than 45° is measured at this characteristic frequency, meaning that Fcrit overestimates the onset of the NQS effect. To our knowledge, no clear definition is given for the emergence of NQS transport. Usually, the concept of transit frequency fT is used, i.e. the frequency where the modulus of the current gain HDG falls to unity, and the NQS frequency is often defined as being proportional to fT [START_REF] Tsividis | Operation and modeling of the MOS transistor[END_REF]. However, this definition relies on the low frequency transconductance gm, and therefore is implicitly a quasi-static definition. In order to assess the relation between fT and the NQS critical frequency, the current gain is plot for several IC values with respect to the normalized Fnorm1 frequency. where ID and IG are the current phasors across port-2 (drain) and port-1 (front gate), respectively. VD is the voltage across port-2, which is matched in this case. HDG is frequently used to extract the transit frequency of the transistor. The transit frequency fT is defined as the frequency at which the magnitude of HDG becomes equal to unity (i.e. 0 dB). fT is proportional to Fcrit in MI and SI as can be expected from (5.6) and

(5.2), and noting that fT is proportional to the square root of the drain current provided that velocity saturation is ignored. However, for WI, the proportionality is less valid, which is expected knowing that Fcrit becomes constant in WI while fT remains proportional to IC. If we use the SI approximation (5.6) for the frequency normalization for all the levels of inversion with L = 1 µm, all |HDG| plots are superimposed for various IC values, including WI regime, as shown in inset of Fig. 5.15. This suggests that transit frequency is proportional to the square root of the current all the way from WI to SI. Therefore, the proportionality between the onset of NQS frequency and fT holds only in SI. In WI and practically in MI, the rules of thumb based on proportionality to fT underestimates the critical NQS frequency. Depending on the criteria invoked, we propose to use two expressions for the onset of device distributed effects:

• 10° phase shift of the transadmittance efficiency:

¨© R%°= 1 2™ tan ™ 18 1 2™ • ˜ ƒ + { † • (5.19)
• 3% decrease in the transadmittance efficiency magnitude from the low frequency value:

¨© •% = 1 2™ 0.25 1 2™ • ˜ ƒ + { † • (5.20)
Note that FNQS3% is practically equal to fT in SI and, higher in WI and MI.

Back gate control

In a DG UTBB MOSFET, the independent back gate voltage controls the threshold voltage and consequently IC. The back gate also influences the apparent mobility of the carriers in the silicon film thanks to the volume inversion in low electrical field condition. This fact is already evidenced in Chapter 3 and also validated by the Transit Frequency fT extracted using 4-port measurements and shown in Fig. 5.16. For L = 100 nm a higher measured maximum fT (119 GHz) is achieved for VbG = 2 V in comparison to the VbG = 0 V case for same IC values. The 6% high frequency performance enhancement is expected to be greater for longer devices. Therefore, as the NQS characteristic frequency Fcrit is dependent on both mobility and IC, we expect an impact of the back gate voltage on NQS effects. In this section, this impact is assessed using TCAD simulations for various back gate voltages and for fixed front gate voltage for the front gate transadmittance efficiency on the one hand and for the back gate transadmittance efficiency on the other hand. TCAD simulations were used to avoid tedious deembedding steps of the 4-port structures measurements that provide an independent access to the back gate terminal. Likewise for the front gate analysis, a further normalization of the modulus (|ym1|/ID) is applied using the low frequency transconductance efficiency gm1/ID. It should be noted that in TCAD simulations no gate distributed effect is taken into account. ) V bG = -3 V IC = 0.02

V bG = -3 V IC = 0.02 V bG = -1 V IC = 1 V bG = 1 V IC = 8 V bG = 3 V IC = 24.3 V bG = 0 V IC = 3.
V bG = -1 V IC = 1 V bG = 1 V IC = 8 V bG = 3 V IC = 24.3 V bG = 0 V IC = 3.5

Back gate transadmittance efficiency

In the UTBB FDSOI MOSFET, an input small signal can also be applied to the back gate to modulate the channel. In order to evaluate the back gate performance at high frequency, as in [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF], the transadmittance efficiency of the back gate is now assessed for a fixed front gate voltage VGS = 0, and for various inversion levels imposed by the back gate (various VbG). Fig. 5.20 shows the phase of the transadmittance efficiency of the back gate at VGS = 0 V. In this case, the channel is located in all the volume of the silicon film. Again, after applying the same normalization for the frequency and transconductance to current ratio, a unique plot is obtained in Fig. 5.21. This closes the loop on the normalization scheme used to predict non static transport in UTBB FDSOI MOSFETs. Phase(y m /I D ) (deg)

V bG = -3 V IC = 0.02 V bG = -1 V IC = 1 V bG = 1 V IC = 8 V bG = 3 V IC = 24.3 V bG = 0 V IC = 3.5

Channel Mobility extraction using NQS effect

As shown in Fig. 5.6, the channel NQS related normalization (5.10) leads to a more or less unique curve. Actually, after the normalization in (5.10), we still get a discrepancy of the NQS effect critical frequency Fcrit of about 15% while using a constant mobility (µ = 240 cm 2 /Vs) for all levels on inversion. According to (5.5), the observed Fcrit discrepancy is caused by a rather variant mobility, a variant length or an inaccurate IC. The two aftermost causes are unlikely to happen, that is in one hand, Phase(y m2 /I D ) (deg)

V bG = 3 V IC = 0.004 V bG = 4 V IC = 0.062 V bG = 5 V IC = 0.6 V bG = 6 V IC = 2.4 V bG = 7 V IC = 6 V bG = 8 V IC = 13 V bG = 9 V IC = 24 10 -3 10 -2 10 -1 10 0 10 1 -180 -135 -90 -45 0 45 90 135 180
F norm (n.u.)

Phase(y m2 /I D ) (deg)

V bG = 3 V IC = 0.004 V bG = 4 V IC = 0.062 V bG = 5 V IC = 0.6 V bG = 6 V IC = 2.4 V bG = 7 V IC = 6 V bG = 8 V IC = 13 V bG = 9 V IC =

Discussion

The NQS critical frequency Fcrit for a single gate bulk MOSFET developed in [START_REF] Sallese | A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation[END_REF][128] holds for a DG MOSFET, including with asymmetric operation. In particular, the normalization of the frequency leads to almost unique charts for long channel devices allowing fast and accurate high frequency performance assessment.

Moreover, the invariance is also confirmed for short channel devices with a dominant gate distributed effects provided that the related time constant is taken into consideration. The transadmittance efficiency concept defined in this Chapter provides deep insight into high frequency UTBSOI MOSFET behavior and an estimation of the limiting MOSFET characteristic frequencies. The critical channel NQS frequency depends on the device length, free carrier mobility and inversion coefficient IC. The gate distributed effect, in turn, depends on the gate resistance and capacitance. The frequency normalization using the distributed gate time constant generalizes the normalization scheme by merging the longitudinal (gate) distributed effect with the channel NQS effect. The invariant normalized transadmittance efficiency versus normalized frequency was confirmed extensively with both measured and simulated data. This novel approach provides a way to calculate the critical frequency beyond which the gain and the phase will be affected. In Analog and RF design, oversimplified rules of thumb are used and bias the analysis. For instance, stating that operating frequency should be lower than fT/10 or fT/3 is encouraging the designer to choose shortest MOSFETs while introducing detrimental mismatch and SCE, especially Drain Induced Barrier Lowering (DIBL).

Such a rule of thumb can be overlooked using the transadmittance efficiency charts and critical frequency expressions developed in this Chapter and introducing the Inversion Coefficient concept as in [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. Then, knowing Fcrit versus the channel length and DC operating point, the optimum geometry can be selected unambiguously.

At high frequency, beyond the transit frequency fT, charge carriers oscillate in the channel with a delay versus the applied gate voltage oscillation leading to what we generally call Non-Quasi-Static effect. The mobility term in Fcrit expression (5.5) is an effective mobility of carriers that do not reach the source side and consequently with less degradation due to access resistance. This explains why the mobility extracted using Fcrit expression is rather higher compared to classical extraction methods. The mobility extraction using Fcrit is more straightforward than using I-V and C-V measurements where series resistances miserably impact the extraction leading to incoherent mobility values without a careful estimation of the series resistances.

Conclusion

In this Chapter, we have shown that the frequency normalization using a critical frequency and taking into account lateral and longitudinal MOSFET distributed effects offers a practical insight to help high frequency performance assessments of UTBB FDSOI MOSFETs through a powerful normalization scheme. We have experimentally shown that frequencies of interest at which MOSFET distributed effects occur can be predicted using simple analytical expressions which are valid down to 28 nm channel length. The NQS critical frequency is also used for the mobility extraction. The proposed method provided comparable values to the classical methods in SI. In WI, in contradiction to the classical methods, the proposed method revealed that mobility is remaining at the same levels compared to stronger inversion levels.

The normalization scheme is application to whatever the gates length and DC biasing, and supports the very general character of the NQS analysis proposed in this research work.

Part III RF Design application

Chapter 6 RF and mm-Wave design application

Introduction

More and more wireless devices and IoT building blocks rely on CMOS analog and RF circuits to efficiently interact with the physical world. Thanks to the geometry down-scaling, CMOS MOSFETs have been widely used in low-cost and low-power RF integrated circuits (RFIC). Short-channel related issues, as side effects of the geometry shrink, have been controlled using new architectures and new materials [4] [3]. As stated earlier, the new architectures allow for excellent electrostatic control [26].

Clearly the UTBB FDSOI technology has proven to be suitable for Analog and RF applications, especially when both power consumption and performance are valued equally. UTBB FDSOI MOSFETs exhibit high analog and RF performances thanks to the reduced parasitic capacitances and resistances [14]. Moreover, the independent back gate provides an interesting degree of freedom that allows tradeoff between power consumption and performance [41] [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF].

Several circuit-topology-based techniques such as current reuse are proposed in analog design to optimize performance and power consumption [START_REF] Karanicolas | A 2.7-V 900-MHz CMOS LNA and mixer[END_REF]. These techniques are out of this research work scope. In this Chapter, the UTBB FDSOI characteristics are used for first-cut analog sizing method. In particular, the transconductance efficiency versus inversion coefficient (IC) studied in Chapter 3 is used to determine the width of the MOSFET while the transit frequency (fT) versus IC charts are used for length selection. The design method, using relaxed length and Moderate Inversion regime, provides a valuable tradeoff between gain, power consumption and performance while MOSFET width is kept reasonably large and short channel effects are mitigated. An eye is also kept on passive devices limitations from the very beginning of the sizing flow. This Chapter is organized as follows. First, the classical analog design methods, based on inherited rules of thumb, are briefly discussed in Section 6.2. Second, the UTBB FDSOI technology capabilities for Analog and RF applications are reminded in Section 6.3. Third, the transconductance (gm) over drain current (ID) based design method is presented in Section 6.4. Fourth, the high frequency performance versus IC and MOSFET length is assessed in Section 6.5. Fifth, a 35 GHz LNA design tradeoff in Moderate Inversion is proposed in Section 6.6. Finally, a new LNA-MIXER circuit combining both amplification and mixing operations in one circuit is proposed in Section 6.7, and a conclusion is given in Section 6.8.

Classical design sizing methods in Analog and RF

Sizing MOSFETs through iterative simulations and trial and error practices takes considerable amount of the precious design time. Optimum design tradeoff is hardly achieved using these methods [START_REF] Foty | Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id[END_REF]. Furthermore, hand calculation based analog design remains the method of choice to minimize iterative simulations, and enables intuitive design. The classical hand calculation sizing methods are still based on inaccurate and questionable concepts such as the gate voltage overdrive (Vov = VGS -VTH, where VTH is the threshold voltage), and pessimistic rules of thumb such as the shortest possible length for higher fT, higher Vov constraint, and a maximum operation frequency of fT/10.

Design in Moderate Inversion has become attractive in advanced technologies

as it offers the optimum trade-off between speed, transconductance, and power consumption [START_REF] Shameli | Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study[END_REF] [START_REF] Ghouli | Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model[END_REF]. However, the classical gate voltage overdrive is becoming a poor metric for MOSFET inversion level assessment in advanced technologies as it is based on conflicting definitions of the threshold voltage [START_REF] Ortiz-Conde | Revisiting MOSFET threshold voltage extraction methods[END_REF]. The latter is defined as the VGS value at the onset of the Strong Inversion and extracted using several methods and criteria leading to uncorrelated definitions. Moreover, gate overdrive voltage can only be used for the hand calculation sizing method based on SI square law that miserably fails to predict gm/ID in MI as seen in Fig. 6.1. At Vov = 100 mV, the error is more than 100% for L = 30 nm. For short channel devices (e.g. L = 30 nm in Fig. 6.1), the simple square law is not valid in all levels of inversion. Moreover, as see in Chapter 2 for a double gate transistor which is the UTBB FDSOI MOSFET, we experimentally observe two separate threshold voltages in the forward back gate bias condition while considering the measured C-V characteristic and its derivative both reproduced respectively in Fig. 6.2 and its Inset. Consequently, the gate overdrive voltage becomes impractical for describing the level of inversion of the advanced MOSFET architectures. It should be noted that Vov can become negative in MI and for lower levels of inversion, and thus becomes useless. Fig. 6.1 Square law model and weak inversion exponential model failures to predict measured gm/ID in MI for a long and short channel devices. VTH is defined here as the VGS at the maximum of ∂Cgc/∂VGS.

V GS (V) C gc (n.u.) V bG = -10 V V bG = -5 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 5 V V bG = 10 V -0.5 0 0.5 1 10 - 12 10 -11
V GS (V)

∂C gc /∂V GS (F/V)
In RF circuits, designers tend to use shortest devices to get highest possible transit frequency fT and consequently better performance. However, shortest MOSFETs are subject to detrimental short channel effects, lower intrinsic voltage gain, and higher mismatch. In Fig. 6.3, Drain-Induced-Barrier-Lowering (DIBL) versus the gate length is reproduced for bulk and FDSOI technologies. Using relaxed and nonminimal lengths provides lower DIBL effect and lower variability while frequency performance is still high enough for the majority of today's applications in the RF spectrum as shown in Fig. 6.4 where fT is plotted versus the Inversion Coefficient (IC)

for various MOSFET lengths in 28 nm UTBB FDSOI technology. IC is defined as:

= • ' 3 G , (6.1)
where ID, W and L are respectively the drain current, the width, and the length. I is the square current at the middle of the moderate inversion with a value of about 0.7 µA for 28 nm UTBB FDSOI NMOS [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. For L = 100 nm, the maximum transit frequency is still in the mm-Wave spectrum (> 100 GHz) for the UTBB FDSOI technology while DIBL is reduced by 23 mV/V with respect to L = 28 nm. Moreover, according to (6.1)

and for fixed ID and inversion level IC, the device area increases as L 2 , which is beneficial for local mismatch effect. 19 GHz with no degradation on |Y21|. In summary, it is clearly evidenced that non minimal channel lengths (i.e. L > 30nm in 28 nm node) in advanced technologies provide high enough fT values that can still be used to design RF circuits, while the conservative fT/10 rule of thumb is misleading, in particular at low inversion levels.

'Common' rules are then inaccurate and lead to overdesign. To overcome these issues, optimal geometries and bias conditions are approximated using timeconsuming iterative numerical simulations. Other sizing methods based on the Inversion Coefficient concept have been proposed [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF]. However, in many circuits where passive elements play a key role such as Low Noise Amplifier (LNA), circuits are optimized using time-consuming iterations of the IC based method since no passive part related constraints are considered in the active part optimization [START_REF] Fadhuile | Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient[END_REF].

Advantages of UTBB FDSOI technology

In the UTBB FDSOI technology, MOSFET channel is formed in a thin silicon film separated from the substrate by an oxide film called the Buried OXide (BOX). In 28 nm FDSOI technology, the final silicon film is 7 nm thick after process [3]. This architecture provides with multiple advantages for high performance and low power applications. In the addition of the well-known SOI technology advantages [38][39], UTBB FDSOI technology features lower parasitic capacitances and then high-speed operation. The harmful parasitic substrate coupling is avoided in the UTBB FDSOI by introducing the Ground Plane which is a highly doped region underneath the thin BOX [40]. The ground-plane implantation under the BOX is well-type in the structures studied in this work. FDSOI technology allows co-integration of both bulk and SOI devices on the same die thanks to BOX opening for the bulk parts with a dedicated mask [44].

With less parasitic capacitances, supply voltage can be lowered for reduced power consumption with still high speed operation. Other advantages of UTBB FDSOI are steep subthreshold slope [8], reduced SCE (cf. Fig. 6.3), tolerance to radiation as for standard SOI and high temperatures, even though buried oxide isolation is known to give birth to temperature increase because of self-heating effect [17]. However, thanks to a thinner BOX in the UTBB FDSOI, thermal effects influence on device parameters are limited in comparison with standard SOI [18].

The advantages of the UTBB FDSOI technology make it possible to implement high performance MOSFETs operating at a low voltage, specifically in the moderate inversion regime. An understanding of the fundamental behavior of the UTBB FDSOI MOSFETs at high frequency is essential for circuit design and a sizing method in MI is a must.

g m over I D invariance based method

In digital CMOS circuits, static power consumption is mainly related to the leakage current. However, in analog circuits, biasing current is the main contributor for circuit power consumption. Thus, the devices used in analog blocks need to be permanently biased in the appropriate region. Besides power supply voltage lowering in recent technology nodes, the current budget should be reduced as well.

In RF circuits, a good tradeoff between speed and low current budget is satisfied in moderate inversion. However, for advanced devices such as the asymmetric double gate MOSFETs, the validity of classical hand calculation expressions is questionable.

The lack of simple expressions for hand calculation can be reasonably contained using measurement based charts. The measured transconductance efficiency charts assessed in [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF], can be used to size the transistor and to ensure its operation in moderate inversion. The invariance of the gm over ID chart in MI for L ≥ 100 nm makes it easy to generate the required chart. If we take into account the slope degradation using the slope factor n1, shorter geometries can also be accounted for with same merged chart. In Fig. 6.7, gm over ID charts are shown versus IC. A longer geometry (L = 1 µm) is also shown for comparison. Using these charts, the gm over ID value can be reasonably retrieved for any selected IC and for each displayed geometry from WI to SI.

Recently, it is claimed that preselecting drain current (ID), IC, and channel length is the most efficient way to size MOSFETs in analog circuits [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF]. However, the proposed simple expressions of MOS performance mainly rely on EKV formalism which has been extrapolated to a symmetric DG in [START_REF] Sallese | A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism[END_REF] but not yet transposed to the asymmetric DG. However, the choice of the inversion coefficient as a measure of the inversion level in the channel happens to be totally justified since it accurately describes the inversion charge and consequently the operating regime for single or double gate MOSFETs [81][127]. According to Fig. 6.7, selecting an IC value is equivalent to setting gm over ID of the device. Moreover, based on (6.1), once IC an ID are known, the geometry ratio (W/L) can be calculated. One of the interesting high frequency FoM is the transit frequency fT that estimates the high frequency amplification limit and also provides an insight of the transconductance to input capacitance ratio (fT ≈ gm/2πCgg) of the MOSFET. The transit frequency versus IC charts for several lengths provide high frequency performance limits since fT represents the frequency at which current gain falls to unity. However, it should be noted that the transistor can operate at any frequency even beyond this limit, provided that non-quasi-static related limitations are carefully taken into account and modeled. The modulus and phase of the transadmittance versus frequency charts (e.g. Fig. 6.5 and Fig. 6.6) can also be used to estimate the phase shift and modulus drop when frequency is set beyond fT (cf. Chapter 5 for more detail). As stated in Section 6.2, the rule of thumb stating that maximum frequency of operation must be lower than fT/10 is too stringent. This rule of thumb finds its origin in the validity of the quasi-static model proposed in [START_REF] Tsividis | Operation and modeling of the MOS transistor[END_REF] and thus is essentially a misinterpretation.

LNA design using MI Tradeoff in UTBB FDSOI

In this Section, the focus will be on another challenge which is the transistor sizing. The RF designer dilemma is to calculate transistor geometry and current in order to get maximum amplification, minimum degradation of the signal-to-noise ratio, and minimum power consumption. The goal is to provide an illustration of a design method mainly based on the charts and properties described in previous Chapters and reminded in Section 6.4 and 6.5.

One of the key building blocks in a wireless system is a Low Noise Amplifier (LNA). The LNA circuit amplifies the input signal with minimum degradation of the signal-to-noise ratio. One of the challenges RF designers face is the simultaneous matching of the noise and the input impedance for the same source impedance. This challenge is beyond the scope of this Chapter therefore ideal impedance matching is considered here. However, a constraint on the value of the inductors is considered in order to account for integrated inductors with acceptable quality factors.

‹" = • Ž . € (6.2)
Optimal IC lays, at least theoretically, between IC = 4 and IC = 10. Depending of the length selection, corresponding IC will be chosen where FoM is maximum.

Fig. 6.9 FoM versus IC for two lengths.

Passives related constraints and Length selection

In order to avoid passive components with degraded quality factors Q, some constraints are considered prior to MOSFETs sizing. The values are chosen within the integrated mm-Wave inductor values [25 pH -100 pH] as in [START_REF] Brinkhoff | Scalable Transmission Line and Inductor Models for CMOS Millimeter-Wave Design[END_REF]. The real part of the LNA input impedance is mainly tuned using degeneration inductor Ls. The expression of this real part is given in (6.3), provided that M1 intrinsic conductance influence on input impedance is neglected:

{&~-• = G ≈ 2™Ž . G (6.3)
where Cgs, and fTi are the gate-source, and intrinsic transit frequency of M1, The LNA is designed to operate at F0 = 35 GHz and consequently, to cancel the input impedance imaginary part at this resonance frequency, the inductor Lg is tuned with a target value given by [START_REF] Razavi | RF Microelectronics[END_REF]:

G = 1 2™ % • -G (6.4)
where Cin is including the total M1 gate capacitance Cgg and the Miller effect of the gate-drain capacitance (Cgd).

Width and V GS calculations

The Width is calculated using the following expression: The results of the above sizing flow are shown in Fig. 6.12 versus frequency and summarized in Table 6-1 for the operation frequency F0 = 35 GHz. Power gain is lower for the L = 70 nm based LNA because of the higher IC and consequently lower transconductance efficiency. The input impedance matching is acceptable for both LNA circuits. The NFmin value is higher for the longer channel based LNA as expected, however this can be lowered using optimized layout. The power consumption of both LNAs is 2 mW which is excellent for low-power applications.

3 = • • G (6.

LNA -MIXER

The back gate of the input MOSFET M1 in the LNA circuit of Fig. 6.8 is grounded which fixes the voltage drop between back gate and source. The goal of the LNA as an important element of the transceiver, is to amplify the signal with minimal impact on the signal to noise ratio. In the receiver path, after amplification, the signal is downconverter using a mixer. The down-conversion mixer senses the amplified RF signal at its first port and the local oscillator waveform at its second port. The mixer performs frequency translation or modulation of the RF signal by multiplying the two waveforms at its two input ports in order to obtain a baseband signal which is convenient for signal processing. Mixers are usually realized using either passive or active circuits that contribute to the total transceiver noise and power consumption.

The design of the LNA and the mixer are tightly linked. A tradeoff is usually examined One of the advantages of the UTBB FDSOI MOSFET discussed in previous chapters is the possibility to control the threshold voltage using the back gate. This feature can be used here in order to modulate the input signal at the front gate of the same MOSFET used for amplification in the LNA circuit shown in Fig. 6.8. We propose to merge both the LNA and the mixer in the same circuit as shown in Fig. 6.13. This LNA-MIXER circuit allows a simultaneous amplification and frequency conversion of the input signal using a minimum number of MOSFETs. The noise figure is minimized as only one MOSFET channel is used for both operations (e.g. amplification and mixing).

Conclusion

In this Chapter, a constrained sizing methodology is proposed for the UTBB FDSOI MOSFET. The methodology is based on fT versus IC measured or simulated curves for the length selection, and on gm over ID charts for the width calculation. The Inversion Coefficient is fixed to a value where the MOSFET optimum performance is expected, making this analysis dependent only on the channel current, and 'independent' of the front and back gate biases, a great simplification in terms of analysis. The methodology takes into account the passive components limitations and thus requires less if not minimal iterations.

General conclusion

Silicon based RF technology and wireless communication have had an impressive impact on our lives. The success was mainly based on the aggressive downscaling dictated by the high-performance integrated digital circuits. The detrimental short-channel related issues have been controlled by brilliant scientists and creative engineers using new device architectures and new materials. The new architectures such as the UTBB FDSOI studied in this research work allow for excellent electrostatic control, high level of integration, reduced power consumption, and very high operation frequency.

Moreover, with these recent advances in silicon industry, IoT network is becoming more of a reality in terms of their widespread use in various aspects of life.

Although IoT already brings more capability in our daily life in terms of sensing and communicating using RF systems, higher performance along with more autonomy are still to be explored. Therefore, profound skills have to be developed in the following two key areas: (1) Silicon based CMOS technology usage in mm-Wave spectrum and beyond, and (2) Transistor operation at lower applied voltages and in lower levels of inversion.

Given the above mentioned needs, the first goal of this thesis has been to study and evaluate the capabilities of the newly developed UTBB FDSOI technology through its main building block, which is the double gate MOSFET. The other goal is to explore and expand the low frequency modeling approaches and sizing methods to high frequency, with a strong focus on moderate inversion where a tradeoff between performance and power consumption is predicted.

Research work results

The main results of this research work are summarized in the following although conclusions are already presented for each Chapter.

Transconductance efficiency invariance in asymmetric double gate

As MOSFET high frequency operation is tightly linked to its bias conditions, DC and low frequency behavior assessment was our first target before tackling the high frequency operation. One of the most convenient metrics that combines both the amplification capability and power consumption is the gm over ID namely the transconductance efficiency. Transconductance efficiency is proven to be an essential design synthesis tool for low-power analog and RF applications.

Transadmittance efficiency concept

High frequency operation is governed by both the MOSFET extrinsic elements and the distributed effects. Carful characterization techniques with several correction steps have been used in order to get rid of the measurement setup and pads related parasitic elements. In particular, dedicated SHORT structures are used to extract the parasitic DC series resistances. Classical OPEN-SHORT method is used to de-embed measured S-parameters. These techniques provided a closer insight to the intrinsic behavior of the UTBB FDSOI MOSFET and allowed the distinction between two competing distribution effects: the channel NQS effect and the gate distribution effect.

The UTBB FDSOI MOSFET NQS behavior is studied with a special focus on moderate inversion. Frequency dependence of small signal characteristics derived from experimental S-parameters are analyzed and reveal that the transconductance efficiency (gm/ID) concept, already adopted as a low frequency Analog figure-of-merit, can be generalized to high frequency. In particular, the concept of the transadmittance efficiency is introduced to assess MOSFET capability in a wider frequency range. The new FoM allows operation tradeoffs prediction in all levels of inversion and all operation frequencies.

The generalized FoM (i.e. ym/ID) with respect to the normalized frequency, using the first NQS pole, only depends on the mobility and inversion coefficient (IC). This interesting property is used to define NQS critical frequencies based on the gain decrease and phase shift. A link to the generally used transit frequency is also given.

Mobility extraction using NQS effect

In addition, we used the novel approach (i.e. the normalized critical frequency invariance assessed using the transadmittance efficiency) to extract essential parameters such as the mobility, the critical NQS frequency fNQS and the transit frequency fT. Contrary to the classical methods, the proposed mobility extraction method allows accurate extraction including in MI and WI. This capability is based on the fact that, at high frequency, charge carriers "oscillate" in channel and are less subject to extrinsic series parasitics.

DC and quasi-static low-frequency modeling

The analysis of the measured and simulated DC and C-V characteristics for various back gate voltages, shows that the thin silicon film is subject to multiple phenomena. In particular, the channel is not confined to the front and back interfaces although the majority of compact models adopt the double interface approach. The volume inversion phenomena is found to be the most adapted to explain the electrostatic and transport observations. The DC UTBB FDSOI MOSFET characteristics are compared to a single gate bulk counterparts. Although the two gates control and the thin film quantum effect occurrence, the DC characteristics are comparable to the bulk ones. Moreover, thanks to a better electrostatic control, the long channel DC characteristics are closer to the ideal square law in SI and to the exponential law in WI. The derivation of the threshold based models in both bulk and UTBB FDSOI showed that the classical bulk models can be used as fair approximations provided that the threshold voltage dependence on both gates is accounted for in UTBB FDSOI MOSFET. It should be noted that mobility reduction and saturation can be accounted for using same classical bulk methods as a first order model.

A small signal low frequency equivalent circuit is proposed and gradually enhanced for higher frequency operation. The proposed equivalent circuit simulation is compared to UTSOI2 model and showed to be accurate enough to be used in analog

High frequency NQS model

The used high frequency characterization technics allowed to get clean measurements up to 110 GHz. The high frequency characteristics are used to validate the proposed model, noting that the proposed characterization is based on lower frequency measurements. Two main effects limit the high frequency MOSFET capability: (1) the extrinsic layout dependent elements, and (2) the lateral (i.e. channel related) and longitudinal (i.e. gate related) distributed effects.

The extrinsic elements are modeled using on the one hand the series source and drain resistances and, on the other hand two gates networks. The front gate network is taking into account the physically distributed resistances and capacitances in particular three series resistances and two main fringing capacitances. The front gate is consequently accounting for the distributed effect especially for large MOSFETs. This distributed effect is competing with the channel NQS effect and is carefully modeled partly using a pole-zero compensation technique.

The non-quasi-static effect is modeled using a channel segmentation and an additional MOSFET shell in order to take into account the overlap and a part of the extrinsic fringing capacitance. The DIBL is modeled using extrinsic voltage dependent voltage sources at the front and back gates in order to emulate the threshold voltage shift.

The proposed model predicts accurately the Y-parameters and high frequency FoMs over the wide frequency range from 100 MHz up to 110 GHz. The excellent accuracy over a wide frequency band of the simulations compared to measurements verifies that the topology of our model is correct and complete.

Analog RF and mm-Wave sizing

Having previously prepared low and high frequency charts and developed high frequency accurate models, a circuit sizing methodology is proposed and discussed to illustrate the benefits of operation in moderate inversion. The classical sizing methods along with their impact on circuit sizing are discussed and found to cause overdesign.

The UTBB FDSOI characteristics are used for first-cut analog sizing of a simple 35 GHz LNA circuit. The goal is to provide with an application example where operation in MI is profitable as long as both high frequency performance and power consumption matters. The transconductance efficiency versus inversion coefficient (IC) studied in Chapter 3 is used to determine the width of the MOSFET while the transit frequency (fT) versus IC charts are used for length selection. The design method, using relaxed length and Moderate Inversion regime, provides a valuable tradeoff between gain, power consumption and performance while MOSFET width is kept reasonably large and short channel effects are mitigated. An eye is also kept on passive devices limitations from the very beginning of the sizing flow.

Perspectives

Large signal validation

Although small signal models are often sufficient for the design of linear circuits, the implementation of nonlinear circuits such as power amplifiers and oscillators requires accurate prediction of the nonlinear characteristics of MOSFETs in a wide range of bias conditions. The equivalent circuit developed in this thesis is a small signal model and can only be used with linear circuits. However, the augmented UTSOI2 model, also proposed in this thesis for industrial circuits simulation, is conceptually a large signal model provided that we assume that large signal performance is primarily governed by its DC nonlinearities. The approach based on an augmented compact model predicts accurately the harmonic distortion behavior although a quasi-static assumption is considered in [START_REF] Emami | Large-signal millimeterwave CMOS modeling with BSIM3[END_REF]. This extended compact model approach can also be used in the case of the UTBB FDSOI MOSFET for large signal simulation.

Therefore, in order to validate this approach, mm-Wave nonlinearity characterization needs to be performed using for instance mm-Wave load-pull measurements or power spectrum analysis.

High frequency noise model

An accurate high frequency noise model is a must for LNA design. Still, noise is commonly characterized in a frequency range where the transistor behavior verifies the quasi-static assumption. Therefore, noise measured data are often not reproduced with inadequate models at high frequency. Moreover, noise effects of different origins have made it difficult for scientists to develop an accurate model. In particular, empirical models are being used for high frequency noise modeling because of the ambiguity related to the real cause of excess noise in short channel devices. The two-port noise parameters, traditionally required for RF design as a better alternative to inaccurate models, have to be extended to the mm-Wave spectrum and powerful de-embedding techniques are still to be proposed.

Variability

Because of the shirked dimensions in the advanced technologies such as UTBB FDSOI, managing variability has become one of the most important, if not the most important challenge. The electrical variability caused by the process variation at nanoscale greatly impacts the yield and thus the cost of the integrated circuits.

In analog and RF/mm-Wave design, a variability model has to be accurate enough to predict the impact of local and global process variations on the electrical simulations. Although conservative models exist to accommodate the high yield requirements, a rigorous and comprehensive analysis of variability and its origins along with robust models are invaluable.

.

;R A = 0 R • -. • ln 2 • 0 R • R • -. S • 0 • T -0 R -1 • U A -0 R • -. • ln V tanh >Z • U A -A 2 • -. >Z • U A -A 2 • -. [ (A. 36)
Similar expressions can be derived for the back interface inversion charge and threshold voltage, which is dependent on the front gate voltage:

7 = -0 • • -. • & `µ² ³ |`+ ´3 | )¯• ` )¯• * + (A.

37)

.

; A = 0 • -. • ln 2 • 0 • • -. S • 0 • T -0 -1 • A -0 • -. • ln V tanh >Z • U A -A 2 • -. >Z • U A -A 2 • -. [ (A . 38)
Simu V DS = 0.05 V Simu V DS = 0.15 V Simu V DS = 0.3 V Simu V DS = 0.5 V Simu V DS = 0.7 V Simu V DS = 1 V Meas V DS = 0.05 V Meas V DS = 0.15 V Meas V DS = 0.3 V Meas V DS = 0.5 V Meas V DS = 0.7 V Meas V DS = 1 V -0.2 0
Simu V DS = 0.05 V Simu V DS = 0.15 V Simu V DS = 0.3 V Simu V DS = 0.5 V Simu V DS = 0.7 V Simu V DS = 1 V Meas V DS = 0.05 V Meas V DS = 0.15 V Meas V DS = 0.3 V Meas V DS = 0.5 V Meas V DS = 0.7 V Meas V DS = 1 V
Transconductance is shown in V DS (V) V DS (V) V DS (V) Une propriété importante des transistors MOSFET double-grille (i.e. FinFET, UTBB FDSOI, etc.) à savoir l'inversion volumique (IV) a été découverte en 1987 [11].

V GS (V) g m (n.u.) Simu V DS = 0.05 V Simu V DS = 0.15 V Simu V DS = 0.3 V Simu V DS = 0.5 V Simu V DS = 0.7 V Simu V DS = 1 V Meas V DS = 0.05 V Meas V DS = 0.15 V Meas V DS = 0.3 V Meas V DS = 0.5 V Meas V DS = 0.7 V Meas V DS = 1 V 0.1 0.2 0.
V GS (V) g m (n.u.) Simu V DS = 0.05 V Simu V DS = 0.15 V Simu V DS = 0.3 V Simu V DS = 0.5 V Simu V DS = 0.7 V Simu V DS = 1 V Meas V DS = 0.05 V Meas V DS = 0.15 V Meas V DS = 0.3 V Meas V DS = 0.5 V Meas V DS = 0.7 V Meas V DS = 1 V -0.2 0 0.2 0.4 0.6 0.8 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 V GS (V) ∂g m /∂V GS (n.u.) Simu V DS = 0.05 V Simu V DS = 0.15 V Simu V DS = 0.3 V Simu V DS = 0.5 V Simu V DS = 0.7 V Simu V DS = 1 V Meas V DS = 0.05 V Meas V DS = 0.15 V Meas V DS = 0.3 V Meas V DS = 0.5 V Meas V DS = 0.7 V Meas V DS = 1 V -0.
I d (n.u.) Simu V GS = 0.15 V Simu V GS = 0.3 V Simu V GS = 0.6 V Simu V GS = 0.9 V Meas V GS = 0.15 V Meas V GS = 0.3 V Meas V GS = 0.6 V Meas V GS = 0.9 V 0.2 0.4 0.6 0.8 1 0 50 100 150 V DS (V) I d (n.u.) Simu V GS = 0.15 V Simu V GS = 0.3 V Simu V GS = 0.6 V Simu V GS = 0.9 V Meas V GS = 0.15 V Meas V GS = 0.3 V Meas V GS = 0.6 V Meas V GS = 0.9 V 0.2 0.4 0.6 0.8 1 10 0 10 2 10 4 V DS (V) I d (n.u.) Simu V GS = 0.15 V Simu V GS = 0.3 V Simu V GS = 0.6 V Simu V GS = 0.9 V Meas V GS = 0.15 V Meas V GS = 0.3 V Meas V GS = 0.6 V Meas V GS = 0.
I d (n.u.) Simu V GS = 0.15 V Simu V GS = 0.3 V Simu V GS = 0.6 V Simu V GS = 0.9 V Meas V GS = 0.15 V Meas V GS = 0.3 V Meas V GS = 0.6 V Meas V GS = 0.9 V
∂g ds /∂V DS (S/V) Simu V GS = 0.15 V Simu V GS = 0.3 V Simu V GS = 0.6 V Simu V GS = 0.9 V Meas V GS = 0.15 V Meas V GS = 0.3 V Meas V GS = 0.6 V Meas V GS = 0.9 V
L'inversion volumique se produit dans des films de silicium très minces contrôlés par deux grilles, ce qui est le cas dans un transistor MOSFET UTBB FDSOI où les porteurs de la charge mobile ne sont pas confinés dans les interfaces Si/SiO2 comme le prédit la physique classique du semi-conducteur. Ce phénomène est illustré en utilisant nos simulations TCAD dans la partie 2 et mis en évidence en utilisant nos données mesurées dans les parties 2, 3 et 5. Le confinement quantique dans le film de Si mince est à l'origine de l'effet de l'IV [12]. Bien que le phénomène de l'inversion volumique ) Quatre modèles compacts sont disponibles pour la simulation MOSFET UTBB FDSOI: BSIM-IMG [16], HISIMSOTB [14], UFDG [20] et Leti-UTSOI2 [21]. Des simulations TCAD (cf. Fig. 7) sont également effectuées en utilisant deux decks TCAD différents qui sont basés sur le simulateur de processus et de dispositifs Sentaurus de Synopsys Inc.: (1) un deck simple sans source et drain surélevés et utilisant une mobilité de porteurs constante pour capturer les effets de premier ordre;

V bG = -3 V V bG = 0 V V bG = 2 V V bG = 5 V
(2) un deck calibré avec la source et le drain surélevés, et un modèle avancé de mobilité [33]. Le deck TCAD calibré de la technologie FDSOI 28 nm est cruciale pour l'évaluation de l'impact de la grille arrière dans le fonctionnement à basse et haute fréquences. traditionnelles sont utilisées, ce qui peut conduire à une conception des circuits inefficace [36].

Les pratiques dépassées rappelées ci-dessus concernant les calculs manuels empêchent les concepteurs analogiques de tirer pleinement parti des technologies modernes (haute efficacité de la transconductance et faible VDSAT). Afin de remédier à la faiblesse des pratiques traditionnelles, où des concepts discutables tels que la tension d'Early, le VGS-VTH et la loi quadratique classique sont utilisés, la méthodologie de conception basée sur l'efficacité de la transconductance (gm/ID) a été proposée [37].

L'approche gm sur ID repose sur l'aspect fondamental et universel de la caractéristique représentant l'efficacité de la transconductance en fonction du courant de drain normalisé dans les MOSFET à grille unique. Une telle caractéristique est considérée comme invariante indépendamment de la tension de seuil et de la longueur à condition que les effets canaux courts soient considérés comme négligeables [37][38] . Cette invariance est étudiée dans ces travaux de thèse pour un transistor double-grille asymétrique. L'objectif est de vérifier dans quelle mesure la méthodologie de conception mentionnée ci-dessus et basée sur le gm/ID est valable pour les transistors à grilles doubles asymétriques avancées telles que l'UTBB FDSOI. La méthodologie de conception basée sur le gm/ID est brièvement expliquée. Les simulations TCAD rappellent l'effet de la grille arrière sur l'efficacité de la transconductance de la grille avant déjà discutée précédemment. La normalisation de l'efficacité de transconductance et du courant pour un transistor à double grille est décrite. Le dispositif expérimental est décrit et l'invariance de la caractéristique représentant l'efficacité de la transconductance en fonction du coefficient d'inversion (IC) est évaluée à l'aide des données expérimentales obtenues (cf. Fig. 9). Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V Simu V GS = 0.2 V Simu V GS = 0.3 V Simu V GS = 0.4 V Simu V GS = 0.5 V Simu V GS = 0.6 V Simu V GS = 0.8 V Simu V GS = 1 V Meas V GS = 0.2 V Meas V GS = 0.3 V Meas V GS = 0.4 V Meas V GS = 0.5 V Meas V GS = 0.6 V Meas V GS = 0.8 V Meas V GS = 1 V (a) L'excellente précision des simulations sur une large bande de fréquence par rapport aux mesures prouve que la topologie de notre modèle est correcte et complète. ses non linéarités DC. L'approche basée sur un modèle compact augmenté prédit avec précision la distorsion harmonique bien qu'une hypothèse quasi-statique soit considérée dans [45]. Cette approche de modèle compact étendu peut également être utilisée dans le cas du MOSFET UTBB FDSOI pour la simulation grand signal. Par conséquent, afin de valider cette approche, la caractérisation de la non-linéarité à des fréquences millimétriques doit être effectuée en utilisant par exemple des mesures de charge-traction dans les fréquences millimétriques ou une analyse de spectre de puissance.

Model de bruit haute fréquence

Un modèle de bruit haute fréquence précis est une nécessité pour la conception

Variabilité

En raison des petites dimensions dans les technologies avancées telles que UTBB FDSOI, la gestion de la variabilité est devenue l'un des défis les plus importants.

La variabilité électrique provoquée par la variation du processus de fabrication à l'échelle nanométrique impacte fortement le rendement et donc le coût des circuits intégrés.

Pour la conception des circuits analogiques et RF / millimétriques, un modèle de variabilité doit être suffisamment précis pour prédire l'impact des variations du processus de fabrication (variations locales et globales) sur les simulations électriques.

Bien que des modèles empiriques existent pour répondre aux exigences de rendement élevé, une analyse rigoureuse et complète de la variabilité et de ses origines ainsi que des modèles robustes sont aujourd'hui une nécessité.

Salim EL GHOULI ETUDE ET MODELISATION DU COMPORTEMENT DYNAMIQUE DU TRANSISTOR MOS DU TYPE UTBB FDSOI POUR LA CONCEPTION DE CIRCUITS INTEGRES ANALOGIQUES

Résumé en anglais

This research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz.

Fig. 1

 1 Fig. 1.1 FinFET (left) and UTBB FDSOI (right) similarity. ......................................................

Fig. 1 . 2 Fig. 1 . 3

 1213 Fig. 1.1 FinFET (left) and UTBB FDSOI (right) similarity. ...................................................... Fig. 1.2 Benchmarking transit frequency fT for various state-of-the-art MOSFETs versus gate length [14]. ................................................................................................................. Fig. 1.3 Measured fT versus normalized drain current ID/(W/L) for UTBB FDSOI NMOS and PMOS (L = 30 nm, Nf = 20, Wf = 1µm, VDS = 1 V). .................................................

Fig. 1 . 4

 14 Fig. 1.4 Simulated electron density in the silicon film at different back gate voltages VbG for a UTBB FDSOI NMOS (L = 1 µm & W = 1 µm) in saturation VDS = 1 V and strong inversion (at constant VGS = 1 V). ......................................................................... Fig. 1.5 UNIBOND fabrication process with Smart Cut .........................................................

Fig. 1 . 6

 16 Fig. 1.6 Cross section (left) and TEM (right [3]) of the UTBB FDSOI MOSFET ..................

Fig. 1 . 7 Fig. 1 . 8

 1718 Fig. 1.7 Cross section comparison between bulk MOSFET (right) and UTBB FDSOI (left) .................................................................................................................................. Fig. 1.8 Measured and normalized drain current ID/(W/L) versus front gate voltage VGS for various back gate voltages VbG in semi logarithmic scale for L = 1 µm, W = 10 µm at VDS = 1 V. .............................................................................................................. Fig. 1.9 Bulk MOSFET (left) versus UTBB FDSOI MOSFET (right). ................................... Fig. 1.10 Comparison of DIBL between FDSOI 28 nm and bulk 28nm technologies in saturation (VDS = 1 V) and VbG = 0 V. .............................................................................

Fig. 1 .

 1 Fig. 1.11 Transconductance efficiency gm/ID versus normalized drain current ID/(W/L) for long channels in saturation for bulk 65 nm, bulk 28 nm, and UTBB FDSOI 28 nm. ......

Fig. 1 .

 1 Fig. 1.12 Modified Meyer equivalent circuit. ..........................................................................

Fig. 1 .

 1 Fig. 1.13 Regions of operation on the front and back gates voltages plane for an imref splitting Vc = 0.5V, Tsi = 20 nm, Tox1 = 2 nm, and Tox2 = 40 nm. V1 and V2 are the front and back gate voltages respectively [57]. ................................................................

Fig. 2 .

 2 Fig. 2.1 UTBB transistor architecture (cross-section) with modeled charges as well as front and back surface potentials. .....................................................................................

2 . 2 Fig. 2 . 3

 2223 Fig. 2.2 Measured and normalized front gate capacitance versus front gate voltage for various back gate voltages for NMOS and at VDS = 0 V (L = 10 µm, W = 2 µm, MULT = 30). Inset: diagram showing C-V measurement procedure. ............................. Fig. 2.3 Measured and normalized front gate capacitance versus front gate voltage for various back gate voltages for PMOS and at VDS = 0 V (L = 10 µm, W = 2 µm, MULT = 30). ....................................................................................................................

Fig. 2 . 4

 24 Fig. 2.4 Measured gate capacitance derivatives versus VGS for various back gate voltages for NMOS (L = 10 µm, W = 2 µm, MULT = 30). ........................................................... Fig. 2.5 TCAD simulations of the gate capacitance versus VGS for three VbG values (-7 V, 0 V, and 7 V) for L = 1 µm and VDS = 1 V. .....................................................................

Fig. 2 . 6

 26 Fig. 2.6 Electron concentration versus position in the silicon film for various VGS values and fixed VbG = 7 V for L = 1 µm and VDS = 1 V. ...........................................................

Fig. 2 . 7

 27 Fig. 2.7 Electron concentration using TCAD simulations for fixed VbG = 7 V, and (a) VGS =0 V, (b) at threshold VGS = 0.3 V and (c) VGS = 1 V for L = 1 µm and VDS = 1 V. ......

Fig. 2 . 8

 28 Fig. 2.8 Front gate threshold voltage VTH versus back gate voltage VbG for NMOS (L = 10 µm, W = 2 µm, MULT = 30) ......................................................................................

Fig. 2 . 9

 29 Fig. 2.9 Measured and normalized drain current (i.e. ID/(W/L)) versus front gate voltage VGS for VDS = 1 V and various back gate voltages for NMOS (L = 1 µm, W = 1 µm). ..........................................................................................................................................

Fig. 2 .

 2 Fig. 2.10 Measured gm over ID characteristics versus normalized drain current ID/(W/L) for various back gate voltages VbG along with the WI and SI trends for NMOS (L = 1 µm, W = 1 µm, VDS = 1 V). .......................................................................................... Fig. 2.11 Measured gm over ID derivative versus front gate voltage for VDS = 0.05 V and various back gate voltages for NMOS (L = 1 µm, W = 1 µm). .......................................

Fig. 2 .

 2 Fig. 2.12 TCAD simulations showing the impact of the back gate voltage on carriers concentration and consequently on input characteristic ID -VGS. (a) ID -VGS for various VbG from -10 V to 8 V. (b) channel inversion at the front for negative VbG = -10 V (c) channel inversion in silicon film volume at VbG = 0 V, and (d) channel inversion local maximum near the back interface for VbG = 8 V. Distance unit is µm. ................................................................................................................................... Fig. 2.13 TCAD simulations showing (a) Cgc and its derivative for VbG = 5 V (b) derivative of gm/ID for VbG = 5 V, and (c) Cgc and its derivative for VbG = 10 V, L = 1 µm and VDS = 1 V .........................................................................................................

Fig. 2 .Fig. 2 .

 22 Fig. 2.14 Measurements showing (a) gm over ID and (b) ∂(ln(Qinv)/∂VGS versus normalized drain current for various VbG values (from -3 V to 3 V) in linear mode (VDS = 50 mV). ................................................................................................................................. Fig. 2.15 Measurements showing the transport term ∂ln(v)/∂VGS versus gate voltage VGS in (a) and normalized drain current in (b) for various VbG values (from -3 V to 3 V) in linear mode (L = 1 µm, W = 1 µm)..............................................................................

Fig. 2 .Fig. 2 .Fig. 2 .

 222 Fig. 2.16 Cross section of the bulk MOSFET for VD = VS (N-type) ....................................... Fig. 2.17 FDSOI UTBB transistor architecture (cross-section) with involved charges as well as front and back surface potentials. ........................................................................ Fig. 2.18 Equivalent schematic for small signal and low-frequency operation of the UTBB FDSOI including series resistances RS and RD (Cgd = Cgdi + Cgde and Cgs = Cgsi + Cgse). .................................................................................................................................

Fig. 2 .

 2 Fig. 2.19 NMOS gate to drain transadmittance phase (left) and modulus (right) simulated using Leti-UTSOI2 and the small signal equivalent circuit in Fig. 2.18. L = 1 µm, W = 10 µm, NF = 10, and VGS = VDS = 1 V. .........................................................................

Fig. 2 .

 2 Fig. 2.20 Equivalent schematic for small signal and quasi-static operation of the UTBB FDSOI MOSFET including series resistances RS and RD (Cgd = Cgdi + Cgde and Cgs = Cgsi + Cgse). ....................................................................................................................

Fig. 2 .

 2 Fig. 2.21 NMOS gate to drain transadmittance phase (left) and modulus (right) simulated using Leti-UTSOI2 and the quasi-static small signal equivalent circuit in Fig. 2.20. L = 1 µm, W = 10 µm, NF = 10, and VGS = VDS = 1 V. ................................................... Fig. 2.22 DC structure illustration. ........................................................................................... Fig. 2.23 RF multi-finger structure with a finger length of Wf = 10 µm. ................................ Fig. 2.24 (Top) SHORT structure equivalent schematic used to extract parasitic external resistances Rg_ext, Rd_ext and Rsb_ext (gate, drain and common source and back gate terminals series resistances respectively, source and back gate being shorted). (Bottom) an illustration of the performed optimization. ..................................................

Fig. 2 .

 2 Fig. 2.25 Normalized drain current Id vs. gate voltage overdrive in linear operation |VDS| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C. ......................................................................................................... Fig. 2.26 Normalized drain current Id vs. VGS -VTH in linear operation |VDS| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C. .............................................................................................................................

Fig. 2 .

 2 Fig. 2.27 Normalized transconductance vs. overdrive VGS -VTH in linear operation |VDS| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C. ......................................................................................................... Fig. 2.28 Normalized transconductance (left) and its derivative (right) vs. gate overdrive in linear operation |VDS| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C. ....................................................................

Fig. 2 .

 2 Fig. 2.29 Transconductance efficiency vs. normalized drain current Id = ID.L/W in linear operation |VDS| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10 at T = 25°C) (left). Same for NMOS and PMOS with L = 2 µm in saturation is given (right). ...............................................................................................................................

Fig. 2 .

 2 Fig. 2.30 Normalized Cgg and Cgd vs. gate voltage overdrive TYPE.(VG -VTH) in linear mode |VD| = 0.3 V for NMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C and frequency = 100 MHz. .....................................................................................................

Fig. 2 .

 2 Fig. 2.31 Normalized Cgg and Cgd vs. gate voltage overdrive TYPE.(VG -VTH) in linear mode |VD| = 0.3 V for PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C and frequency = 100 MHz. .....................................................................................................

Fig. 2 .

 2 Fig. 2.32 Smith chart showing the input and output S-parameters simulated using the proposed equivalent circuit in Fig. 2.18 and the Leti-UTSOI2 of L = 1 µm NMOS in saturation (VDS = 1 V). .................................................................................................

Fig. 2 .

 2 Fig. 2.33 Polar chart showing the input to output and output to input S-parameters simulated using the proposed equivalent circuit in Fig. 2.18 and the Leti-UTSOI2 of L = 1 µm NMOS in saturation (VDS = 1 V)...................................................................... Fig. 2.34 Y-parameters simulated using the proposed equivalent circuit in Fig. 2.18 and the Leti-UTSOI2 of L = 1 µm NMOS in saturation (VDS = 1 V). ...................................

Fig. 2 .

 2 Fig. 2.35 The real part of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V) .......................................................................................................................

Fig. 2 .

 2 Fig. 2.36 The phase of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V) ....................................................................................................................... Fig. 2.37 A sub-circuit example of a RF MOSFET (B instead of bG in bulk). .......................

Fig. 2 .

 2 Fig. 2.38 Comparison of OP Info capacitances and extracted counterparts in saturation VDS=1V for NMOS (L = 1 µm and W = 0.5 µm). ...........................................................

Fig. 2 .Fig. 2 .

 22 Fig. 2.39 Comparison of the Leti-UTSOI2 and 2/(gm/ID) expression VDSAT values versus VGS in saturation for NMOS and L = 2µm. ...................................................................... Fig. 2.40 ID -VDS characteristics for various VGS and L = 2 µm showing two VDSAT definitions (Leti-UTSOI2 and 2/(gm/ID) expression). ......................................................

Fig. 2 .

 2 Fig. 2.41 Comparison of the Leti-UTSOI2 and 2/(gm/ID) expression VDSAT values versus VGS in saturation for NMOS and L = 100 nm. .................................................................

Fig. 2 .

 2 Fig. 2.42 ID -VDS characteristics for various VGS and for L = 100 nm showing two VDSAT definitions (Leti-UTSOI2 and 2/(gm/ID) expression). ...................................................... Fig. 3.1 gm1 over ID versus normalized drain current (ID.L/W) of NMOS (L = 1 µm) in saturation at VbG = {-4 V, 0 V, 5 V} and T = 25°C. ........................................................

Fig. 3 . 2

 32 Fig. 3.2 Gate capacitance Cgg versus front gate voltage VG of NMOS (L = 1 µm) in saturation at VbG = {-4 V, 0 V, 5 V} and T = 25 °C. Inset shows capacitance derivative ∂Cgg/∂VG. .........................................................................................................

Fig. 3 . 3

 33 Fig. 3.3 Measured gm1 over ID versus square shape drain current (ID.L/W) of NMOS and PMOS (L = 1 µm) in saturation at VbG = 0 V and T = 25 °C. .........................................

Fig. 3 . 4

 34 Fig. 3.4 Normalized transconductance efficiency versus IC of a NMOS and PMOS (L = 1 µm) in saturation at VbG = 0 V and T = 25 °C. .............................................................

Fig. 3 . 5

 35 Fig. 3.5 Normalized gm1 over ID as a function of the inversion coefficient at different VbG for NMOS (L = 1 µm & W = 1 µm) in saturation (VD = 1V) at T = 25 °C. ....................

Fig. 3 . 6

 36 Fig. 3.6 Transconductance efficiency curves delta versus VbG = 0V curve. ............................Fig. 3.7 Normalized gm1 over ID as a function of the inversion coefficient at different VbG for PMOS (L = 1 µm & W = 1 µm) in saturation (VD = -1 V) at T = 25 °C ................... Fig. 3.8 Normalized gm2 over ID as a function of the inversion coefficient at different VG for NMOS (L = 1 µm) in saturation (VD = 1V) at T = 25°C. ..........................................

Fig. 3 . 9

 39 Fig. 3.9 Measured gm1 over ID as a function of IC for fixed VbG and simultaneous front and back gates sweep with an offset for NMOS (L = 1 µm) in saturation (VD = 1V) at T = 25°C. ......................................................................................................................

Fig. 3 .

 3 Fig. 3.10 n1.UT.gm1/ID as a function of the inversion coefficient at different temperatures for NMOS (L = 300 nm & W = 1 µm) in saturation (VD = 1V) and VbG = 0 V; inset shows delta versus T = 125 ºC case. ................................................................................ Fig. 3.11 Normalized gm1 over ID as a function of the inversion coefficient for different lengths for NMOS (W = 1 µm) in saturation (VD = 1V) at T = 25°C. .............................

Fig. 3 .Fig. 3 .

 33 Fig. 3.12 Normalized gm1 over ID as a function of the inversion coefficient for different lengths for PMOS (W = 1 µm) in saturation (VD = 1V) at T = 25°C. ............................. Fig. 3.13 Normalized gm1 over ID as a function of the inversion coefficient at different VbG for NMOS (L = 30 nm & W = 1 µm) in saturation (VD = 1 V) at T = 25 °C. ..........

Fig. 3 .Fig. 3 .Fig. 3 .

 333 Fig. 3.14 n1.UT.gm1/ID as a function of the inversion coefficient at different temperatures for NMOS (L = 30 nm & W = 1 µm) in saturation (VD = 1V) and VbG = 0 V; inset shows delta versus T = 125 ºC case. ................................................................................ Fig. 3.15 Normalized gm1 over ID as a function of the inversion coefficient for different VD for NMOS (W = 1 µm and L = 1 µm) at T=25°C. ..................................................... Fig. 3.16 NMOS transconductance efficiency as a function of the inversion coefficient for different process corners (L = 1 µm & W = 1 µm) in saturation (VD = 1V) and VbG = 0 V; inset shows delta versus typical corner case. .................................................

Fig. 4 .

 4 Fig. 4.1 2-port RF structures setup for S-parameters measurement. ......................................

Fig. 4 .Fig. 4 . 3

 443 Fig. 4.2 2-port test structures using Ground-Signal-Ground probe pads ............................... Fig. 4.3 Schematics representing the DUT with parallel and series parasitic elements (B = bG). .............................................................................................................................

Fig. 4 . 4

 44 Fig. 4.4 Measured modulus (left) and phase (right) of the mutual transadmittance of an N Type MOSFET with L = 1 µm in saturation (VDS = 1 V). .............................................

Fig. 4 . 5

 45 Fig. 4.5 Measured phase of the mutual transadmittance of an N-Type MOSFET with L = 28 nm in saturation (VDS = 1 V). .................................................................................... Fig. 4.6 A representation of the two distribution effects in the channel (1) and in the gate finger (2). ........................................................................................................................ Fig. 4.7 UTBB FDSOI transistor architecture (3D). .............................................................. Fig. 4.8 RF equivalent schematic proposal with additional front-gate (Rg) and back-gate (RbG) resistances. Top: the core model. Bottom: the complete quasi-static model. .......

Fig. 4 . 9

 49 Fig. 4.9 The real part of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V). Model includes simplified front and back gates resistances and ignores NQS effect. .....................................................................................................................

Fig. 4 .Fig. 4 .

 44 Fig. 4.10 The real part of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V). Model includes front and back gates simplified resistances. Front gate resistance is tuned for SI. ...............................................................................................

Fig. 4 .

 4 Fig. 4.12 Channel segmentation using 5 series MOSFETs. ...................................................

Fig. 4 .

 4 Fig. 4.13 Non-quasi-static model with simplified gates models. ...........................................

Fig. 4 .Fig. 4 .Fig. 4 .

 444 Fig. 4.14 Gate resistance (left) and gate capacitance (right) vs. frequency for L = 1 µm and Wf = 1 µm. .............................................................................................................. Fig. 4.15 Front gate network with series and parallel RC lumped circuits. ........................... Fig. 4.16 Complete Non-Quasi-Static model. ........................................................................

Fig. 4 .

 4 Fig. 4.17 One side and two side gate access configurations. .................................................

Fig. 4 .Fig. 4 .

 44 Fig. 4.18 Simulation and measurements of the input admittance Y11 and input to output transadmittance Y21 of a 30 nm long NMOS vs. frequency for various gate to source voltages from WI to SI in saturation (VDS = 1 V). ......................................................... Fig. 4.19 Simulation and measurements of the input transadmittance Y11 and input to output transadmittance Y21 of 1 µm long NMOS vs. frequency for various gate to source voltages from WI to SI in saturation (VDS = 1 V)...............................................

Fig. 4 .

 4 Fig. 4.20 Mutual transadmittance ym = Y21-Y12 of a 1 µm long NMOS vs. frequency for various gate to source voltages from WI to SI in saturation (VDS = 1 V). .....................

Fig. 4 .

 4 Fig. 4.21 Measured and simulated mutual transadmittance phase of a 1 µm long NMOS vs. frequency for various Inversion Coefficients IC from WI to SI in saturation (VDS = 1 V). ............................................................................................................................ Fig. 4.22 Small signal current gain (|HDG|) vs. frequency (F) in linear mode VDS = 0.3 V for NMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C. ......................................

Fig. 4 .

 4 Fig. 4.23 Current gain |HDG| of a 30 nm long (left) and 1 µm long (right) N-type MOSFETs for various gate to source voltages VGS from WI to SI in saturation (VDS = 1 V). ............................................................................................................................

Fig. 4 .

 4 Fig. 4.24 Normalized transit frequency (fT) vs. normalized drain current Id = ID /(W/L) in linear mode |VDS| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C. .............................................................................................................. Fig. 4.25 Transit frequency fT versus IC of a short (L = 30 nm) and long (L = 1 µm) Ntype MOSFETs in saturation (VDS = 1 V). .....................................................................

Fig. 4 .Fig. 4 .

 44 Fig. 4.26 Mason gain vs. frequency (F) of NMOS (L = 30 nm) for various gate to source voltages in linear mode VDS = 0.25 V. ........................................................................... Fig. 4.27 Mason gain vs. frequency (F) of NMOS (L = 30 nm) for various gate to source voltages in saturation mode VDS = 1 V. Model w/o gates resistances (left) and with the gates networks (right). ..............................................................................................

Fig. 4 .Fig. 4 .

 44 Fig. 4.28 Normalized fmax vs. the normalized drain current Id in linear mode |VDS| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C. ................... Fig. 4.29 Normalized fmax vs. drain current Id in linear mode (i.e. |VDS| = 0.3 V) for NMOS and for following frequencies: 10 GHz, 20 GHz, 30 GHz, 40 GHz, 50 GHz, 70 GHz and 80 GHz (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C. ....................................

Fig. 4 .

 4 Fig. 4.30 fmax vs. IC for NMOS L = 30 nm for various VDS from linear to saturation...........

Fig. 4 .

 4 Fig. 4.31 FoMRF vs. Id in linear operation |VDS| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C. .....................................................................

Fig. 5 .

 5 Fig. 5.1 3-D plot of the measured transadmittance efficiency modulus versus the frequency and inversion coefficient IC for L = 1 µm at VDS = 1 V. ..............................

Fig. 5 . 2

 52 Fig. 5.2 Measured transadmittance efficiency modulus versus the frequency for different IC for a NMOS (L = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V. ..........................

Fig. 5 . 3

 53 Fig. 5.3 Measured phase of the transadmittance over ID versus frequency at different IC for NMOS (L = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V. ..................................

Fig. 5 . 4

 54 Fig. 5.4 Measured phase of the transadmittance over ID versus frequency at different IC for PMOS L = 1 µm (left) and L = 300 nm (right) in saturation (VDS = -1 V) and VbG = 0 V. .............................................................................................................................. Fig. 5.5 Normalized transadmittance magnitude over ID versus normalized frequency Fnorm1 at different IC for NMOS (L = 1 µm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements). .....................................................................................

Fig. 5 . 6

 56 Fig. 5.6 Phase of the transadmittance over ID versus normalized frequency Fnorm1 at different IC for NMOS (L = 1 µm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements). ...................................................................................................

Fig. 5 . 7 Fig. 5 . 8 Fig. 5 . 9

 575859 Fig. 5.7 Phase of the transadmittance over ID versus frequency at different IC for NMOS (L = 300 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements). ........................................................................................................................................

Fig. 5 .Fig. 5 .

 55 Fig. 5.10 Frequency error versus phase shift after normalization using Ftot (IC = 93.1 is taken as a reference) ....................................................................................................... Fig. 5.11 Measured phase of the transadmittance over ID versus frequency at different IC for NMOS (L = 28 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V. ...........

Fig. 5 .

 5 Fig. 5.12 Measured phase of the transadmittance over ID versus frequency at different IC for PMOS (L = 28 nm & W = 1 µm) in saturation (VDS = -1 V) and VbG = 0 V. ..........

Fig. 5 .

 5 Fig. 5.13 Phase of the transadmittance over ID versus the normalized frequency Fnorm1 estimated with a constant mobility at different IC for NMOS (L = 28 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements). ....................................

Fig. 5 .

 5 Fig. 5.14 Phase of the transadmittance over ID versus normalized frequency Fnorm2 with constant mobility at different IC for NMOS (L = 28 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements). .................................................................

Fig. 5 .

 5 Fig. 5.15 Measured |HDG| versus normalized frequency Fnorm1 at different IC for NMOS (L = 1 µm & W = 1 µm), (VDS = 1 V) and VbG = 0 V. Inset shows |HDG| versus F/FcritSI where FcritSI is given by (5.6). ............................................................................ Fig. 5.16 Transit frequency fT versus IC at two different back gate voltages VbG (blue: VbG = 0 V and red: VbG = 2 V) for NMOS (L = 100 nm) in saturation (VDS = 1 V) (4-port Measurements). ..................................................................................................

Fig. 5 .

 5 Fig. 5.17 Simulated transadmittance efficiency modulus versus frequency at different VbG for NMOS (L = 1 µm) in saturation (VDS = 1 V) and VGS=0.5V (TCAD). ...................

Fig. 5 .

 5 Fig. 5.18 Normalized transadmittance efficiency modulus versus normalized frequency Fnorm at different VbG for NMOS (L = 1 µm) in saturation (VDS=1V) and VGS = 0.5 V (TCAD). .....................................................................................................................

Fig. 5 .Fig. 5 .Fig. 5 .

 555 Fig. 5.19 Simulated phase of the transadmittance efficiency versus normalized frequency Fnorm at different VbG for NMOS (L = 1 µm) in saturation (VDS= 1V) and VGS = 0.5 V (TCAD). .....................................................................................................................

Fig. 5 .Fig. 6 . 1

 561 Fig. 5.22 Mobility versus gate voltage overdrive for L = 0.3 µm extracted using various methods: Fcrit based, fT based, classical Y function with iteration, Lambert-W Split C-V based, and Fcrit based with correction of the distributed gate effect. ...................... Fig. 6.1 Square law model and weak inversion exponential model failures to predict measured gm/ID in MI for a long and short channel devices. VTH is defined here as the VGS at the maximum of ∂Cgc/∂VGS. ..........................................................................

Fig. 6 . 2 Fig. 6 . 3 Fig. 6 . 4 Fig. 6 . 5 Fig. 6 . 9

 6263646569 Fig. 6.2 Measured gate to channel capacitance normalized using front oxide capacitance (Cox.W.L) with respect to VGS for various VbG and its derivative (Inset) for N-type UTBB FDSOI MOSFET. ...............................................................................................Fig. 6.3 Comparison of DIBL between FDSOI and bulk in saturation (VDS=1V) and VbG = 0 V. .............................................................................................................................. Fig. 6.4 Measured fT versus IC for various MOSFET lengths in saturation (VDS=1V). Inset gives a focus on the second part of the MI (1 < IC < 10) ...................................... Fig. 6.5 Measured and normalized |Y21| versus frequency for various lengths and finger length is 1 µm. ................................................................................................................ Fig. 6.6 Phase shift of the transadmittance Y21 versus frequency for various lengths and finger length is 1 µm. ..................................................................................................... Fig. 6.7 gm over ID charts versus IC for several short NMOS along with a longer channel (L = 1 µm) for comparison. ............................................................................................Fig. 6.8 LNA cascode circuit. ................................................................................................Fig. 6.9 FoM versus IC for two lengths. ................................................................................

Fig. 6 .

 6 Fig. 6.10 NFMIN noise figure vs. IC for various lengths in saturation. ...................................

Fig. 6 .Fig. 6 .Fig. 6 .

 666 Fig. 6.11 Inversion Coefficient vs. gate voltage overdrive for two lengths L = 40 nm and L = 70 nm. ...................................................................................................................... Fig. 6.12 Power gain S21, Input Match S11, and minimal noise figure NFmin with respect to frequency for two LNA circuits (first with MOSFET length of 40 nm and second with 70 nm). ...................................................................................................................

  improve life by providing quick tracking and diagnostics, and have become ubiquitous over the last few years. The main reasons of this spectacular spread are the low price and high performance. Still, the powerconsumption remains one of the major barriers somehow preventing the complete achievement of the wider Network of Things. With the emergence of the Internet of Things (IoT), there has been rising interest in fast, low-cost and low-power Systems-On-Chip (SoCs) to satisfy the thirst for sensing and communicating in a continuous and unnoticeable way. The popularity of these devices and things is due mainly to advances in the semiconductor industry which have promoted low-cost, low-power and high speed Integrated Circuits (ICs) through aggressive scaling[1].Background and MotivationSilicon technology has been driven for years by downscaling dictated by the high-performance integrated digital circuits. Today, further reduction of transistor dimensions is critical due to intrinsic limitations such as short channel effects. To overcome these challenges, semiconductor industry strategies include the use of new materials and revolutionary device architectures such as Multiple-Gate (MG). Moreover, shrinking the thickness of the silicon body is proposed in the case of planar ultra-thin Body and Box (UTBB) fully depleted (FD) Silicon-on-Insulator (SOI) doublegate (DG) MOSFET, and vertical FinFET [2][3][4][5].

[ 23 ]

 23 [24][25][14]. Fig. 1.2 shows a benchmarking of the transit frequency fT of various state-of-the-art MOSFETs versus gate length. UTBB FDSOI shows higher fT versus FinFET thanks to the reduced parasitic resistance and capacitance elements. Moreover, the ITRS (International Technology Roadmap for Semiconductors) expectations are met by UTBB FDSOI and confirmed by our measurements of a nominal L = 30 nm length NMOS and PMOS devices as depicted in Fig. 1.3.

Fig. 1 . 1

 11 Fig. 1.1 FinFET (left) and UTBB FDSOI (right) similarity.

Fig. 1 . 3

 13 Fig. 1.3 Measured fT versus normalized drain current ID/(W/L) for UTBB FDSOI NMOS and PMOS (L = 30 nm, Nf = 20, Wf = 1µm, V DS = 1 V).

Fig. 1 .Fig. 1 . 4

 114 Fig. 1.4 Simulated electron density in the silicon film at different back gate voltages VbG for a UTBB FDSOI NMOS (L = 1 µm & W = 1 µm) in saturation V DS = 1 V and strong inversion (at constant VGS = 1 V).

Fig. 1 .

 1 Fig. 1.5 UNIBOND fabrication process with Smart CutIn the UTBB FDSOI technology, MOSFET channel is formed in a thin silicon film separated from the substrate by an oxide film called Buried OXide (BOX) as depicted in Fig.1.6. In 28 nm FDSOI technology from STMicroelectronics, final silicon film is 7 nm thick and BOX is 25 nm thick after a few process steps[3]. This architecture provides with multiple advantages for high performance and low power applications. In addition of the well-known SOI technology advantages[38][39], UTBB FDSOI technology features lower parasitic capacitances as depicted in Fig.1.7, and consequently high-speed operation. The harmful parasitic substrate coupling is avoided in the UTBB FDSOI by the introduction of the Ground Plane (GP) which is a highly doped region underneath the thin BOX[40]. The ground-plane implantation under the BOX is well-type in the structures studied in this research work. This highly doped layer underneath the BOX opens various possibilities to tune the device threshold Voltage (VTH)[41] and extends the usage of the MOSFET back biasing to dynamically optimize the power consumption[42].

Fig. 1 . 6

 16 Fig. 1.6 Cross section (left) and TEM (right [3]) of the UTBB FDSOI MOSFET

Fig. 1 . 7

 17 Fig. 1.7 Cross section comparison between bulk MOSFET (right) and UTBB FDSOI (left)

Fig. 1 . 8

 18 Fig. 1.8 Measured and normalized drain current ID/(W/L) versus front gate voltage VGS for various back gate voltages VbG in semi logarithmic scale for L = 1 µm, W = 10 µm at VDS = 1 V.

Fig. 1 . 9

 19 Fig. 1.9 Bulk MOSFET (left) versus UTBB FDSOI MOSFET (right).

Fig. 1 .

 1 Fig. 1.10 Comparison of DIBL between FDSOI 28 nm and bulk 28nm technologies in saturation (VDS = 1 V) and VbG = 0 V.One of the key features of SOI CMOS structures is the smaller junction capacitances in comparison to bulk CMOS structures. The junction capacitances in UTBB FDSOI, with thin silicon film, are negligibly small. Moreover, in UTBB FDSOI MOSFET, the capacitance between the drain (source) and the substrate is negligibly small thanks to the thickness of the BOX, and the dielectric constant of the BOX SiO2, which is lower than that of Si.

FDSOI is less subject

  to SCE, and the ID-VGS is closer to the classical square law as shown in the inset of Fig. 1.11. The goal of all the research work in semiconductor industry in the last decades is to keep the subthreshold slope as high as possible in Weak Inversion and the square law trend as long as possible in SI. The UTBB FDSOI seems to be near to the ultimate technology. For short channel devices, all the aforementioned short channel effects are more amplified in bulk in comparison to UTBB FDSOI.

  e. ~ 1/sqrt(ID) frequency operation. An augmented version of the Meyer model is shown in Fig. 1.12

Fig. 1 .

 1 Fig. 1.12 Modified Meyer equivalent circuit. Compact models of semiconductor devices are mathematical descriptions of their complex behavior, and usually implemented in a computer language such as Verilog-A. Compact models simulations are fast despite the complex and lengthy codes, and are systematically used for IC simulation earlier to an expensive production process. Moreover, compact models are flexible enough to describe MOSFETs fabricated in different foundries. Standard compact models go through extensive qualification within semiconductor foundries and fabless industrials that are organized into an industry consortium, namely Compact Model Coalition (CMC). It should be

  1.

Fig. 1 .

 1 Fig. 1.13 Regions of operation on the front and back gates voltages plane for an imref splitting Vc = 0.5V, Tsi = 20 nm, Tox1 = 2 nm, and Tox2 = 40 nm. V1 and V2 are the front and back gate voltages respectively [57].

  of a 210 nm width are used for calibration. C-V characteristics are used to set the dielectric material properties as well as the work function of the back gate. Mobility model calibration is taken care of using transconductance gm in linear mode and including doping dependence, Philips unified mobility, remote Coulomb and Phonon scattering, and ballistic transport. The transconductance calibration at high field is taking into account the self-heating effect. Moreover, doping and temperature dependent Shockley-Read-Hall (SRH) recombination model are all accounted for as well.

Fig. 2 .

 2 Fig. 2.1 UTBB transistor architecture (cross-section) with modeled charges as well as front and back surface potentials.

Fig. 2 . 2

 22 Fig. 2.2 Measured and normalized front gate capacitance versus front gate voltage for various back gate voltages for NMOS and at VDS = 0 V (L = 10 µm, W = 2 µm, MULT = 30). Inset: diagram showing C-V measurement procedure.

Fig. 2 . 3

 23 Fig. 2.3 Measured and normalized front gate capacitance versus front gate voltage for various back gate voltages for PMOS and at VDS = 0 V (L = 10 µm, W = 2 µm, MULT = 30).

Fig. 2 .

 2 Fig.2.5 along with the corresponding carriers concentration evolution in the silicon film with respect to VGS for VbG = 7 V in Fig.2.6. For higher VbG, the back interface is inverted first, which corresponds to the local maximum of the capacitance derivative at low VGS. A cross section view for this situation is shown in Fig.2.7 (b) where carrier's concentration near the back interface is higher. The second local maximum occurs when the front interface is inverted at VGS ≈ 0.6 V. This is evidenced in Fig.2.6 where carrier concentration is almost constant in the volume of the silicon film with a local maximum near the front gate for VGS = 1 V. In Fig.2.7, the electrons concentration at VGS = 0 V (a) is very low as the channel is not inverted. The concentration is maximum close to the back interface at lower VGS = 0.3 V (b) and maximum at the front interface for VGS = 1 V (c). Actually, the carriers occupy all the thickness of the silicon film. The concentration of the carriers is maximizing locally based on the applied gate voltage.

Fig. 2 . 4

 24 Fig. 2.4 Measured gate capacitance derivatives versus VGS for various back gate voltages for NMOS (L = 10 µm, W = 2 µm, MULT = 30).

Fig. 2 .

 2 Fig. 2.5 TCAD simulations of the gate capacitance versus VGS for three VbG values (-7 V, 0 V, and 7 V) for L = 1 µm and VDS = 1 V.

Fig. 2 . 6 Fig. 2 . 7

 2627 Fig. 2.6 Electron concentration versus position in the silicon film for various VGS values and fixed VbG = 7 V for L = 1 µm and VDS = 1 V.

Fig. 2 . 8

 28 Fig. 2.8 Front gate threshold voltage VTH versus back gate voltage VbG for NMOS (L = 10 µm, W = 2 µm, MULT = 30)

Fig. 2 . 9

 29 Fig. 2.9 Measured and normalized drain current (i.e. ID/(W/L)) versus front gate voltage VGS for VDS = 1 V and various back gate voltages for NMOS (L = 1 µm, W = 1 µm).

Fig. 2 .

 2 Fig. 2.10 Measured gm over ID characteristics versus normalized drain current ID/(W/L) for various back gate voltages VbG along with the WI and SI trends for NMOS (L = 1 µm, W = 1 µm, VDS = 1 V).

Fig. 2 .

 2 Fig. 2.11 Measured gm over ID derivative versus front gate voltage for VDS = 0.05 V and various back gate voltages for NMOS (L = 1 µm, W = 1 µm).

2 .

 2 13 where capacitance and gm/ID based threshold voltages are close for VbG = 5 V in (a) and (b). At VbG = 10 V, the negative threshold voltage result is close to the -

Fig. 2 .

 2 Fig. 2.12 TCAD simulations showing the impact of the back gate voltage on carriers concentration and consequently on input characteristic ID -VGS. (a) ID -VGS for various VbG from -10 V to 8 V. (b) channel inversion at the front for negative VbG = -10 V (c) channel inversion in silicon film volume at VbG = 0 V, and (d) channel inversion local maximum near the back interface for VbG = 8 V. Distance unit is µm.

Fig. 2 .

 2 Fig. 2.13 TCAD simulations showing (a) Cgc and its derivative for VbG = 5 V (b) derivative of gm/ID for VbG = 5 V, and (c) Cgc and its derivative for VbG = 10 V, L = 1 µm and VDS = 1 V The electrostatic part of (2.8) is shown in Fig. 2.14 (b) with respect to the normalized drain current. The gm over ID is measured in linear mode (VDS = 0.05 V) to be as close as possible to the Cgc-VGS bias conditions. The gm over ID plots are shown in Fig. 2.14 (a) where the invariance is evidenced for linear mode too. The transport contribution to the gm over ID is finally depicted in Fig. 2.15 with respect to both VGS in (a) and ID.L/W

Fig. 2 .

 2 Fig. 2.14 Measurements showing (a) gm over ID and (b) ∂(ln(Qinv)/∂VGS versus normalized drain current for various VbG values (from -3 V to 3 V) in linear mode (VDS = 50 mV).

Fig. 2 .

 2 Fig. 2.15 Measurements showing the transport term ∂ln(v)/∂VGS versus gate voltage VGS in (a) and normalized drain current in (b) for various VbG values (from -3 V to 3 V) in linear mode (L = 1 µm, W = 1 µm).

Fig. 2 .

 2 Fig. 2.16 Cross section of the bulk MOSFET for VD = VS (N-type)

Fig. 2 .

 2 Fig. 2.17 shows a cross section of the UTBB FDSOI under study. This structure has different front and back oxide thicknesses and different gate work-functions. A lightlydoped silicon film is assumed. Using the gradual channel approximation, the potential in the silicon film is obtained by solving the 1-D Poisson's equation and taking Gauss's law at the front and back surfaces as the boundary conditions. Then, front and back inversion charges are derived using the calculated front and back surface potentials.

Fig. 2 .

 2 Fig.2.17 FDSOI UTBB transistor architecture (cross-section) with involved charges as well as front and back surface potentials.

2. 3 . 2

 32 Equivalent low frequency small signal circuit UTBB FDSOI small-signal equivalent schematic valid in low-frequency operation is depicted in Fig.2.18. It includes intrinsic MOSFET components such as the front transconductance gm1 and extrinsic elements such as source and drain series resistances (i.e. RS and RD, respectively). The explicit series resistances shown in Fig.2.18 are taken into account in UTSOI2 implicitly in the mobility reduction saving some CPU time during circuit simulations as two circuit nodes are skipped. Gate-to-source (Cgs), gate-to-drain (Cgd) and front-to-back gates (Cgb) capacitances are also included as shown in Fig.2.18. It should be noted that the equivalent circuit elements (i.e. capacitances and resistances) include both intrinsic and extrinsic parts. It is important to distinguish between the intrinsic (denoted by 'i') and extrinsic (denoted by 'e') contributions that have different origins. The intrinsic part is related to the device itself and mainly useful for channel current modulation, while the extrinsic part is related to parasitic elements unnecessary for the device operation. The extrinsic part can be optimized using proper layout technics such as multi-finger layout but cannot be completely removed. At high frequency operation the extrinsic elements gain particular importance and must be carefully modeled. At mm-Wave operation, these parasitic elements can even dominate the device performance.The small-signal equivalent circuit depicted in Fig.2.18 is frequently used in the literature to model small-signal operation of the MOSFET. This circuit was first proposed by Meyer in early semiconductor modeling life and enriched gradually. It represents the main channel modulation effect through gm along with the coupling effects of other terminals on MOSFET gate terminal through the three capacitances Cgs, Cgd and Cgb. All the coupling effects represented in this equivalent circuit are extracted and validated under quasi-static operation. The quasi-static operation is defined when an applied small signal varies sufficiently slowly that the carriers in the channel can follow the variation simultaneously.

Fig. 2 .

 2 Fig. 2.18 Equivalent schematic for small signal and low-frequency operation of the UTBB FDSOI including series resistances RS and RD (Cgd = Cgdi + Cgde and Cgs = Cgsi + Cgse).

Fig. 2 .

 2 Fig. 2.19 NMOS gate to drain transadmittance phase (left) and modulus (right) simulated using Leti-UTSOI2 and the small signal equivalent circuit in Fig. 2.18. L = 1 µm, W = 10 µm, NF = 10, and VGS = VDS = 1 V.

  2.20 including series drain and source resistors. It should be noted that Csd is included when required in particular for short channels. In saturation, the new equivalent circuit provides strictly the same results as the Leti-UTSOI2 model as shown in Fig. 2.21.

Fig. 2 .

 2 Fig. 2.20 Equivalent schematic for small signal and quasi-static operation of the UTBB FDSOI MOSFET including series resistances RS and RD (Cgd = Cgdi + Cgde and Cgs = Cgsi + Cgse).

Fig. 2 .

 2 Fig. 2.21 NMOS gate to drain transadmittance phase (left) and modulus (right) simulated using Leti-UTSOI2 and the quasi-static small signal equivalent circuit in Fig. 2.20. L = 1 µm, W = 10 µm, NF = 10, and VGS = VDS = 1 V.

  and low frequency characterization DC and C-V operations accuracy is a prerequisite for analog and RF modeling. All model parameters are extracted based on dedicated structures and following predefined flows. Two different structures are characterized in this work. First, the simple DC structures generally adapted to digital or low frequency analog applications. An example of this type of structures is shown in Fig. 2.22. These simple structures are used for scalable core model extraction. Several other variants of this type of structures are adapted to extract advanced effects such as mismatch, STI stress, and Well-Proximity effect (WPE). The other type of structures (usually called RF structures) is dedicated to high frequency characterization using scattering parameters (Sparameters) measurement. This type of structures is depicted in Fig. 2.23, where multiple fingers are used to increase the device width (bias current) and optimize the dynamic behavior without degrading the gate resistance, which is detrimental at high frequency operation. These structures are optimized to have higher gain and higher transit frequency at the cost of increased footprint and layout complexity.

Fig. 2 .

 2 Fig. 2.22 DC structure illustration.

Fig. 2 .

 2 Fig. 2.23 RF multi-finger structure with a finger length of Wf = 10 µm.

Fig. 2 .

 2 Fig. 2.24 (Top) SHORT structure equivalent schematic used to extract parasitic external resistances Rg_ext, Rd_ext and Rsb_ext (gate, drain and common source and back gate terminals series resistances respectively, source and back gate being shorted). (Bottom) an illustration of the performed optimization. Several gate lengths and widths are measured and used for DC parameters extraction purpose. Long and wide structures are first used to extract main model parameters such as front oxide and BOX thicknesses, gates work-functions, effective and saturated mobility parameters and gate leakage. Short and narrow devices are then used to extract small geometry effects parameters. The minimal characterized MOSFET length and width are respectively 28 nm and 80 nm.

  DC extraction: Short / Wide transistor in saturation regime DIBL @ various V bG and T DIBL @ various V bG with CLM Saturation velocity and CLM w/o SHE Saturation velocity, DIBL and CLM with SHE at various V bG DC extraction: Long / Wide MOSFET with updated series resistances V TH and Mobility (for various V bG ) Sub-threshold and its T dependence Saturation DC extraction: Short / Wide transistor in linear regime subthreshold & low field mobility subthreshold at various Vb CLM vs. V G and V bG Series resistance Sub-threshold T dependence DC extraction: Long / Wide MOSFET Vt & low field mobility Sub-threshold Mobility Temperature dependence Saturation AC extraction: Long / Wide MOSFET capacitance Parasitic fringe capacitance Front EOT T BOX & GP doping concentration Tsi

Fig. 2 .

 2 25 shows the transfer characteristic for NMOS and PMOS considering short and long channels. The normalized drain current in logarithmic scale is convenient to capture weak and moderate inversion behaviors while the linear scale highlights the strong inversion region as shown in Fig.2.26.

Fig. 2 . 2 VFig. 2 .

 222 Fig. 2.25 Normalized drain current Id vs. gate voltage overdrive in linear operation |VDS| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C.

Fig. 2 .

 2 Fig. 2.30 Normalized Cgg and Cgd vs. gate voltage overdrive TYPE.(VG -VTH) in linear mode |VD| = 0.3 V for NMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C and frequency = 100 MHz.

Fig. 2 .

 2 Fig. 2.32 Smith chart showing the input and output S-parameters simulated using the proposed equivalent circuit in Fig. 2.18 and the Leti-UTSOI2 of L = 1 µm NMOS in saturation (VDS = 1 V).

Fig. 2 .

 2 Fig. 2.33 Polar chart showing the input to output and output to input S-parameters simulated using the proposed equivalent circuit in Fig. 2.18 and the Leti-UTSOI2 of L = 1 µm NMOS in saturation (VDS = 1 V).

Fig. 2 .

 2 Fig. 2.34 Y-parameters simulated using the proposed equivalent circuit in Fig. 2.18 and the Leti-UTSOI2 of L = 1 µm NMOS in saturation (VDS = 1 V).

Fig. 2 .

 2 35 shows the measured mutual transadmittance for a long channel MOSFET compared with the quasi-static UTSOI2 model simulations, which provides same results as the proposed equivalent circuit. Both models are clearly valid only up to 1 GHz and do not reproduce the performance degradation (i.e. 'transconductance' decrease) at high frequency.

Fig. 2 .

 2 Fig. 2.35 The real part of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V)

Fig. 2 .

 2 Fig. 2.36 The phase of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V) Measurements show negative real part of the transadmittance at high frequency, which means that the phase shift is greater than 90°. This is confirmed in Fig. 2.36 where ym phase is shown versus frequency. The quasi-static model is valid up to 1 GHz for VGS = 0.4 V (i.e. IC = 0.3) and up to 8 GHz for VGS = 1 V (i.e. IC = 109). The simulated phase tends to -90° for WI and SI while measurements show a clear antiphase phenomena. An enhancement of the model will be proposed in Chapter 4 for high frequency operation.

Fig. 2 .

 2 Fig.2.37 shows a simplified sub-circuit example of a RF MOSFET device with an external front gate resistor, series source and drain resistors and extrinsic capacitors. If DC V GS and V DS voltages are applied to the gate and drain terminals respectively while source and bulk or back gate are grounded, SPICE simulator provides OP information regarding all sub-circuit components separately (i.e. Cgs and VTH of MOSFET M1, RS, Cgse, etc.). The voltage drop between the internal MOSFET terminals Gi and Si is different from the real VGS applied to the device. Thus, the threshold voltage provided by existing simulators for M1 at the given V DS voltage is not accurate. Moreover, the Cgs capacitance of the real device is not retrieved by a sum of

Fig. 2 .

 2 Fig. 2.37 A sub-circuit example of a RF MOSFET (B instead of bG in bulk).

Fig. 2 .

 2 Fig. 2.38 Comparison of OP Info capacitances and extracted counterparts in saturation VDS=1V for NMOS (L = 1 µm and W = 0.5 µm).

Fig. 2 .

 2 Fig. 2.39 Comparison of the Leti-UTSOI2 and 2/(gm/ID) expression VDSAT values versus VGS in saturation for NMOS and L = 2µm.

Fig. 2 .

 2 Fig. 2.41 Comparison of the Leti-UTSOI2 and 2/(gm/ID) expression VDSAT values versus VGS in saturation for NMOS and L = 100 nm.

Fig. 2 .

 2 Fig. 2.42 ID -VDS characteristics for various VGS and for L = 100 nm showing two VDSAT definitions (Leti-UTSOI2 and 2/(gm/ID) expression).

  The long channel I-V model of the UTBB FDSOI MOSFET showed deep similarities with bulk counterpart. In particular, the WI and SI trends are identical provided short channel effects are neglected. The DG MOSFET SI square law model, which is still in use in advanced technologies besides multiple limitations, is assessed through the threshold voltage parameter derivation for a long channel. The bulk square law model can be re-used provided that VTH dependence on VbG is correctly modeled.However, for production circuit simulation, the proposed charts in next Chapters and UTSOI2 model should be used as both account for all involved physical effects in a UTBB FDSOI MOSFET.For small signal dynamic operation, a simple model is proposed for the core of the UTBB FDSOI MOSFET. The proposed model should be carefully used and the corresponding assumptions are verified.In order to obtain the parameters of the small signal equivalent circuit or the UTSOI2 model, DC and low frequency characterization is carried out using DC and RF structures. RF structures along with the de-embeding structures are helpful to gain insight into the DC characterization as the series parasitics are extracted accurately and accounted for in the simulation.The comparison between the extracted model and the measurements validatesthe capabilities of the model to accurately reproduce the DC and low frequency behavior of the UTBB FDSOI MOSFET. Both NMOS and PMOS are extracted and compared for several bias conditions with a focus on moderate inversion. Both UTSOI2 and the equivalent circuit based models are able to accurately capture the low frequency behavior over more than seven decades of current from WI to SI. However, the high frequency measured data are not captured at high frequency by both quasistatic models as shown in Fig.2.35 and Fig.2.36 because of non-quasi-static effects.A non-quasi-static model will be developed in Chapter 4.The operating point information feature provided by the main SPICE simulators today is subject to several limitations that are discussed. In particular, the information provided to analog designers for advanced sub-circuit based RF models is inaccurate.The reason for this inaccuracy is the fact that all simulators rely on the information specified for individual lumped elements and ignore the complexity of parasitic aware models. An enhancement of this important feature has been proposed to the main EDA vendors, namely Mentor Graphics, Synopsys and Cadence, and is already implemented in recent simulators versions. Attempts to standardize the DC OP information are ongoing within CMC organization (DC OP Info subcommittee and PSP subcommittee).Chapter 3 g m over I D invariance assessment3.1 IntroductionDouble gate fully depleted MOSFETs exhibit a large inherent immunity to short channel effects, a steeper subthreshold slope and a higher drive current[26]. The independent double gate architecture is further enlarging circuit design space as the two gates can be independently controlled. These advanced structures, as discussed in Chapter 1, are chosen to continue the aggressive CMOS technology down-scaling and demonstrate excellent digital and analog performances especially in low-power applications[10][14].

  To assess the invariance of the transconductance efficiency versus normalized current chart, electrical ID-VG and Cgg-VG characteristics have been first obtained using TCAD simulations based on constant mobility model. The simulated N-channel MOSFET device is an UTBB FDSOI MOSFET. Si body, BOX and equivalent gate oxide thicknesses are 7 nm, 25 nm and 1.3 nm, respectively. ID-VG and Cgg-VG characteristics are simulated in saturation for various back gate voltages VbG while source is grounded (all voltages in this Chapter are referred to the source). Fig.3.1 shows the gm1/ID as a function of the normalized drain current ID.L/W with back gate voltage VbG as a parameter (gm1 is the front gate transconductance, W and L are width and length of the device respectively) and a focus on MI and SI. As current increases for high forward back gate voltage (VbG = 5 V), the back-channel inversion occurs first and results in a lower transconductance efficiency and lower subthreshold slope (i.e. higher "body effect"), corresponding to a lower equivalent front capacitance (front gate oxide capacitance in series with the silicon film capacitance). The transconductance efficiency for VbG = 5 V tends towards the VbG = 0 V curve at higher current (higher VG) when the front channel inversion occurs. It should be noted that transconductance efficiency behavior at constant mobility is related to the Cgg capacitance (electrostatic) shown in Fig.3.2. Indeed, Cgg-VG curve at high forward back gate voltage VbG = 5 V reveals the two interfaces (back and front) activation corresponding to the two pronounced peaks of the Cgg derivative (inset in Fig.3.2). The gm1/ID versus normalized drain current curves for VbG = 5 V and VbG = 0 V do not superpose (delta is greater than 15%) and hence TCAD simulations with constant mobility model do not unambiguously comfort/demonstrate the sought invariance for an asymmetric double gate MOSFET.

Fig. 3 .

 3 Fig. 3.1 gm1 over ID versus normalized drain current (ID.L/W) of NMOS (L = 1 µm) in saturation at VbG = {-4 V, 0 V, 5 V} and T = 25°C.

Fig. 3 . 2

 32 Fig. 3.2 Gate capacitance Cgg versus front gate voltage VG of NMOS (L = 1 µm) in saturation at VbG = {-4 V, 0 V, 5 V} and T = 25 °C. Inset shows capacitance derivative ∂Cgg/∂VG.

Fig. 3 . 3

 33 Fig. 3.3 Measured gm1 over ID versus square shape drain current (ID.L/W) of NMOS and PMOS (L = 1 µm) in saturation at VbG = 0 V and T = 25 °C.

  field, which in turn depends on front and back gate voltages. In the same model, the two ideality factors or namely front and back coupling factors n1 and n2 depend on the front or back channels activation. The explicit threshold based ID model considers two

  channel and P-channel MOSFETs range from 28 nm to 4 µm and from 80 nm to 5 µm respectively. Drain current versus gate voltage ID-VG curves are measured at different drain voltages VD (linear 50 mV to saturation 1 V), different back gate voltages VbG (from -4V to 5V) and different temperatures (-40 ºC, 0 ºC, 25 ºC, 80 ºC and 125 ºC).

Fig. 3 . 4

 34 Fig. 3.4 Normalized transconductance efficiency versus IC of a NMOS and PMOS (L = 1 µm) in saturation at VbG = 0 V and T = 25 °C.

Fig. 3 . 5

 35 Fig. 3.5 Normalized gm1 over ID as a function of the inversion coefficient at different VbG for NMOS (L = 1 µm & W = 1 µm) in saturation (VD = 1V) at T = 25 °C.

Fig. 3 . 6

 36 Fig. 3.6 Transconductance efficiency curves delta versus VbG = 0V curve.

Fig. 3 . 7

 37 Fig. 3.7 Normalized gm1 over ID as a function of the inversion coefficient at different VbG for PMOS (L = 1 µm & W = 1 µm) in saturation (VD = -1 V) at T = 25 °C

  back technology current I2. The technology current I2 varies between 0.3 µA and 1.3 µA while front gate voltage VG is varied from -0.3 V to 0.6 V.Considering an invariant chart of the back transconductance efficiency gm2/ID vs. IC generates a less than 20 % error in weak and moderate inversion.

Fig. 3 . 8

 38 Fig. 3.8 Normalized gm2 over ID as a function of the inversion coefficient at different VG for NMOS (L = 1 µm) in saturation (VD = 1V) at T = 25°C.

Fig. 3 . 9

 39 Fig. 3.9 Measured gm1 over ID as a function of IC for fixed VbG and simultaneous front and back gates sweep with an offset for NMOS (L = 1 µm) in saturation (VD = 1V) at T = 25°C.

Fig. 3 .

 3 Fig. 3.10 n1.UT.gm1/ID as a function of the inversion coefficient at different temperatures for NMOS (L = 300 nm & W = 1 µm) in saturation (VD = 1V) and VbG = 0 V; inset shows delta versus T = 125 ºC case.

Fig. 3 .Fig. 3 .Fig. 3 .

 333 Fig. 3.11 Normalized gm1 over ID as a function of the inversion coefficient for different lengths for NMOS (W = 1 µm) in saturation (VD = 1V) at T = 25°C.

Fig. 3 .Fig. 3 .

 33 Fig. 3.13 Normalized gm1 over ID as a function of the inversion coefficient at different VbG for NMOS (L = 30 nm & W = 1 µm) in saturation (VD = 1 V) at T = 25 °C.

Fig. 3 .

 3 Fig. 3.15 shows normalized transconductance efficiency versus IC for different drain to source voltages. In linear regime, the gm1/ID curve departs from the saturation and strong inversion asymptotic behavior and follows the 1/IC asymptote instead (also shown in Fig. 3.15). The transconductance efficiency chart defined at VD = 1 V can be used for lower drain to source voltages down to VD = 250 mV in weak and moderate inversion (with an error of less than 4%).

Fig. 3 .

 3 Fig. 3.15 Normalized gm1 over ID as a function of the inversion coefficient for different VD for NMOS (W = 1 µm and L = 1 µm) at T=25°C.

Fig. 3 .

 3 Fig. 3.16 NMOS transconductance efficiency as a function of the inversion coefficient for different process corners (L = 1 µm & W = 1 µm) in saturation (VD = 1V) and VbG = 0 V; inset shows delta versus typical corner case.

  Only DC-based extraction leads to RF performance overestimation therefore RF extraction is required to mitigate high frequency operation real performances. The characterization using S-parameters measurements and de-embedding procedures is a method of choice for mm-Wave spectrum operation assessment. Accurate characterization needs several correction steps to get rid of the measurement setup and pads related parasitic elements, and consequently set the reference plan close enough to the intrinsic DUT.Model parameters are determined using extraction routines applied to measured characteristics. Dedicated test structures are measured in order to assess the different properties of the device and the several effects involved. Measurements are performed under various bias conditions, temperatures, and frequencies. As presented in Chapter 2, MOSFET characterization starts with DC and low frequency C-V measurements of several MOSFET geometries using voltmeter, ammeter, and LCR meter. For high frequency RF small-signal characterization in particular up to the mm-Wave spectrum, scattering (S-) parameters of dedicated structures are measured using a vector network analyzer (VNA), which measures the vector ratio of reflected and transmitted wave energy components in regard to incident energy component.Multi-finger MOSFET structures are embedded in Coplanar Waveguide (CPW) pads for high frequency characterization. Multi-finger and wide structures are used to obtain higher RF gain since gm ~ Nf.W/L. S-parameters are measured in a frequency range from 100 MHz up to 110 GHz (i.e. up to the beginning of the Terahertz spectrum) in linear, saturation and for all channel inversion levels: weak, moderate and strong. The test structures used for RF and mm-Wave measurements follow specific design rules to minimize the impact of coupling paths between probe-heads and the adjacent area of the measured structure[START_REF] Andrei | Coupling on-wafer measurement errors and their impact on calibration and de-embedding up to 110 GHz for CMOS millimeter wave characterizations[END_REF][START_REF] Potereau | Limitations of On-Wafer Calibration and De-Embedding Methods in the Sub-THz Range[END_REF].

  4.1 is used where gate and drain represent respectively port 1 (v1) and 2 (v2), source and back gate being shorted and grounded. Mainly 2-port measurements are used while 4-port measurements are undertaken when required, in particular to set back gate voltage and source voltage independently.

Fig. 4 .

 4 Fig. 4.1 2-port RF structures setup for S-parameters measurement. On-wafer high frequency measurements using G-S-G (ground-signal-ground) probes are sensitive to parasitic elements that degrade the performance of the inner DUT (device-under-test). Parasitic elements originate from the measurement setup or from the G-S-G probe pads attached to the DUT as shown in Fig. 4.2. The parasitic capacitive and resistive extrinsic elements must be characterized and excluded carefully. In order to get rid of these parasitic contributions, RF measurements are deembedded using dedicated OPEN and SHORT structures for each measured device as shown in Fig. 4.2. DC-extraction flow undergone in Chapter 2 is a prerequisite for

4 . 3

 43 and stripped off first. Sparameters from the DUT and the OPEN structures shown in Fig. 4.2 are converted into Y-parameters, and subtracted in order to de-embed the parallel pad parasitic elements and leave the DUT along with the series parasitic elements. A second operation is executed to remove the series parasitic elements using the SHORT structure, and the operation uses the converted Z-parameters.

Fig. 4 . 3

 43 Fig. 4.3 Schematics representing the DUT with parallel and series parasitic elements (B = bG).

Fig. 4 .

 4 Fig.4.4 shows the mutual transadmittance with respect to frequency of a long channel MOSFET. The modulus, which is equal to the transconductance gm at low frequency, starts to decrease beyond a critical frequency Fcrit. The phase shift decreases faster than the modulus from initial value of zero up to more than 270° (i.e.

Fig. 4 . 4

 44 Fig. 4.4 Measured modulus (left) and phase (right) of the mutual transadmittance of an N Type MOSFET with L = 1 µm in saturation (VDS = 1 V).

Fig. 4 . 5

 45 Fig. 4.5 Measured phase of the mutual transadmittance of an N-Type MOSFET with L = 28 nm in saturation (VDS = 1 V).

Fig. 4 .

 4 Fig. 4.6 A representation of the two distribution effects in the channel (1) and in the gate finger (2).

resistance

  RbG. Front gate resistance RG takes into account several contributions shown in Fig. 4.7: (a) the contact resistances, (b) the horizontal gate sheet resistance and finally (c) the vertical gate resistance related to the processed gate stack. The augmented model is shown in Fig. 4.8 (bottom) where series resistors RS and RD as well as gates resistors are added on top of the core model. Two models are proposed for the core part: (1) the equivalent circuit in Fig. 4.8 (top), and (2) the UTSOI2 compact model with implicit series resistances. The gate resistance RG is calculated as:

Fig. 4 .

 4 Fig. 4.7 UTBB FDSOI transistor architecture (3D).

Fig. 4 .

 4 Fig. 4.8 RF equivalent schematic proposal with additional front-gate (Rg) and back-gate (RbG) resistances. Top: the core model. Bottom: the complete quasi-static model. Back gate resistance RbG describes the resistive access to the ground plane underneath the BOX. RbG resistance takes into account the structure layout in a simple manner using access perimeter Pbgate. In the following RbG expression, the horizontal resistive path under the box is considered to be negligible in comparison to the vertical strap access represented by the resistance per unit perimeter Rbsh and including the effect of the N+ access zone and vertical N-Well path.

Fig. 4 . 9

 49 Fig. 4.9 The real part of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V). Model includes simplified front and back gates resistances and ignores NQS effect.

Fig. 4 .

 4 Fig. 4.10 The real part of the measured and simulated mutual transadmittance ym of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V). Model includes front and back gates simplified resistances. Front gate resistance is tuned for SI.

Fig. 4 .

 4 Fig. 4.11 The modulus of the measured and simulated current gain HDG of a long channel L = 1 µm for various gate to source voltages from WI to SI in saturation (VDS = 1 V). Model includes front and back gates simplified resistances and ignores NQS effect.

  parameters. Segmented model parameters extraction follows same procedure described in Table 2-2 with a special care being given to the saturation mode. In comparison to the quasi-static model, only saturation parameters are tuned provided that short channel effects related parameters are scaled in order to avoid any overestimation of these effects. The intermediate segments (i.e. M2, M3 and M4) do not include series resistances, DIBL effect, and overlap and fringe capacitances. The outer segments (i.e. M1 and M5) do not include DIBL effect, and overlap and fringe capacitances but include source and drain series resistances.

Fig. 4 .

 4 Fig. 4.12 Channel segmentation using 5 series MOSFETs.

Fig. 4 .

 4 Fig. 4.13 Non-quasi-static model with simplified gates models.

Fig. 4 .

 4 Fig. 4.14 Gate resistance (left) and gate capacitance (right) vs. frequency for L = 1 µm and Wf = 1 µm.

Fig. 4 .

 4 Fig. 4.15 Front gate network with series and parallel RC lumped circuits.

Fig. 4 .

 4 Fig. 4.16 Complete Non-Quasi-Static model.

Fig. 4 .

 4 Fig. 4.17 One side and two side gate access configurations.

4. 4

 4 .1 Y-parameters S-parameters are practical metrics and are frequently used by microwave engineers and RF designers as the open or short circuit assumptions are not required. Instead, adapted terminations are used. However, S-parameters are generic and generally not practical to gain a deeper insight into the MOSFET physics. The measured S-parameters are transformed into Y-parameters and compared with the simulated counterparts for several inversion levels from WI to SI.

Fig. 4 .

 4 Fig. 4.18 shows the real and imaginary parts of the input and transfer Yparameters for a short device (i.e. L = 30 nm) with respect to frequency in saturation (V DS = 1 V). Fig. 4.19 shows the equivalent metrics for a long channel device (L = 1 µm).The proposed model predicts accurately the Y-parameters over the wide frequency range from 100 MHz up to 110 GHz. The excellent accuracy over a wide frequency band of the simulations compared to measurements verifies that the topology of our model is correct and complete.

Fig. 4 .

 4 Fig. 4.18 Simulation and measurements of the input admittance Y11 and input to output transadmittance Y21 of a 30 nm long NMOS vs. frequency for various gate to source voltages from WI to SI in saturation (VDS = 1 V).

Fig. 4 .

 4 Fig. 4.19 Simulation and measurements of the input transadmittance Y11 and input to output transadmittance Y21 of 1 µm long NMOS vs. frequency for various gate to source voltages from WI to SI in saturation (VDS = 1 V).

Fig. 4 .

 4 Fig.4.20 shows the real and imaginary part of the mutual transadmittance of a 1 µm long device with respect to frequency. The non-quasi-static effect is accurately reproduced including the antiphase phenomena. This is also evidenced in Fig.4.21

Fig. 4 .

 4 Fig. 4.20 Mutual transadmittance ym = Y21-Y12 of a 1 µm long NMOS vs. frequency for various gate to source voltages from WI to SI in saturation (VDS = 1 V).

Fig. 4 .

 4 Fig. 4.21 Measured and simulated mutual transadmittance phase of a 1 µm long NMOS vs. frequency for various Inversion Coefficients IC from WI to SI in saturation (VDS = 1 V). Derived from Y-parameters, two important RF Figures of Merit (FoMs) are the Transit Frequency of the current gain and the maximum oscillation frequency or cut-off frequency of the Mason's unilateral power gain. These two FoMs will be assessed in the following two sections. The FoM representing the tradeoff between the transconductance efficiency and the high frequency performance will be also assessed next.

110 Fig. 4 .Fig. 4 .

 11044 Fig. 4.22 Small signal current gain (|HDG|) vs. frequency (F) in linear mode VDS = 0.3 V for NMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

Fig. 4 .

 4 Fig. 4.24 Normalized transit frequency (fT) vs. normalized drain current Id = ID /(W/L) in linear mode |VDS| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

Fig. 4 .

 4 Fig. 4.25 Transit frequency fT versus IC of a short (L = 30 nm) and long (L = 1 µm) N-type MOSFETs in saturation (VDS = 1 V).

Fig. 4 .

 4 Fig. 4.26 shows Mason's gain modulus with respect to frequency for a short channel (i.e. L = 30 nm) in linear mode (i.e. V DS = 0.25 V) and for various gate to source voltages covering WI to SI regimes. Mason's gain is correctly reproduced for all levels of inversion although back gate resistance can be tuned to capture the high frequency slope for WI regime. Fig. 4.27 (left) shows Mason's gain simulated without the gates networks to illustrate the importance and accuracy of the proposed topology. The Mason's gain is reproduced correctly in saturation (i.e. VDS = 1 V) while accounting for the gates networks (right).

Fig. 4 .

 4 Fig. 4.26 Mason gain vs. frequency (F) of NMOS (L = 30 nm) for various gate to source voltages in linear mode VDS = 0.25 V.

  Fig. 4.27 Mason gain vs. frequency (F) of NMOS (L = 30 nm) for various gate to source voltages in saturation mode VDS = 1 V. Model w/o gates resistances (left) and with the gates networks (right).

Fig. 4 .

 4 Fig. 4.28 shows the simulated and measured fmax normalized using maximum fmax vs. Id demonstrating the model accuracy at high frequency operation. In weak inversion, Mason's gain slope decreases with frequency (as shown in Fig. 4.26), and this behavior is captured with a tuned RbG resistance [125]. Back gate resistance RbG impact is revealed and correctly reproduced in the frequency dependence of fmax vs. Id curves particularly in weak inversion up to 80 GHz (Fig. 4.29). fmax is reproduced in linear and saturation for all levels of inversion from WI to SI as shown in Fig. 4.30.

Fig. 4 .

 4 Fig. 4.28 Normalized fmax vs. the normalized drain current Id in linear mode |VDS| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

Fig. 4 .Fig. 4 .

 44 Fig. 4.29 Normalized fmax vs. drain current Id in linear mode (i.e. |VDS| = 0.3 V) for NMOS and for following frequencies: 10 GHz, 20 GHz, 30 GHz, 40 GHz, 50 GHz, 70 GHz and 80 GHz (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

Fig. 4 .

 4 Fig. 4.31 FoMRF vs. Id in linear operation |VDS| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

  wide frequency range up to 110 GHz, and operation under different channel inversion levels down to low current and low voltage regime. An excellent agreement is shown over more than eight decades of current density for DC and four decades for RF and mm-Wave. The optimum operating point for low-power RF lies in the moderate inversion where our model is very well-suited. In particular, this Chapter demonstrates the accuracy of the proposed high frequency non-quasi-static model to enable RF/mm-Wave and Low Power circuit design applications in UTBB FDSOI technology. RF CMOS based MOSFETs have been widely used in RF integrated circuits

  main attention is paid to the impact of Non-Quasi-Static (NQS) effect on the transadmittance efficiency, and in particular how a proper choice of the normalization factors ends with simple representation of this fundamental figure of merit, with special focus on low-moderate inversion levels. The Chapter is organized as follows. The device architecture along with the high frequency characterization are described in Section 5.2. Next in Section 5.3 we discuss and validate experimentally the generalization of the transconductance efficiency (TE) concept in UTBB FDSOI MOSFETs derived at low frequency in Chapter 3 and published in [127]. The gate distribution effect is assessed and compared to channel NQS effect in Section 5.4, and

  measurements are carried out to extract the device electrical parameters (e.g. threshold voltage VTH, Kp, Cox, etc.). In particular, the Inversion Coefficient (IC) is derived following the method proposed in Chapter 3. Multi-finger MOSFETs are embedded into CPW (Coplanar-Waveguide) transmission lines for high frequency characterization. After a standard short, open, matched load, and through (SOLT) calibration for reference plan definition, S-parameters are measured using groundsignal-ground (GSG) configuration probes up to a frequency of 110 GHz under several DC bias conditions. All transistor modes of operation are covered: non-saturation, saturation, weak inversion, moderate inversion and strong inversion. Measurements are de-embedded using Open-Short method. The gate lengths of the measured NMOS devices range from 28 nm to 1 µm while gate widths range from 200 nm to 5 µm.

Fig. 5 .

 5 Fig. 5.1 3-D plot of the measured transadmittance efficiency modulus versus the frequency and inversion coefficient IC for L = 1 µm at VDS = 1 V.

Fig. 5 .F = 4 Fig. 5 . 2

 5452 Fig. 5.2 Measured transadmittance efficiency modulus versus the frequency for different IC for a NMOS (L = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V.

Fig. 5 Fig. 5 . 3

 553 Fig. 5.3 Measured phase of the transadmittance over ID versus frequency at different IC for NMOS (L = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V.

Fig. 5 . 4

 54 Fig. 5.4 Measured phase of the transadmittance over ID versus frequency at different IC for PMOS L = 1 µm (left) and L = 300 nm (right) in saturation (VDS = -1 V) and VbG = 0 V.

Fig. 5 . 5

 55 Fig. 5.5 Normalized transadmittance magnitude over ID versus normalized frequency Fnorm1 at different IC for NMOS (L = 1 µm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements).

7 Fig. 5 . 6

 756 Fig. 5.6 Phase of the transadmittance over ID versus normalized frequency Fnorm1 at different IC for NMOS (L = 1 µm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements).

Fig. 5 . 7

 57 Fig. 5.7 Phase of the transadmittance over ID versus frequency at different IC for NMOS (L = 300 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements).

Fig. 5 . 8

 58 Fig. 5.8 Phase of the transadmittance over ID versus normalized frequency Fnorm1 with constant mobility at different IC for NMOS (L = 300 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements).

1 Fig. 5 . 9

 159 Fig. 5.9 Phase of the transadmittance over ID versus normalized frequency Fnorm2 with constant mobility at different IC for NMOS (L = 300 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements).

Fig. 5 .

 5 Fig. 5.10 Frequency error versus phase shift after normalization using Ftot (IC = 93.1 is taken as a reference)

Fig. 5 .

 5 Fig. 5.11 Measured phase of the transadmittance over ID versus frequency at different IC for NMOS (L = 28 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V.

Fig. 5 .

 5 Fig. 5.12 Measured phase of the transadmittance over ID versus frequency at different IC for PMOS (L = 28 nm & W = 1 µm) in saturation (VDS = -1 V) and VbG = 0 V.

  as given from (5.17) which now includes the first order distributed effect originating from the gate. The way the different characteristics are distributed in a narrow region which is in favor of the predominance of the enhanced gate delay in short channel devices.

Fig. 5 .

 5 Fig. 5.13 Phase of the transadmittance over ID versus the normalized frequency Fnorm1 estimated with a constant mobility at different IC for NMOS (L = 28 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements).

Fig. 5 .

 5 Fig. 5.14 Phase of the transadmittance over ID versus normalized frequency Fnorm2 with constant mobility at different IC for NMOS (L = 28 nm & W = 1 µm) in saturation (VDS = 1 V) and VbG = 0 V (Measurements).

Fig. 5 .

 5 Fig. 5.15 shows the magnitude of the current gain HDG as a function of the normalized frequency Fnorm1 for various IC and for a channel length of L = 1 µm. The current gain HDG is defined for a 2-port structure as:

Fig. 5 .

 5 Fig. 5.15 Measured |HDG| versus normalized frequency Fnorm1 at different IC for NMOS (L = 1 µm & W = 1 µm), (VDS = 1 V) and VbG = 0 V. Inset shows |HDG| versus F/FcritSI where FcritSI is given by (5.6).

Fig. 5 .

 5 Fig. 5.16 Transit frequency fT versus IC at two different back gate voltages VbG (blue: VbG = 0 V and red: VbG = 2 V) for NMOS (L = 100 nm) in saturation (VDS = 1 V) (4-port Measurements).

Fig. 5 .

 5 Fig. 5.17 shows |ym1|/ID versus frequency for various back gate voltages VbG and fixed front gate voltage VGS = 0.5 V. A constant mobility of µ0 = 1.417E3 cm 2 /Vs is used. Forward back gate bias enhances IC and consequently the frequency at which the NQS effect becomes important at the cost of a decrease in the transadmittance efficiency. In Fig. 5.18 and Fig. 5.19, the normalization Fnorm1 is used showing accurate prediction of NQS effects for all levels of inversion, both in modulus and phase.

Fig. 5 .

 5 Fig. 5.17 Simulated transadmittance efficiency modulus versus frequency at different VbG for NMOS (L = 1 µm) in saturation (VDS = 1 V) and VGS=0.5V (TCAD).

Fig. 5 .

 5 Fig. 5.18 Normalized transadmittance efficiency modulus versus normalized frequency Fnorm at different VbG for NMOS (L = 1 µm) in saturation (VDS=1V) and VGS = 0.5 V (TCAD).

Fig. 5 .

 5 Fig. 5.19 Simulated phase of the transadmittance efficiency versus normalized frequency Fnorm at different VbG for NMOS (L = 1 µm) in saturation (VDS= 1V) and VGS = 0.5 V (TCAD).

Fig. 5 .

 5 Fig. 5.20 Simulated phase of the back transadmittance efficiency versus frequency at different VbG for NMOS (L = 1 µm) in saturation (VDS = 1 V) and VG = 0 V (TCAD).

Fig. 5 .

 5 Fig. 5.21 Simulated phase of the back transadmittance efficiency versus normalized frequency Fnorm at different VbG for NMOS (L = 1 µm) in saturation (VDS = 1 V) and VG = 0 V (TCAD).

  24 the length L = 1 µm is considered long in advanced technologies and accurately extracted, on the other hand, Inversion Coefficient IC is based on a technology current derived from accurate extraction of the product β1 = n1.Cox1.µ1[START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. However, the mobility extraction is still subject to intensive research and usually considered as gate voltage dependent[START_REF] Mourrain | New method for parameter extraction in deep submicrometer MOSFETs[END_REF][START_REF] Karatsori | Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction[END_REF]. Two major challenges are faced in the mobility extraction: one is the limitation of the empirical SI model based on gate voltage overdrive and the other is the difficulty to extract the inversion charge based on capacitance measurements in weak and moderate inversion regimes. In this research work, the proposed mobility extraction method is compared to two other methods namely the classical Y function with iterative corrections as in[START_REF] Mourrain | New method for parameter extraction in deep submicrometer MOSFETs[END_REF] and the Lambert-W function based method proposed in[START_REF] Karatsori | Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction[END_REF]. The Y function based method is first used to retrieve the mobility dependence in order to replace the constant mobility in (5.5) by an IC dependent mobility. The normalization using Fnorm2 and a variant mobility (extracted using Y-function method[START_REF] Mourrain | New method for parameter extraction in deep submicrometer MOSFETs[END_REF]) leads to a better Fcrit alignment for the various IC values with less than 4% discrepancy on the normalized plots for long and short geometries. Ftot remaining discrepancy observed in Fig.5.9 is due to a mobility variation of 15-19 % illustrated in Fig.5.22 (Fcrit + distr. gate corr.) and compared against the mobility extracted using fT expression taken from[START_REF] Shameli | Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study[END_REF], Y-function and Lambert-W function. The mobility slightly decreases in WI and SI, and has a maximum corresponding to IC ≈ 4 which corroborates the findings in[START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. This apparent mobility variation is due to the low transverse field influence on volume inversion. Neither the Y function based mobility extraction nor the Lambert-W Split C-V based extraction predict mobility in WI. The Lambert-W Split C-V function based extraction methodologyunderestimates mobility values in MI and WI levels because of a difficult estimation of the inversion charge in this region. Our method provides comparable results to the extraction using magnetoresistance characterization[START_REF] Shin | Magnetoresistance mobility characterization in advanced FD-SOI n-MOSFETs[END_REF].

Fig. 5 .

 5 Fig. 5.22 Mobility versus gate voltage overdrive for L = 0.3 µm extracted using various methods: Fcrit based, fT based, classical Y function with iteration, Lambert-W Split C-V based, and Fcrit based with correction of the distributed gate effect.

  Split CV Lambert-W F crit + distr. gate corr.

Fig. 6 . 2

 62 Fig. 6.2 Measured gate to channel capacitance normalized using front oxide capacitance (Cox.W.L) with respect to VGS for various VbG and its derivative (Inset) for N-type UTBB FDSOI MOSFET.

Fig. 6 . 3 Fig. 6 . 4

 6364 Fig. 6.3 Comparison of DIBL between FDSOI and bulk in saturation (VDS=1V) and VbG = 0 V.

Fig. 6 . 5 Fig. 6 . 6

 6566 Fig. 6.5 Measured and normalized |Y21| versus frequency for various lengths and finger length is 1 µm.

Fig. 6 .

 6 Fig. 6.7 gm over ID charts versus IC for several short NMOS along with a longer channel (L = 1 µm) for comparison.

  respectively. The specification related to impedance matching fixes the real part of Zin at 50 ohm and consequently a relation between the inductance Ls and the transit frequency is given by (6.3). If we consider a maximum Ls inductance of 100 pH, M1 transit frequency fTi should be greater than 80 GHz. According to Inset of Fig.6.4, for operation at IC = 4, the MOSFET length that guarantees the required fT is strictly lower than L = 100 nm. To obtain acceptable noise figures and using NFmin versus IC charts shown in Fig.6.10, length should also be lower than 100 nm. In order to verify the noise figure specification and inductor value constraint, we will consider two channel lengths that are L = 40 nm and L = 70 nm, with FoM maximizing respectively at IC = 5 and IC = 9. Both geometries provide acceptable high frequency performance. Moreover, L = 40 nm and L = 70 nm MOSFETs are less subject to DIBL and Mismatch than minimal length. Thus, an Ls value of 33 pH and 39 pH for respectively L = 40 nm, and L= 70 nm MOSFET based LNAs are found.

Fig. 6 .

 6 Fig. 6.10 NFMIN noise figure vs. IC for various lengths in saturation.

5 )

 5 Close width values of 22.8 µm and 22.1 µm are found for respectively L = 40 nm and L = 70 nm based LNA circuits. The gate voltage overdrive with respect to IC charts shown in Fig. 6.11 are used to retrieve the gate to source voltage corresponding to the two IC values for each length. The calculated VGS values are respectively 0.49 V and 0.55 V.

Fig. 6 .

 6 Fig. 6.11 Inversion Coefficient vs. gate voltage overdrive for two lengths L = 40 nm and L = 70 nm.

Fig. 6 .

 6 Fig. 6.12 Power gain S21, Input Match S11, and minimal noise figure NFmin with respect to frequency for two LNA circuits (first with MOSFET length of 40 nm and second with 70 nm).

  linearity and its noise figure in one hand and the LNA gain in the other hand.

Fig. 6 .

 6 Fig. 6.13 The LNA-MIXER circuit. In Fig. 6.14, an illustration of the LNA-MIXER operation is provided in time and frequency domains. The input RF signal VRF at the front gate of M1 is modulated using the back gate voltage VLO which is generated locally using an oscillator. The LO voltage is sufficiently high to control the channel through the thick BOX. The output current ID represents the product of the two input signals and produces a voltage signal at the circuit output VIF. The output signal spectrum is shown in Fig. 6.14 (bottom) where the signal frequency is down-converted from 60 GHz to a very low baseband frequency.

Fig. 6 .

 6 Fig. 6.14 (top) Time domain input voltages VRF and VLO, and output current ID, (bottom) corresponding output VIF spectrum.

  For better insight into the MOSFET operation at lower levels of inversion, the gm over ID figure of merit is studied in detail. The invariance of this important FoM versus the Inversion Coefficient is analyzed in UTBB FDSOI MOSFET. The breakdown of this invariance has been assessed with respect to back gate voltage, transistor length, temperature, drain to source voltage and process variations. The invariance can be used to predict the transconductance provided that W/L and level of inversion (i.e. IC) are given. Moreover, with the additional chart of IC with respect to the gate voltage overdrive VGS -VTH, one can predict drain current provided that W/L and gate voltage are provided. This can allow designers to predict MOSFET DC properties without the need of an analytical model including in MI which is difficult to capture. The aforementioned charts along with main MOSFET capacitances (i.e. in use in the proposed equivalent circuits) versus IC charts can provide accurate predictions of the equivalent circuit parameters and thus completely replace a compact model for simple circuit investigations. Furthermore, we have experimentally shown that gm over ID versus inversion coefficient chart can be considered as a fundamental characteristic of UTBB FDSOI technology transistors and thus be used in gm over ID based analog design sizing procedures.

  circuit investigations. Two modeling approaches are investigated: the simple equivalent circuit and the industrial recently proposed quasi-static compact model namely Leti-UTSOI2 model. The important low frequency Figures-of-Merit are assessed using both models and showed accurate reproduction of the measured data.DC OP Information feature enhancementAn enhancement of the classical Operating Point Information feature in circuit simulators is proposed. The classical feature is intensively used in Analog and RF design CAD despite severe limitations discussed in Section 2.5 of Chapter 2. The proposed enhancement provides accurate information for complex RF sub-circuit based models despite the multiple extrinsic elements involved and the high frequency NQS models. The proposal is adopted by major EDA vendors.

Fig. D. 1

 1 Fig. D. 1 Normalized drain current versus VGS for NMOS with L=30nm (left) and L=1µm (right) at various VDS (from 50mV to 1V).

  Fig. D. 3 for a short (left) and long (right) evidencing an accurate reproduction. The Transconductance derivative shown in Fig. D. 4, which is important for RF operation, are correctly reproduced using parameters that are extracted with no optimization.

Fig. D. 3

 3 Fig. D. 3 Normalized transconductance in logarithmic scale versus VGS for NMOS with L = 30nm (left) and L = 1 µm (right) at various VDS (from 50 mV to 1 V).

Fig. D. 4

 4 Fig. D. 4 Transconductance derivative versus VGS for NMOS with L = 30 nm (left) and L = 1 µm (right) at various VDS (from 50 mV to 1 V). Output characteristics in linear and logarithmic scales are shown in Fig. D. 5 and Fig. D. 6, respectively. The logarithmic scale highlights the region where DIBL is detrimental. All output characteristics are accurately reproduced linear and saturation.

Fig

  Fig. D. 5 Normalized drain current in linear scale versus VDS for NMOS with L = 30 nm (left) and L = 1 µm (right) at various VGS (from 150 mV to 0.9 V).

Fig. D. 6

 6 Fig. D. 6 Normalized drain current in logarithmic scale versus VDS for NMOS with L = 30 nm (left) and L = 1 µm (right) at various VGS (from 150 mV to 0.9 V). Output conductance gds is shown in Fig. D. 7 and its derivative in Fig. D. 8. All first order and second order parameters are satisfactorily reproduced. An accurate gds reproduction along with an accurate transconductance gm simulation lead to an accurate prediction of the intrinsic gain, which is given by:

Fig. D. 7

 7 Fig. D. 7 Normalized conductance versus VDS for NMOS with L = 30 nm (left) and L = 1 µm (right) at various VGS (from 150 mV to 0.9 V).

Fig. D. 8

 8 Fig. D. 8 Conductance derivative versus VDS for NMOS with L=30nm (left) and L=1µm (right) at various VGS (from 150mV to 0.9V).

  Fig. 3.

Fig. 1

 1 Fig. 1 Comparaison du FinFET (à gauche) et de l'UTBB FDSOI (à droite).

Fig. 2 Fig. 3

 23 Fig. 2 Comparatif de la fréquence de transition fT pour différents transistors MOSFET avancés en fonction de la longueur de grille [10].

Fig. 4

 4 Fig. 4 Densité électronique simulée dans le film de silicium à différentes tensions de grille arrière VbG pour un NMOS FDSOI UTBB (L = 1 µm & W = 1 µm) en saturation et forte inversion (à VGS = 1 V).

Fig. 5

 5 Fig. 5 Coupe transversale (gauche) et TEM (droite [19]) du MOSFET UTBB FDSOI.

Fig. 6

 6 Fig. 6 Schéma équivalent petit signal et quasi-statique du transistor MOSFET UTBB FDSOI prenant en compte les résistances série RS et RD (Cgd = Cgdi + Cgde et Cgs = Cgsi + Cgse). Cm, gm1, gm2 et gds étant respectivement la transcapacité mutuelle, la transconductance avant, la transconductance arrière et la conductance. Les travaux présentés dans cette partie se concentrent sur la description et la modélisation du comportement DC et basse fréquence du transistor MOSFET UTBB FDSOI. L'opération sous l'influence des deux grilles est présentée et comparée à l'opération de la grille simple dans la technologie bulk en utilisant des données mesurées. La capabilité du modèle à décrire le comportement DC ainsi que le petit signal (à faible et haute fréquences) est évaluée en mettant l'accent sur des conditions de polarisation à basse tension.

Fig. 7

 7 Fig. 7 Simulations TCAD montrant l'impact de la tension de la grille arrière sur la concentration des porteurs et par conséquent sur la caractéristique d'entrée ID-VGS. (a) ID-VGS pour différents VbG allant de -10 V à 8 V. (b) inversion du canal à l'avant pour VbG négatif = -10 V (c) inversion du canal dans le volume de film de silicium à VbG = 0 V, et (d) inversion du canal avec un max local près de l'interface arrière pour VbG = 8 V. L'opération en basse fréquence et DC du MOSFET UTBB FDSOI est décrite à l'aide des données mesurées et des simulations TCAD, en particulier pour les faibles niveaux d'inversion. Ensuite, le modèle quadratique du canal long en bulk est comparé à son équivalent double-grille. La comparaison montre des similitudes profondes entre les deux approches. Le circuit équivalent petit signal proposé est évalué en comparaison avec le modèle basé sur UTSOI2. Le circuit équivalent est utile pour une

Fig. 8

 8 Fig. 8 La transconductance normalisée (à gauche) et sa dérivée (à droite) en fonction de VGS -VTH en mode linéaire |VDS| = 0.3 V pour deux longueurs NMOS et PMOS (L = 30 nm et 2 µm), Wf = 2 µm et Nf = 10 à T = 25 °C. Enfin, la fonctionnalité importante DC OP Info des simulateurs Spice pour la conception analogique est revue tout en signalant ses limitations actuelles. Une amélioration est finalement proposée avec des résultats prometteurs.

Fig. 9

 9 Fig. 9 gm/ID normalisé en fonction du coefficient d'inversion IC à différentes valeurs de VbG pour un NMOS (L = 1 µm & W = 1 µm) en saturation (VD = 1V) à T = 25 °C.

  haute fréquence De nos jours, nous pouvons avoir accès à l'information presque partout grâce à la technologie sans fil. Des progrès remarquables ont été réalisés pour répondre aux différentes exigences en matière de portée, allant des réseaux Bluetooth à courte portée aux réseaux cellulaires et satellites à longue portée. Selon le théorème de Shannon, la capacité du canal et par conséquent le débit des données de communication dépendent de la bande passante et du rapport signal sur bruit. Une façon d'augmenter le débit de données est de se déplacer vers des fréquences plus élevées où plus de bande passante est disponible [39]. Avec les performances élevées en hautes fréquences des noeuds technologiques avancés, les applications à ondes millimétriques à coût réduit basées sur la technologie CMOS sont maintenant possibles malgré le fait que le CMOS, à l'origine, n'est pas optimisé pour les performances millimétriques. Cependant, la réalisation de certaines applications millimétriques utilisant les technologies CMOS implique le fonctionnement à des fréquences très élevées et proches des "limites" de fonctionnement des transistors (c'est-à-dire les fréquences fT et fmax). Diverses applications fonctionnent aujourd'hui dans la bande millimétrique, comme le contrôle de la vitesse automatique à longue distance pour l'automobile à 77 GHz et d'autres applications telles que l'USB sans fil à 60 GHz [40][41]. Avec de telles applications, les circuits CMOS ont de nouvelles opportunités de fonctionnement au-dessus de 60 GHz. Par conséquent, des modèles MOSFET RF et millimétriques précis sont requis. Il faut noter que la caractérisation et la modélisation sont des étapes délicates pour le fonctionnement à haute fréquence du transistor MOSFET. Comme illustré dans la Fig. 10, à haute fréquence, la capacité d'amplification du transistor tend à diminuer et les modèles quasi-statiques ne permettent pas de reproduire ce comportement. Non seulement la transadmittance mutuelle ym (i.e. y21-y12) acquière une partie imaginaire, mais aussi les parties réelles et imaginaires diminuent en amplitude et le déphasage augmente. Ce phénomène est observé pour toutes les géométries et les conditions de polarisation, en particulier pour les dispositifs à canaux longs. Le déphasage de ym signifie que l'excitation de la tension au terminal de la grille est en retard sur le courant généré au terminal de drain. Ce retard est dû aux effets distribués qui se produisent dans la structure MOSFET et qui ne sont modélisés ni dans le circuit équivalent de la Fig. 6 ni dans le modèle compact Leti-UTSOI2. La méthode de caractérisation RF et millimétrique est brièvement décrite et des solutions de modélisation sont proposées pour les parties intrinsèques et extrinsèques des structures UTBB FDSOI. Le modèle proposé est finalement validé en utilisant des mesures jusqu'à 110 GHz. Le modèle final est représenté dans Fig. 11.

Fig. 10

 10 Fig. 10 La partie réelle de la transadmittance mutuelle ym mesurée et simulée d'un canal long L = 1 µm pour différentes tensions de grille couvrant tous les niveaux d'inversion en saturation (VDS = 1 V).

Fig. 11

 11 Fig. 11 Modèle non-quasi-statique complet. La comparaison du modèle proposé avec les données mesurées est résumée dans les deux figures : Fig. 12 et Fig. 13.

Fig. 12

 12 Fig. 12 Simulation et mesures de la transadmittance d'entrée Y11 et de la transadmittance d'entréesortie Y21 d'un NMOS de 30 nm de long en fonction de la fréquence pour diverses tensions de grille pour différents niveaux d'inversion en saturation (VDS = 1 V).

Fig. 13

 13 Fig. 13 Simulation et mesures de la transadmittance d'entrée Y11 et de la transadmittance d'entréesortie Y21 de 1 µm de longueur d'un NMOS en fonction de la fréquence pour différentes tensions de grille et pour différents niveaux d'inversion en saturation (VDS = 1 V).

  de la transadmittance en présence des effets NQS Les transistors MOSFET RF à base de la technologie CMOS ont été largement utilisés dans les circuits intégrés RF (RFIC) grâce à la miniaturisation. Comme on l'a vu précédemment, les effets canaux courts ont été atténués à l'aide d'architectures novatrices couplées à de nouveaux matériaux [10]. Les nouvelles architectures CMOS permettent un niveau d'intégration plus élevé et un fonctionnement à très hautes fréquences. Pour les applications analogiques et RF, la technologie UTBB FDSOI s'est révélée pertinente, notamment lorsque la consommation d'énergie est une priorité [42]. Les transistors MOSFET UTBB FDSOI présentent des performances analogiques et RF intéressantes grâce à la réduction des capacités et des résistances parasites. De plus, la grille arrière indépendante permet de contrôler la tension de seuil et la mobilité dans le canal [43][42].La notion de l'efficacité de la transconductance du transistor MOSFET UTBB FDSOI est généralisée et étudiée à haute fréquence pour différents niveaux d'inversion du canal (cf. Fig.14). L'attention est portée sur l'impact de l'effet non-quasi statique (NQS) sur l'efficacité de la transadmittance. En particulier, la normalisation des grandeurs électrique mène à une simplification de cette figure de mérite fondamentale tout en mettant en avant les niveaux d'inversions modérés (cf. Fig.15et Fig.16).

Fig. 14 7 Fig. 16

 14716 Fig. 14 Tracé 3-D du module de l'efficacité de la transadmittance (ym/ID) mesuré en fonction de la fréquence et du coefficient d'inversion IC pour L = 1 µm et à VDS = 1 V.

  .

7 Fig. 17

 717 Fig. 17 La mobilité en fonction de VGS-VTH pour L = 0.3 µm extraite en utilisant diverses méthodes: en utilisant Fcrit , en utilisant fT , en utilisant la fonction Y classique avec itération, en utilisant la fonction Lambert-W et Split C-V et en utilisant Fcrit avec la correction de l'effet distribué de la grille.

Fig. 18

 18 Fig. 18 Circuit représentant un LNA cascode.

Fig. 19

 19 Fig. 19 Gain de puissance S21, adaptation à l'entrée S11, et NFmin en fonction de la fréquence pour deux circuits LNA (d'abord avec une longueur de MOSFET de 40 nm puis avec L = 70 nm).

  d'un circuit comme le LNA. Cependant, le bruit est généralement caractérisé dans une gamme de fréquences où le comportement du transistor vérifie l'hypothèse quasistatique. Par conséquent, les données de mesure du bruit ne sont souvent pas reproduites avec des modèles inadéquats à haute fréquence. De plus, les effets de bruit de différentes origines ont rendu difficile le développement d'un modèle précis par les scientifiques. En particulier, des modèles empiriques sont utilisés pour la modélisation du bruit haute fréquence en raison de l'ambiguïté liée à la cause réelle du bruit excessif dans les dispositifs à canaux courts. Les paramètres de bruit 2-ports, traditionnellement requis pour la conception RF comme une meilleure alternative aux modèles inexacts, doivent être étendus au spectre millimétrique et des techniques d'épluchage adaptées doivent être proposées.

  A HAUTES FREQUENCES ET BASSE CONSOMMATIONRésuméCe travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l'art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l'impact de la grille arrière, à l'aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l'inversion modérée jusqu'à 110 GHz.Mots-clés : Analogique et RF, Double Grille, FDSOI, UTBB, Coefficient d'inversion, Efficacité de la transconductance, gm sur ID, Efficacité de la transadmittance, faible puissance, faible tension, HF, spectre millimétrique, NQS, LNA, LNA-MIXER.

  Key words: Analog and RF, Double-gate FETs, Fully Depleted Silicon-on-Insulator (FDSOI), UTBB, Inversion Coefficient, Transconductance efficiency, gm over ID, Transadmittance efficiency, Low-Power, Low-Voltage, HF, mm-Wave, NQS, LNA, LNA-MIXER.

Table 1 -

 1 1 Summary of surface potential calculation models in a DG MOSFET[START_REF] Poiroux | UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs[END_REF]. ............

Table 2 -

 2 1 Threshold voltage comparison between the C-V derivative based and gm/ID derivative based methods. ................................................................................................

Table 2 -

 2 2 Summary of the extraction steps. .............................................................................

Table 2 -

 2 3 Normalization. .........................................................................................................

Table 2 -

 2 4 Operating Point information restricted list proposal for analog design (B = bG). ..........................................................................................................................................

Table 3 -

 3 1 n1 factor and I1 for N-MOSFET and P-MOSFET in saturation and at 25 ºC ..........

Table 4 -

 4 1 Summary of the expressions used for equivalent circuit parameters extraction from Y-parameters (source and back gate being tight together in a 2-port). .................

Table 6 -

 6 1 Summary of the two LNAs parameters at F0 = 35 GHz. .......................................

	I1	Technology characteristic current for the front gate (= Ispec) in [A]
	I2	Technology characteristic current for the back gate in [A]
	I	Square shape drain current in [A]
	ION	MOSFET ON current (digital applications FoM) in [A]
	IOFF	MOSFET OFF current (digital applications FoM) in [A]
	Conductances and Transconductances
	gm1 or gm	Front gate transconductance in [S]
	gm2 or gmb Back gate transconductance in [S]
	gds	Output conductance (= gd) in [S]
	Charges
	Qinv	Inversion mobile charge density (= Qi) in [C.m -2 ]
	QI	Inversion charge in [C]
	QG	front gate charge (= Qg1) in [C]
	QD	Drain charge in [C]
	QS	Source charge in [C]
	QbG	Back gate charge for UTBB FDSOI MOSFET (= Qg2) in [C]
	QB	Bulk charge for bulk MOSFETs in [C]
	Gains in [dB]
	HDG	Current gain
	U	Unilateral gain or Mason's gain
	Av	Voltage gain
	Admittances and Transadmittances
	ym	Intrinsic mutual front gate transadmittance in [S]
	yxy	Admittance (x = y) or transadmittance (x ≠ y) in [S] where x and y
		are taking the following values: 1 for drain, 2 for gate, 3 for source
		and 4 for back gate
	Capacitances and Transcapacitances
	Cox	Oxide capacitance per unit area in [F.m -2 ]

Table 1 -1 Summary of surface potential calculation models in a DG MOSFET [59].

 1

			Approx.		Comput.
	Reference	Interpolation functions	on potential vertical	Numerical resolution	Of boundaries between	Use of Lambert functions
			profile		modes
	H. Lu et al. IEEE TED 2006 [60]	No	No	Yes	Yes

Table 2 -

 2

	VbG (V)	-2	-1	0	1	2	5
	C-V derivative	0.52	0.46	0.38	0.3	0.22	0
	based method
	gm/ID	0.61	0.54	0.46	0.37	0.29	0.017
	derivative
	based method
	Delta (V)	0.09	0.08	0.08	0.07	0.07	0.017

1 Threshold voltage comparison between the C-V derivative based and gm/ID derivative based methods.

Table 2 -

 2 2 Summary of the extraction steps.

both log(ID(VGS)) and ID(VGS) in non-saturation mode and refined using gm and gm derivative with respect to VGS.

Table 2 -

 2 3 Normalization.

	Quantity	Normalization
	Drain Current	Id = ID/(Ispec.W/L)
	Capacitance	C/(Cox.W.L)
	Gate Voltage	Overdrive: Vgt = (VGS -VTH)
	Transconductance	gm = Gm .UT/(Ispec.W/L)
	Transconductance derivative	gm2 = Gm2.UT 2 /(Ispec.W/L)
	Conductance	gds = Gds.UT/(Ispec.W/L)
	Conductance derivative	gds2 = Gds2.UT 2 /(Ispec.W/L)

where W is the total width (W = Nf.Wf), Wf is a one finger length, Cox is the front oxide capacitance per unit area, VTH is the threshold voltage, TYPE is 1 for NMOS and -1 for PMOS, and Vgt is the gate voltage overdrive. Ispec is a technology current extracted in Chapter 3 and equal, for the front gate, to I1 ≈ 0.7 µA.

The validation of the extracted models is achieved through the comparison between the simulated MOSFET characteristics, and the measured counterparts. As stated earlier, several geometries and structures are characterized to validate the model scalability and all physical effects listed in Table

C

. 1. However, for an illustration purpose, only some geometries are shown in this document.

Table 2

 2

		2
			Cgg Simu
		1.8	Cgg Meas
			Cgd Simu
		1.6	Cgd Meas
		1.4
	Cgg & Cgd (n.u.)	0.8 1 1.2
		0.6
		0.4
		0.2
		0	-0.4	-0.2	0	0.2	0.4	0.6	0.8
					TYPE*(V G -V T0 ) (V)

-2. Both models are simulated over a wide frequency range from 100MHz up to 500 GHz and compared. In Fig. 2.32 and Fig. 2.33, simulated S-parameters of a 1 µm NMOS are shown respectively in a

Table 2

 2

-4

, and includes a restricted set of MOSFET FoMs. This specification can be applied to various existing logic and analog MOSFETs with 4 terminals (i.e. a source, a drain, a front gate, and a back gate or a bulk terminal) in several technologies (i.e. bulk, SOI, etc.). The NMOS convention is chosen to display PMOS related information (i.e. the VTH of a PMOS for instance is positive in SI and saturation when equivalent bias conditions provide a positive VTH for NMOS). The source and drain are determined based on V DS voltage sign as in bulk PSP model. All parameters include temperature effect and self-heating effect (DC thermal voltage part).

Table 2 -

 2

	Name	Unit	Formulation	Description
			Total currents
				Total DC drain current:
	I D	A	-	-flowing into drain terminal for NMOS
				-flowing out of drain terminal for PMOS
				Total DC gate current:
	I G	A	-	-flowing into gate terminal for NMOS
				-flowing out of gate terminal for PMOS
				Total DC source current:
	I S	A	-	-flowing into source terminal for NMOS
				-flowing out of source terminal for PMOS
	I B	A	-	Total DC bulk current: -flowing into bulk terminal for NMOS

4

Operating Point information restricted list proposal for analog design (B = bG).

  .36) For short channel (e.g. L = 100 nm), the proposed SI expression provides lower VDSAT values as shown in Fig. 2.41. However, the values provided by Leti-UTSOI2 are too high to be defined as a threshold for current saturation. Actually the current already saturated at the values provided by Leti-UTSOI2 as depicted in Fig. 2.42. Expression (2.35) provides acceptable values for onset of saturation region.

Table 3 -

 3

	1 n1 factor and I1 for N-MOSFET and P-MOSFET in saturation and at 25 ºC
		n1	I1
	NMOS	1.086	7.028e-7 A
	PMOS	1.094	2.152e-7 A
	Following the normalization explained in the previous section, Fig. 3.4 shows the
	normalized gm1 over ID as a function of the inversion coefficient IC. NMOS and PMOS
	curves overlap in strong and weak inversion regions while a maximum of 7% difference
	is encountered in moderate inversion as charge carriers nature influences mobility

behavior mostly in this region. In the following Sections, we will analyze the dependence of the normalized gm/ID versus inversion coefficient chart on transistor back or opposite gate voltage, temperature, geometry, drain to source voltage and process variability.

Table 3

 3

-1)

. Thermal voltage UT considers the measurements temperature. Less than 0.06 % error per degree Celsius is expected when considering gm1 over ID versus IC characteristic invariance overall inversion levels. Maximum delta is obtained in the second half of the moderate inversion where charge carriers sensitivity is higher. It can be seen from Fig.

3

.10 that transistor length of 300 nm slightly departs from strong inversion square law trend for high IC values

Table 4 -

 4 1 Summary of the expressions used for equivalent circuit parameters extraction from Yparameters (source and back gate being tight together in a 2-port).

Table 6 -

 6 1 Summary of the two LNAs parameters at F0 = 35 GHz.

  Les deux différences fondamentales entre les deux solutions technologiques sont l'orientation des grilles et des canaux d'une part, et la connexion des deux grilles d'autre part. Le FinFET est fondamentalement un transistor double-grille dans lequel les deux grilles sont connectées. Cependant, dans un MOSFET UTBB FDSOI, les deux grilles ne sont pas connectées et peuvent être polarisées différemment. Sinon, le FinFET et l'UTBB FDSOI se ressemblent comme illustré dans la Fig. 1 et proposent des performances digitales comparables [6]. Le comportement RF du FinFET est cependant affecté par un grand nombre d'éléments parasites [7][8][9][10]. La Fig. 2 montre un comparatif de la fréquence de transition fT de différents MOSFET avancés en fonction de la longueur de grille. L'UTBB FDSOI présente une fT supérieure par rapport au FinFET grâce à une résistance parasite et des éléments capacitifs réduits. De plus, les attentes de

	encore plus autonomes et plus performants pour étendre les applications de l'internet
	Introduction des objets. I. Etat de l'Art
	La première partie de la thèse dresse un état de l'art de la modélisation des
	transistors MOS en lien avec les besoins de la conception des circuits. La deuxième
	La miniaturisation du transistor MOS à effet de champ a permis de faire des partie est consacrée à la description du comportement DC et faible fréquence du Au cours des cinq dernières décennies, l'industrie du semiconducteur a été
	progrès considérables tant au niveau performance des circuits qu'au niveau de leur dispositif étudié. Cette description est principalement axée sur les caractéristiques principalement régie par la miniaturisation progressive du transistor selon la loi de
	coût de fabrication. Toutefois, la diminution drastique de la taille du transistor est mesurées courant-tension et capacité-tension. La troisième partie est dédiée à Moore jusqu'à atteindre l'échelle nanométrique. La loi de Moore porte principalement
	confrontée à des limitations majeures telles que les effets canaux courts et la variabilité l'étude de l'invariance de la notion de l'efficacité de la transconductance (la sur la réduction des coûts, et l'aspect économique a entraîné une démocratisation des
	particulièrement à partir du noeud technologique 20 nm. La poursuite de l'intégration transconductance divisée par le courant). L'invariance est étudiée en fonction de la dispositifs électroniques. Récemment, de nouveaux matériaux et de nouvelles
	vers les noeuds technologiques plus denses nécessite désormais l'utilisation de tension de la grille arrière, de la longueur du canal, de la température, de la tension architectures ont été utilisés pour surmonter les limitations des effets canaux courts et
	nouveaux matériaux et de nouvelles architectures pour le transistor à effet de champ. l'effet couramment appelé DIBL causés par la proximité entre la source et le drain. Ces
	nouvelles solutions sont inévitables, en particulier en dessous du noeud technologique
	20 nm.
	Néanmoins, il n'existe pas de modèle industriel suffisamment précis et efficace de ce
	type de transistor pour la conception des circuits hautes fréquences (RF et
	millimétriques) à faible consommation. Par ailleurs, les méthodes de conception des
	circuits à faibles niveaux d'inversion du transistor MOS privilégiant ainsi une faible
	consommation font défaut pour la nouvelle génération des transistors MOS à plusieurs
	grilles.
	dessus, de nouvelles architectures du transistor MOSFET avec plusieurs grilles ont
	C'est dans ce contexte que s'inscrit cette thèse qui se propose de faire une été proposées pour poursuivre la réduction de la taille du transistor. Le premier travail
	étude et une modélisation du comportement fréquentiel du transistor MOS du type publié au sujet du transistor MOSFET à double grilles, [4], montre une réduction
	UTBB FDSOI dans le but de servir la conception de circuits dédiés aux signaux significative des effets canaux courts dans les MOSFET FDSOI grâce à l'addition
	Analogiques Mixtes, Hautes Fréquences, et nécessitant une très faible consommation. d'une grille à l'arrière du canal. Avec cette architecture, l'influence du champ électrique
	du drain sur le canal est réduite. Cependant, le transistor MOSFET à double grille
	Les travaux ont permis d'appréhender les phénomènes complexes intervenants fabriqué en premier était le transistor DELTA complètement appauvri qui est similaire
	dans les 7 nm du film du silicium et de proposer un modèle non-quasi-statique précis au FinFET mais sans le masque supérieur [5]. Deux architectures ont été finalement
	jusqu'à 110 GHz. Les résultats obtenus dans le cadre de cette thèse ouvrent la voie
	vers l'exploitation de la technologie UTBB FDSOI dans la conception des circuits

Dans ce domaine, deux principales alternatives sont proposées : l'architecture 3D de type FinFET, et l'architecture planaire de transistor MOS complètement désertée, à canal non dopé et intégrée sur film de silicium et d'isolant ultra-minces (UTBB FDSOI, pour Ultra-Thin Body and Box Fully-Depleted SOI). De par son aspect planaire, le transistor UTBB FDSOI étudié dans cette thèse est moins exposé à l'impact des éléments parasites et par conséquent plus adapté aux applications analogiques et RF. V DS et des variations dues au processus de fabrication. La quatrième partie propose une étude du comportement haute fréquence allant jusqu'à 110 GHz et la modélisation associée, respectivement intrinsèque et extrinsèque, du transistor MOS UTBB FDSOI. Dans la cinquième partie, la notion de l'efficacité de la transconductance a été généralisée pour couvrir tous les modes de fonctionnement du transistor en basses et hautes fréquences. L'étude du comportement non-quasi-statique est basée sur cette notion généralisée. Enfin, en s'appuyant sur les modèles et méthodes proposées dans les parties précédentes, le dimensionnement d'un amplificateur à faible bruit (LNA) est présenté dans la sixième partie, en exploitant le régime d'inversion modérée du transistor MOS UTBB FDSOI. Afin de réduire le courant de fuite à l'état bloqué du transistor MOSFET, l'effet de la grille sur la distribution du potentiel dans le canal doit être amélioré. Des matériaux à constante diélectrique élevée (high-k) ont été introduits depuis le noeud technologique 45 nm afin d'améliorer le contrôle de la grille tout en réduisant les fuites du courant par effet tunnel [1]. Toutes les techniques d'amélioration utilisées dans les noeuds technologiques précédents ont un effet limité dans les noeuds proche du 20 nm. En effet, la dégradation de la mobilité due aux effets de collision limite la concentration de dopants dans le canal et le seuil de la contrainte du réseau freine l'amélioration de la mobilité dans les canaux contraints [2][3]. Avec les limitations ciadoptées et sont en production aujourd'hui: le double-grille symétrique appelé FinFET et le double-grille asymétrique appelé UTBB FDSOI.

  soit démontré, sa modélisation est souvent négligée et l'approximation des charges surfaciques est considérée par défaut[13][14]. Des résultats assez précis sont obtenus en modélisant l'effet de confinement quantique à l'aide d'un décalage appliqué aux tensions des grilles ou aux dimensions verticales dans[15] et[16], et en utilisant le concept de centroïde de la charge d'inversion dans[17]. De plus, des charges d'inversion multiples (avant et arrière) et une mobilité des porteurs variant verticalement sont considérées afin de calculer la charge totale et la mobilité effective [15][18]. En fait, le calcul de la concentration d'électrons en présence du confinement doit passer par la résolution des équations de Poisson et de Schrödinger de manière cohérente, mais cela est souvent ignoré. La Fig. 4 présente la densité électronique simulée dans le film de silicium de 7 nm d'épaisseur (cf. Fig. 5) d'un MOSFET UTBB FDSOI pour différentes tensions de grille arrière VbG et pour une tension de grille avant fixe VGS = 1 V en utilisant l'outil de simulation Synopsys Sentaurus TCAD. Les différentes valeurs de VbG génèrent un champ électrique vertical variant dans le film

qui contrôle, à son tour, l'intensité de l'inversion volumique et par conséquent la concentration verticale des porteurs de charge. Pour VbG = 2 V, la densité électronique est presque constante loin des deux interfaces Si/SiO2 avant et arrière.

  Comme indiqué dans la première partie, les deux architectures permettent un excellent contrôle du canal ayant comme conséquence directe de très hautes performances en ce qui concerne les applications digitales grâce au contrôle des deux grilles et au film mince de silicium[22][23][24]. En revanche, grâce à des éléments parasites réduits, il a été démontré que la technologie FDSOI d'excellentes performances au niveau prédiction et évolution[31]. Cependant, ses performances RF n'ont été mises en évidence que dans[32] et demandent clairement une analyse plus approfondie. Les grandeurs digitales telles que ION et IOFF ne sont pas suffisantes pour évaluer le comportement analogique

	II. Le comportement DC et basse
	fréquence
	Leti-UTSOI2 (ou UTSOI2) est le premier modèle compact à double grilles indépendantes capable de décrire précisément le MOSFET UTBB FDSOI dans toutes les conditions de polarisation. Le fonctionnement à haute fréquence d'un transistor MOSFET est étroitement lié à sa condition de polarisation, et par conséquent à son fonctionnement en courant continu (DC). L'opération quasi-statique à haute fréquence peut être considérée comme une évaluation des dérivations multiples de l'opération DC, en ce sens qu'elle balaie une partie de la caractéristique I-V et "détecte" ses variations. Lorsque les variations de la tension appliquée aux terminaux du transistor sont suffisamment Un modèle compact sert de lien entre le processus de fabrication et la conception du circuit. C'est une description mathématique compacte de la physique des dispositifs complexes avec un compromis entre la précision et l'efficacité du calcul et le temps CPU induit. Un modèle compact basé sur la physique du dispositif permet à la fois aux technologues et aux concepteurs de circuits de prédire le comportement du transistor au-delà des données mesurées utilisées pour extraire le modèle. Comme pour les modèles du transistor MOSFET à grille unique, les modèles compacts disponibles pour le MOSFET double-grille reposent sur un coeur d'un modèle canal long auquel s'ajoutent divers effets physiques tels que les effets canaux courts (SCE), la dégradation de la mobilité, la saturation de la vitesse et les effets quantiques (QME). Les technologies FinFET et SOI entièrement déplété (FDSOI) remplissent les exigences ITRS (International Technology Roadmap for Semiconductors) pour la performances analogiques et RF et surpasse les technologies bulk et FinFET sur différents aspects RF [25][26]. En outre, le MOSFET UTBB FDSOI surpasse le FinFET en termes de fréquences de coupure comme le montre la Fig. 2 [10]. Le MOSFET UTBB FDSOI est par conséquent un meilleur candidat pour les applications faible Afin de profiter pleinement des avantages de la technologie FDSOI, les modèles compacts MOSFET doivent reproduire fidèlement le comportement du transistor dans toutes les régions d'opération, en particulier en faible inversion. Pour les calculs manuels souvent entrepris dans le monde du design analogique, bien que les modèles classiques de loi exponentielle en faible inversion et de loi carrée en forte inversion puissent être utilisés avec précaution, les abaques basés sur la notion du gm/ID développées dans la partie suivante sont plus pratiques pour prédire la performance du transistor MOSFET UTBB FDSOI à tous les niveaux d'inversion. De plus, pour un usage industriel et comme il a été mentionné précédemment, UTSOI2 est le premier modèle compact à double grilles indépendantes capable de décrire précisément le d'un transistor MOSFET. De plus, les applications analogiques telles que l'amplification nécessitent une prédiction précise des figures de mérite et des dérivées continues des caractéristiques du transistor MOSFET d'ordre supérieur et dans tous les niveaux d'inversion. miniaturisation des dispositifs. planaire avec un film et un BOX ultra-minces (UTBB) présente d'excellentes puissance et basse tension. Par conséquent, deux modèles quasi-statiques différents sont considérés dans

Trois

modèles sont des standards ou des candidats à la standardisation dans l'industrie du semiconducteur: BSIM-IMG, HISIMSOTB et Leti-UTSOI2. Tous les modèles sont basés sur la physique, évolutifs et efficaces pour les simulations de circuits. Tous ces modèles compacts incorporent plusieurs effets physiques, tels que les effets canaux courts (SCE), la dégradation de la mobilité, la saturation de vitesse, la résistance série, la modulation de la longueur du canal (CLM), les effets de la mécanique quantique, le courant de l'effet tunnel dans la grille, le DIBL et les capacités parasites. faibles, l'hypothèse du petit signal peut être considérée et des relations linéaires entre les variations de courant produites et les variations de tension d'entrée peuvent être utilisées. Par conséquent, une seule dérivation de la caractéristique I-V est suffisante pour prédire le comportement du MOSFET dans l'hypothèse d'un petit signal. La prédiction précise des dérivées de la caractéristique DC repose évidemment sur un modèle DC très précis. Par conséquent, un modèle précis pour le fonctionnement DC du transistor UTBB FDSOI est une nécessité.

Dans les circuits avancés de faible puissance et de haute performance tels que ceux mis en oeuvre dans le marché FDSOI pour l'internet des objets, il est nécessaire de faire fonctionner les transistors MOSFET dans des régimes de faibles à forts niveaux d'inversion

[27]

. Il convient de souligner qu'une région d'inversion modérée s'est avérée être un bon compromis quand la consommation d'énergie et la vitesse sont considérées avec le même niveau de priorité

[28]

[9]

[29]

. L'inversion modérée fournit une transconductance plus élevée pour un courant plus faible, et une bande passante qui reste acceptable pour les applications faible puissance et basse tension.

L'importance de la région d'inversion modérée et les problèmes de modélisation associés sont soulignés dans

[30]

.

MOSFET UTBB FDSOI dans toutes les conditions de polarisation, y compris à des tensions de polarisation élevées appliquées à la grille arrière

[15]

. Le modèle UTSOI2 a été validé par rapport à des simulations numériques (TCAD) et à des mesures en courant continu démontrant ces travaux pour le fonctionnement à basse fréquence et sont tous les deux utilisés comme blocs de base pour le développement d'un modèle non-quasi-statique haute fréquence amélioré: (1) un circuit équivalent petit signal présenté dans la Fig. 6 et (2) le modèle UTSOI2.

Leti-UTSOI2 Small Signal Equivalent Circuit with C m

Acknowledgments

his patience, support, and encouragement. Without his

List of Appendices

The cascode transistor is used to isolate the input from the inductive load. In particular, the Miller effect is reduced for the input transistor. However, using a cascode topology leads to a minimal room for drain to source voltage required to set both transistors in saturation. This also corroborates the need for MI operation as VDSAT is lower in this regime. The circuit of the cascode LNA is shown in Fig. The following specifications are taken as an example: Drain current is 2 mA, power gain is greater than or equal to 8, operation frequency is F0 = 35 GHz, minimal noise figure NFmin is no more than 2 dB, and input impedance is matched for 50 ohm.

In order to size the circuit components and meet the aforementioned specifications, the following 3 steps are followed:

IC selection

The maximum value of the FoM given in (6.2) and representing the trade-off between high frequency performance, power consumption, and noise figure is located in the second half of the MI for short channels as shown in Fig. 6.9 for two channel lengths (L = 30 nm and 1 µm).

Appendix A

The 1-D Poisson's equation of the lightly doped silicon film is written as:

where ψ(x,y) is the electronic potential in the silicon film, V(x) is the quasi Fermi level or the channel potential (V(0) = 0 and V(L) = VDS, ni is the intrinsic concentration, q is the elementary electronic charge, and εsi is the permittivity of the silicon.

The boundary conditions at the front and back interfaces using Gauss's law give:

3)

The charge neutrality in the structure gives:

For seek of simplification we define:

The integration of the Poisson's equation along with Gauss's law gives [START_REF] Reyboz | Continuous model for independent double gate MOSFET[END_REF]:

We will follow the approach of splitting the inversion charge into front and back inversion charges [START_REF] Reyboz | Continuous model for independent double gate MOSFET[END_REF].

Using (A. 4) and (A. 7) one gets:

And after a few rearrangement and using "tanh" function we have:

(A. 9)

The front and back inversion charges, respectively Qinv1 and Qinv2, can be defined such as:

In the case of a weak inversion on both interfaces (front and back), the inversion charge plays a minimal role in the structure electrostatic. The transverse electrical field is given by: ∂Ψ 7, e e = Ψ 7 -Ψ R 7 T (A. 12)

The charges in the two gates become:

In this case, (A. 10) and (A. 11) become:

When the two interface potentials are close to each other, the two last expressions converge to the symmetric gate MOSFET charge.

In the case where one of the interfaces is inverted, deriving (A. 2) with respect to ψs1 and using (A. 6) along with the charge conservation in (A. 4), we obtain:

where

We assume the silicon film is still weakly inverted, VbG is fixed, and Qinv1 >> Qinv2.

Using (A. 3), (A. 6) and (A. 13), we have:

The back gate charge is given by:

) becomes:

Consequently, the threshold condition for the front interface is:

where

With Qinv1 >> Qinv2 assumption, the "tanh" term in (A. 14) is equal to -1 and we get:

Using (A. 18) and (A. 19), we get:

Deriving the expression with respect to ψs1 results in Cinv1 expression:

The threshold condition (A. 21) becomes:

If we further assume Ψ R 7 -U A ≫ -. , we get:

Similarly, we get for the back interface:

.; = -0 • • -.

(A. 28)

Where

Using (A. 2), (A. 6), and (A. 18), and knowing that Qg1 = -Qg2 we get:

where

Using (A. 5) and (A. 13), inversion charge expression (A. 14) becomes:

Using (A. 19) and (A. 30), we get:

And consequently we have:

The front interface inversion charge writes:

Where VTH1' is the threshold voltage of the front gate inversion, which is dependent on the back gate voltage:

Appendix B

In Leti-UTSOI2 case, the integration of the 1-D Poisson's equation (A. 1) along with the boundary conditions, result in three coupled equations:

where Q(x) is a coupling charge that can be real (hyperbolic mode) or imaginary (trigonometric mode). The originality of Leti-UTSOI2 is the form of the equation (B. 3

as there is no need to know a priori the mode of operation (hyperbolic or trigonometric).

Using a coth -1 instead of tanh -1 as in [START_REF] Ortiz-Conde | Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET[END_REF], simplifies the solution as no more signfunction is required. A rearrangement of (B. 3) using a coth identity provides three useful equivalent equations, and the derivation in [START_REF] Poiroux | Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies -Part I: Interface Potentials Analytical Model[END_REF] ends up with a single equation that is solved analytically to calculate the surface potentials ψs1 and ψs2 using an initial guess and correction steps. Once surface potentials are calculated, the inversion charge is obtained for all levels of inversion as a sum of a front and back inversion charges using front and back gate charges and capacitances [START_REF] Poiroux | Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies -Part I: Interface Potentials Analytical Model[END_REF].

In order to obtain the drain current expression, the general expression (2.9) is used with an effective average mobility µeff. An effective electrostatic potential is defined as:

and its value is calculated at the source and drain side using the inversion charge density and its derivative with respect to xdrift at both the source and drain. Then, knowing xdrift value at the source and drain, the charge density along the channel is derived. The analytical integration of the inversion charge with respect to xdrift results in a closed form of the drain current ids [30]. The mobility model is treated as usually in compact models including Coulomb, phonon, and surface roughness scattering to calculate the effective mobility µeff. The difference with respect to bulk is that Leti-UTSOI2 is considering a repartition of the effective mobility into front and back parts.

The drain current expression is given as:

where vsat is the saturation velocity, δxdriftds is the difference of xdrift value between drain (xdriftd) and source (xdrifts), and ids is given as:

where qis and qid are the inversion charge density at the source and drain respectively, ds (dd) is the derivative of qis (qid) with respect to xdrift, and :

Ground-plane depletion

The highly doped region underneath the BOX can be accumulated or depleted, which alters the effective BOX oxide thickness. The effect is modeled as in bulk PSP as the region underneath the BOX is considered as the channel of a Bulk MOSFET.

Quantum confinement

The quantum well physically formed by the thin silicon film between the front and back dielectrics.

The second aspect is the vertical field induced quantum well. Both are taken into account and modeled.

Velocity saturation Velocity saturation is accounted for similarly as in [31].

Short channel effects

The 2D electrostatics is accounted for using the coupling between front gate, back gates, source, and drain.

Channel length modulation

The channel length modulation is implemented as in bulk PSP but using a simpler expression of the relative channel length reduction.

Series

Résultats du travail de recherche

Les principaux résultats de ce travail de recherche sont résumés ci-après.

Perspectives

Validation grand signal

Bien que les modèles petits signaux soient souvent suffisants pour la conception des circuits linéaires, la conception des circuits non linéaires tels que les amplificateurs de puissance et les oscillateurs nécessite une prédiction précise des caractéristiques non linéaires des transistors MOSFET dans une large gamme de conditions de polarisation. Le circuit équivalent développé dans cette thèse est un modèle petit signal et ne peut être utilisé qu'avec des circuits linéaires. Cependant, le modèle UTSOI2 augmenté, également proposé dans cette thèse pour la simulation de circuits industriels, est conceptuellement un modèle grand signal à condition de supposer que la performance grand signal du circuit est principalement gouvernée par