Nicolas Monnereau

Fabrice Caignet

Nicolas Nolhier

Marise Bafleur

David Trémouilles

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Keywords: Electrostatic discharge (ESD), Input Output Buffer Information Specification (IBIS), behavioral modeling, ElectroMagnetic Compatibility (EMC)

published or not. The documents may come

L'archive ouverte

I. INTRODUCTION

YSTEM level ESD has become an important concern since IC's technologies have reached deep submicron dimensions. Moreover the recent years have seen the explosion of embedded applications in various fields like multimedia, automotive, aeronautics, etc… In some applications, people safety has to be considered and as a result, reliability requirements are even tougher. Before detailing the objectives of reliability regarding ESD, it is important to define system level ESD. In this work the considered system is a printed circuit board (PCB) including all the passive and active components. When a system level ESD occurs, the strong current generated during the discharge will propagate through the PCB to reach the ground, thus generating high voltages and currents. The ESD requirements become even more severe with the emergence of applications directly exposing specific IC pins to the outside world. As a result, the demand for robustness against system-level HBM, defined by IEC61000-4-2 standard [START_REF] Mergens | ESD Protection Considerations in Advanced High-Voltage Technologies for Automotive[END_REF], is increasingly shifted to the IC component itself [START_REF] Mergens | ESD Protection Considerations in Advanced High-Voltage Technologies for Automotive[END_REF] [START_REF] Smedes | Relations Between System Level ESD and (vf-) TLP[END_REF]. Therefore, taking into account these disturbances during the system design phase becomes necessary to improve the system immunity, which tends to decrease with technology nodes, as observed by Camp [START_REF] Camp | Influence of the Technology on the Destruction Effects of Semiconductors By Impact of EMP and UWB Pulses[END_REF]. Two aspects have to be considered when talking about ESD reliability. The first one is the robustness, which is the ability of the product to avoid destruction. An ESD stress generates high current density dissipated into the IC, which could induce thermal effect or oxide breakdown [START_REF] Semenov | ESD protection device and circuit design for advanced CMOS technologies[END_REF], [START_REF] Stadler | From the ESD robustness of products to the system ESD robustness[END_REF] and [START_REF] Stadler | Do ESD fails in systems correlate with IC ESD robustness ?[END_REF]. Robustness to failure has been largely studied at chip level. Another consequence of ESD stress is the susceptibility failure like RESET, clock cycle losses, data error [START_REF] Besse | Identifying electrical mechanisms responsible for functional failures during harsh external ESD and EMC aggression[END_REF]. In previous papers [START_REF] Lacrampe | Investigation of effects of an ESD pulse injected by a near-field probe into an oscillator block of a 16-bit microcontroller[END_REF] [START_REF] Lacrampe | Investigation on ESD Transient Immunity of Integrated Circuits[END_REF] we have pointed out that ESD events can generate microprocessors RESET and clock cycle losses. These failures were directly correlated to the amplitude of the injected TLP pulse . Failure issues revealed by the IEC61000-4-2 standard test [START_REF]testing and measurement techniques -electrostatic discharge immunity test[END_REF], which is one of the most important and focuses on system level ESD, are becoming more and more significant since IC's technologies have reached deep submicron dimensions. Up to now, designers of electronic-system focused on the ESD robustness of a product. However, nowadays, more and more applications involve the user's safety. As a result, the products have to fulfill different classes of functionalities defined by the standards [START_REF]testing and measurement techniques -electrostatic discharge immunity test[END_REF]. In automotive applications, products must handle an ESD event, without any disturbances like reset or even clock loss [START_REF] Besse | Identifying electrical mechanisms responsible for functional failures during harsh external ESD and EMC aggression[END_REF]. From the system designer's point of view, no circuit's models and no information about IC internal protection's structures are available from manufacturers to predict failures during ESD events. Manufacturers provide only the datasheets (functionality and electrical characteristics) and IBIS models [START_REF]IBIS (Input Output Buffer Information Specification)[END_REF], but up to now, no information that could be used for ESD simulations. IBIS files already provide a lot of information about I/O pins of an IC buffer. One of the main advantages is that it does not reveal any information about architecture or process, which can compromise the intellectual property of semiconductor manufacturers. An

S

improvement of these models with relevant parameters for network ESD protection elements into the IC would allow achieving system level IC models. To this purpose, a behavioral modeling methodology, in the same spirit of IBIS concept, i.e. preservation of proprietary information, is proposed in this paper.

In the present paper we focus on the understanding of the ESD stress impact on the clock of a commercial IC. The system is based on a D flip-flop component mounted as a divider by two. The ESD stress is injected on the power bus of the circuit using the Electromagnetic compatibility (EMC) method described in IEC 62132-part 4 [START_REF]Integrated circuits, Measurement of electromagnetic immunity -150 kHz to 1 GHz -Part 4: Direct RF power injection method[END_REF], also called DPI injection technique. The defined susceptibility criterion is the loss of one clock cycle. We describe the different parts of the setup used to disturb the IC, and the models developed in order to accurately predict its behavior. In a previous paper [START_REF] Monnereau | Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation[END_REF] we have presented a methodology to build behavioral simulation of system level ESD to study the propagation of an ESD into a system. In this paper, we applied and improved the methodology with behavioral ESD protection's structures, in order to both predict the susceptibility and try to extract a basic formulation of the failure probability. Measurement data of the evolution of the probability to generate a fault depending on the influence of an external decoupling capacitor are presented, and compared to theory.

II. SYSTEM DESCRIPTION AND TEST BENCH

Figure 1 shows the simplified schematic of the studied system built around a CMOS 0.25um D flip-flop configured as a frequency divider. An external decoupling capacitor is placed as close as possible to the IC, between VDD pin and the ground plane.

To evaluate the susceptibility of the circuit, an ESD disturbance is injected into the V DD pin using the DPI technique [START_REF]Integrated circuits, Measurement of electromagnetic immunity -150 kHz to 1 GHz -Part 4: Direct RF power injection method[END_REF]. The susceptibility level of the output is monitored. Transmission Line Pulse (TLP) tester [START_REF] Maloney | Transmission line pulsing techniques for circuit modeling of ESD phenomena[END_REF] is used to inject a rectangular pulse of 100ns duration having a 1 ns rise and fall time. It has an excellent reproducibility and does not generate electromagnetic disturbances. This is not the case for the gun testers usually used at system level as recommended in the IEC61000-4-2 standard [15] [START_REF] Lin | Metrology & methodology of system level ESD testing[END_REF].

The TLP tester is connected through a DC block composed of a 6.8nF capacitor as shown in Figure 1.

A voltage regulator supplies the D flip-flop through a decoupling network including a diode and a 5.6uH inductor. This network ensures that all the TLP current discharge only stresses the device under test and not the regulator. The regulator current is limited to 150 mA to prevent any latch-up issues. If a latch-up occurs and shortcircuits the power pin, a voltage drop at the regulator output will be visible.

A dedicated Printed Circuit Board (PCB) has been designed for the study including all the elements previously described. The printed circuit is made on a 1.6mm thick PCB FR4 substrate. SMA connectors are used to connect the board to the TLP tester, the function generator and other instruments. All electronic components on the board (capacitor, inductor, resistance, and diodes) are Surface Mounted Devices (SMD).

A function generator is connected to the CLK pin to synchronize the D flip-flop configured as a frequency divider. The disturbance is injected on the V DD pin. The output Q of the D flip-flop is monitored on the oscilloscope with 1 MΩ impedance. The oscilloscope is triggered on the rising edge of the TLP pulse.

As described in papers [START_REF] Lacrampe | Investigation of effects of an ESD pulse injected by a near-field probe into an oscillator block of a 16-bit microcontroller[END_REF][10], for all ESD pulse amplitudes, the output is disturbed. Therefore it is necessary to choose a failure criterion. In our case the loss of one clock edge was arbitrarily chosen. The probability of generating an error by following this failure criterion is studied according to the impact of the decoupling capacitor value, the operating frequency and the level of the disturbance is studied.

III. MODELING AND SIMULATION

A. Modeling of the system The modeling of the system is based on previous work [START_REF] Monnereau | Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation[END_REF][17] [START_REF] Monnereau | Behavioral-Modeling Methodology to Predict Electrostatic-Discharge Susceptibility Failures at System Level : an IBIS Improvement[END_REF] and VHDL-AMS (Very-high-speed integrated circuit Hardware Description Language -Analog and Mixed Signals) is used as the description language [START_REF]VHDL Analog and Mixed-Signal[END_REF]. The methodology is intended to model a system composed of digital ICs mounted on a Printed Circuit Board. The main principle consists in modeling each system part separately and assembling all parts hierarchically by following the system topology. The PCB and environment modeling is carried out following the methodology described in [START_REF] Monnereau | Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation[END_REF], but a new approach for the ICs is proposed here. A behavioral modeling is applied to model the IC ESD protections, and the IC core to take into account the circuit operation. This section describes respectively the IC ESD protections and core modeling.

The figure 2 shows the simplified schematic of the integrated circuit built to evaluate system level ESD susceptibility. The model is built around the functionality of the chip described in VHDL language ("Function D flipflop" center block). The input and output buffer information is added to the VHDL-AMS model from the Input/Output Buffer Information Specification (IBIS) file [START_REF]IBIS (Input Output Buffer Information Specification)[END_REF]. The IBIS standard provides signal integrity designers with I(V) tables of buffers, V(t) tables for the dynamic output buffers, passive-elements of the package pins, input/output (I/O) equivalent capacitances (Ccomp) and others. The "2-state IBIS output buffer" blocks include the V(t) and I(V) curve of the pull-up and the pull-down of each output. A numerical signal from the core of the circuit allows triggering the output transitions. The "IBIS input buffer" blocks allow taking into account the threshold voltage levels that switch the component to high or low levels. To build these blocks the V IH and V IL from the datasheet information is used and combined to IBIS. Although the IBIS file gives tables of "ESD_clamps", the ESD protection elements are based on TLP and static measurements and modeled into VHDL-AMS.. Note that in the IBIS standard, the structure called "power clamp" represents the structure between one I/O and V DD , and not the protection between V DD and V SS as commonly used in the ESD community. 1) Extracting parameters from measurement From quasi-static I(V) curves, behavioral models of the protections are built following machine state diagrams. Figure 3 gives the state machine example of a diode (a) and a SCR (b) extracted from the simplified reported characteristics. The main difficulty of such models is to fulfill the convergence of the simulator for strong discontinuities (like between state 1 and 2 of the SCR). This is overcome by adding in parallel to the protection structures the parasitic capacitances given by IBIS form each I/O. This is fully detailed in [START_REF] Besse | ESD system level characterization and modeling methods applied to a LIN transceiver[END_REF] and [START_REF] Monnereau | Behavioral-Modeling Methodology to Predict Electrostatic-Discharge Susceptibility Failures at System Level : an IBIS Improvement[END_REF]. One TLP measurement example of the SCR-based ESD protection structure is given in figure 4. The inflexion points of the measured waveform are extracted as parameters to build the model. Six couples of voltage and current parameters (Vx, Ix) are needed to implement the full SCR model as reported in figure 4 andtable 1. Four states, highlighted on the measurement, are identified: no conduction (0), reverse conduction before snapback (1), snapback (2), forward conduction (3). For each SCR states, a generic linear equation is used. The current I, and voltage V, are respectively the current flowing through and the voltage across the structure. The curve slope and the yintercept are computed from parameters of table 1. For the SCR, four simultaneous equations, each defined by a state, must be solved. A simultaneous "If" statement structure is used to switch from one equation to the other. Change-equation conditions could be defined by two ways. For simple structures, such as a diode, condition could be directly defined in the analog solver on voltage or current level. In this case, only the analog core is used. This kind of condition does not permit to model a structure such as a SCR. The main difficulty with SCR is the modeling of the discontinuity when it goes into snapback states. To define more complex change states conditions, the digital core of the VHDL-AMS simulator is used as explained in the next section. 2) Using the Digital Core for State machine This section describes how to define the change state conditions for the model using the digital core. As a starting point, a state diagram is developed to define the release statement conditions of the SCR (figure. 3b), in which all the changes are reported. Moving from State 0 to State 1 implies that the voltage across the SCR must be higher than V3 defined by the parameter number 3 in Table 1. Reciprocally, to move from state 1 to state 0, the voltage across the SCR must be lower than V3. An access to a state can only be defined in one way. When the voltage V is above V4, the state switches to state 2 (snapback). However, no return condition is defined between state 2 and 1. The SCR can leave state 2 only to switch to state 0. A digital signal used as flag allows indicating to the analog solver the state of the SCR as indicated in figure 5. It is updated each time the process ends. This flag is used as condition in the "If" statement of analog core. The VHDL-AMS source file corresponding to the SCR is reported in figure 6. The main advantage of this method is that it is possible to model complex ESD functionalities such as the discontinuity induced by the snapback of a structure. Moreover, VHDL-AMS allows complex interactions such as the derivation for the modeling of active ESD structure. Using simple information, such as six I/V points for SCR structures, it is easy to build behavioral models for ESD system level simulation. Before using full behavioral models, semi-physical models have been investigated in [START_REF] Monnereau | Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation[END_REF]. The same results have been obtained with a significant decrease in computation time for the behavioral models.

3) Circuit modeling from IBIS and Behavioral ESD Protection Model

The circuit studied here includes diodes from ground to outputs and outputs to V DD , SCR between inputs and ground, and a power clamp between V DD and GND. From TLP measurement, it is impossible to determine the actual design of the power clamp, but the IBIS behavioral description makes appear that the structure triggers on dV/dt. So in our VHDL-AMS model, the I(V) curve looks like the characteristic of a diode, but the triggered condition is defined by the VHDL command "V'dot>0.1e9". The Finally the parasitic elements of the package and the input and output capacitances provided by the IBIS file are added. The "IBIS Input Buffer" defines the High-level and Low-level input voltage (V IH and V IL ), extracted from the datasheet, proportional to V DD -V SS . The function of the circuit core, represented in grey on figure 2, is described in VHDL. The new circuit model following the modeling methodology allows analyzing the system behavior circuit during an ESD disturbance.

B. Comparison of the measurement data and the simulation results

The measurement and simulation are performed with a 50nF external decoupling capacitor between VDD and ground, and a 75V TLP injection. The clock input frequency is 2MHz. Figure 8 shows the comparison of measurements and simulations in two cases (a) and (b). In configuration (a), the ESD disturbance occurs far from the clock synchronization point, which is the rising edge of the clock pulse. The output signal is still operating normally even if a strong disturbance is observed on the output signal. In configuration (b), the ESD event takes place at the time when the clock synchronization occurs and is not taken into account by the D flip-flop. The output voltage remains at a high level and one period of the input signal is lost. More details about the failure mechanisms are given in section IV-B. As shown on Figure 8, the simulation matches the measurements. Our modeling approach allows predicting what happens during an ESD event, specifically the analysis of the circuit behavior interaction with the system. A similar case that could introduce some failures is when the perturbation occurs close to the synchronization signal whereas the output is at low level. As in the previous case, clock synchronization is lost. Measurement and simulation related to this case are reported in Figure 9. The simulation shows that the output keeps at a low level after the ESD stress. The simulation was not able to reproduce the observed noise close to the synchronization signal.

IV. PROBABILITY

A. Measurements of susceptibility failures Measurement of failure probability has been performed regarding the external decoupling capacitor value (50nF and 6,8nF), the operational clock frequency (2, 5 and 10Mhz) and the ESD pulse amplitude (10 to 200V precharge voltage). Each TLP amplitude was repeated a hundred times. The TLP pulse is repeated every two seconds to avoid possible charge effects. All the results are computed and the percentage of failures is extracted and reported in Figure 10. For the low capacitor value and for high operating frequency, the probability to generate failures is increased.

B. Analysis

To simplify the situation as much as possible we start by considering the electrical schematic (fig 1). For this system we will only take into account the IC and its ESD protection between VDD and ground and the decoupling capacitor C dec . Let us consider the case where the voltage across the decoupling capacitor does not reach the triggering value of the protection. A transition on the output occurs when a rising edge on the CLK signal is detected. The triggered input voltage, VIH, of the CLK signal is given by the datasheet as VIH = 0.7*VDD. When the TLP stress occurs, the internal power supply bus voltage increases as the external decoupling capacitor C dec and the VIH of the clock do. Two cases have to be considered: if the VIH level is lower than the clock input signal, the output switches to low-state (configuration a); if VIH is higher than the clock input signal it is not detected (configuration b). In the case displayed in figure 8, VIH reaches the value of 3.15V when VDD reaches 4.5V while the clock signal is between 0 and 2.2V. If the clock signal appears while VIH is higher than 2.2V it will not be taken into account. This occurs if VDD is higher than 3.15V, which will be defined as the critical power supply value V crit . Let us assume that, as reported in Figure 11, a failure is generated if a clock event occurs while the power supply is over V crit during a fixed time (T failure ). So the probability to generate a failure is: [START_REF]testing and measurement techniques -electrostatic discharge immunity test[END_REF] Where T clk_cycle is the synchronization clock cycle. To estimate (in a first approximation) this probability, we have to formulate T failure , which is the sum of T f_charge and T f_discharge . T f_charge, is the time during which the power supply voltage exceeds V crit corresponding to the capacitor charge and T f_discharge is the time during which the power supply voltage exceeds V crit corresponding to the capacitor discharge.

1) 1. Estimation of T f_charge : Since the increase of V DD during the TLP pulse (TLP amplitude = I TLP , and TLP duration = T TLP ) is forced by the external capacitance C dec , we can use the basic equation ( 2).

(

V crit is reached at the time :

(3) If V reach is over V crit . Then T f_charge is defined by

T f_charge = T TLP -T crit (4)
2) Estimation of T f_discharge : The discharge is more complex because the only discharge path goes through the IC via its Pull-Up transistor. The equivalent resistance, R Pull_up , given by the IBIS files is around 8 Ohms and so, the evolution of the discharge voltage, V disch is : [START_REF] Semenov | ESD protection device and circuit design for advanced CMOS technologies[END_REF] where τ is the R Pull_up . C dec product. It results that T f_discharge is :

(6) [START_REF] Stadler | Do ESD fails in systems correlate with IC ESD robustness ?[END_REF] Finally, the probability to generate a failure in this case is given by :

€ P failure = T failure T clk _ cycle ! I = C dV dt € t crit = (V crit -V DD ).C dec I TLP € V disch (t) = V DD + (V reach -V DD )e -t τ € T f _ disch arg e = -τ.ln V crit -V DD V reach -V DD $ % & ' ( ) € T f _ disch arg e = -τ.ln V crit -V DD ( ) .C dec I TLP .T TLP -V DD .C dec $ % & & ' ( ) ) (8)
According to this set of equations, an error could happen as soon as Vcrit is higher than 2.2V in our configuration (T TLP = 100 ns and C dec = 50nF), i.e. when VDD>3.15V. The minimum TLP pulse that could generate this perturbation is extracted from (2) which is the correct measured value:

i.e. V TLP > 52V

In Figure 12, equation ( 8) is plotted and compared to measurement data for C dec =50nF. The probability fits correctly for higher frequencies but not well when the amplitude of the stress increases.

When the amplitude of the TLP is high enough to cause the power supply bus VDD to reach the triggering value of the power clamp (7V), a part of the current goes through the ESD protection slowing the charge of the capacitor and reducing the probability of upset. The triggering voltage of the power clamp (PC) is reached for a TLP injection of :

Where V th is the triggering voltage of the power clamp.

For the 50nF decoupling capacitance, Vth corresponds to I TLP =2.5A, i.e. 125V injection, and for the 6.8nF, to 0.37A, i.e. 18V. In comparison to Figure 10, the chances in the probabilities seem to be in this range of about 100V for 50nF injected voltage. This validates the impact of the power clamp to reduce the probability of failure. But what happens when the injected TLP voltage increases? is predicted with a very good accuracy. Concurrently, a basic analysis has been conducted to define a simple formulation of the failure probability. A preliminary model based on a simple theory have been proposed and compared with measurement. The influence of the ESD protection on the evolution of the failure probability has been demonstrated but modeling improvement is still needed to establish a generic formulation.

Fig. 1 :

 1 Fig. 1: Simplified schematic of the system with DPI injection

Figure 2 :

 2 Figure 2: Simplified integrated circuit model with ESD protection from measurement and input and output buffer from IBIS model

Figure 3 :

 3 Figure 3: Example of the machine states describing the behavior of the ESD protection.

Figure 4 :

 4 Figure 4: Quasi-static (TLP) measurement of a SCR protection structure.

Figure 5 :

 5 Figure 5: Process organization chart.

Figure 6 :

 6 Figure 6: VHDL-AMS SCR description.

figures 7 a

 7 figures 7 a and b report the simplified I(V) curves and the state diagram machine respectively.

Figure 7 :

 7 Figure 7: Characteristic and state machine diagram used for the behavioral description of the Power Clamp.

Figure 8 :

 8 Figure 8: Transient measurements and simulations of the output voltage for configuration (a) and (b).

Figure 9 :

 9 Figure 9: Transient simulations of the output voltage when the ESD stress occurs on a low level of the output.

Figure 10 :

 10 Figure 10: Evolution of the failure probability as a function of the external decoupling capacitance (Cdec), the clock frequency and the ESD pulse amplitude

Figure 11 :

 11 Figure 11: Chronograms showing the signal evolution during the ESD TLP stress.

Figure 12 :

 12 Figure 12: Evolution of failure probability depending on external decoupling capacitance (Cdec = 50nF), clock frequency and ESD pulse amplitude Figure 13 displays the simulation waveforms of the internal VDD voltage, and the current through the PC for a 400V TLP injection. The results from two simulations are shown, one taking into account the PC and the second one without

Figure 13 :

 13 Figure 13 : Transient simulations of the current through the power clamp (PC) and of the internal VDD voltage (without the PC : black, and with the PC : grey).V. CONCLUSIONThe susceptibility of an IC configured as a simple D flipflop is investigated and the impact of ESD stresses is investigated during system operation. The failure probability is addressed and linked to the parameters of the external decoupling capacitor, the operational frequency and the stress amplitude. The full simulation of the system is carried out using a behavioral description. The protection strategy has been extracted from quasi-static measurement.The functional core chip is described in VHDL, and I/Os buffers are introduced from IBIS description file. As shown in this paper, the behavior of the IC undergoing ESD events

  Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

	Nicolas Monnereau 1,2 , Fabrice Caignet 1,3 , Nicolas Nolhier 1,3 , David Trémouilles 1,2 , Marise Bafleur 1,2
	1 CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France

2 Univ de Toulouse, LAAS, F-31400 Toulouse, France 3 Univ de Toulouse, UPS, LAAS, F-31400 Toulouse, France

TABLE I .

 I SCR PARAMETER EXTRACTION FROM QUASI-STATIC CURVE

	Parameters	1	2	3	4	5	6
	Voltage (V)	-1	-0.6	12	13	2	3
	Current (A) -0.5	0	0	0.2	0.2	2

ACKNOWLEDGMENT

This research was supported by ANR E-SAFE project. The authors would like to thank Michael Hopkins for reviewing this paper.


Chan Aurélie
email: aurelie.chanyong@telecom-bretagne.eu

Kevin Yong

Christiane Heggarty

Denis Carré

Battarel

A Chan Yong

K Heggarty

C Carre

D Battarel

Rapid prototyping of diffractive optical elements in microstructured sol-gel hybrid material

Introduction

Diffractive optical elements (DOEs) are currently gaining increased acceptance in the photonic industry in a wide range of applications such as laser beam shaping (e.g. in micromachining), information technology, telecommunications, medical and aerospace. DOEs can notably limit the loss of light, correct optical aberration and reduce the volume of an optical assembly. However, their more extensive use is often hindered by the barrier of high prototyping costs -cost advantages only appearing in mass production. We aim to reduce the entrance barrier to this technology by the development of rapid and simple prototype fabrication processes.

For laboratory prototypes, photoresist DOEs are widely used. They are simple to fabricate by parallel direct-write; this technique has chosen by TELECOM Bretagne and its spin-off company HOLOTETRIX. However, for many industrial applications the properties of photoresist are insufficient: optical (diffraction efficiency, resistance to high power laser beams), mechanical (hardness, durability and strength), thermal (stability) and chemical (resistance to usual cleaning solvents). To solve this problem, we have developed a process based on direct molding of a photoresist DOE in higher performance hybrid sol-gel material without the need for a time-consuming and costly nickel master.

Discussion

A DOE modifies the spatial distribution of a light beam by diffraction. The diffracted light creates several wavefronts which interfere and recombine to give the desired light distribution in the reconstruction plan. In our study, the DOEs [1] modify the phase of the lightwaves. In this case, the differences in optical path from one point to another of the DOE are produced by local variations of thickness in the material. The patterns created with thickness variations are calculated (digital algorithms) from the incident wave and the desired diffraction pattern.

In our laboratory, DOEs fabrication is accomplished by two main photolithographic techniques: 1. by direct light irradiation through a reconfigurable mask into photoresist (PR) and 2. by irradiation molding in a hybrid sol-gel material (HSG).

1. The first material is a commercial positive PR: SHIPLEY S1805 [2]. Its microstructuration is realized directly with a high speed parallel-write photoplotter at TELECOM Bretagne [1] operating at the wavelength of 436 nm (wavelength included in the visible absorption band of the PR). The photoplotter uses a liquid crystal micro-screen as a reconfigurable mask. The pattern on the micro-screen is projected onto the photosensitive using a high performance photoreduction lens. After development, the element is hardened by further UV illumination and final thermal treatment.

2. The second material is a HSG of the ORMOCER® family: Ormocomp [3]. This is a liquid photopolymer, which absorbs up to 400nm and can be cured at 365nm (peak emission wavelength of a mercury lamp). HSG, efficient for nanofabrication [4], can also be tailored for our project. We transfer the three-dimensional pattern of a photoresist DOE to the HSG by molding. A mask-aligner is used to control the contact and press both materials and to irradiate at 365nm for initiation of the HSG polymerization. After curing, PR and HSG are separated. HSG element is further processed (thermal treatment) to optimize its properties.

The replication process has been validated after analysis of the optical properties and comparison between microstructure of PR template and corresponding HSG copy. The patterns and the thickness layer measurements show high fidelity (Fig. 1). The HSG material has a higher industrial performance than PR because it is a hybrid organic/inorganic material. The interest of the two-steps process is the use of HSG corresponding to a monomer combining a polymerizable function and a mineral part. The organic part enables microstructuration by photochemical means and the inorganic structure gives the final material glass-like properties. HSG offers better optical (transparency), mechanical (hardness, strength), thermal (stable up to 270°C) and chemical (resistance to usual solvents: acetone and isopropanol) properties compared to PR (stable up to 145°C, soluble in acetone and isopropanol).

Conclusion

The fabrication of HSG elements by direct molding from PR micro-patterns has been demonstrated and HSG shown to be a high-performance material for DOE fabrication. HSG is better suited to industrial requirements such as cleaning with usual solvents. The next steps concern the production of multiple replicas in HSG by micro-imprint with one HSG mold or by dicing a multi-DOEs substrate.

  A. CHAN YONG, K. HEGGARTY, C. CARRE, D. BATTAREL, "Rapid prototyping of diffractive optical elements in microstructured sol-gel hybrid material", Proc. of 2nd EOS Conference on Manufacturing of Optical Components (EOSMOC 2011), (2011).

Fig 1 .

 1 Fig 1. DOE pattern: 3D views (a) and profiles (b) performed by interferometric microscopy


Nicolas Monnereau

Fabrice Caignet

David Trémouilles

Nicolas Nolhier

Marise Bafleur

A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

HAL is

Index Terms-Electromagnetic compatibility (EMC), electrostatic discharge (ESD), modeling, system level, time-domain simulation.

During their manufacturing and use phases, electronic products are subject to electrostatic discharges (ESD) disturbances.

In the case of stand-alone circuits, a dedicated ESD protection strategy is implemented inside the silicon chip using protection elements like diodes, siliconcontrolled rectifier (SCR), MOSFET etc. The main goal of this strategy is to evacuate the high ESD current from one port to the other, whatever the possible connections exposed to the stress. The first step, to design efficency IC ESD protection is the development of stand-alone protection devices.

Semiconductor designers can use various tools to help them in the design and characterization of ICs. Physical modeling tools provide a good estimation of the performance of on-chip protections. These models are validated by a set of measurement methods like transmission line pulsing (TLP) [START_REF] Maloney | Transmission line pulsing techniques for circuit modeling of ESD phenomena[END_REF], very fast TLP (VF-TLP) [START_REF] Gieser | Very-fast transmission line pulsing of integrated structures and the charged device model[END_REF].

N. Monnereau, F. Caignet, D. Tr´emouilles, and M. Bafleur are with the Laboratory of Analysis of System Architecture, CentreNational de la Recherche Scientifique, Toulouse F-31400, France (e-mail: nicolas.monnereau@laas.fr; fcaignet@laas.fr; david.tremouilles@laas.fr; Marise.bafleur@laas.fr). N. Nolhier is with the Laboratory of Analysis of System Architecture, Centre National de la Recherche Scientifique, Toulouse F-31400, France, and also with the University Paul Sabatier, Toulouse 31062, France (e-mail: Nicolas.nolhier@laas.fr).

To ensure that the product is sufficiently robust regarding ESD events, which can occur during the manufacturing process, the very well-known standards like the human body model [START_REF]Electrostatics-Part 3-1[END_REF] and charge device model [START_REF]Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components[END_REF] are required.

The ESD protection problem is specific when the ICs are mounted on a printed circuit board (PCB). Electronic equipment operating in real world is subject to more severe ESD stress than in manufacturing ESD-controlled environment. Moreover, complex interactions between passive and active components (ICs, PCB lines geometry, passives. . .) and the environment significantly impact the ESD waveform. The IEC 61000-4-2 standard test [START_REF]Part 4-2: Testing and Measurement Techniques-Electrostatic Discharge Immunity Test[END_REF] is widely used to evaluate system robustness against ESD. Up to now this standard is the only one available that can be applied on final products like multimedia ones. It does exist another standard called ISO10605, but it is dedicated for automotive applications [START_REF]Road Vehicles-Test Methods for Electrical Disturbances From Electrostatic Discharge[END_REF], [START_REF] Besse | Correlation between system level and TLP tests applied to stand-alone ESD protections and commercial products[END_REF]. The IEC 61000-4-2 standard has been developed twenty years ago for electromagnetic compatibility (EMC) in order to evaluate the ESD susceptibility of systems. It is intended to emulate real world events such as human body discharge into a system. When ESD issues are revealed, there is a lack of investigation's method, which can lead to many unsuccesful system redesigns. Moreover, there are not enough design tools that allow an accurate prediction of the possible ESD propagation paths and events. Designers need modeling methodologies able to simulate the design before prototyping to anticipate ESD failures and provide the most suitable solutions to protect the product combining efficiency and low cost. In this paper, a methodology to build a behavioral and accurate model of a system is proposed and evaluated to predict current paths during ESD events. A simple system, made up of an inverter and its passive components required for its proper operation, is used to illustrate the proposed modeling methodology. Each part of this system is modeled separately using very-high-speed integrated circuit Hardware Description Language-Analog and Mixed Signals (VHDL-AMS) [START_REF]VHDL Analog and Mixed-Signal[END_REF]. The main advantage of using such behavioral description language is to build the complete system level simulation using building blocks that can be assembled hierarchically to model the whole system as represented in Fig. 1.

We will describe how to build each block and to achieve full system modeling. A dedicated PCB including specific measurement methods has been designed to validate the approach and to demonstrate that it is possible to obtain accurate results within a high level of abstraction. This paper is organized in six sections. After this brief introduction, the system, and test methods used to compare the developed simulation methods and measurement methods are presented in Section II. Section III describes how IBIS models are improved for system level simulation. Section IV details the implementation of each block for system modeling. Section V presents analysis of some cases study in which the complex current shape is thoroughly analyzed and explained. Section VI reports comparisons between measurement and simulation. Fig. 2. Studied case schematic with case 1 and 2 injection and "one-ohm measurement" method.

II. PCB AND TESTS METHODS

The studied system is built around a commercial inverter integrated in 0.25-µ m CMOS technology. The system is composed of the IC, a few passive components and PCB lines as shown on Fig. 2. Two cases are investigated in this paper. 1) Case 1 : Study of the impact of an external capacitance C1 used for IC power-supply decoupling (between VDD and VGND) when an ESD event occurs on the output to ground. 2) Case 2 : Study of the impact of an external capacitance connected between the input and ground plane C2. ESD injection is performed on the input to ground. A dedicated PCB, shown in Fig. 3(a), was realized to perform measurements and ESD injections. All IC pins are connected to SMA connectors through the same PCB layout structure. Depending on the passive components mounted on this dedicated structure, various ways of measurements and injections can be performed. Measurement techniques included on this structure are mainly extracted from EMC standards, which allow measuring the conducted emissions of an IC [START_REF]Integrated Circuits, Measurement of Electromagnetic Emissions, 150 kHz to 1 gHz-Part 4:Measurement of Conducted Emissions-1w/150w Direct Coupling Method[END_REF]. To measure the current, which flows into the circuit, a measurement method called "one-ohm measurement" issued from the EMC standard IEC61967 [START_REF]Integrated Circuits, Measurement of Electromagnetic Emissions, 150 kHz to 1 gHz-Part 4:Measurement of Conducted Emissions-1w/150w Direct Coupling Method[END_REF] is used. Initially, intended to measure the IC power supply conducted emissions, this technique was used to measure the current that circulate into the circuit during an ESD stress. A 1Ω resistance is inserted into the ground path. The 50Ω impedance adaptation is obtained with a 49Ω resistance. Testing at system level is usually done using an IEC 61000-4-2 generator (ESD gun). However, the interpretation of gun, generated complex waveforms, is not straightforward. Moreover, guns can generate perturbations that disturb the measurement [START_REF] Honda | Measurement of ESD-gun radiated fields[END_REF] and the reproducibility of the pulse is very poor [START_REF] Lin | Metrology and methodology of system level ESD testing[END_REF]- [START_REF] Wang | Characterization of human metal ESD reference discharge event and correlation of generator parameters to failure levels-Part II: Correlation of generator parameters to failure levels[END_REF]. Instead, we used a transmission line pulse (TLP) generator. The TLP setup, shown in the test bench of Fig. 3(b), uses a 1-ns rise time and 100-ns width rectangular pulse. The analysis of the measurement resulting from this TLP waveform allows understanding the impact of each component on the ESD system current propagation. The analysis of the current waveform shape, obtained with the one-ohm measurement, is performed with the help of the simulation.

III. MODELING METHODOLOGY

This section presents the modeling of each system part. To keep a behavioral approach, VHDL-AMS is selected as the description language. The description of the system is split into three blocks: the IC, the PCB, and the external test bench. Parts A, B, and C detail each of these blocks and how to interconnect them.

A. Circuit Modeling Methodology

The integrated circuit model is composed of three parts: the package, the ESD protection structures, and the IC core. The interaction between the ESD protections and the core are not taken into account in this study. The core functionality can be described in VHDL. A previous paper has already presented the ESD susceptibility of the core [START_REF] Lacrampe | Characterization and modelingmethodology for IC'sESDsusceptibility at system level using VF-TLP tester[END_REF].

1) Integrated Circuit Model From IBIS File:

The circuit modeling is based on standardized models called Input Output Buffer Information Specification (IBIS) and also known as ANSI/EIA-656 [START_REF]Input output buffer information specification[END_REF]. This standard allows reproducing the electrical behavioral of input/output buffers of digital circuits in order to predict signal integrity (SI) at system level [START_REF] Cuny | SPICE and IBIS modeling kits the basis for signal integrity analyses[END_REF]- [START_REF] Shen | PCB level SI simulation based on IBIS model for high-speed FPGA system[END_REF]. IBIS models, provided to designers, are a file that contains information for each pin of an integrated circuit. This file format is ASCII text. It contains I (V ) IC buffers and ESD clamps tables, V (t ) tables for the dynamic output buffers, passive elements of the package pins, input and output equivalent capacitances (Ccomp ), and others. The schematics of Fig. 4 report a typical IBIS model for (a) input pins and (b) output pins. All data included in IBIS file are obtained from measurements and/or from SPICE simulations in precise configurations defined by the standard depending on the application of the final product. One of the main advantages is that it does not reveal any information about architectural or process, which can compromise the intellectual property of semiconductor manufacturers. Although IBIS files are very useful for SI simulations, there is no information about ESD protection and, so, is still incomplete for system level ESD simulation. The I (V) characteristic of ESD clamps (between inputs and output to ground or VDD (see Fig. 4) is only given for -1 x VDD to 2

x VDD which is not sufficient to cover the full ESD protection responses. Moreover, the ESD current paths are not all considered-for example, the IBIS file does not include the power supply protection between VDD and VSS pins, or the protections between the various power supplies. It means that IBIS is not able to reproduce all the current paths that can occur during an ESD event. For all these reasons, IBIS model extension is required to fulfill high current level ESD simulation for all possible ESD paths. In the IC model proposed by us, ESD protections are replaced by other models described in the next two sections. Moreover, the IC model should take into account the parasitics of the IC to ensure that the dynamic aspects of the ESD impact will be reproduced by simulation. This is performed by reusing the values of passive elements of the packages pins and input/output on-chip equivalent capacitances given by IBIS models as shown in Fig. 5. Finally, the I/O buffer models are kept so that the simulation works even if the IC is powered up or not, in order to reproduce failures into normal operating conditions.

2) Extract Information About ESD Protection:

The IC used to validate our ESD modeling approach is a commercial integrated inverter. From the system designer's point of view, no information about its internal structure is available. The manufacturer provides only the data sheet (functionality and electrical characteristics) and IBIS model, but no information that could help for ESD simulation [see Fig. 6(a)]. To extract information from the ESD protections of the circuit, static, and quasi-static (TLP) measurements are performed. An experimented engineer aware of state-of-the-art integrated ESD protection can, however, quite easily identify the type of protection devices associated with each pin [START_REF] Voldman | The state of the art of electrostatic discharge protection: Physics, technology, circuits, design, simulation, and scaling[END_REF], [START_REF] Semenov | ESD Protection Device and Circuit Design for Advanced CMOS Technologies[END_REF]. From the simple circuit studied here, three types of devices were identified: several diodes, an RC triggered power clamp (PC) and an SCR, with a dedicated strategy protection as shown in Fig. 6(b). The next section will describe how to build the ESD models from TLP and static measurements.

3) Modeling of ESD Protection Based Only on Measurements:

Models of IC-internal protections need to be simple enough to allowfast calculation and good convergence. Acoarse behavioral model can easily introduce many discontinuities either on the signal or its derivatives and then induce serious convergence issues. Here, our basic idea consists in using equations known to represent correctly the device behavior and known to offer good simulation convergence. As will be shown, these physically based equations are simplified as much as possible to reach a minimum set of parameters. Strictly speaking, these model parameters are not physical anymore. The proposed model type is thus somewhere in between physical and behavioral.We only consider the quasi-static protection devices behavior. Notice that most ESD protection dynamic effects are already taken into account by the input/output equivalent capacitances provided in the circuit IBIS file. The diode model is built upon the very classical diode current equation including a serial resistance:

(1) with Ut being the thermodynamic voltage.

The diode model has three parameters: is , Nf , and Ron that are, respectively, the reverse-bias saturation current, nonideality coefficient, and serial resistance of the diode. id is the current through the diode and v d is the voltage across the diode. Equation ( 1) is directly implemented into the VHDL-AMS as this type of language allows the use of implicit equation, which often eases the modeling work. To build the model, each diode parameters are extracted by fitting the measurement data.

The RC triggered clamp model is based on the schematic proposed in Fig. 7. Three parameters allow defining the power clamp model: the serial resistance Ron , R, and C ,which together are the triggering elements that control the gate of an NMOS transistor. For the MOS transistor, we use classical level-one MOS equations composed of three regions: no current below the threshold voltage (2), a linear region (3), and a saturation region [START_REF]Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components[END_REF]. We also have to define an additional "Size" parameter that actually corresponds to the transconductance and W/L product 1) When Vgs ≤ Vt where M is the avalanche multiplication factor of the junction collector/base of NPN, given by the Miller expression [START_REF] Miller | Ionization rates for holes and electrons in silicon[END_REF]:

with VCB being the voltage across the junction collector base, VBV being the breakdown voltage, and 2 < m < 6 being an arbitrary factor depending on junction characteristics. When the voltage VCB reaches the breakdown voltage value VBV, the iav source provides the necessary current to trigger and hold the SCR. Modeling the avalanche source from ( 6) and ( 7) is critical regarding convergence issues. Indeed, the multiplication factor expressions suffer from a sudden change of sign near the breakdown. In order to avoid the change of sign, the Miller expression is derived from the Taylor series:

with Nb , the number of terms. This development corresponds to a geometric sequence and thus This last expression is used as the multiplication factor M in the model [START_REF]Road Vehicles-Test Methods for Electrical Disturbances From Electrostatic Discharge[END_REF]. The parameter Nb is the number of terms of the mathematical series. It can be adjusted to high value for better accuracy. A lower value reduces the accuracy but leads to a smoother variation that helps convergence. We found Nb = 100 as a good compromise. Note that this expression of M is not defined for a voltage exactly equal to the breakdown voltage. However, the expression is continuous around this point, and its value can be calculated at this point. We finally obtain a five-parameter model with Beta (βp /βn ) being the bipolar transistor current gain, isat and Nf being the diodes nonideality coefficient and saturation current, respectively, VBV being the breakdown voltage, and Ron being the serial resistance of the SCR. Diodes RC triggered PC and SCR protection models are combined with the previously described IBIS elements to model the whole ESD circuit. Fig. 9 shows the simplified schematic of the IC model obtained by this methodology. The conduction of the PC is modeled by a diode for its reverse-biased operation.

4) Model Verification and Discussion:

The validity of the model is checked on the discharge paths that involve more than one protection element. In all cases, we observed a discrepancy lower than 20%. The largest discrepancy results are shown in Fig. 10 for a stress injected between Out and VSS pins.

B. Print Circuit Board Modeling Methodology

Two kinds of generic PCB line models have been developed to take into account propagation effect and crosstalk phenomena. The simple line, modeling the propagation, consists in the distribution of an elementary length of a transmission line. Generally, the elementary transmission line elements are modeled with four parasitics elements [START_REF] Wadell | Transmission Line Design Handbook[END_REF] as shown in Fig. 11(a): R (serial resistance in ohms), L (serial inductance in Henry), C (parallel capacitance in farads), and G (parallel conductance in Siemens). According to these parameters, the expression of the line impedance can be established as follows:

In most general cases, the line impedance is complex. However, the good quality of the conductors used in PCB (copper) as well as the good quality of the substrate dielectric generally result in the "weak losses" condition that implies: R << jLω and G << jCω . The characteristic impedance is then purely real Fig. 11(b) shows the simplified elementary length where only the L and C effects are taken into account. These simplifications have been validated in a previous work done by Lacrampe [24] using a TDR-like method based on a VF-TLP tester. The line parameters depend on geometric dimensions (length L , width W , thickness t, and substrate height H ) and on the dielectric constant εr of the material used for the PCB (FR-4 epoxy for the studied case). The inductance and capacitance per unit length are computed from these parameters and equations given by Bakoglu [START_REF] Bakoglu | Circuits, Interconnections, and Packaging for VLSI[END_REF]. PCB lines are discretized in n portions by taking as an assumption the quasi-transverse electromagnetic (TEM) approximation [START_REF]Electromagnetic Compatibility (EMC), Part 4-20: Testing and Measurement Techniques-Emission and Immunity Testing in Transverse Electromagnetic (TEM) Waveguides-Basic EMC Publication[END_REF]. To carry out this serialization of the various line portions, we programmed a generic code module having as inputs the values of the capacitance and the inductance per unit length and the number of lumped elements. An example of the VHDL-AMS code is given bellow (see Fig. 12) showing the advantage of using a behavioral description. Another model has been built to take into account crosstalk phenomena between several lines. The coupling effect is modeled by inserting a mutual inductance and capacitance per unit length on elementary length as shown on Fig. 13. These elements are computed from geometry with the equations proposed by Sohn et al. [START_REF] Sohn | Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board[END_REF]. The generic model, described in VHDL-AMS, allows the prediction of the noise coupled between lines. This model has been validated for ESD in [START_REF] Lacrampe | Characterization and modelingmethodology for IC'sESDsusceptibility at system level using VF-TLP tester[END_REF]. Two generic modules have been developed to model the whole PCB: one module named "LC line" for propagation and a second module named "LC line coupled" to take into account coupling effect between several lines. The methodology of the generic model's connections is illustrated in Fig. 14. Depending on the interaction between the lines, each segment is modeled by a module, which takes into account the impedance, length, and optionally the coupling effect. In the portion III and I, there is no coupling effect between lines. So, the module "LC line," without coupling effect, is appropriate. In portion II, where lines are close, the "LC line coupled" module is used to take into account crosstalk between lines. Following the assembly methodology presented, it could be easy to extract an equivalent Hardware Description Language (HDL) from PCB layout by automatic extraction's software.

C. Full System

This section presents the modeling of case 1 discharge configuration, between output and ground plane. All the other configurations of ESD discharge stress are modeled and can then be analyzed in a similar way. The integrated circuit elements, such as package, I/O capacitances from IBIS and ESD protections modeled from measurements, are assembled with the generic blocks previously described. The methodology of PCB lines connections, described in the previous section, is applied to form the PCB block. IC and PCB block are assembled hierarchically as shown in Fig. 15. It has to be noticed that only the main PCB lines are reported on the schematic, but the whole PCB lines are modeled. The PCB block includes the line injection connected to the pin "OUT," the one-ohm measurement technique connected to the VSS pin, and the decoupling capacitance connected to the VDD pin. To model the whole system, it is necessary to consider all the external elements including generator and cables. The discharge configuration between output and ground plane takes into account the test bench as shown in Fig. 16. A pulse voltage source in series with a 50-Ω resistance is used to represent the TLP generator. Connections between the oscilloscope, the TLP generator, and the PCB board are modeled by simple transmissions lines (Tline) with 50-Ω impedance whose delay is adjusted to match with the cable delay. Current and voltage probes, represented in Fig. 16, correspond to the probe of the TLP tester. This allows measuring the injected and reflected waveforms. To summarize the methodology to build the full simulation scheme, the device model (including package protection strategy and IC core), PCB, cables, measurement test bench, and generator are clearly separated. It will be shown in the following paragraphs that simulations reveal the interactions between each of these model elements.

IV. SIMULATION OF THE WHOLE SYSTEM A. Case 1: Decoupling Capacitance Connected Between VDD and VSS

In this section, the simulation of the whole system is analyzed for various IC's decoupling capacitance values (50 nF, 14 nF, and no capacitance). The TLP pulse has the following characteristics: amplitude : 1 A; pulsewidth : 100 ns; and rise time: 1 ns. Fig. 17 shows the simulation results when the decoupling capacitance is not connected. The current I corresponds to the current that circulates through the 1-Ω resistance. VI is the internal voltage of the IC between VDD and VSS pins, across the power clamp. The whole injected current flows through the 1Ω resistance. As expected by the protection strategy of the IC, the discharge current flows through the output diode D1 and the power clamp. If a 50nF decoupling capacitance is connected between VDD pin and the ground plane, the shape of the current I through the 1Ω resistance is significantly different as shown in Fig. 18. Complex interactions between the chip, its package, the PCB lines, and the decoupling capacitance are observed. Simulations of the current I in the 1-Ω resistance and internal voltage VI across the power clamp for one ampere TLP pulse injected between output and ground were carried out to compare the two configurations: with and without 50-nF decoupling capacitance. The external decoupling capacitance defines the internal potential between VDD and VSS (VI ). Initially, there is no charge on the decoupling capacitance, voltage VI is equal to zero, and the power clamp is closed. When an ESD stress occurs on the output pin, the current goes through the diode D1. Because the capacitance is directly connected to the ground, the current path can flow either through the PC or through the capacitance. In this case, the decoupling capacitance offers a lower impedance than the power clamp, creating a preferential path for the ESD discharge current from the VDD pin to ground. The current peak observed on the resistance needs explanation. During the fast TLP rising edge, between t0 and t1 (see Fig. 18) the inductive effect of the package allows the PC to conduct some current for a very short time. This is because the package inductance is not able to drive current instantaneously respecting the basic equation V = Lpkg (di/dt). So, the voltage across the VDD package inductance increases strongly. The threshold voltage of the PC is reached allowing the conduction of the current. Fig. 19 shows the current path into the circuit during TLP rising edge. Just after the TLP rising edge at t1 + ε, the inductive effect decreases, voltage VI decreases and the power clamp switches OFF. During the following interval time, t2 to t3, all the current directly goes out of the chip and the external capacitance begins to charge up. No current circulates through the 1-Ω resistance. When the charge voltage of the capacitance reaches the triggering voltage of the PC, at t3, the PC conducts more and more current as the capacitance still charges up gradually. When the TLP pulse begins to fall, at t4 (returns to zero), a negative peak current is visible on the simulation. It can be explained by what we could call "the package inductance balance effect." Just before the TLP pulse end at t4-ε, the current circulates mainly in the package VDD inductance (about 700 mA/1-A injected) to charge the external capacitance. When the ESD-pulse currentflow stops, the current continues to circulate through the VDD package inductance forcing the PC to conduct a reverse current to fulfill the "inductance balance effect." The current path into the circuit during TLP falling edge is presented in Fig. 20. Fig. 21. Simulations of the current I in the 1-Ω ground resistance and internal voltage VI across the power clamp for 1-A TLP pulse injected from output to ground, with 14-nF decoupling capacitance.

After the TLP pulse ends at t5 + ε (returns to zero), the decoupling capacitance discharges through the PC until the RC triggering circuitry turns it OFF. It is noted that even if the external capacitance absorbs a great part of the energy stress corresponding to the white hatched area in Fig. 18, the PC must conduct within a time delay considerably longer than the stress duration to evacuate the charge accumulated inside the capacitance. Even if the current through the PC during the TLP pulse (gray on Fig. 18) is smaller than the whole current injected, the PC continues to discharge current. It implies that the decoupling capacitance increases the time required by the PC to shunt the current.

When the PC stops conducting (i.e., the sustaining voltage goes below the transistor holding voltage), the remaining charges in the capacitance are then locked and the capacitance maintains a high voltage between VDD and VSS. This could have a crucial impact on the susceptibility when the system is powered-up. Results with a 14 nF decoupling capacitance are shown in Fig. 21. The capacitance charges up more rapidly during the TLP pulse. At t3, the voltage capacitance increases more rapidly, and results in a shift of the PC triggering. The current path is the same except at t4 when the TLP pulse begins to return to zero. At t5ε, the current circulates mainly in the package VSS inductance (about 700 mA) to the 1-Ω resistance. The current that circulates through the capacitance is only 300 mA. When the ESD-pulse stops, the current continues to circulate through the VSS package inductance forcing the PC to conduct the current in a same way to fulfill the "inductance balance effect." This explains why the peak on the one-ohm measurement at t4 is not negative. Depending on the decoupling capacitance value (14 and 50 nF), the current path varies when TLP pulse end, and the PC can switch from direct to reverse mode very quickly.

B. Case 2: Capacitance Connected Between the Input and Ground Plane

The TLP generator is connected between the input and ground plane and has the following characteristics: amplitude : 2 A; pulsewidth : 100 ns; and rise time : 1 ns. The impact of an external capacitance connected in parallel with an SCR internal-IC protection is analyzed. Fig. 22 shows the simulation results when the capacitance is not connected. The current I corresponds to the current that circulates through the 1-Ω resistance. Vscr is the internal voltage of the IC across the SCR. Due to impedance discontinuities between TLP generator, 50-Ω cable and 110-Ω PCB lines, the injected current level is about 1.7 A. The whole injected current flows through the 1-Ω resistance. As expected by the protection strategy of the IC, the discharge current is sunk by the SCR in forward mode. When a 6.8-nF decoupling capacitance isconnected betweeninput pin and the ground plane, the shape of the current I is strictly different as shown in Fig. 23. The external capacitance actually defines the internal potential between the Input and VSS (Vscr = Vc2 -VR1Ω). Initially, there is no charge on the capacitance and no current circulates through the 1Ω resistance. Voltage Vscr is equal to zero and the SCR is OFF. When an ESD stress occurs on the input pin, at t = t0, the discharge current is absorbed by the capacitance, the SCR does not trigger. From t0 to t1, the ESD current charges up the decoupling capacitance. The voltage Vscr increases gradually and the capacitance charges up. When the capacitance charge voltage reaches the triggering voltage of SCR (about 13 V), at t = t1 , it turns ON and goes to snap-back state. The voltage across the SCR drops to 2 V, the holding voltage, and its on-state resistance becomes very low. The SCR then conducts the current from the generator TLP and cumulates the discharge current of the capacitance creating a very strong current peak as shown on the simulation results of Fig. 23. The voltage difference between the SCR and capacitance is balanced by the inductive effect of the input package to match with Kirchhoff's voltage law: (VC2 -Lin x di/dt -Vscr -VR1Ω = 0). Fig. 24 shows the current path into the circuit during this phase. When the TLP pulse ends, at t = t2, the ESD current flow stops that creates an abrupt change on the current simulation results. The charge voltage of capacitance is still higher than the holding voltage of the SCR. The capacitance continues to discharge through the SCR. At t = t3, as the current becomes lower than the holding current, the SCR switches OFF. This leads to a shift of the current, from about 200 mA to 0, on the current simulation result of Fig. 23. After the SCR stops, no more current circulates through the circuit. This capacitance's charge and discharge effects during an ESD stress has been highlighted by P.

Besse in [START_REF] Besse | ESD/EMC in an automotive environment[END_REF] for an automotive device and an external capacitance used as an electromagnetic interference (EMI) filter. The same effect could occur for an integrated capacitance and power clamp as shown in [START_REF] Lee | The influence of decoupling capacitor on the discharge behavior of fully silcided power-clamped device under HBM ESD event[END_REF]. This current corresponds to the conduction of the NMOS transistor of the output buffer due to the polarization of the gate-drain coupling capacitance charging up rapidly during the transition of injected TLP pulse. This current is 100 mA for 1-A stress. This was not predicted by only taking into account the protection devices in the simulation. Consequently, a more complex model for system level ESD prediction must include the pull-down transistor, which is given into the IBIS description. The gate coupling capacitance (Cgd) of the output buffers that control the current flowing through the drivers must also be included. We solved this mismatch by using a Spice level 1 MOS structure fitted from the data given in IBIS files as shown in Fig. 26. The exposed experience considered an injection of only 1 A. For higher stress level, the gate coupling effect can lead to a very high gate polarization that can drive the transistor into avalanche mode and then it can be destroyed. To estimate the ESD robustness, the breakdown voltage of the output drivers should be known to predict the failure of the device. The 1-Ω resistance allows the measurement of the current going out of the circuit through the ground pin. But, this method has to be used cautiously. For example, when we study the impact of the external decoupling capacitance, the inverter input was not connected and the current could not be discharged through this input pin. However, if the input is connected to the ground plane, new paths could be created as shown in Fig. 27. The ESD discharge current that circulates through the 1-Ω resistance increases the internal VSS potential allowing the SCR conduction in reverse mode.

B. Case 2: Capacitance Connected Between the Input and Ground Plane

The simulation results are compared with measurements and shown in Fig. 28. The simulation without capacitance matches perfectly with the measurement. With 6.8 nF capacitance, a difference of about 20% is observed between simulation and measurement. When the SRC turns ON, it conducts the current derived from the TLP generator plus the discharge of the capacitance. This observed mismatch could be attributed to several reasons: First, the TLP generator model is a perfect current source forcing the current whatever the system load. Second, the discharge time constant of the capacitance could be more complex than a perfect one. First, the model validity of TLP generator is checked. Simulations and measurements of incident and reflected current waveforms from TLP probe are performed with and without capacitance and are shown in Fig. 29. The first and last parts of the curve are, respectively, the incident and reflected current pulses. The superposition of the two waveforms (center part) corresponds to the transmitted current. Without decoupling capacitance, the polarization point of the SCR does not vary during the pulse, the transmitted current is constant. When a capacitance is connected, the impedance viewed by the TLP generator changes during the pulse due to the charge and discharge of the capacitance and the variation of SCR polarization point. It shows that the transmitted current is not constant as depicted in Fig. 29. In both cases, the current waveform simulation matches with the measurement thus indicating that the TLP generator model is not the origin of the discrepancy. The discrepancy is mainly due to the discharge constant of the capacitance. It is possible to adjust the simulation result by increasing the total resistance of the discharge branches. This has been done by inserting the equivalent high-frequency model of the capacitance on one part, and by introducing some access resistance to the SRC of 1Ω. The comparison of measurement and adjusted simulation is given in Fig. 30.

VI. CONCLUSION

In this paper, we proposed a methodology to build a complete system level ESD simulation taking into account the IC, the PCB, and the test bench. This methodology based on the principle of standalone blocks provides system level designers the possibility of simulating their electronic systems and analyzing their behavior during ESD test. Each block of the system is independent and can be reused in any other configuration. The various elements of the system: ESD generator, PCB, package, and IC have been presented and described separately.

We have demonstrated that it is possible to build IC ESD behavioral models without knowing in detail the internal IC ESD protection by using a combination of informations from IBIS files and TLP measurements. Based on existing model (IBIS) and from dedicated ESD measurements, the modeling approach of an IC has been presented. We demonstrated that IBIS model gives a lot of very useful information like buffers, on-chip capacitances, and passive elements of the package, but it has to be improved regarding the ESD strategy and high power I (V) curves to perform ESD simulations. The ESD protection models added are extracted from TLP measurements and fitted with classical diodes, SCR or MOS models. Even if our ESD protection's behavioral models introduce an error (lower than 20%), the comparison of theoretical and experimental results shows that it is possible to perform predictive simulation with good correlation to measured data. This could be explained by the fact that the 20% of mismatch on the models of the protections only introduces a small variation on the equivalent resistance. For a fixed current, it results in a small variation of the voltage across the protection device, and due to the number of elements in the current path, the cumulative impedance is higher than the one of the protections. To summarize, the simulation and measurement results, for the simple case considered here, show that even when using these simple semiempirical models to perform the simulation, complex interactions can be identified which involve the IC ESD protection network and the other components of the system like the IC external decoupling capacitance. This paper shows that it is necessary to identify relevant system level and component circuit parameters to be able to simulate the ESD behavior at the system level. Apossible solution to allowfast system level ESD verification and simulation would be is to add improved ESD protection network description and parameters in conventional IBIS files. In addition, other parameters such as the amount of energy supported by IC internal ESD protection elements can give an estimate of the ESD robustness at system level. Future work will focus on the robustness and susceptibility investigations and how to implement it at simulation level.

Fig. 1 .

 1 Fig. 1. Schematic representation to build system level generic block's simulation.

Fig. 3 .

 3 Fig. 3. (a) Picture of the test board. The IC is soldered on the bottom layer of the PCB. (b) Picture of the test setup.

Fig. 4 .

 4 Fig. 4. Typical schematic of IBIS model of (a) input and (b) output.

Fig. 5 .

 5 Fig. 5. Typical schematic of model IBIS without the output buffer.

Fig. 6 .

 6 Fig. 6. (a) Typical ESD protection network. (b) Identified protection elements after TLP measurement.

Fig. 7 .

 7 Fig. 7. Power clamp model.

2 )

 2 Fig. 8. SCR model, forward bias diode model are not represented.The RC triggering element's values and the MOS size is adjusted by fitting both the TLP I (V ) curve and the transient behavior of the device during TLP pulses. The reverse operation, which involves the drain-substrate diode, is modeled by a diode connected in parallel using the previously described diode model. SCR reverse-operation model is based upon the most simple bipolar transistor transport model (simplified Gummel and Poon[START_REF] Gummel | An integral charge control model of bipolar transistors[END_REF]) as represented in Fig.8. The current if is thus represented by a simple diode-like exponential as follows:

Fig. 9 .

 9 Fig. 9. Simplified ESD integrated circuit model.

Fig. 10 .

 10 Fig. 10. TLP measurements and simulations of the power clamp (VDD to VSS ) and of Out to VSS stress that combines two protection elements (diode + PC).

Fig. 11 .

 11 Fig. 11. (a) Elementary length transmission lines and (b) simplification for ESD propagation into PCB.

Fig. 12 .

 12 Fig. 12. VHDL-AMS code to model PCB line using LC module.

Fig. 13 .

 13 Fig. 13. Methodology of PCB lines connections.

Fig. 14 .

 14 Fig. 14. Methodology of PCB line connections.

Fig. 15 .

 15 Fig. 15. Simplified PCB model.

Fig. 16 .

 16 Fig. 16. Simplified system model for ESD discharge between output and ground plane.

Fig. 17 .

 17 Fig. 17. Simulations of the current I in the 1-Ω ground resistance and internal voltage VI across the power clamp for 1-A TLP pulse injected from output to ground, without IC decoupling capacitance.

Fig. 18 .

 18 Fig. 18. Simulations of the current I in the 1-Ω ground resistance and internal voltage VI across the power clamp for 1-A TLP pulse injected from output to ground, without IC decoupling capacitance.

Fig. 19 .

 19 Fig. 19. Simplified schematic showing the ESD current path into the circuit over fast TLP rising edge with 50-nF decoupling capacitance at t0 + ε.

Fig. 20 .

 20 Fig. 20. Simplified schematic showing the ESD current path into the circuit on fast TLP falling edge, with 50-nF decoupling capacitance at t4 .

Fig. 22 .

 22 Fig. 22. Simulations of the current I in the 1-Ω ground resistance and internal voltage Vscr across the SCR for 1-A TLP pulse injected from input to ground, without capacitance.

Fig. 23 .

 23 Fig.[START_REF] Wadell | Transmission Line Design Handbook[END_REF]. Simulations of the current I in the 1-Ω resistance and internal voltage Vscr across the SCR for 2-A TLP pulse injected between input and ground plane, comparison with and without 6.8-nF capacitance.

Fig. 24 .

 24 Fig. 24. Simplified schematic showing the ESD current path into the circuit from t1 to t2 , when the SCR deviate the TLP current and current capacitance.

Fig. 25 .

 25 Fig. 25. Measurements and simulations of the current in the 1-Ω ground resistance for 1-A TLP pulse injected from output to ground, with 14 nF, 50 nF, and without IC decoupling capacitance.V. COMPARISON BETWEEN MEASUREMENT AND SIMULATION A. Case 1: Decoupling Capacitance Connected Between VDD and VSSThe simulation results and measurements comparison are shown in Fig.25. For various decoupling capacitance values (50 nF, 14 nF, no capacitance) the simulations perfectly match with the 1-Ω resistance measurements. As can be noticed, from t2 to t3, a small current circulates through the 1Ω resistance.

Fig. 26 .

 26 Fig. 26. Connection of the pulldown output transistor to take into account the gate coupling effect.

Fig. 27 .

 27 Fig. 27. New path created by the one-ohm measurement technique when the input is connected to the ground.

Fig. 28 .

 28 Fig. 28. Measurements and simulations of the current in the 1-Ω ground resistance for 2-A TLP pulse injected from input to ground, with 6.8 nF and without capacitance.

Fig. 29 .

 29 Fig. 29. Measurements and simulations of the current in the 1-Ω ground resistance for 2-A TLP pulse injected from input to ground, with 6.8 nF and without capacitance.

Fig. 30 .

 30 Fig. 30. Measurements and optimized simulations of the current in the 1-Ω ground resistance for 2-A TLP pulse injected from input to ground, with 6.8 nF and without capacitance.

level modeling methodology is presented and validated on a simple case. It allows precise simulations of electrostatic discharge (ESD) stress propagation on a printed circuit board (PCB). The proposed model includes the integrated circuit (IC) ESD protection network, IC package, PCB lines, passives components, and externals elements. The impact of an external component on the ESD propagation paths into an IC is demonstrated. Resulting current and voltage waveforms are analyzed to highlight the interactions between all the elements of an operating PCB. A precise measurement technique was designed and used to compare with the simulation results. The model proposed in this paper is able to predict, with good accuracy, the propagation of currents and voltages into the whole system during ESD stress. It might be used to understand why failures occur and how to fix them with the most suitable solution.

	A System-Level Electrostatic-Discharge-
	Protection Modeling Methodology for Time-
	Domain Analysis
	Nicolas Monnereau, Fabrice Caignet, David Trémouilles, Member, IEEE, Nicolas Nolhier, and Marise
	Bafleur
	Abstract-A system