Stéphane Rubini
email: rubini@univ-brest.fr

Christian Fotsing
email: fotsingta@univ-brest.fr

Frank Singhoff
email: singhoff@univ-brest.fr

Hai Nam Tran

Pierre Dissaux
email: pierre.dissaux@ellidiss.com

Scheduling Analysis from Architectural Models of Embedded Multi-Processor Systems

Keywords: C.3 [Special-Purpose and Application-Based Systems]: Real-time and embedded systems; D.2.4 [Software Engineering]: Software/Program Verification-validation Performance, Reliability, Verification Real-Time Embedded System, Real-Time Scheduling, Multi-Processor, Model-Driven Engineering, AADL

As embedded systems need more and more computing power, many products require hardware platforms based on multiple processors. In case of real-time constrained systems, the use of scheduling analysis tools is mandatory to validate the design choices, and to better use the processing capacity of the system.

To this end, this paper presents the extension of the scheduling analysis tool Cheddar to deal with multi-processor scheduling. In a Model Driven Engineering approach, useful information about the scheduling of the application is extracted from a model expressed with an architectural language called AADL. We also define how the AADL model must be written to express the standard policies for the multi-processor scheduling.

INTRODUCTION

During several decades and until recently, the processing power supplied by sequential processors has grown more and more quickly. The reason of this trend is the improvement in microelectronic technologies, and the internal parallelism of execution through architectural schemes like single or multiple pipelines, out of order instruction issues or speculative executions. The programming model remains the sequential one, but the processors use complex strategies to au-tomatically extract the Instruction Level Parallelism (ILP) available inside the instruction flow.

However, integrated circuit technology and ILP exploitation have reached a state where potential improvements seem to be limited too. Since few years, the answer to that situation is to increase the computing power through the parallel execution of several execution flows. Multi-task applications or systems contain Thread Level Parallelism (TLP) and thus, are naturally adapted to such an execution platform. Parallel multi-processing is today the main way to obtain more powerful computing machines.

In the context of embedded systems, multiple processors may be found even within small embedded systems (for instance in smart phones [START_REF] Van Berkel | Multi-core for mobile phones[END_REF]). Since a long time, complex embedded systems, like avionic or automotive ones, rely on a large set of processors to achieve their computation needs; but they belong rather to the class of the distributed systems, with loosely coupled processing units. The availability of processors or Systems on Chip (SoC) which integrate several tightly coupled processing cores changes this view, and shifts the programming paradigm towards the shared memory multi-processing.

Beyond the speed-up expected from the parallel computing, multi-processor systems are known to have a better energy efficiency (trade-off performances-power). Pollask's rule states that the performances increase is proportional to square root of the increase of complexity [START_REF] Borkar | Thousand core chips: a technology perspective[END_REF]. Duplicating a core should give better performance than developing a twice more complex core. So, considering multi-processing is now a key feature of the hardware platforms intended to implement high performance embedded systems, the software engineering process must deal with parallel computing resources. We focus our study on applications where the software is described by a set of periodic tasks, and a scheduler is in charge of sequencing the task releases on the system's processors according to extra-functional timing requirements (i.e. real-time systems). The scheduling analysis theory [START_REF] Liu | Scheduling algorithms for multiprogramming in a hard real-time environnment[END_REF], and its extension to the multi-processors, are theoretical frameworks that may help the designers to validate their applications.

Another characteristic of embedded systems is that they usually perform specific functions, and so, engineers can optimize them by using dedicated software and hardware.

Hence, as a lot of designs are specific, there is a need for modeling languages which encompass both the software and hardware architecture of the system. Obviously, the models include information about the available processing units.

In this context, the article investigates the ability of the architectural language AADL to model different multi-processor architectures, and to express significant information for controlling a multi-processor scheduling analysis tool, called Cheddar.

The article is structured as follows. The section 2 presents foundation of real-time scheduling analysis on multi-processor systems, and how the Cheddar tool has been adapted to support such kind of analysis. The section 3 defines the architecture of the parallel execution platforms that we consider for the scheduling analysis. The section 4 binds this analysis to a model driven development process. In the last part, after the presentation of related works, we conclude and give some perspectives.

MULTI-PROCESSOR SCHEDULING ANALYSIS WITH THE CHEDDAR TOOL

We consider real-time applications which are modeled by a set of periodic tasks. For schedulability analysis, each task Ti is usually defined by four temporal parameters [START_REF] Liu | Scheduling algorithms for multiprogramming in a hard real-time environnment[END_REF]: its first release time ri, its Worst Case Execution Time (WCET) Ci which is the highest computation time of the task, its relative deadline Di which is the maximum acceptable delay between the release and the completion of any instance of the task, and its period Pi which is the fixed delay between two successive task release time. A task consists of an infinite set of instances (or jobs) released at times ri + k * Pi, where k ∈ N.

From this task model, the community has proposed various ways to assess the schedulability of a real-time application. Each schedulability analysis assumes a scheduling algorithm which decides at each time the jobs that have to be run on the processors. In the sequel, we first give an outline of realtime multiprocessor scheduling algorithms. Then, we show how we have implemented them in the Cheddar tool.

Multi-processor scheduling

Multi-processor scheduling is used to support multi-programming (large number of independent jobs), or to support parallel programming (dependent jobs with multiple exchanges). Given a set of jobs and a set of processors one of the question a multi-processor scheduling algorithm has to answer is how jobs can be assigned to processors [START_REF] Carpenter | A categorization of real-time multiprocessor scheduling problems and algorithms[END_REF].

We distinguish two classes of multi-processor scheduling:

• Global scheduling [3][9]. In this approach, any instance of any task may be executed on any processor. A job may halt its execution on one processor and resume it on a different processor.

Consequently, this approach assumes an execution environments which allow task migrations. Classically, a task can migrate at any time, or migration can be limited to job activation (e.g. when a task job is started on a given processor, it is supposed to complete on the same processor).

This class of scheduling algorithms suffers from high run-time overhead as the number of pre-emptions and migrations can increase significantly.

• Partitioned scheduling. With partitioned scheduling, each task can only be executed on a dedicated processor and task migrations are not allowed.

A significant advantage of partitioned scheduling is that it is well-understood since schedulability analysis can be verified with uniprocessor schedulability analysis methods. Then, classical scheduling such as EDF, RM [START_REF] Liu | Scheduling algorithms for multiprogramming in a hard real-time environnment[END_REF] can be reused.

But, finding an optimal assignment of tasks to processors is equivalent to a bin-packing problem, which is known to be NP-hard [START_REF] Leung | On the complexity of fixed-priority scheduling of periodic, real-time tasks[END_REF]. However, many polynomialtime heuristics have been proposed for solving this problem [START_REF] Coffman | Bin packing approximation algorithms: Combinational analysis[END_REF] (First Fit, Best Fit, . . . ).

Each of these approaches described above have been extended in various studies.

Cheddar and multi-processor scheduling support

Cheddar is a schedulability tool that implements classical schedulability methods for uniprocessor systems [START_REF] Singhoff | Cheddar: a Flexible Real-Time Scheduling Framework[END_REF]. To support scheduling analysis of multi-processor architectures, we have extended Cheddar with both partitioned and global scheduling features.

As a partitioned system can be analyzed as a set of uniprocessor subsystems, most of the Cheddar features can be used to assess schedulability of these system. Cheddar uniprocessor analysis features only have been extended with some simple bin-packing algorithms in order to define processor's tasks. The currently supported bin-packing algorithms are RM Next Fit, First Fit, Best Fit, Small tasks and General Tasks [START_REF] Burchard | Assigning real-time tasks to homogeneous multiprocessor systems[END_REF].

For scheduling analysis with global scheduling, Cheddar offers less features. For this class of multiprocessor architectures, Cheddar only offers scheduling analysis by scheduling simulation. The current Cheddar implementation proposes a global scheduling algorithm for each uniprocessor algorithm (e.g. global DM/EDF/RM/LLF/...).

MULTI-PROCESSING IMPLEMENTATION

In this section, we describe different implementations of the concept of multi-processing. These implementations differ by the resources in the architecture which are shared when executing the instruction flows. The figure 1 illustrates the major, although not mutually exclusive, solutions: multiprocessors, multi-cores and multi-threading.

Historically, multi-processor architectures have been the first solution. The processors are located on different integrated circuits, and share the memory. Memory and bus contention is a major concern in this kind of architecture, and the offchip implementation of the buses limits the field of implementations that could be used to deal with this problem. The off-chip buses are also known to consume a significant part of overall power budget [START_REF] Basu | Power protocol: reducing power dissipation on off-chip data buses[END_REF].

Today's multi-core processors are only integrated implementations of multi-processor systems. But, the technical constraints are not the same, and more efficient solutions may be developed to interconnect the cores and the memory hierarchy inside a chip. Multiplexed bus, crossbar switches or Network-On-Chip are examples of interconnect architectures that allow parallel transactions between cores, memories, or I/O devices.

Multi-threading strategies have been introduced to increase the usage efficiency of processing units inside the pipeline of the super-scalar processors. When the ILP is too limited and/or the execution flows are stalled, waiting for the end of memory requests, processing units are available for executing instructions issued from another threads.

However, the concept of multi-threading inherently leads to the sharing of the processing units of a core/processor. In the general case, the starting up of an additional thread impacts the performances of the other threads running on the same processor. This implicit interference between threads 1 is very difficult to quantify, because it depends on the set of instructions, coming from the candidate threads, that can be issued at a given time towards the processor pipelines.

The next section describes how the model of a system can take such architectures into consideration, and its exploitation to drive a multi-processor scheduling analysis.

SCHEDULING ANALYSIS FROM AADL MODELS

The figure 2 shows the tool chain which drives the scheduling analysis.

OSATE, Stood or ADELE are textual and graphical model editors for AADL. AADLInspector 2 is a model processing 1 The same problem exists when threads share other resources like memory buses for instance. 2 AADLInspector and Stood are products of Ellidiss Tech- In this section, after a short presentation of the AADL language, we discuss the deployment schemes for different multiprocessor scheduling strategies. Next, the AADL model of a system, and a scheduling analysis is shown as an example.

AADL

The Architecture Analysis & Design Language (AADL) is a SAE standard (AS-5506), first published in 2004 [START_REF] Feiler | The SAE AADL standard: A basis for model-based architecture-driven embedded systems engineering[END_REF]. AADL is a modeling language for description and analysis of system architecture in terms of components and their interactions.

It allows the modeling of software and execution platform components. The deployment of a software application on an execution platform is specified through binding properties.

An AADL component is defined by a declaration and implementations. Each component relies on a category. Categories of components are related to software entities, like process, thread or data, and hardware entities like processor, memory, bus or device. Each component may have several attributes called properties. The AADL standard includes a large set of pre-declared properties to model system characteristics. Moreover, new properties can be defined to precisely describe the expected system.

Modeling and Assignment of computing units

As noticed before, AADL represents the deployment of an application by binding properties, and hence associates software entities to execution resources. For instance, the following property assigns the execution of a thread ta, belonging to the process as1, to a processor p1.

A c t u a l P r o c e s s o r B i n d i n g=>( r e f e r e n c e ( p1 ) ) applies to a s 1 . ta ;

Now, we will explain how this binding mechanism may be used in the multi-processing context.

Partitioned scheduling. To deal with partitioned scheduling, a list of software threads may be assigned to their targeted processors by duplicating the processor bindings for all of them. As AADL defines a processor as an executing nologies (www.ellidiss.com) 3 Marzhin, a multi-agent based simulator, is a product of Virtualys and Ellidiss Technologies. 4 Cheddar may be downloaded from http://beru. univ-brest.fr/~singhoff platform including a scheduler that manages the sharing of its computing resources, the system is modeled as a set of nodes with their associated local scheduling policy . Nodes can be connected by a bus component.

We expect that one AADL processor should be associated to one processing unit, i.e. hardware executing one instruction flow, regardless whether this processing unit constitutes a core of a processor, or a processor as a whole (we postpone the case of multi-threading later in this section); hence, an AADL processor includes the private resources dedicated to an instruction flow, mainly the execution pipelines and the private cache memories (cf figure 1). Such a modeling guideline aims to exclude of the "processor" all the shared resources between them, in order to define independent subsystems when they do not need to interact through external resources. Shared resources are often a bottleneck in multiprocessors or multi-cores and the models should highlight them.

Global scheduling. A global scheduler maintains a system wide queue of ready tasks and considers a set of processors to execute them. An AADL processor deals with a single hardware execution flow at a given time, and cannot be used to model a set of processors. A first approach is to group the target processors into a system component, and to bind the threads to this multi-processing system (smp in the example below). An AADL processor includes a scheduler, of which the type is specified by the standard property Scheduling_Protocol.

In the case of global scheduling, the value of this property must be the same for all the processors. To remove this consistency rule, the AADL standard could be adapted to associate a global scheduling method to all the processing units available within a system component.

Multi-threading. Multi-threaded processors or cores allow the parallel execution of few tasks. The AADL hardware model should represent each physical thread by a processor component.

A pessimistic performance scaling factor may be defined, according to the maximal number of physical threads per core, in order to take into account the performance provided by a physical thread in relation with the mono-thread core performance. The AADL standard property Scaling_Factor and Reference_Processor allow to specify the scaling factor with respect to a reference processor, and can be used in that goal. Now, we will illustrate this guideline by modeling a simple image processing application on a multi-core execution platform.

Example

We have chosen the LEON4 DEMO ASIC of AEROFLEX Gaisler [START_REF] Gaisler | Dual core LEON4 SPARC V8 Processor LEON4-ASIC-DEMO, Data Sheet and User's Manual[END_REF] as a target platform for our case study. The key features of this Multi-Processor SoC (MPSoC) are:

• Dual LEON4 cores at 200 MHz with symmetric multi-processing support. An instruction cache and a data cache are associated to each core. The LEON4 core does not provide multi-threading capabilities.

• Many on-chip devices and IO connections: USB-2.0 host/device, SVGA, Ethernet, PCI, I2C, CAN, . . . Bus utilization is a major concern in the design of a SoC; bus bandwidth and device communication requirements must be balanced. So, the organization of the AADL model follows the bus architecture of the SoC.

The next listing describes, with the AADL textual syntax, the simplified model of the subsystem connected by the processor memory bus. The component implementation Core.Leon4 is not detailed here; mainly it defines some processor properties, and characteristics of its private cache level. In association with the hardware model, AADL allows us to specify the software architecture. In our example, we consider a simple image processing process; figure 4 outlines the processing steps, implemented by three periodic tasks. The AADL standard supplies a set of properties to qualify the behavior of real-time tasks. These properties give the information to define the parameters of the task model presented in the beginning of section 2. Finally, the root of the model hierarchy brings together the hardware and the software view of the embedded system in a system component. The deployment properties complete the model and bind the software entities to components of the execution platform.

The binding properties below define that the three threads of our application may be executed on the two cores of the SoC. We implement a global scheduling multi-processor strategy here.

RELATED WORKS

Other works focus on the integration of a scheduling analysis in a MDE approach. They differ from our proposition by the expressiveness of the ADL and the analysis method that has been chosen.

UML/Modeling and Analysis of Real-Time and Embedded System (MARTE) profile currently supports mono and multiprocessor scheduling algorithms, but only for a partitioned approach. [START_REF] Magdich | A MARTE extension for global scheduling analysis of multiprocessor systems[END_REF] has proposed various updates for MARTE metamodels of specialization and generalization stereotype in order to support global scheduling approaches, allowing task migrations. Those changes allow a schedulable resource to be executed on different computing resources in the same period.

The work in [START_REF] Anssi | Completing EAST-ADL2 with MARTE for enabling scheduling analysis for automotive applications[END_REF] describes an approach to combine MARTE and EAST-ADL2 to overcome EAST-ADL2 limitation of notions for modeling the timing features. EAST-ADL2 is an architecture description language defined as a domain specific language for the development of automotive electronic systems. The MAST toolset is integrated in the MDE process to perform the scheduling analysis.

An approach to extend the AADL standard properties to support the modeling and specification of embedded multicore system was also proposed in [START_REF] Deubzer | Modeling and simulation of embedded real-time multicore systems[END_REF]. Analysis is performed with a Monte-Carlo and scheduling simulation mixed approach.

In [START_REF] Brekling | MoVES-a framework for modelling and verifying embedded systems[END_REF], a verification framework for schedulability of multicore systems, called MoVES, is described. MoVES provides a simple specification language to define a system. It can model software components and execution platform; however, the architecture seems to be restricted to only one processor bus. The analysis method is based on timed automata.

CONCLUSION

This article has shown how scheduling analysis may be handled in a MDE process. The AADL language provides the means to express the basic information required to control a multi-processor scheduling tool. The availability of multiples processing units extend the design space and engineers need help at the early stages of the design to check their choice about their assignment to the tasks.

For our future work, we plan an extension of the Cheddar simulation framework to consider uniform processors, i.e. processors with equal capabilities but different speeds. Especially, this feature will help to integrate some of the effects related to the multi-threaded processors in the results.

After that, a key point in the multi-processor analysis is to consider the sharing of resources, like buses or shared caches, which introduces implicit inter-processor dependencies. Extensions of the Cheddar tool to deal with some of these aspects will be useful, and once again precise architectural models of the computing and memory resources [START_REF] Rubini | Modeling and verification of memory architectures with AADL and REAL[END_REF] will be required.

Figure 1 :

 1 Figure1: Architectural localization of the multiprocessing capabilities. The ability of executing multiple threads may be provided at different levels: by the coupling of processor chips, inside a "processor" chip or inside the data-path.

Figure 2 :

 2 Figure 2: Analysis tool chain

A c t u

  a l P r o c e s s o r B i n d i n g=>( r e f e r e n c e ( smp ) ) applies to a s 1 . ta ; An alternative binding method enumerates explicitly the set of processors involved in the scheduling. A c t u a l P r o c e s s o r B i n d i n g=> ( r e f e r e n c e ( smp . p1 ) , r e f e r e n c e ( smp . p2 ) ) applies to a s 1 . ta ;

Figure 3

 3 Figure 3 shows the general architecture of the SoC, structured around three types of buses: (1) the processor memory bus, a 64-bit multiplexed synchronous AMBA AHB at 200 MHz, (2) the 32-bit AHB Fast I/O bus at 100 MHz, and (3) two 32-bit low latency asynchronous APB I/O buses.

Figure 3 :

 3 Figure 3: Simplified architecture of the SoC, modeled with the AADL graphical notation. Rounded rectangles and "double" rectangles represent respectively subsystems and devices.

system

  Proc Bus System features Proc Bus : p r o v i d e s bus access ; Mem Bus0 : p r o v i d e s bus access ; --bank 0 Mem Bus1 : p r o v i d e s bus access ; --bank 1 VGA : p r o v i d e s bus access ; end p r o c b u s s y s t e m ; system implementation Proc Bus System . SoC Leon4 subcomponents Core1 : processor Core . Leon4 { S c h e d u l i n g P r o t o c o l =>H i g h e s t P r i o r i t y F i r s t ; } Core2 : processor Core . Leon4 { S c h e d u l i n g P r o t o c o l =>H i g h e s t P r i o r i t y F i r s t ; } ; FSB : bus Communication Bus .AHB; DDR2 Ctrl : device Mem Ctrl .DDR2; Fb : device F r a m e b u f f e r .VGA; connections bus access FSB <-> Core1 . Proc Bus ; bus access FSB <-> Core2 . Proc Bus ; bus access FSB <-> Proc Bus ; . . . end Proc Bus System . SoC Leon4 ;

Figure 4 :

 4 Figure 4: Software architecture. Rectangles and dashed parallelograms represent respectively shared data and execution threads. Threads communicate through data ports, which define data dependencies.

  process E d g e D e t e c t i o n end E d g e D e t e c t i o n ; process implementation E d g e D e c t e c t i o n . impl subcomponents G e t L i n e : thread IO { D i s p a t c h P r o t o c o l => P e r i o d i c ; P e r i o d => 20 us ; Compute Execution Time => 2 us . . 4 us ; D e a d l i n e => 20 us ; P r i o r i t y => 1 0 ; } ; Sharp : . . . end E d g e D e c t e c t i o n . impl ;

  A c t u a l P r o c e s s o r B i n d i n g => ( r e f e r e n c e ( Hard . Proc Bus System ) ) applies to S o f t . G e t L i n e ; A c t u a l P r o c e s s o r B i n d i n g => ( r e f e r e n c e ( Hard . Proc Bus System ) ) applies to S o f t . Sharp ; --or w i t h an e x p l i c i t l i s t o f p r o c e s s o r s A c t u a l P r o c e s s o r B i n d i n g => ( r e f e r e n c e ( Hard . Proc Bus System . Core1 ) , r e f e r e n c e ( Hard . Proc Bus System . Core2 ) ) applies to S o f t . Edge ; The Gantt diagram shown in figure 5 is the partial result of a simulation performed by the Cheddar tool. Information provided by the AADL model (component hierarchy, property values, and the deployment bindings) are transformed into Cheddar's Architecture Description Language (ADL). The three time-lines represent the instants when tasks are released.

Figure 5 :

 5 Figure 5: Result of a Cheddar simulation. The Cheddar ADL groups in a "Cpu" the set of processing units managed by a global scheduling algorithm.

ACKNOWLEDGMENTS

This work is done in the context of the SMART project, in collaboration with Ellidiss Technologies and Virtualys. SMART is supported by the Conseil Régional de Bretagne and OSEO. Cheddar is supported by the Conseil Régional de Bretagne and Ellidiss Technologies.


Julien Sarrazin
email: julien.sarrazin@telecom-paristech.fr

Anne Claire Lepage

Xavier Begaud

Circular High-Impedance Surfaces Characterization

Keywords: High-Impedance Surface (HIS), Artificial Magnetic Conductor (AMC), Electromagnetic Band-Gap (EBG) structures, metasurface, phase diagram characterization

published or not. The documents may come

I. INTRODUCTION

ince their introduction, High-Impedance Surfaces (HIS) [START_REF] Sievenpiper | High-Impedance Electromagnetic Surfaces with a Forbidden Frequency Band[END_REF] found themselves in a lot of applications. Most of them are based on two interesting properties that these metasurfaces exhibit. The first one is an Electromagnetic Band Gap (EBG) which forbids the propagation of surface waves. The second one is the in-phase reflection of incident waves, that makes the metasurface to behave like an Artificial Magnetic Conductor (AMC). These two properties have been extensively investigated in the field of microwave antennas leading to some improvements of their performances [START_REF] Yang | Electromagnetic Band Gap Structures in Antenna Engineering[END_REF]. Though the most common structure used to perform a HIS is the array of square patches arranged in a two-dimensional lattice, many different patterns have been investigated [START_REF] Foroozesh | Investigation Into the Application of Artificial Magnetic Conductors to Bandwidth Broadening, Gain Enhancement and Beam Shaping of Low Profile and Conventional Monopole Antennas[END_REF]. Most of the time, only the shape of the single element is considered, the arrangement usually being a cartesian lattice. However, few papers deal with a circular arrangement of single elements [START_REF] Llombart | Planar Circularly Symmetric EBG Structures for Reducing Surface Waves in Printed Antennas[END_REF][START_REF] Ruvio | Radial EBG cell layout for GPS patch Antennas[END_REF][START_REF] Yan | Strip-Type AMC Structure and Analysis to Its Band-Gap Characteristic[END_REF]. In [START_REF] Llombart | Planar Circularly Symmetric EBG Structures for Reducing Surface Waves in Printed Antennas[END_REF], the circular HIS presents a 1D-periodicity and is introduced as a Planar Circularly Symmetric EBG Structure (PCS-EBG). The EBG behavior of such a structure is studied and its benefit over a traditional rectangular lattice is highlighted for a printed antenna-based application. The aim being to suppress surface waves, using such geometry makes them experience the same band gap effect in all radial directions. Another antenna application is investigated in [START_REF] Ruvio | Radial EBG cell layout for GPS patch Antennas[END_REF]. The 2D-periodicity circular HIS is used for the same purpose as in [START_REF] Llombart | Planar Circularly Symmetric EBG Structures for Reducing Surface Waves in Printed Antennas[END_REF]: to suppress surface waves thanks to the EBG behavior. In addition to the higher flexibility on the antenna design over traditional cartesian configurations, it appears that circular configuration also improves the axial ratio of the circularly polarized circular patch antenna used in the study. A 1D-periodicity circular HIS is suggested in [START_REF] Yan | Strip-Type AMC Structure and Analysis to Its Band-Gap Characteristic[END_REF] to be used as an AMC for a low profile spiral antenna, but no design is given.

So it appears that circular lattices are considered to be used for HIS. However, the literature mainly focuses on the EBG behavior of such configurations whereas their AMC behavior has not been characterized. Cartesian lattice AMC's response is usually obtained with the phase diagram method [START_REF] Yang | Reflection Phase Characterizations of the EBG Ground Plane for Low Profile Wire Antenna Applications[END_REF]. A single cell is simulated and by applying appropriate periodic boundary conditions, it is possible to determine the reflected phase of such a structure. The surface exhibits an AMC behavior when the reflected phase is null on the surface plane. By applying Floquet theorem, it is even possible to characterize the reflected phase for various incident angles [START_REF] Luukkonen | Simple and Accurate Analytical Model of Planar Grids and High-Impedance Surfaces Comprising Metal Strips or Patches[END_REF]. However, when only the response for a normal incidence is desired and when the pattern does not introduce any crosscoupling between incident waves having orthogonal polarizations, the periodic boundary conditions of the unit cell can be replaced by Perfect Electric Conductor/Perfect Magnetic Conductor (PEC/PMC) conditions in order to generate a TEM wave [START_REF] Yu | Reflection Characteristic Analysis of an Artificially Synthesized Absorbing Medium[END_REF][START_REF] Zhang | Planar Artificial Magnetic Conductors and Patch Antennas[END_REF]. This unit cell characterization is well known and works well for cartesian lattices. In this paper, we propose to apply this characterization technique to circular lattices.

The circular HIS characterization is presented in section II. In section III, the influence of geometrical parameters is studied and some problems specific to the circular arrangement are discussed. The design methodology of a complete circular HIS is addressed in section IV and some useful guidelines are given. Finally, a conclusion is drawn in section V.

II. AMC CHARACTERIZATION

A circular HIS is the conformal mapping (using an exponential function) of the rectangular pattern shown in Fig. 1a into the cylindrical pattern shown in Fig. 1b. The rectangular (or square) patch is the well-known Sievenpiper pattern having or not a metallic via-hole in its center [START_REF] Sievenpiper | High-Impedance Electromagnetic Surfaces with a Forbidden Frequency Band[END_REF]. Since for normal incidence, the via-hole does not have any impact on the reflected phase, the structure in this paper will focus on patches which do not contain any vias. As it has been mentioned earlier, the AMC phase diagram for normal incidence is obtained by applying PEC and PMC boundaries on rectangular waveguide walls. For example, according to Fig. 1a, if a PEC condition is applied to the two walls lying in the yz plane and a PMC condition applied to the two walls in the xz plane, a TEM wave will be generated with an electric field oriented along x-axis (referred as E TE in Fig. 1a). If PEC

Circular High-Impedance Surfaces Characterization

Julien Sarrazin, Member, IEEE, Anne-Claire Lepage and Xavier Begaud, Member, IEEE S and PMC walls are inverted, the TEM wave will be polarized along the y-axis (E TM ). With this method, the phase diagram of the HIS can be determined for both the polarizations shown in Fig. 1a. Similarly, the reflected phase of a circular HIS can be obtained. While mapping the cartesian geometry into the cylindrical one, the x-oriented polarization (E TE ) becomes ρoriented (E radial ) and the y-oriented polarization (E TM ) becomes φ-oriented (E concentric ) as shown in Fig. 1b. To generate TEM waves with such polarizations in a cylindrical structure, the coaxial geometry is used as it can be seen in Fig. 1b. The coaxial waveguide ends on a circular HIS. Boundary conditions are applied to the inner and outer surfaces of the waveguide. To obtain a radial polarization (E radial ), PEC conditions are applied to both the surfaces whereas to obtain a concentric polarization (E concentric ), PMC conditions are applied to both the surfaces. Then the phase diagram is obtained with the same method than for cartesian HIS. Both the obtained polarizations may emulate the field radiated by a source (such as a linearly or a circularly, polarized antenna) located in the center of the circular HIS. In cartesian structures, simulating a single cell is equivalent to assume an infinite HIS along x-as well as along ydirections. However, for circular HIS, though the structure is considered to be infinite along the radial dimension (along ρaxis), it is finite along the angular dimension (along φ-axis). So while performing the mapping, a finite number of cells along φ-axis has to be chosen. Consequently, instead of a unitcell simulation, a unit-ring simulation is performed. Furthermore, for a given inner radius r inner , the number of cells will have an influence on the dimensions w p and g w (w p being the patch width taken in the middle at l p /2 and g w is the gap along the patch length l p ). Intuitively, if the patch length l p and the patch width w p remain unchanged between the cartesian and the circular structure (as well as g w and g l ), one could expect that null reflected phase frequencies are conserved for both the polarizations. However, the curvature may have an impact on those frequencies. So, we firstly propose to study this influence.

On a FR4 epoxy substrate ( r =4.4, tan =0.02, h=1.58mm), a square patch is firstly simulated with the following dimensions: w p =l p =26mm, g w =g l =1.5mm. Then, using the same dimensions, a circular structure is designed and simulated. To keep the patch width w p and the gap g w unchanged, the inner radius of the coaxial waveguide must be equal to: ,

with N the number of patches. Four different circular structures are studied, the varying parameter being the number of patches: N=6, 8, 12 and 16. The simulation has been performed with Ansoft HFSS using the methodology previously described to obtain the phase diagram. Results are shown in Fig. 2 for both the polarizations, except in the cartesian case for which only one polarization is given because the geometry is completely symmetric. The cartesian pattern shows a null reflected phase at 2.47GHz. For circular lattices, radial and concentric modes do not exhibit the same null phase frequency. The radial mode exhibits a null phase frequency greater than the cartesian one whereas the concentric mode exhibits a lower one. Both these frequencies appear to be almost equally shifted from the cartesian pattern's frequency. Differences regarding responses between cartesian and circular lattices can be explained by the curvature's effect inherent to the circular structure. Moreover, when the number of patches N increases, the response becomes similar to the cartesian one. This is due to the fact that when the number of patches increases, the radius of the HIS increases as well, according to eq. 1, thereby making the curvature's effect less strong. For N=16 patches, the radius of the circular HIS being quite large, the patches are not much bended so concentric and radial modes exhibit a null phase frequency very close to each other (2.45GHz and 2.48GHz respectively) and very close to the cartesian one too.

These results show that the curvature has an impact on the HIS response. So the characterization appears to be necessary: by simulating the circular HIS, it is possible to set the desired reflected phase response for both the polarizations. To design and to simulate the HIS in a cartesian lattice and then to map it into a circular one without any additional simulations can lead to some unexpected frequency shifts, especially when the radius of the HIS is small.

III. INFLUENCE OF THE DESIGN DIMENSIONS

The reflected phase response of a cartesian HIS depends on the size of patches and gaps [START_REF] Yang | Reflection Phase Characterizations of the EBG Ground Plane for Low Profile Wire Antenna Applications[END_REF]. While the patch length l p and the gap g l have an impact only on the TE polarization response (according to Fig. 1a), the patch width w p and the gap g w have an impact only on the TM polarization response. However, since with a circular HIS an additional parameter exists (r inner ), sizes dependencies differ slightly from the cartesian ones. Indeed, if patch and gap sizes change, the curvature of the structure changes too. It has been shown previously that the curvature of the circular lattices has an effect on the response of both the polarizations. So by changing one dimension of the patch (or one gap), one can expect that both the radial and concentric null phase frequencies will be affected, thereby making the circular HIS design trickier than the cartesian HIS one. That is why the influence of the dimensions involved in the design is now investigated.

Fig. 3 shows the influence of the patch width w p on the reflected phase for radial and concentric polarizations. The HIS has exactly the same properties than the one previously simulated with a number of patches N=6 (l p is constant and equal to 26mm). The patch width has a direct impact on the concentric mode resonance as it has on the TM mode resonance for cartesian lattices (see Fig. 1a). So changing w p achieves a significant frequency shift on the concentric mode phase response as it can be observed in Fig. 3. Like with cartesian HIS, the smaller the patch width, the greater the null phase frequency. Nevertheless, a modification of the patch width changes the radius of the HIS and so the curvature experienced by the radial mode. This explains why the radial polarization phase response is affected by slight frequency shifts as well. The influence of the patch length l p is shown in Fig. 4 (w p being constant and equal to 26mm). The patch length has a direct influence on the radial polarization resonance. So a variation of l p changes significantly the radial mode phase response as it can be observed in Fig. 4. The patch length having an impact on the HIS curvature, concentric mode phase response is also influenced but to a lesser extent. Fig. 4 -Influence of patch length l p on the reflected phase Fig. 5 shows the influence of the gap g l along the radial direction (with w p =l p =26mm and g w =1.5mm). A modification of g l largely influences the radial mode phase response. Like with cartesian HIS, the smaller the gap, the lower the null phase frequency. However, this gap being tangential to the concentric electric field, it does not have any effect on the concentric mode response. The influence of the gap g w along the angular dimension can be seen in Fig. 6 (with w p =l p =26mm and g l =1.5mm). The null reflected phase frequency of the concentric mode can be tuned by adjusting the value of g w . Like previously, the smaller the gap, the lower the null phase frequency. Since the gap g w is tangential to the radial electric field, it should not have any effect on the radial mode response and yet slight frequency shifts can be observed, especially when g w =2.5mm. This can be explained by the fact that the radius of the circular HIS depends on the gap g w and so does the patch curvature. Since the radial electric field is sensitive to the patch curvature, slight differences in the reflected phase response may be observed.

Since the size of gaps g l and g w have a significant effect on the reflected phase of only one mode, the radial and the concentric mode, respectively, null phase frequency may be adjusted independently for both the polarizations. Gaps variation appears to be convenient for designing purpose.

IV. DESIGN CONSIDERATIONS FOR A COMPLETE HIS

The aim of this section is to give some insights regarding the design of a complete circular HIS for a potential integration with an antenna. For cartesian HIS, once the characterization of a unit-cell has been performed, the pattern can be simply duplicated in order to obtain a 2D metasurface exhibiting the same response than the unit-cell. Circular HIS design is different because the unit-ring cannot be duplicated within the same way as the cartesian lattices. The inner radius of each ring is different and so is the curvature's effect previously observed. Also, the number of patches constituting each ring may be different in order to keep the same null phase frequency. So, as an example, two circular HIS rings are considered as shown in Fig. 7. The first ring, the inner one, is composed of N=6 patches and is designed alone, being characterized like in previous sections. Dimensions w p , l p , g w and g l are adjusted in such a way that the reflected phase of concentric and radial modes is null at 2.45GHz. According to Fig. 7, dimensions are the following: l p =28.3mm, w p =24.2mm, g w =2.6mm, g l =1.3mm, with the same substrate than earlier. Using eq. 1, the inner radius is found to be 10.79mm and so the outer one is 40.39mm. Results regarding the reflected phase can be observed in Fig. 8. Both the modes exhibit a null phase at approximately 2.45GHz. However, it can be observed that the +/-90° phase bandwidth of the radial mode (5.09%) is wider than the concentric one (3.69%). Fig. 7 -Two rings HIS (l p =28.3mm, w p =24.2mm, g w =2.6mm, g l =1.3mm, l p2 =26.5mm, g w2 =2.3mm, g l2 =1.5mm)

Then, the outer ring, composed of N=12 patches, is designed. The method is now slightly different. For the inner ring, the radius is determined according to the desired patch dimensions. Here, the outer ring radius is fixed by the inner one. So simulations are conducted on the outer ring alone and the dimension l p2 is adjusted in order to obtain a radial mode resonance at 2.45GHz. Then, by adjusting g w2 , the concentric mode resonance is also set to 2.45GHz. Here, the gap g l2 is chosen arbitrarily at g l2 =1.5mm and has not been used to set the radial mode response (it could have been used within the same way as the parameter l p2 ). Dimensions are found to be: l p2 =26.5mm, g w2 =2.3mm. The reflected phase of the outer ring is plotted in Fig. 8. Both the modes exhibit a null phase at 2.45GHz. Bandwidths are more similar between each other than those of the first ring. The radial mode has a bandwidth of 6.5% and the concentric mode a bandwidth of 5.8%.

After the design of both the single rings, the simulation of the whole circular HIS, as presented in Fig. 7, is carried on and results are shown in Fig. 8. As expected, the null phase frequency of both the modes is similar to the single rings one. This observation validates the following in the characterization of circular HIS: to simulate and to design different rings independently or all together lead to similar results. However, unlike cartesian lattices for which only one unit-cell simulation is performed to predict the response of the complete metasurface, it is necessary to simulate each ring to ensure all of them exhibit the same null phase frequency. In this letter, the waveguide-based reflection phase method is used to characterize circular High-Impedance Surfaces (HIS). Using a coaxial waveguide structure, the reflected phase can be determined for incident waves with concentric or radial polarization. The HIS is composed of a patch array arranged along a circular lattice over a grounded dielectric substrate without via. Effects of the geometrical dimensions of the circular HIS have been investigated and differences with a cartesian lattice have been highlighted. It has been shown that designing a circular HIS is more complicated than designing a cartesian HIS because of the curvature's effect. Thus, the proposed characterization is suitable to obtain the desired reflected phase response of a circular HIS for a possible integration with a circularly polarized antenna. The last section of the letter detailed the design methodology of a complete circular HIS.

Fig. 1 -

 1 Fig. 1 -HIS (a) unit cell of a cartesian lattice (b) unit ring of a circular lattice

Fig. 2 -

 2 Fig. 2 -Phase diagram of cartesian and circular HIS

Fig. 3 -

 3 Fig. 3 -Influence of patch width w p on the reflected phase

Fig. 5 -

 5 Fig. 5 -Influence of the gap g l on the reflected phase

Fig. 6 -

 6 Fig. 6 -Influence of the gap g w on the reflected phase

Fig. 8 -

 8 Fig. 8 -Reflected phase diagram of the two-rings HIS V. CONCLUSION


Lila Mouffok
email: lila.mouffok@telecom-paristech.fr

Anne Claire Lepage

Julien Sarrazin

Xavier Begaud

A compact dual-band dual-port diversity antenna for LTE

The design of a compact dual-band dual-port antenna system is presented. It operates in two frequency bands, 790-862 MHz and 2500-2690 MHz, thereby making it suitable for Long Term Evolution (LTE) handheld devices. The proposed system is composed of two orthogonal inverted-F antennas (IFA) to perform diversity in mobile terminals. A good agreement is observed between simulated and experimental results. The high antenna diversity capability of the proposed system is highlighted with the calculation of envelope correlation coefficient, mean effective and diversity gains for different environment scenarii.

Introduction

The use of multiple antennas can improve reliability and increase the channel capacity [START_REF] Foschini | On limits of wireless communications in a fading environment when using multiple antennas[END_REF]. However, for wireless mobile devices, the available space is limited. Therefore, compact antenna systems are required. Recently, a variety of compact antennas for MIMO (Multiple-Input Multiple-Output) systems have been presented. An internal loop antenna with distributed feed which operates in LTE 700 MHz and GSM 800 MHz bands is presented in [START_REF] Eom | Broadband internal antenna for 700 MHz LTE application with distributed feeders[END_REF]. In this solution the two operating bandwidths are close. A dual port ferrite antenna is presented in [START_REF] Lee | Miniature Long-Term Evolution (LTE) MIMO ferrite antenna[END_REF] which operates in LTE 700 MHz but with low gain (-8 dBi). In [START_REF] Kulkarni | A compact multiband antenna with MIMO implementation for USB Size 4G LTE wireless devices[END_REF], to achieve compactness, a PIFA is top loaded with a dielectric sheet. This solution covers the bands: 1710-1880 MHz, DCS 1800 MHz, and 2.5-2.69 GHz. Significant research has been made on dual-port and multiband antennas. However, there are few solutions covering two bands which are separated by more than an octave such as LTE bands (790-862 MHz and 2.5-2.69 GHz), with implementation of MIMO, for handheld devices.

Thus, the objective of the work presented in this paper is to propose a compact antenna system for mobile devices that operates in the above mentioned bands.

Antenna design

The proposed structure is printed on FR4 substrate with ε r =3.7, tan δ=0.019, and thickness of 0.7 mm (fig. 1). The dimensions of the ground plane are L*L=70*70 mm 2 (λ 01 /5 * λ 01 /5) where λ 01 is the free space wavelength of the lower band central frequency (f 1 =816 MHz). The structure is composed of two identical elements shaped IFA (Inverted-F Antenna) located orthogonally to each other. The longer monopole allows operation on the lower band. It is connected to the ground plane with a metallic via hole to improve impedance matching. Its dimensions are l 1 =60 mm (λ 01 /6), and h 1 =16 mm (λ 01 /22). The shorter L shaped monopole controls the higher band operation with dimensions of l 2 =7.6 mm (λ 02 /15) and h 2 =8.4 mm (λ 02 /13) where λ 02 is the free space wavelength of the higher band central frequency (f 2 =2.6 GHz). The two monopoles are fed by two 50 Ohms SMA connectors (fig.

Experimental results and discussions

The proposed structure has been simulated with the transient solver of CST Microwave Studio® and a prototype has been fabricated. Simulated and measured S-parameters are compared in Fig. 2. A similar behavior between simulations and measurements is obtained. The structure operates in two bands (|S 11 | < -6 dB): the lower band is about 10% (777-862 MHz) and the higher one about 8 % (2.49-2.70 GHz). The mutual coupling between the two ports is less than -6 dB in the lower band and -13 dB in the higher one. Polarization diversity is naturally achieved because of the orthogonal positions of both antennas. For both planes and both bands, it is found that the simulated and the measured radiation patterns are in good agreement.

In the lower band, the measured cross-polar level is about 10 dB lower than the co-polar level in the H plane but it increases in the E plane at 90° direction. This is due to the coupling with the second radiating element. To further investigate the diversity, the simulated radiation patterns of each antenna in the XY plane for the two bands are plotted in Fig. 4 (one port is excited while the other one is loaded by 50 ohms). Thanks to a good agreement observed in Fig. 3 between simulations and measurement, only simulations results are presented. As it can be observed for the lower band, quasi-orthogonality between the patterns is achieved. The maximum realized gain is about 1 dB at 0° for the port 1 and 1 dB at -90° for the port 2. The realized gain, by definition, takes into account the reflection coefficient at each port. For the higher band, the maximum realized gain is 3.5 dB. At 2.6 GHz, even if patterns are not orthogonal, the two monopoles present minimum and maximum gain in different directions. This is well-suited to provide high diversity capabilities.

Evaluation of the diversity performance

In this section, we propose to evaluate the diversity performance of the proposed antenna by calculating the envelope correlation coefficient, the mean effective gain and the diversity gain while taking into account the propagation environment.

The envelope correlation coefficient ρ e quantifies the similarity between the radiation patterns of the two monopoles. The lower the correlation, the better the diversity performance. Vaughan shows in [START_REF] Vaughan | Antenna diversity in mobile communication[END_REF] that this coefficient can be expressed by (1) using the complex electric field radiated by each antenna.

(

) 1
ρൌ ቚ ሺE 1θ E 2θ * l Ω p θ XPD E 1φ E 2φ * p φ ሻdΩቚ 2  ሺE 1θ E 1θ * p θ XPD E 1φ E 1φ * p φ ሻdΩ l Ω  ሺE 2θ E 2θ * p θ XPD E 2φ E 2φ * p φ ሻdΩ
l Ω E 1θ (Ω), E 1φ (Ω), E 2θ (Ω), E 2φ (Ω) are complex electric fields along θ and φ radiated by the antenna fed by two different ports. The solid angle Ω is defined by θ [0: π] in elevation and φ [0:2π] in azimuth. p θ (Ω) and p φ (Ω) are the Angle-of-Arrival (AoA) distributions of incoming waves. The parameter XPD is the cross-polarization discrimination of the incident field and is defined as XPD= S φ /S θ (where S φ and S θ represent the average power along the spherical coordinates φ and θ). The environment depends strongly on the arrival angles distribution and on XPD. The most common distributions proven by measurements are Gaussian and Laplacian distributions [START_REF] Kalliola | Angular power distribution and mean effective gain of mobile antenna in different propagation environments[END_REF]. Thus, we consider different distributions in elevation, while in azimuth plane the distribution will be uniform, as demonstrated by the two main measurement campaigns in the literature [START_REF] Kalliola | Angular power distribution and mean effective gain of mobile antenna in different propagation environments[END_REF], [START_REF] Adachi | Cross correlation between the envelopes of 900 MHz signals received at a mobile radio base station site[END_REF]. In order to obtain more realistic results, different environments are considered. Each environment is characterized by typical values of XPD, mean angle of incident wave distribution (θ i ) and standard deviation of wave distribution (σ). These values were deduced from several measurements [START_REF] Kalliola | Angular power distribution and mean effective gain of mobile antenna in different propagation environments[END_REF], [START_REF] Ying | Diversity antenna terminal evaluation[END_REF], [START_REF] Adachi | Cross correlation between the envelopes of 900 MHz signals received at a mobile radio base station site[END_REF] for different environments: isotropic, indoor, and outdoor. The isotropic environment is defined by XPD=0 dB, p θ (Ω)=p φ (Ω)=1, the indoor environment by XPD=1 dB, θ i = 20°, σ =30° and the outdoor environment by XPD=5 dB, θ i = 10°, σ =15°.

The envelope correlation coefficient of the proposed structure has been calculated from simulated radiation patterns. Results are given in Fig. 5.

For the lower band, the correlation coefficient is higher at extremities than at the center of the band, for all environments (see Fig. 5a). Note that correlation takes into account the radiation, matching and isolation level at each frequency. According to S-parameters levels, the correlation is more or less higher. Since lS 11 l variation over the whole band is more significant (from -6 dB to -20 dB) than lS 21 l variation (from -6 to -8 dB), ρ e variation depends mainly on lS 11 l variation. Thus, the lower lS 11 l is, the lower ρ e is. For the higher band, the maximum value is below 0.08 which is less than in the lower band, thanks to a better isolation (<-13 dB). However, the ρ e levels remain below 0.16 for the two bands which largely satisfies the condition (ρ e <0.5) to provide high diversity capabilities [START_REF] Vaughan | Antenna diversity in mobile communication[END_REF].

In the following part, we evaluate the Mean Effective Gain (MEG) which was introduced by Taga [START_REF] Taga | Analysis for mean effective gain of mobile antennas in land mobile radio environments[END_REF]. It is defined as the ratio between the mean received power of antennas over the random route and the total mean incident power. When each monopole receives the same quantity of power, the MEG ratio of the two monopoles is equal to one, which means that no performance deterioration is expected due to some power imbalance [START_REF] Brown | Antenna diversity for mobile terminal[END_REF]. The mathematical expression is given by the equation ( 2):

(2)

MEGൌ න න ሺ XPD XPD1 π 0 2π 0 G θ p θ 1 XPD1 G φ p φ ሻdΩ
Where G θ and G φ are the θ and φ components of the antenna power gain pattern respectively. The calculated mean effective gains of the monopoles from simulated radiation patterns in the two bands are presented in Table I. It can be seen that the ratio of MEG 1 , determined at port 1, over MEG 2 , determined at port 2, is almost equal to 1, which satisfied equal contribution of the two monopoles to receive the same quantity of power. This is due to the fact that the proposed structure is completely symmetric and that the Gaussian and Laplacian angular distributions are taken only along the elevation as presented in [START_REF] Kalliola | Angular power distribution and mean effective gain of mobile antenna in different propagation environments[END_REF].

Finally, the efficiency of the diversity is usually presented in terms of diversity gain (DG). It can be defined as the difference between the signal-to-noise ratio (SNR) of the combined signals and the SNR of a single antenna. In theory, the maximum gain estimated for diversity of two antennas is 10.2 dB [START_REF] Diallo | Estimation of the diversity performance of several two-antenna systems in different propagation environments[END_REF]. It can be seen in Table 1 that calculated DG is about 10 dB across the whole desired bands, which is very satisfactory.

From the results shown in Fig. 5 and Table 1, it is found that the received signals satisfy the conditions ρ e < 0.5, MEG 1 /MEG 2 ≈1 and allows a diversity gain of 10 dB. These values fit the diversity requirements of MIMO systems.

Conclusions

In this paper, a compact dual-band dual-port system for handheld devices has been proposed. The radiation element has an advantage to be only 60*16 mm 2 (λ 01 /6 *λ 01 /22), thus it can be easily implemented in mobile terminals. In addition, it covers two bands which are separated by more than an octave. The system provides good diversity capabilities thanks to a low correlation coefficient (ρ e < 0.2), an equal amount of received power between the two radiating elements (MEG 1 /MEG 2 ≃1), and a diversity gain equal to 10 dB for different environments: isotropic, indoor and outdoor. Consequently, the presented design is suitable for MIMO communication applications.

Figure 1 :

 1 Figure 1: Photography and dimensions of the realized structure: (a) top view, (b) Bottom view.

Figure 2 :

 2 Figure 2: Simulated and measured S-parameters.

Fig. 3

 3 Fig.3compares the simulated and measured co-polar and cross-polar radiation patterns in the E plane (YZ plane) and H plane (XZ plane) respectively. Because both ports are symmetrical, we only present radiation patterns for port 1 at 816 MHz and 2.6 GHz (port 2 being connected to a 50Ω). Polarization diversity is naturally achieved because of the orthogonal positions of both antennas. For both planes and both bands, it is found that the simulated and the measured radiation patterns are in good agreement. In the lower band, the measured cross-polar level is about 10 dB lower than the co-polar level in the H plane but it increases in the E plane at 90° direction. This is due to the coupling with the second radiating element.

Figure 3 :

 3 Figure 3: Simulated and measured radiation patterns: (a) in the E plane at 816 MHz, (b) in the H plane at 816 MHz, (c) in the E plane at 2.6 GHz, (d) in the H plane at 2.6 GHz.

Figure 4 :

 4 Figure 4: Realized total gain (dB) in the XY plane for the two bands: (a) at 816 MHz (b) at 2.6 GHz.

Figure 5 :

 5 Figure 5: Envelope correlation for different environments of the proposed structure: (a) in the lower band (b) in the higher band.

Table 1 :

 1 Diversity performances of the proposed antenna.

MEG 1 /MEG 2 Diversity gain (dB)

		816	2.6	816	2.6
		MHz	GHz	MHz	GHz
	Isotropic	-4.33/-4.35	-4.93/-4.91	9.9	9.9
	Indoor
	Gaussian	-5.03/-5.05	-5.17/-5.15	9.9	10
	Outdoor
	Gaussian	-7.63/-7.64	-7.18/-7.15	9.9	9.9
	Indoor
	Laplacian	-5.04/-5.05	-5.17/-5.15	9.9	10
	Outdoor
	Laplacian	-7.63/-7.64	-7.18/-7.15	9.9	9.9

Acknowledgements

The research leading to these results has received funding from the European Community's Seventh Framework Program (FP7/2007-2013) under grant agreement SACRA n° 249060.