Samet Gelincik

Philippe Mary

Anne Savard

Jean-Yves Baudais

Preserving the Minimum Distance of Polar-Like Codes while Increasing the Information Length

Keywords: Polar codes, Reed Muller codes, minimum distance, code extension

Reed Muller (RM) codes are known for their good minimum distance. One can use their structure to construct polar-like codes with good distance properties by choosing the information set as the rows of the polarization matrix with the highest Hamming weight, instead of the most reliable synthetic channels. However, the information length options of RM codes are quite limited due to their specific structure. In this work, we present sufficient conditions to increase the information length by at least one bit for some underlying RM codes and in order to obtain pre-transformed polar-like codes with the same minimum distance than lower rate codes. Moreover, our findings are combined with the method presented in [1] to further reduce the number of minimum weight codewords. Numerical results show that the designed codes perform close to the meta-converse bound at short blocklengths and better than the polarized adjusted convolutional polar codes with the same parameters.

I. INTRODUCTION

Polar codes are the first provably capacity achieving error correction codes with explicit construction and a low complexity decoder, based on successive cancellation for binary input memoryless channels [START_REF] Arikan | Channel polarization: A method for constructing capacityachieving codes for symmetric binary-input memoryless channels[END_REF]. Thanks to their low complexity decoding, polar codes are now used for control channels in the 5G networks [3] and may be used for other usages in the future wireless network generations, such as ultra-reliable low-latency communications and massive machine-type communications [START_REF] Bioglio | Design of polar codes in 5G new radio[END_REF]. Eventhough polar codes are asymptotically capacity achieving, they do not show outstanding performance at short-to-moderate blocklenghts due to their poor minimum distance and a noncomplete polarization.

To overcome this issue, several methods such as enhanced-Bose-Chaudhuri-Hocquenghem subcodes [START_REF] Trifonov | Polar subcodes[END_REF] and low-weightbit polar codes [START_REF] Yuan | Polar code construction for list decoding[END_REF] have been proposed to improve the distance spectrum. In [START_REF] Miloslavskaya | Design of short polar codes for scl decoding[END_REF], a pre-transformation method based on brute search minimizing successive cancellation error probability for a given minimum distance has been proposed. However, the method is getting complex for blocklengths higher than 64. Cyclic-redundancy-check (CRC) aided successive cancellation list (SCL) decoding, which boosts the performance by choosing the best decoding paths in a hierarchical tree, has been proposed This work has been partially supported by IRCICA, CNRS USR 3380, Lille, France and the French National Agency for Research (ANR) under grant ANR-16-CE25-0001 ARBurst.

in [START_REF] Tal | List decoding of polar codes[END_REF]. This work has even been enhanced by optimizing the used CRC polynomial in order to improve the minimum distance in [START_REF] Zhang | CRC code design for list decoding of polar codes[END_REF], [START_REF] Piao | Approaching the normal approximation of the finite blocklength capacity within 0.025 dB by short polar codes[END_REF], and has been considered as the best code construction up to the introduction of polarized adjusted convolutional (PAC) polar codes in [START_REF] Arıkan | From sequential decoding to channel polarization and back again[END_REF].

The PAC polar codes, proposed by Arikan [START_REF] Arıkan | From sequential decoding to channel polarization and back again[END_REF], perform very close to the second-order rate approximation of the binary-input additive white Gaussian noise (BIAWGN) in short blocklength regime. The performance gain comes by choosing the information set of the polar code with the Reed-Muller (RM) rule, i.e., the rows of the polarization matrix that have the highest Hamming weights. Moreover, the convolutional pre-transformation allows to decrease the number of minimum weight codewords. The effect of pre-transformation has been justified in [START_REF] Li | On pre-transformed polar codes[END_REF], where it has been proved that any pretransformation with upper-triangular matrix, which is the case for PAC codes, does not reduce the minimum distance and can reduce the number of minimum weight codewords if properly designed. Based on [START_REF] Elkelesh | Decoder-tailored polar code design using the genetic algorithm[END_REF], authors in [START_REF] Tonnellier | On systematic polarization-adjusted convolutional (PAC) codes[END_REF] proposed a genetic algorithm tailored to PAC code construction that achieves higher rates than the ones authorized by RM rule and it performs better than the original Arikan's PAC codes.

We recently proposed another way to improve the performance of polar codes in the short blocklength regime by encoding some information bits with the sum of two or three rows of the polar encoding matrix [START_REF] Gelincik | Achieving PAC code performance without extra computational complexity[END_REF]. The pairs and triplets of merged rows are determined via the connection between the binary representations of the selected row indices and their common 1 bits. The designed codes achieve the same performance as PAC codes with same parameters, and without extra computational complexity.

In this work, we extend the method proposed in [START_REF] Gelincik | Achieving PAC code performance without extra computational complexity[END_REF] and state sufficient conditions to increase the information length of some polar-like codes with RM information set, i.e., to increase the rate for a given codeword length, and we explicitly give the corresponding deterministic pre-transformation matrix to sustain the same minimum distance as the RM code. We do the analysis by partitioning the indices of the encoding matrix rows with respect to the recursive structure projected on binary representation of row indices. Our proposed design is shown to perform close to the meta-converse (MC) bound and outperforms the PAC codes with the same parameters.

II. PRELIMINARIES

A. Notations

The entries in a vector of length N are indexed from 0 to N -1. Any vector of length N is considered as a row vector and is denoted by x or x N -1 . The j th entry of the vector x is denoted as x j . The set of positive integers is N and the binary field is F 2 . The set of integers from j to k -1 is represented by [j, k) or [j, k -1]. Uppercase calligraphic letters, such as A, are reserved to index sets. Any index set is sorted in the ascending order and A(i), i ∈ [0, |A|) denotes the i-th element of A. Specifically, we set N := [0, N ). For any given two index sets A and B, A ≻ B denotes that any element of A is larger than any element of B, i.e., A(i) > B(j) ∀i ∈ [0, |A|) and ∀j ∈ [0, |B|). For a given binary vector x ∈ F 1×N 2 and index set A ⊂ N , x A denotes the vector consisting of the elements of x at the positions indexed by A. The matrices are denoted by uppercase sans serif font, e.g., G. Uppercase boldface letters denote set of vectors, e.g., C. The indicator function is I{•}. The sets P 1 (•) and P 0 (•) denote the indices of 1's and 0's of a given vector, respectively.

For any 0 ≤ j < 2 n , its n-bit binary representation is denoted by the vector b n j , or b j if it is clear enough from the context. The ℓ-th bit position of b j is denoted by b j,ℓ , 0 ≤ ℓ < n and the indexing is started from the least significant bit, which is placed at the rightmost position. The number of 1's and 0's in a vector is represented by i 1 (•) and i 0 (•), respectively.

The operator ∪ represents the element-wise 'OR' operation of binary vectors such that, for all (j 1 , j 2 )

∈ [0, 2 n ) 2 : b j1,ℓ ∪b j2,ℓ = 1, if b j1,ℓ = 1 or b j2,ℓ = 1 (1)
The operator ∩ represents the element-wise 'AND' operation of binary vectors such that

b j1,ℓ ∩b j2,ℓ = 1, if b j1,ℓ = b j2,ℓ = 1 (2)
The operator ⊕ denotes binary addition in F 2 .

B. Properties of the Polar Encoding Matrix

For any given

N = 2 n , n ∈ N, the polarization matrix is G = G ⊗n 2 where G 2 := 1 0 1 1 (3)
is the corresponding kernel matrix and ⊗ is Kronecker product. The jth row g j of G can be represented by

g j = ĝbj,n-1 ⊗ ĝbj,n-2 ⊗ • • • ⊗ ĝbj,0 (4)
where ĝ0 = [1 0] and ĝ1 = [ 1 1]. By (4), for a given n ∈ N, the jth row of G can be divided into n disjoint regions, i.e.,

r j,ℓ = 0 2 ℓ -1 if b j,ℓ = 0 [r j,0 r j,1 • • • r j,ℓ-1 ] if b j,ℓ = 1 (5)
for ℓ ∈ [1, n) and r j,0 = ĝbj,0 . Close inspection of the recursive nature of r j,ℓ reveals that each bit position ℓ ∈ [0, n) of b j is associated with a set of positions at g j denoted by the index set

M ℓ ⊂ N M ℓ := {k : b k,ℓ = 1, k ∈ N } (6)
and

M c ℓ := N \ M ℓ . The fact that g j,M ℓ = 0 N/2-1 if b j,ℓ = 0 imposes that g j,M c
ℓ is independent from the value of b j,ℓ [START_REF] Gelincik | Achieving PAC code performance without extra computational complexity[END_REF]. The following definition highlights this fact.

Definition 1. The projection of a row g j of the polar encoding matrix onto indices of M c ℓ is denoted by g ℓ j and given as

g ℓ j := ĝbj,n-1 ⊗ • • • ⊗ ĝb j,ℓ+1 ⊗ ĝb j,ℓ-1 • • • ⊗ ĝbj,0 (7)
Note that, by ( 5), b j,ℓ = 1 imposes that [r j,0 r j,1 • • • r j,ℓ-1 ] is copied to r j,ℓ and r j,t>ℓ is obtained with respect to corresponding bit values. Hence, the projection of g j onto M ℓ is the same as g j,M c ℓ if b j,ℓ = 1

g j,M ℓ = 0 N 2 -1 if b j,ℓ = 0 g ℓ j if b j,ℓ = 1 (8)
The following definition is the generalization of Definition 1.

Definition 2. The projection of row g j of the polar encoding matrix onto ∩ ℓ∈B M c ℓ is denoted by g B j and g j | ∩ ℓ∈B M c ℓ , and is given as

g B j : = g j |∩ ℓ∈B M c ℓ = ĝb j,W(|W|-1) ⊗ ĝb j,W(|W|-2) ⊗ • • • ⊗ ĝb j,W(0) (9)
where

W := [0, n) \ B.
Note that, similar to (8), for any subset B 0 ⊂ B, the projection of g j onto ∩ ℓ∈B0 M ℓ ∩ l∈B/B0 M c l is given by

g j | ∩ ℓ∈B0 M ℓ ∩ l∈B\B0 M c l = 0 N |B| -1 if ∩ℓ∈B0 b j,ℓ = 0 g B j if ∩ℓ∈B0 b j,ℓ = 1 (10)

C. Row Merging Pre-transformed Polar-like Codes and RM Codes

A polar-like code (N = 2 n , k) ∈ N 2 , is constructed as

C = {c = uG : u ∈ F n 2 , u F = 0} ( 11
)
where F is the index set of the frozen bit positions, and

A = N \ F is the information set, with |A| = k and |F| = N -k.
For classical polar codes under SC decoding, the set A is the set of the most reliable bit sub-channels [START_REF] Arikan | Channel polarization: A method for constructing capacityachieving codes for symmetric binary-input memoryless channels[END_REF]. However in this paper, we allow to choose the information set differently. From this perspective, a RM(n, r) code of degree r can be seen as a polar-like code of information set

A = n p=n-r N p , N p := {t : i 1 (b t ) = p, t ∈ N }. (12)
In [START_REF] Hassani | Rate-dependent analysis of the asymptotic behavior of channel polarization[END_REF], the minimum distance of a polar-like code is given by

d(C) = min i∈A i 1 (g i ) (a) = 2 min i∈A i1(bi) (13)
where (a) is due to [1, Theorem 2].

The pre-transformed polar-like codes [START_REF] Li | On pre-transformed polar codes[END_REF] is obtained through a pre-transformation matrix T ∈ F N ×N 2

C P = {c = uTG : u ∈ F n 2 , u F = 0} ( 14
)
where T is an upper triangular matrix with T i,i = 1, i ∈ N and F d := {j : T i,j = 1, i ∈ N , j > i} is the set of dynamic frozen bits. If T is restricted such that |{i : T i,j , i ∈ N }| ∈ {1, 2} ∀j ∈ F d , then T turns out to be a row merging pretransformation matrix since some information bits are encoded with more than one row of the polarization matrix but any frozen row can be associated with at most one information row

c = uTG = u G (15)
with

gi = g i j∈P1(ti)\i g j ( 16
)
where ti is the i-th row of T.

III. ADDING INFORMATION BITS TO RM INFORMATION SET BY SUSTAINING THE SAME MINIMUM DISTANCE

In this section, we present how to obtain triples of polarization matrix rows to keep the same minimum distance as the underlying RM code and state the size of information length increment for some given parameters. Let T ⊆ N be any subset of row indices of the polarization matrix G. Then, by g T , we denote

g T = t∈T g t (17)

A. Preliminary Theorems

Let us first state a corollary of [1, Theorem 2] that will be exploited later on in the paper.

Corollary 1. Let Π : F n 2 → F n 2 be a permutation on binary representations of j ∈ N and T be the index set obtained by applying permutation Π to the binary representations of elements of T : b j = Π(b j ), j ∈ T and j ∈ T . Then,

i 1 (g T ) = i 1 (g T ) (18)
Proof: The number of common 1-bits will not change with permutation for any subset T w ⊂ T , i.e.,

i 1 ( ∩j∈T w b j ) = i 1 ( ∩j∈T w Π(b j )) = i 1 ( ∩j ∈Π T w b j ) = i 1 ( ∩j ∈ T w b j ) (19)
then, by [1, Theorem 2], the Hamming weight does not change.

The following theorem is also used to obtain subsequent results of this paper. It basically states that for any given set of rows of the polarization matrix, the Hamming weight of the sum of all rows is lower bounded by the maximum Hamming weight of the sum of a subset of rows whose binary representations are zero at the corresponding binary indices.

Theorem 1. For any given T ⊆ N the Hamming weight of g T is lower bounded by

i 1 (g T ) ≥ max ℓ∈[0,n) i 1 (g T 0 ℓ ) (20)
where

T 0 ℓ := {k : b k,ℓ = 0, k ∈ T }. Proof: For any u, v ∈ F 1×N 2 , we have i 1 (u ⊕ v) + i 1 (v) = i 1 (u) + i 1 (v) -2 • i 1 (u ∩v) + i 1 (v) = i 1 (u) + 2 • (i 1 (v) -i 1 (u ∩v) ≥0 ) ≥ i 1 (u). (21)
Then, note that for any j ∈ N

i 1 (g j ) = i 1 (g ℓ j ) if b j,ℓ = 0 2 • i 1 (g ℓ j ) if b j,ℓ = 1 (22)
for any ℓ ∈ [0, n) due to ( 7) and ( 8). Therefore, for any ℓ ∈ [0, n) we can write

i 1 (g T ) = (g T |M c ℓ ) + (g T |M ℓ ) ( 23
) (a) = i 1 ( j∈T g ℓ j ) + i 1 ( j∈T g ℓ j I{b j,ℓ = 1}) = i 1 ( j∈T g ℓ j I{b j,ℓ = 0} j∈T g ℓ j I{b j,ℓ = 1}) + i 1 ( j∈T g ℓ j I{b j,ℓ = 1}) (b) ≥ i 1 ( j∈T g ℓ j I{b j,ℓ = 0}) = i 1 ( j∈T 0 ℓ g ℓ j ) (c) = i 1 ( j∈T 0 ℓ g j )
where (a) is due to [START_REF] Miloslavskaya | Design of short polar codes for scl decoding[END_REF] and ( 8), (b) is due to (21) and (c) is due to (22).

Theorem 2. Let C be a polar-like code with information set A = n p=ℓ+1 N p . and (i, j, k) be a triple such that

(i, j) ∈ N ℓ , ℓ ≥ 2, k ∈ N 2 and i 1 (b i ∩b j ) = i 1 (b i ∩b k ) = i 1 (b j ∩b k ) = 0.
Moreover, let C be another polar-like code that encodes an additional information bit by g i ⊕ g j ⊕ g k , i.e., C := {C} ∪ {c : c = g {i,j,k} ⊕ g T , T ⊆ A}.

(24)

Then, the minimum distance of C is the same as C, i.e.,

d( C) = min{d(C), min T ⊆A i 1 (g {i,j,k} ⊕ g T )} = d(C) = 2 ℓ+1 (25)
Proof: The proof is given in Appendices of [START_REF] Gelincik | A pre-transformation method to increase the minimum distance of polar-like codes[END_REF].

B. Merging Three Rows with Common 1-bit Positions

The following theorem is a generalization of Theorem 2 and states the sufficient conditions on the rows of a triple with some common 1-bit positions in their binary representations, to be merged together such that the minimum distance of the underlying RM code is preserved. Theorem 3. Let C be a polar-like code with information set A = n p=ℓ+1 N p . and (i, j, k) be a triple such that

P 1 (b i ∩b j ) = P 1 (b i ∩b k ) = P 1 (b j ∩b k ) ̸ = ∅, (i, j) ∈ N ℓ , k ∈ N i1(bi ∩bj )+2 , ℓ ≥ i 1 (b k ).
Let the code C be:

C := {C} ∪ {c : c = g {i,j,k} ⊕ g T , T ⊆ A} (26)
Then,

d( C) = d(C) = 2 ℓ+1 (27) Proof: Since d( C) = min{d(C), min T ⊆A i 1 (g {i,j,k} ⊕ g T )} (28)
it is sufficient to prove the following statement

i 1 (g {i,j,k} ⊕ g T ) ≥ 2 ℓ+1 , ∀T ⊆ A. ( 29
)
For any T ⊆ A, the index set can be divided into two subsets such that

T := {t : P 1 (b t ) ∩ P 0 (b i ∪b j ∪b k ) ̸ = ∅, t ∈ T } ( 30
)
and T = T \ T . Then,

i 1 (g {i,j,k} ⊕ g T ⊕ g T ) (a) ≥ max p0∈P0(bi ∪bj ∪b k ) i 1 (g {i,j,k} ⊕ g T t∈ T g t I{b t,p0 = 0}) (b) ≥ max p1∈P0(bi ∪bj ∪b k )\p0 i 1 (g {i,j,k} ⊕ g T t∈ T g t I{b t,p0 = b t,p1 = 0}) . . . (c) ≥ i 1 (g {i,j,k} ⊕ g T t∈ T g t I{b t,p0 = b t,p1 =• • •= b t,p n-2ℓ-1 = 0}) (d) = i 1 (g {i,j,k} ⊕ g T ) (31)
where {p 0 , p 1 , • • • , p n-2ℓ-1 } = P 0 (b i ∪b j ∪b k ), where (a), (b) and (c) follow from the repeated application of Theorem 1, and (d) comes from (30), which implies that there is no t ∈ T such that P 1 (b t ) ∩ {p 0 , p 1 , • • • , p n-2ℓ-1 } = ∅. This means that the Hamming weight of g {i,j,k,T } is lower bounded by the Hamming weight of g {i,j,k, T } . Therefore, in the following, we will proceed the proof for T .

Note that by assumption of the theorem P 1 (b i ∩b j ) = P 1 (b i ∩b j ∩b k ). Now, assume that W = P 1 (b i ∩b j ∩b k ), which is the index set of common one bit positions of b i , b j and b k . Then, by partitioning the row indices of the polar encoding matrix, we obtain the following expression

i 1 (g {i,j,k} ⊕ g T ) = i 1 (g {i,j,k} ⊕g T |M c W(|W|-1) ∩M c W(|W|-2) ∩• • •∩M c W(0) ) + i 1 (g {i,j,k} ⊕g T |M c W(|W|-1) ∩M c W(|W|-2) ∩• • •∩M W(0) ) . . . + i 1 (g {i,j,k} ⊕g T |M W(|W|-1) ∩M W(|W|-2) ∩• • •∩M W(0) ) (a) = i 1 (g W {i,j,k} t∈ T g W t )+i 1 (g W {i,j,k} t∈ T g W t I{b t,W(0) = 1}) . . . + i 1 (g W {i,j,k} t∈ T g W t I{b t,W(|W|-1) =b t,W(|W|-2) =• • • • • • = b t,W(0) = 1}) (32)
where (a) is due to ( 9) and [START_REF] Piao | Approaching the normal approximation of the finite blocklength capacity within 0.025 dB by short polar codes[END_REF]. Since P 1 (b i ) \ P 1 (b i ∩b j ), P 1 (b j ) \ P 1 (b i ∩b j ) and P 1 (b k ) \ P 1 (b i ∩b k ) comply with the conditions of Theorem 2, each term of the partition is lower bounded by 2 ℓ-|W|+1 . Then,

i 1 (g {i,j,k} ⊕ g T ) ≥ 2 i1(bi ∩bj ) • 2 ℓ-i1(bi ∩bj )+1 = 2 ℓ+1 (33)
where

|W| = i 1 (b i ∩b j ).
In the following, we state the sufficient conditions to increase the information length by multiple bits for a fix codeword length. Thanks to the symmetry imposed by Corollary 1, we apply a permutation Π to any given row triple satisfying the conditions of Theorem 3 to have the following form

P 1 (b i ∪b j ∪b k ) ≻ P 0 (b i ∪b j ∪b k ) (34)
and

P 1 (b i ∩b j ∩b k ) ≻ P 1 (b i ∪b j ∪b k ) \ P 1 (b i ∩b j ∩b k ) (35)
and

P 1 (b k ) \ P 1 (b i ∩b j ) ≻ P 1 (b j ) \ P 1 (b i ∩b j ), P 1 (b k ) \ P 1 (b i ∩b j ) ≻ P 1 (b i ) \ P 1 (b i ∩b j ) (36)
and

P 1 (b i ) \ P 1 (b i ∩b j ) ⊁ P 1 (b j ) \ P 1 (b i ∩b j ), P 1 (b j ) \ P 1 (b i ∩b j ) ⊁ P 1 (b i ) \ P 1 (b i ∩b j ) (37)
Moreover, let Π θ p be a left-circular shift permutation on the index set of binary representation of p ∈ N , with θ ∈ [0, t 0 +t 1 ],

t 0 = i 0 (b i ∪b j ∪b k ) and t 1 = i 1 (b i ∩b j ∩b k ). We have b Π θ p ,v = b p,v-θ+n (mod n) (38)
The following theorem is the main result of this paper.

Theorem 4. Let C be a polar-like code with information set A = n p=ℓ+1 N p . Let (i, j, k) be a triple satisfying the conditions of Theorem 3 and (34), (35), (36), (37). Let C be a code obtained by encoding each of the extra m ≤ t 0 + t 1 + 1 information bits with a merged row triple g {Π θ i ,Π θ j ,Π θ k } . Then,

d( C) = d(C) (39)
Proof: The proof is given in Appendices of [START_REF] Gelincik | A pre-transformation method to increase the minimum distance of polar-like codes[END_REF]. The following section explains how Theorem 4 is used in order to increase the information length of a polar-like code with RM information set by preserving the minimum distance.

IV. CODE CONSTRUCTION

Let us consider a triple (i, j, k) that satisfies the conditions of Theorem 3, (34), ( 35), (36) and (37). For any m ∈ [1, t 0 + t 1 + 1],

• m-1 triples, {(i 0 , j 0 , k 0 ), • • • , (i m-2 , j m-2 , k m-2 )}, are obtained from the left-circular shift of (i, j, k). • For all triples, the permutation of their binary representations such that the smallest element among all the triples is maximized, is searched. This prevents from adding more badly polarized bit sub-channels to the information set. Indeed, with Corollary 1, the code constructed by any permutation of m-triples has the same distance spectrum since the underlying information set is chosen by RM rule.

• Algorithm 1, proposed in [START_REF] Gelincik | Achieving PAC code performance without extra computational complexity[END_REF] and given below for the sake of completeness, is applied to obtain the pairs (t, v), where t ∈ N ℓ+1 , v ∈ N ℓ , v > t, ℓ = i 1 (b i ), to decrease the number of minimum weight codewords.

Remark 1. Even though we have verified experimentally that the application of the third step does not decrease the minimum distance, an explicit proof remains to be done.

The pre-transformation matrix is constructed by adding the smallest index of each of m-triple to the information set and the other two indices are considered as dynamic frozen bits. For any obtained pair (t, v), v is considered as a dynamic frozen bit. The pre-transformation matrix T, is such that

T a,a = T a,b = T a,c = T t,v = 1 (40)
where a ∈ N is the minimum of the triples, and v ∈ N ℓ is the associated index to any t ∈ N ℓ+1 by the application of Algorithm 1 for a given ℓ * = i 1 (b t ∩b v ) ≤ ℓ -1.

Algorithm 1: Row Merging Pairs for ℓ * .

Set K ← N ℓ ; for w = 1 to |N ℓ+1 | do Set t ← N ℓ+1 (w); Set K t ← {z : i 1 (b t ∩b z ) = ℓ * , z > t, z ∈ K}; if K t ̸ = ∅ then Set (t, v) ← (t, K t (1)) ; Set K ← K \ v; end end
Decoding is performed by SCL decoding with dynamic frozen functions, i.e. instead of setting a frozen bit to zero as in standard SCL decoding, the value of any dynamic frozen bit is set through its corresponding dynamic frozen function.

V. SIMULATION RESULTS

We numerically compare in Figure 1 our proposed design (PD) with PAC codes under SCL decoding with list size 256 and the saddle-point approximation of the MC (SMC) bound [START_REF] Anada | An upper bound on the error induced by saddlepoint approximations-applications to information theory[END_REF] for BIAWGN channel. Our construction for the code For PAC codes, the additional information indices are chosen as the most reliable bit subchannel indices from the set N ℓ , which are the highest indices due to partial ordering [START_REF] Schürch | A partial order for the synthesized channels of a polar code[END_REF]. We optimize the polynomial of the convolutional code with memory length 7 to minimize the number of minimum weight codewords. The algorithm [START_REF] Li | An adaptive successive cancellation list decoder for polar codes with cyclic redundancy check[END_REF] with a large list size, i.e., 5•10 4 , has been implemented and we choose the polynomial that leads to the minimal number of second minimum weight codewords since the number of minimum weight codewords does not change for a few increment of the information length. As a result, we have implemented PAC codes with the polynomials [1 1 0 0 1 1 0 0 1] and [1 1 1 1 0 1 1 1] for information lengths k = 66 and k = 100, respectively.

It is seen that our design performs better than PAC codes for the entire range of SNR, since, at short blocklengths, the minimum distance plays an important role in the SCL decoding with large list sizes. Moreover, our design performs close to the MC bound especially at high E b /N 0 .

VI. CONCLUDING REMARKS

In this work, we proposed a method to increase the information length of a polar-like code while keeping the same minimum distance with the underlying RM code. Moreover, we proposed an heuristic to reduce the number of minimum weight codewords that allows to design codes that perform closer to the MC bound than PAC codes with the same system parameters. We believe that this work allows a better understanding of the polarization matrix properties, which may lead to more efficient code design, particularly for short blocklengths. The extension of this work to moderate blocklengths is under investigation.

  128, 66) is obtained by first adding two extra bits to the (128, 64) polar-like code with RM information set and then by applying Algorithm 1 to obtain the (t, v) pairs such that i 1 (b t ∩b v ) = 1. Similarly, the code (128, 100) is obtained by first adding one extra bit to the polar-like code (128, 99) with RM information set and then by applying Algorithm 1 to obtain the (t, v) pairs such that i 1 (b t ∩b v ) = 0.

	k = 66, SMC	k = 66, PD	k = 66, PAC
	k = 100, SMC	k = 100, PD	k = 100, PAC
	10 -1
	Frame Error Rate
		E b /N 0 in dB
	Figure 1. FER of our proposed scheme (PD), compared to SMC and PAC
	codes, N = 128, k ∈ {66; 100}.

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Keywords: Silicon carbide, power MOSFET, neutrons, single event burnout

The mechanisms responsible for the neutron-induced single event burnout (SEB) in commercial Silicon Carbide power MOSFETs under atmospheric-like neutron spectrum was investigated and analyzed. Combined effect of applied reverse gate voltage and drain voltage was evaluated. First, local analysis of the packaged device at the wafer level is performed to reveal the failure mechanism inside the semiconductor lattice. Secondly, based on gate stress testing of survived devices and looking at the influence of reverse gate bias during irradiation, we demonstrated an enhanced failure sensitivity especially for drain voltage values close to the safe operating area. In addition to support this assumption, TCAD simulations with damage sites were performed in order to address physical mechanisms related to gate leakage degradation and SEB.

I. INTRODUCTION

Power MOSFETs have been known for decades to be susceptible to atmospheric environment [START_REF] Oberg | First observations of power MOSFET burnout with high energy neutrons[END_REF], [START_REF] Normand | Neutron-induced single event burnout in high voltage electronics[END_REF]. In particular, it is well known that their failure probability increases with applied drain-to-source voltage (VDS). For device qualification, the most common method for assessing the radiation sensitivity of power MOSFET is to test with different VDS values while gate-to-source voltage (VGS) is kept at 0 V. This is to ensure that the transistor is in off-state which means there is no current flowing through the channel of the transistor. In this context, several studies focused on the effect of applied drain voltage on destructive failure sensitivity of SiC power MOSFETs under atmospheric neutron environment [START_REF] Lichtenwalner | Reliability of SiC power devices against cosmic ray neutron single-event burnout[END_REF]- [START_REF] Asai | Tolerance against terrestrial neutron-induced single-event burnout in SiC MOSFETs[END_REF] and heavy ion irradiations [START_REF] Mizuta | Investigation of single-event damages on silicon carbide (SiC) power MOSFETs[END_REF], [START_REF] Witulski | Single-Event Burnout Mechanisms in SiC Power MOSFETs[END_REF]. However, the impact of gate voltage on the sensitivity to radiation induced failure has not been considered in such studies.

For silicon devices, the effect of gate voltage on the single event burnout (SEB) sensitivity under atmospheric neutron environment has been investigated in some studies for IGBTs [START_REF] Foro | Gate voltage contribution to neutron-induced seb of trench gate fieldstop IGBT[END_REF] and power MOSFETs [START_REF] Hands | Single event effects in power MOSFETs due to atmospheric and thermal neutrons[END_REF], [START_REF] Liu | Recommended test conditions for SEB evaluation of planar power DMOSFETs[END_REF]. The contribution of gate voltage is often related to single event gate rupture (SEGR). For SiC MOS power devices, SEGR sensitivity has been reported to be lower compared to Si devices [START_REF] Deki | Single event gate rupture in SiC MOS capacitors with different gate oxide thicknesses[END_REF]. Therefore, SEGR is not supposed to be the main failure mechanism to be expected for SiC devices.

When power MOSFET devices are used in operation, such as in switching power converter, the VGS is likely to vary between negative and positive values. For example, in switching power converter utilizing SiC power MOSFET, VGS can vary from -4 V to 15 V during switching operation [START_REF]CRD-60DD12N 60kW Interleaved Boost Converter[END_REF]. Therefore, it is important to assess, if the off-state gate voltage plays a role in the sensitivity to destructive failure while operating in radiation environment.

In this paper, the effect of reverse applied gate voltage on the SEB sensitivity of SiC power MOSFET during neutron irradiation is investigated. For this, three different drain bias voltages are used during the test for two different VGS values: 0 V and maximum negative value. For failed devices, a failure analysis at the wafer level has been performed in order to identify and well understand the SEB mechanisms and consequences. In addition, to perform a comprehensive study, post irradiation gate stress (PIGS) testing and simulations are performed for survived devices in order to reveal possible latent damage induced by neutron radiation II. EXPERIMENTAL DETAILS Devices under test (DUT) in this study are discrete commercial 3 rd generation SiC power MOSFETs manufactured by CREE (part number C3M0120090D, lot number W14918). Each device has the same lot number. The devices have vertical structure and the package type is TO-247-3. Nominal maximum ratings are VDS = 900 V, VGS = -4/+15 V, IDS = 23 A and Ron = 120 m. Electrical characterizations, including IDSVGS and IGSVGS measurements, have been performed before and after irradiation. In addition, forward IDSVDS characteristics of the body diode were also measured.

In total, 120 devices and 6 voltage configurations during irradiation were tested. 20 DUTs per configuration were irradiated at room temperature in parallel configuration. During irradiation, devices were biased at VDS = 675 V, VDS = 765 V and VDS = 900 V (75%, 85% and 100% of VDSmax respectively). For each VDS value, gate voltage configurations VGS = 0 V and VGS = -4 V were tested. As indicated, the devices for each test configuration were from the same manufacturing lot and therefore, no process related effects on the device behavior should be expected.

A. Facility description

Neutron irradiations were performed at the ChipIr facility [START_REF]ChipIr facility website[END_REF] in Rutherford Appleton Laboratory, UK. The facility provides atmospheric-like neutron spectrum with acceleration factor of 10 9 compared to ground level neutron flux. The nominal neutron flux was 5.4 × 10 6 n/cm 2 /s (En > 10 MeV) at the test position. A comparison between the ChipIr neutron energy spectrum and atmospheric neutron energy spectrum is given in [START_REF]ChipIr facility website[END_REF].

B. Irradiation test setup

For the experimental study, test board schematics follows the MIL-STD-750E test standard [START_REF]Test Method Standard[END_REF]. The test board containing DUTs was placed under beam while drain and gate voltages were controlled and total currents were monitored with PC and SMUs in the control room. Drain voltage was applied and total drain current was measured with Heinzinger EVO HV power supply. Gate voltage was applied and corresponding current measured with Keysight B2902A precision source meter unit (SMU). Schematics of the test setup is presented in Fig. 1.

During irradiation, destructive failure of the DUT was identified by step increase of the total current caused by low resistance path inside the device structure.

III. RESULTS AND DISCUSSION

A. Reliability extraction from failure data

Based on literature [START_REF] Akturk | Terrestrial Neutron-Induced Failures in Silicon Carbide Power MOSFETs and Diodes[END_REF], [START_REF] Asai | Tolerance against terrestrial neutron-induced single-event burnout in SiC MOSFETs[END_REF], regarding the drain bias, the most sensitive configuration for SEB is the highest drain voltage during the irradiation. Then for this configuration, DUTs were kept under beam until all of the devices were failed. For other configurations, the beam was stopped, when at least 65 % of the DUTs were failed, in order to gain sufficient statistics and plot an accurate reliability law.

To determine statistical failure behavior of the irradiated devices, a Weibull analysis has been performed on the failure data. Y-value for the data points for the Weibull plot were obtained after Benard's approximation [START_REF] Abernethy | The new Weibull handbook : Reliability & statistical analysis for predicting life, safety, survivability, risk, cost and warranty claims[END_REF], which is given in (1):

𝐹 = 𝑖 -0.3 𝑁 + 0.4 , ( 1
)
where i is the running number of the failure and N is the total number of devices. Thus, the value of the fluence for each failure is then determined and represented on the x-axis (Fig. 2). Failure plots for each irradiation run are done in Fig. 2 for all bias configurations. Weibull parameters were extracted by using software library [START_REF] Reid | Reliability -a Python library for reliability engineering[END_REF] and by using maximum likelihood estimation (MLE). As a cross correlation procedure, second analysis on the failure data was performed by using linear regression (LR) method in which linear fit is performed on the Weibull data by using least squares method.

Based on the Weibull parameters, we have also extracted mean fluence to failure (MFTF) which in turn can be derived from extracted Weibull parameters with [START_REF] Normand | Neutron-induced single event burnout in high voltage electronics[END_REF]. All the extracted parameters are given in Table I.

𝑀𝐹𝑇𝐹 = 𝜂 × Γ(1 + 1 𝛽 ) (2)
The Weibull shape parameter β is an indicator of failure rate behavior over time. If β < 1, the distribution will show a decreasing failure rate with time, which is representative of early life failures. If β > 1, it implies increasing failure rate with time. Finally, β = 1 implies random failures which means constant failure rate over time. When dealing with neutroninduced failure, a β = 1 is to be expected.

B. The effect of combined applied drain and gate voltages on SEB sensitivity

As mentioned earlier, the goal of this study is to investigate the role of applied gate voltage either during irradiations on the SEB occurrence and also on the long term reliability for unfailed devices. Therefore, considering at first the influence of reverse gate bias on SEB sensitivity, two different VGS values for each VDS configuration were tested during irradiations.

By comparing the MFTF values in Table I, we can see, as expected, that the applied bias on the drain strongly increases the risk of failure. The lower the applied VDS, the higher the fluence needed for the device to fail. However, beyond those well-known considerations, this figure rises some questions about the contribution of the reverse gate voltage on the risk of failure during irradiation.

Indeed, looking more closely on the MFTF (Table I) for the lowest applied VDS value (675 V), we can see that the MFTF seems to be affected by the applied gate voltage. This might indicate an enhanced sensitivity to SEB when VGS = -4 V. In literature, similar negative gate bias dependence on the SEB sensitivity has been observed for trench Si IGBT technology [START_REF] Foro | Gate voltage contribution to neutron-induced seb of trench gate fieldstop IGBT[END_REF]. This behavior is not so clearly observed for higher drain voltage, though the behavior at 900 V is unclear. Indeed, if the mean fluence to failure values tend to indicate a higher sensitivity when a reverse gate bias is applied, the minimum and maximum values are overlapping for the two configurations. We assume thus that the contribution of the reverse gate bias to SEB increases as the drain voltage is closer to the safe operating area (SOA) limit, which for this reference has been found to be between 50% and 75% of the applied drain voltage [START_REF] Niskanen | Impact of electrical stress and neutron irradiation on reliability of silicon carbide power MOSFET[END_REF]. Indeed, applied drain voltage results in electric field across the drift layer which is an important contributor to the SEB triggering for such devices [START_REF] Shoji | Analysis of neutroninduced single-event burnout in SiC power MOSFETs[END_REF], especially at maximum electrical rating.

In addition to MFTF parameter, we should also pay attention to the number of failed devices for different irradiation configurations in Table I. For irradiation configuration VDS = 675 V, VGS = 0 V, after the beam was stopped, we observe 13 failures over 20 devices irradiated. However, while the reverse gate bias was applied, with the same VDS and same stopping fluence, we observe 19 failures over 20 devices irradiated. This can indicate an enhanced SEB sensitivity for VDS = 675 V configuration when reverse gate bias is applied. For higher VDS values, no such differences between VGS configurations are observed.

Finally, looking at the reported results in Table I, we can see that β values are close to 1 for each configuration, confirming random failures, which is expected failure mode for neutron induced-failures since the interaction is considered stochastic. However, for each VDS voltage configuration, β values for configurations with negative gate voltages are relatively greater compared to configurations with VGS = 0. This behavior might be related to the possibility that reverse gate bias might act as a complementary stressor for the device, giving an increase to the failure rate over time.

Those three aforementioned parameters (MFTF, number of failures, β) give us indication of enhanced SEB sensitivity of SiC MOSFET close to the SOA limit while negative gate bias is applied.

In order to well understand the failure mechanism of SiC power MOSFET and evaluate with precision the parameters which impact the SEB occurring, we performed following investigations:  On one hand, a failure analysis at the wafer level has been performed for devices having suffered a SEB (section C).  On the other hand, a Post Irradiation Gate Stress (PIGS) test has been performed for unfailed devices irradiated at VDS = 675 V (section D-1).  Then, in order to support experimental results and related hypothesis, TCAD simulations have been performed (section D-2).

C. Neutron-induced damage failure analysis at wafer level

In order to increase the understanding of the destructive mechanism, a failed device (having suffered a SEB) was analyzed at the SiC wafer level. For the semiconductor analysis, scanning electron microscopy (SEM) observations were performed at the failure location.

IV-characteristics in Fig. 3 show the electrical signature of the SEB for a device irradiated at VDS = 675 V and VGS = 0 V. Note that IDS reaches the compliance limit of the measurement unit at 1A. A drain to source shortening signature is observed while the gate leakage shows a linear behavior with gate voltage (Fig. 3). This linear gate leakage behavior indicates that the oxide exhibits a resistive response typical of a low resistance current path on the gate.

In this case, the challenge was to locate the failure. In fact, for SEB failure, the device degradation is the consequence of a single probabilistic neutron interaction with the SiC material of the packaged device. This first interaction originates in the generation of one or several secondary ions themselves able to generate electron-hole pairs in the semiconductor. Thus, because of the stochastic aspect of the interaction, a simple cross-section along an axis parallel to the gates is not suitable. Indeed, the probability to find out the failure signature would be too low. In addition, in our case, it is important to note that the epoxy molding component (EMC) material of the TO-247-3 packaging did not present any defects (holes, peeling, cracks, etc...) allowing to have a first indication of the possible location of the failure signature. This complicated the localization of the SEB defect.

Therefore, before the cutting of the SiC packaged device, a fine localization of the SEB signature at the wafer level is necessary. To this end, an original sample preparation was developed. To be sure to find out and analyze the local degradation for a failed device, several steps are required: packaging opening, localization of the defect, cutting, polishing and observation. Obviously, all steps must maintain the integrity of the defect, which means that the device preparation must not introduce additional defects. For that, after the mechanical opening of the resin package on the back side, the SiC die was thinned from the drain side in order to achieve a thin SiC layer which becomes optically transparent (Fig. 4). After that, we were able to locate the failure point through the thin SiC material. A defect with a diameter of 202 µm was thus optically located from the back side of the thinned SiC. The sample cutting line was then located at the center of the observed failure location and to finish the sample preparation, the cross section of the SiC device was polished. After sample preparation, the device was observed with scanning electron microscopy (SEM). Results are presented in Fig. 5. The crosssectional SEM view indicates the failure inside the SiC MOSFET structure.

As expected, no degradation is observed in the EMC material. The neutron passed completely through the EMC packaging without damage. However, a strong detachment of the epoxy matrix is to be noted. Surely a signature of a strong energy release during the SEB. Moreover, a melted area which due to the high localized current and subsequent thermal expansion of the SiC material, is revealed.

We can see in Fig. 5 that width of the damage site is similar to the width of the elementary cell. In particular, we can observe that the oxide region has been melted for a single cell. According to our best knowledge, this is the first time that neutron SEB failure is located and analyzed by SEM while there are no cracks on the packaging of the commercial SiC power MOSFET. In addition to the damage caused by the melting of the metallic contact at the device surface leading to the melting of the oxide region, the melting occurs also deeper below in the SiC material. We also identified two main cracks inside the lattice of the device localized in the N -drift region. For this region, the doping has a lower value and therefore the layer material has higher resistance compared to highly doped drain layer. Higher resistance led thus to higher power dissipation and further higher temperature along the current path which eventually led to cracking of the semiconductor material. From this local analysis of the SEB signature at the wafer level, we turned our attention to gate oxide for the following.

D. Post-irradiation gate stress for survived devices and TCAD simulations

In this section, the long term reliability of survived devices is investigated. Indeed, though those devices have not suffered a SEB, they have very likely suffered non-destructive neutron interactions. This means that, due to the high electric fields inside each device cell, some current transients might have been generated inducing possibly some latent defects. Thus, a post irradiation gate stress (PIGS) has been performed on those devices in order to determine whether they were weakened due to irradiation D-1). In section D-2, hypothesis will be raised thanks to TCAD simulation focusing in particular on the contribution of the reverse gate bias.

1) Post-irradiation stress test

Looking at the lowest SEB sensitivity irradiation configuration (VDS = 675 V, VGS = 0 V), 7 devices over 20 did not exhibit SEB when the beam was stopped. In order to reveal possible latent damage induced by the neutron interaction, PIGS measurements were performed for these survived devices.

During the PIGS test, drain terminal was shorted with source terminal (VDS = 0 V) and gate voltage was swept from -8 V to +19 V, which is the safe dynamic gate voltage range for this technology. Before this stress test, note that no differences were observed in IDSVGS characteristics or in body-diode forward IDSVDS characteristics between pre-and post-irradiation measurements. However, in the survived devices lot, 3 devices over 7 show an increased gate current level during PIGS after neutron irradiation (Fig. 6). Due to a high sensitivity to SEB (only one survived device), the sensitivity to PIGS test of the other gate bias configuration (VDS = 765 V, VGS = -4 V) was not able to be investigated.

This means that for experimental data shown on Fig. 6, the gate degradation observed is only related to the influence of the electrical field induced by the VDS which resulted in transient currents through the oxide, generating subsequent latent damage sites within the oxide or at its interface. Therefore, though the latent damage generation should be emphasized by the reverse gate bias (as this will be discussed in section D.2 with the TCAD analysis), it was observed that the applied drainto-source voltage during irradiation is enough to generate latent damage sites within the oxide. Similar post-irradiation gate leakage has been observed also after heavy ion impact for SiC power MOSFETs [START_REF] Martinella | Current Transport Mechanism for Heavy-Ion Degraded SiC MOSFETs[END_REF], [START_REF] Abbate | Gate damages induced in SiC power MOSFETs during heavy-ion irradiation-Part I[END_REF], confirming our hypothesis.

Indeed, looking at the devices having survived to neutronirradiation, a clear gate oxide degradation has been revealed for almost the half of them (3 over 7). Concerning their functional capabilities, devices still maintained their blocking and switching capabilities.

However, those survived devices clearly exhibit a weakening of the gate oxide which might lead to a decrease of their lifetime. As an assumption, secondary ions generated by the primary neutron interaction, have induced free carrier generation. Depending on the location of the primary interaction, carriers have drifted or diffused. Due to the electric filed repartition, some interactions might have generated carriers which have drifted in the neck region below the oxide region leading to localized stresses by transient current through the oxide layer. Such localized electrical micro stress might induce localized interface and oxide traps originating in a decrease of local oxide resistivity and leading to an overall device reliability degradation.

2) TCAD simulation study

TCAD simulations were performed in order to address the physical mechanism of the device degradation and the impact of drain and gate bias on the failure behavior. TCAD tool ECORCE specifically developed for radiation effects studies [START_REF] Michez | ECORCE: A TCAD Tool for Total Ionizing Dose and Single Event Effect Modeling[END_REF] was used for this purpose. ECORCE uses a drift-diffusion model coupled with the heat equation (i.e., thermodynamic simulation with lattice temperature) and provides an automated and dynamic mesh generator that optimizes the mesh distribution for all modeling steps for either DC or transient analysis, and for 1D, 2D and axisymmetric geometries.

The implemented device geometry is presented in Fig. 7 and the simulation parameters are based on the previous work [START_REF] Niskanen | Impact of electrical stress and neutron irradiation on reliability of silicon carbide power MOSFET[END_REF]. Charge deposition subsequent to neutron interaction is modelled by Si-ion hit in the device active volume. In the following simulations, the ion impact occurs at t = 1 × 10 -14 s.

a) The effect of radiation impact on gate degradation

At first we have focused on the non-destructive interaction impact on the gate oxide. For that, the hole density (Fig. 8) and the electric field (Fig. 9) in the gate oxide layer were observed during charge deposition and transport inside the device structure. The impacting Si-ion energy was 30 MeV which has a range of 7.1 µm in SiC and a linear energy transfer (LET) value of 15.5 MeV cm 2 mg -1 . During simulations, investigated bias configurations were fixed at VDS = 675 V for two applied gate bias VGS = 0 V and VGS = -4 V.

Due to neutron and secondary recoiling ion, hole pairs are generated along the ion track in the SiC epitaxial layer. Observing the hole density right under the oxide layer brings a crucial information on the possibility that transient currents induced by secondary generated ions might create a localized micro stress of the oxide leading to the subsequent creation of latent damage sites. Investigation with TCAD the transport of holes for a specific ion track location in the neck region, a significant hole accumulation under the gate oxide layer is observed (Fig. 8). We can note that this result is similar to the SEGR mechanism observed in Si MOSFETs [START_REF] Allenspach | Evaluation of SEGR Threshold in Power MOSFETs[END_REF] though no SEGR has been observed during experiments. Based on experimental results and on TCAD simulations, it is thus expected that an applied negative gate bias would reinforce the probability of localized latent damage creation within the oxide, since the field in the oxide layer will reach higher value. Fig. 9 represents the simulated electric field in the device at t=0 ps and t = 3 ps after the ion impact.

A strong increase in electric field in the gate oxide during the ion impact is observed and can be related to hole accumulation as observed on Fig. 8 at t = 3 ps. Such electric field is not high enough to induce direct oxide failure [START_REF] Deki | Instability of critical electric field in gate oxide film of heavy ion irradiated SiC MOSFETs[END_REF] but can result, as discussed earlier, in charge injection within the oxide layer. This charge injection is likely to create latent defects in the oxide layer which may impact the long term reliability of the device during operation when a switching VGS is applied. In order to assess the impact of applied gate voltage on the gate oxide degradation, TCAD simulations were performed for both VGS = 0 V and VGS = -4 V configurations. Simulated time evolution of electric field values in the gate oxide layer during the ion impact for VDS = 675 V bias configuration are presented in Fig. 10. The measurement point is at the location where the electric field reached its maximum value (indicated in Fig. 9). It is important to note that this simulation study has focused on the impact of neutron-induced ion impact in the neck region of the SiC Power MOSFET. Indeed, the applied reverse bias on the gate will in this specific case enhance the electric field within the oxide layer compared to grounded gate configuration. Such behavior was expected since the electric field in the oxide during ion impact originates from holes accumulated under the gate oxide layer. Therefore, by applying negative voltage at the gate terminal, the difference in electrostatic potential across the oxide layer is increased. The maximum values of electric field transients for each voltage configuration have been plotted in Fig. 11, pointing out that such behavior might be expected whatever the VDS value is applied. However, as will be shown in subsection D2b, the impact of VDS far above the SOA may mask this post irradiation behavior by increasing the probability of SEB during irradiation as was observed in our experimental results.

b) The effect of gate degradation on SEB triggering

First, it has to be reported that TCAD simulations (not presented here) have been performed at the different VDS values and for both VGS configurations, grounded and reverse biased, in order to analyze the influence on overall transient drain current. Though it has been observed that the reverse gate bias was responsible for an increase of the electric field in the channel region close to the source contact due to hole accumulation, TCAD simulations did not allow to report an increase of the drain current with a negative gate voltage. This means that we cannot conclude that the SEB sensitivity is increased by the gate bias on top of the drain voltage. However, it also indicates that due to the location of hole accumulation close to the source region, there might be mutual effects between gate oxide degradation and subsequent SEB triggering. Moreover, such mutual effects are emphasized by the fact that at the irradiation fluence used during experiments, the mean number of n-Si or n-C interactions leading to secondary ions generation in each elementary cell is about 160 considering events of ≥ 100 fC generated charge. Such statistics has been estimated by using MC-ORACLE monte carlo code [START_REF] Wrobel | MC-ORACLE : A tool for predicting Soft Error Rate[END_REF], calculating for the device geometry with a Rectangular Parallelepiped (RPP) approach the overall cross section of the irradiation facility neutron spectrum. Then multiplying the cross section by the fluence has given the number of events in the elementary cell. The critical charge of 100 fC was chosen since in TCAD simulations, it was observed to induce significant increase in gate oxide electric field during the event.

It should be noted though, that compared to our test conditions, in atmospheric environment we should expect lower accumulated fluence during the device lifetime. However, based on the statistics obtained from MC-ORACLE simulation, we should still expect about 15 events per elementary cell in avionic applications.

Moreover, this number does not include neutron interactions generating less than 100 fC of charge, which also might contribute on the gate degradation.

Thus, starting from the observation that the neutron irradiation can induce several interactions in one elementary cell and that each time transient currents are able to be generated, the second part of the TCAD study focuses on the effect of degraded gate oxide on the SEB triggering. Since the degradation and increased gate leakage current does not imply the immediate device failure, we assume that devices which eventually exhibited SEB, could have suffered gate damage prior to SEB. For that purpose, we created a simulation model, in which the gate damage is modeled by replacing a small portion of the gate oxide with SiC material. Based on a recent publication for Si MOSFET [START_REF] Kuboyama | Physical Analysis of Damage Sites Introduced by SEGR in Silicon Vertical Power MOSFETs and Implications for Postirradiation Gate-Stress Test[END_REF], in our case we simulated the damage sites by creating a SiC path through the gate oxide layer just on the top of the source well (Fig. 12) which corresponds to the current behavior observed during PIGS test. With this simulated structure, the impact on SEB triggering of the injected charge through the gate is evaluated. As reported as accurate parameters in previous studies [START_REF] Witulski | Single-Event Burnout Mechanisms in SiC Power MOSFETs[END_REF], [START_REF] Kuboyama | Thermal Runaway in SiC Schottky Barrier Diodes Caused by Heavy Ions[END_REF], simulated currents and impact ionization rates for the two simulation models (with non-degraded oxide and with gate oxide degradation) are respectively presented in Fig. 13 and in Fig. 14. Note that simulations were still performed under such ion energy conditions (reducing from 30 MeV to 20 MeV) that at the given position, no SEB was able to be triggered. Such simulation parameters have been chosen in order to determine if the localized oxide degradation might enhance the SEB triggering sensitivity. In Fig. 13, the global currents at the device terminals have been plotted as a function of time.

Comparing the drain current shapes between VDS = 675 V and VDS = 900 V, we confirm the fact that without any degradation in the oxide (Fresh models), a SEB might be triggered more likely at higher drain voltage. However, looking at the drain current transients at VDS = 675 V for non-degraded oxides (Fresh model) and for degraded oxide model (Degraded model), a 50% increase in the first drain current peak value at t = 1 ps and a 100% increase in the sustained drain current value between 10 ps and 100 ps are observed. Considering then the higher drain bias configuration at VDS = 900 V, the first IDS peak value of the degraded model is still higher compared to the fresh model but the maximum value of the second drain current peak value in the sustained region at t = 1 ns is similar for both models.

Whatever the VDS, one can note that the difference in the drain current values between the two models can originate from the current path through the gate oxide and resulting gate current, as shown in Fig. 13. However, this gate current contribution to the overall drain current takes only place in the very first picoseconds since the gate current recovers after this time dynamic. Looking at what happens in the sustained region, the degraded model shows a significant impact, especially for the lowest drain voltage value (VDS = 675 V). This could indicate that the injected charge in the gate oxide and leading to a localized conductive path in the beginning of the event brings a contribution to the charge enhancement mechanism occurring later. This is confirmed in Fig. 14 where the maximum impact ionization rates at the epitaxial layer/drain (N-/N+) interface are reported. In particular, the difference in impact ionization rates between the fresh and degraded models is much more significant for VDS = 675 V configuration whereas for the VDS = 900 V configuration, the simulated impact ionization rate difference is almost non-existent. From these TCAD simulation results, we have shown that the contribution of the reverse gate bias is significant for bias close to the SOA. Furthermore, we reported that if at high VDS values (far above the SOA limit), the single contribution of the internal drain to source electric field dominates the SEB triggering, this is not the case for lower bias configurations close to the SOA. Indeed, in the experimental section, an enhanced sensitivity to SEB for the reverse gate biased has been reported for the lowest VDS value. We have brought up a physical understanding using a phenomenological conductive path model for the oxide degradation in the TCAD simulation section. Thus, we have concluded that for bias configurations close to the SOA, the reverse gate bias might result in charge injection, contributing to higher drain current transients and higher impact ionization rates, favoring finally the SEB mechanism.

Fig. 2 .

 2 Fig. 2. Weibull plots for different bias voltage configurations during irradiation. Fits are performed with MLE method.

Fig. 1 .

 1 Fig. 1. Test setup schematics. Control instruments were placed in the control room while only the test board containing DUTs was placed under beam in the irradiation chamber.

Fig. 3 .Fig. 4 .Fig. 5 .

 345 Fig. 3. IDSVGS and IGSVGS characteristics of the failed device before and after irradiation. Device was irradiated at VDS = 675 V and VGS = 0 V Both drainsource and gate failures can be observed after irradiation induced failure. IDS reaches the compliance limit of the measurement unit at 1 A.

Fig. 6 .

 6 Fig. 6. Gate current (absolute value) of the survived devices before and after irradiation. Devices were irradiated at VDS = 675 V, VGS = 0 V. 3 of 7 survived devices show increased gate current levels during post-irradiation gate stress.

Fig. 7 .

 7 Fig. 7. SiC MOSFET geometry implemented in TCAD simulation tool ECORCE. Fig. 8. Hole density after the ion impact. Holes are transported and accumulated at the gate oxide surface due to the electric field in the drift layer.

Fig. 9 .

 9 Fig. 9. Simulated electric field before (left) and after (right) the ion impact. Zoom in the gate oxide area with the maximum electric field location is presented in the bottom figure.

Fig. 10 .

 10 Fig.10. Simulated time evolution of electric field in the gate oxide layer during the ion impact for VDS = 675 V bias configuration. The applied reverse gate bias results in higher electric field in the oxide during the charge deposition in the device for an ion impact in the neck region.

Fig. 11 .

 11 Fig. 11. Simulated maximum values of electric field transient in the oxide layer for different irradiation voltage configurations. For each VDS configuration, maximum electric field value is higher when reverse gate bias is applied compared to grounded gate configuration.

Fig. 12 .

 12 Fig. 12. Gate leakage current in TCAD simulation is modeled by replacing a portion of gate oxide with SiC material. Width of the region is 50 nm and ndoping density is 1 × 10 14 cm -3 .

Fig. 13 .

 13 Fig. 13. Simulated time evolution of drain (IDS) and absolute value of gate currents (IGS) during the ion impact for two different irradiation VDS configurations and for original model and model with degraded gate.

Fig. 14 .

 14 Fig. 14. Simulated impact ionization rates (II) during the ion impact for two different irradiation VDS configurations and for two different simulation models.

TABLE I

 I

		EXTRACTED RELIABILITY PARAMETERS FOR EACH IRRADIATION CONFIGURATION BY MLE AND LR METHODS
	VDS (V)	VGS (V)	Survived/ Failed	βMLE	βLR	ηMLE (cm -2 )	ηLR (cm -2 )	MFTFMLE (cm -2 )	MFTFLR (cm -2 )	Stopping fluence (cm -2 )
		0	7/13	1.12	1.26	5.19 × 10 10	4.39 × 10 10	4.99 × 10 10	4.08 × 10 10	5.98 × 10 10
	675	-4	1/19	1.33	1.34	2.49 × 10 10	2.46 × 10 10	2.30 × 10 10	2.26 × 10 10	5.92 × 10 10
		0	1/19	1.12	1.07	4.63 × 10 9	4.59 × 10 9	4.44 × 10 9	4.47 × 10 9	2.41 × 10 10
	765	-4	0/20	1.56	1.46	8.98 × 10 9	9.59 × 10 9	8.36 × 10 9	9.79 × 10 9	2.25 × 10 10
		0	0/20	0.87	0.92	9.06 × 10 8	8.75 × 10 8	9.75 × 10 8	9.11 × 10 8	4.50 × 10 9
	900	-4	0/20	1.07	0.96	6.96 × 10 8	7.11 × 10 8	6.78 × 10 8	7.23 × 10 8	2.35 × 10 9

K. Niskanen, A. D. Touboul, A. Michez, F. Wrobel, J. Boch, and F. Saigné are with IES, Univ Montpellier, CNRS, Montpellier, France (corresponding authors; e-mail: kimmo.niskanen@ies.univ-montp2.fr, antoine.touboul@umontpellier.fr).R.Coq Germanicus is with Normandie Univ, Unicaen, Iut, Ensicaen, CNRS, Crismat, 14000 Caen, France.

ACKNOWLEDGEMENTS

Authors would like to thank Maria Kastriotou and Carlo Cazzaniga from ChipIr facility for their help during the experiments.

IV. CONCLUSION

Gate voltage dependence on failure rate of SiC power MOSFETs under neutron irradiation is investigated. We address in this paper the contribution of the reverse gate bias on the risk of failure, in particular at lower VDS, closer to the safe operating area (SOA) limit. For SEB failed device, failure analysis at wafer level supported by current behavior after the failure event revealed the material failure at the gate/oxide region.

In the meantime, latent gate damages were revealed by postirradiation gate stress on irradiated devices having not suffered a SEB. Increased post-irradiation gate leakage current were observed. Using TCAD simulations, an accumulation of carriers (holes) has been observed in the channel region below the oxide layer and close to the source contact, suggesting some similar mechanisms to the ones involved in SEGR. Such latent damages are expected to be more severe when additional negative gate bias is applied since the hole accumulation below the oxide has been shown to be enhanced with a negative gate bias. Based on the statistics of neutron interactions into a single cell during our experiments obtained using MC-Oracle, Monte Carlo calculation tools, we demonstrated that the applied negative VGS will affect the probability of gate degradation and therefore the SEB failure rate of a last generation SiC device under neutron environment. Such result is particularly to be considered when the device is integrated into a system for example in a switching power converter, where for power yield considerations, a negative gate bias is often used by designers.