Damien Querlioz
email: damien.querlioz@u-psud.fr

Philippe Dollfus

Olivier Bichler

Christian Gamrat

Learning with memristive devices: how should we model their behavior?

Keywords: component, formatting, style, styling, insert (key

This work discusses the modeling of memristive devices, for architectures where they are used as synapses. It is shown that the most common models used in this context do not always accurately reflect the actual behavior of popular devices in pulse regime. We introduce a new behavioral model, intended towards the nanoarchitecture community. It fits the conductance evolution of Univ. Michigan's synaptic memristive devices. A variation of the model fits HP labs's memristors' behavior in the same conditions. Finally, we discuss using a simple example the importance of this type of modeling for learning architectures and how it can impact the behavior of the learning.

INTRODUCTION

In recent years, memristive devices have emerged as a fantastic opportunity for renewal in electronic systems. Memristive devices are a family of two-terminal devices whose resistance evolves according to the bias and currents they experience [START_REF] Strukov | The missing memristor found[END_REF]. Different applications fields have been targeted for such technology. Memory and reprogrammable logic are probably the most direct application of memristive devices and other nanoscale switches [START_REF] Strukov | CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices[END_REF]- [START_REF] Xia | Memristor-CMOS Hybrid Integrated Circuits for Reconfigurable Logic[END_REF]. A reinvention of logic using schemes appropriate to their device physics has also been proposed [START_REF] Borghetti | Memristive' switches enable `stateful' logic operations via material implication[END_REF]. Most current proposals, however, do not exploit the multivalued resistance capability (analog memory) which is a fantastic property of some memristive technology. HP lab's original memristors [START_REF] Strukov | The missing memristor found[END_REF] have this feature. It is present in Univ. Michigan's synaptic devices [START_REF] Jo | Nanoscale Memristor Device as Synapse in Neuromorphic Systems[END_REF], and others [START_REF] Choi | An electrically modifiable synapse array of resistive switching memory[END_REF], [START_REF] Yu | Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory[END_REF]. It has also been reported in memristive three-terminal devices (optically gated carbon nanotube FETs [START_REF] Zhao | Nanotube devices based crossbar architecture: toward neuromorphic computing[END_REF], [START_REF] Liao | Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices[END_REF], nanoparticle organic memory FETs [START_REF] Alibart | An Organic Nanoparticle Transistor Behaving as a Biological Spiking Synapse[END_REF], Palermo organic devices [START_REF] Erokhin | Hybrid electronic device based on polyaniline-polyethyleneoxide junction[END_REF] and UCLA ionic transistors [START_REF] Lai | Ionic/Electronic Hybrid Materials Integrated in a Synaptic Transistor with Signal Processing and Learning Functions[END_REF]).

A currently highly researched approach is to use such memristive devices as synapses for learning [START_REF] Versace | The brain of a new machine[END_REF], since this may be a way to exploit the intermediate resistance states of the devices, with relaxed requirements on the controllability of such states. Various proposals go into that direction. Some use conventional artificial neural networks [START_REF] Lee | Defect-tolerant nanoelectronic pattern classifiers[END_REF], [START_REF] Chabi | Hight fault tolerance in neural crossbar[END_REF], a concept that has been experimentally demonstrated in [START_REF] Liao | Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices[END_REF]. Some use novel approaches inspired directly by Biology (like amoeba learning [START_REF] Pershin | Memristive model of amoeba learning[END_REF]). Finally, a popular idea is to associate memristive devices with spiking neural networks (neural networks that compute with asynchronous spikes, like the brain). It has indeed been suggested [START_REF] Snider | Spike-timing-dependent learning in memristive nanodevices[END_REF], [START_REF] Rez-Carrasco | On neuromorphic spiking architectures for asynchronous STDP memristive systems[END_REF], [START_REF] Querlioz | A memristor-based spiking neural network immune to device variations[END_REF] and shown experimentally [START_REF] Jo | Nanoscale Memristor Device as Synapse in Neuromorphic Systems[END_REF] that memristive devices can implement a learning rule observed in biological synapses (Spike Timing Dependent Plasticity [START_REF] Markram | Regulation of Synaptic Efficacy by Coincidence of Postsynaptic APs and EPSPs[END_REF]). In different contexts, this rule has been shown to have important potential for machine learning [START_REF] Masquelier | Unsupervised Learning of Visual Features through Spike Timing Dependent Plasticity[END_REF], [START_REF] Nessler | STDP enables spiking neurons to detect hidden causes of their inputs[END_REF].

Such research could lead to particularly innovative electronic architectures and develop intelligent and low power electronic systems able to learn and to adapt themselves to their environment. Many explorations are now performed in this direction, both on devices and architectures. A serious difficulty for the "nanoarchitects" working in that field, however, is that the many memristive technologies that exist rely on different physics. Therefore, they can have extremely different behaviors, which can lead to different results if used for learning. To invent the applications of memristive technology, we have to rely on simplified models of devices. Are they sufficient? How do they compare with the actual technology developed in device labs, especially in "learningtype" situations?

In this paper, we review the most popular device models used to develop nano-architectures capable of learning with memristive devices and introduce a new one. We then compare these models with measurements from two popular technologies for use as synapses that rely on different physics: Univ. Michigan's nanoscale synapses [START_REF] Jo | Nanoscale Memristor Device as Synapse in Neuromorphic Systems[END_REF] and HP Labs's TiO 2 memristors [START_REF] Strukov | The missing memristor found[END_REF]. We explore strengths and weaknesses of the models and conclude how we believe memristive devices should be considered for studies involving learning.

II. MEMRISTOR MODELS FOR LEARNING

A. The original linear memristor model (model A)

Different models have been used by nanoarchitects for exploratory studies that aim at taking advantage of multivalued resistance capability of memristive devices. Actually, memristors were introduced by HP Labs using a simple model [START_REF] Strukov | The missing memristor found[END_REF] taking inspiration from Chua's pioneering views on the "fourth passive element", the memristor [START_REF] Chua | Memristor-The missing circuit element[END_REF]. In HP's model, a memristor of thickness D has two layers: one of low linear resistance R ON , and the second (of thickness w) of high resistance R OFF . The device resistance is therefore:

   w R w D R R OFF ON     
This work was supported by the European Union through the FP7 Project NABAB (Contract FP7-216777).

The front between the two regions evolves according to (where µ is the front mobility)

  i D R dt dw ON     which leads to:  R V i dt dR      
(where we have introduced

  D R R R ON ON OFF    
). The resistance is additionally bounded between a minimum and a maximum value ( Using the devices for learning usually involves repeated, short voltage pulses that aim at changing the conductance of the devices only moderately [START_REF] Lee | Defect-tolerant nanoelectronic pattern classifiers[END_REF]- [START_REF] Snider | Spike-timing-dependent learning in memristive nanodevices[END_REF]. Some learning proposals also involved more complex voltage pulses [START_REF] Rez-Carrasco | On neuromorphic spiking architectures for asynchronous STDP memristive systems[END_REF], but understanding the effect of constant voltage pulses is an important step in order to grasp how learning could be done with memristive devices. In addition, we focus primarily on conductance because it corresponds to the synaptic weights in the context of neural networks and thus has more significance than resistance for learning. If the voltage V during such a pulse is constant, the conductance of the device evolves as

 3 3 VG R V dt dG        
This law leads to small conductance steps when conductance is low, and to large conductance steps when conductance is already high. The two top plots of Fig. 1 illustrate how this behaves in situation (the model parameters are listed in Table 1). On the left graph we apply a series of short "potentiating" (i.e. V<0 with the convention used within this paper) identical pulses and plot the conductance of the device after each pulse. The conductance increase starts slowly and accelerates sharply after 70 pulses until conductance reaches the maximum conductance of the device. On the right graph we apply a series of "depressing" (i.e. V>0) pulses. In this case, the conductance decrease starts rapidly and then slows down after 10 pulses. In both cases, the envelope of the curve conductance vs. N is in 1/N 2 (where N is the number of pulses). In this paper, these two series of repeated pulses are the reference experiments to identify how memristive devices behave in a learning situation.

If we plot the device resistance instead of its conductance (top plots of Fig. 2), the same qualitative behavior is seen, but is not as sharp, the resistance steps being in 1/R. The envelope of the curve is in log N. Model parameters are listed in Table I.

B. Threshold model (models B and C)

Though particularly helpful to understand how memristive devices work, the linear memristor model lacks important properties of actual devices. In this model, the time derivative of resistance is proportional to the current. This is not the case for actual devices that are all deeply nonlinear. Most devices even have a threshold voltage below which they experience no or little change [START_REF] Borghetti | Memristive' switches enable `stateful' logic operations via material implication[END_REF], [START_REF] Jo | Nanoscale Memristor Device as Synapse in Neuromorphic Systems[END_REF]. This makes a huge difference for nanoarchitectures since this allows probing the resistance state without changing it, and should be accounted for when designing them. Therefore, other models have been developed that include a threshold effect. We introduce the most commonly used model, for example by Snider [START_REF] Snider | Self-organized computation with unreliable, memristive nanodevices[END_REF], Pershin [START_REF] Pershin | Memristive model of amoeba learning[END_REF] or Linares-Barranco [START_REF] Rez-Carrasco | On neuromorphic spiking architectures for asynchronous STDP memristive systems[END_REF] (model B). The device resistance evolves as:

   V f dt dR   
where f is generally nonlinear, typically a hyperbolic or piecewise linear function, as illustrated on Fig. 3. This leads to (for a constant voltage pulse) On the second line of Fig. 1 and2, we illustrate the behavior of this model in the same test situation used for the linear memristor model. Conductance evolution (Fig. 1) is actually similar: potentiation (left graph) starts slow and accelerates, and depression (right graph) starts rapidly and decelerates. The envelope of the curve is 1/N instead of 1/N² in the linear memristor case. The resistance (Fig. 2) has, however, a distinct and characteristic feature: it is a linear function of pulse number. This should be recognizable immediately on measured devices if they behave consistently with this model.

   V f G dt dG 2    
A variation (model C) is also used by nanoarchitects [START_REF] Chabi | Hight fault tolerance in neural crossbar[END_REF]. It consists of the same model, with conductance instead of resistance:

    V f dt dG    which leads to    V f R dt dR 2    
As illustrated on the third line of Figs. 1 and2, the behavior is identical to model B, but with conductance and resistance inverted. On experimental devices, this behavior should be easily recognizable by the linear behavior of the conductance with pulse number.

C. Asymmetric model (model D)

We finally introduce a new model that we will show to have value in matching with device measurements. Unlike all the other models, the conductance change is asymmetric for potentiation and depression. For negative voltages (leading to increase of the conductance, or potentiation), we model the change of conductance with:

   min max min G G G G e V f dt dG             
The more potentiated it is, the smaller the step. For positive voltages (depression), the expression is similar:

   min max max G G G G e V f dt dG              
For the resistance, this translates to

 dt dG R dt dR 2    
The behavior of this model is illustrated on the last lines of Figs. 1 and2. The conductance (Fig. 1) curves are different from that of the other models. Depression (left graph) starts rapidly and then slows down (in models A and B it starts slowly and accelerates, in model C it is linear). Potentiation also starts rapidly and then slows down (which is similar to models A and B). This asymmetry of potentiation and depression should be easy to recognize in experiments.

Resistance behavior (Fig. 2) is different due to the competition between R² and exponential in the resistance derivative, and may look different depending on the parameters of the model.

III. CONFRONTATION WITH CURRENT TECHNOLOGY

A. Univ. Michigan's nanoscale synapses

We first study devices from [START_REF] Jo | Nanoscale Memristor Device as Synapse in Neuromorphic Systems[END_REF]. They are a variation of the devices introduced in previous works [START_REF] Jo | Programmable Resistance Switching in Nanoscale Two-Terminal Devices[END_REF], [START_REF] Jo | CMOS Compatible Nanoscale Nonvolatile Resistance Switching Memory[END_REF], but specifically targeted toward synaptic operation with continuous variation of the resistance (whereas the original devices had binary resistance, i.e. distinct low and high resistance states). The physics of these devices actually seems close to the original memristor model. Silver is cosputtered with the device thin film material (silicon), on top of a silver-free layer of thin film. An electric field moves the silver atoms giving rise to Agrich and Ag-poor regions, the width of which defining the device conductance (Fig. 4,a). Thus, unlike many resistive memory technologies and the group's previous samples, these devices do not switch by rupturing or reforming filaments (in which case a more binary switching behavior is obtained). Fig. 5 plots (red diamonds) measurements on these devices reproduced from [START_REF] Jo | Nanoscale Memristor Device as Synapse in Neuromorphic Systems[END_REF]. On the left plot, devices were subjected to brief -3.2 V potentiating pulses, and the conductance after each pulse (measured by 1 V read pulses) is plotted. On the right plot the same is done with depressing (2.8 V) pulses. Fig. 6 plots the corresponding resistance data. As seen on Fig 5 conductance can indeed be tuned finely by the short voltage pulses. However, neither the conductance nor the resistance is linear in respect to pulse number. This invalidates both models B and C for this technology. We also notice an extremely asymmetric behavior between potentiation and depression. They both start rapidly and then slow down. This invalidates model A. By contrast model D can fit the measurements (blue line in Fig. 1 and Fig. 2) and thus seems appropriate for architectural studies. More experimental data will be needed however to fit f + (V) and f -(V) for other voltages than those reported in [START_REF] Jo | Nanoscale Memristor Device as Synapse in Neuromorphic Systems[END_REF]. I).

Figure 6. Same as Fig. 5 with resistance. I. HP Labs' TiO 2 memristors were first introduced with a simple physical interpretation [START_REF] Strukov | The missing memristor found[END_REF]. The physical view has largely progressed with subsequent experiments and analysis [START_REF] Strukov | Coupled Ionic and Electronic Transport Model of Thin-Film Semiconductor Memristive Behavior[END_REF], [START_REF] Strukov | Exponential ionic drift: fast switching and low volatility of thin-film memristors[END_REF], [START_REF] Borghetti | Electrical transport and thermometry of electroformed titanium dioxide memristive switches[END_REF]. Comprehensive characteristics of their dynamical behavior at room temperature were introduced in [START_REF] Pickett | Switching dynamics in titanium dioxide memristive devices[END_REF] and are used as a reference in this paper. The devices appear to operate via modulation of tunnel barrier width at the end of a conductive channel that was obtained by electroformation (Fig. 4,b) [START_REF] Pickett | Switching dynamics in titanium dioxide memristive devices[END_REF]. The tunnel width w is the essential state parameter that can be connected to current by the model presented in [START_REF] Simmons | Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film[END_REF] and in the supplementary information of [START_REF] Pickett | Switching dynamics in titanium dioxide memristive devices[END_REF].

B. HP TiO 2 memristors

In [START_REF] Pickett | Switching dynamics in titanium dioxide memristive devices[END_REF], the authors extracted the parameter w as a function of time t after potentiating and depressing voltage pulses. This is plotted on Fig. 7 (left: potentiating, right: depressing). This data was obtained by repeating voltage pulses whose duration was not constant. That is why the graphs are plotted as a function of time and not pulse number, and can still be read similarly to the previous plots of this paper. On Fig. 8, we converted w into a low field conductance using the wellestablished model given in [START_REF] Pickett | Switching dynamics in titanium dioxide memristive devices[END_REF]. Potentiation (left) starts with an extremely abrupt increase of conductance and then becomes a lot slower. Similarly depression (right) starts with an extremely abrupt decrease of conductance, and then becomes a lot slower. Among our models, only model D has this behavior. The initial increase or decrease of conductance is however so abrupt that Fig. 8 cannot be fitted by model D. Without any change, none of our device model is thus appropriate.

Interestingly, however, the evolution of w can be fitted roughly by the equations of model D, with w taking the place of conductance G (full lines of Fig. 7). The fit is not perfect, but can give an acceptable model of device behavior for architectural studies. Alternatively the full model given in [START_REF] Pickett | Switching dynamics in titanium dioxide memristive devices[END_REF] may be used, but is a lot more complex than model D.

The reason for which these devices (unlike Michigan's) cannot be fitted by model D directly seems to be due to the tunneling aspect of transport. If the conductance had a linear dependence on w, model D would work, but the conductance is rather an exponential function of w. This extremely abrupt start of the potentiation and depression would have significant impact if the device is used for learning. We have seen in part II that the different models used for designing learning architectures with memristive devices lead to qualitatively different conductance evolution dynamics when voltage pulses are used to change the conductance (these pulses constituting a baseline at evaluating memristive device modeling for learning architectures). In that regard, a significant difference between the common models (A, B, C) and the new model D is that models A, B, C use symmetric equations for potentiating (V<0) and depressing (V>0) pulses, whereas model D uses asymmetric equations. In particular, for models A and B, this implies that if a device is in low conductance state, potentiating pulses (pulses that increase the conductance) have a small effect and a number of them is required before potentiation becomes efficient. Whereas with model D, for a device with a low conductance, the first potentiating pulses cause the most conductance change, and then potentiation slows down (assuming identical pulses). In part III, we have seen how two popular devices actually behave more like the new model D. Michigan's devices can be fitted by model D. In HP's devices, the state's variable w may be roughly modeled by model D, and the conductance switches abruptly when the device is in a low or high conductance state. Now, how important is it to catch this behavior correctly when developing nanoarchitectures capable of learning? It seems to be significantly, in that the considered memristive device behavior can have significant repercussions on the learning strategy that needs to be put in place. To illustrate this point, we performed a simple computational experiment. We simulated the behavior of the four models for a series of 2000 pulses of either potentiating type (with a probability of P pot ) or depressing type (with a probability of 1 -P pot ). In Fig. 9, we show the evolution of the conductance for each model for different values of the probability P pot (0.8, 0.2, 0.6, and 0.4 successively). It is noteworthy that the mean conductance approximates the probability P pot for the asymmetric model (model D). For the models A and B, the initial increase in conductivity being very slow compared to its initial decrease, the mean conductance stay close to zero for low values of the probability P pot . The model C has a different behavior: since the conductivity change is independent of the current state of the device, the conductivity always tends to increase when P pot > 0.5 and decrease when P pot < 0.5 .The conductance of the device therefore does not stabilize to intermediate values with this simple scheme. This illustrates that the type of learning will be different depending on the model used. In model A and B, low conductance states are extremely stable. In model C, the memristive device is naturally led to low or high conductance states that are more stable. In model D, depending on the model parameters, any intermediate resistance can be stable. Of course, the simple computational experiment presented above does not preclude the learning of stable arbitrary conductance states with devices best modeled by models A, B or C. It suggests, however, that the commonly used models that may look similar will give very different results regarding the final state of learning.

IV. DISCUSSION

V. CONCLUSION

In this work, we first saw that the equations (linear memristor A, and threshold models B and C) commonly used to model the conductance change of memristive device in nanoarchitectures lead to significantly different behaviors when used with short voltage pulses. Such pulses are fundamental for nanoarchitectures involving learning. We then presented two memristive technologies targeted towards learning, and saw that their behavior matched none of these common models. For both devices, potentiation (the process that increases the conductance of the memristors) and depression (the processes that decreases it) are extremely asymmetric, which none of the three models captures. The new model that we introduced (asymmetric model D) corrects this issue and fits measurements on Univ. Michigan's synaptic devices directly, and after an adaptation measurements on HP Labs' original memristors. Finally, we pointed with a simple simulation that using one or the other of the models will change the stability of the memristors' states in a learning situation. All this suggests that existing memristors' models should be used with caution when developing this kind of architectures.

Figure 1 .

 1 Figure 1. Conductance vs pulse number for a serie of "potentiating" (V=-1V) voltage pulses (left) and depressive (V=+1V) pulses (right) with the four devices models (pulse durations: 1 ms). From top to bottom: linear memristor (model A), threshold models (models B and C), asymmetric model (model D).Model parameters are listed in TableI.

Figure 2 .

 2 Figure 2. Same as Fig 1 with resistance plotted instead of conductance.

Figure 3 .

 3 Figure 3. Examples of typically used f functions for equations (5) to (11), to model the nonlinearity of resistance change depending on the voltage applied across the device.

Figure 4 .

 4 Figure 4. Schematization of the two kind of devices considered . a) Univ Michigan nanoscale synapses. The position of the front between Ag-rich and Ag-poor regions determines conductance, b) HP Labs' TiO2 memristors.Conductance is determined by the thickness of a barrier at the end of an electroformed conductive channel.

Figure 5 .

 5 Figure 5. Evolution of the conductance for the devices from Michigan, fitted with the model D. Left: device conductance (measured at 1 V) after each pulse in a serie of potentiating (V=-3.2V) pulses. Right: same with depressing (V=2.8V) pulses. Diamond: experimental data, reproduced from [11]. Full line: Model D (parameters listed in TableI).

Figure 7 .

 7 Figure 7. Tunneling gap width w as a function of time in a serie of potentitation (left) or depressing (right) pulses on HP memristors (symbols: experimental data from [33], full line: Model D), for different pulse voltages (left: -1.4 and -1.25 V; right: 4, 3.5 and 3 V). Insets show details of the figure for short times. Model D parameters are listed in TableI.

Figure 8 .

 8 Figure 8. Low field conductance computed from tunneling gap width w from Fig 7 in the same conditions. For depressing pulse, conductance is shown in a log scale because of its abrupt change. The insets (details for short time) are both in linear scale.

Figure 9 .

 9 Figure 9. Conductance as a function of the potentiating / depressing pulses ratio for the four models described above. From top-left to bottom-right: linear memristor (model A, top, left), threshold models (models B, top, right, and C,bottom, left) and asymmetric model (model D, bottom, right). The dashed red curve is the probability Ppot of the pulse to be a potentiating pulse and the blue curve is a moving average of the conductance of the device.

Fig. 5 , 6 Fig. 7 Potentation:

 567 Figure Model parameters Fig. 1, 2 model A 1.25.10 12 ²/V/ms Fig. 1, 2 model B f(1V)=-f(-1V)=0.85 M/ms Fig. 1, 2 model C f(1V)=-f(-1V)=12.5 nS/ms Fig. 1, 2 model D

TABLE I .

 I MODEL PARAMETERS USED IN THIS PAPER

ACKNOWLEDGMENTS

We would like to thank D. Chabi, J.-O. Klein, W. Zhao, J. Saint-Martin and V. Derycke.


Jérôme Saint-Martin
email: jerome.saint-martin@ief.u-psud.fr

Damien Querlioz

Arnaud Bournel

Philippe Dollfus

Efficient multi sub-band Monte Carlo simulation of nano-scaled Double Gate MOSFETs

Keywords: MOSFET, Multi sub-band, Monte Carlo, Double gate, Ballistic transport, 2D Electron Gaz

An efficient two-dimensional self-consistent Monte-Carlo simulator including multi sub-band transport in a 2D electron gas is described. This simulator takes into account both out of equilibrium transport and quantization effects. A new algorithm improves significantly computation time and allows us to study the sub-threshold behavior of deep sub-100 nm CMOS devices. We analyze quantization effects in a 15 nm-long DGMOS transistor.

INTRODUCTION

Double gate (DG) structure are promising architectures to overcome short channel effects in nanometer scaled MOSFETs. To obtain good performance in both the off and on states, DG scaling requires ultra-thin body thickness T Si , typically less than 10 nm for sub 50 nm MOSFETs [START_REF] Saint-Martin | Comparison of multiplegate MOSFET architectures using Monte Carlo simulation[END_REF]. Consequently, quantum confinement in the direction perpendicular to the gate stacks may affect the operation of these devices. Moreover, in ultra-short devices the quasiballistic transport strongly affect device performance [START_REF] Saint-Martin | On the ballistic transport in nanometer-scaled DG MOSFET[END_REF]. In this context, Monte Carlo (MC) simulation with multi sub-band description is required to properly describe both the quantum vertical confinement in the channel together with accurate scattering and out-of equilibrium effects. However this kind of simulation induces a dramatic increase of computation time, in comparison with traditional semi-classical MC simulation.

We present a new approach for reasonably fast and stable simulation of these devices without loss of accuracy, using a perturbative approach to solving the Schrödinger equation. In particular, this approach makes possible to investigate the subthreshold behavior of transistors within an acceptable computation time.

The first part of the paper is devoted to the presentation of our original multi-sub-band algorithm. Then, we present the acceleration technique. In the last part we analyze the performance of a typical double gate structure, focusing on the sub threshold behavior.

I. REFERENCE ALGORITHM

Our model is inspired by the mode-space approach of quantum transport [START_REF] Venugopal | Simulating quantum transport in nanoscale MOSFETs: Real vs. mode space approaches[END_REF] and extends the technique developed in ref. [START_REF] Fischetti | Monte Carlo study of electron transport in silicon inversion layers[END_REF]. It is self consistently coupled with 1D Schrödinger's equation and 2D Poisson's equation (cf. Each time step begins with the solution of the 1D Schrödinger equation along the z-axis perpendicular to gate stacks in each x 0 -slice of the DG. This provides the evolution along the source-drain x-axis of the eigen energies E n (x 0 ) and of the wavefunctions ξ n (x 0 ,z) associated with each sub-band numbered 'n'.

Along the Source/Drain x-axis, the confined carrier movement is supposed semi classical, and the Boltzmann transport equation is solved using a MC technique. According to the mode-space approach, the driving field undergone by a Scattering mechanisms included in the MC transport simulation are bulk phonons, roughness scattering and impurity scattering, taking non parabolic and ellipsoidal band structures into account. The acoustic and intervalley phonon scattering rate calculations are detailed in Ref. [START_REF] Monsef | Electron transport in Si/SiGe modulation-doped heterostructures using Monte Carlo simulation[END_REF]. The considered phonons and related coupling constants used for the multi subband, or 2Dk, calculations are the same than that considered in semi-classical, or 3Dk, simulation. The surface roughness effect is calculated by considering both influences of electrostatic potential along z [START_REF] Goodnick | Surface roughness at the Si(100)-SiO 2 interface[END_REF] and of eigen energies fluctuations [START_REF] Sakaki | Interface roughness scattering in GaAs/AlAs quantum wells[END_REF]. The 2D scattering rates are updated regularly according to the new wave-functions resulting from the Schrödinger equation.

This transport algorithm provides the number of electrons present in each sub-band of the "Schrödinger" x 0 -slice at the end of the time step. The electron density is calculated by distributing the charge of each electron along its x 0 -slice according to the appropriate probability density |ξ n (x 0 ,z)| 2 .

Finally, the 2D Poisson equation is solved by using the electron density n(x,z) derived from the sum of the charge contribution of each particle present in a x 0 -slice of the device The previous multi sub-band simulator makes possible detailed investigation of vertical confinement in nanoscale devices. It is however about 50 times slower than the corresponding classical simulations.

II. EFFICIENT ALGORITHM

In order to make the simulator practical, it is important to improve its computation speed. In these simulations, it is essential to solve the Poisson equation and to calculate the associated Schrödinger eigenvalues E n (x) every time step, in order to update the driving field according to the electron density. However, solving the Schrödinger equation every step costs a lot of computation time. That is why, in order to drastically accelerate the method, the Schrödinger equation is solved only every N steps in our approach. Every other step, the eigenenergies E n (x) are updated using a perturbative approach at the first order:

) z , x ( ) z , x ( V . q ) z , x ( ) x ( E ) x ( E 0 i n 0 0 i n 0 i n 0 n ξ ∆ - ξ + = (1)
where ∆V(x,z) refers to the difference between the updated electrostatic potential and that used for the last 'i' th Schrödinger solution. We found no need to correct the wavefunctions which are only updated every N steps.

It should be mentioned that we have finally chosen to solve the Schrödinger equation every 100 th time step. So, the part Schrödinger equation computation becomes negligible in the total computation-time compared to Poisson, scattering rates and transport calculations. If the frequency of the Schrödinger calculation is further more diminished, the expected reduction of the computation time will be small, and some instability may appear in the algorithm...

III. RESULTS

The simulated DGMOS has a gate length L G equal to L ch = 15 nm (cf. In this work, we consider the 6 ellipsoidal ∆ valleys of silicon conduction band. The "primed" valleys correspond to the valleys which have a transverse mass m t along the confinement direction. The "unprimed" valleys refer to the valleys with a longitudinal mass m l along the confinement direction. The self-consistent sub-band profile obtained for V GS = V DS = V DD = 0.7 V is shown in Figure 3. As expected, the heaviest valleys in the confinement direction have the lowest quantized energies and the first primed sub-band has a higher energy: E 1 ' > E 2 > E 1 . Nevertheless, first primed subbands (E 1 ') are very close to the second unprimed sub-bands (E 2 ) all along the device. It should be noted that the modespace approach is a very good approximation for this ultra-thin double gate structure symmetrically biased. Indeed, the coupling potentials between sub-bands, calculated as in Ref. [START_REF] Sverdlov | Quantum transport in ultra-scaled double-gate MOSFETs: A Wigner functionbased Monte Carlo approach[END_REF], are negligible for this geometry since the wave functions x (nm) z (nm) (cm -3 ) do not evolve strongly along the source-drain axis, as illustrated in the inset of Figure 3. At V GS = V DS = V DD = 0.7 V, i.e. for the most critical case, the perturbative coupling potentials remain smaller than 0.5 meV which is lower than all energies involved (not shown). The use of a perturbative solution of the Schrödinger equation makes the method drastically faster than in our previous work [START_REF] Goodnick | Surface roughness at the Si(100)-SiO 2 interface[END_REF]. For results discussed below, equilibrium is obtained 15 times faster when solving Schrödinger's equation every 100 steps than when solving it every time step. Convergence is obtained without any loss of accuracy and no detectable difference in the results is seen. It should be noted that semi-classical simulation is still 3 times faster than the accelerated multi sub-band approach. Combined with a particle multiplication technique to enhance the statistics of rare events, this improved multi-subband simulation approach makes possible the investigation of sub-threshold regime in a reasonable calculation time, which is known to be difficult in any particle Monte Carlo simulation. This improvement allows us to study the evolution of the total charge in the device and the gate capacitance as a function of the gate voltage as shown in Figure 5. and in the corresponding inset.

The gate control is softly degraded by the confinement effects in this 3 nm thick device. Indeed, the gate capacitance is reduced compared to classical simulation, which results from the dark space at Si/SiO 2 interfaces pointed out in Figure 4.

The electrical characteristics at low drain voltage are presented in Figure 6. The confinement effects induce a 51 mV increase of the threshold voltage V T . In spite of the decrease of the gate capacitance observed previously, the sub-threshold slope remains excellent about 63 mV/dec. in both 2Dk and 3Dk simulations. Indeed in this well designed device with a high enough form factor L ch /T Si equal to 5, short channel effects are successfully controlled. The I D -V GS characteristics in the above threshold are shown in Figure 7. The predominant effect which limits the current for V GS higher than 0.6 V appears to be the total series resistances (about 170 µΩ.m). Finally, we have calculated the number of scattering events N scatt experienced by each carrier crossing the channel from source-end to drain-end. The resulting scattering spectra are plotted at low V DS and high V GS in Figure 8. as a function of N scatt . Then, the fraction of ballistic electrons B int reaches 47% for the 3Dk simulation but decreases to 28% in the 2Dk case. Indeed, the roughness scattering (with ∆ = 0.5 nm and Λ = 1.5 nm) induces a higher spreading of the spectrum in the 2Dk case because of high fluctuations of energy levels [START_REF] Sakaki | Interface roughness scattering in GaAs/AlAs quantum wells[END_REF]. So, even if the ballisticity is high in this device the scattering mechanisms are far from being negligible.

CONCLUSION AND PERPECTIVES

We have developed a multi sub-band MC simulator for n-MOS transistors that extends the quantum confinement calculation to the whole device region. It also uses a simple and effective self-consistent iterative method that gives meaningful results with good convergence. This improved algorithm gives a more accurate description of density profile and carrier transport than semi-classical or quantum corrected MC simulation, with a reasonable increase of computation time. In particular, this approach makes possible the study of the subthreshold behavior of transistors.

Additionally, the accelerated multi sub-band approach make possible the coupling to a quantum 1D Wigner transport approach [START_REF] Querlioz | An Improved Wigner Monte-Carlo Technique for the self-consistent Simulation of RTDs[END_REF] in order to investigate the sub 10 nm-long channel in which the quantum transport in the Source/Drain direction is predominant. This work is under development.

Fig 1 and

 1 Fig 2).

Figure 1 .

 1 Figure 1. Schematic of DGMOS structure.

Figure 2 .

 2 Figure 2. Multi sub-band Monte-Carlo algorithm.

Figure 1 . 1 Figure 3 .Figure 4 .

 1134 Figure 3. Quantized energy evolutions along x axis. Inset: 2D cartography of square wave-function of the first sub-band. Unprimed and primed sub-bands have a quantization mass of 0.916 m0 and 0.19 m0, respectively

Figure 4 .

 4 Figure 4. indicates clearly that electrons are moved away from the Si/SiO 2 interface due to quantum repulsion in the whole structure, even in the source and drain regions.

Figure 5 .

 5 Figure 5. Charge vs. gate voltage characteristic at low V DS obtained using semi classical MC simulation (triangles: 3Dk) and multi sub-band MC simulation (circles: 2Dk). Inset: Gate capacitance vs. gate voltage at low V DS

Figure 6 .Figure 7 .

 67 Figure 6. I D (V GS ) characteristic at low V DS obtained using semi classical MC simulation (3Dk) and multi sub-band MC simulation (2Dk).

Figure 8 .

 8 Figure 8. Fraction of electrons vs. the number of scattering events undergone at low V DS and high V GS during the channel crossing (2Dk).


Manan Suri

Daniele Garbin

Olivier Bichler

Damien Querlioz

Dominique Vuillaume

Christian Gamrat

Barbara Desalvo

Impact of PCM Resistance-Drift in Neuromorphic Systems and Drift-Mitigation Strategy

Neuromorphic architectures that exploit emerging resistive memory devices as synapses are currently receiving a lot of interest. Phase Change Memory (PCM), in particular, is a strong candidate for such architectures. However, it suffers from a resistance-drift effect in the amorphous phase (high-resistance). In this work, we investigate the impact of resistance-drift in 'Learning-' and 'Read-' mode operation of large-scale hybrid neuromorphic architectures that use bio-inspired 'STDP-type' learning rules. We show that our '2-PCM Synapse' approach is inherently tolerant to resistance-drift. We also present a new architecture ('Binary-PCM Synapse') and programming strategy based on partial-reset states of PCM devices, which strongly minimizes the impact of resistance-drift. To benchmark the two programming approaches and architectures, we perform systemlevel simulations on a complex visual pattern extraction application. A power consumption analysis for the two approaches is finally presented. It highlights the ultra low-power potential of PCM-based neuromorphic computing.

I. INTRODUCTION

Interest in the field of bio-inspired computational hardware has increased dramatically over the last few years. Several research groups [START_REF] Merolla | A digital neurosynaptic core using embedded crossbar memory with 45pj per spike in 45nm[END_REF], [START_REF] Sharad | Spin-based neuron model with domain-wall magnets as synapse[END_REF], [START_REF] Snider | Spike-timing-dependent learning in memristive nanodevices[END_REF], [START_REF] Suri | CBRAM Devices as Binary Synapses for Low-Power Stochastic Neuromorphic Systems: Auditory (Cochlea) and Visual (Retina) Cognitive Processing Applications[END_REF] are actively exploring neuromorphic hardware due to its promising advantages such as low-power, high defect/variability-tolerance, and efficient handling of large scale non-linear computations. Among the different implementations of neuromorphic hardware, of particular interest are the ones that exploit hybrid architectures: CMOS + emerging resistive memory (RRAM). In these hybrid Fig. 1. Resistance drift with time for different initial programming conditions. Measurement was carried out on GST PCM devices. Equation governing the drift dynamics is also shown.

architectures, the neuronal functionality is implemented by using standard CMOS circuits while the synaptic functionality is implemented through densely integrated arrays or crossbars of RRAM technologies. These RRAM technologies may include devices such as phase change memory (PCM) [START_REF] Kuzum | Energy Efficient Programming of Nanoelectronic Synaptic Devices for Large-Scale Implementation of Associative and Temporal Sequence Learning[END_REF], [START_REF] Suri | Phase Change Memory as Synapse for Ultra-Dense Neuromorphic Systems: Application to Complex Visual Pattern Extraction[END_REF] conductive-bridge (CBRAM) or programmablemetallization cell (PMC) [START_REF] Suri | CBRAM Devices as Binary Synapses for Low-Power Stochastic Neuromorphic Systems: Auditory (Cochlea) and Visual (Retina) Cognitive Processing Applications[END_REF], [START_REF] Yu | Modeling the switching dynamics of programmable-metallization-cell (PMC) memory and its application as synapse device for a neuromorphic computation system[END_REF] and oxide based resistive memory (OXRAM) [START_REF] Yu | A Neuromorphic Visual System Using RRAM Synaptic Devices with Sub-pJ Energy and Tolerance to Variability: Experimental Characterization and Large-Scale Modeling[END_REF], [START_REF] Park | RRAM-based Synapse for Neuromorphic System with Pattern Recognition Function[END_REF], [START_REF] Strukov | Hybrid cmos/memristor circuits[END_REF]. Owing to their compact size, resistive-memory devices help in achieving a high synaptic density which is not possible with pure CMOS-synapse circuits, as a large number of transistors are required (>10) per synapse [START_REF] Mitra | A VLSI spike-driven dynamic synapse which learns only when necessary[END_REF]. RRAM also provides the much needed nonvolatility to the neuromorphic system.

Here, we focus on hybrid neuromorphic architectures that use PCM devices as synapses. PCM devices consist of an active chalcogenide layer sandwiched between two metal electrodes. The working principle exploits reversible and nonvolatile phase-change phenomena inside chalcogenide layers such as Ge 2 Sb 2 Te 5 (GST). Phase-change is obtained through joule-heating, when electrical bias or pulses are applied. PCM devices can be programmed to a high-resistance (or reset) state by creating a resistive amorphous region inside the chalcogenide layer. Heating the chalcogenide layer above its melting temperature and then quickly quenching it gives rise to formation of amorphous region. A low-resistance (or set) state can be obtained by creating crystalline regions in the chalcogenide layer. Crystallization occurs when the chalcogenide layer is heated at its crystallization temperature for sufficient duration. Intermediate resistance states can also be obtained by carefully tuning the programming conditions (i.e pulse-width and amplitude) [START_REF] Wong | Phase change memory[END_REF]. These properties have led to proposed use of PCM devices for mimicking synaptic-plasticity effects such as potentiation (LTP-like) [START_REF] Suri | Phase change memory for synaptic plasticity application in neuromorphic systems[END_REF], depression (LTD-like) and bioinspired learning rules like spike-timing dependent plasticity (STDP). In previous works [START_REF] Suri | Phase Change Memory as Synapse for Ultra-Dense Neuromorphic Systems: Application to Complex Visual Pattern Extraction[END_REF], we presented a novel lowpower PCM based neuromorphic architecture called the '2-PCM Synapse'. Using our architecture we demonstrated a twolayer spiking neural network (SNN) capable of complex visual pattern extraction. However, in PCM devices, the amorphous or highresistance states are not entirely stable. Melt-quenched amorphous regions created inside the chalcogenide layer undergo structural relaxations and the resistance of PCM device tends to increase with time (known as resistance-drift). The resistancedrift follows an empirical exponential rule which depends upon the initial programmed resistance and a parameter known as the drift coefficient (ν) [START_REF] Ielmini | Physical interpretation, modeling and impact on phase change memory (pcm) reliability of resistance drift due to chalcogenide structural relaxation[END_REF]. The crystalline or low-resistance states of PCM are shown to be free from resistance-drift [START_REF] Papandreou | Drift-tolerant multilevel phase-change memory[END_REF]. Fig. 1 shows the resistance-drift measured in our GST-PCM devices and the equation governing the drift dynamics. The devices were programmed in two different initial (reset) states and the resistance was read at different time intervals. Inside a neural network such resistance-drift may cause undesired change of trained synaptic weights.

In this paper, we discuss how our '2-PCM Synapse' architecture is inherently tolerant to PCM resistance-drift. We also introduce a new 'Binary-PCM Synapse' architecture with a stochastic STDP learning rule. We show that by carefully defining the reset state (partial-reset) in the 'Binary-PCM Synapse' architecture the effects of drift can be mitigated even further. Section II describes the two different PCM based architectures and programming schemes. Section III, discusses the visual pattern extraction simulations, the impact of drift, and overall system performance.

II. PCM BASED SYNAPTIC ARCHITECTURES

A. The '2-PCM Synapse'

Our main motivation for developing the '2-PCM Synapse' architecture was to emulate synaptic behavior (i.e. gradual synaptic-potentiation and -depression) using identical neuron spikes (Fig. 2) [START_REF] Suri | Phase Change Memory as Synapse for Ultra-Dense Neuromorphic Systems: Application to Complex Visual Pattern Extraction[END_REF]. In this approach, we use two PCM devices to implement a single synapse and connect them in a complementary configuration to the post-synaptic output neuron. One of the PCM device implements synaptic potentiation (LTP-device), while the other implements synaptic depression (LTD-device). Both devices are initialized to a high resistive amorphous state. When synaptic potentiation is required, the LTP device is crystallized, while when synaptic depression is required, the LTD device is crystallized. Fig. 3 shows the characteristic resistance evolution of our GST-PCM devices with gradual crystallization events. The detailed programming schemes and the simplified STDP learning rule used are described in [START_REF] Suri | Phase Change Memory as Synapse for Ultra-Dense Neuromorphic Systems: Application to Complex Visual Pattern Extraction[END_REF]. Note that as the neural network undergoes learning, with time the PCM devices become more and more crystallized and finally saturate to a minimum resistance value. In order to enable continuous learning of the network, we defined a refresh-sequence, explained in detail in [START_REF] Bichler | Visual pattern extraction using energy-efficient 2-pcm synapse neuromorphic architecture[END_REF]. In this Experimental LTP curve for pulse width of 300ns. Inset shows 100 different simulated LTP curves with a 20% standard deviation variability included on all synaptic parameters described in equation 3 of [START_REF] Suri | Phase Change Memory as Synapse for Ultra-Dense Neuromorphic Systems: Application to Complex Visual Pattern Extraction[END_REF]. refresh-sequence, the saturated PCM devices are amorphized (reset) and the effective weights of the corresponding synapses are re-programmed.

B. 'Binary-PCM Synapse' and Partial-Reset

Alternatively, we propose for the first time, to use PCM devices as binary synapses but with a stochastic-STDP rule, similar to the one we developed for bipolar CBRAM devices [START_REF] Suri | CBRAM Devices as Binary Synapses for Low-Power Stochastic Neuromorphic Systems: Auditory (Cochlea) and Visual (Retina) Cognitive Processing Applications[END_REF]. In this approach, there will be 1-PCM device per synapse. Two resistance states (or weights) can be defined for the PCM synapse. The high-resistance state should be chosen such that it is a partial-reset (Fig. 4) state. The partial-reset state should lie in the negligible or low-driftable region. For GST based devices a resistance value < 50 kΩ will lie in low or negligible drift regime [START_REF] Papandreou | Drift-tolerant multilevel phase-change memory[END_REF], [START_REF] Ielmini | Physical interpretation, modeling and impact on phase change memory (pcm) reliability of resistance drift due to chalcogenide structural relaxation[END_REF]. Fig. 5 shows an example of our stochastic-STDP rule. The y-axis represents a probability to switch from the set-to-reset or reset-to-set states for the PCM synapses. Fig. 6 shows the architecture and the programming scheme required to implement the stochastic learning with binary PCM synapses.

The stochasticity is controlled by an extrinsic PRNG (pseudo-random number generator) circuit. The PRNG circuit controls the probability of LTP and LTD with a 2-bit signal. Initially, the input neurons (A-D) generate small read pulses when they encounter any stimuli event. The read current is integrated in the output neurons A' and B'. When the output neuron reaches its firing threshold it generates a feedback signal(3) and a post-spike signal. In the example shown in Fig. 6 output neuron A' fires and B' doesn't fire. The signal(3) activates the gates of all the select transistors on the synaptic line connected to A'. If LTP is to be implemented the Input neuron will send a signal(1), as shown for Input neuron A in this example. In the case of LTD the input neuron will send a signal(2), as shown for the input neuron D. The probabilities of LTP/LTD can be tuned according to the learning rule (Fig. 5).

III. RESULTS AND DISCUSSION

In this section, we benchmark impact of drift on the two different architectures discussed in the previous section, by simulating a large-scale real world pattern extraction application. We used our custom built XNET SNN simulator [START_REF] Bichler | Unsupervised features extraction from asynchronous silicon retina through Spike-Timing-Dependent Plasticity[END_REF] to simulate a complex visual pattern application. Our 2-layer SNN with 70 neurons and about 2 million PCM synapses is shown in Fig. 7. AER video of cars passing on a freeway was recorded using a special DVS-Sensor [START_REF] Lichtsteiner | A 128 x 128 120 dB 15 µs Latency Asynchronous Temporal Contrast Vision Sensor[END_REF] and used as the input data for our SNN. During the learning, the neurons were able to extract patterns (car-shapes) in different lanes (different positions and orientations) in a fully unsupervised manner. The detailed learning mechanism of the network is described in [START_REF] Bichler | Extraction of temporally correlated features from dynamic vision sensors with spike-timing-dependent plasticity[END_REF]. Table. I and Table. II summarize the SNN performance and detection rates for all the simulations performed for this paper.

A. Drift Impact

In order to study the impact of PCM resistance-drift in our network we first classify its operation in two different modes: (a) Learning-mode and (b) Read-mode. In learning mode the synaptic programming is enabled and the network is trained using various datasets or stimuli. It is only during this mode that the synaptic weights can be changed. For the '2-PCM Synapse' architecture, in the learning-mode, the PCM are typically not experiencing drift. Only, whenever a refreshsequence is applied to a synapse, it pushes the respective PCM devices into the driftable region. In the refresh-sequence, both devices are reset and one of them is reprogrammed to a lower resistance state. For the device which stays in the fully reset state, drift is irrelevant: the more reset it is, the better. The other device, which is reprogrammed to a high resistance but intermediate state, may experience drift until it encounters sufficient crystallizing events (LTP or LTD) that push it in the non-driftable region. Such drift can delay learning, and its occurrence can be attributed to the refresh-frequency. More precisely, the drift in learning will be a consequence of the on-going competition between the refresh-frequency and the set-frequency.

Set-frequency depends on (1) nature of the learning rule and (2) nature of the stimuli used for training, while the refresh-frequency mainly depends on the type of chalcogenide material used. A chalcogenide material which crystallizes slowly and offers more intermediate resistance states before saturation will require less frequent refresh. In previous works we showed that growth dominated materials like GeTe have almost double the refresh-frequency compared to nucleation dominated material such as GST [START_REF] Suri | Physical aspects of low power synapses based on phase change memory devices[END_REF]. While interface engineering (GST+HfO 2 ) can further improve the number of intermediate resistance states thus decreasing the refresh frequency [START_REF] Suri | Interface engineering of pcm for improved synaptic performance in neuromorphic systems[END_REF]. From Table. I, we can see that for the '2-PCM Synapse', the ratio of set-frequency (/device/s) to resetfrequency (/device/s) is about 25. In the case of interface engineered devices [START_REF] Suri | Interface engineering of pcm for improved synaptic performance in neuromorphic systems[END_REF] this ratio further increases to a value of 55.

Drift is more dramatic in the case of the read-mode compared to learning mode, since the system has no means to compensate for it through learning. In the read-mode, synaptic programming is disabled and a pre-trained neural network is used to identify patterns in new datasets or stimuli without changing the synaptic weights. Thus impact of resistance-drift in the read-mode is proportional to the final weight distribution of the synapses at the end of the training, and the time interval after which the network is operated in read-mode post training.

Synaptic weight distribution at the end of learning mode gives the number of synapses that are left in the highresistance or driftable state. An inherent advantage of the '2-PCM Synapse' approach, compared to the methodology used in [START_REF] Kuzum | Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing[END_REF], is that we implement both potentiation and depression by crystallization. Thus the majority of PCM devices at the end of the learning are programmed in low resistance or nondriftable states. This is irrespective of the fact that we use a pre-dominantly depression (LTD) based learning rule. As crystalline or low resistance states are more stable and immune to the resistance drift [START_REF] Ielmini | Physical interpretation, modeling and impact on phase change memory (pcm) reliability of resistance drift due to chalcogenide structural relaxation[END_REF], [START_REF] Papandreou | Drift-tolerant multilevel phase-change memory[END_REF], [START_REF] Papandreou | Programming algorithms for multilevel phase-change memory[END_REF] the '2-PCM Synapse' diminishes the loss of synaptic information in the read-mode. Fig. 8, shows the final synaptic resistance (weights) distribution at the end of the cars learning simulation. About 60% of the devices are in the non-driftable region. The strong reduction in percentage of devices in driftable region is more evident from Table . I. We can see that the number of set events is about ten times greater than number of reset events for the '2-PCM Synapse' as LTD is also implemented by set or crystallization.

In the case of 'Binary-PCM Synapse' architecture the impact of drift in learning-mode can be fully mitigated if the reset state of the PCM devices is tuned carefully to a partialreset state (negligible drift region). Fig. 9 shows the final synaptic resistance distribution at the end of learning when the simulation was performed for the 'Binary-PCM Synapse' architecture with stochastic learning. In this simulation the mean reset state was defined as 20 kΩ, which lies in the nondriftable region. At the end of the learning, about 97% of the synapses are in the reset state. This is due to the strongly LTD dominant nature of our learning rule (Fig. 5). Even though majority of the synapses are in reset state, they will not drift as they lie in the non-driftable region.

We performed the cars-learning simulations for the 'Binary-PCM Synapse' architecture with 3 different PCM reset resistance states, keeping the set state constant: (1) negligible drift region (mean Roff = 20 kΩ), (2) Low drift region (mean Roff = 30 kΩ), and (3) high drift region (mean Roff > 100

B. Overall System Performance

Fig. 12 shows the final neuron sensitivity maps for the 6-lanes at the end of cars-learning simulation for the case of '2-PCM Synapse' and 'Binary-PCM Synapse' (20 kΩ) architectures. Table . 2 gives the exact value of detection rate for each individual lane. Lanes 1 and 6 were classified as not-learnt as their detection rates were < 85%. The average detection rate was 91% for the '2-PCM Synapse' and 95% for the 'Binary-PCM Synapse'. Obtaining a high detection rate with an unsupervised system is a strong accomplishment from a machine learning point of view. It is also interesting that the binary synapses performed better. Binary synapses appear especially fit to process this kind of highly dynamic video data.

From Table . 1 we can see that, as we move from the '2-PCM Synapse' architecture to the 'Binary-PCM Synapse', the number of read-events becomes half as the number of PCM devices is also halved. However the read frequency/device/s stays constant. The read-frequency stays constant as it depends on the nature of stimuli used to train the network. In the case of 'Binary-PCM Synapse' the set and reset events are a direct representative of the number of LTP and LTD events. However in the case of '2-PCM Synapse' the reset events represent the number of refresh-sequences while the set events denote both LTP and LTD.

To estimate the energy consumption by the PCM devices during the learning process, we use the following equations (CMOS or neuron power consumption is not included): E set/reset = V set/reset ×I set/reset ×t pulse E total = (E set ×total set events) + (E reset ×total reset events) Power synaptic learning = E total /Duration learning The total duration of learning for all the simulations is fixed (680 s). The energy consumption decreases in the case of 'Binary-PCM Synapse' as the current required to program partial-reset states (20 kΩ and 30 kΩ) is much less compared to the current required to program a strong reset state (128 kΩ). However the energy consumption doesn't decrease drastically as the number of reset-events increases in the 'Binary-PCM Synapse' architecture. In both cases (Roff:20 kΩ, 30 kΩ ), the power consumption by the PCM devices during learning remains low (<80 µW). Additionally, use of aggressively scaled PCM devices may futher decrease the power to a few nanowatts [START_REF] Suri | Phase Change Memory as Synapse for Ultra-Dense Neuromorphic Systems: Application to Complex Visual Pattern Extraction[END_REF]. During read, the devices are not programmed anymore and their power consumption is much smaller (about 75 nW). The total read energy and power dissipation for all the cases is provided in Table .1. Read-energy is estimated using the following equation:

E read = Σ (V read ) 2 • T read R i
where, R i is the instantaneous resistance value of a specific PCM device that received the 'ith' read-pulse. The R i values are recorded in real time using the XNET simulator.

IV. CONCLUSION

In this paper, we show how our '2-PCM Synapse' architecture is inherently tolerant to the impact of PCM resistancedrift. We show that the synaptic weight distribution postlearning are concentrated more in the non-driftable region, as in our approach even LTD is obtained by crystallization. We introduce, for the first time, a new architecture 'Binary-PCM Synapse' with stochastic STDP learning rule and partial-reset states. The programming methodology is also presented. We show that by carefully tuning the partial-reset state the impact of drift can be mitigated even further as almost all the synapses post-learning lie in the non-driftable regime. Systemlevel simulations show that both approaches can perform complex problems of machine learning with ultra low power consumption. This highlights the potential of PCM technology for future intelligent ubiquitous embedded systems.

Fig. 2 .

 2 Fig. 2. Schematic of the '2-PCM Synapse' architecture. Inset shows a TEM image of GST PCM device.

Fig. 3 .

 3 Fig. 3.Experimental LTP curve for pulse width of 300ns. Inset shows 100 different simulated LTP curves with a 20% standard deviation variability included on all synaptic parameters described in equation 3 of[START_REF] Suri | Phase Change Memory as Synapse for Ultra-Dense Neuromorphic Systems: Application to Complex Visual Pattern Extraction[END_REF].

Fig. 4 .

 4 Fig. 4. Experimental Resistance-Voltage curves for different programming pulse widths on GST PCM devices.

Fig. 5 .

 5 Fig. 5. Simplified stochastic STDP learning rule. 'On' corresponds to set and 'Off' to reset of the PCM synapse.

Fig. 6 .

 6 Fig. 6. Schematic of the 'Binary-PCM Synapse' architecture and the proposed programming-scheme.

Fig. 7 .

 7 Fig. 7. (Top) Model of the retina and DVS sensor [18] used for generating AER data. (Bottom) Schematic of the two-layer SNN used for complex visual pattern extraction.

Fig. 8 .

 8 Fig. 8. Distribution of synaptic resistance states for the '2-PCM Synapse' architecture at the end of the visual learning simulation.

Fig. 9 .

 9 Fig. 9. Distribution of synaptic resistance states for the 'Binary-PCM Synapse' architecture with 20 kOhm mean Roff.

Fig. 10 .

 10 Fig. 10. Distribution of synapses in off-state for the 'Binary-PCM Synapse' with mean Roff values of 20 kOhm, 30 kOhm and 123 kOhm.

Fig. 11 .

 11 Fig. 11. Distribution of synapses in on-state for the three cases shown in Fig.10.

Fig. 12 .

 12 Fig. 12. Final neuron sensitivity maps for the '2-PCM Synapse' and the 'Binary-PCM Synapse' (20 kOhm partial-reset state) architectures.

TABLE I .

 I COMPARISON OF LEARNING STATISTICS AND PERFORMANCE FOR THE DIFFERENT ARCHITECTURES.

ACKNOWLEDGMENT

The PhD scholarship of Manan Suri is supported by DGA-France.