Clément Gaine

Driss Aboulkassimi

Simon Pontie

Jean-Pierre Nikolovski

Jean-Max Dutertre
email: dutertre@emse.fr

Simon Pontié

Electromagnetic Fault Injection as a New Forensic Approach for SoCs

Keywords: Electromagnetic Fault Injection, SoC, Forensic, Smartphones

I. INTRODUCTION

The security of sensitive data stored in integrated circuits (IC) can be altered by passive hardware attacks such as sidechannel (e.g. the electromagnetic (EM) side-channel [START_REF] Aboulkassimi | ElectroMagnetic analysis (EMA) of software AES on Java mobile phones[END_REF]) or active attacks (e.g. physical tampering or fault injection). Various techniques are used to stress the attacked devices, such as laser [START_REF] Vasselle | Laser-Induced Fault Injection on Smartphone Bypassing the Secure Boot[END_REF], voltage glitch [START_REF] Timmers | Escalating Privileges in Linux Using Voltage Fault Injection[END_REF], electromagnetic perturbations [START_REF] Dehbaoui | Electromagnetic Transient Faults Injection on a Hardware and a Software Implementations of AES[END_REF]- [START_REF] El Mehdi | Analyzing the Resilience of Modern Smartphones Against Fault Injection Attacks[END_REF] or even the software-induced CLKSCREW attack [START_REF] Tang | CLKSCREW: Exposing the perils of security-oblivious energy management[END_REF]. Faults Injections intentionally disrupt the operations of a system and obtain behaviors not anticipated by designers. This can be data flow or control flow modifications. The exploitation is obtained by inverting the result of a conditional test, by skipping a branch instruction or exiting a loop prematurely (as discussed in Section V).

In this paper, we focus on Electromagnetic Fault Injection (EMFI) by applying a transient EM pulse on the device under test. A voltage pulse is transmitted to a fault injection probe, an electromagnetic coil, to generate this field. It targets the physical implementation of a microprocessor to corrupt its control flow. This may allow a privilege escalation or an information leakage. In the case of smartphones, their exploitation can reveal a large amount of personal data.

EMFI is routinely used for security characterization of microcontrollers: circuits that have a simple architecture and WIFS'2020, December, 6-11, 2020, New York, USA. 978-1-7281-9930-6/20/$31.00 ©2020 IEEE. run at low frequency. Smartphones use complex hardware and software architectures. They also run at higher frequency (1 GHz or above). This explains why there was to date no report of successful data extraction from a smartphone through an EMFI technique. EMFI may also be used to complement conventional forensic tools (e.g. using fault injection to recover boot-ROM dumps in order to identify weaknesses that can be exploited in a standard methods).

In our research, we studied a smartphone-grade 64-bit System on a Chip (SoC) running a Linux OS. Our intent was to ascertain the ability to use privilege escalation through EMFI for forensic purposes. Interesting effects created on the target by the EMFI process were identified during preliminary tests (i.e. the fault model).

This article is organized as follows. Section II reviews the state-of-the-art of EMFI and introduces the aim of our work. Our experimental setup and settings are described in section III. Section IV reports on our first experiments on our SoC target. Then, an attack path is identified and validated in section V. In section VI we discuss the use of the technique in a forensic context. Section VII concludes the paper.

II. RELATED AND PREVIOUS WORK

A. State of the art of EMFI attacks

To the best of our knowledge the first time that physical attacks have been introduced as a potential forensic application was by Aboulkassimi et al. [START_REF] Aboulkassimi | ElectroMagnetic analysis (EMA) of software AES on Java mobile phones[END_REF] in which the authors showed how to use side channel analysis for recovering data from a mobile device. We extend this approach to active hardware security techniques. EMFI was mainly used against microcontroller or FPGA targets running at low frequencies, as in [START_REF] Dehbaoui | Electromagnetic Transient Faults Injection on a Hardware and a Software Implementations of AES[END_REF]. This has been the subject of numerous publications, and studies about fault models (i.e. the characteristics of the induced faults). Zussa et al. [START_REF] Zussa | Investigation of timing constraints violation as a fault injection means[END_REF] proposed that faults are produced by timing violations. This assumption was reinforced with Schaumont et al. [START_REF] Schaumont | Inducing local timing fault through EM injection[END_REF] and their study at different levels: wirelevel, chip-network level and gate-level. Most of injections target the CPU, through some (as Menu et al. [START_REF] Menu | Precise spatio-temporal electromagnetic fault injections on data transfers[END_REF]) rather faulted data transfers from the Flash memory to the data buffer of a cortex-M microcontroller.

So far little work has been done about SoC, due to their complexity: advanced hardware technology, numerous software layers with an OS, high operating frequencies. However, Regarding EMFI on SoCs, Majeric [START_REF] Majéric | Etude d'attaques matérielles et combinées sur les 'Systemon-Chip[END_REF] [8] successfully conducted a Differential Fault Analysis (DFA) to extract the secret key of a software Advanced Encryption Standard (AES) running on a A9-Cortex (32-bit ARM core). On the same device, Proy et al. [START_REF] Proy | Studying EM Pulse Effects on Superscalar Microarchitectures at ISA Level[END_REF] caused software loop exits.

Majeric et al. [START_REF] Majéric | Etude d'attaques matérielles et combinées sur les 'Systemon-Chip[END_REF] also studied a A7-Cortex (32-bit ARM core). They were able to bypass a secure boot with the repeatability of 0.78%. They also tried to realize EMFI attacks on a software running in a Trusted Execution Environment (TEE) on a A53-Cortex (64-bit ARM core).

Recently, Trouchkine et al. [START_REF] Trouchkine | Electromagnetic fault injection against a System-on-Chip, toward new micro-architectural fault models[END_REF] worked on a A54-Cortex (a 64-bit ARM core). Studying loops, they showed that the EMFI effects were different in bare metal mode w.r.t. using an OS. The difference is related to how the cache memories are managed. In the case of a bare metal target, they were able to attribute the faults to the cache memories (L1 and L2) and to the Memory Management Unit. Ait el Mehdi [START_REF] El Mehdi | Analyzing the Resilience of Modern Smartphones Against Fault Injection Attacks[END_REF] tried to bypass the lock screen of a 64-bit ARM target running Android 8 with EMFI. He proposed a theoretical attack scheme which was demonstrated in simulation, but its practical implementation failed.

Other fault injection methods have also been used with SoCs. A laser attack on Android smartphone targeting the secure boot sequence was made by Vasselle et al. [START_REF] Vasselle | Laser-Induced Fault Injection on Smartphone Bypassing the Secure Boot[END_REF]. Timmers et al. [START_REF] Timmers | Escalating Privileges in Linux Using Voltage Fault Injection[END_REF] showed that Voltage Fault Injection allows a full control of a Linux OS without any logical vulnerability.

A new class of fault attack that can be exploited on SoCs is the CLKSCREW attack [START_REF] Tang | CLKSCREW: Exposing the perils of security-oblivious energy management[END_REF]. Controlling the Dynamic and Voltage Frequency Scaling system (DVFS) allows to modify the power voltage and clock frequency by software means for the purpose of conducting an attack. Instruction skips are predominantly the effects of fault injections [START_REF] Timmers | Escalating Privileges in Linux Using Voltage Fault Injection[END_REF], [START_REF] Dehbaoui | Electromagnetic Transient Faults Injection on a Hardware and a Software Implementations of AES[END_REF], [START_REF] Proy | Studying EM Pulse Effects on Superscalar Microarchitectures at ISA Level[END_REF], however Proy extended the classification with 3 other observable effects at Instruction Set Architecture (ISA) level: register most-significant half-word reset, register corruption or source operand substitution. Among of all the publications presented, there are two objectives: (1) extracting secrets [START_REF] Aboulkassimi | ElectroMagnetic analysis (EMA) of software AES on Java mobile phones[END_REF], [START_REF] Majéric | Electromagnetic security tests for SoC[END_REF], [START_REF] Tang | CLKSCREW: Exposing the perils of security-oblivious energy management[END_REF] , or (2) bypassing security features [START_REF] Vasselle | Laser-Induced Fault Injection on Smartphone Bypassing the Secure Boot[END_REF], [START_REF] Timmers | Escalating Privileges in Linux Using Voltage Fault Injection[END_REF], [START_REF] El Mehdi | Analyzing the Resilience of Modern Smartphones Against Fault Injection Attacks[END_REF], [START_REF] Tang | CLKSCREW: Exposing the perils of security-oblivious energy management[END_REF]. However, of all these publications, only one was in a forensic context [START_REF] Aboulkassimi | ElectroMagnetic analysis (EMA) of software AES on Java mobile phones[END_REF]. This latter work is based on passive method, we chose here to conduct our research using an active method: EMFI. In this paper, we propose a new technique using physical attacks as a new approach for EMFI based forensic application. We focus on an A53-Cortex core. It is a 64-bit multi-core SoC used in many smartphones, mainly at entry and mid-range price levels. We propose a fault model at the ISA level. We also propose an attack scenario on the same target running an OS. [START_REF] Timmers | Escalating Privileges in Linux Using Voltage Fault Injection[END_REF] has shown that fault injection can exploit various attack paths. We limited ourselves to one path, but with another method: EMFI. This technique could be used on a critical command, allowing Super User privilege escalation on Linux (su). This is the first study on a 64-bit chip with a complete software architecture, usable in a smartphone. This can be used for forensic purposes to access protected or hidden data or to execute code.

III. EXPERIMENTAL SETUP

A. Targeted SoC

The targeted SoC, based on 4 ARM Cortex cores A53 with 32-bit and 64-bit support, is part of a development board for mobile platforms. Its operating frequency can be set between 800 MHz and 1.2 GHz. An external 1 GB RAM is soldered on the board. So, the chip is directly accessible via EM injection. Removing a part of the plastic package of the chip or modifying the board was not necessary to perform EMFI

The target was flashed with a Linux-based system: the Sumo release of the Yocto Project with a Linux kernel 4.14. Yocto allows having a custom Linux distribution, however we haven't made any major system change.

B. EMFI platform and injector

The source of the EM perturbation is a voltage pulse delivered to an injection probe. This probe is a coil for creating a magnetic field, which is guided by a ferrite rod. For this experiment, the pulse generator can provide a voltage pulse amplitude of up to 400 V with a rise time of 2 ns in nominal operation. The EM injection probe is shown in Figure 1. A thin ferrite rod of 750 µm in diameter was chosen together with a thin enameled copper wire, featuring 5 turns. Its characteristics improve the locality of the induced perturbations. This is necessary for EM injection on small advanced technological nodes used in SoC. Due to the locality of the EM perturbation radiated, the probe must be placed close to the chip. The probe position is finely controlled by a XYZ motorized stage.

A Unit Control (Raspberry Pi Board) completes the electromagnetic fault injection platform, presented in Figure 2. It communicates with the board using 2 UARTs: one for the control console and the other for the data. A signal trigger is produced through one GPIO of the SoC to trigger the voltage pulse generator. A controlled delay may be added between the reception of the trigger signal and the actual pulse generation.

IV. IDENTIFICATION OF A PHYSICAL VULNERABILITY

Inducing faults into a SoC is more difficult than into a microcontroller due to many factors. This is due first, to a small technological node. Thus we have to make a very precise location scan using an EM probe with a small diameter. Moreover, the target size (55 mm 2 for the targeted SoC) is larger than that of general-purpose microcontrollers (about ten mm 2 ). This enlarges the area to be explored. Due to the higher operating speed, the cycle time is also shorter, which implies increasing the time resolution and accuracy of the scans. Besides, there are many uncontrollable desynchronization sources. Finally, this requires a higher EM field and therefore more powerful equipments. On another aspect, the multiple reboots and the loading time of the OS on a SoC is long, which lengthens the time needed to perform the data acquisition campaigns.

The first part of our methodology is to learn how to inject faults (ie identify a physical vulnerability). A simple test code is used to find the time and space injection parameters and deduce the fault model.

A. Identifying when to fire

The aimed target is complex, for the sake of simplicity we chose to force the CPU frequency at 1.2 GHz. Then we always used the same configuration, in order to improve repeatability.

We use the Code Under Test (CUT) given in Listing 1, to obtain faults by EMFI. To alleviate the synchronization constraints, this test code was chosen long enough (300 ns) to be easily faultable. It consists in a series of subtractions by one from an initial value passed successively to ten registers and iterated 32 times. We use no loop in the test code in order to highlight the fault effect on the registers rather than alterations of the loop control flow, which are harder to interpret. The registers we are manipulating, x 19 to x 28 , are 64-bit registers that are dumped in memory at the end and readback. When no fault is injected, the expected result corresponds to a decreasing series of hexadecimal numbers (from 39 to 30), as shown in the reference A line of Table I. A Simple ElectroMagnetic Analysis (SEMA) was used to identify the relevant timing of the EMFI. It consists in recording an image of the computational activity of the target through its EM emanations, which are sampled using a passive EM probe connected to an oscilloscope through a low noise amplifier. While listening, it is not possible to perform EM shots to avoid damage to the acquisition system. In figure 3, we can see, in green color, the EM trace captured via a Langer probe and its amplifier positioned near the processor. The trigger signal is colored in blue. It is raised, then no operation instructions (NOP) are executed, followed by the test code and other NOPs and finally the trigger is lowered. NOPs allow us to isolate the CUT, which also makes it easier to view in SEMA. We can observe the EM emissions produced by the CUT 2.1 µs after the trig up with a 300 ns duration.

Delay and jitter are introduced by the code and characteristics of the equipment. The minimum delay between the GPIO raising instruction and the shot is about 420 ns and the jitter is 50 ns. The use of a trigger signal and the SEMA analysis of the target activity allowed us to synchronize the EM perturbation with the CUT. As a result, any timing uncertainty is suppressed. The next step was to find a spatial location of the injection probe that makes it possible to inject faults into the target.

B. Identifying where to fire

It turns out that only one Central Processing Units (CPU) out of the four embedded in the targeted SoC was sensitive to EMFI. The other three CPUs couldn't be faulted. In order to keep the parameters identical throughout the campaign, it was chosen to run the test programs only on this CPU. Injecting a fault without controlling the CPUs is nevertheless possible, but it lengthens the duration of the campaigns. Similar results were obtained with different chips of the same reference.

The first tests were also done with a large diameter probe, 1.5 mm of ferrite's diameter, to save time by identifying the sensitivity of a larger area. To test the sensitivity of a larger area, tests should be done with the maximum available voltage to highlight sensitive areas. The area is considered sensitive when freezing or rebooting the SoC. Once a sensitive area is found, we reduce the probe diameter and the voltage to locate the most sensitive point, and look for some exploitable faults.

C. Results

By iterating, the best configuration (position, timing, stress intensity) could be found. Figure 4 displays the effects obtained due to EMFI overlaid to a picture of the target silicon die. These effects are classified as: no fault when the target behavior is undisturbed, succeed when the registers return is corrupted, and crash when the target initiates an autoreboot or freezes (i.e. communication is lost). One result of this campaign is presented in Figure 4. The categorization of data has been simplified and is as follows: undisturbed results (no fault), modifications of registers (succeed) and crashes including auto-reboots and freeze. Auto-reboots correspond mainly to a report of an illegal modification of the Program Counter, which is corrected by reboot. We consider a freeze when the card does not respond to any request on UARTs.

The green box that contains the region with the vulnerability measures 1 mm by 1 mm. The interesting area, with fault on when manipulating the registers, is lower than 0.4 mm 2 . It's located in an area that appears to be close to the CPU represented in red. The values returned from the registers are given in Table I During a campaign, pulse delays and positions are varied, thus maximizing the types of faults. Approximately 30% of faulty results are obtained. The majority are communication losses (14%, reference B), due to a restart of the board or a closing of the application. This mostly happens in the first 50 ns of code execution. This can be seen in figure 5 which depicts the obtained faults as a function of the delay between the trigger signal and the actual EMFI.

Reference C corresponds to EMFI induced between the 1 st and 310 th sub instructions (13% of the results). We analyze it as an instruction skip (i.e. the fact that one instruction is not executed). It breaks a chain of 10 successive subtractions made on the ten registers. As a result, the returned values are higher than expected (an increase by 0x0A). Note that, we Reference D and E correspond to fault induced during the 10 lasts sub. Their frequency rate are around 0.1%. The first part of the results correspond to the expected values, but the following ones are incremented by 10 (highlighted in red). This means that the execution of one instruction have been skipped, and we observe the values of the previous round. By considering the case of the fault injection mechanism reported in reference E, skipping the sub x20,x19,#1 instruction left x20 content unchanged at 42. This faulted value breaks the chain of subtractions: the subsequent sub instructions also produce faulted values (with an increment of 10 w.r.t the correct values). Note that skipping several successive instructions produces the same result. These results therefore occur when the shooting takes place during the last instructions. The timing analysis in Figure 5 confirms it. These results show that we can modify the behavior of the SoC. The effect obtained is that of an instruction skip. The code used does not make it possible to determine the number of instruction skips made (between 1 and 10). However, further testing showed that only one instruction is skipped. The rest of the methodology is devoted to change the behavior of a security function.

V. PRIVILEGE ESCALATION EXPLOITING THE PHYSICAL VULNERABILITY

A. Analyze the code to identify an attack path

The results obtained with a test code are now applied to a more complex code used by a security application. EM-induced instruction skip can be exploited. By choosing the instruction to skip, as an instruction branch, we should successfully modify the control flow. Indeed, in the case of a loop, if we skip an instruction branch, we should exit it prematurely. So we looked for these instructions in a software code.

It was chosen to try to achieve an escalation of privilege in order to have a full access to the system. The command chosen was the su command of Linux. This Substitute User command is used to acquire privileges of another user account. su uses the libpam library (Pluggable Authentication Modules LI-Brary) to authenticate a user before providing new privileges. libpam asks the user to provide an administrator password, once verified and validated, it opens an administrator console with full permission. Obtaining administrator rights with a wrong password is considered as a successful attack.

A first attack path is to modify the control flow of the authentication function. A jump of the branch instruction that check the password allows to continue the elevating procedure even if the password is wrong. However a protection introduces a jitter of 1 second if the password is wrong. We don't know the password, so we'll have a random delay of about a second introduced before the targeted branch. The synchronization must be accurate to the nanosecond, so this makes it impossible in practice to attack. We therefore looked for another instruction before this random delay.

The validity of the entered password is not assessed by comparing it directly to the stored password. At first it is hashed (using a hash function) and then compared to the hash of the stored password. The strcmp function from the LIBC library is used to compare the two hash strings. This chain has a length of 106 bytes and consists of the hash id, the seed and the hash separated by $. Two examples are shown below.

• $6$wWxFc-tJdeOI05-KNO$lAAh-w8Th... • $6$wWxFc-tJdeOI05-KNO$Uung-4U7s... Comparison of the 2 hashes (ASCII representation) The strcmp function compares 8-char blocks from left to right. If it encounters two different blocks, the check is stopped and the two strings are reported as different. Regardless of the password entered, the first two 64-bit words are identical because they correspond to the prefix of the hash function. A premature loop exit during the 1 st or 2 nd word comparison would cause all passwords to be interpreted as valid passwords. Nevertheless, an injection at the 3 rd comparison will also cause a loop exit, but the password will be considered as wrong and won't allow the privilege escalation.

In order to validate this analysis, the behavior in the event of a loop exit was tested. An extract of the strcmp function is shown, in listing 2. This code loads two words, performs the comparison, checks if there is a difference (or for the end of the chain), then continues the comparison or stops. The Compare and Branch on Zero instruction (cbz), highlighted in red, is in charge of branching to the beginning of the function to perform the next block comparison, or to end the comparison.

A first validation was conducted on simulation basis, we used the gdb debugger tool to run the strcmp function on our target and emulate the effect of skipping the cbz instruction. An instruction skip on the 1 st or 2 nd cbz instruction exit the loop without detecting any password difference. It validates the proof of concept of this vulnerability. The control flow could theoretically be modified, the next step was to assess the practical feasibility of this vulnerability.

B. Preparation to facilitate the characterization of strcmp

With the previous simulation results, the exploitation of this vulnerability seems attractive. The rest of the methodology is to prove the vulnerability of strcmp in an experimental way. We decided to start by proving the concept only on a strcmp comparison code identical to that used by su.

For the best understanding of fault injection mechanism to obtain privilege escalation, the adopted approach consist in starting by strcmp which is used in su, before attacking su itself. The idea was to ascertain experimentally the existence of a vulnerability on a simpler case. A code calls it and passes two different character strings in argument. These strings are entered directly into the code, which, unlike the su code, doesn't make calls to the flash memory. This allows a less important jitter than in the real case. We could directly monitor the output of strcmp, which is not possible with the su code, in order to check if there has been a modification of the control flow. The trigger is set just after the reception of the password.

We managed to get a success rate of 2%, which corresponds to a success every 2 minutes, for a code running always on the same CPU with a fixed probe position at a fixed frequency.

C. Results and Exploitation

The success obtained in the previous part encouraged us to demonstrating the proof of concept of a more complex attack. As we already observed that only one core of the target is vulnerable to EMFI, we use a program to launch the su process on this very specific CPU. It has been chosen to always send the same incorrect password. A trigger was added in a modified libpam. This trigger is managed by the module libpam_misc and the file misc_conv.c. This trigger is set up after the password reception and set down after the call of the strcmp function. The area of interest, bordered by the trigger, is 200 ns.

The test was successful when the operating frequency was set at 1.2 GHz, but it was also successful with the Dynamic Voltage and Frequency Scaling activated. Once the settings have been made, we obtained 21 success for 6,000 tests. This is equivalent to obtaining a success every 300 shots, which corresponds to a successful authentication every 15 minutes.

We can authenticate quite regularly, but the board restarts as soon as the authentication is successful. In order to circumvent this limitation and in the scenario of an attack, one can add to the call of su the parameters "chmod + s /bin/bash" allowing to make persistent the root access to the terminal.

The command had time to be executed before the restart. Thus, we can set the SETUID to allow a permanent escalation of privilege. This is observed by the flag "s" instead of "x" for all users in the Unix permissions. These results show the effectiveness of EM injection attacks on a SoC for the purpose of inducing privilege escalation.

VI. TOWARDS A FORENSIC USE

A. Discussion of results

The first compromise we made on a real scenario was to move most processus to different CPU to keep only one CPU for the code under test. Regarding this point, tests have shown that this only influences the success time rate and, by multiplying the campaign time by the number of CPUs we can find equivalent results. This has been implemented, and, in order to have a uniform distribution of the code under test on all the CPUs, a program soliciting the processor is used. This allows a frequent change of the CPU where the code to be faulted runs, and therefore in our case, decreases only by a factor of 4 the success rate. Forcing the code to run on a CPU therefore has the effect of speeding up the manipulation.

The study was done on a SoC, which can also be used with Android OS, but the attack should be adapted.

Using a trigger signal in order to have an ideal synchronization was particularly interesting to understand the fault model. For a forensic use, this technique cannot be used because it assumes root access to the SoC in order to authorize the use of GPIOs. In a more realistic case, we would look for another way to synchronize as explained hereafter.

B. Synchronize EMFI without a GPIO

In the case of forensic use on a real mobile device, we cannot have all the accesses we have on a development board, so it is wise to pose the problem of EMFI synchronization without using a trigger from a GPIO. The first idea when we want to perform a simple synchronization would be to use a fake usb keyboard to enter the password and get a good synchronization. Before carrying out such an analysis, the jitter due to the code was estimated. A first analysis showed a standard deviation of approximately 5 ms between the reception of the password by the su and the call of the strcmp function. By keeping the optimal parameters of the injection bench and according to our estimates, several weeks experimentation should be conducted to generate one successful fault injection. This could be achieved, but the lapse time of attack strongly encourages the development of tools to improve synchronization. A solution could be to exploit the EM fields emitted by the processor in order to generate a trigger signal.

C. Use Cases for Forensic

One of the problematic points in the forensic is to bypass secure boot or root access. Commercial forensic solutions work using specific software flaws. EMFI is an alternative because it targets the hardware. Our results show that EMFI, similarly to software attacks, can be used to gain access to the data of a smartphone, execute or plan the execution of a code.

EMFI-based hardware forensic may also be used as a first step in order to increase the potentiality of the usual forensic software tools. Indeed, EMFI could provide new contents to be analyzed. We can imagine using EMFI to unlock security in order to dump a boot-ROM. Then, the extracted code can be analyzed, in order to identify a software flaw and to be exploited by using conventional tools. Thus, the joint use of these two techniques can push forward the limits of forensic tools.

VII. CONCLUSION AND FUTURE WORKS

This paper shows that it is possible to apply successfully EM fault injection on a smartphone-grade SoC despite the complexity of the hardware and software architectures of the target. The reported exploitation case consists in bypassing the root privilege protection of the target. The proof of concept has been demonstrated, even if the real scenario would require a synchronization tool. As the objective of this article is to present a new approach for forensic, we also suggested some use cases. Future works will focus on bypassing a secure boot on a Smartphone, using the EMFI approach.

Fig. 1 .

 1 Fig. 1. Probe designed for EM Injection on a SoC target

Fig. 2 .

 2 Fig. 2. EM pulse injection setup B. Contributions, EMFI in the forensic field

/

  /Initialisation x28 = 368 = 0x170 mov x28, #0170 //Following sequences repeated 32 times sub x19, x28, #0x1 sub x20, x19, #0x1 sub x21, x20, #0x1 ... sub x28, x27, #0x1 Listing 1. Code working with registers

Fig. 3 .

 3 Fig. 3. Delay identification using SEMA, without EM fire

Fig. 4 .

 4 Fig. 4. Localization of EMFI-sensitive areas on an IR image of the target

Fig. 5 .

 5 Fig. 5. Number of faults by function type versus pulse delaycannot conclude on the exact number of skipped instructions because any value between 1 and 9 would produce the same faulted result. This analysis is further strengthened by reading the time repartition of these faults in Fig.5(i.e. from 50 ns to 300 ns of the faults window).Reference D and E correspond to fault induced during the 10 lasts sub. Their frequency rate are around 0.1%. The first part of the results correspond to the expected values, but the following ones are incremented by 10 (highlighted in red). This means that the execution of one instruction have been skipped, and we observe the values of the previous round. By considering the case of the fault injection mechanism reported in reference E, skipping the sub x20,x19,#1 instruction left x20 content unchanged at 42. This faulted value breaks the chain of subtractions: the subsequent sub instructions also produce faulted values (with an increment of 10 w.r.t the correct values). Note that skipping several successive instructions produces the same result. These results therefore occur when the shooting takes place during the last instructions. The timing analysis in Figure5confirms it. These results show that we can modify the behavior of the SoC. The effect obtained is that of an instruction skip. The code used does not make it possible to determine the number of instruction skips made (between 1 and 10). However, further testing showed that only one instruction is skipped. The rest of the methodology is devoted to change the behavior of a security function.

  .

	Ref.	Occurrences	Result (x19, ..., x28)	Proportion
	A	27287	39,38,37,36,35,34,33,32,31,30	71.0%
	B	5314	Communication lost	13.8%
	C	4899	43,42,41,40,3F,3E,3D,3C,3B,3A	12.7%
	D	48	39,38,37,36,35,3E,3D,3C,3B,3A	0.1%
	E	28	39,42,41,40,3F,3E,3D,3C,3B,3A	0.1%
		...	...	...
			TABLE I
		RESULT OBTAINED WITH EMFI ON THE CODE IN LISTING 1


Sylvain Prigent

Charles Kervrann

Jean Salamero

come

BIOIMAGE-IT: DESIGN DATA ANALYSIS WORKFLOWS USING TOOLS FROM DIFFERENT LANGUAGES AND KEEP TRACK OF THE METADATA SYLVAIN PRIGENT [1][3], CHARLES KERVRANN [1][3], JEAN SALAMÉRO [2][3]

[1] Inria, Centre Rennes-Bretagne Atlantique, France [2] UMS3714 CNRS Institut Curie, France [3] France-BioImaging, France

New image acquisition systems generate large number of images and large volume images. Such data sets are hard to store, to process and to analyze for one user in a workstation. Many solutions exist for data management (Omero, OpenImadis…), image analysis (Fiji, Icy, CellProfiler, Python libraries…) and statistics (R…). Each of them has it specificities and several bridges have been developed between pieces of software. Nevertheless, in many use-cases, we need to perform analysis using tools that are available in different pieces of software and different languages. It is then tedious to create a workflow that brings the data from one tool to another. It needs programing skills and most of the time, a dedicated script using a dedicated file system for processed data management is developed.

The aim of the BioImage-IT project it to create a "bandmaster" application that allow any scientist to annotate data, process data and analyze data using only one single high level application. This BioImage-IT application is based on 3 components: § an image annotation method based on a json file system, § an image processing and analysis tools integration method based on Docker and XML commands description, § an application with a graphical interface to easily annotate data, run processing tools, and visualize data and results.

This software architecture has three main goals. First, data are annotated using a file system. This means that data are not dependent on any software like a SQL database, and each experiment can then be stored in a different directory and moved from one server to another or to any drive with a simple copy pasting operation. Second, the processing tools are used as binary packages managed by Docker. Docker makes it easy to deal with the dependencies and allows to use several versions of the same tool. Any existing tool can then be integrated as it is without re-inventing the wheel. Third, using a single "bandmaster" application allows to automatically generate metadata for any processed data, making available the traceability and repeatability of any result. BioImage-IT is developed in the context of the France-BioImaging research infrastructure in coordination with the IPDM-FBI (Image Processing and Data Management) node in order to provide a standardized image processing tool set and data management for the imaging facilities.


Mohammad Sadegh Saadatzi
email: saadatzi@email.sc.edu

Plastic strain energy dissipated in fatigue crack propagation

A comparison between thermal dissipation of fatigue crack propagation in plane stress and plane stress condition is presented. The results show the role of plastic hardening of material as a variable which determines the ratio of plastic dissipation in plane stress and plane strain conditions. The results also show that the plastic dissipation is higher for plane stress compared to plane strain for the same material and same load condition. Poisson ratio Crack length (m) Strain range Dimensionless constant Cyclic strength coefficient (MPa) Equivalent stress Cyclic yield stress (MPa) Equivalent strain Frequency

∆P

Normal load range (N)

Introduction

The study of damage mechanics is an interesting aspect of engineering field in different structure such as composite material [START_REF] Arashmehr | An experimental and numerical investigation of a grid composite cylindrical shell subjected to transverse loading[END_REF][START_REF] Jafar | Stress analysis of clamped-free grid composite cylindrical shell under various end loadings[END_REF] honeycomb structure [START_REF] Rohanifar | Numerical modelling of mechanical properties of 2D cellular solids with bi-modulus cell walls[END_REF] and metals. The study of damage is facilitated through Acoustic Emission [START_REF] Saadatzi | Utilization of Scanning Acoustic Microscope (SAM) to prove the existence of stress relaxation in woven composite[END_REF][START_REF] Saadatzi | Modeling and Fabrication of a Piezoelectric Artificial Cochlea Electrode Array with Longitudinal Coupling[END_REF] and the exciting part of damage is related to crack propagation.

Fatigue, as a damage accumulation in components, has been the subject of study for many years. This is known that the cyclic stress can degrade material up to a point when the small crack nucleate and the final rupture of the part takes place when the crack starts to propagate. This propagation of fatigue crack has essential role in safety of the mechanical parts in rotating machinery where cyclic stress is an inevitable part of the operation condition.

Fatigue crack propagation has been subject of study from different aspects. Conventionally, crack propagation rate, which is the main concern in studying of crack propagation, has been related to stress intensity factor [START_REF] Paris | A critical analysis of crack propagation laws[END_REF][START_REF] Koohbor | Characterizing fracture response of cracked transversely graded materials[END_REF] or energy release rate [START_REF] Mohammadi | Micromechanical prediction of damage due to transverse ply cracking under fatigue loading in composite laminates[END_REF], however, in recent years the thermal investigation of fatigue crack propagation has emerges and this puts forward the need for understanding fatigue crack propagation plastic dissipation. The propagation rate of fatigue crack can be found by other aspects including thermography. Recently Hajshirmohammadi and Khonsari [START_REF] Hajshirmohammadi | A simple approach for predicting fatigue crack propagation rate based on thermography[END_REF] found a simple approach for determining the crack propagation rate based on thermography.

In the present paper the approach proposed by Hajshirmohammadi and Khonsari [START_REF] Hajshirmohammadi | On the entropy of fatigue crack propagation[END_REF] is used to investigate dissipation rate.

The crack front experience concentrated filed of stress when loads are applied to the faces of crack (Fig. 1). The plastic zone is the area ahead of the crack tip where plastic dissipation takes place. The reason for the plastic dissipation is the excessive values of the stress and strain around the tip. A portion of plastic work which is done around the tip is converted to heat that represents itself as a temperature rise around the crack. It is assumes that the plastic strains and stress are the source of dissipation and a comparison between plane stress/plane strain dissipation in the vicinity of crack tip is given according to plastic stress field given by HRR (Hutchinsone_Rice_Rosengren) [START_REF] Hutchinson | Singular behaviour at the end of a tensile crack in a hardening material[END_REF].

Theory and formulation

It is widely accepted to use Ramberg-Osgood relation as an equation to describe plastic strain of material.

(

) 1
where and denote the range of strain and stress and represents the cyclic strain hardening. is the elastic modulus and cyclic strengths coefficient is shown by .

According to Hutchinson [START_REF] Hutchinson | Singular behaviour at the end of a tensile crack in a hardening material[END_REF] the field of stress and strain ahead of the crack tip can be estimated by the following relations.

(2)

(3)

In the equations above, and are functions for angular distribution of stress. The cyclic yield stress is shown by and stands for the dimensionless constant which is given by Eq. 4. and is the integration constant of crack.

(

) 4
As illustrated in Fig. 2, the plastic zone has a butterfly shape. Each point in the plastic zone acts as a dissipation source. The total dissipation is the summation of the contribution of all the points in the plastic region. For each point within the plastic zone, the stress and strain can be found by HRR singularity.

Suppose the dissipation is found for the point B shown in Fig. 2. The dissipation is derived using Eq. 5.

(5)

The size of plastic zone is found for plane stress and plane strain condition according to Eq. 6 and Eq. 7 respectively. (6) [START_REF] Koohbor | Characterizing fracture response of cracked transversely graded materials[END_REF] Replacing Eq. 2 and Eq. 3 in Eq. 5, one can derive the relation for plastic dissipation at any point in this region. [START_REF] Mohammadi | Micromechanical prediction of damage due to transverse ply cracking under fatigue loading in composite laminates[END_REF] in which is the range of stress intensity factor and f is frequency of loading. The angular equivalent distribution of stress and strains are denoted by functions respectively. The value for equivalent stress and strain in the case of plain stress is given by the following relations.

(9) [START_REF] Hajshirmohammadi | On the entropy of fatigue crack propagation[END_REF] For the plain strain case, these value can be found by Eq. 11 and Eq. 12. [START_REF] Hutchinson | Singular behaviour at the end of a tensile crack in a hardening material[END_REF] (12)

In these relations, and represent functions of angular distribution for the case of two dimensional problem.

The total strain energy dissipated from crack tip is the summation of each point generation inside the plastic zone.

(13)

The angular function of plastic zone border is: (14) And the radius of plastic zone circle is given by Eq. 9.

(15)

Looking back into Eq. 13, it is seen that the relation can be written in the following form for the polar coordinate system.

(16)

The parameters in the integration of Eq. 16 are independent of and except for and . This implies that this relation can be written in the following form:

(17)
This can be found from Eq. 17 that the is a constant for a specific material (when is a material parameter). The value of is called . This is understood that the value of is different for the same material in plane stress and plane strain condition. To determine the relation between the plastic dissipation in plane stress and plane strain condition, the ratio of .

Numerical approach

Eq. 13 is used to determine the plastic dissipation where the integration is found using Simpson method. The numerical procedure is carried out by A MATLAB script. The accuracy of integration is set to be 10 -6 . The singularity problem is solved by subdividing the area of integration into too regions and separation of plastic zone from the rest of area.

Results and discussion

Fig. 3 depicts the energy generated from plastic zone ahead of crack for different stress intensity factors. As it is seen, the heat generation from the crack is more when the plane stress condition prevails. This result implies that for the same condition of loading, the energy needed for crack activation is higher when the situation of plane stress prevail. In other words, if a thick plate is under fatigue crack propagation, the plastic dissipation is less in the center of the plate where the situation is closer to plane strain compared to the outer parts close to the surface of plate where loading is close to the plane stress case.

Conclusions

A numerical model is developed to find the strain energy dissipation from a crack tip of a moving fatigue crack in mode one. The solution shows that dissipated energy directly increase with the stress intensity factor. This model predicts higher dissipation in plane stress compared to plane strain crack propagation.

Fig 1 .

 1 Fig 1. Crack faces loaded in the first mode of crack propagation.

Fig 2 .

 2 Fig 2. Cyclic plastic zone in front of the plastic zone.

Fig. 3 Fig. 4

 34 Fig.3plastic dissipation as the function of stress intensity factor Fig.4illustrates the variation of in respect with . This figure shows that for low values of the strain hardening exponent, the ration of is less than one which means that the plastic dissipation in plane stress is less than the plane strain plastic dissipation.