Quoc Tran The Hoang
email: tran-the.hoang@g2elab.grenoble-inp.fr

Bao Duong
email: quoc-bao.duong@grenoble-inp.fr

Tuan Tran Quoc

Yvon Besanger
email: yvon.besanger@g2elab.grenoble-inp.fr

Tung Lam Nguyen
email: tung-lam.nguyen@g2elab.grenoble-inp.fr

Bao Quoc

Duong

Quoc Tuan Tran
email: quoctuan.tran@cea.fr

A Fault Classification Method for Medium Voltage Networks with a high Penetration of Photovoltaic Systems using Artificial Neural Networks

Keywords: Artificial neural network, Multilayer Perceptron Classifier, fault classification, distribution network, photovoltaic system;

come

I. INTRODUCTION

Faults on distribution feeders are one of the main factors causing disturbances or sometimes interruption in power supply to customers, and therefore need to be quickly and accurately detected and cleared by protection systems. These faults then should be isolated by fault management systems, and the supply is recovered to as many affected customers as possible. For these systems to realize fast, accurate, and effective performance, the role of the fault classification scheme is of vital importance.

The development of fault classification algorithms for distribution networks has attracted lots of research over the last decades. According to [START_REF] Chen | Fault detection, classification and location for transmission lines and distribution systems: a review on the methods[END_REF], fault classification methods may be approximately divided into the following categories, including logic flow-based, decision tree, support vector machine, fuzzy inference systems, and artificial neural network. Prior to the era of smart grid technologies, most researches for distribution networks had used the same principles developed for transmission systems. Authors in [START_REF] Oliveira | New algorithms for fault classification in electrical distribution systems[END_REF] used a negative sequence factor derived from pre-fault and post-fault measurements of negative-sequence and zero-sequence currents as inputs for their neural network-based fault classification algorithm. The scheme in [START_REF] Usman | Fault classification and location identification in a smart distribution network using ann[END_REF] also proposed to use µPMUs located at different locations across the feeder for obtaining the input data for the classification system. A method in [START_REF] Zhang | An anfis-based fault classification approach in power distribution system[END_REF] developed an ANFIS-based method that can adapt to different grounding systems, fault resistance, load levels, and the change in network configuration, achieving a rather high accuracy of about 99.4%. A method published in [START_REF] Guo | Deep-learning-based fault classification using hilbert-huang transform and convolutional neural network in power distribution systems[END_REF] was based on Hilbert-Huang Transform and Convolution Neural Network that employed transient and stationary fault signals as inputs. Research in [START_REF] Das | Fuzzy logic-based fault-type identification in unbalanced radial power distribution system[END_REF] made use of fuzzy-logic, avoiding the requirement for training stages. The main disadvantage of these methods in [START_REF] Zhang | An anfis-based fault classification approach in power distribution system[END_REF]- [START_REF] Das | Fuzzy logic-based fault-type identification in unbalanced radial power distribution system[END_REF] is the requirement for a high sampling rate (10 kHz) that would impose huge computation burdens for the fault recording systems. Hence, a waveletbased scheme was described in [START_REF] Dwivedi | A wavelet based approach for classification and location of faults in distribution systems[END_REF] that utilized Daubechies fourth-order wavelet for reducing the computational burden. Nonetheless, none of these above-mentioned researches took the impacts of distributed generators and their detailed fault characteristics into considerations.

In the event of a fault, new inverter-interfaced generating units, such as photovoltaic (PV) systems, Battery Energy Storage System (BESS), converter-based wind turbine (WT) ... and so on, respond to faults in a way differing from that of conventional synchronous generators. As a result, as the integration of such distributed generations (DGs) has increased, fault characteristics of the distribution systems have changed significantly. Moreover, many countries have upgraded their grid codes to require these DGs, especially those connected to medium-and low-voltage grids, to actively be involved in supporting grid stability in the event of faults, resulting in their unneglectable impacts on transient processes of the overall network. Thus, those methods developed for transmission networks cannot be applied. Moreover, the distribution networks are no longer radial after the installation of DGs downstream of the outgoing feeders. Nondirectional overcurrent based protection units are not sufficient for protecting the whole grid in different operating scenarios. Other methods, such as directional or distance protections, should be applied [START_REF] Laaksonen | Adaptive protection and microgrid control design for hailuoto island[END_REF]- [START_REF] Memon | A critical review of ac microgrid protection issues and available solutions[END_REF]. Since these protection principles require information on fault types before moving to the next operating stage, the development of new effective fault classification algorithms dedicated to distribution networks with high penetration of inverter-interface DGs has become more and more essential. However, the number of fault classification studies for a new kind of active distribution network is still limited. In [START_REF] Adewole | Fault detection and classification in a distribution network integrated with distributed generators[END_REF], the wavelet energy spectrum entropy-based method was utilized. Different fault locations, fault resistances, fault inception angles, load angle variations, network topology changes as well as the connection of distributed generators, were taken into account. A similar methodology was also presented in [START_REF] Dehghani | Fast fault detection and classification based on a combination of wavelet singular entropy theory and fuzzy logic in distribution lines in the presence of distributed generations[END_REF]. The processing time of this method is less than 10ms, which is quick enough for protection purposes. Nonetheless, the effects of fault resistances and variations of DG generation were ignored. Reference [START_REF] Lout | Current transients based phase selection and fault location in active distribution networks with spurs using artificial intelligence[END_REF] suggested wavelet transform for extracting distinct features for identifying faulted phases. However, the computation time and sampling rates of input data that are very important for practical implementation were not mentioned.

For the application of new kinds of protection principles rather than nondirectional overcurrent, new fault type classification that can cope with the high integration of PV systems and their intermittent nature should be developed. In the context of smart grids, especially the potential application of big data analytics for utilizing historical data accumulated from practical power system operation, machine learning is an inevitable trend of research, and of course, it would be the most suitable application tool in this case. Therefore, in this paper, a fault-type classification scheme based on Artificial Neural Network that can deal with these shortages mentioned above was proposed. The Artificial Neural Network was theoretically explained in subsection III-A. The performance of the proposed system was investigated in different fault scenarios.

II. THE STUDIED NETWORK

The studied network is a realistic medium-voltage distribution network whose parameters are provided by a local utility. The single-line diagram of the network is shown in Fig. 1. The network consists of 7 diesel generators feeding the loads via 7 transformers whose connection groups are ∆/Y -11. The rating of each generator is 1.125 MVA. The total installed capacity of PV and wind systems are 8 MW and 3 MW, respectively. The rating of a PV system is 500 kW. There are two PV plants located in different locations with PV-1 at the generation center and PV-2 near the end of feeder 1. The number of PV systems installed at PV-1 and PV-2 are 6 and 10, respectively. From the 22 kV busbar systems located in the generation center, three radial feeders are originated from the 22 kV busbar systems of the generation center, supplying various single-phase and three-phase LV loads. Moreover, feeder 1 and feeder 2 mesh at several points by normally-open switches. The earthing system used for the MV network is the solidly and undistributed earthed method. Regarding the earthing LV grid, the TT system was selected since it appears as the most suitable method, allowing the PV systems to be coupled with the grid without grounding their neutral point [START_REF] Jayawarna | Safety analysis of a microgrid[END_REF].

Since the total maximum load demand, which is 8 MW, is less than the overall installed capacity of the PV and wind energy, a battery energy storage system (BESS) was installed at the production center to store the surplus amount of power generation during peak hours of PV systems. On the other hand, the BESS will be discharged to feed the loads during some periods over a day when required, for instance, during no-generation hours of PV systems.

Note that the PV and wind systems in the study are modeled to fulfill the new grid code requirements. In other words, PV and wind systems should be capable of staying connected during the fault and feeding reactive current to support the network voltage recovery. The control scheme of PV systems is illustrated in Fig.

2 [START_REF] Castilla | Grid-fault control scheme for three-phase photovoltaic inverters with adjustable power quality characteristics[END_REF]. During the fault event, the reference signal generator block generates the reference currents that follow the dynamic voltage support requirements imposed by the grid code indicated in [START_REF] Bartels | Generating plants connected to the medium-voltage network[END_REF]. Also, the output current should be confined to the inverter thermal limit, which in the case is equal to 1.2 times its rated current [START_REF] Bartels | Generating plants connected to the medium-voltage network[END_REF]. Additionally, the three-phase loads were partially modeled as dynamic loads, i.e., frequency-and voltage-dependent, to obtain more realistic load effects on fault data. In contrast, single-phase loads were represented as static load, i.e., constant impedance.

III. THE PROPOSED FAULT CLASSIFICATION ALGORITHM

A. Multi-layer perceptron classifier-based artificial neural network

Artificial Neural Networks (ANNs) are statistical learning algorithms that are widely used recently in numerous applications, including classification schemes. Many libraries and frameworks are available to develop neural networks. Among these other, Multi-layer Perceptron (MLP) Classifier appears to be one of the most suitable candidates for developing classification purposes. Opposed to other classification methods, such as Support Vector Machines or Naive Bayes Classifier, MLP Classifier applies an underlying Neural Network for conducting classification tasks [START_REF] Music | Classification of leaf type using multilayer perceptron, naive bayes and support vector machine classifiers[END_REF]. Therefore, the authors proposed to use the MLP classifier in this paper thanks to their ability to solve problems stochastically, which often allows approximate solutions for extremely complex problems like fitness approximation. The layer-based architecture of the applied MLP classifier can be observed in Fig. 3.

Each layer contains N neurons connected to the neurons of the previous layer. Each neuron, in turn, receives many inputs from other nodes and computes a single output based on the inputs and the connection weights. The layers which are between these two are named hidden layers. In our proposal, we applied a three-layer neural network. The first layer consists of a set of 50 neurons, whereas the two followings comprise sets of 30 and 4 neurons, respectively. The output of the neural network should be of 4 since we were intended to classify the fault into four categories. The number of the inputs was justified in subsection III-B. For properly triggering each layer, a suitable activation function should be chosen according to the application goals. In our case, an activation function, namely sigmoid, was chosen and described as:

σ(z) = 1 1 + e -z = e z e z + 1 (1)
The computation that is carried out in the neuron of the first layer would be as:

z (1) = W (1) • X + b (1) (2)
where X is the input vector, b (1) is the bias vector of all units whose dimension is [50 × 1], and W (1) is the weight matrix of dimension [50 × N ] described by (3):

W (1) =     ω (1) 1-1 • • • ω (1) 1-N . . . . . . . . . ω (1) 50-1 • • • ω (1) 50-N     (3)
The calculations in the two hidden layers are defined as:

z (2) = W (2) T • σ z (1) + b (2) (4) z (3) = W (2) T • σ z (2) + b (3) (5)
where W (2) and W (3) are weight matrix whose dimensions can be obtained from Fig. 3. The sizes of b (2) and b (3) are [30× 1] and [4 × 1] respectively. The output neuron of dimension [4 × 1] is calculated as:

ŷ = σ z (3) (6)
The learning of the neural network is accomplished by altering the weight of the connection. By updating the weight iteratively, the performance of the network is improved. In this developed algorithm, we utilized the Back-propagation method presented in [START_REF] Rojas | Neural networks: a systematic introduction[END_REF]. Back-propagation is a standard method whose goal is to train the neural network for calculating the weights and bias. In this case, we had the known data output (supervised learning), by a method to lessen the error function E, we can obtain weights ω (l) ij . We can estimate the error for each output neuron by adopting the squared error function and sum them to find the total error:

E = 1 2 • N n=1 m l i=1 y l i (x n ) -t n,i 2 (7)
where x n is the n-th element of the input vector X, t n,i is the n-th element of the output vector of the i-th class, y l i (x n ). The back-propagation step computes the gradient of E with respect to this input as follows:

ω (l) ij ← ω (l) ij -n • ∂E ∂ω (l) ij (8)
where n represents the learning rate.

The learning process of the proposed algorithm is described in Algorithm 1 [START_REF] Rojas | Neural networks: a systematic introduction[END_REF].

Algorithm 1

The learning process of the proposed algorithm 1: Feed-forward computation: use equation ( 2), ( 3), ( 4), [START_REF] Guo | Deep-learning-based fault classification using hilbert-huang transform and convolutional neural network in power distribution systems[END_REF] and ( 6) for calculate for each layer. The vectors z (1) , z (2) and z (3) are computed and stored. The evaluated derivatives of the activation functions are also stored at each unit 2: Back-propagation to the output layer 3: Back-propagation to the hidden layer 4: Weight updates

B. Data measurement and feature extraction

The faults in power systems can be classified into four types, including single-phase-to-ground (Type-1), two-phase (Type-2), two-phase-to-ground (Type-3), and three-phase (Type-4). The last type of fault may be to earth or clear of the earth that has the same nature [START_REF] Anderson | Analysis of faulted power systems[END_REF]. As justified in the introduction, with high penetration of PV systems and the introduction of new grid codes, the fault currents have become bidirectional rather than unidirectional. Moreover, the PV systems respond to faults in a way differing from that of conventional wellestablished synchronous generators. Therefore, one-point measurement appears impossibly enough for fault type identification within such an active grid.

In this research, after having considered the number of measurement data set, the author proposed to install three measuring units (MU) on the concerned feeder, i.e., feeder 1, as shown in Fig. 1 including MU1, MU2, and MU3. The measuring units may be µPMUs or smart meters that can provide timely and time-synchronized current and voltage phasors effectively for data analysis in our case, [START_REF] Usman | Fault classification and location identification in a smart distribution network using ann[END_REF]. Each MU samples the measured three-phase current and voltage values at the sampling rate of 800Hz. The derived currents and voltages were filtered by using a cosine-filtering algorithm that is quite popular in relay technologies, as presented in Fig. 4 [START_REF] Rebizant | Digital signal processing in power system protection and control[END_REF]. Application of machine learning-based approaches for fault type identification, especially for large networks, necessitates a large data set of faults, requiring a great number of fault scenarios. In the study, the authors proposed to carry out fault simulation at different hours during a day, from 0 to 20 hours by a of 4 hours. The varying operation times at which the fault happened also allowed us to cover the impacts of intermittent nature of PV generation. Moreover, we took the effects of fault resistance into account by increasing its value from 0 to 60 Ohm by a step of 10 Ohm. Faults were assumed to occur at 14 different sections of three feeders. By combining these above fault scenarios with 4 fault types, a totally of 2352 faults scenarios were simulated. In the study, faults were assumed to occur at t = 1.5s and be cleared at t = 1.65s, i.e., lasted for 7.5 cycles; however, the authors only made use of 4 samples per cycle per each quantity for a duration of 2 first cycles from the instant of fault inception. So, for each fault scenario, there were 8 data windows taken into consideration.

Based on these sampled values, the data processing unit carried out the calculation of magnitudes and angles of current and voltage symmetrical sequence components. For each data window received from each MU, 12 quantities would be derived. As a result, the authors obtained 36 quantities from three MUs plus one quantity standing for the time, a totally of 37 quantities for each data window, as dictated in Fig. 5, corresponding to vector input X that was provided to the proposed ANN (Fig. 3).

C. Data set for training and testing the designed ANN

The data set was split into two smaller sets, one for training and another for testing with a ratio of 75:25 correspondingly, as shown in Fig. 5. Firstly, the first part of the data set was loaded into the designed ANN for learning purposes following the Algorithm 1 described in Subsection III-A. Afterward, the remaining part of the data set was used for testing the proposed approach. Fig. 5 presents the flowchart of the proposed method.

IV. EVALUATION AND DISCUSSION

The result of testing the developed network presented in types with high accuracy, the overall average error is lower than 1%. One more notable feature of the proposed approach is that its average computation time for all cases in the testing data set is only 2.323 millisecond, rather fast compared with 10 ms of a method presented in [START_REF] Dehghani | Fast fault detection and classification based on a combination of wavelet singular entropy theory and fuzzy logic in distribution lines in the presence of distributed generations[END_REF]. It can also be observed that the computation time and the error increase at 8, 12, and 16 hours compared with three remaining testing hours. This is due to the participation of PV systems in power production.

The type of faults that occurred during a high generation of PV systems was more difficult to be identified. It took the developed network more time and iteration steps to reach the final results. Although the developed method was tested with the different grid configurations, it needs to be checked and upgraded in case of a large modification of the concerned network, e.g., disconnection of an outgoing feeder or a primary transformer.

V. CONCLUSION AND PERSPECTIVE

An MLP classifier based artificial neural network was proposed in this paper for fault classification within medium voltage distribution networks with a high share of PV systems. The proposed approach can deal with different fault scenarios with varying network operational times and scenarios. Detailed models of PV systems and loads were also employed for making the simulation data as close to practice as possible. High accuracy and low computation time of the method were demonstrated. Moreover, the proposed method can be employed for more complicated electrical networks since its performance just depends on the data set provided.

In the further step, the authors are determined to develop the presented methodology for fault location since this topic is rather challenging for distribution network operators in the context of high penetration of DGs.

Fig. 1 .

 1 Fig. 1. Single-line diagram of the studied network

Fig. 2 .

 2 Fig. 2. The control diagram of the PV systems

Fig. 3 .

 3 Fig. 3. The layer-based architecture of the applied MLP classifier

Fig. 4 .

 4 Fig. 4. of current phasor from sampled waveform

Fig. 5 .

 5 Fig. 5. The flowchart of the proposed method

  Table I indicates that the proposed method identified fault

	.. . .. . .. .	.. . .. . .. .	.. . .. . .. .
	.. . .. . .. .

TABLE I

 I

		FAULT TYPE CLASSIFICATION RESULTS PER HOUR
	Hour	Average computation time, ms	Accuracy, %
	0	1.889	100
	4	2.016	100
	8	2.259	99.1
	12	2.432	98.6
	16	3.391	98.7
	20	1.950	99.3
	Average	2.323	99.3


Wendpanga Fadel Bikinga
email: wendpanga-abdoul.bikinga@grenoble-inp.fr

Kouceila Alkama

Bachir Mezrag

Jean Michel Guichon

Yvan Avenas
email: yvan.avenas@g2elab.grenoble-inp.fr

Implementation of TAPIR switching cells with integrated direct air-cooling for SiC power devices

Keywords: packaging», «SiC devices», «Thermal management», «Switching cell»

This paper presents the design of an SiC switching cell made with the TAPIR technology. Electromagnetic and thermal simulations are carried out in order to analyze the performance of this switching cell. This cell is then compared to commercial power modules and discrete components and exhibits excellent junction to ambient thermal resistance and stray inductance.

Introduction

The energy transition involves a deep change in energy production and consumption patterns and involves an increase in the electrification of systems. According to the U.S. Advanced Research Projects Agency-Energy (ARPA-E)' more than 80% of electrical energy in the United States will use static converters by 2030 [START_REF] Broughton | Review of thermal packaging technologies for automotive power electronics for traction purpose[END_REF]. Modern power electronics is thus facing a substantial demand on improving efficiency while reducing size and cost of systems for a broad range of areas, including electric vehicles, renewable energies, industrial motors and generators, and distribution grid applications [START_REF] Lee | A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues[END_REF]. Size reduction and efficiency of converters have been improved in recent years due to the growth of widebandgap semiconductors use [START_REF] O¨ Stling | SiC power devices present status, applications and future perspective[END_REF]. The increase in switching frequency allows reducing the size of passive components and thus obtaining converters with higher power density [START_REF] Adamowicz | Performance comparison of sic schottky diodes and silicon ultra-fast recovery diodes[END_REF] [START_REF] Ranstad | On dynamic effects influencing IGBT losses in soft-switching converters[END_REF]. However, the packaging of these semiconductors requires special attention due to their high switching speeds [START_REF] Regnat | Optimized Power Modules for Silicon Carbide mosfet[END_REF].

Therefore, the challenges of tomorrow's power electronics designers include improving semiconductor packaging to reduce electrical and electromagnetic disturbances, and optimizing cooling to lighten converters to meet the needs of electric mobility where weight is a significant constraint. Indeed, the weight of the cooling system is generally non-negligible. For example, Delhommais et al. [START_REF] Delhommais | Using design by optimization for reducing the weight of a SiC switching cell[END_REF] propose a global optimization of a SiC switching cell and show that about 25% of the global weight is due to the heatsink and the fan.

The TAPIR (compacT and modulAr Power modules with IntegRated cooling) technology [START_REF] Bikinga | Low voltage switching cell for high density and modular 3D power module with integrated air-cooling[END_REF] seems to be able to reduce the mass of power modules and cooling systems by a ratio of 3 to 5 by distributing the heat sources (chips) in the volume of the heatsink. Contrarily to most researches on double side cooling [START_REF] Broughton | Review of thermal packaging technologies for automotive power electronics for traction purpose[END_REF], the heat extraction is made by air-cooling and the heatsinks are used as electrodes as it is the case with press-pack power converters [START_REF] Senturk | Converter Structure-Based Power Loss and Static Thermal Modeling of The Press-Pack IGBT Three-Level ANPC VSC Applied to Multi-MW Wind Turbines[END_REF] or Power Chip on Bus (PCoB) modules [START_REF] Xu | Development of an ultra-high-density Power Chip on Bus (PCoB) module[END_REF]. TAPIR technology consists in sandwiching vertical semiconductor components between two heat sinks. Then two sandwiches and a decoupling capacitor are assembled to make a low voltage-switching cell as shown in Fig. 1. Finally, the global power module is made by assembling several switching cells together. An example of a 4-phase converter is given in [START_REF] Bikinga | Low voltage switching cell for high density and modular 3D power module with integrated air-cooling[END_REF].

Fig. 1: TAPIR low voltage Switching cell

In [START_REF] Bikinga | Low voltage switching cell for high density and modular 3D power module with integrated air-cooling[END_REF], two packaged 60V-100A power MOSFETs are implemented in a switching cell that is characterized using the double pulse method. The parasitic inductance of the switching loop is less than 2 nH. Also the thermal behavior is estimated using thermo-sensitive electrical parameters. The measured junction to ambient thermal resistance is close to 1.30 K/W. The coupling thermal resistance is relatively low and limited to 0.2 K/W. However, the junction-to-ambient thermal resistance can be further reduced by using bare chips and improving the heat sink as proposed by Xu et al. [START_REF] Xu | Development of an ultra-high-density Power Chip on Bus (PCoB) module[END_REF]. In this reference, the authors propose a sandwich similar to the one of the TAPIR method and including SiC devices with a junction-to-ambient thermal resistance of only 0.5 °C/W.

The aim of the present paper is to propose an implementation of the TAPIR technology on a high voltage SiC switching cell. The goal is to analyze the electromagnetic and thermal performances of the cell and compare it to commercially available power modules and discrete components. The implementation of the SiC switching cell is presented, followed by electromagnetic and thermal simulations. Before concluding, a comparison will be made with commercially available components.

Implementation of an SiC switching cell

SiC MOSFETs CPM2_1200_0080b (1200V-36A, RDSon=80mΩ) from CREE company were used to build a switching cell. A 4-layer printed circuit board (PCB) has been designed to connect the MOSFET to the gate drive circuit but also to ensure a connection of the die to the heatsinks with few thermal interfaces (Fig. 2 and3).

In Fig. 3, it can be seen that the source and gate pads of the chip are soldered on PCB layer 2. For this purpose, a nickel-gold coating has been made on the gate and source metallizations. Beneath the two source electrodes of the chip, a copper inlay is inserted between layer 2 and layer 4. Layer 1 is cut so that the Drain is accessible from the PCB surface through a hole (Fig. 2 and3). This implementation has several advantages in terms of thermal management:

-one heatsink can be directly connected to the drain of the chip, -the number of thermal interfaces between the source metallization and the other heatsink is relatively low.

The gate drive circuit (buffer) is located on layer 4 of the PCB and vias provide electrical connections between the control signals and the chip. Layer 1 is thin (35µm) to minimize the distance between the chip and the top of the PCB in order to have the thinnest soldering thickness and ensure good electrical and thermal conductions. Layer 3 is used to connect the gate to the driver circuit avoiding the guard rings. Vias connecting the source are located on either side of the gate track. This minimizes the inductance of the gate circuit and creates electromagnetic shielding of the gate. Layer 4 thickness is 120µm for allowing heat spreading of the heat flux and thus reducing the thermal resistance of the solder between the PCB and the heatsink. To make the switching cell, the heatsinks are cut (Fig. 4) to avoid any electrical contact with the components of the gate control circuit on the PCB board. The thickest component is the gate driver which has a height lower than 2 mm. This choice is made in order not to degrade too much the thermal performances by improving the electromagnetic one. Note that a gate driver chip could be directly integrated inside the PCB to simplify the assembly but the technological process is not done already.

Fig. 4: SiC Switching cell

Once the switching cell is presented, electromagnetic simulations will be proposed to estimate the parasitic inductance of the switching loop, then thermal simulations will be carried out to analyse the thermal performances of this assembly.

Stray inductance of the SiC switching cell

Electromagnetic simulations are carried out with Flux3D software based on the finite element method. Indeed, the PEEC method that is usually used for evaluating power electronics packages is not adapted to the TAPIR geometry that does not include any thin electrical conductors like it is the case in classical power modules. The MIPSE software still under development at G2Elab which uses integral methods [START_REF] Le-Duc | A New Integral Formulation for Eddy Current Computation in Thin Conductive Shells[END_REF] is also used here to visualize the distribution of the current density in order to refine the mesh on Flux3D, but also to confirm the result obtained with Flux3D.

In Fux3D, a magneto-harmonic application at a frequency of 100 MHz is used. The simulation is done at this frequency because the equivalent frequency measured in [START_REF] Bikinga | Low voltage switching cell for high density and modular 3D power module with integrated air-cooling[END_REF] was about 100MHz. The decoupling capacitor is replaced by a current source of 1A injected on the surface over a thickness of 2mm (see Fig. 5). This consideration was made after having noted that during switching time only the lower part of the capacitor injects current in the structure (see Fig. 4). The voltage is measured across the current injection areas and the stray inductance is deducted. The capacitive effects are not included in this simulation.

The simulated geometry is shown in Fig. 5. The chip (3mm*3mm*0.35 mm) is assumed to be directly attached to the heatsinks, as well as the copper inserts (3mm *1mm*0.4mm). Only one internal layer is considered in this simulation because adding the second one does not change much the result. This inner layer is not connected to the copper inlay as can be seen on the PCB architecture in Fig. 3. The micro vias that link the inner layers to the source potential are represented as two bars.

All components of the switching cell are assumed to be made of aluminum of resistivity 2.68E-8 Ω.m. This approximation is valid since the size of the chips and inserts is small compared to that of the heatsinks.

Fig. 5: Simulated switching cell geometry

For applying boundary conditions, an infinite box is used. Its dimension is twice the size of the device to be tested as recommended in the software documentation. The thickness of the infinite box is 20mm.

Simulations have been performed to analyze the impact of increasing the size of the infinite box. This has almost no influence on the results.

As in any finite element resolution, the quality of the mesh has an impact on the veracity of the results. For this purpose, it is necessary to know which is the main current path and thus to adapt the mesh by decreasing the elements size in critical areas. Several simulations have been done with Flux3D and MIPSE sofwares to determine the current path at the proposed frequency. Fig. 6 shows the distribution of the current density in logarithmic form obtained after simulation on MIPSE. It can be seen that the current flows mainly on the edges (skin effect) of the heatsinks and in the semiconductor chips and copper inlay. The mesh is densified at these places by adding 100µm plates shown in red in Fig. 5, so as to have at least two meshes in the skin thickness which is about 60µm. The mesh creates more than 500,000 1st order volume elements.

Fig. 6: Current path in the switching cell

The parasitic inductance obtained after simulation with Flux3D is 1.41nH. To carry out the simulation with MIPSE, the appropriate mesh is exported from Flux3D. The application is always magnetoharmonic and the injected current is 1A. The elements here are assumed to be in copper simply because that is the only available conductive material. This time the parasitic inductance obtained is 1.38nH that confirms the value obtained with Flux3D. Note that the simulation time is largely decreased using MIPSE compared with Flux3D, it will allow optimizing the geometry in the future.

The parasitic inductance of the simulated SiC cell is thus less than 1.5 nH while the parasitic inductance measured in [START_REF] Bikinga | Low voltage switching cell for high density and modular 3D power module with integrated air-cooling[END_REF] is 2nH. This is explained by the fact that in [START_REF] Bikinga | Low voltage switching cell for high density and modular 3D power module with integrated air-cooling[END_REF] the MOSFETs are packaged and thus the PCB is thicker that increases the stray inductance of the assembly.

The SiC switching cell shows the advantages that were expected from an electromagnetic point of view.

The thermal behavior will now be studied.

Thermal behavior of the SiC switching cell

Thermal simulations are performed to estimate the junction to ambient thermal resistance of a MOSFET and the thermal coupling that would exist between the two MOSFETs of the switching cell. They are carried out with the Flotherm software. The simulated architecture is shown in Fig. 7 and Fig. 8. This assembly is fairly representative of the actual switching cell. The solder thickness of 200µm between the heatsink and the drain of the chip (fig. 7) is present in practice due to a too large margin taken by the subcontractor (CIBEL) in order to avoid the breakdown of the chip during the PCB fabrication. This thickness will be considerably reduced in the next phases of production. Contact resistances are not considered in these simulations. The thermal conductivity of the different materials used for the simulation are shown in Table I. The heat transfer coefficient varies between 500 and 1500 W.m-². K-1, these values are estimated from heat sink datasheets [START_REF] Bikinga | Low voltage switching cell for high density and modular 3D power module with integrated air-cooling[END_REF]. The dissipated power is 50W in MOS1 and 0W in MOS2. The average temperature of both MOSFETs is measured to determine the junction to ambient thermal resistance of MOS1 and the coupling thermal resistance between MOS1 and MOS2.

The results are shown in Fig. 9.

Then MOS2 dissipates 50W and the other 0W to check if the heat is extracted in the same way. The thermal resistance value is slightly lower than that of the MOS1 and is 1.38K/W for a heat transfer coefficient of 1500 W.m-². K-1 instead of 1.46 K/W for MOS1. The coupling remains the same 0.074K/W. Fig. 9: Junction to ambient thermal resistance and thermal coupling as a function of the heat transfer coefficient

It is then interesting to analyze the temperature map inside the assembly to understand what can be done to improve its thermal behavior. For that purpose, Fig. 10 presents the evolution of the temperature along two paths: the first is perpendicular to the chip surface and crosses its center, the second is also perpendicular to the chip but crosses the center of the copper inlay. First it can be observed that the temperature is not uniform in the chip, the temperature being largely higher at the chip center than at the inlay center. It is something usual but that is accentuated here by the non-uniform dissipation area on the source side of the device. It is also observed that the temperature drop in the inlay is relatively high. It is due to its small cross section compared to the chip surface area. This problem induces a nonsymmetrical heat flux diffusion inside the assembly: using Flotherm, it is estimated that about 2/3 of the total dissipated heat flows through the top heat sink (ΦD in the figure) and thus only 1/3 of the remaining heat goes through the bottom heat sink (ΦS in the figure). Therefore, a good way to improve the global thermal behavior should be to propose a solution for increasing the average cross section of the copper inlay to obtain a better heat repartition between the two faces of the chip. Also, it is observed that there are large temperature drops in the heat sink base plates and between these base plates and the ambient temperature. This is the reason why the temperature evolution inside the assembly using a copper base plate was also shown. It can be clearly seen that the better thermal conductivity induces a lower temperature gradient and a better heat spreading (the temperature at the base plate surface is decreased). The last way to improve the thermal behavior would be to use a more performant heat sink to increase the global heat transfer coefficient. The thermal performances obtained are those expected. However, it would be possible to optimize the heatsink in order to have higher heat transfer coefficients and therefore a lower junction-to-ambient thermal resistance. The TAPIR SiC switching cell will then be compared with commercially available discrete SiC power modules and discrete components.

Benchmark of TAPIR SiC switching cell with commercially available power modules and discrete components

For this comparison power modules and discrete components using 1200V-80mΩ MOSFET SiC devices are chosen. It is obvious that the thermal resistance depends on the size of the devices and on the number of paralleled chips but it can even give fist ideas on the performance of the proposed package. Data are given in Table II.

Considering the stray inductance parameter, the TAPIR switching cell exhibits very interesting performances (1.5 nH) compared with classical power modules [12] and circuits using discrete devices with global stray inductances that are higher than 10 nH. Today commercial power modules are improved, by including decoupling capacitors for example [13], but such a low stray inductance is not reported. Note that if N devices are put in parallel in the TAPIR technology, the stray inductance is divided by N which is hardly obtained when implementing 2D packages.

Considering thermal aspects, it can be seen that the junction to ambient thermal resistance of the TAPIR switching cell is close to the junction to sink thermal resistance of power modules. That proves its very good thermal behavior. The use of better ceramic materials in power modules could reduce their thermal resistances but it has also to be noted that the thermal resistance of the TAPIR switching cell could be largely reduced by implementing better heat sinks. It was proved by Xu et al. [START_REF] Xu | Development of an ultra-high-density Power Chip on Bus (PCoB) module[END_REF] that obtained a junction to ambient thermal resistance of 0.5 K.W-1 with a geometry close to the TAPIR one. Finally, it is important to mention that the coupling thermal resistance of the TAPIR technology is very low especially when the heat transfer coefficient is high because the cooling is made at chip level. In the case of power modules, a thermal coupling exists through the power module substrate but also through the heat sink that induces more important values. For example, in [START_REF] Dbeiss | Power semiconductor ageing test bench dedicated to photovoltaic applications[END_REF], the thermal coupling resistance between devices was until 25 % of the junction to ambient thermal resistance using water cooling.

Table II: Electromagnetic and thermal performances benchmark

Conclusion

An SiC switching cell was designed and the structure of the related PCB was presented. The results obtained from the electromagnetic simulations show the quality of the switching loop and therefore makes this technology suitable for wideband gap components. The TAPIR SiC switching cell has also been evaluated from a thermal point of view. It has be seen that this technology is more efficient than those currently on the market. The TAPIR solution has a junction to ambient thermal resistance close to the junction to sink thermal resistance of some modules. The next step will therefore be to electrically and thermally characterize the SiC switching cell. The breakdown voltage, the common mode perturbations and the assembly of several switching cells to make a more complex topology will also be specific points to be addressed in the future.

Fig. 2 :Fig. 3 :

 23 Fig. 2: PCB for SiC MOSFETs

Fig. 7 :Fig. 8 :

 78 Fig. 7: Cross-section simulated for one MOSFET (dimensions are given in mm)

Fig. 10 :

 10 Fig.10: Temperature evolution inside the assembly (dissipated power in MOS1 50W, h=1500 W.m -2 . K -1 and ambient temperature 25°C)

  Rth(j-a) = 1.4 K/W @ h=1500 W.m -2 . K Rth(j-a) = 2.3 K/W @ h=500 W.m-2

The authors would like to thank SATT LINKSIUM for funding the work.


W F Bikinga

W Deffous

B Mezrag

A Derbey

F Dumas

B Sarrazin

Y Avenas

Low voltage switching cell for high density and modular 3D power module with integrated air-cooling

This paper presents the TAPIR (compacT and modulAr Power modules with IntegRated cooling) power module technology based on dual side air-cooling, the heat sinks acting as electrodes of power devices. Used with a large number of power semiconductor devices, this technology improves the cooling performances while maintaining low stray inductances in switching cells. It is therefore suited to high-speed devices and allows increasing the density of power converters. A low-voltage switching cell is designed and electrically and thermally tested. The weight of the semiconductor and thermal management parts of a three-phase inverter made with TAPIR technology is estimated and compared with more classical packaging approaches.

Introduction

The challenges of tomorrow's power electronics are among others the improvement of semiconductor packaging [START_REF] Van Wyk | On a future for power electronics[END_REF][START_REF] Seal | High performance silicon carbide power packaging-past trends, present practices, and future directions[END_REF]. Particularly, new power modules are designed to reduce electrical and electromagnetic disturbances in order to be used with high switching speed devices [START_REF] Regnat | Optimized power modules for silicon carbide mosfet[END_REF]. The optimization of the thermal management system is also a major issue to reduce the weight of converters and meets the needs of electrical mobility. Indeed, the weight of the cooling system is generally non-negligible. For example, Delhommais et al. [START_REF] Delhommais | Using design by optimization for reducing the weight of a SiC switching cell[END_REF] propose a global optimization of a SiC switching cell and show that about 25% of the weight is due to the heat sink and the fan. For a Si switching cell, they show that 38% of the weight is due to the cooling system because losses are higher. This paper presents a double-sided cooling technique, called TAPIR; adapted to high switching speed semiconductors and that would allow reducing drastically the weight of power converters. Contrarily to most researches on double side cooling [START_REF] Broughton | Review of thermal packaging technologies for automotive power electronics for traction purpose[END_REF], the heat extraction is made by air cooling and the heatsinks are used as electrodes like it is done in press-pack power converters [START_REF] Senturk | Converter structure-based power loss and static thermal modeling of the press-pack IGBT three-level ANPC VSC applied to multi-MW wind turbines[END_REF]. As it will be seen later, this implementation technique allows for a better distribution of heat losses inside the cooling system and therefore increases the effectiveness of heat sinks that are thus lighter than in classical cooling systems. TAPIR technology will be presented in the next section. Then an implementation of a switching cell will be proposed using discrete low voltage silicon components. The switching cell will be characterized from electromagnetic and thermal points of view. Before concluding, the weight of the semiconductor and thermal management parts of a three phase inverter will be estimated and compared with more classical packaging approaches

TAPIR technology

The basic of the proposed technology consists of inserting a semiconductor chip between two aluminum heatsinks (see Figure 1). The buffer part of the gate drive circuit can also be contained between these two heatsinks to be as close as possible to the chip for reducing disturbances on the gate circuit. Ideally, the chip can be connected (soldered or silver sintered) directly to a heatsink on one face to reduce the number of thermal interfaces. Note that plating of the aluminum heatsinks is necessary to perform the soldering process. There is not any ceramic material in this assembly, thus ensuring a good electrical and thermal conduction.

Figure 1 TAPIR elementary brick

The elementary brick of Figure 1 can be connected with others in series or in parallel through heatsinks to construct different types of converters. As an example, Figure 2 presents a possible implementation of an multiphase converter with four arms. The heat sinks are plotted in grey: they are plate fin heat sinks but they could be made using different technologies (foams, pin fins (Figure 1)…) to optimize the cooling efficiency. In orange, there are metallic plates to connect the heatsinks to each other. The green parts are isolating materials that can be made in plastic or polymer materials. The blue part is also an isolating material in which it is interesting to integrate a

G

Buffer

capacitor to reduce the stray inductance of the switching cells. Note that an enclosure surrounding the system (not represented in Figure 2 is necessary to isolate the heatsinks from the outside and/or manage conducted and radiated electromagnetic fields. As it can be seen in Figure 2, one major advantage of this technology is to distribute the heat sources (semiconductor chips) in the whole volume of the cooling system. Furthermore, cooling on both sides and directly on the power component improves the evacuation of the heat flux. This would allow increasing the power density compared to classical systems.

Figure 2 Possible implementation of a multiphase converter

The following section will be dedicated to the presentation of a first implementation of a single switching cell.

Low voltage switching cell

SiC and Si MOSFET semiconductor chips available on the market have generally a source metallization that is not adapted to the proposed technology (aluminum plating). Thus, to make a first implementation of the proposed technology, packaged components adapted to double side cooling were used. They are 60V-100A silicon MOSFETs TPW1R306PL components from Toshiba (Figure 3).

Figure 3 Top view of the PCB including electronic devices

A printed circuit board (PCB) was made to connect the power MOSFET with the buffer of the gate driver circuit (Figure 3). The Drain electrode of the MOSFET is soldered to the PCB and the Source is directly accessible on the top of the PCB through one cavity. The Source electrode can then be directly assembled on a tin plated heatsink. The connection of the Drain electrode to the other heatsink is made via a copper inlay inside the PCB. Figure 4 shows the specific architecture of the PCB. It is a four layers PCB with a cavity between layers 1 and 3. The components (MOSFET packaged, buffer circuit) are soldered in the cavity and on layer 3. The details of this layer can be seen in Figure 5. Under the MOSFET, there is a copper inlay between layers 3 and 4. It is used to make the drain potential accessible from the bottom layer of the PCB with low electrical and thermal resistances. between elementary bricks is carried out with lead solder (lower soldering temperature). One elementary brick after the soldering process is presented in the center of Figure 1. Two elementary bricks are then assembled to fabricate a switching cell (Figure 6). This figure shows that three aluminum plates were also assembled to the heatsinks for electrical connections of the switching cell with a power supply and a load. The capacitor C included in this assembly is achieved by integrating numerous SMD capacitor (0803) into a PCB. This capacitor is made with 63 capacitors of 10µF each and a capacitance value of 570 µF is measured using a multimeter. This capacitor is inside the structure and thus allows reducing the stray inductance. In the literature, several methods exist to measure the junction temperature of power semiconductors devices [START_REF] Avenas | Temperature measurement of power semiconductor devices by thermo-sensitive electrical parameters-a review[END_REF]. Temperature measurement by thermo-sensitive electrical parameters (TSEPs) is today the main way to carry out fast measurements on packaged devices [START_REF] Avenas | Temperature measurement of power semiconductor devices by thermo-sensitive electrical parameters-a review[END_REF]. In the case of power MOSFETs, the forward voltage under low bias current of the body diode can be used as temperature indicator. The voltage dependence is close to -2mV/•C for silicon devices [START_REF] Sofia | Electrical measurement using semiconductors[END_REF]. During the calibration step, the temperature is fixed by an oven. A measurement of the body diode voltage VSD is performed for several temperatures and a current Im of 20 mA (Figure 11). The circuit of Figure 12 is designed to estimate the junction temperatures of the components under constant dissipation thanks to the calibration previously performed [START_REF] Thollin | Partial thermal impedance measurement for die interconnection characterization by a microsecond "pulsed heating curve technique[END_REF]. One device is heated by using a high current source Ip. Two thermocouples are placed in the baseplate of the heatsinks to determine when the stationary state is reached. Once the temperature is stabilized, the voltage across the other MOSFET is measured to estimate its junction temperature and to estimate the thermal coupling between both devices. Then the current in the hotter MOSFET is turned off and it is possible to estimate its temperature during dissipation. The ambient temperature is measured with the thermosensitive parameter before the current dissipation step. This temperature is 22°C.

Figure 12 Circuit for measurement of the diode forward voltage under low current

For 100 A drain current, the power dissipation is 73W. In these conditions, the estimated junction temperature of the dissipating MOSFET is 119°C. The temperature of the other MOSFET is 37.5°C. The junction to ambient thermal resistance of the MOSFET is thus close to 1.30 K/W. The coupling thermal resistance is 0.2 K/W. Note that the datasheet of the packaged MOSFET indicates that the junction to case thermal resistance is close to 0.45 K/W if the heat flux is the same on both sides of the device. Thus the thermal resistance of the proposed solution could be lower than 1 K/W for air cooling if bare dies were used.

Benchmark

In this section, a theoretical study will be carried out to estimate the potential gains of the TAPIR technology compared with classical approaches in terms of weight and thermal efficiency -the stray inductance and electromagnetic issues will not be studied. The weight includes only the semiconductor parts and the thermal management system (fan + heatsinks). The case study is a three-phase inverter.

Commercial solutions

The thermal performance of the conventional converter is obtained using the SEMIKRON's online calculation tool "Semisel". The inverter is composed of three SKM50GB12T4 power modules composed of 2 IGBTs and 2 diodes chips. The DC bus voltage is 600V and the output current is 40A. The switching frequency is 15 kHz. The dissipated powers are 96W in each IGBT and 22W in each diode. By using the online tool in the case of air cooling by forced convection, it is found that the transistor junction temperature is 169°C using the P3-180 (0.120 K/W) heatsink with an ambient temperature of 22°C. From the datasheets, the weight of the power module, the heatsink and the fan are respectively 160g, 3100g and 550g. The global weight is thus about 4.1 kg. The same calculation has been made with water cooling. In this case, the reference of the cold plate is WP16_280 and the transistor junction temperature is 83°C. The weight of the system is close to 2 kg.

Estimation of TAPIR performance

The estimated performance of the TAPIR solution is determined by simulations with FLoTHERM software by considering the same chips as those in the selected SKM50GB12T4 modules. Figure 13 shows a cross-section of the simulated geometry for an IGBT. It is then possible to distinguish the different interfaces taken into account. The top is the collector and the bottom is the emitter. The pins of the heat sink are replaced by a global heat transfer coefficient. This heat transfer coefficient is obtained from the heatsink thermal resistance presented in Figure 14 for an air velocity of 5 m/s. The relationship between the thermal The TAPIR switching cell is simulated by arranging the semiconductor chips as shown in Figure 15. The decoupling capacitor is replaced by FR4 material with a thickness of 2.5mm and a height of 2mm. It is placed between IGBT 1 and Diode 2 and along the assembly (see Figures 15 and16). The losses given by 'Semisel' are used for thermal simulations of the TAPIR phase leg.

Figure 17 shows a 3D schematic of the inverter (semiconductor devices and cooling) considered. One fan is used per arm. By symmetry, the thermal study of the three-phase inverter can be reduced to that of one inverter arm. Note that the power connections from the outside are not represented. The heat transfer coefficient h applied to the heatsinks is then varied from 500 W/m 2 /K -2 m/s air velocityto 1500 W/m 2 /K and the average junction temperature of the hottest component is recorded. The simulation shows that the temperature of both IGBT (respectively both diodes) are not the same. This is due to the structure of the assembly and principally to the presence of the decoupling capacitor that reduces the exchange surface (see Figure 16). However, the difference is small. It is between 3 and 5°C depending on the applied heat transfer coefficient. For h=1500 W•m -1 •K -1 , the temperature of IGBTs 1 and 2 are respectively 88°C and 86°C and the temperatures of diodes 1 and 2 are respectively 53°C and 52°C.

Comparison

The difference between the junction temperature of the hotter IGBT and the ambient temperature is given in taking into account the mass of the heat sinks, PCBs containing the components (Figure 3), the fan and the plastic box (Figure 10). It should be noted that this weight does not include some elements like the busbar. Concerning the weight of the solution, it can be seen that TAPIR allows for a mass reduction of a ratio of 5 to 6 compared to the chosen SEMIKRON system with aircooling. Compared with water cooling ("classical water" in Figure 18), the weight reduction is lower (ratio of 2 to 3) but it must be mentioned that a complementary heat exchanger and a pump are generally necessary. Concerning thermal performances, it can be seen that the junction temperature obtained with the TAPIR solution is close to the one obtained with the air-cooled classical solution for lower heat transfer coefficients. For higher heat transfer coefficients, it is very close to the classical water-cooled solution. However, it must be noted that the Semikron power module is made with an alumina DBC which explains why the thermal performances are limited with water cooling. A simple calculation allows estimating the junction temperature if alumina is replaced by AlN ("classical water DBC AlN" in Figure 18). It can thus be seen that watercooling is the best solution if performant electrical insulators are used but the weight of the cooling system remains higher than the weight of the TAPIR solution.

Figure 18 IGBT junction temperature for different cooling technologies.

Conclusion

The TAPIR technology was presented and was first implemented in a simple switching cell fabricated with low voltage power MOSFETs. The stray inductance is very low. The measured thermal resistance reflects the cooling performance of this solution. The thermal simulation of a three-phase TAPIR inverter compared to a three-phase inverter made with commercial technologies has shown that TAPIR is more efficient than a conventional air cooling system and reduces drastically the weight. TAPIR's performance is close to that of water-cooling with high (but realistic) heat transfer coefficients. This performance is achieved by reducing the mass of the module and cooling system assembly by a ratio of 3 to 6 depending on the cooling strategy.

The scalability of this technology in terms of power and voltage will be addressed in future works. Regarding the power level, it must be proved that a large number of switching cells could be connected in parallel to provide both a good current sharing between devices and also a good cooling. Regarding the voltage, two different aspects must be studied: prove the possibility of connecting devices in series and design switching cells with high voltage capability.

Figure 4

 4 Figure 4 Architecture of the PCBThe deepness of the cavity (0.9mm) and thus the thickness of related PCB layers is linked to the thickness of the packaged MOSFET and its solder, this device being the thickest component of the circuit. The upper surface of the MOSFET and the height of layer 1 of the PCB should ideally be the same or as close as possible in order to make the soldering process easier and to have a good electrical and thermal contact with the heatsink. Layer 1 is at the Source potential like the heatsink. Layers 2 and 3 are also at the Source potential trough vias as it can be seen in blue at the left hand side of Figure4. This architecture allows reducing the gap between Source and Drain potentials in order to reduce the stray inductance. The stray inductance could be further reduced by decreasing the FR4 thickness between layer 3 and 4. The PCB manufacturer (CIBEL) has achieved the thickness of 490µm to facilitate the PCB manufacturing process. The connector in Figure5is used to power and control the buffer. The first three pins from the left are connected to the MOSFET electrodes (Drain, Source and Gate) for implementing Kelvin measurements as close as possible to the component. Layer 4 of the PCB is thick (205µm) for a better heat spreading and thus minimizing the thermal resistance of the assembly. The PCB with the soldered component is sandwiched between two aluminum heatsinks previously coated with 5µm Ni and 5µm Sn. A lead-free solder (Sac 305) is used to solder the components inside the hole and also for assembling heatsinks and PCBs, so that the assembly

Figure 5 Figure 6 8 .

 568 Figure 5 PCB layer 3 architecture

Figure 8 Figure 9 Figure 10

 8910 Figure 8 Electromagnetic measurement test bench

Figure 11

 11 Figure 11 Body diode voltage VSD as function of the device temperature (Im=20 mA and VGS=-5V).

resistanceFigure 13 Figure 14

 1314 Figure 13Cross-section simulated for an IGBT

Figure 15 Figure 16

 1516 Figure 15 Temperature map in the cross section of the assembly containing the chips (h=1300 W/m 2 /K)

Figure 18

 18 for the different cases presented above: the commercial solution (air and water-cooling), the TAPIR solution with different heat transfer coefficients. The weight of each solution is also given in this figure. The weight of the TAPIR solution (0.7 kg) is estimated by

Acknowledgement

The authors would like to thank SATT LINKSIUM for funding the work. They are also grateful to Pierina Perroti, from CEDMS for soldering electronic components, Sebastien Garcia for supporting the mechanical design of the switching cell and Valérie Coquand for supplying the components of the TAPIR switching cell (PCB, heat sinks, etc...).


Soleiman Galeshi
email: soleiman.galeshi-mooziraji@g2elab.grenoble-inp.fr

David Frey
email: david.frey@g2elab.grenoble-inp.fr

Yves Lembeye
email: yves.lembeye@g2elab.grenoble-inp.fr

Computational Cost Efficient Model of Losses for Multi-port Active-bridge Converters

Keywords: component, formatting, style, styling, insert (key

Multi-port active-bridge (MAB) converters, in single and clustered architecture, are used for many different applications. Due to intertwining of currents and powers of all their ports, finding a closed form solution for optimal control of single and clustered MAB converters that leads to highest efficiency is not an option. Therefore, optimization of power distribution in a cluster of MAB converters must be done by trial and error, which requires a model that can predict the losses. A detailed and accurate model of losses, however, would need large amounts of memory and processing resources, which makes real-time optimization of control and modulations costly, if not almost impossible. This work seeks to propose a computational cost efficient model, which is able to predict the losses with acceptable accuracy. Given the operating point of a MAB converter, this model is able to predict total losses using polynomial calculations. This efficient model can be employed for optimizing control of a cluster of MAB converters. Predictions of this model are compared against experimental measurements to validate its correct operation.

I. INTRODUCTION

Multi-port active-bridge (MAB) converters are finding their place in many different areas of industry because of their advantages, such as intrinsic galvanic isolation, soft switching, small passive components and bidirectional power transfer between multiple resources. They can be employed to transfer energy between generation, storage and consumption units; these three units can be in an electric car/aircraft [START_REF] Blanc | Optimization of a DC/DC dual active bridge converter for aircraft application[END_REF] or in a green building/micro-grid [START_REF] Galeshi | Application of Clustered Multi-port Active-bridge Converters in Microgrids[END_REF]. Their modular structure makes them a good candidate for distributed converter systems, where a cluster of converters work together to perform certain functions. They can be used in series/parallel to connect HVAC networks to dc networks [START_REF] Vermulst | Quad-Active-Bridge Single-Stage Bidirectional Three-Phase AC-DC Converter With Isolation: Introduction and Optimized Modulation[END_REF].

A power routing algorithm is proposed in [START_REF] Ko | Discontinuous Modulation based Power Routing for Modular Smart Transformers[END_REF] that tries to balance lifetime of parallel cascaded H-bridge and dual activebridge (DAB) converters based on junction temperature. It should be noted that MAB converters usually operate in soft switching condition and their switching losses are very small. Therefore, junction temperature cannot be a proper indicator of the total losses. Parallel operation of DAB converters connected for energy collection of wind farms is studied in [START_REF] Sang | Analysis and Control of a Parallel DC Collection System for Wind Turbines with Single Active Bridge Converters[END_REF]. The main goal in designing the controller in [START_REF] Sang | Analysis and Control of a Parallel DC Collection System for Wind Turbines with Single Active Bridge Converters[END_REF] is dynamic performance and stability. Employing a model of losses allows adding efficiency to the design optimization goals. Application of clustered MAB converters in smart buildings has been studied in [START_REF] Galeshi | Application of Clustered Multi-port Active-bridge Converters in Microgrids[END_REF], however, no optimization strategy is proposed for routing power between the converters. Several other works in the literature study control and power routing of parallel or clustered active-bridge converters, however they do not pursue optimal power distribution between them.

A general model of losses can be used to determine optimal power distribution in a cluster of MAB converters [6 PCIM]. Many works have studied losses in DAB converters. They propose analytical calculation for each type of losses in a DAB converter, including core losses, conductions losses, and switching losses. When determining losses in a DAB converter, only one phase shift can be defined. This phase shift easily gives the power and the current that flow between the two ports. The operating point parameters (voltages and currents) that are required for calculation of losses can be determined using polynomial equations in this case. However, in case of an n-port MAB converter, (n(n-1))/2 phase shifts can be defined between each pair of ports. There are (n(n-1))/2 power transfers between each pair of ports, too. The winding voltages and currents are affected by all the phase shifts at the same time. The shapes of transformer voltage and the currents get more and more complex and difficult to predict with an increasing number of ports. It will still be possible to calculate the losses in a MAB converter, but the number of calculations quickly increases. In case of a cluster of MAB converters, as described in [START_REF] Galeshi | Application of Clustered Multi-port Active-bridge Converters in Microgrids[END_REF][START_REF] Ko | Discontinuous Modulation based Power Routing for Modular Smart Transformers[END_REF], the optimization process would become even more difficult. This work seeks to present a simple, but accurate enough model for losses. This model can be employed in finding optimized modulation of a MAB converter and optimal power distribution in a network of clustered MAB converters. In the following sections, an overview of the losses in a MAB converter will be presented. The approximations that help reach the simplified model will then be explained. The final section presents experimental validation of the model.

II. LOSSE IN ACTIVE-BRIDGE CONVERTERS

A quad active-bridge (QAB) converter is illustrated in Fig. 1. This converter has four active-bridges, four inductors, and a four-winding transformer. The four active-bridges generate square-wave voltages with phase shifts between them. The phase shifts lead to flow of power between the ports. In this regard, the desired power transfer between the ports, are the inputs of the converter control system and the phase shift are the outputs. The model should be able to determine losses in the converter, based on the powers or their corresponding phase shifts.

Major types of losses in MAB converters are switching losses; conduction losses in the switches and windings of the inductor and the transformer; and, iron losses in magnetic cores of the inductors and the transformer. In order to assess the switching losses, voltages and currents at the switching A quad active-bridge converter with four active-bridges (the green box) and inductors (the blue box) and a four-winding transformer (the red box). moments are needed. Effective current value is the important parameter that should be determined to predict conduction losses. Core losses depend on shape and magnitude of magnetic flux density. Magnetic flux density itself can be determined from shape and magnitude of voltage across the windings on the core.

III. APPROXIMATION OF THE LOSSES

A. Scope of Application and Assumptions

Optimization in power electronic converters corresponds to various aspects, such as sizing magnetic components and semiconductors, thermal analysis, cooling system design, and switching modulations. These optimizations are performed through different approaches. The first approach is to determine the optimization goal as a function of input parameters and find the optimum using mathematical analysis. As systems are getting more and more complex, this approach is not always possible, i.e., it is not possible to determine a closed form solutions that gives the optimum point in big and complex systems. Numerical approaches, such as finite element analysis in thermal design, are able to find the optimum point whenever the analytical approach fails. The main drawback of numerical approaches is that they require large memory and processing resources and take a long time to find the optimum point. It means that numerical approaches are not the proper solution in real-time optimization and online control.

In cases where analytical and numerical approaches are not an appropriate choice for optimization, reduced order models (ROM) can be helpful. With the current trend of emerging more and more complex architectures in power electronics, ROM is becoming more relevant and useful in both academic and industrial applications [START_REF] Rolán | Reduced-Order Models of Squirrel-Cage Induction Generators for Fixed-Speed Wind Turbines Under Unbalanced Grid Conditions[END_REF][START_REF] Hao | Reduced-Order Small-Signal Models of Modular Multilevel Converter and MMC-Based HVdc Grid[END_REF][START_REF] Purba | Reduced-order Aggregate Model for Parallel-connected Single-phase Inverters[END_REF]. Reference [START_REF] Rolán | Reduced-Order Models of Squirrel-Cage Induction Generators for Fixed-Speed Wind Turbines Under Unbalanced Grid Conditions[END_REF] presents a ROM of and induction generator for fixed speed wind turbines. This model can be used in design and control of the generators. A ROM of modular multilevel converters (MMC) is presented in [START_REF] Hao | Reduced-Order Small-Signal Models of Modular Multilevel Converter and MMC-Based HVdc Grid[END_REF]. MMC is a clear example of large power electronic systems where ROM can be a handy tool. Reference [START_REF] Purba | Reduced-order Aggregate Model for Parallel-connected Single-phase Inverters[END_REF] studies a ROM for a network of arbitrary number of parallel single-phase converters. Considering the internal phenomenon of each converter and the possible dynamic interaction between the converters, the state and solution spaces are large. Therefore, analytical and numerical approaches will not be appropriate for optimization. The ROM in [START_REF] Purba | Reduced-order Aggregate Model for Parallel-connected Single-phase Inverters[END_REF] can be useful in dynamic analysis and control of parallel converters.

The goal of this work is to propose a ROM for MAB converters that can be used for control and optimization purposes, including optimal power flow in a cluster of MAB converters and internal control of a single converter. It should be noted that soft switching conditions in MAB converters allows operation with negligible losses at tens and hundreds of kilohertz. Considering the high frequency, switching losses would be too high if the control system was not able to maintain soft switching conditions. Therefore, it is assumed that MAB converters rarely operate at hard switching conditions and it is simpler to ignore the switching losses. It should be mentioned that one of the goals of clustering is to employ the converters near their nominal power, where their efficiency is high and soft switching conditions are met. Detailed switching process and calculation of soft and switching losses in MAB converters is presented in [START_REF] Galeshi | Design Procedure of DC-DC Multi-Port Active-Bridge Converters[END_REF].

Conduction losses have a direct relationship with resistance of transformer and inductor windings. These resistances can be analytically calculated for each converter based on the length and cross section area of the wires, in addition to some geometric parameters such as core size and winding fitting coefficients. However, the additional losses due to skin effect and eddy losses (because of proximity effect) cannot be ignored. Several works propose methods of calculation these effects, but doing so will add to complexity and computational cost of the ROM. In this regard, it is assumed that resistances of the windings are measured using an impedance analyzer at the switching frequency. On-state resistance of mosfet channel vary with operating conditions, too, but these variations are usually negligible compared to winding resistances. Hence, datasheet value of on-state resistance of the channels at designed gate-source voltage, nominal current and 75 °C is used in the model. Considering these assumptions, determining effective current magnitudes will be enough for prediction of conduction losses.

The ROM in this work is a series of mathematical calculations that gives an estimation of the losses in a MAB converter based on its design parameters, such as winding resistances, size of magnetic cores and dc link voltages, and operating point, i.e., phase shift between switchings of active bridges. Variation of parameters from their nominal value can affect the accuracy of the predictions. The extent of this impact will be studied in section IV.

B. Conduction Losses

Conduction losses occur in the channels of the mosfet switches and in the windings of the transformer and the inductors. In order to determine conduction losses, effective value of the currents should be calculated. Operating parameters of a sample switching of a QAB is shown in Fig. 2. It can be considered as a general set of voltage/current waveforms of a QAB converter. The phase shifts, from the smallest to the largest, are , , and , respectively. Based on Fig. 2, currents can be approximated as trapezoidal waveforms. The two currents that correspond to the smallest and the largest phase shifts have the same general shape (i1 and i4 in Fig. 2, respectively) and their trapezoidal approximation is shown in Fig. 3. In order to determine effective values of and , their maximum value is needed. This value can be determined from where, is the voltage across the inductor connected to the k-th active bridge. Approximation of inductor voltage integration will be presented later. Knowing the maximum value of a trapezoidal waveform, its effective value can be determined from

(2)
where, is the maximum value of the current, and .

The shape of the currents that correspond to the second and the third phase shifts, and is different from and . It is still possible to approximate their shape with a trapezoidal waveform, but with a slightly different approach. Fig. 4 displays three possible trapezoidal approximations of . Similar approximations are possible for . The effective current values resulted from these approximations were compared to effective value of the original waveform for different sets of phase shifts. The results showed that the approximation illustrated in green dotted line has maximum -3% error, while the dark blue and light blue had +30% and ±8% maximum errors, respectively. The maximum value of the approximation in green dotted line in Fig. 4 can be determined from inductor voltages (Fig. 5), and their effective value can be determined using Eq. ( 2) afterwards.

Approximated waveform (red) of the current (blue) in Fig. 2. Similar approximation applies to current . Vertical light green lines indicate phase shifts.

Trapezoidal approximations (dark blue, light blue and dark green) of the in Fig. 2 (red). Similar approximation applies to .

The voltages across the transformer and inductor windings. Voltage units are percentage of active-bridge dc link voltages (Fig. 1).

In order to determine the shape of inductor voltages, , the voltage across transformer windings, , has to be determined. Based on Fig. 1, , being the output voltage of the k-th active-bridge (the square-wave voltages shown in Fig. 2). Fig. 5 shows the general shape of transformer and inductor voltages. As shown in Fig. 5, inductor voltages have steps of ±150% and ±50% of the dc link voltage, depending on their phase shift. Width of these steps is equivalent to phase shifts indicated in Fig. 2. Integration of inductor voltages over half a cycle can be calculated as (3) to [START_REF] Galeshi | Design Procedure of DC-DC Multi-Port Active-Bridge Converters[END_REF]. Based on (2), maximum value of currents can be predicted as , or expressed as a matrix, , in [START_REF] Rolán | Reduced-Order Models of Squirrel-Cage Induction Generators for Fixed-Speed Wind Turbines Under Unbalanced Grid Conditions[END_REF].

Effective currents can now be determined as a matrix, , using ( 2) and ( 7).

1 0 0 1 0 1 0 1 1 0 1 0 1 0 0 1 [START_REF] Hao | Reduced-Order Small-Signal Models of Modular Multilevel Converter and MMC-Based HVdc Grid[END_REF] Knowing the effective currents, measured resistances of windings and datasheet value of drain source channel on-state resistance, total conduction losses in a MAB converter can be predicted.

( 1 )

 1 General voltage and current waveforms of a quad active-bridge converter. Measurement points are indicated in Fig.1. Each switching cycle has 2000 sampling points (horizental axis).

ACKNOWLEDGMENT

This work has been partially supported by the CDP Eco-SESA receiving fund from the French National Research Agency in the framework of the "Investissements d'avenir" program (ANR-15-IDEX-02).

C. Core Losses

Many works in the literature propose methods that can predict magnetic core losses. A commonly used method for this purpose is iGSE, proposed in [START_REF] Venkatachalam | Accurate prediction of ferrite core loss with nonsinusoidal waveforms using only Steinmetz parameters[END_REF]. It is method based on Steinmetz coefficients, which are determined through experimental measurements and curve fitting for different types of ferrite cores. The iGSE is well known to have accurate prediction of losses in ferrite cores when the voltage across is not sinusoidal, as in MAB converters. The main equation that gives the losses in this method is

where, , and are constants, related to the core material, is the core volume, is the switching frequency, and is magnetic flux density. The two important terms that should be evaluated are , maximum flux density, and

. The magnetic flux density itself can be calculated from [START_REF] Venkatachalam | Accurate prediction of ferrite core loss with nonsinusoidal waveforms using only Steinmetz parameters[END_REF] where N is the number of turns, and S is the cross section area of the core. Fig. 5 and (10) can help determine the two important parameters for calculations of core losses. The approach is similar to the previous section on prediction of effective currents. Maximum value of magnetic flux densities in inductor cores can be determined from [START_REF] Venkatachalam | Accurate prediction of ferrite core loss with nonsinusoidal waveforms using only Steinmetz parameters[END_REF] as in (11), and a coefficient matrix similar to the one in [START_REF] Rolán | Reduced-Order Models of Squirrel-Cage Induction Generators for Fixed-Speed Wind Turbines Under Unbalanced Grid Conditions[END_REF] gives the value for each inductor core.

(11)

The second term, , can also be calculated from Fig. 5. Based on the relationship between the voltage across the windings and the magnetic flux density in [START_REF] Venkatachalam | Accurate prediction of ferrite core loss with nonsinusoidal waveforms using only Steinmetz parameters[END_REF],

. Due to the abstract value, the coefficient matrix will be different from the one used for effective currents and maximum flux densities. Therefore, the second term can be calculated from

Although the shape of the voltage across the transformer winding is different from that of the inductor windings, the same concept can still be employed to determine losses in the magnetic core of the transformer. Based on Fig. 5 and (10)

2

(13) and ( 14)

IV. EXPERIMENTAL VALIDATION

A laboratory-scale QAB converter was built in G2ELab for experimental validation of the proposed model. Fig. 6 shows the converter. Table I lists some of its details. Transformer turns are equal on every ports and so are nominal dc link voltage and inductors. This converter can transfer maximum 250 Watts on each port at 40 V dc link voltage and 40 kHz switching frequency.

Validity of the model was tested at different switching frequencies and dc link voltages. A comparison between predicted and measured losses at 40 kHz switching frequency and dc link voltage of 40 V is illustrated in Fig. 7 for several operating points. In this test, two ports provided power and the other two acted as loads. The horizontal axis is the total power drawn from the sources. The total input power increases from 18 W up to 240 W. The difference between predicted and measured losses is indicated as "Error". Fig. 7 shows that there is a small error below 1 W. It varies between 0.3 W to 0.8 W and its average value is 0.6 W. This error can be due to approximations, difference between real and datasheet parameters, or accuracy of measurement devices. In any case, it shows that accuracy of the model in these operating points is in an acceptable range.

In order to verify that performance of the model remains acceptable with different dc link voltages and switching frequencies, the converter was tested with another set of operating points. The results are illustrated in Fig. 8. Dc link voltages in this test are 30 V and switching frequency is 20 kHz. The maximum power is limited is this case due to reduction of dc link voltages. The error in this test is between 0.2 W and 0.9 W, with average value of 0.45 W.

TABLE I. DETAILS OF THE PROTOTYPE CONVERTER

Parameter Value

Maximum DC voltage 40 V

Nominal power 250W each port

External inductors 10 µH

Transformer turns 7:7:7:7

Switching frequency 40 kHz

The quad active-bridge converter that was built in G2ELab for experimental validation of the proposed model of losses. The boxes numbere 1 and 2 are controller and signal conditioning circuit, respectively. The green and the blue boxes indicate the four active bridges and inductors, respectively. The red box is a four-winding transformer. The colored boxes correspond to the ones in Fig. 1.

Comparing the measured losses with the losses predicted by the proposed model. The switching frequency is 40 kHz and dc link voltages are 40 V. Efficiency of the converter is between 90% and 95%.

So far, the experimental results showed that the reduced order model is able to predict the losses with acceptable accuracy. However, there are situations where this model is not able to give an accurate prediction. These situations occur when operating conditions of the converter are far from its nominal values. Fig. 9 shows the results of experiments where one of the dc link voltages is 12% above its nominal value. Dc link voltage of one the ports is 28 V while the rest are 25 V. The power transfer in this test is lower than the previous tests because the dc link voltages are smaller.

The results show that in low power there error is relatively large. The reason for this increase is hard switching losses, which occur at low powers when there is dc link voltage variation. The reduced order model does not consider hard switching conditions and losses, hence the errors can be large when there is hard switching. As the power increases, soft switching conditions are met and switching losses become negligible, hence the error becomes smaller. However, when the power continues to increase further, circulating currents due to dc link voltage difference become large and increase the losses. The model does not currently consider losses due to dc link voltage variations and circulating currents, hence the error increases again.

V. CONCLUSIONS Application of multi-port active-bridge converters is increasing in many different applications. Considering the complexity of their internal phenomenon and large number of control parameters, finding analytical methods for real-time optimization of their control is not possible. Numerical methods can be useful but require large computational and memory resources. This work presents a reduced order model with low computational costs, that can predict losses in Comparing the measured losses with the losses predicted by the proposed model in a different operating condition. The switching frequency is 20 kHz and dc link voltages are 30 V.

Comparing measured and predicted losses when there is variation in dc link voltages. In this test, dc link voltage of all ports are 25 V, except for one, which is 28 V. Hard switching and circulating currents, which are not considered in the model, lead to large prediction errors. multi-port active-bridge converters. Some approximations were used in this model to reduce the computational cost. These approximations affect accuracy of the model. Experimental tests were performed on a laboratory-scale prototype of a four-port converter. The results showed that the accuracy is acceptable if the converter works in normal operating conditions. Additional tests were performed with variation from nominal value in one of the dc links. The results showed that large variations reduce accuracy of the model, i.e., care should be given when using the model. The control system should be able to avoid situations that deteriorate the accuracy of the model.