Jean Bruant Ovhcloud -Tima

Pierre-Henri Horrein

Ovhcloud Olivier

Muller Tima

Tristan Groléat

Ovhcloud Frédéric

Pétrot Tima

Towards Agile Hardware Designs with Chisel: a Network Use-case

Facing Distributed Denial-of-Service (DDoS) attacks that are growing in both number and intensity, cloud service providers' network stability is at stake. Mitigation systems must provide highly responsive lines of defense while handling terabits per second. Combining reconfigurability with guaranteed throughput and latency, FPGAs are recognized targets for high-speed network applications. Although traditional hardware development flows struggle to be responsive, hardware construction languages (HCLs) bring new opportunities to hardware development. This article showcases how Chisel HCL unleashes the power of agile development methodologies through three successive development iterations of a hash-table, a core network processing module in OVHcloud mitigation systems.

THE INTERNET TRAFFIC carries indifferently

legitimate and malicious packets, with among other risks, distributed denial of service (DDoS) attacks. These attacks aim at taking down a targeted cloud service -or even at unsettling a whole network infrastructure-by saturating network devices or computing resources [START_REF] Moore | Inferring internet denial-of-service activity[END_REF].

Only best-in-class network devices are able to handle the latest record-breaking DDoS attacks that reached peak traffic rate over 1.5 terabits per second (Tbps). To stay in business, cloud service providers are compelled to protect their customers and their infrastructures. This leads to a cat and mouse game, where attackers con-tinuously sharpen their strategies, and mitigations strategies must be continuously updated -often within days-to remain efficient.

As reconfigurable devices implementing digital circuits, FPGAs exhibit an interesting trade-off between performances and lifetime management, which makes them well-suited to build network processing systems. They indeed benefit from the digital circuits ability to accurately control both latency and throughput of implemented algorithms, while retaining update capabilities. However development is hindered by the time-consuming process of designing and implementing circuits for FPGAs using Hardware Description Languages (HDLs). To tackle this issue, previous research focuses on increasing the abstraction level of hardware development considering two main approaches [START_REF] Bacon | FPGA programming for the masses[END_REF] [START_REF] Shacham | Rethinking digital design: Why design must change[END_REF]. The first path consists in expressing functionality instead of describing hardware. This includes High-Level Synthesis (HLS), where software languages are compiled into hardware architectures, and Domain-Specific Languages (DSL), where domain-dependent primitives are provided to describe the design. The second path takes an opposite direction by bringing highlevel software principles into a hardware level abstraction, to provide advanced configuration and generation capabilities. This path led to the proposal of HCLs, such as Chisel [START_REF] Bachrach | Chisel: constructing hardware in a scala embedded language[END_REF] or PyMTL [START_REF] Lockhart | Pymtl: A unified framework for vertically integrated computer architecture research[END_REF].

To protect our worldwide network with more than 20 Tbps connected to the Internet, at OVHcloud we have developed our own anti-DDoS protection system which successfully mitigates thousands of attacks a day. It consists of multiple custom layers featuring both highperformance FPGAs and CPUs. Our aim being to keep hardware development synchronized with software continuous improvement, HDLs have not proven to be efficient, raising a need for an improved agile hardware development flow. After first adapting our organization to increase agility, we now need to move towards more flexible hardware design tools and languages to match the pace of software development [START_REF] Lee | An agile approach to building risc-v microprocessors[END_REF] [START_REF] Izraelevitz | Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations[END_REF]. As our main focus is to achieve agility through design iterations, we want to apply the principle of least power, which comes with the following philosophy: 1) Complexity is your enemy 2) Do not fear refactoring 3) Do not over engineer In this article we present how an higher abstraction can increase agility and allow an iterative process when implementing hardware network applications. Specifically this real industry-oriented use-case enables us to:

• discuss how existing higher-abstraction solutions can be leveraged and combined to improve the whole development process • demonstrate how HCLs can benefit hardware development and help building higher architectural abstractions of circuits, • show that adopting these solutions can also be done in an agile manner by integrating new developments in existing HDL projects, • evaluate the quality of HCLs generated circuits in terms of latency, throughput and resource usage against equivalent HDL implementations.

Already industrially used through the RISC-V project, we selected Chisel, a Scala-embedded HCL for our experiments. We first introduce an example of network application, focusing on existing high-level development tools. We then focus on a central function, the hash-table, describe the classic cuckoo hashing algorithm and dig into its iterative implementation as a Chisel hardware module. We show that the generated hardware is on par with our current, thoroughly optimized, SystemVerilog implementation both in terms of performances and resource usage. Finally we present our analyze of the advantages and drawbacks in the use of Chisel.

NETWORK APPLICATIONS

In order to design a DDoS filtering application, we need to collect statistics to decide if a flow is legitimate. This involves passive operations on the network, such as counting the number of packets originating from a source IP address. It may also integrate active network operation, such as sending reply packets to TCP connection requests, to check if the source is real or simply flooding the network. Based on theses statistics, a decision can be taken, These applications also have tight performance constraints, and must guarantee worstcase performances to avoid becoming DDoS targets themselves. Throughput performances of a network application are evaluated on both bitrate and packet per second (pps) scales. The packet rate target is computed for the worst-case: smallest packets -complete Ethernet packet of 84 bytes-at full bitrate. Considering the usual bitrate target for high-end network interfaces of 100Gbps, an up-to-date network-oriented FPGA board with 8 interfaces is expected to process 1.2Gpps for 800Gbps.

In a network application, some operations such as checksum computation are done at bitrate, while others such as packet filtering or state storage are done at packet rate. This leads to a conceptually simple architecture represented in Figure 1. Network packets are split into several chunks sequentially processed in the application. Operations are chained as a pipeline for operations occurring at bit level and a sufficient number of pipelines is instantiated to reach the required bitrate. These pipelines then access shared operations executed at packet rate. However, when going deeper into this simple architecture, complexity increases. First, the layered design of network protocols leads to complex developments and integration when new protocols need to be included. Second, network applications are stateful. For example, a rate limiter aims at limiting the incoming traffic from a given IP address. This is done by counting the flows from this address: each time a packet arrives, the IP addresses are extracted, the current number of packets is retrieved, and incremented. If the resulting number of packets is higher than a given threshold, the packet is dropped. This is a simple algorithm, but it requires to maintain the state (counter) associated with an address. The required size of state storage in the worst-case is obtained from target packet rate and retention time: 1.2Gpps with 1 second retention time requires storage for 1.2G flows.

Implementing network applications for FPGA targets with HDLs is feasible, but evolving towards faster development and deployment is desirable. DSLs are promising for defining an appliance at application level. Flow-Blaze [START_REF] Pontarelli | Flowblaze: Stateful packet processing in hardware[END_REF] is a DSL that provides a way to represent stateful applications. Another popular language is P4 [START_REF] Bosshart | P4: Programming protocolindependent packet processors[END_REF], which is designed to program network pipelines. It relies on an architecture representation which defines the capabilities of the underlying processing system, and on an application representation based on required fields and operations applicable on packets. Toolchains implementing P4 offer real improvements over baseline HDL implementation. They automate the tedious process of protocol implementation, thus limiting the usual errors in bit manipulation, and speeding up integration of new protocols. They also provide an implementation agnostic view of the application, which eases discussion with nonhardware specialists and helps focusing on the functionality instead of implementation details.

However, while P4 increases agility and expressiveness in this context, it is not sufficient. It relies on vendor IPs for function implementation, or on HLS when none exists. As HLS is not really adapted for these control-oriented applications, this leaves the implementation of missing functions unresolved. In our application, available state storage solutions were not satisfactory, as they were either too small, or not worst-case guaranteed. We heavily rely on QDR memories to mitigate this issue, which are not supported by the tools. The second issue with P4 is that production-ready implementations are vendor dependent. As cloud provider, we cannot depend on a single supplier and currently use both Intel and Xilinx FPGAs in our production environment. Using or developing vendor-agnostic tools could mitigate this issue, but the tight performance constraints will always lead to a need for custom implementations of critical functions. This means that agile development cannot be achieved only through the use of a network-related DSL.

CUCKOO HASH-TABLE ALGORITHM

As above-mentioned most network applications need to store per flow state. Given the range of potential source IP addresses (up to 2 128 for IPv6), the total number of flows is far too large to use standard memory. This problem further increases when the flow is defined with additional parameters, such as traffic category, internal profile, or both source/target addresses. In practice not all slots are required, and dictionaries can be used.

While specialized Content-Addressable Memories (CAMs) or Ternary CAM (TCAMs) are perfectly suited for dictionary hardware implementation, these highly specialized circuits are ill-suited to FPGAs. Efficient dictionary implementation is usually obtained through the use of hash-tables, which can be based on external memories, decoupling logic and storage functions.

We here focus on one particular hash-table implementation, based on the cuckoo hashing algorithm [START_REF] Pagh | Cuckoo hashing[END_REF]. This dictionary implementation provides worst-case constant lookup time while focusing on efficient memory space utilization. The present cuckoo hashing algorithm is based on N independent memory banks, respectively associated with N corresponding hashing functions. Cuckoo hashing is well suited to hardware implementation, as memory banks can be accessed in parallel.

Given a (key, value) pair, the N hash functions are applied to the key. Each resulting hash is the address of a slot in the associated memory bank. Any (key, value) pair can hence be stored in N different slots.

Given a key, the lookup operation is quite straightforward:

1) N hashes of the key are computed, 2) slots pointed by each hash are retrieved, 3) if the key is found in one of the retrieved slots, the associated value is returned.

The lookup operation execution time does not depend on where or when the data was stored, ensuring worst-case constant lookup time.

The insert operation is a bit more complex. Given a (key, value) pair to be inserted, the last step is replaced by: 3) Lookup for free slots: a) If at least one slot is free, randomly pick one of them for insertion, b) Otherwise swap the content of one randomly chosen slot with the (key, value) pair and go back to step 1).

The re-insert operations of overwritten (key, value) pairs are called moves. Having moves create a possibly infinite loop in the design, if no free slots are found for each successive move. This is avoided by limiting the number of reinsertions, dropping the last (key, value) pair when the limit is reached. This hash-table was already implemented and used in our anti-DDoS solution, with many improvements and variations to fit our usecases. As part of an ongoing migration of our applications from SystemVerilog to Chisel, we decided to re-implement it, starting with a very We target the following performance requirements:

• one operation per clock cycle, • a latency within hundreds of cycles, which is quite transparent at network scale.

The first design iteration is a core cuckoo hash-table module depicted Figure 2. Moves are blocking, with incoming requests stalled until the move is successful or the limit is reached.

The implementation process for this module is the same with Chisel or with SystemVerilog. The hardware description closely follows the linear pipeline architecture. Expressing this simple assembly of modules from a coarsegrained point of view is straightforward in both languages. This is expected from SystemVerilog, but it validates the fact that Chisel provides the necessary constructs to be used as a standard hardware description language. It also enables the inclusion of existing SystemVerilog modules as black-boxes, a mechanism used in this initial implementation to integrate our existing custom hash functions. While there is no significant gain in using Chisel at this point, there is also no loss in hardware expressiveness.

READ-MODIFY-WRITE ITERATION

As the second design iteration, we extend the initial implementation with the ability to process user-defined read-modify-write operations. This allows for example to increment a counter within a single request. A read-modifywrite operation consists of 3 successive steps:

1) lookup a (key, value) pair, 2) compute updated value given userdefined algorithm, 3) write result back to original memory slot.

The complexity of this iteration lies in the user-defined aspect of the modification. Adding an atomic read-modify-write is simply a matter of locking the table and inserting the userdefined function between the decision stage and the actual write to memory. But being able to externally provide the operation is not as simple. Our SystemVerilog implementation uses an external module for this operation, and carefully designed hardware ports, but this approach comes with many pitfalls. First, increasing the number of ports increases the complexity, reducing overall expressiveness of the source code. Modifying the function means ensuring that the connection is done correctly. It also implies a complex validation of the modifier, mocking the expected in-place integration. Secondly, providing a default modifier can only be done with a wrapper module or with generate statements, which limits code reuse. Lastly, the resulting hierarchy seen during verification and synthesis analysis presents the modifier outside of the main hash-table pipeline, resulting in harder debug and resources enumeration. In our anti-DDoS application, we use several different hash-tables, with different modifier functions. Limitations encountered using SystemVerilog for this simple read-modify-write upgrade are symptomatic of design patterns that prevent code reusability with HDLs. As upgrades come at high maintainability and ver-ification costs, full rewrite are often preferred in practice.

In contrast functional parameterization object inheritance in Chisel provides the ability to split roles. Users can instantiate the hashtable with any modifier function, provided that it fulfills the software interfaces documented below (for simplicity, we use a UInt as data type). Possible flavors of this parameterization are endless. For example, we could have used the build function as a parameter, but using a trait allows for more complex modifiers. We could also use a list of modifiers, along with a modifier selector mechanism, to implement different modifications in a single hash-table. With this approach, hardware interfaces are not growing out of control, hierarchy is preserved and a default child module generator can be provided to the module constructor, hence increasing reusability. Changes in code are quite limited and confidently integrated into the code base thanks to associated unit-tests. The flexibility offered by this parameterization hardly suffers from any limitation and greatly helps with integrating the Chisel implementation within our complex code base.

EXPERIMENTING WITH HASH FUNCTIONS

The hash function choice is a balance between resource usage and latency on one hand, and collision avoidance on the other hand. While redesigning our hash-table, we wanted to experiment with other hash functions, which is the subject of this third iteration.

In SystemVerilog, new hashes can be integrated in several ways: using hardware ports as above-mentioned; manually selecting the desired hash function within hash-table code; or with a generic parameter, coupled to an enumeration of known hash functions using generate statements. However, none of these solutions avoid modification of original code for each new hash function -or at the cost of complex and constrained interfaces. In Chisel, as described through the second iteration, functional parameterization allows fast integration of user-defined code without internal changes, thus easing design exploration and increasing reuse.

An interesting hash function candidate is the SipHash algorithm [START_REF] Aumasson | Siphash: a fast short-input PRF[END_REF] which was deemed one of the most performant hash [START_REF] So | Named data networking on a router: Fast and DoS-resistant forwarding with hash tables[END_REF]. Originally designed for software, it is highly sequential with multiple iterations of a computation -the sipround-over the input message. To integrate SipHash in our fully-pipelined architecture we need to unroll the sequential loops while duplicating the siprounds and chaining them through register stages. The number of siprounds is configurable and impacts the hash function properties. Within SystemVerilog, the usual way to deal with such variable length pipelines is to define an array of register stages. These stages are then connected using their respective indexes which results in low read-ability and highly error-prone code. Resorting to a to factorize sipround computations between registers stages is appealing. Unfortunately, SystemVerilog functions can hardly integrate registers, which prevents exploration of different registers configuration inside the stages.

In contrast Chisel supports recursive generating functions which are able to describe both the functionality and the pipeline details by inferring either registers or wires between stages. Hardware stages are defined during elaboration (i.e. the execution of these generating functions), leading to a very comprehensive match between the algorithm steps and the generated hardware stages.

This third iteration shows two other aspects of the usefulness of Chisel: the extended use of functions for both code generation and advanced software configuration. First, the possibility to instantiate hardware inside a function allows more natural expression of algorithms. Secondly, configuration functions can be defined as software within the hardware description, whereas for our SystemVerilog hash functions, a configuration file is generated using a Python script prior to hardware elaboration. This limits the number of errors, and interestingly speeds up simulation and synthesis, as the hardware is generated in a static form, as opposed to the SystemVerilog version where configuration file is read dynamically by the tools.

HARDWARE EVALUATION

The primary goal of languages is to allow efficient implementation in terms of resource usage and performance. In resources-constrained FPGA, a language must be chosen carefully in this respect. As we observed the same trend over numerous possible parameterizations, this section focuses on the result corresponding to the following configuration:

• 75 bits key width Moreover, synthesis time, omitted in this table, is up to 5 times lower for Chisel-generated Verilog than for SystemVerilog. This is mainly due to the fact that no generation occurs within Chisel-generated Verilog, which limits the required operations -and possible tool-related errors. Ease of use is also enhanced: a single file is generated for simulation, which can then be included directly in the synthesis tools for synthesis.

AGILE-FRIENDLY DESIGN

As demonstrated with this study, Chisel parameterization process greatly improves the flexibility and reusability of modules. While agility is achievable with SystemVerilog, iterations are limited by the low genericity of the language thus impacting the entire flow. Low flexibility leads to harder iterations, which in turn lead to bigger increments, as the integration of a feature overwhelms the time required to develop the said feature. When using Chisel, the entire focus is on small increments.

This improved agility also applies to the design and validation flow, presented in Figure 3, through the elaboration step. In SystemVerilog, each simulation or synthesis tool has its own elaboration process, supporting its own subset of the language. Simulation tools are usually more feature-rich, and synthesis tools limitations are found late in the flow, requiring a full rewrite of the already validated module. To avoid this, we usually stick to a very basic subset of the language, further limiting code reuse. Chisel elaboration ensures transformation of Chisel code to this basic subset. It also provides numerous checks such as types or combinational loop checking. As it occurs before functional simulation, this flow brings three major benefits. First, these checks do not need to be asserted during functional validation anymore. Secondly, many mistakes can be caught in a matter of seconds before any lengthy simulation start-up, which reduces iteration times and improves developer experience. Thirdly, the generated Verilog is compatible with all synthesis and simulation tools.

On the validation side, ScalaTest library natively provides test-cases management and straightforward integration of pass/failed results into continuous integration (CI) systems.

It allows testing of collections of programmatically defined parameter sets. For example, it's possible to routinely check all existing hash functions within a single test. Testbenches, also written in Scala, are fed to the Chisel-tester which provides bindings with fast open-source hardware simulators such as treadle and verilator.

In conclusion HCLs introduce more checking steps, taking place earlier in the validation flow, enabling faster iterations and hence improving the overall hardware development agility and predictability.

CONCLUSION

As designers of hardware network applications, we seek to improve development through agility. While the emerging DSLs such as P4 are promising for functionality description, the need for custom hardware functions remains. We developed a hash-table using Chisel as construction language and evaluated the contributions of the agility it provides. The highlevel constructs Chisel brings allow an actual iterative development, permitting small increments, with improved validation at each step. In the end, our hash-table was successfully integrated into the OVHcloud anti-DDoS mitigation system, with comparable resource usage and performance.

Designing generators instead of describing circuits proves to be an efficient approach which fully exhibits its agility as soon as successive design iterations occur. HCLs integrate powerful software engineering concepts into hardware development, unlocking higher abstraction levels while still mastering generated hardware. As a direct benefit, it becomes easier to build highly reusable design libraries. We now expect to reshuffle our vision of basicblocks integration in hardware network applications designs.

Figure 3 .

 3 Figure 3. Chisel design and validation flow

  Finally the HashTable module takes a Cuck-ooModifier as parameter, and uses it in its implementation.

	trait CuckooModifier {
	def build(valid: Bool, input: UInt)
	: (UInt, Bool)
	}
	The build function is the main function
	called in the hash-table to generate modifier
	hardware. The concrete modifier implementa-
	tion is then for example defined as the Incre-
	ment modifier below:
	class HashTable(
	val modifier : Option[CuckooModifier]
	= None
	// ...
	) extends Module {
	//...
	modData, modValid = modifier match {
	case Some(mod) => mod.build(
	lookupValid, lookupData)
	case None =>
	(lookupValid, lookupData)
	}
	//..
	}

object Increment extends CuckooModifier { def build(valid: Bool, input: UInt) : (UInt, Bool) = { (input + 1.U, valid) } }

Table 1 . Hardware resource usage comparison through iterations

 1

	• 21 bits address width
	• 69 bits data width
	• frequency: 200 MHz
	• device: Xilinx VU9P
	Table 1 summarizes the resource usage for


André Mégarbané
email: andre.megarbane@yahoo.fr

Sayeeda Hana

Stephany El-Hayek

Alicia Gambarini

Mahmoud Taleb

Valérie Delague

| Mahmoud

Taleb Al-Ali

Developmental delay, intellectual disability, short stature, subglottic stenosis, hearing impairment, onychodysplasia of the index fingers, and distinctive facial features: A newly reported autosomal recessive syndrome

Keywords: Developmental delay, intellectual disability, short stature, subglottic stenosis, hearing impairment, onychodysplasia of the index fingers, and distinctive facial features: A newly reported autosomal recessive syndrome consanguinity, dysmorphology, intellectual disability, malformation

à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

| INTRODUCTION

It is well established that consanguineous marriages can enhance the probability of rare genetic disorders in offspring. This has been clearly demonstrated in the Arab region, which exhibits some of the highest consanguinity rates worldwide [START_REF] Ozçelik | Collaborative genomics for human health and cooperation in the Mediterranean region[END_REF][START_REF] Teebi | Genetic disorders among Arab populations[END_REF]. The rate of consanguineous unions in the Arab world varies between 20 and 50%, with first-cousin marriages being the most common [START_REF] Tadmouri | Consanguinity and reproductive health among Arabs[END_REF]. These high rates of consanguinity have led to the immense burden of autosomal recessive genetic disorders in this region [START_REF] Teebi | Genetic diversity among the Arabs[END_REF].

In Syria, similar to other countries in the region, marriage between relatives has been a deep-rooted social, cultural and religious practice. The rate of consanguineous unions is 30.3% in urban Syrian populations and 39.8% in rural areas [START_REF] Othman | Prevalence of consanguineous marriages in Syria[END_REF]. Families often have multiple consanguineous marriages over generations resulting in a high burden of genetic disorders (Al-Gazali & Hamamy, 2014) and the emergence of novel autosomal recessive syndromes [START_REF] Abou Jamra | Homozygosity mapping in 64 Syrian consanguineous families with non-specific intellectual disability reveals 11 novel loci and high heterogeneity[END_REF][START_REF] Tawamie | Hypomorphic pathogenic variants in TAF13 are associated with autosomal-recessive intellectual disability and microcephaly[END_REF].

In this article, we describe two siblings from a multiply consanguineous Syrian family, with mainly developmental delay (DD), intellectual disability (ID), absent speech, hearing impairment, short stature, subglottic stenosis, dysmorphic facial features, and onychodysplasia of index fingers. Two other individuals from the extended family, with similar clinical features, are also described. Differential diagnoses and the possibility that we might be reporting a hitherto unknown syndrome are discussed.

| MATERIALS AND METHODS

| Subjects

The subjects were born to healthy second cousin Syrian parents. The siblings underwent extensive work-up including a thorough clinical evaluation, skeletal surveys, brain MRIs, echocardiography, and routine blood tests (complete blood count, serum electrolytes, blood glucose levels, cholesterol, thyroid, liver and renal function tests). Two other individuals, from the extended family were investigated remotely. They were not seen in our clinic as they live abroad, but their clinical description and medical history were shared by their parents.

| Molecular analysis

DNA isolation

Informed consent for genetic analysis was obtained from the individuals IV.4, V.2, V.3, and V.5 (Figure 1) in compliance with national ethics regulations. Genomic DNA was isolated from blood samples using standard techniques.

Genome-wide microarray CGH analysis

Genome-wide microarray CGH analysis was done for individual V.3.

Genomic DNA was amplified and purified. Following denaturation of probe DNA, hybridization was carried out with the affymetrix cytogenetics whole-genome 2.7 M Array following the manufacturers' standard protocol. Data was collected using GeneChip® Scanner 3000 7G and CEL files were analyzed using Affymetrix Chromosome Analysis Suite software (ChAS v.1.0.1).

Whole exome sequencing

Whole exome sequencing (WES) was carried out on four individuals: the two affected individuals (V.3 and V.5), the unaffected father (IV.4) and the unaffected older sister (V.2) (Figure 1). WES was performed by the Genomics and Bioinformatics Platform (GBiM) from the UMR 1251/Marseille Medical Genetics facility, using the NimbleGen SeqCap EZ MedExome kit (total design size 47 Mb) according to the manufacturer's protocol (Roche Sequencing Solutions, Madison). The SeqCap EZ MedExome kit targets the entire human exome with enhanced coverage of exons from medically relevant genes in Mendelian diseases. Enriched fragment libraries were sequenced on the Illumina NextSeq 500 platform (Illumina, San Diego, CA) using a 150 bp paired-end sequencing protocol. Raw data were mapped to the build of the human genome (hg19) by using BWA 0.7.5 [START_REF] Li | Fast and accurate short read alignment with burrows-wheeler transform[END_REF]. Variant calling was subsequently performed using GATK [START_REF] Mckenna | The genome analysis toolkit: A MapReduce framework for analyzing next-generation DNA sequencing data[END_REF] and annotation was done with ANNOVAR [START_REF] Wang | ANNOVAR: Functional annotation of genetic variants from high-throughput sequencing data[END_REF].

All subsequent steps were performed using VarAFT [START_REF] Desvignes | VarAFT: A variant annotation and filtration system for human next generation sequencing data[END_REF] (V.3 and V.5), which were also heterozygous in the obligate carrier father (IV.4). For the unaffected older sister V.2, two separate analyses were performed, taking into consideration that she could either be a heterozygous carrier or homozygous for the wild-type allele.

In order to refine the list of candidate nucleotide variations, filtering was performed by removing all variants with allele frequencies >1% in the genome aggregation database (gnomAD) database (http:// gnomad.broadinstitute.org/). Additional filtering was also performed using the GME database [START_REF] Scott | Characterization of greater middle eastern genetic variation for enhanced disease gene discovery[END_REF], as well as in-house exome databases which include the variants detected by exome sequencing.

In order to predict the deleterious effect of the identified sequence variations, different bioinformatics tools were applied; such as MutationTaster [START_REF] Schwarz | MutationTaster evaluates disease-causing potential of sequence alterations[END_REF] (http://www.mutationtaster.org/), SIFT [START_REF] Kumar | Predicting the effects of coding non-synonymous variants on protein function using the SIFT algorithm[END_REF] (http://sift.bii.a-star.edu.sg/) [START_REF] Kumar | Predicting the effects of coding non-synonymous variants on protein function using the SIFT algorithm[END_REF], PROVEAN (http:// provean.jcvi.org/index.php/) [START_REF] Choi | Predicting the functional effect of amino acid substitutions and indels[END_REF], PolyPhen-2 [START_REF] Adzhubei | A method and server for predicting damaging missense mutations[END_REF] (http://genetics.bwh. harvard.edu/pph2/), and UMD predictor (http://umd-predictor.eu/) [START_REF] Salgado | UMD-predictor: A high-throughput sequencing compliant system for pathogenicity prediction of any human cDNA substitution[END_REF].

| RESULTS

| Clinical report

For all affected individuals, delivery was normal with no recall of exposure to pre-or perinatal environmental toxins. Family history noted a possible affected aunt who died at age 12 from unknown reasons. She was described as having had a short stature, congenital onychodysplasia of the index fingers (COIF), and ID.

| Subject 1

This affected boy (V.3 in Figure 1) was seen in our clinics in Beirut, Lebanon at the age of 14 years and 4 months. He is the second child of the family. When he was born, the mother was 20 years old and the father 30. Birth weight was 3,500 g (60th centile), but neither the length nor the occipito-frontal circumference (OFC) measures were available. Since birth, one of the major complaints was an abnormal breathing and stridor. Developmental milestones were delayed, as he started walking without help at the age of 4 years but with an abnormal gait. He started to babble in syllables only at age 5. According to the parents, various investigations were performed in their own community in Syria, and reported as "normal."

F I G U R E 2 Frontal
When the boy was brought to us for consultation, he was cooperative, could understand simple orders, but could speak only a few words. His height was 139 cm (< 3rd centile), weight 31 kg (< 3rd centile), and OFC 52.2 cm (5th centile). He had a round face, thin lips, a short philtrum, long palpebral fissures with a total length of 3.5 cm (>97th centile), a normal inner canthal distance of 3 cm (Figure 2a); onychodysplasia of the index fingers, with anonychia in the left index and hemi-micro-onychia in the right one (Figure 3a); inverted left nipple; a genu valgum; and broad halluces (Figure 4a). Joint laxity, and 2 small café-au-lait spots were noted as well (Table 1). Neurological, heart examinations and echocardiography were unremarkable.

A skeletal survey revealed the presence of left lumbar scoliosis of 18 (Figure 5a). No skeletal abnormalities of the distal phalanges were noted.

Two years later, he was operated on for his scoliosis. At that time, his OFC was 53 cm (10th centile), height was 151 cm (< 3rd centile), and weight 40 Kg (< 3rd centile). A hearing assessment at the time showed a mild hearing impairment. A brain MRI was performed but did not show any remarkable findings. After the operation, the individual experienced severe respiratory difficulties and the medical staff considered that it was because of some inflammation of the trachea on a mild subglottic stenosis. At the most recent examination, at the age of 17 years, the individual weighed 42 kg, and his height was 156 cm, both measures below the third centile.

| Subject 2

Subject 2 (V.5 in Figure 1), a girl born 14 years after her affected brother was seen at age 2 months. At birth, her weight was 2,600 g (10th centile), length 47 cm (15th centile), and OFC 35 cm (50th centile). The parents noticed the onychodystrophy of index fingers directly at birth and thought that she had the same diagnosis as her elder brother (Figure 3b). At the time of first presentation at age 2 months, the baby girl weighed 3,000 g (< 15th centile), her length was 46 cm (< third centile) and OFC 37.5 cm (15th centile). She had the same clinical manifestations as her affected brother, in addition to a frontal bossing and a flat nasal bridge (Figure 2b). The length of the palpebral fissures was 3 cm (>97th centile), and the inner canthal distance 2.2 cm. External genitalia, neurological and heart examinations, brain MRI, as well as echocardiography and x-ray findings, were unremarkable.

At the age of 1 year, the parents noticed that she was not responding to sounds. Audiometry was performed and showed a severe hearing impairment, for which the girl received a cochlear implant. A few days later she had respiratory distress. Clinical investigation revealed a subglottic stenosis for which she was operated. At age 14 months she was diagnosed with epilepsy. At that time, her weight was 9 kg (25th centile), her length 72 cm (3rd percentile). She could stand and walk on her tip-toes with help.

At the most recent examination at the age of 40 months, she weighed 13.7 kg (25th centile), her height was 85 cm (<3rd centile) and her OFC 51 cm (75th centile). She was still unable to speak (Table 1).

Examination of the parents and their non-affected children showed a complete absence of all the features present in the affected siblings.

| Subject 3

Subject 3, a girl (V.7 in Figure 1), had nearly the same clinical presentation and evolution as her first cousins (individuals V.3 and V.5). Her birth weight was 2,000 g (< 3rd centile). A detailed clinical history since birth was not available but according to her parents, her major problems were her severe ID, and some breathing difficulties. She started to walk at the age of 3 years and said a few, often incomprehensible, words at the age of 4. At age 14, her height was 147 cm (3rd centile) and her OFC 53 cm (25th centile). She had the same dysmorphic features seen in her cousins with the addition of upslanting palpebral fissures (Figure 2c). Her toes were malpositioned and she also had broad halluces, but no onychodysplasia (Figure 3c). Similar to the other subjects, she had scoliosis and genu valgum. In addition, she had knee stiffness and restricted knee movement. Subglottic stenosis was diagnosed at age 9. Her parents noted that she was not responding to sounds unless they were very loud and suspected that like her cousins might have a hearing impairment (Table 1).

F I G U R E 3

| Subject 4

Subject 4, a boy (VI.2 in Figure 1), was 26 months of age when his clinical file was reviewed. Since birth, the parents noted respiratory difficulties and hypospadias. At 4-5 months of age, he required a tracheostomy after an unsuccessful attempt to repair a subglottic stenosis. He started to walk at the age of 2 years but still needed some help because of abnormal knee motion and severe genu valgum. Clinical description at the age of 26 months, showed that he had the same dysmorphic features as individuals 1 and 2 (Figure 2d), as well as joint laxity and broad abnormal halluces with onychodysplasia, but no scoliosis, possibly due to his young age (Table 1). His OFC was 46 cm (3rd centile), length 77 cm (< 3rd centile), weight 10.8 kg (10th centile).

According to his parents, his hearing has never been assessed.

It is important to note that individuals 3 and 4 were not clinically examined by us as they live abroad and presently have no access to healthcare facilities. The parents of individuals 3 and 4, as those of individuals 1 and 2, have reported a complete absence of the features exhibited by their affected children.

| Laboratory studies

Complete blood counts, serum electrolytes, blood glucose levels, triglycerides, cholesterol, amino acid studies of plasma and urine, urinary screening for organic acids, urinalysis, thyroid, liver and renal function tests, were all unremarkable in both siblings (individuals 1 and 2).

| Molecular studies

Array-CGH analysis for submicroscopic deletions/duplications performed in the boy revealed no causal CNVs.

We then carried out WES on individuals 1 and 2 (V.3 and V.5), their unaffected father (IV.4) and their unaffected older sister (V.2) (Figure 1). Following the first hypothesis (V.3 and V.5 homozygous, IV.4 heterozygous, and V.2 heterozygous), we obtained 697 variants, of which only 9 had a frequency below 1% in the gnomAD and GME data set. Of these 9, 6 were frequent (>10%) in our local database and the other three were either false homozygous or sequencing errors. Moreover, none of the nine variants were in the coding region.

Following the second hypothesis (V.3 and V.5 homozygous, IV.4 heterozygous and V.2 homozygous for the normal allele), we obtained 51 variants, of which 4 had a frequency below 1% in the gnomAD and GME datasets. After applying the local database filter, no variant remained.

| DISCUSSION

The clinical features of the individuals reported here consist of DD, ID, absent/rudimentary speech, hearing impairment, short stature, subglottic stenosis, dysmorphic facial features such as a round face, long palpebral fissures, thin lips and a short philtrum, onychodysplasia of index fingers, and malposition (Table 1). No other ectodermal abnormalities were noted. All subjects exhibited genu valgum except for individual 2. This distinct clinical presentation of the four subjects does not conform to any well-delineated syndrome, raising the possibility of it being a previously unseen disorder. One remarkable feature we report here is the onychodysplasia of the index fingers. COIF, known also as Iso-Kikuchi disease (Iso, 1969;[START_REF] Kikuchi | Congenital onychodysplasia of the index fingers[END_REF], is a rare disorder characterized by the following five criteria: congenital occurrence, unilateral or bilateral nail dystrophy of the index fingers, variability in nail appearance, bone abnormalities, and possible autosomal dominant inheritance [START_REF] Baran | Congenital onychodysplasia of the index fingers. Iso and Kikuchi syndrome[END_REF]. In the present subjects, there were no bone abnormalities and the inheritance seemed mostly autosomal recessive.

Furthermore, in COIF, no short stature or ID have been described. [START_REF] Franceschini | Peculiar facial appearance and generalized brachydactyly in a patient with congenital onychodysplasia of the index fingers (Iso-Kikuchi syndrome)[END_REF] described a COIF patient with mild ID, dysmorphic facial features, and inguinal hernias. However, the ID was considered to be caused by his epilepsy, and his facial features were distinct from those reported here'. In addition, other important features seen in the individuals reported herein, such as DD, subglottic stenosis, short stature, and absence of speech were not found in the individual described by [START_REF] Tonoki | A new syndrome of dwarfism, brachydactyly, nail dysplasia, and mental retardation in sibs[END_REF] were all ruled out because of the absence in the present cases of the major features seen in these syndromes. Furthermore, known genes involved in the latter syndromes were fully covered by our exome analysis and were found to be normal. Ectodermal dysplasia syndromes that can present with nail dysplasia were also ruled out because of the normal skin, hair, and teeth.

The presence of subglottic stenosis in all four of the subjects is another intriguing finding. Congenital subglottic stenosis, defined as a partial or complete narrowing of the endolarynx, is generally seen as a sporadic occurrence and is rarely found to run in families [START_REF] Manickavasagam | Congenital familial subglottic stenosis: A case series and review of literature[END_REF].

Depending on the severity of obstruction, stenosis is classified into grades I to IV where grade IV indicates a complete obstruction and no detectable lumen [START_REF] Cotton | Management of subglottic stenosis[END_REF]. In the present cases, individuals The facial features reported here consist of a round face, long palpebral fissures, thin lips and a short philtrum. Individually, these features are observed in several other syndromes. For instance, hyperphosphatasia (OMIM 239300), Kabuki syndrome (OMIM 147920), and KBG syndrome (OMIM 148050), all feature long palpebral fissures, however they lack other phenotypic characteristics exhibited by the four subjects. Collectively, the facial dysmorphic features observed here result in a distinct appearance, not seen in other syndromes.

Broad halluces, with or without hammer toes, are featured in several syndromes, the closest of which to the syndrome described here are Rubinstein-Taybi syndrome (OMIM 180849) and a syndrome described by [START_REF] Nampoothiri | Macrostomia, thin upper vermilion border, long philtrum, broad halluces, and intellectual disability in two sibs[END_REF]. The former has been ruled out by different facial features, as well as general thumbs and toes aspects in the individuals reported here. Moreover, Rubinstein-Taybi syndrome shows autosomal dominant transmission, which is unlikely in the family reported here. [START_REF] Nampoothiri | Macrostomia, thin upper vermilion border, long philtrum, broad halluces, and intellectual disability in two sibs[END_REF], described two siblings who share certain features with the subjects described here such as ID, hearing impairment and broad halluces, but with different facial features and normal stature. Furthermore, the two siblings did not exhibit the nail onychodysplasia and subglottic stenosis described here, also absent in individuals with Rubinstein-Taybi syndromes.

Based on these findings, it is believed that the four individuals represent a previously unseen autosomal recessive syndrome. While WES failed to identify the causal variant(s), it is hoped that whole genome analysis will clarify the gene(s) involved. In conclusion, we report here a multiply consanguineous Syrian family where four young subjects and possibly a deceased aunt presented a unique cluster of anomalies. The marked level of consanguinity in this pedigree indicates an autosomal recessive inheritance of a syndrome not previously described. The defining phenotypic features of this syndrome will be better outlined once more families are diagnosed with this novel syndrome.

  (Variant Annotation and Filter tool), an in-house variant filtering and prioritization tool allowing easy and fast selection and segregation of variants from exome or genome data (http://varaft. eu/). Considering autosomal recessive inheritance and the presence of consanguinity in the family, we segregated the variants from exome data following a homozygous by descent model. More precisely, we selected homozygous variants shared by the two subjects F I G U R E 1 Pedigree of the reported family. Black symbols indicate affected individuals. Double lines indicate consanguineous marriages

  views of individual 1 (a), 2 (b), 3 (c), and 4 (d) at the ages of 15 years, 7 months, 14 years, and 2 years, respectively. Note the thin lips, short philtrum, long palpebral fissures in all four subjects. Distinguishing features include inverted left nipple in individual 1 and upslanting palpebral fissures in individuals 2 and 3 [Color figure can be viewed at wileyonlinelibrary.com]

  Images of subjects' hands. Note the onychodysplasia of the index fingers in (a) individual 1, (b) individual 2, and (c) individual 4 [Color figure can be viewed at wileyonlinelibrary.com]

F

  I G U R E 4 Images of feet showing the abnormal halluces and toes. (a) Individual 1, (b) Individual 2, (c) Individual 3, and (d) Individual 4 [Color figure can be viewed at wileyonlinelibrary.com] T A B L E 1 Summary of clinical features in the four reported subjects

F

  I G U R E 5 Images highlighting individual 1's scoliosis (a) and individual 2's genu valgum (b) [Color figure can be viewed at wileyonlinelibrary.com]

Franceschini

  et al. Other syndromes with nail abnormalities have also been described. Congenital anonychia (OMIM 161050; 206800) lacks skeletal abnormalities of the distal phalanges such as in the individuals reported herein, but all nails are usually affected. The nail-patella syndrome (OMIM 161200), Poland syndrome (OMIM 173800), DOOR syndrome (OMIM 220500), and Tonoki syndrome (Tonoki, Kishino, &

2 and 4

 4 were found to have a grade III, while the other two subjects were seen to have a grade II. The subjects were evaluated for syndromes with subglottic stenosis as a feature, including trisomy 21, Chromosome 22q11.2 deletion syndrome (OMIM 611867), Geleophysic Dysplasia 3 (OMIM 617809), psychomotor retardation, epilepsy and craniofacial dysmorphism (OMIM 614501), none of which fit the phenotype seen in this study. Additionally, analysis of the genes associated with these disorders did not uncover any mutations.

  To confirm our findings a thorough search was conducted in the face2gene database (http://suite.face2gene.com/lmd/), the POSSUM databases (http://www.possum.net.au), the Online Mendelian Inheritance in Man (https://www.omim.org/), and PubMed (https:// pubmed.ncbi.nlm.nih.gov/). All differential diagnoses were considered with syndromes presenting at least 2 of the pertinent features. None were retained as a possible diagnosis in this case.

ACKNOWLEDGMENTS

We are thankful to the family for their cooperation and sharing of clinical information, despite being abroad.

DATA AVAILABILITY STATEMENT

Data sharing is not applicable to this article as no new data were created or analyzed in this study.

CONFLICT OF INTEREST

The authors declare no potential conflict of interest.

AUTHOR CONTRIBUTIONS

André