text:
User talk:72.145.138.57

Please don't blank sections of books without leaving some justification for doing so on that book's talk page. Thanks! --Jomegat (talk) 22:42, 29 April 2008 (UTC)

title: User talk:72.145.138.57


text:
Futurebasic/Language/Reference/usr abs

USR ABS(expr)

 Description  This function returns the absolute value of expr.

The absolute value of a number is its distance from zero: the absolute value of -23 is 23; the absolute value of 16 is 16.

USR ABS is slower than the ABS function, but it is included for backward compatibility.

 See Also  ABS

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: Futurebasic/Language/Reference/usr abs


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Futurebasic/Language/Reference/usr applescriptgetresult

USR APPLESCRIPTGETRESULT

Revised June, 2003 (Release 8)

Description - This routine returns a handle pointing to the data in memory returned by an AppleScript script executed with USR APPLESCRIPTRUN or USR APPLESCRIPLOADANDRUN. If there is no result or if the routine fails to retrieve the data, the value returned by USR APPLESCRIPTGETRESULT is _nil. You are responsible for the disposing of the handle returned (if any). You must be aware that the routine empties the AppleScript internal buffer. You could possibly use the USR APPLESCRIPTGETRESULT function to retrieve the text source of your entire script right after storing it into the AppleScript buffer using the ROUTE and PRINT statements, however you cannot expect to compile and execute the script afterwards, since the buffer would be empty. In a general manner, you must call the USR APPLESCRIPTGETRESULT function after a script has been executed whether an error occurred or not and dispose of the handle returned if any and if necessary.

Example: The following example will return the list of all the folders located at the root level of your hard drive:

INCLUDE "Subs AppleScript.Incl" DIM AS STR255

DIM AS HANDLE textH

DIM AS RECT r WINDOW 1

CALL SetRect

CALL InsetRect( r, 32, 32 )

''' NEED LINK!!! ''' EDIT FIELD 1,"",@r ROUTE _toAppleScript

PRINT "the name of every folder of the startup disk"

''' NEED LINK!!! ''' ROUTE _toScreen err = USR APPLESCRIPTRUN

H = USR APPLESCRIPGETRESULT

LONG IF H  TESetText([H],FN GetHandleSize(H), TEHANDLE(1)) DisposeHandle( H ) CLS XELSE EDIT$( 1 ) = message$ END IF See Also: USR APPLESCRIPLOADANDRUN; USR APPLESCRIPTRUN


text: User talk:68.237.247.30

title: User talk:68.237.247.30


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Futurebasic/Language/Reference/usr applescriptloadandrun

USR APPLESCRIPTLOADANDRUN

Revised June, 2003 (Release 8)

Description - This routine loads and executes the AppleScript script specified by resID% and located in the file specified by fSpec. If the routine fails to launch the script errorFlag is set to a non-zero value. If the script returns a result, you can get a handle pointing to the data using the USR APPLESCRIPTGETRESULT function. Note that the script might also return an error in the AppleScript buffer, therefore you should always empty the buffer after a script has been executed getting the result with USR APPLESCRIPTGETRESULT then disposing of the handle returned if any. fSpec is an FSSpec record specifying an existing file. If you pass _nil for the fSpec parameter, the script will be retrieved from the resource fork of the running application.

Note: Usually, resID% is set to 128 which is the default resource ID for Apple's compiled scripts. However, if you pass 0 for this parameter, the routine will assume an ID of 128, thus USR APPLESCRIPLOADANDRUN(0,0) is functionally equivalent to USR APPLESCRIPLOADANDRUN(appSpec,128). In order for the script to function properly, your program must have entered its main event loop before it attempts to run the script.

See Also USR APPLESCRIPTGETRESULT; USR APPLESCRIPTSTORE


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Chess Opening Theory/1. d4/1...d5/2. Bf4

= The London System =

Introduction

Within the vast tapestry of chess openings, the London System stands out, illuminating the board with its unique blend of simplicity and depth. In the constantly evolving meta of chess, this opening has demonstrated its timeless allure, captivating novices and grandmasters alike. Its simplicity, harmoniously combined with the promise of latent aggression, has anchored its place in modern chess.

Opening Concept

The London System is not just a series of moves; it's a philosophy. Beginning with the move 1.d4, White unveils the first step in a dance that revolves around a solid pawn structure in the center. This shield of pawns, bolstered by the knight on f3 and the dark-squared bishop on f4, serves as the backbone of White's position, challenging Black to find the chinks in the armor.

 * The London is setup-based, meaning the development is usually consistent and not riddled with tricky lines. The London System offers a consistent setup but requires the player to be adaptable based on the opponent's moves.
 * Players often develop pieces similarly, regardless of many of black's responses, ensuring a safer exit from the opening phase. It's essential to watch the opponent's setup to determine the best continuation.
 * Aim to put early pressure on the opponent, especially when they diverge from standard setups.
 * Maintain Flexibility: Keeping options open in the opening can help adapt to the opponent's moves.
 * Delaying Captures: Strategic patience is vital. Avoid rushing captures, especially when the opponent's pawn structure is tough to exploit.
 * Optimal Piece Placement: Before initiating an attack or capture, ensure all pieces are ideally positioned.
 * Exploiting Weaknesses: Target weaknesses, like the a6 pawn in the example, by accumulating attackers against a single point.
 * Knight Placement: Ensure knights are positioned to control or support crucial squares, especially the e5 and c5 squares.
 * Rook Activity: Use rooks to control open files and exert pressure, as seen with the a6 pawn capture in the game example.

 History

Origins

The inception of the London System can be attributed to the brilliance of James Mason, a luminary in British-American chess circles. His influence is particularly notable in tournaments such as Vienna (1882), London (1883), and New York (1889).

Evolution over the Years

While the London System took time to gain traction, certain trailblazers like F.J. Lee, Joseph Henry Blackburne, and Akiba Rubinstein consistently demonstrated its capabilities. The system earned its moniker from its prominent display at the celebrated 1922 London tournament, a gathering of chess greats including José Raúl Capablanca and Alexander Alekhine. The roots of the London System trace back to its iconic pawn structure. Over time, as chess literature expanded, this system was recognized and embraced. Time brought refinement to the London System. As Black devised varied counterplays, White's approach matured, leading to intricate and innovative gameplay patterns that enriched the legacy of the London System.

Modern Adoption

The 21st century heralded a London System revival, especially at the club level. Grandmasters like Gata Kamsky, Levon Aronian, and Magnus Carlsen became its champions, showcasing its power in pivotal matches. This was underscored when the London System became the centerpiece in the 6th round of the 2023 World Chess Championship, featuring a duel between Ding Liren and Ian Nepomniachtchi. In contemporary chess, the London System remains a timeless classic. Its adaptability allows White to respond resiliently to Black's maneuvers, making it a favorite for players from all echelons of the chess community.

Core Set-up and Typical Moves

 * 1) d-Pawn Opening: The London system starts with the d-pawn, giving a strong presence in the center right from the start.
 * 2) The quintessence of White's strategy aims to form a solid pawn structure, typically resembling a pyramid, solidifying the position around the moves d4, Nf3, Bf4, e3, Bd3, Nbd2, and c3. An auxiliary move, h3, acts as a lifeline, providing the f4 bishop a haven at h2 when under duress.
 * 3) Bishop on f4: A signature move in the London System and the heart and soul of the London System reside in its core setup.
 * 4) * Light-Square Bishop Activity: A crucial piece in this opening, targeting weak pawns, especially on the queenside.
 * 5) * Controls a key diagonal for potential tactics. it pressures black and controls a diagonal.
 * 6) * Trading Bishops: Offer or accept bishop exchanges strategically. Sometimes it's beneficial to keep the bishops on the board for positional advantages.
 * 7) * Helps in central control, focusing on the e5 square.
 * 8) e5 Square: A key battleground. White aims to either station a knight here or maintain stringent control to prevent black's e5 push. Central to White's plans is the knight's elevation to e5, exerting significant pressure on Black. This central dominance often opens avenues for aggressive kingside pursuits. The essence of the London System is its tactical depth. The pawn pyramid, a hallmark of this strategy, along with the tactical maneuvers of Knight to E5, offers White an array of offensive possibilities.
 * 9) Centralized pawns fortified by the knight's development to f3 and the dark-squared bishop's aggressive positioning create a solid foundation for White's gameplay.

Adapting to Different Setups

 * King's Indian and Other Setups: On moves like g6, the recommendation is to opt for Knight c3, potentially leading to aggressive lines including an early h4 push, targeting a kingside pawn storm.
 * Queen's Gambit Setup: If the opponent aims for an early LightSquared Bishop development, consider transitioning into a Queen's Gambit with c4, aiming for Queenside pressure.
 * Evasive Moves: On moves like a6 or h6, consider developing naturally, but keep an eye out for potential tactics or aggressive pawn pushes in the center.

Starting moves: d4, d5, Bf4

 * Monitor for moves like c5, early development of the LightSquared Bishop, and other central strategies.
 * Prioritize moves that strengthen the central pawn structure and control key squares.
 * Be wary of early c5 pushes by Black. Instead of capturing, focus on fortifying your center and continuing development.
 * Consider variations like the modern approach where c3 is postponed, focusing on Knight development first.

Aggressive Variations

 * Early Knight c3 and h4-h5: These tactics can be used against setups like the King’s Indian and can lead to potent attacks on the opponent’s position, particularly the kingside.
 * Jobava London Variation: This features early Knight c3 against c5 systems, leading to unpredictable and aggressive play.
 * Bishop Deployment: In positions where Black challenges your dark-squared bishop early, consider sliding the bishop back to g3, potentially opening the h-file for future tactics.
 * Pawn Storm: In certain positions, aggressive pawn storms like f4, combined with piece activity on the kingside, can lead to strong attacking chances.

Black Responses and Strategies
Primary Defense Systems

The London System's restrained nature grants Black a myriad of defensive avenues, ranging from the Queen's Gambit Declined-style to the more hypermodern Queen's Indian-style defense. The essence of the London System is its tactical depth. The pawn pyramid, a hallmark of this strategy, along with the tactical maneuvers of Knight to E5, offers White an array of offensive possibilities.

Adapting to White’s Play

Black's strategies in the London System are fluid by necessity, often oscillating between offense and defense in response to White's overtures. Given the London System's formidable presence, Black often finds themselves oscillating between aggressive and passive play, adapting fluidly to White's strategic ploys.

Black's Counterattacks and Breaks:

One of the critical responses by black is the early c5, challenging white's center, followed by the disruptive ...Qb6. This tactic targets the vulnerable b2-pawn, attempting to destabilize White's harmonious progression.

 Traps and Tactical Ideas

For White

 * 1) The London system offers tactical opportunities, especially when pieces are aligned favorably.
 * 2) Discovery checks, using the alignment of the queen with the opponent's king, can be potent, leading to winning material. Moves like the unexpected Bishop takes h7, followed by Qh5, exploit pins and open the door for quick checkmates.
 * 3) While the London System is undoubtedly challenging, it is not insurmountable.
 * 4) Embedded within the London System's structure are several tactical traps. Moves like Knight takes F7 showcase White's tactical brilliance, often catching Black off-guard.

For Black

 * 1) Despite the challenges the London System poses, Black has their own set of traps. By capitalizing on White's potential over-extensions, Black can initiate swift counterattacks, often turning the tables in their favor.
 * 2) Black can capitalize on White's overextensions, devising traps that swiftly swing the game in Black's favor.
 * 3) By capitalizing on moves like Pawn to c5, Black can disrupt White's momentum, creating tactical opportunities to seize the advantage.

 Drawbacks and Criticisms

Limitations

There exist certain board positions where the London System might not present White with optimal chances, underscoring the importance of adaptability. Despite the challenges the London System poses, Black has their own set of traps. By capitalizing on White's potential over-extensions, Black can initiate swift counterattacks, often turning the tables in their favor.

Criticisms

The London System often faces criticism for its perceived passive stance. However, these views may not account for its concealed aggressive potential.

 Conclusion

 * 1) The London System, while steeped in tradition, remains a formidable tool in contemporary chess.
 * 2) It provides a solid, consistent framework, emphasizing a sturdy pawn structure and central control, making it a go-to choice for players across all levels.
 * 3) It promises both stability and surprise, making it a worthy choice for players looking to deepen their strategic repertoire.
 * 4) The London System is a rich opening with a focus on a robust pawn structure and efficient piece development. By understanding the nuances of pawn structure and bishop mobility, players can navigate the complexities of this opening to achieve positional and tactical.
 * 5) Detractors argue that the London System, for all its structure, might verge on the monotonous. However, this criticism often overlooks the rich tactical depth this opening offers.

Theory table
. '''1. d4 d5 2. Bf4'''


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Futurebasic/Language/Reference/usr applescriptrun

USR APPLESCRIPTRUN( errorMessage$ )

Revised June, 2003 (Release 8)

Description - This function compiles and executes an AppleScript script that has been previously stored in FB's AppleScript internal buffer with the ROUTE statement. The result returned by the routine is in the form of a flag that indicates whether the script was successfully compiled (_noErr) or if the operation has failed (non-zero value). The errorMessage$ parameter will contain the result of the script (if any) or a human friendly error message from AppleScript. The errorMessage$ variable is set up to contain up to 255 characters, consequently if the result of the script is larger than the maximum allowed, you will not get the full data returned by the script. In such case you may wish to use the USR APPLESCRIPTGETRESULT routine to get a handle to the entire result. In any case you must call that function to empty the AppleScript buffer and dispose of the possible handle returned. Example:

The following example will return the file access path of the running application:

INCLUDE "Subs AppleScript.Incl"

DIM err

DIM reply$ or DIM reply AS STR255 ''' NEED LINK!!! ''' ROUTE _toAppleScript

PRINT "path to me as string"

ROUTE _toScreen err = USR APPLESCRIPTRUN

IF err = _noErr THEN PRINT reply$ resultHandle = USR APPLESCRIPTGETRESULT

IF resultHandle THEN CALL DisposeHandle( resultHandle )

Program output: Macintosh HD:AppleScriptRun folder:FB_Temp Note: In order for the script to function properly, your program must have entered its main event loop before it attempts to run the script.

See Also USR APPLESCRIPTGETRESULT; USR APPLESCRIPTSTORE


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Futurebasic/Language/Reference/usr applescriptstore

Usr AppleScriptStore(fSpec, resID%, scriptName$)

Revised August, 2002 (Release 7)

Description - This routine saves a compiled script into the resource fork of the file specified by fSpec with a resource ID and a resource name specified respectively by resID% and scriptName$. Once you have filled the AppleScript internal buffer with the Route and Print statements, you may wish to store the script permanently in compiled format for later use. The resulting script file can be run with the Usr AppleScriptLoadAndRun routine as well as with any application that can run AppleScript scripts such as Apple Script Editor. fSpec is an FSSpec record that specifies a file. If the file doesnÕt exist, it is created. If you pass _nil for the fSpec parameter, the resulting compiled script will be stored in the resource fork of the running application. resID% is usually set to 128 (the default resource ID for AppleÕs compiled scripts), and if you pass zero for this parameter the routine will assume an ID of 128. The routine will override any existing script having the same ID in the file specified.

For example, Usr AppleScriptStore would store or replace in the resource fork of the running application a script with resource ID 128 whose resource name would be ÒMy ScriptÓ. You can pass a null string for the scriptName$ parameter.

Note In order for the script to function properly, your program must have entered its main event loop before it attempts to run the script. The AppleScript routines are made available to your program with the following Include statement:

Include "Subs AppleScript.Incl"

See Also: Usr AppleScriptGetResult; USR APPLESCRIPLOADANDRUN


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Futurebasic/Language/Reference/usr convertimagefile

USR CONVERTIMAGEFILE(srcName$,srcRef%,¬ destName$,destRef%,newTypeIn&,newCreator&)

Revised June 2001 (Release 5)

Description - This function takes the picture information from one disk file and translates it into a different format. A new file is built with the correct file type and creator in the location that you determine. If the final four parameters are left blank, QuickTime will bring up a "Save As..." dialog so that you may specify the type of file, its name, and its location. The following example opens a graphic file and translates it into any specified format.

Include "Subs Image Files.Incl" gFBUseNavServices = _zTrue  WHAT IS THIS!!!

dim fName$,err dim @vRef% fName$ = files$(_fOpen, "Locate a picture",vRef%) long if fName$[0] err = USR CONVERTIMAGEFILE(fName$,vRef%,"",0,0,0)

end if Note: Before you can use this function, you must include it in your project with the following statement: include "Subs Image Files.Incl"

See Also USR IMAGEFILETOPICT, USR SAVEIMAGEFILEASPICT


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Futurebasic/Language/Reference/usr copyfile

USR COPYFILE(SrcName$, SrcVol%, SrcDir&, ¬ DestName$, DstVol%, DstDir&)

Revised FEBRUARY, 2002 (Release 6)

Description - This function copies a file from one location to another. If the copy is successful, the function returns _noErr (zero). If the copy fails, a file error code is returned. In the process of this operation, the original file is left intact. The source and destination folders may be the same if the file name is different.

Example:

The following example allows the user to select a file and a new destination before calling the USR COPYFILE function.

INCLUDE "Util_Files.incl" DIM filename$,folderName$,destName$ DIM @vRefNum%,destVref% DIM err fileName$ = FILES$(_fOpen,,"Select a file to move",vRefNum) LONG IF LEN(fileName$) folderName$ = FILES$(_fFolder,,,destVref%)   LONG IF LEN(folderName$) destName$ = "Copy of" + filename$ err = USR COPYFILE(fileName$, vRefNum, ¬ 0, destName$, destVref, 0) LONG IF err PRINT "File was not copied." XELSE PRINT "File copy successful." END IF  END IF END IF

''' LOTS OF MUMBO JUMBO!!! '''

See Also USR MOVEFILE; RENAME; FILES$


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Futurebasic/Language/Reference/usr dynamicitemsize

USR DYNAMICITEMSIZE( arrayPtr& )

Revised: November; 2006 (FB 4, Release 4)

Description - This function returns the element size specified when the array was DIMensioned. This is a runtime equivalent of SIZEOF( gMyDynamicArray ), which is actually a compiler directive. It is for use in generic functions where only the address of the dynamic array is known to avoid the necessity of passing the size as a parameter.

Note: Whether currently populated or not, a dynamic array must have held data at some point before being passed to this function.

arrayPtr& is a pointer to any FutureBASIC Dynamic Array previously dimensioned using DYNAMIC or DIMÊDYNAMIC. In typical usage, this address will come from a parameter to the calling function, such as ( @arrayPtr AS PTR ), to which the name of a dynamic array would be passed.

See Also DEF DYNAMICINSERTITEMS; DEF DYNAMICREMOVEITEMS; SIZEOF


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Futurebasic/Language/Reference/usr even

USR EVEN(expr)

Description - This function returns the smallest even integer which is greater than or equal to the integer part of expr. USR EVEN can be useful for finding even address boundaries.

Example: PRINT USR EVEN(5) PRINT USR EVEN(-9) PRINT USR EVEN(40.3) PRINT USR EVEN(160)

Program output: 6 -8 40 160

See Also MOD

title: Futurebasic/Language/Reference/usr even


text: User talk:70.51.79.68

title: User talk:70.51.79.68


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Talk:Chess Opening Theory/1. a4

a4 is a joke of an opening. I understand the desire for this wikibook to be exhaustive but the fact that there are some major lines missing and yet this page exists is ridiculous. Tomson (talk) 00:14, 30 April 2008 (UTC)
 * While I totally agree it's a joke move. There are a few reasons for the page
 * Unusual 1st moves are are required for presentation on Opening_theory_in_chess
 * Same issue in the navigation template.
 * If the page didn't exist someone would create it and if they followed some of the advice written by some other here, they would copy the page that linked to it, i.e the main Opening_theory_in_chess page which is not an easy way to start with a new page.
 * Unusual moves(not just 1.a4) get a lot of traffic, many times what you'd expect, quite strange and can't really find out why. I guess people are just curious. Why for example did you come and look at the page? It does show it's viewed a lot, even if as a chess player it's an irrelevant move.
 * On wikibooks you could image people clicking a4 because it's on the main page and navigation template. But that's not true on wikipedia that doesn't really have a navigation between openings.
 * And guess what, on wikipedia views of 1. a4 are higher they views of the Sicilian Accelerated Dragon. SunCreator (talk) 16:44, 30 April 2008 (UTC)
 * I wound up here, because someone actually did pull it on me, and I couldn't imagine why. I still can't. Mechroneal (talk) 22:22, 15 July 2008 (UTC)
 * Same here - the game didn't last long though... Alan16 (talk) 16:44, 14 August 2009 (UTC)
 * why I play it: at a lower level (around ELO:12-1400), where the shortcomings of this opening aren't as fatal, it's advantage is that it throws people out of book openings, forcing them to rely on their opening skills rather than opening knowledge: if you haven't memorized opening books, it can allow you to beat platers who are 'better' because they have, but haven't developed any actual opening skill. I've played several games that go 1.a4 e5 2.b4 Bxb4 3.Ba3 Bxa3 4.Rxa3 resulting in white being a pawn down and black having no idea how to proceed if he's relying on playing from memorized openings --Arkelweis (talk) 09:56, 7 November 2009 (UTC)

title: Talk:Chess Opening Theory/1. a4


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User:Tomson~enwikibooks

Call me Tomson.

Just thought I'd throw in my two cents regarding chess openings et cetera.

title: User:Tomson~enwikibooks


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Talk:Chess Opening Theory/1. a4/1...e5/2. h4

I would be in favor of deleting this page entirely. This can hardly even be considered an opening. There is no strategy involved and no benefits. Is there even any historical support for calling this the "crab" opening? Some novice wikipedian is having a laugh by putting this entry in. Tomson (talk) 00:17, 30 April 2008 (UTC)

 * With all due respect, Tomson, I thoroughly disagree. Despite the opening's lack of practicality, it deserves to be documented regardless. To take down the page would be to take down real (albeit useless) chess knowledge. The restriction of knowledge is virtually never for the best, even when it involves the Crab. Furthermore, the name "Crab" is entirely possible, if not plausible for a chess opening such as this. You must take into account such openings such as the Cow and Monkey's Bum and realize people have been giving chess openings foolish names for many a year. For these reasons, I must defend the legitimacy of the Crab. 🦀🦀🦀💪💪 DuckLordReal (discuss • contribs) 20:45, 7 July 2023 (UTC)


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Talk:Chess Opening Theory/1. a4/1...e5/2. Ra3

This page will need to be deleted if this wikibook is actually a serious project. Tomson (talk) 00:19, 30 April 2008 (UTC)


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Futurebasic/Language/Reference/usr fileexists

USR FILEEXISTS(fileName$, vRefNum%, dirID&)

Revised February, 2002 (Release 6)

Description - Your program may determine whether or not a file exists using this function. A non-zero value is returned when the file is present. You need to pass the fileName and the vRefNum% in all cases, but the dirID& can usuually be zero. To determine if a file named "My File" is present in the application folder you would use the following code. LONG IF USR FILEEXISTS("My File", SYSTEM(_aplVol), 0) PRINT "File exists!" END IF Note: You will not be able to use this function unless you include the proper header file as follows:

INCLUDE "Util_Files.incl"

See Also USR FSFILEEXISTS


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Futurebasic/Language/Reference/usr fontheight

USR FONTHEIGHT

Description - This function returns the current "font height" in pixels. This is based on the current font ID and font size for the current output window or printer. The font height is the full height of a line of text, measured from the top of one line to the top of the line below it. It is not the same thing as the "font size," although there is often a relationship between the font size and the font height. The font height is the sum of the font's "ascent," its "descent" and its "leading." See the "Font Manager" chapter in Inside Macintosh: Text for more information.

Example: USR FONTHEIGHT is useful for determining how many lines of text will fit within a rectangle of a given height. This LOCAL FN returns the number of text lines that can fit in the current window: LOCAL FN MaxLines wh = WINDOW(_height) fh = USR FONTHEIGHT max = wh \\ fh  END FN = max

See Also TEXT


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Futurebasic/Language/Reference/usr fsfileexists

USR FSFILEEXISTS(fsSpec)

Revised February, 2002 (Release 6)

Description - Your program may determine whether or not a file exists using this function. A non-zero value is returned when the file is present. You need to pass a file spec record which can be created using FN FBmakeFSSpec or by using a file spec version of the FILES$ function. To determine if a file named "My File" is present in the application folder your would use the following code.

INCLUDE "Util_Files.incl" DIM fs AS FSSpec FN FBmakeFSSpec(SYSTEM(_aplVol),0,"My File",fs) LONG IF USR FSFILEEXISTS(fs) PRINT "File exists!" END IF Note: You will not be able to use this function unless you include the proper header file as follows:

INCLUDE "Util_Files.incl"

See Also USR FILEEXISTS;

Appendix H: File Spec Records; FILES$


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Futurebasic/Language/Reference/usr fsgetfoldername

USR FSGETFOLDERNAME(fsSpec,folderName$)

Revised August, 2002 (Release 7)

Description - This function returns the name of the folder that contains the file specified by fsSpec.

Example:

INCLUDE "Util_Files.incl"

DIM fs AS FSSpec

DIM x,name$ name$ = FILES$(_FSSpecOpen,,,fs) x = USR FSGETFOLDERNAME(fs,name$)

PRINT name$

DO HANDLEEVENTS UNTIL 0

See Also FINDERINFO, FILES$; USR SCANFOLDER


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Futurebasic/Language/Reference/usr fssendfiletotrash

USR FSSENDFILETOTRASH(FSSpec)

Revised February, 2002 (Release 6)

Description - Rather than deleting a file, it is often desirable to move it to the trash. In this way, your user has a chance to retrieve it from the trash if he changes his mind. This particular version of the function requires a file spec record for operation.

See Appendix H for information on file spec records.

Note: You will not be able to use this function unless you include the proper header file as follows:

INCLUDE "Util_Files.incl"

See Also SYSTEM function; USR MOVEFILE; RENAME;

Appendix H:File Spec Records


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Futurebasic/Language/Reference/usr fsgetfullpathname

USR FSGETFULLPATHNAME(fsSpec,pathName$)

Revised August, 2002 (Release 7)

Description - This function returns the full path name for the file specified by fsSpec. Folder names are separated by colons.

Example:

INCLUDE "Util_Files.incl"

DIM fs AS FSSpec

DIM x,name$ name$ = FILES$(_FSSpecOpen,,,fs) x = USR FSGETFULLPATHNAME(fs,name$)

PRINT name$

DO HANDLEEVENTS UNTIL 0

See Also FINDERINFO, FILES$; USR SCANFOLDER


text:
Futurebasic/Language/Reference/usr getdoublebyte

USR GETDOUBLEBYTE

Revised July 26, 2000 (Release 3)

Description - If you have selected "Automate handlers for 1 & 2 byte strings" in the Preferences window under the Vars tab, this function will return a non-zero value when operating in double byte mode. Single byte mode is used for Roman fonts. Two byte script systems such as Chinese, Japanese, Vietnamese, and Korean require two bytes per character. This function will return zero if you selected "Automate handlers for 1 & 2 byte strings" and if you have not used DEF SETSINGLEBYTE (or have reset the system with DEF SETDOUBLEBYTE.)

In all other cases, it returns -1.

See Also DEF SETDOUBLEBYTE; DEF SETSINGLEBYTE, USR GETSINGLEBYTE


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Futurebasic/Language/Reference/usr getfoldername

Usr FSGetFolderName(fsSpec, folderName$)

Revised August, 2002 (Release 7)

Description - This function returns the name of the folder that contains the file specified by fsSpec.

Note: You will not be able to use this function unless you include the proper header file as follows: Include "Util_Files.incl"

Example:

Include "Util_Files.incl"

Dim fs As FSSpec

Dim x,name$ name$ = Files$(_FSSpecOpen,,,fs) x = Usr FSGetFolderName(fs,name$)

Print name$ Do HandleEvents Until 0

See Also FINDERINFO, FILES$; USR SCANFOLDER


text:
Futurebasic/Language/Reference/usr getfullpathname

resultCode = Usr FSGetFolderName(fsSpec, folderName$)

Revised August, 2002 (Release 7)

Description - This function returns the name of the folder that contains the file specified by fsSpec.

Note: You will not be able to use this function unless you include the proper header file as follows:

Include "Util_Files.incl"

Example:

Include "Util_Files.incl"

Dim fs As FSSpec

Dim x,name$

name$ = Files$(_FSSpecOpen,,,fs)

x = Usr FSGetFolderName(fs,name$)

Print name$

Do HandleEvents Until 0

See Also FINDERINFO, FILES$; USR SCANFOLDER


text:
Futurebasic/Language/Reference/usr getsinglebyte

boolean = USR GETSINGLEBYTE

Revised July 26, 2000 (Release 3)

Description - If you have selected "Automate handlers for 1 & 2 byte strings" in the Preferences window under the Vars tab, this function will return a non-zero value when operating in single byte mode. Single byte mode is used for Roman fonts. Two byte script systems such as Chinese, Japanese, Vietnamese, and Korean require two bytes per character. This function will return zero if you selected "Automate handlers for 1 & 2 byte strings" and if you have not used DEF SETSINGLEBYTE.

In all other cases, it returns -1.

See Also DEF SETDOUBLEBYTE; USR GETDOUBLEBYTE, DEF SETSINGLEBYTE


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Futurebasic/Language/Reference/usr getpict

pictHandle&, = USR GETPICT ({rect|#rectAddr&})

Description - This function captures a picture of a portion of the screen using the screen's current color depth, and returns a handle to the picture. Given the handle, you can then draw the picture (using the PICTURE statement), or save the picture as a "PICT" resource (using the ADDRESOURCE Toolbox routine), etc. The captured picture is bound by the rectangle which is specified in rect (which should be an 8-byte variable such a RECT type), or which is pointed to by rectAddr& (which should be a long-integer expression or a POINTER variable). The rectangle should be expressed in the local coordinate system of the current output window. The captured picture is also limited to the "clip region" of the current output window. Therefore, what actually gets captured is the intersection of the clip region and the specified rectangle. The captured picture is not limited to the visible contents of the window. Whatever is on the screen within the specified rectangle (and within the clip region) will get captured. By appropriately adjusting the rectangle and the clip region, you can capture any part of the screen you want.

Example:

This program captures a snapshot of the entire screen, then displays the snapshot at 1/2 scale in a small window. DIM rect.8, pt.4

sWidth = SYSTEM(_scrnWidth)

sHeight = SYSTEM(_scrnHeight)

WINDOW -1,"",(0,0)-(sWidth/2, sHeight/2), _dialogMovable

HANDLEEVENTS'Let Finder refresh things 'Get screen corner in window's local co-ord's:

CALL SETPT(pt, 0, 0)

CALL GLOBALTOLOCAL(pt) 'Define rect as entire screen, in local co-ord's:

CALL SETRECT(rect, pt.h%, pt.v%, pt.h%+sWidth,pt.v%+sHeight) 'Save window's current clip region:

oldClip& = FN NEWRGN

CALL GETCLIP(oldClip&) 'Set clip region to entire screen:

CALL CLIPRECT(rect) 'Snap entire screen:

h& = USR GETPICT(rect) 'Restore old clip region:

CALL SETCLIP(oldClip&)

CALL DISPOSERGN(oldClip&) 'Draw the little picture:

WINDOW 1'make window visible

HANDLEEVENTS'handle initial refresh event

PICTURE (0,0)-(sWidth/2, sHeight/2), h& DEF DISPOSEH(h&) DO HANDLEEVENTS UNTIL _false This LOCAL FN takes a snapshot of the current window's contents, then pastes the picture onto the clipboard. Note that if the window is hidden or partially obscured, other parts of the screen will appear in the captured picture. LOCAL FN Window2Clip DIM rect.8 CALL SETRECT(rect, 0, 0, WINDOW(_width), WINDOW(_height)) oldClip& = FN NEWRGN'Init a new region CALL GETCLIP(oldClip&)'Save a copy of current clip region CALL CLIPRECT(rect)'Set clip region to this rectangle pictH& = USR GETPICT(rect) 'Get the picture CALL SETCLIP(oldClip&)'Restore the old clip region CALL DISPOSERGN(oldClip&) 'Don't need this copy any more LONG IF FN ZEROSCRAP = _noErr'Clear clipboard contents CALL HLOCK(pictH&)

OSErr = ¬

FN PUTSCRAP(FN GETHANDLESIZE(pictH&),_"PICT",[pictH&]) END IF  KILL PICTURE pictH&'Don't need this any more END FN

See Also PICTURE statement


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Talk:Chess Opening Theory/1. e4/1...e5/2. f4/2...exf4

The very beginning moves of the King's gambit state that the king pushes his f-pawn for the sake of getting the chance to play d4; where doe sthat move take place? Here it would be disasterous upon Qh4+. Tomson (talk) 01:19, 30 April 2008 (UTC)
 * Where does it say that? Anyway the move 2. f4 means that d4 becomes unlikely. Would be more likely after 2. Nf3 or c3 which support a possible d4 push and by playing 2. f4 there is pressure on the Kingside first to deal with before d4 can be played. That being said there are some lines in the Kings gambit accepted and also the Falkbeer(3. f4 d5) where d4 can be played. SunCreator (talk) 16:25, 30 April 2008 (UTC)
 * I've found what your referring to the King's Gambit, King's Gambit. White is threatening to play d4 but doesn't get around to it for some time in the main line as there are more important things. Initially after 2. f4 exf4 3. d4 would be a mistake because of 3...Qh4 and so instead white plays 3. Nf3 but unless black plays relatively passively (3...d6 or 3..h6) white doesn't get around to playing d4 for several more moves. Debateably it should not be played anyway as the main line goes 3. Nf3 g5 4. h4 g4 5. Ne5 d6 6. Nxg4 Be7 7. d4 ( 7.d3 is considered a more solid and better try here I believe). SunCreator (talk) 17:14, 30 April 2008 (UTC)


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User talk:Tomson~enwikibooks

Tomson (talk) 01:20, 30 April 2008 (UTC)

Welcome!
Tomson, Thanks for joining Wikibooks Chess.

You may like to have this link handy, public chess watchlist, and also this navigator.

SunCreator (talk) 16:31, 30 April 2008 (UTC)

Your account will be renamed
Hello,

The developer team at Wikimedia is making some changes to how accounts work, as part of our on-going efforts to provide new and better tools for our users like cross-wiki notifications. These changes will mean you have the same account name everywhere. This will let us give you new features that will help you edit and discuss better, and allow more flexible user permissions for tools. One of the side-effects of this is that user accounts will now have to be unique across all 900 Wikimedia wikis. See the announcement for more information.

Unfortunately, your account clashes with another account also called Tomson. To make sure that both of you can use all Wikimedia projects in future, we have reserved the name Tomson~enwikibooks that only you will have. If you like it, you don't have to do anything. If you do not like it, you can pick out a different name.

Your account will still work as before, and you will be credited for all your edits made so far, but you will have to use the new account name when you log in.

Sorry for the inconvenience.

Yours, Keegan Peterzell Community Liaison, Wikimedia Foundation 23:48, 17 March 2015 (UTC)

Renamed
 This account has been renamed as part of single-user login finalisation. If you own this account you can |log in using your previous username and password for more information. If you do not like this account's new name, you can choose your own using this form after logging in: . -- Keegan (WMF) (talk) 05:36, 19 April 2015 (UTC)

title: User talk:Tomson~enwikibooks


text:
User:Brim/Sandbox

This page is BEAVIS

title: User:Brim/Sandbox


text:
Managerial Economics/Business Cycles

Business cycle consists of seven main steps
 * 1) market discovery
 * 2) development and creating the customer
 * 3) increasing profits
 * 4) stable profits
 * 5) loosing consumers
 * 6) struggling and re-living
 * 7) closing the business

title: Managerial Economics/Business Cycles


text:
Talk:This Quantum World/Serious illnesses

Please add a reference to information about experiments to determine the lifetime of hydrogen. JasonWoof (talk) 05:09, 30 April 2008 (UTC)


text:
User:Artzalexander

Hallo;Mein name ist GERHARD Aexander.Meine alte name ist AYDOGMUS ONDER;Ich bin jetzt ein ARTZ auf dem HUMBOLD UNIVERSITAT. Meine branche ist herz-ader chirurgium(CARDIO-VASCULER SURGERY). GEBURTSTAG:28 APRIL 1975;GEBURTSORT:ANKARA-TURKEI;FAMILIENSTAND:VERHEIRATET;REYHAN GERHARD(AYDOGMUS)

Ich habe die schulerin gelesen

in der turkei -Ankara

ismail enderuni ioo

ayvali orta okulu

Ankra Gazi Lisesi

-Istanbul

Istanbul universitesi tip fak. DEUTSCHLAND

Humboldt Universitat Arznei fakultat HERZ-ADER CHİRURGIUM ASSISTENT ARTZ(2000-2006) Berlin-DEUTSCHLAND

Humboldt Universitat Arznei fakultat HERZ-ADER CHİRURGIUM EXPERTE ARTZ HERZ-ADER CHİRURGIUM(2007-

title: User:Artzalexander


text:
Clock and Data Recovery/Introduction/Acquisition, tracking and jitter performances

Requirements and characteristics
What are the different requirements for the extraction of the clock from an incoming (encoded) bit stream?

They are essentially related to two different conditions of the CDR operation:
 * 1) Acquisition of the phase lock
 * 2) Tracking of the acquired phase timing once the acquisition is sufficient.

Acquisition
This condition of the CDR operation starts when :
 * the CDR has been turned ON, and
 * the input signal appears.
 * As long as the received signal is not present, the CDR is kept idle by the LOS control signal, which is generated by the first stages of the receiver, (LOS = Loss Of Signal).

 * When the LOS is deactivated, the CDR is released and the acquisition phase begins.
 * The local oscillator of the CDR at that moment has an unpredictable phase mismatch with the phase of the incoming signal.
 * The CDR then reacts as if it had been in perfect lock and the phase of the input signal had taken an abrupt step change.
 * It may be added that, in case the CDR operates as a slave CDR, it would also be subject to the equivalent to an abrupt, though small, change of the frequency of the input signal.
 * In fact, the input signal (during LOS) was unknown and the CDR acted as if the input signal frequency was its own free-running frequency, ffr..

The acquisition ends when the tracking begins.

The condition of tracking starts when the CDR keeps consistently its sampling point close enough to the eye center.
 * Close enough means that the sampling time (affected by jitter and possibly by a systematic steady state error) remains close enough to the optimum sampling point to achieve a very low Bit Error Rate.
 * For example, remaining within a sampling error of ± 0.5 rad ( = ± 0.07 U.I.) and below a BER of 10-12 could be considered as being in the tracking condition of the CDR operation.

An abrupt step of the phase of the input signal can be studied as a new acquisition with the same initial phase mismatch.

Different CDR architectures behave differently, also during the acquisition phase.

Acquisition bears a strong analogy with the unit step response of a linear systems.
 * In fact, if a CDR can be adequately modelled by a linear system, its acquisition is modelled by the (Unit) Step Response of the system.

[[File:USRs 3 models.png|thumb|center|750px| Responses of the 3 fundamental linear models of PLL to an input step of 1 rad.

Parameters are chosen to have a meaningful comparison, although the value of ζ for the second order loops is lower than the values used in practice. In other words, the two 2nd order loops are under-damped to stress the differences amongst different architectures. ]]

Many non-linear factors may strongly influence how the acquisition evolves into tracking. For instance, the use of a bang-bang phase detector, the slew-rate consequence of the limited swing range of the VCO, the use of a PFD, each gives the acquisition transient special characteristics.
 * a linear phase comparator and input conditions that allow the other blocks to remain within their linearity ranges, make the VCO phase follow a typical catch-up with the input phase that is exponential and make the time to reach tracking independent from the amplitude of the input step (the response time τ is dependent only on the circuit characteristics and remains the same if the phase step to catch up is bigger or smaller) - See the figure above;
 * a bang-bang phase detector makes the acquisition follow a constant slope until catch-up has taken place. The slope is the same for different step amplitudes.
 * a PFD makes the CDR output phase (as long as slips of decreasing frequency precede the achievement of tracking) follow a sort of parabolic shape (spanning as many 2π multiples as the number of slips that took place) before completing the acquisition.

The simplest architecture (1st order and type 1) is best fit to implement CDRs with fast and slip-free acquisition of phase lock.
 * Its response to an abrupt change of phase (step input), even if combined with a frequency difference between the timing of the received signal and the free running frequency of the local oscillator (ramp input), is always free from slips.
 * The phase difference during the acquisition is always a decreasing function (apart from a small drift that may originate by ffr / fp mistuning and that would only be evident during periods of missing transitions and only if the mistuning sign was making the VCO resist the direction of the acquisition transient).

 * In the figure above, the simulation uses 3000 discrete time steps. Each time increment is 2.7 ps (that is the line pulse period of 100 ps divided by 37).
 * After 200 time steps (i.e. after 2.7 * 37 = 543 ps) the loop - that was open until then (because LOS was = 1) starts its acquisition phase ( LOS = 0).
 * The input phase takes in that moment a positive step of  1.3 rad.
 * The input transitions appear with an average density of 50 %, but otherwise in a fully random sequence.
 * The acquisition lasts for a little over 3 ns in this example. It ends when the phase error settles around its final value (settles around 0 rad in this example).
 * The pattern of pulses in the signal that drives the VCO (black trace) is, although random, constantly made only of positive pulses during the acquisition of lock.

 * It may be noted that the VCO has a ffr lower than fp (in this example lower by exactly 5750 ppm), as the VCO phase lags behind the input phase (lower negative slope in the red trace) every time the VCO drive signal it at its intermediate level, both before detection of the input signal and when there is a lack of transition (mid level of the VCO drive signal).
 * The steeper slopes of the red trace, positive and negative, tell when the VCO is driven to its top and bottom frequencies (1.00575 1010 ± 2.39 108 Hz ) by the positive and negative pulses of its drive signal.
 * The drive signal is exponentially smoothed when it goes down to zero, because there is a parasitic low-pass (at 6.28 1011 rad/sec = ten time ti line pulse frequency) just after the ternary phase detector. It is sharp at its top and bottom corners because the it is clamped by an instantaneous circuit.

 * The acquisition time would vary every time with the randomness of the transitions at the signal appearance, and be significantly longer than in the example with a non-zero probability.
 * If the transitions density had been equal to 100%, the acquisition would have been faster and predictable.
 * The following figure gives an example of the same circuit if the transition density is forced to 100%.
 * Acquisition with a preamble of 101010.. of adequate duration, are a standard in systems that frequently need to reacquire the signal lock.

 * When DT = 100%, it is even more evident that the tracking of a fp higher than ffr is the cause of a ratio of positive pulses to negative pulses (evident in the VCO drive signal) that is higher than 1.

There are other CDRs (based on the other two more sophisticated architectures, the "second order loops of type 1 and 2") whose acquisition is inevitably long and sometimes a series of slips precedes the achievement of a stable acquisition. The presence of slips at the beginning of the acquisition is acceptable in applications operating in (Continuous transmission mode), and in inevitable in some of those where a PFD must be used.

Tracking
Acquisition ends, and the condition of tracking is reached, when the CDR keeps consistently its sampling point close to the eye center (that is, when the phase error settles and just jitters around the steady state error value.
 * During tracking, the sampling instant (though affected by jitter and possibly by a systematic steady state error) remains close enough to the optimum sampling point to achieve a Bit Error Rate practically equal to 0.
 * For example, remaining within a sampling error of ±0.5 rad ( = ±0,07 U.I.) and below a BER of 10-12, could be considered as a tracking condition.
 * During tracking, an abrupt step of the phase of the input signal can be studied much as a new acquisition, with the initial phase mismatch equal to that step.

Poor tracking: with an input jitter that is too large, the loop repeatedly slips twice, then locks-in again.

There are 3 fundamental requirements for the performances of a tracking CDR:

One applies to all CDRs,

the other 2 apply to the subset of the "regenerator" CDRs.

All CDRs
To study the tracking state, the fundamental characteristic of all CDRs is:
 * the ability to operate correctly (that is with a low enough Bit Error Rate = BER) in the presence of a given jitter.

 * This is measured by the Jitter Tolerance (or Jitter Acceptance).
 * It gives, at every frequency, the sinusoidal input signal amplitude below which the BER is 0 and above which the BER is higher than 0.
 * It is often specified as a mask of jitter amplitude versus jitter frequency.
 * The circuit must operate correctly at any condition defined by a jitter amplitude and a jitter frequency within the boundary set by the mask.
 * In other words, the (locus of the conditions of) onset of BER shall be found above (=at higher jitter amplitudes than) the boundary set by the mask.

Regenerator CDRs

 * When the recovered clock is used for the data stream that is resent further downstream (which is a common case in a network), the CDR is a regenerator CDR.
 * Definition: A "regenerator" CDR is a slave CDR that is used as a master for at least another CDR further downstream.

 * For regenerators, two other characteristics are important as well:

 * filtering out the input jitter frequencies above the frequency range involved in the lock-in and tracking. This is called Jitter Transfer characteristic, and there often exists a mask setting an upper limit for the curve that characterises the circuit (the jitter transfer function is the function (part of the circuit model) expressing the ratio - at any given frequency - of the magnitude of the sinusoidal jitter at the output to the magnitude of the sinusoidal jitter at the input).
 * The presence of a filter block in the model of 2nd order PLLs allows one more degree of design freedom (instead of τ only, ωn and ζ can be chosen). The 2nd order architecture is used when particular requirements (for jitter and/or noise and/or effects of non-linearities) make the 1st order PLL inadequate. The quantity ωn essentially defines the cut off frequency of the low pass effect that such PLL has on the incoming jitter (≈ the jitter bandwidth of the loop).

 * the amount of Generated Jitter inside our circuit (phase noise added to the retrieved timing signal). Often specified as:
 * a rms or peak value for the output wander ( < 10 Hz) with zero input wander, and
 * as a curve of maximum magnitude vs frequency for jitter (> 10 Hz).

 * See, for instance, the TDEV (Time Deviation) and the MTIE (Maximum Time Interval Error) used by the ITU-T inside its Recommendations for wander limit definition,  and for output jitter as well.
 * The ITU-T, in its Recommendations Telecommunication Standardization Sector (ITU-T), is an invaluable source of theory and practical knowledge on the subject. It primarily deals with the requirements of large, geographical, networks, and therefore these Recommendations are especially useful, and exact in their quantitative references, for the engineer that studies Telecom digital networks, but they can also provide a lot of insight in other fields of application of CDRs.

Other examples of acquisition and tracking can be found in subsequent pages of this book.

Data recovery and Clock recovery: Definitions
In a serial transmission the two CDR functions of Data Recovery and of Clock Recovery are not exactly the two parts of the same definition.

The Data recovery can be uniquely defined as the operation of an end point CDR (Data recovery and Clock recovery with a specified jitter tolerance). Alternatively, it can be defined as the recovery of data with a specified BER and of a clock sufficient to write the serial data stream in a buffer memory for later retrieval.

The Clock recovery can be defined as the recovery of the clock according to a requirement either of: The difference to appreciate consists in the additional requirements that are included in the second case
 * jitter tolerance only, like in an end point equipment (wider sense - note that the jitter tolerance is the only requirement involving both Data and Clock)), or
 * jitter tolerance, jitter transfer and jitter generation (tighter sense, like in a regenerator equipment - note that jitter transfer and jitter generation are requirements involving the Clock only, but not the Data).


text:
Clock and Data Recovery/Structures and types of CDRs/The jitter tolerance function

[[File:Jitter tolerance phase aligners.png|thumb|center|800px|alt=Three magnitude functions of jitter tolerance for the three main loop models. For each the lateral eye opening is the same, as is the same the length of the elastic buffer (=phase adder).| Three magnitude functions of jitter tolerance for the three main loop models in the case of phase-aligner architectures. For all architectures the lateral eye opening is the same and the length of the elastic buffer (=phase adder) is the same.

The two important 2nd order PLLs are plotted in the under-damped but significant condition of ζ = 0.5.

The natural frequency is 500 KHz (ωn= 3.14 e6 rad/sec) and is the same for each of the three loops (yellow marker). ]]

The jitter tolerance of an equipment
In digital networks it is established practice  (see for instance some of the ITU-T Recommendations G7xx )  to specify, and to characterise by measurement, the jitter that can be tolerated at the input ports of an equipment.

At any frequency of interest, a sinusoidal input jitter is added to the phase of an otherwise flawless incoming signal, and the jitter amplitude is increased as much as the equipment can tolerate. Beyond that limit, the received data stream is not regenerated perfectly and error bits and possibly also slips begin to appear. The same procedure is repeated at different jitter frequencies, to cover all the frequency band of interest for the jitter tolerance and the results are interpolated to obtain a continuous curve.

The boundary of the area (in the plane of jitter frequencies and magnitudes) where the CDR operates without bit errors is then called the curve of jitter tolerance of that equipment.
 * Note: jitter tolerance curve = measured ;  jitter tolerance function = obtained from models or simulations.

The errors can either be generated by sampling the received pulses too far from the optimum point, or by slips. In both cases, the tolerance limit has been exceeded.
 * Slips can either come from exceeding the range of the phase comparator, or by exceeding the range of an elastic buffer. The slip is a catastrophic event in terms of BER because, after its occurrence, 50% (statistically) of the regenerated bits are seen as errors and 50% (statistically) are seen as fictitiously correct. The BER is as high as it can ever be (until the framing circuits are able to get in sync again).
 * Error-ed bits. The CDR under test extracts the clock directly from the pulses of the received signal, and then uses it to regenerate the pulses received.  The tolerance limit will be reached when the clock that samples the incoming pulses is too far (too early or too late) from the optimum point (the point of “maximum eye opening”, that approximately coincides with the central point between transitions).  Such distance from the central sampling point, beyond which errors begin to occur, is called lateral eye opening ΦLEO . Error-ed bits will give evidence that the tolerance limit has been exceeded (even if they only pop up sparsely in small bursts, at the moments of peak amplitude of the periodic phase error induced by the jitter sinusoidal oscillation).

Remarks
The tolerance at high frequencies is just a horizontal asymptote, and the asymptote value indicates, for the equipment port under measurement, the difference: ΦLEO - steady state error
 * 1) The jitter tolerance curve always has a "low-pass" shape. The tracking ability of an equipment is best at low frequencies and is low at high frequencies.
 * 2) At high frequencies, where no more tracking takes place, the equipment can only tolerate the jitter that does not bring the sampling instant to the eye corners. With zero jitter, the sampling point is offset from the central point by the steady state error, if the steady state error is non zero. If the steady state error is zero, the sampling point is in the eye center.
 * where the steady state error is the possible error corresponding to an offset of the frequency of the incoming pulses from the free-running frequency of the local oscillator.
 * Such error is $$\tfrac{\omega_p - \omega_{fr}}{G}$$ [rad] in a slave system of type 1, and is 0 [rad] in a phase aligner system or in any type 2 system.
 * 1) Towards lower frequencies the measured tolerance curve also is asymptotic, but the slope of the asymptote depends on the PLL architecture:
 * 2) 0 dB/decade, i.e. horizontal, This indicated that an elastic buffer is present to absorb some large low frequency jitter. The horizontal asymptote indicates that the jitter compensation is finite. (The length of the buffer is approximately twice the magnitude of the tolerance represented by the horizontal asymptote).
 * 3) - 20 dB/decade. This indicated that the receiver is a slave (the local oscillator can follow an infinite phase accumulation, as long as its frequency can track the incoming pulse frequency). The - 20 dB/decade slope tells that the PLL is a type 1 loop (or a type 2 loop whose tolerance is "slew-rate" limited).
 * 4) - 40 dB/decade. This indicated that the receiver is a slave (the local oscillator can follow an infinite phase accumulation, as long as its frequency can track the incoming pulse frequency). The - 40 dB/decade slope tells that the PLL is a type 2 loop.
 * 5) The tolerance curve sometimes looks like the slope of terraced rice field, with more than one flat section after the first left slope. This indicates that more than one CDR is present along the regeneration path between the injection of the test signal, and that some of them operate at different bit rates.
 * 6) In general:
 * 7) a flat section, or a flat asymptote, indicates that the tolerance is exceeded in a elastic buffer. Note that the lateral eye opening at high frequencies acts as a elastic buffer;
 * 8) a section with a slope of -20 dB/decade indicates that (in the related frequency range) the tolerance is exceeded in a PLL operating there like a 1-1 architecture;
 * 9) a section with a slope of - 40 dB/decade indicates that (in the related frequency range) the tolerance is exceeded in a PLL operating there like a 2-2 architecture.

The tolerance function, a simulation of the tolerance curve
In a feedback loop, like in a PLL for CDR use, the operation is linear, and the linear modeling remains valid, as long as all blocks in the loop operate within their linearity range.

Increasing the input signal amplitude, a point will be reached where one block reaches the limit of its range of linear operation.

Increasing further the input signal amplitude, the linear model loses its adherence to the real system and the actual operation deviates from the modeled behavior.

When investigating the effects of the timing variation of the input signal (the input jitter), the tolerance function (that can be derived using the border between linear operation and the most important hard non-linearities - see below) is of particular interest. It corresponds to the important characteristic of the CDR that is often a precise requirement, specified and measured as a function of the magnitude of the input sinusoidal jitter at different frequencies. The mathematical function can be very close to the measured curve, and is therefore a fundamental engineering tool.

Reaching with the signal level the onset on hard non-linearity inside an internal block often corresponds to the appearance of errored bits in the regenerated data stream. The input signal has then exceeded the level of the CDR tolerance (such level is a function of the frequency of the input signal).

A mathematical derivation of such jitter tolerance function can be made finding out:
 * 1) 	the block in the loop that is first to reach its limit of non-linear operation and to generate errored bits or slips;
 * 2) 	the amplitude of the (phase) signal inside such block that reaches the limit of linear operation (such amplitude is a function of ω)
 * 3) 	the input signal amplitude (function of ω) that generates such internal signal amplitude.

In mathematical terms, defining as W(jω) the signal at a generic node of the CDR model, and as ± Φ tol the deviation tolerated at that node ,

the tolerance function is the locus, for every angular frequency ω, of the magnitude of the input signal X(jω) that produces a W(jω) that reaches, at one or both of its sinusoidal peaks, the tolerance level for that node:

Jitter tolerance =  |X(jω)|' ''' is exactly the input (to the CDR) needed for the internal signal to touch the tolerance limit at least at its positive or negative sinusoidal peaks.

Different circuit shortcomings may identify different tolerance functions. These are then combined into one considering, at every frequency, the lowest value among their values.

The function so obtained is called the jitter tolerance function.

In order to derive a tolerance function that simulates well the tolerance curve obtained by measurement, there are 3 (three) fundamental shortcomings of the linear model must be considered :
 * the pulse regeneration (= the eye corners and the steady state sampling offset)
 * the limited frequency range of the VCO
 * the limited range of the (possible) elastic buffer.

The limited range of the phase comparator
The border of normal operation of a phase comparator is reached when the distance in phase between its two inputs exceeds a certain value.

It does not depend on the absolute value of either input, but on their difference only.

The phase comparator is built so that its range covers without discontinuity the period T of one line pulse, and the PLL is designed so that zero difference between the comparator inputs corresponds to the perfect lock of the loop: Φmax = -T/2, +T/2 ⇒ = -π , + π.

When Φmax is exceeded by the error signal x(t)-y(t), the phase comparator output falls into the next period of its characteristic and its output indicates to the PLL that the closest locking point is now the center of the nearby pulse.

If the transient is short enough the loop has no time to react, the error signal comes back quickly within range, and the output goes back to the original segment of the comparator characteristic. A large burst of errors have affected the CDR, but at the end there is no slip of the recovered clock

If instead the transient lasts long enough for the loop to react, then lock will be achieved at the center of the new segment of the comparator characteristic: a slip has occurred.

Mathematically such limit of linearity of the phase comparator characteristic defines one of the tolerance curves of the closed loop. Such tolerance can be modeled as the locus -for every frequency- of the magnitudes of sinusoidal input signals X(jω) such that : |X(jω) - Y(jω)| = |Ε(jω)| = $$\Phi$$max = $$ \pi $$

But, in the particular case of the measurement of the tolerance curve, as well as in the derivation of the tolerance function, the range extremes of the phase comparator are never reached!

Its range may be exceeded during real operation, in particular during the early phase of a difficult acquisition of phase lock, but it will not be reached while finding the tolerance limit.

In fact, the range of error-less sampling corresponds a sub-range of the phase comparator range. Sampling errors do appear as a consequence of sinusoidal jitter when the lateral eye margin is reached, while the comparator range limit is always larger. The following figure helps identify the quantities involved and clarify the related concepts, and the following sub-paragraph addresses the loop tolerance associated with the sampling phase margin.

The pulse regeneration (= the eye corners and the steady state sampling offset)
[[File:Eye_lateral_aperture.pdf|thumb|center|900x300 px|alt=The pulse regeneration may not take place at the best instant because of a timing deviation. There is margin against a bit error resulting from a misplaced sampling instant. Looking at the eye diagram it is easy to identify the margin.| The pulse regeneration may not take place at the best instant because of a timing deviation.

There is margin against a bit error resulting from a misplaced sampling instant.

Looking at the eye diagram it is easy to identify the margin. ]]

The tolerance function due to the lateral closure of the eye diagram can be modeled by an equation like the one resulting from the comparator range, but using a tighter range limit, and taking also into consideration the possible sampling offset that exists in some cases.

The input jitter that is not tracked by the PLL leaves a residual (sinusoidal) error between input (that represents the eye center) and output (that represents the sampling instant).

Overall, the output y(t) is not able to track exactly the input x(t) because of two shortcomings:
 * 1) a d.c. offset (the steady state error) and
 * 2) its (sinusoidal) phase variation is not able to replicate exactly the input (sinusoidal) phase variation, and a (sinusoidal) error of the same frequency remains.

When the sinusoidal error adds to the steady state error the sampling may take place before the beginning transition or after the end transition of the pulse.

Just one, or a few, or a high density of errors are equally relevant in the identification of the tolerance limit. In other words, the limit is meant to have been reached when the sampling takes place in what could be a wrong instant, even if the irregular jitter of the beginning or of the end of the pulse do not necessary imply an error at every bit time, but with a lower frequency of occurrence. (It should be remarked that the "irregular jitter" of the transitions happens at random -due to line noise and I.I.- but to a large extent faster than the sinusoidal jitter of the tolerance measurement or simulation). |X(jω)|undefined = |X(jω)|undefined  where Φleo ≤ Φmax.

When the error signal instantaneously exceeds Φleo, error bits are generated in the CDR with a certain probability.

When the error signal exceeds Φmax and a slip consolidates, the BER remains very high as long as the framing circuits downstream of the CDR re-align (in a real transmission network) or as long as the sequence recognition circuits of the BER tester re-align (in a tolerance curve test set-up).

The curves in the figure above can be seen as examples, with the exclusion of the flat asymptote towards low frequencies.

The tolerance due to the lateral eye closure decreases with increasing frequency and flattens out at high frequencies.

The clamping of the curves at low frequencies if present because the circuits described incorporate an elastic buffer (see section here below).

The limited frequency range of the VCO and the CDR slew-rate
There always exists the possibility that the PLL is not able to follow a rapidly changing phase of its input because the rate of change of the VCO phase (i.e. the VCO instant frequency deviation) is limited.

This may happen either:
 * because the PLL, still operating within its linear boundaries, is simply limited by the loop intrinsic low-pass behaviour. In this case to a sinusoidal input jitter corresponds a sinusoidal phase error signal as well as a sinusoidal output jitter.
 * or because the PLL non-linear boundary is reached in the characteristic of the VCO, or of a block preceding it in the loop forward chain. The phase error signal is not a sinusoid like the input phase signal. The output phase signal deviates from the sinusoidal input phase with tracts of lower, often constant, slope. In this latter case the PLL is " slew-rate " limited.  This can occur both because of the VCO characteristics (the VCO gain falls rapidly at the ends of its useful range) or because of the limited range of its drive signal.

The PLL can track the input phase variations, but it cannot react faster than reaching to the frequency extremes of the VCO useful range (the frequency jump is a linear ramp of the PLL phase: the maximum ramp slope of a circuit is called the slew-rate ), and staying there as long as it detects its lag.
 * Slewing can be defined as a contiguous sequence of ten or more identical phase-error indications.

When the phase of the input signal varies more rapidly than the VCO slew-rate, the phase error that appears may grow for a period long enough to possibly affect the CDR tolerance.

The VCO centering error shall also be kept into consideration: it appears at the VCO input as a voltage shift from the free-running value: Vdrive(fp) - Vdrive(ffr).

Sinusoidal input and slew-rate

 * Run-length is length of stretches (runs) of repeated bits during which the signal does not change.

The slew-rate limit can be investigated using a sinusoidal input phase jitter, that is the same input signal used for the tolerance curve of the CDR.
 * The tolerance is measured with a sinusoidal input jitter whose frequency sweeps the frequency range of interest and whose amplitude at each frequency is increased until errors appear.
 * A sinusoidal function (phase function of time in the case of jitter) has its maximum rate of variation at the zero crossings, that is the tangent at the points of zero crossing.
 * The slope at the zero crossing is the same of its tangent Aωt, i.e. Aω.

Maximum phase slew-rate = maximum frequency deviation.

The frequency (= the phase rate of variation) that the VCO can generate in response to a step Δdrive (positive or negative) of its drive signal depends on:
 * the amplitude of the drive signal
 * the frequency of the VCO immediately before
 * whether the VCO reaches one of its range extremes.

It also depends on the relative frequency of input transitions DT, because the CDR behaves as if the PD gain Gφ was reduced (i.e. multiplied) by DT.
 * The open loop gain is defined as G = Gφ Gf GVCO.

Slew-rate asymptotes with - 20 dB/dec slope and GVCOVD intersection
When the VCO is driven away from ffr, its excursions are limited (up or down) by the limited range of the circuitry that drives it (more than by its intrinsic characteristic, that is very imprecise and variable at the range ends: it is preferable to clamp the VCO range externally).

When driven by a voltage sinusoid Vdsin(ωt), the VCO produces a perfect sinusoid of frequency VdGVCOsin(ωt) (and therefore also of phase -(1/ω)VdGVCOcosin(ωt) ) with exactly the same 1/2πω period. (The amplitudes of the frequency sinusoid and of phase sinusoid differ by a GVCO/ω coefficient).

The range for Vd is inevitably finite: let’s call VD whichever of the two limitations (positive or negative) comes first (i.e. is smallest).

When Vd reaches VD, the sinusoid encounters a clamp at either or at both of its peaks.

If the input signal of the CDR increases, and tries to drive the amplitude of the signal at the filter output beyond VD, the VCO output frequency gets correspondingly clamped and the VCO output phase does not fully follow and starts slewing.

The onset of slewing happens when Vd = VD, that is when the output phase amplitude reaches VDGVCO/ω.

In general, there is no slewing as long as : ω ≤  VDGVCO / Aj Otherwise said, as long as amplitude of the phase jitter at the CDR input Aj ≤ VDGVCO / ω, the tolerance is not reduced by the slew rate; when Aj ≥ VDGVCO / ω, the phase error due to slewing appears and the tolerance is reduced and its limit may be reached.

Unfortunately the phase error due to slewing is a non-linear function of both Aj (or of Vd) and of ω, and it is not possible to compute it with a closed formula, but only with simulations case by case.

It is convenient to restrict the attention to the onset of slewing because:
 * it is a prudent (=conservative) estimation of the tolerance function;
 * all CDRs are designed so that slewing never appears for any expected condition of input jitter and run-length.

In a Bode plot the function VDGVCO/ω is a line going down with a slope equal to - 20 dB/dec and that intersects the 0 dB ( i.e. magnitude = 1 ) horizontal axis in: VDGVCO/ω = 1 ω = VDGVCO The margin between the onset of slewing and the actual border of the tolerance region (that is defined as the condition where the phase error increases up to the LEO value), is never large, islower at smaller ω, and increases somewhat at larger ω around, around the region where the tolerance deviates toward its high-frequency asymptote.

When the output phase jitter becomes triangular, like in the figures below, the actual tolerance gradually flattens out towards the asymptote Tol. ≈ LEO.

A 1st order type 1 loop goes into slew rate limiting (= into slewing) only because of the VCO range limits
The slew-rate occurs when the VCO frequency can not track the input jitter frequency.

In a 1st order type 1 loop this only occurs when the VCO reaches one or both the extremes of its frequency range.
 * (If fp ≠ ffr the maximum frequency swing that is possible in one direction is shorter than in the other direction, which means that the slew-rate in the corresponding direction is less steep than the slew-rate in the other, or that it is not present at all.)

 * During the first 100 simulation steps (1.78 nsec) there is no input signal.
 * LOS is asserted in this interval and the CDR is free-running at its centre frequency ωffr, that is 2000 ppm ( 0.2% ) slower than the nominal link frequency ( i.e. the frequency of the remote transmitter) of 6.28 1010 rad/sec. After 1.78 nsec the PLL lags 0.22 rad behind the transmit clock.
 * Then the input signal appears (LOS is dis-asserted) with a "step" of +1.25 rad (useful to mark the beginning of the acquisition phase).
 * The input signal is flat in phase for the time being (no jitter yet).
 * The phase detector jumps from its intermediate state (that was forced by the LOS signal) to its upper state, signalling that a delay is detected.
 * This jump propagates without appreciable delay to the VCO drive signal: the VCO jumps to its maximum possible frequency (DT of the incoming signal is 50%) and its phase (i.e. the CDR output phase) increases linearly with its maximum possible slope.
 * The VCO maximum frequency is 7.743 108 rad/sec (=12324 ppm) higher than ωp (6.28e10 rad/sec), but this value must be reduced because the actual DT is < 100%  (DT=50%), in order to obtain the maximum possible value of 4.71 108 rad/sec (=7499 ppm), that is the "rising" slew-rate of this CDR in the present conditions.
 * In a similar way, the "falling" slew-rate of this CDR is -7.22 108 rad/sec (=-11499 ppm). It is larger because of the offset between ωfr and ωp (2000 ppm, i.e. by 1.257e8 rad/sec).
 * The output phase catches up with the input after 4.9 nsec.
 * The bang-bang detector, that has been frozen to its upper level during the catch-up transient, starts now its typical pattern of bang-bang frequent jumps.
 * It may also be remarked that, as long as the PD follows its typical bang-bang pattern, the distance in phase between input and output (=the error signal) remains very close to zero, and there is no evidence of the steady-state phase error typical of linear systems. In this condition the PD operates very close to its middle point, where its gain is extremely high: the steady stye error of a type 1 system can be computed as the angular frequency offset, divided by the open loop gain. As the gain is almost infinite, the error is almost zero during this interval.
 * When 300 simulation steps have elapsed (5.35 nsec), the input signal starts an additional sinusoidal jitter with an angular frequency of 7.5 108 rad/sec and a peak amplitude of 1.20 rad.
 * The sinusoidal component of the input jitter starts with its maximum slope (9.0 108 rad/sec) and the slew-rate that the PLL can produce is slightly smaller: as indicated above it is 4.71 108 rad/sec
 * The output phase cannot follow the input but follows its maximum slope until the input slows down and it can track it again. This happens 2.46 nsec after the start of the sinusoidal jitter.
 * Then the tracking resumes until the falling slope of the input sinusoidal jitter becomes too steep and exceeds the maximum negative slew-rate that is -7.22 108 rad/sec.
 * Once there has been tracking at one peak of the input sinusoid, all the subsequent cycles are identical, and the average value of the phase error waveform generates the average drive error at the VCO input that corrects the ωp - ωffr difference.
 * The output phase cannot follow the input but follows its maximum slope until the input slows down and it can track it again. This happens 2.46 nsec after the start of the sinusoidal jitter.
 * Then the tracking resumes until the falling slope of the input sinusoidal jitter becomes too steep and exceeds the maximum negative slew-rate that is -7.22 108 rad/sec.
 * Once there has been tracking at one peak of the input sinusoid, all the subsequent cycles are identical, and the average value of the phase error waveform generates the average drive error at the VCO input that corrects the ωp - ωffr difference.
 * Once there has been tracking at one peak of the input sinusoid, all the subsequent cycles are identical, and the average value of the phase error waveform generates the average drive error at the VCO input that corrects the ωp - ωffr difference.

A 2nd order type 2 loop goes into slew rate limiting because of the limited HF gain of the loop filter
When tracking becomes difficult because the loop must operate close to its ability to track, the effort becomes evident by the periodic deviation of the phase comparator output (same period as the input jitter) from its average level. In case of a phase detector, such effort is made evident by a reduction of the bang-bang duty-cycle. Around the zero-crossing of the input jitter sinusoid, the PD output stays constant and indicates the onset of a phase error due to slewing.

 * The sinusoidal jitter signal must be considered in conjunction with the steady state error because a type 1 loop compensates all frequency differences and wander with a shift of the bias level of the signal driving the VCO. The slew rate slope of the CDR response is consequently increased in one direction and reduced by the same amount in the other direction. This would be exactly true if the VCO corresponded to its simulation model, but is just approximately true because the actual VCO characteristic is never so neat, symmetric and and simple.

Slewing can be defined as a contiguous sequence of ten or more identical phase-error indications.

When the jitter frequency is too high for a correct tracking, the slew-rate covers the entire jitter period, and the output jitter becomes a triangular saw-tooth of reduced amplitude.The CDR still tracks well because the steady-state frequency error ωp - ωfr is tracked as well, as can be seen in the asymmetry of the triangular output wave.

The following figure illustrates the above remarks with the phase signals of a typical CDR (in this example, a 2-2 loop with PFD). In this figure the slew rate occurs (at both low and high jitter frequencies) because of the very low gain of the loop filter at frequencies higher than ωz (the frequency of the zero of the loop filter).

The waveform (in black) of the VCO drive signal bang-bangs when there is no slewing, and slowly ramps away as long as the phase error keeps the same sign (constant slew-rate condition of either sign). The steep bang transitions and the slope of the ramps that follow implement the step response of the loop filter driven by the steps (bang-bangs) of the PD output. In the PD output, the slow ramp during slewing compensates any possible steady-state error of the loop output.

There is also -in a 2nd order type 2 loop- the other source of slew-rate generated by a frequency clamp (the overall limitation of the VCO frequency range) forced either by the saturation of the output of the loop filter at large signals, or by the saturation of the VCO characteristic at the extremes of its frequency range.

This second source of slew-rate obviously takes places with much larger Δω and much smaller ω. In type 1 loops it is the only source of slew-rate (as seen in the previous example).

Onset of slewing in a 2nd order type 2 CDR with bang-bang PD and its curve of VCO range limits
This example is interesting because it corresponds to an architecture that is quite common, and also because it points out an intriguing analogy between the linear model of a 2-2 loop and this application of a non-linear 2-2 architecture.

The frequency of a VCO in a 2-2 CDR with bang-bang PD is limited in its excursion either because of:
 * 1) the limited amplification (variable with the jitter frequency) of the filter block, that receives the square wave of fixed amplitude coming out of the PD and that then drives the VCO frequency, or
 * 2) the rapid fall of the VCO gain at the extremes of the VCO characteristic (to simplify it is assumed here that the VCO characteristic is linear inside the range, and flat outside).

The limitation of the VCO frequency is therefore a curve as in the following figure:

The curve plotted (fine red line) approximates the curve of max frequency swing of the VCO using the condition of onset of slewing.

It should be kept in mind that the linear model (green curve in the figure at the page beginning) plots a tolerance function, while the onset of slewing plots a prudent boundary that is lower than the actual tolerance function.

As long as the loop keeps on tracking, the PD maintains its continuous bang-bang and the phase error in front of the PD remains very limited. For a run-length of n, it is limited by 2 Δφb-b + (n-1)Δφf p-ffr. .

For jitter frequencies of ωj higher than ωz, the waveform at the PD output is amplified by Gf and then used to drive the VCO.

For jitter frequencies ωj lower than ωz, the fundamental component of the waveform at the PD output is amplified by Gfωz / ωj, which is higher than Gf, and the loop is able to track at the onset of slewing following the slope (-20 dB/dec) of the gain Gfωz / ωj versus ωj curve, down to the point where the VCO frequency swing can grow no more and the curve becomes horizontal.

As long as the slew-rate of the incoming jitter Ajωj corresponds to a frequency that is below the curve in the figure above, there will be no slewing and the incoming jitter will be perfectly tolerated.

If the diagram above ( tolerable frequency swing as a function of the frequency of the sinusoidal input jitter) is translated into the classic tolerance format ( tolerable phase amplitude as a function of the frequency of the sinusoidal input jitter),

then the slopes of 0 and of -20 dB/dec become respectively -20 and - 40 dB/dec. The addition of the horizontal asymptote corresponding to the tolerance always present because of the LEO buffer, the tolerance function is approximated by the mask in the following figure:
 * In the segment at -40 dB/dec, there are two 90° phase rotations at play:

This consideration (fully valid in a linear domain) still holds good here: it can be found that the CDR slewing does not appear starting from the instants of maximum slope of the input jitter (what it does normally in correspondence to a -20 dB/dec slope of the tolerance curve),
 * the negative slope of the loop filter
 * the integration frequency-to-phase in the VCO.

but at the instants of peak of the input jitter.

It may be said that this corresponds to a 90° rotation of the CDR output phase...

The following figure shows tolerance curves (in dB and in UI) obtained by numerical simulations.

It may be noted that the asymptotic tolerance at high frequencies is slightly lower that the minimum usually specified of 0.15 UI.

This is a consequence of having used the pessimistic value of 1 rad for the Lateral Eye Opening.

The limited range of the (possible) elastic buffer
In general, a buffer may come in various forms, grouped here below in three categories of decreasing added delay: Magnitude of [I1(jω) + I2(jω)] = |I1(jω) + I2(jω)| = Φmax
 * Buffer memories used to store and forward large amounts of bits, like packets of a TCP/IP protocol.
 * They are often organised by byte, and are written and read with clocks running at the byte rate.
 * The memory is so deep -and the added delay is so large with respect to the bit period- that they easily absorb the timing jitter or the frequency mismatch between the write and the read clocks.
 * These buffers could be located inside a single clock domain or at the border of two different domains.
 * Elastic buffers between clock domains.
 * They are meant to absorb or at least to mitigate the effects of jitter, wander and drifts between the clocks of the two domains.
 * Their depth is chosen to absorb the clocks drifts with as rare slips as possible. These elastic buffers are not as deep as a buffer memory but much deeper than a phase adder in a phase aligner (see below).
 * As there is no prior knowledge of the drift sign, their end of range triggers a reset to the central point.
 * They deal with serial transmissions and are essentially based on shift registers clocked with the incoming clock and read with the local clock.
 * Their tolerance is studied using linear phase ramps.
 * Phase adders for Phase aligner CDRs.
 * Only a clock domain is involved and there are no d.c. drifts between the incoming signal and the local clock.
 * They are meant to absorb just the a.c. jitter that has been generated in a relatively short timing loop inside an equipment or in a downstream/upstream loop of an access network.
 * Their tolerance is studied with sinusoidal jitter i.e. with Fourier transforms.
 * The border of linear operation (= of the tolerance) of a phase adder is typically found when the algebraic sum of the phases of its two inputs reaches the minimum or the maximum value allowed for the output range of the adder.
 * It does not depend on the value of either input, even though in practice such limits of tolerance are often reached when one input simply swings too wide.
 * The mathematical model shall be:
 * where +/- Φmax are the largest values that the adder can process linearly.
 * As there is no drift at all, but just alternating jitter, at the end-of-range the adder saturates (as explained below for the delay line implementation).
 * The model (of steady state condition), with |I1(jω) + I2(jω)| = 0 for the mid output point, is chosen because it matches the corresponding hypothesis that, if the initial delay was not the mid point, then a transient out-of-range with subsequent re-centering has occurred.
 * The phase adder of a PLL is a delay line
 * In PLLs the phase adder is implemented in the form of a delay line . The input of the delay line is one input of the adder, while the other input simply controls the amount of delay added to the signal that enters the delay line.
 * Such adders can tolerate an added delay between zero and the maximum length of the delay line, Dmax.

 The delay can also be measured as a phase, in units of radians at the angular frequency of interest. If a delay is known in seconds, then it can be be converted into radian multiplying it by the angular clock frequency: [sec] * [rad * sec−1] = [rad].
 * The tolerance limit will be in such cases modeled as:

0 < added delay < Dmax.
 * When the tolerance extremes are exceeded, the delay lines simply saturates in the sense that it either does not add any delay or that it keeps on adding its maximum delay Dmax. In terms of signal phases, the output remains constant at its minimum or maximum value.
 * In the case of a phase phase lock loop incorporating the delay line, this means opening the loop until the input jitter changes its direction of variation. The delay range is frozen while the input jitter waveform insists in the same direction and until it starts getting back. At that moment the lock resumes, but the delay range is now translated towards the average value of the incoming jitter by the amount of the sidetracking.
 * This achieves some sort of translation of the delay range towards re-centering around the average value of the input the jitter. It is important to observe that this takes place in a discontinuous mode, because the loop keeps on re-locking into the center of the closest pulse in the delayed waveform presented to its phase comparator. This adds an imprecision of ± π to the positioning of the delay line with respect to the incoming signal, and consequently to the loop jitter tolerance from that moment onwards.
 * The granularity of the delay line can be as coarse as about 1/3 of the line pulse period (π/2 - ε in theory), or as fine as fraction of one percent of such period. This granularity adds to the imprecision of the point above to reduce the resulting tolerance.
 * To model the phase tolerance curve associated to the delay line in the phase alignerthe following points are considered:
 * - Initial conditions. Sufficient re-centerings have occurred in the past, and presently the delay is centered with the inevitable imprecision of ± π
 * - A granularity of Φgran characterizes the delay line;
 * - total delay that the delay line can adjust is Dmax:
 * The tolerance limit imposed by the phase adder to the phase aligner is a fixed amount at all frequencies and is modeled as follows:

|X(jω)| < (Dmax/2 - π - Φgran)

The curves in the figure above can be seen as examples of tolerance of phase adders in the flat part at low frequencies.. Such clamping of the curves at low frequencies if present because the tolerance of the elastic buffer (present in the circuits of the figure) is independent from the jitter frequency and only depends on the length of the buffer. The tolerance due to the lateral eye closure further reduces the tolerance at mid and high frequencies and ultimately flattens out at very high frequencies, as seen just above.

Jitter tolerance and VCO modulation

 * When the CDR operates along the tolerance border, its periodic output is made by two periodic signal parts:
 * the tracking
 * the error.

 * When tracking is the larger part, the angle ( function of $$\omega_m$$ ) represented by the FM modulation index $$ h $$ of the VCO overlaps (almost) with the tolerance function.

 * When tracking is the smaller part and the error is the larger, the tolerance angle tends to the buffer depth and the modulation index becomes very small.

 * Both jitter tolerance and FM modulation index $$ h $$ are defined in the sinusoidal regime.

Focusing on the PLL VCO as a FM modulator:

 * modulation index $$h = \tfrac{\Delta{}f}{f_m} = \tfrac{\Delta{}f_{VCO}}{f_m} = \tfrac{\Delta{}\omega_{VCO}}{\omega_m} $$
 * where $$f_m\,$$ (or $$\omega_m\,$$) is the highest frequency component present in the modulating signal ( i.e. in the VCO drive signal ), and $$\Delta{}f\,$$ (or $$\Delta{}\omega\,$$)is the peak frequency-deviation ( i.e. the maximum deviation of the VCO instantaneous frequency from the un-modulated carrier frequency $$f_{fr}$$ (or $$\omega_{fr}$$).

 * The modulation index is also a measure ( in rad) of the peak phase deviation of the VCO output, with respect to the phase of the VCO output if the VCO was running at ffr or at fp
 *  A d.c. component in the modulating signal (like fp - ffr) does not change the modulation index, but simply shifts the carrier frequency (in the specific example, from ffr to fp), which is nothing but d.c. FM .

 * The jitter tolerance is defined and measured for individual frequencies of input jitter sinusoids. For each frequency the amplitude of the input sinusoid  is increased up to the value where errors appear.
 * These errors are typically generated when the VCO output jitters too wide and samples the signal eye outside the corners defined by the Lateral Eye Tolerance.
 * It is convenient to define some sections of the jitter tolerance functions by the onset of other non linearities of the CDR (slew-rate), but in actuality such sections lie slightly below it the true  border of tolerance.

The two quantities are closely related. The jitter tolerance limit In a CDR  coincides in a wide frequency range with  $$h$$, that is the phase deviation of the VCO in that CDR.
 * Definition : $$\omega_{mc}$$ is the frequency at which the corner with the high frequency asymptote takes place in the tolerance curve.
 * This definition of $$\omega_{mc}$$ applies both to linear type 1 slave CDRs and to bang-bang CDRs of type 1 and 2, as:
 * there is no more tracking at higher frequencies in both cases, and
 * the two cases cover all the applications of CDRs.
 * Moreover, $$\omega_{mc}$$ is the 3 dB point of the tolerance curve both for a the linear architecture and for the two bang-bang architectures used in practical applications.
 * If the jitter frequency is exactly $$\omega_{mc}$$, the tolerance value is about 3 dB higher than the high frequency asymptote, i.e. the tolerance is:
 * $$\sqrt{2} \left( \Phi_ {LEO} - E_ {S} \right)   $$
 * The sinusoidal jitter amplitude tolerated by the CDR input at $$\omega_{mc}$$ is the sum of two (about equal but orthogonal) sinusoids. One part represents what is not tracked by the CDR (i.e. is absorbed by the phase comparator buffer)
 * The other half is tracked because it appears at the output of the VCO. Therefore:
 * $$h = \left( \Phi_ {LEO} - E_ {S} \right) \approx \Phi_{LEO} $$

 * At frequencies >> $$\omega_{mc}$$ the tolerance is exactly the lateral eye opening ΦLEO (more precisely:  ΦLEO - steady state error).
 * The modulating signal ( i.e. of the VCO input ) originates at the phase-comparator output.
 * By definition, the phase comparator output is the phase-error that the loop is unable to track.
 * In sinusoidal regime, the CDR loop is unable to track the frequencies much higher than $$\omega_{mc}$$, and those high frequencies do not reach and do not modulate the VCO.
 * At those high frequencies the CDR input can jitter up to about ± ΦLEO and still be tolerated, but the VCO output phase does not jitter appreciably.
 * Nonetheless, if the definition of $$ h $$ is stretched a bit, it can be seen that the VCO modulating signal depends on the input jitter frequency according to 1/f. A point of this function is already known at $$\omega_{mc}$$. As a result, in this frequency region:
 * $$h \approx  \Phi_{LEO}     \frac{\omega_{mc}}{\omega_m} $$

 * If the jitter frequency decreases down from $$\omega_{mc}$$, the CDR tracks the input jitter more and more (i.e. the VCO phase deviates more and more ).
 * The amplitude of the tolerated jitter becomes >> ΦLEO.
 * An input signal of increasing amplitude is accepted (= tolerated) the test frequency $$\omega_{m}$$ decreases, but there is always a periodic error of constant peak amplitude VCO output.
 * The VCO output can be seen as the sum of a sinusoid identical to the CDR input, plus an error signal. The error signal has the same period of the CDR input sinusoid, may or may not be sinusoidal, is always out of phase with the input of the CDR and has a peak of $$ \left( \Phi_{LEO}  - E_ {S} \right) \approx  \Phi_{LEO}  $$.
 * From $$\omega_{mc}$$ downwards to lower frequencies, the amplitude of the input sinusoid increases (with $$ \tfrac{1}{\omega}$$ or$$ \tfrac{1}{\omega^2}$$, while the periodic error signal keeps the same peak value and becomes therefore rapidly negligible.
 * As a result, in this frequency region:
 * $$h \approx  {jitter } \ {tolerance} \ function $$

In the sinusoidal regime it is possible to contrast directly the FM modulation index of the VCO ( $$h$$ ) with the tolerance function of the whole CDR.

The two functions ( of $$ \omega_m $$ ) vary, depending on the CDR architecture, on the loop gain G, etc..

In any case, the two functions practically overlap each other for low and medium values of $$ \omega_m $$ (up to $$ \omega_{mc} $$ ), and diverge at higher values of $$ \omega_m $$, where they follow respectively a -20 dB/dec asymptote and a flat asymptote.

The three figures below show the simplified asymptotic Bode plots for both functions, in the cases of the 3 fundamental architectures used in CDR applications.

Narrowband FM

As long as the modulation index h of the FM remains below 1 (say no more than 0.3 ), the FM is called narrow-band and its spectrum is very close to the spectrum of an amplitude modulation (AM) that be generated with the same carrier wave and the same modulating signal.
 * The ΦLEO is, with a first approximation valid for most applications of CDRs, ≥ 1 rad (i.e. ≥ 0.15 UI ).
 * In normal tracking conditions the CDR operates with at least 10 dB margin, that brings the jitter peak down to about 0.3 rad.
 * With h < 0.3 rad, FM is a narrowband FM.

In the CDR, the baseband jitter spectrum present at the VCO input becomes, at the VCO output, very similar to an AM spectrum modulated around ffr, and keeps its "shape" without the distortion typical of wideband FM.
 * During acquisition transients and in case of extremely noisy applicative conditions, the VCO modulation may occasionally deviate from this "quiet" condition.

Considerations
(because it depends on non-linearities for its definition, although it is computed within the boundary of the circuit linear operation, and because it may be different for different architectural variants belonging to the same model architecture. See the example of the 1st order type 1 phase aligner that has a different tolerance from the 1st order type 1 slave).
 * It should be emphasized that the jitter tolerance function is:
 * neither a transfer function (its output is not generated with input sinusoids of unit amplitude)
 * nor a part of the mathematical model in the strict sense
 * In the cases where the tolerance function is determined only by the maximum difference acceptable inside the phase comparator, the tolerance limit is a consequence of the one sided eye opening and not of the comparator range (that is larger).
 * Exceeding the comparator range (±π) generates slips (= very high BER), but exceeding only the lateral eye opening just generates error bursts that can be rather short. The lateral eye opening is reached always before the comparator range is exceeded: the tolerance function (as well as the tolerance curve!) corresponds to the errors that occur at the eye corners. Phase comparator slips (and associated errors) do occur in a CDR, but beyond the limit of tolerance set by the lateral eye aperture.
 * The high frequency jitter tolerance corresponds to the LEO and is visible (and measurable) as the horizontal asymptote at the highest frequencies of jitter. From a certain frequency up:
 * the PLL does not track at all,
 * the jitter imposed to the input signal moves back and forward the signal transitions (already affected by I.I., noise etc.) and
 * the sampling clock does not move.
 * The tolerance function, derived from equating the phase error to the eye opening, in such case replicates very well, in magnitude, characteristic asymptotes and corner frequencies the diagram that is obtained with actual measurements.

 * Where different phenomena cause each a different region of tolerance for a CDR, then the overall CDR tolerance will correspond to a combination of those tolerance regions.