text:
X86 Assembly/High-Level Languages

Very few projects are written entirely in assembly. It's often used for accessing processor-specific features, optimizing critical sections of code, and very low-level work, but for many applications, it can be simpler and easier to implement the basic control flow and data manipulation routines in a higher level language, like C. For this reason, it is often necessary to interface between assembly language and other languages.

Compilers
The first compilers were simply text translators that converted a high-level language into assembly language. The assembly language code was then fed into an assembler, to create the final machine code output. The GCC compiler still performs this sequence (code is compiled into assembly, and fed to the AS assembler). However, many modern compilers will skip the assembly language and create the machine code directly.

Assembly language code has the benefit that it is in one-to-one correspondence with the underlying machine code. Each machine instruction is mapped directly to a single Assembly instruction. Because of this, even when a compiler directly creates the machine code, it is still possible to interface that code with an assembly language program. The important part is knowing exactly how the language implements its data structures, control structures, and functions. The method in which function calls are implemented by a high-level language compiler is called a calling convention.

The calling convention is a contract between the function and caller of the function and specifies several parameters:

 * 1) How the arguments are passed to the function, and in what order? Are they pushed onto the stack, or are they passed in via the registers?
 * 2) How are return values passed back to the caller? This is usually via registers or on the stack.
 * 3) What processor states are volatile (available for modification)? Volatile registers are available for modification by the function. The caller is responsible for saving the state of those registers if needed. Non-volatile registers are guaranteed to be preserved by the function. The called function is responsible for saving the state of those registers and restoring those registers on exit.
 * 4) The function prologue and epilogue, which sets up the registers and stack for use within the function and then restores the stack and registers before exiting.

CDECL
For C compilers, the CDECL calling convention is the de facto standard. It varies by compiler, but the programmer can specify that a function be implemented using CDECL usually by pre-appending the function declaration with a keyword, for example __cdecl in Visual studio:

in gcc it would be __attribute__( (__cdecl__ )):

CDECL calling convention specifies a number of different requirements:

 * 1) Function arguments are passed on the stack, in right-to-left order.
 * 2) Function result is stored in EAX/AX/AL
 * 3) Floating point return values will be returned in ST0
 * 4) The function name is pre-appended with an underscore.
 * 5) The arguments are popped from the stack by the caller itself.
 * 6) 8-bit and 16-bit integer arguments are promoted to 32-bit arguments.
 * 7) The volatile registers are: EAX, ECX, EDX, ST0 - ST7, ES and GS
 * 8) The non-volatile registers are: EBX, EBP, ESP, EDI, ESI, CS and DS
 * 9) The function will exit with a RET instruction.
 * 10) The function is supposed to return values types of class or structure via a reference in EAX/AX. The space is supposed to be allocated by the function, which unable to use the stack or heap is left with fixed address in static non-constant storage. This is inherently not thread safe. Many compilers will break the calling convention:
 * 11) GCC has the calling code allocate space and passes a pointer to this space via a hidden parameter on the stack. The called function writes the return value to this address.
 * 12) Visual C++ will:
 * 13) Pass POD return values 32 bits or smaller in the EAX register.
 * 14) Pass POD return values 33-64 bits in size via the EAX:EDX registers
 * 15) For non-POD return values or values larger than 64-bits, the calling code will allocate space and passes a pointer to this space via a hidden parameter on the stack. The called function writes the return value to this address.

CDECL functions are capable of accepting variable argument lists. Below is example using cdecl calling convention:

In order to assemble, link and run the program we need to do the following:

STDCALL
STDCALL is the calling convention that is used when interfacing with the Win32 API on Microsoft Windows systems. STDCALL was created by Microsoft, and therefore isn't always supported by non-Microsoft compilers. It varies by compiler but, the programmer can specify that a function be implemented using STDCALL usually by pre-appending the function declaration with a keyword, for example __stdcall in Visual studio:

in gcc it would be __attribute__( (__stdcall__ )):

STDCALL has the following requirements:

 * 1) Function arguments are passed on the stack in right-to-left order.
 * 2) Function result is stored in EAX/AX/AL
 * 3) Floating point return values will be returned in ST0
 * 4) 64-bits integers and 32/16 bit pointers will be returned via the EAX:EDX registers.
 * 5) 8-bit and 16-bit integer arguments are promoted to 32-bit arguments.
 * 6) Function name is prefixed with an underscore
 * 7) Function name is suffixed with an "@" sign, followed by the number of bytes of arguments being passed to it.
 * 8) The arguments are popped from the stack by the callee (the called function).
 * 9) The volatile registers are: EAX, ECX, EDX, and ST0 - ST7
 * 10) The non-volatile registers are: EBX, EBP, ESP, EDI, ESI, CS, DS, ES, FS and GS
 * 11) The function will exit with a RET n instruction, the called function will pop n additional bytes off the stack when it returns.
 * 12) POD return values 32 bits or smaller will be returned in the EAX register.
 * 13) POD return values 33-64 bits in size will be returned via the EAX:EDX registers.
 * 14) Non-POD return values or values larger than 64-bits, the calling code will allocate space and passes a pointer to this space via a hidden parameter on the stack. The called function writes the return value to this address.

STDCALL functions are not capable of accepting variable argument lists.

For example, the following function declaration in C:

_stdcall void MyFunction(int, int, short);

would be accessed in assembly using the following function label:

_MyFunction@12

Remember, on a 32 bit machine, passing a 16 bit argument on the stack (C "short") takes up a full 32 bits of space.

FASTCALL
FASTCALL functions can frequently be specified with the __fastcall keyword in many compilers. FASTCALL functions pass the first two arguments to the function in registers, so that the time-consuming stack operations can be avoided. FASTCALL has the following requirements:

 * 1) The first 32-bit (or smaller) argument is passed in ECX/CX/CL (see )
 * 2) The second 32-bit (or smaller) argument is passed in EDX/DX/DL
 * 3) The remaining function arguments (if any) are passed on the stack in right-to-left order
 * 4) The function result is returned in EAX/AX/AL
 * 5) The function name is prefixed with an "@" symbol
 * 6) The function name is suffixed with an "@" symbol, followed by the size of passed arguments, in bytes.

C++ Calling Conventions (THISCALL)
The C++ THISCALL calling convention is the standard calling convention for C++. In THISCALL, the function is called almost identically to the CDECL convention, but the this pointer (the pointer to the current class) must be passed.

The way that the this pointer is passed is compiler-dependent. Microsoft Visual C++ passes it in ECX. GCC passes it as if it were the first parameter of the function. (i.e. between the return address and the first formal parameter.)

Pascal Calling Conventions
The Pascal convention is essentially identical to cdecl, differing only in that:

 * 1) The parameters are pushed left to right (logical western-world reading order)
 * 2) The routine being called must clean the stack before returning

Additionally, each parameter on the 32-bit stack must use all four bytes of the DWORD, regardless of the actual size of the datum.

This is the main calling method used by Windows API routines, as it is slightly more efficient with regard to memory usage, stack access and calling speed.

Note: the Pascal convention is NOT the same as the Borland Pascal convention, which is a form of fastcall, using registers (eax, edx, ecx) to pass the first three parameters, and also known as Register Convention.

C/C++
This Borland C++ example splits  into two bytes in , the first containing high 4 bits and low 4 bits in the second.

Pascal
The FreePascal Compiler (FPC) and GNU Pascal Compiler (GPC) allow -blocks. While GPC only accepts AT&T-syntax, FPC can work with both, and allows a direct pass-through to the assembler. The following two examples are written to work with FPC (regarding compiler directives).

In FreePascal you can also write whole functions in assembly language. Also note, that if you use labels, you have to declare them beforehand (FPC requirement):

title: X86 Assembly/High-Level Languages


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X86 Assembly/MASM Syntax

This page will explain x86 Programming using MASM syntax, and will also discuss how to use the macro capabilities of MASM. Other assemblers, such as NASM and FASM, use syntax different from MASM, similar only in that they all use Intel syntax.

Instruction Order
MASM instructions typically have operands reversed from GAS instructions. for instance, instructions are typically written as Instruction Destination, Source.

The mov instruction, written as follows:

mov al, 05h

will move the value 5 into the al register.

Instruction Suffixes
MASM does not use instruction suffixes to differentiate between sizes (byte, word, dword, etc).

Macros
MASM is known as either the "Macro Assembler", or the "Microsoft Assembler", depending on who you talk to. But no matter where your answers are coming from, the fact is that MASM has a powerful macro engine, and a number of built-in macros available immediately.

MASM directives
MASM has a large number of directives that can control certain settings and behaviors. It has more of them compared to NASM or FASM, for example.

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: X86 Assembly/MASM Syntax


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X86 Assembly/HLA Syntax

HLA Syntax
HLA accepts assembly written using a high-level format, and converts the code into another format (MASM or GAS, usually).

In MASM, for instance, we could write the following code:

mov EAX, 0x05

In HLA, this code would become:

mov(0x05, EAX);

HLA uses the same order-of-operations as GAS syntax, but doesn't require any of the name decoration of GAS. Also, HLA uses the parenthesis notation to call an instruction. HLA terminates its lines with a semicolon, similar to C or Pascal.

High-Level Constructs
Some people criticize HLA because it "isn't low-level enough". This is false, because HLA can be as low-level as MASM or GAS, but it also offers the options to use some higher-level abstractions. For instance, HLA can use the following syntax to pass eax as an argument to the Function1 function:

push(eax); call(Function1);

But HLA also allows the programmer to simplify the process, if they want:

Function1(eax);

This is called the "parenthesis notation" for calling functions.

HLA also contains a number of different loops (do-while, for, until, etc..) and control structures (if-then-else, switch-case) that the programmer can use. However, these high-level constructs come with a caveat: Using them may be simple, but they translate into MASM code instructions. It is usually faster to implement the loops by hand.

title: X86 Assembly/HLA Syntax


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X86 Assembly/x86 Assemblers

There are a number of different assemblers available for x86 architectures. This page will list some of them, and will discuss where to get the assemblers, what they are good for, and where they are used the most.

GNU Assembler (GAS)
The GNU assembler is most common as the assembly back-end to the GCC compiler. One of the most compelling reasons to learn to program GAS (as it is frequently abbreviated) is to write inline assembly instructions (assembly code embedded in C source code), as these instructions (when compiled by the gcc) need to be in GAS syntax. GAS uses the AT&T syntax for writing the assembly language, which some people claim is more complicated, but other people say it is more informative.

Note: Recent versions of GCC include the "-masm" option which, when set to "-masm=intel", allow the user to define inline assembly using the Intel syntax. The equivalent option for GAS is "-msyntax=intel" or using the ".intel_syntax" directive.

Microsoft Macro Assembler (MASM)
Microsoft's Macro Assembler, MASM, has been in constant production for many many years. Many people claim that MASM isn't being supported or improved anymore, but Microsoft denies this: MASM is maintained, but is currently in a bug-fixing mode. No new features are currently being added. However, Microsoft is shipping a 64-bit version of MASM with new 64-bit compiler suites. MASM is available from Microsoft as part of Visual C++, as a download from MSDN, or as part of the Microsoft DDK. The latest available version of MASM is version 11.x (ref.: www.masm32.com).

MASM uses the Intel syntax for its instructions, which stands in stark contrast to the AT&T syntax used by the GAS assembler. Most notably, MASM instructions take their operands in reverse order from GAS. This one fact is perhaps the biggest stumbling block for people trying to transition between the two assemblers.

MASM also has a very powerful macro engine, which many programmers use to implement a high-level feel in MASM programs.

JWASM
JWASM is a 16, 32 and 64-bit assembler for 80x86 platforms, based upon Open Watcom's WASM, and was created by Japheth.

While syntactically compatible with MASM, it is faster, and its source code is freely available under the Sybase Open Watcom Public License, and thus it is free for both commercial and non-commercial use. Furthermore, it supports ELF, and is thus the only cross-platform assembler supporting the popular MASM syntax. JWASM is actively being developed, and is generally regarded as the unofficial successor to MASM.

Netwide Assembler (NASM)
The Netwide Assembler, NASM, was started as an open-source initiative to create a free, retargetable assembler for 80x86 platforms. When the NASM project was started, MASM was still being sold by Microsoft (MASM is currently free), and GAS contained very little error checking capability. GAS was, after all, the backend to GCC, and GCC always feeds GAS syntax-correct code. For this reason, GAS didn't need to interface with the user much, and therefore writing code for GAS was very tough.

NASM uses a syntax which is "similar to Intel's but less complex".

The NASM users manual is found at http://www.nasm.us/doc/.

Features:
 * Cross platform: Like Gas, this assembler runs on nearly every platform, supposedly even on PowerPC Macs (though the code generated will only run on an x86 platform)
 * Open Source
 * Macro language (code that writes code)

Flat Assembler (FASM)
Although it was written in assembly, it runs on several operating systems, including DOS, DexOS, Linux, Windows, and BSD. Its syntax is similar to TASM's "ideal mode" and NASM's but the macros in this assembler are done differently.

Features:
 * Written in itself; and therefore its source code is an example of how to write in this assembler
 * Open source
 * Clean NASM-like syntax
 * Very very fast
 * Has macro language (code that writes code)
 * Built-in IDE for DOS and Windows
 * Creates binary, MZ, PE, ELF, COFF - no linker needed

YASM Assembler
YASM is a ground-up rewrite of NASM under the new BSD licence. YASM is designed to understand multiple syntaxes natively (NASM and GAS, currently). The primary focus of YASM is to produce "libyasm", a reusable library that can work with code at a low level, and can be easily integrated into other software projects.

HLA
HLA is an assembler front-end created by Randall Hyde and first popularized in his book "The Art of Assembly".

HLA accepts assembly written using a high-level format, and converts the code into another format (MASM or GAS, usually). Another assembler (MASM or GAS) will then assemble the instructions into machine code.

BBC BASIC for WINDOWS (proprietary)
The proprietary BBC BASIC for Windows supports the development of 32 bit x86  assembler targeting user mode for Windows using INTEL syntax, but does not currently permit the generation of standalone EXE's (without the inclusion of a proprietary runtime and environment). Macro assembly is possible by use the BBC BASIC environment, defining macros by means of BASIC functions wrapped around the relevant code.

More information is in the Assembler section of the manual

X86アセンブラ/x86アセンブラ

title: X86 Assembly/x86 Assemblers


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User talk:85.65.37.172

Welcome to Wikibooks, collection of open-content textbooks! You don't have to log in to read or edit articles on Wikibooks, but creating an account is quick, free and non-intrusive, requires no personal information, and gives you many benefits, including:
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title: User talk:85.65.37.172


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X86 Assembly/X86 Family

The term "x86" can refer both to an instruction set architecture and to microprocessors which implement it. The name x86 is derived from the fact that many of Intel's early processors had names ending in "86".

The x86 instruction set architecture originated at Intel and has evolved over time by the addition of new instructions as well as the expansion to 64-bits. As of 2009, x86 primarily refers to IA-32 (Intel Architecture, 32-bit) and/or x86-64, the extension to 64-bit computing.

Versions of the x86 instruction set architecture have been implemented by Intel, AMD and several other vendors, with each vendor having its own family of x86 processors.

Intel x86 Microprocessors

 * 8086/8087 (1978): The 8086 was the original x86 microprocessor, with the 8087 as its floating-point coprocessor. The 8086 was Intel's first 16-bit microprocessor with a 20-bit address bus, thus enabling it to address up to 1 MiB, although the architecture of the original IBM PC imposed a limit of 640 KiB of RAM, with the remainder reserved for ROM and memory-mapped expansion cards, such as video memory. This limitation is still present in modern CPUs, since they all support the backward-compatible "Real Mode" and boot into it.
 * 8088 (1979): After the development of the 8086, Intel also created the lower-cost 8088. The 8088 was similar to the 8086, but with an 8-bit data bus instead of a 16-bit bus. The address bus was left untouched.
 * 80186/80187 (1982): The 186 was the second Intel chip in the family; the 80187 was its floating point coprocessor. Except for the addition of some new instructions, optimization of some old ones, and an increase in the clock speed, this processor was identical to the 8086.
 * 80286/80287 (1982):The 286 was the third model in the family; the 80287 was its floating point coprocessor. The 286 introduced the “Protected Mode” mode of operation, in addition to the “Real Mode” that the earlier models used. All subsequent x86 chips can also be made to run in real mode or in protected mode. Switching back from protected mode to real mode was initially not supported, but found to be possible (although relatively slow) by resetting the CPU, then continuing in real mode. Although the processor featured an address bus with 24 lines (24 bits, thus enabling to address up to 16 MiB), these could only be used in protected mode. In real mode, the processor was still limited to the 20-bits address bus.
 * 80386 (1985): The 386 was the fourth model in the family. It was the first Intel microprocessor with a 32-bit word. The 386DX model was the original 386 chip, and the 386SX model was an economy model that used the same instruction set, but which only had a 16-bit data bus. Both featured a 32-bits address bus, thus getting rid of the segmented addressing methods used in the previous models and enabling a "flat" memory model, where one register can hold an entire address, instead of relying on two 16-bit registers to create a 20-bit/24-bit address. The flat memory layout was only supported in protected mode. Also, contrary to the 286, it featured an "unreal mode" in which protected-mode software could switch to perform real-mode operations (although this backward compatibility was not complete, as the physical memory was still protected). The 386EX model is still used today in embedded systems,
 * 80486 (1989):The 486 was the fifth model in the family. It had an integrated floating point unit for the first time in x86 history. Early model 80486 DX chips were found to have defective FPUs. They were physically modified to disconnect the FPU portion of the chip and sold as the 486SX (486-SX15, 486-SX20, and 486-SX25).  A 487 "math coprocessor" was available to 486SX users and was essentially a 486DX with a working FPU and an extra pin added.  The arrival of the 486DX-50 processor saw the widespread introduction of fan assisted heat-sinks being used to keep the processors from overheating.
 * Pentium (1993): Intel called it the “Pentium” because they couldn't trademark the code number “80586”. The original Pentium was a faster chip than the 486 with a few other enhancements; later models also integrated the MMX instruction set.
 * Pentium Pro (1995): The Pentium Pro was the sixth-generation architecture microprocessor, originally intended to replace the original Pentium in a full range of applications, but later reduced to a more narrow role as a server and high-end desktop chip.
 * Pentium II (1997): The Pentium II was based on a modified version of the P6 core first used for the Pentium Pro, but with improved 16-bit performance and the addition of the MMX SIMD instruction set, which had already been introduced on the Pentium MMX.
 * Pentium III (1999): Initial versions of the Pentium III were very similar to the earlier Pentium II, the most notable difference being the addition of SSE instructions.
 * Pentium 4 (2000): The Pentium 4 had a new 7th generation "NetBurst" architecture. Pentium 4 chips also introduced the notions “Hyper-Threading”, and “Multi-Core” chips.
 * Core (2006): The architecture of the Core processors was actually an even more advanced version of the 6th generation architecture dating back to the 1995 Pentium Pro. The limitations of the NetBurst architecture, especially in mobile applications, were too great to justify creation of more NetBurst processors. The Core processors were designed to operate more efficiently with a lower clock speed. All Core branded processors had two processing cores; the Core Solos had one core disabled, while the Core Duos used both processors.
 * Core 2 (2006): An upgraded, 64-bit version of the Core architecture. All desktop versions are multi-core.
 * i Series (2008): The successor to Core 2 processors, with the i7 line featuring Hyper-Threading.
 * Celeron (first model 1998): The Celeron chip is actually a large number of different chip designs, depending on price. Celeron chips are the economy line of chips, and are frequently cheaper than the Pentium chips—even if the Celeron model in question is based off a Pentium architecture.
 * Xeon (first model 1998): The Xeon processors are modern Intel processors made for servers, which have a much larger cache (measured in MiB in comparison to other chips' KiB-sized cache) than the Pentium microprocessors.

AMD x86 Compatible Microprocessors

 * Athlon : Athlon is the brand name applied to a series of different x86 processors designed and manufactured by AMD. The original Athlon, or Athlon Classic, was the first seventh-generation x86 processor and, in a first, retained the initial performance lead it had over Intel's competing processors for a significant period of time.
 * Turion : Turion 64 is the brand name AMD applies to its 64-bit low-power (mobile) processors. Turion 64 processors (but not Turion 64 X2 processors) are compatible with AMD's Socket 754 and are equipped with 512 or 1024 KiB of L2 cache, a 64-bit single channel on-die memory controller, and an 800 MHz HyperTransport bus.
 * Duron : The AMD Duron was an x86-compatible computer processor manufactured by AMD. It was released as a low-cost alternative to AMD's own Athlon processor and the Pentium III and Celeron processor lines from rival Intel.
 * Sempron : Sempron is, as of 2006, AMD's entry-level desktop CPU, replacing the Duron processor and competing against Intel's Celeron D processor.
 * Opteron : The AMD Opteron is the first eighth-generation x86 processor (K8 core), and the first of AMD's AMD64 (x86-64) processors. It is intended to compete in the server market, particularly in the same segment as the Intel Xeon processor.

X86アセンブラ/x86ファミリ

title: X86 Assembly/X86 Family


text:
Talk:Botany/Magnoliophyta

added some stuff. Tried to not anthropomorphize the subject, and did not precisely succeed. Maybe I could try and make a simple visual chart showing co-evolution in hummingbirds and the flowers, with say three steps to show how the flowers evolved to be longer to better rub pollen on the bird, and the birds' beak evolved longer to better suck out more nectar- I could discuss how perhaps many different taxa of birds fed on the flower, but when the long flower became prevalent, only the birds that would evolve longer beaks to suck all of the nectar would still find it worth their while to go after those flowers. I can see myself going a little lamarkian if I'm not careful. Or even if I am.
 * I like the start. Develop it how you think best. I will likely do some editing, and may even move it to a different part of the textbook (for example, Chapter 5) if it seems to require that.  But for now, keep going with your ideas - marsh 18:31, 8 December 2005 (UTC)

title: Talk:Botany/Magnoliophyta


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X86 Assembly/Data Transfer

Some of the most important and most frequently used instructions are those that move data. Without them, there would be no way for registers or memory to even have anything in them to operate on.

Move
stands for move. Despite its name the  instruction copies the  operand into the  operand. After the operation both operands contain the same contents.

Modified flags

 * No FLAGS are modified by this instruction

Data swap
stands for exchange. The  instruction swaps the  operand with the  operand. It is like doing three  operations: except that no register needs to be reserved for temporary storage.
 * 1) from  to a temporary (another register),
 * 2) then from  to , and finally
 * 3) from the temporary storage to  ,

This exchange pattern of three consecutive  instructions can be detected by the DFU present in some architectures, which will trigger special treatment. The opcode for  is shorter though.

Operands
Any combination of register or memory operands, except that at most one operand may be a memory operand. You cannot exchange two memory blocks.

Modified Flags
None.

 Example

Application
If one of the operands is a memory address, then the operation has an implicit  prefix, that is, the exchange operation is atomic. This can have a large performance penalty.

However, on some platforms exchanging two (non-partial) registers will trigger the register renamer. The register renamer is a unit in that merely renames registers, so no data actually have to be moved. This is super fast (branded as “zero-latency”). Renaming registers could be useful since
 * some instructions either require certain operands to be located in specific register, but data will be needed later on,
 * or encoding some opcodes is shorter if one of the operands is the accumulator register.

The   instruction is used for changing the Byte order (LE ↔ BE) of 16-bit values, because the   instruction is only available for 32-, and 64-bit values. You do so by addressing partial registers, e. g..

It is also worth noting that the common  (no operation) instruction, , is the opcode for.

Data swap based on comparison
stands for compare and exchange. Exchange is misleading as no data are actually exchanged.

The  instruction has one implicit operand: the  / /  depending on the size of.

 * 1) The instruction compares  to  / /.
 * 2) If they are equal,  becomes  . (   =   )
 * 3) Otherwise,  / /  becomes.

Unlike  there is no implicit   prefix, and if the instruction is required to be atomic,   has to be prefixed.

Operands
has to be a register. may be either a register or memory operand.

Modified flags

 * ≔   = ( | | ) [depending on  ’s size]
 * ,,  ,  ,  are altered, too.

Application
The following example shows how to use the  instruction to create a spin lock which will be used to protect the result variable. The last thread to grab the spin lock will get to set the final value of result :

Move with zero extend
stands for move with zero extension. Like the regular  the   instruction copies data from the  operand to the  operand, but the remaining bits in  that are not provided by  are filled with zeros. This instruction is useful for copying a small, unsigned value to a bigger register.

Operands
has to be a register, and can be either another register or a memory operand. For this operation to make sense has to be larger than.

Modified flags
There are none.

Move with sign extend
stands for move with sign extension. The  instruction copies the  operand in the  operand and pads the remaining bits not provided by  with the sign bit (the MSB) of.

This instruction is useful for copying a signed small value to a bigger register.

Operands
accepts the same operands as.

Modified Flags
does not modify any flags, either.

Move String
Move byte.

The  instruction copies one byte from the memory location specified in   to the location specified in. If the direction flag is cleared, then  and   are incremented after the operation. Otherwise, if the direction flag is set, then the pointers are decremented. In that case the copy would happen in the reverse direction, starting at the highest address and moving toward lower addresses until  is zero.

Operands
There are no explicit operands, but
 * determines the number of iterations,
 * specifies the source address,
 * the destination address, and
 * DF is used to determine the direction (it can be altered by the  and   instruction).

Modified flags
No flags are modified by this instruction.

Example
Move word

The  instruction copies one word (two bytes) from the location specified in   to the location specified in. It basically does the same thing as, except with words instead of bytes.

 Operands

None.

 Modified flags

 * No FLAGS are modified by this instruction

 Example

Load Effective Address
stands for load effective address. The  instruction calculates the address of the  operand and loads it into the  operand.

Operands

 * Immediate
 * Register
 * Memory
 * Register

Modified flags

 * No FLAGS are modified by this instruction

Note
Load Effective Address calculates its  operand in the same way as the   instruction does, but rather than loading the contents of that address into the   operand, it loads the address itself.

can be used not only for calculating addresses, but also general-purpose unsigned integer arithmetic (with the caveat and possible advantage that FLAGS are unmodified). This can be quite powerful, since the  operand can take up to 4 parameters: base register, index register, scalar multiplier and displacement, e.g.   (Intel syntax) or   (GAS syntax). The scalar multiplier is limited to constant values 1, 2, 4, or 8 for byte, word, double word or quad word offsets respectively. This by itself allows for multiplication of a general register by constant values 2, 3, 4, 5, 8 and 9, as shown below (using NASM syntax):

Conditional Move
stands for conditional move. It behaves like  but the execution depends on various flags. There are following instruction available:

Operands
has to be a register. can be either a register or memory operand.

Application
The  instruction can be used to eliminate branches, thus usage of   instruction avoids branch mispredictions. However, the  instructions needs to be used wisely: the dependency chain will become longer.

General
General purpose byte or word transfer instructions:
 * copy byte or word from specified source to specified destination
 * copy byte or word from specified source to specified destination

 * copy specified word to top of stack.
 * copy specified word to top of stack.

 * copy word from top of stack to specified location
 * copy word from top of stack to specified location

 * copy all registers to stack
 * copy all registers to stack

 * copy words from stack to all registers
 * copy words from stack to all registers

 * Exchange bytes or exchange words
 * Exchange bytes or exchange words

 * translate a byte in  using a table in memory
 * translate a byte in  using a table in memory

Input/Output
These are I/O port transfer instructions:
 * copy a byte or word from specific port to accumulator
 * copy a byte or word from specific port to accumulator

 * copy a byte or word from accumulator to specific port
 * copy a byte or word from accumulator to specific port

Address Transfer Instruction
Special address transfer Instructions:
 * load effective address of operand into specified register
 * load effective address of operand into specified register

 * load DS register and other specified register from memory
 * load DS register and other specified register from memory

 * load ES register and other specified register from memory
 * load ES register and other specified register from memory

Flags
Flag transfer instructions:
 * load  with the low byte of flag register
 * load  with the low byte of flag register

 * stores  register to low byte of flag register
 * stores  register to low byte of flag register

 * copy flag register to top of stack
 * copy flag register to top of stack

 * copy top of stack word to flag register
 * copy top of stack word to flag register

title: X86 Assembly/Data Transfer


text:
X86 Assembly/Control Flow

Almost all programming languages have the ability to change the order in which statements are evaluated, and assembly is no exception. The instruction pointer (EIP) register contains the address of the next instruction to be executed. To change the flow of control, the programmer must be able to modify the value of EIP. This is where control flow functions come in.

Comparison Instructions
Performs a bit-wise logical  on   and   the result of which we will refer to as   and sets the  (zero),  (sign) and   (parity) flags based on. is then discarded.

 Operands

reference accumulator
 * Register
 * Immediate
 * Register (where  can be encoded specially if   is an immediate value)
 * Memory

 Modified flags

 * ≔ MostSignificantBit
 * ≔ ( = 0), so a set   means,   and   do not have any set bits in common
 * ≔ BitWiseXorNor( [Max-1:0]), so  is set if and only if  [Max-1:0] has an even number of 1 bits
 * ≔ 0
 * ≔ 0
 * is undefined

 Application

 * passing the same register twice:
 * becomes the sign of, which is a simple test for non-negativity
 * is set if  is zero
 * is set if  has an even number of set bits

Performs a comparison operation between  and. The comparison is performed by a (signed) subtraction of  from , the results of which can be called. is then discarded. If  is an immediate value it will be sign extended to the length of. The  register is set in the same manner as a   instruction.

Note that the GAS/AT&T syntax can be rather confusing, as for example  followed by   will branch if   (and not the opposite as might be expected from the order of the operands).

 Operands

minuend subtrahend
 * (only if  is immediate)
 * Register
 * Memory
 * Register
 * Immediate
 * Memory

 Modified flags

 * ≔ MostSignificantBit, so an unset  means the   is non-negative (  ≥   [NB: signed comparison])
 * ≔ ( = 0)
 * ≔ BitWiseXorNor( [Max-1:0])
 * ,  and

Jump Instructions
The jump instructions allow the programmer to (indirectly) set the value of the EIP register. The location passed as the argument is usually a label. The first instruction executed after the jump is the instruction immediately following the label. All of the jump instructions, with the exception of, are conditional jumps, meaning that program flow is diverted only if a condition is true. These instructions are often used after a comparison instruction (see above), but since many other instructions set flags, this order is not required.

See chapter “X86 architecture”, § “EFLAGS register” for more information about the flags and their meaning.

Unconditional Jumps
Loads  with the specified address (i.e. the next instruction executed will be the one specified by  ).

Jump if Equal
ZF = 1

Loads  with the specified address, if operands of previous   instruction are equal. is identical to. For example:

Jump if Not Equal
ZF = 0

Loads  with the specified address, if operands of previous   instruction are not equal. is identical to

Jump if Greater
SF = OF and ZF = 0

Loads  with the specified address, if the   of the previous   instruction is greater than the second (performs signed comparison).

Jump if Greater or Equal
SF = OF or ZF = 1

Loads  with the specified address, if the   of the of previous   instruction is greater than or equal to the   (performs signed comparison).

Jump if Above (unsigned comparison)
CF = 0 and ZF = 0

Loads  with the specified address, if the   of the previous   instruction is greater than the. is the same as, except that it performs an unsigned comparison.

That means, the following piece of code always jumps (unless  is , too), because negative one is represented as all bits set in the two's complement. Interpreting all bits set (without treating any bit as the sign) has the value 2ⁿ-1 (where n is the length of the register). That is the largest unsigned value a register can hold.

Jump if Above or Equal (unsigned comparison)
CF = 0 or ZF = 1

Loads  with the specified address, if the   of previous   instruction is greater than or equal to the. is the same as, except that it performs an unsigned comparison.

Jump if Lesser
The criterion required for a  is that   ≠ . It loads  with the specified address, if the criterion is met. So either  or   can be set, but not both in order to satisfy this criterion. If we take the  (which is basically what a   does) instruction as an example, we have:

With respect to  and   there are several cases that fulfill this criterion:

 * 1)   <   and the operation does not have overflow
 * 2)   >   and the operation has an overflow

In the first case  will be set but not   and in second case   will be set but not   since the overflow will reset the most significant bit to zero and thus preventing   being set. The  ≠   criterion avoids the cases where:

 * 1)   >   and the operation does not have overflow
 * 2)   <   and the operation has an overflow

In the first case neither  nor   are set, in the second case   will be set and   will be set since the overflow will reset the most significant bit to one and in the last case neither   nor   will be set.

Jump if Less or Equal
≠  or.

Loads  with the specified address, if the   of previous   instruction is lesser than or equal to the. See the  section for a more detailed description of the criteria.

Jump if Below (unsigned comparison)
CF = 1

Loads EIP with the specified address, if first operand of previous CMP instruction is lesser than the second. is the same as, except that it performs an unsigned comparison.

Jump if Below or Equal (unsigned comparison)
CF = 1 or ZF = 1

Loads  with the specified address, if   of previous   instruction is lesser than or equal to the. is the same as, except that it performs an unsigned comparison.

Jump if Zero
ZF = 1

Loads  with the specified address, if the zero bit is set from a previous arithmetic expression. is identical to.

Jump if Not Zero
ZF = 0

Loads  with the specified address, if the zero bit is not set from a previous arithmetic expression. is identical to.

Jump if Signed
SF = 1

Loads  with the specified address, if the sign bit is set from a previous arithmetic expression.

Jump if Not Signed
SF = 0

Loads  with the specified address, if the sign bit is not set from a previous arithmetic expression.

Jump if Carry
CF = 1

Loads  with the specified address, if the carry bit is set from a previous arithmetic expression.

Jump if Not Carry
CF = 0

Loads  with the specified address, if the carry bit is not set from a previous arithmetic expression.

Jump if Overflow
OF = 1

Loads  with the specified address, if the overflow bit is set on a previous arithmetic expression.

Jump if Not Overflow
OF = 0

Loads  with the specified address, if the overflow bit is not set on a previous arithmetic expression.

Jump if counter register is zero
CX = 0

ECX = 0

RCX = 0

Loads  with the specified address if the counter register is zero.

Application

 * The existence of this instruction makes the counter register particularly suitable for holding (high-level language) pointers: In most programming languages the “null pointer”, an invalid pointer, is implemented by the numeric value . Usually, you do not want to dereference such a null pointer as the result will be bogus or even cause a GPF. By jumping away, with , to some code handling this error, you can avoid running into such a situation before you attempt to dereference the pointer value. You do not need an extra.
 * If you are using the  instruction to implement a loop, but it is possible the requested number of iteration is zero, you may want to insert a   before the loop’s body. Otherwise,   will decrement zero, thus ending up doing 232 iterations.

Function Calls
Pushes the address of the instruction that follows the  call, i.e. usually the next line in your source code, onto the top of the stack, and then jumps to the specified location. This is used mostly for subroutines.

Pops the next value on the stack into, and then pops the specified number of bytes off the stack. If  is not supplied, the instruction will not pop any values off the stack after returning.

Loop Instructions
The  instruction decrements   and jumps to the address specified by   unless decrementing   caused its value to become zero. For example:

does not set any flags.

These loop instructions decrement  and jump to the address specified by   if their condition is satisfied (that is, a specific flag is set), unless decrementing   caused its value to become zero.

 * loop if equal
 * loop if not equal
 * loop if not zero
 * loop if zero

That way, only testing for a non-zero  can be combined with testing. Other flags can not be tested for, say there is no  “loop while   ≠ 0 and   unset”.

Enter and Leave
creates a stack frame with the specified amount of space allocated on the stack.

destroys the current stack frame, and restores the previous frame. Using Intel syntax this is equivalent to:

This will set  and   to their respective value before the function prologue began therefore reversing any modification to the stack that took place during the prologue.

Other Control Instructions
Halts the processor. Execution will be resumed after processing next hardware interrupt, unless  is cleared.

No operation. This instruction doesn't do anything, but wastes (an) instruction cycle(s) in the processor.

This instruction is often represented as an  operation with the operands   and   (an operation without side-effects), because there is no designated opcode for doing nothing. This just as a passing remark, so that you do not get confused with disassembled code.

Asserts #LOCK prefix on next instruction.

Waits for the FPU to finish its last calculation.

Programmation Assembleur x86/Les branchements

title: X86 Assembly/Control Flow


text:
X86 Assembly/Arithmetic

All arithmetic instructions are executed in (one of) the ALUs. The ALU can only perform integer arithmetics, for floating point instructions see chapter “Floating Point”.

Basic operations
Arithmetic instructions take two operands: a destination and a source. Note that at most one operand may be a memory location.
 * The destination must be a register or a memory location.
 * The source may be either a memory location, a register, or a constant value.

Addition and Subtraction
This adds addend to destination and stores the result in destination.

Like, only it subtracts subtrahend from destination instead. In C:

Unsigned Multiplication
This multiplies multiplicand by the value of corresponding byte-length in the accumulator.

In the second case, the target is not  for backward compatibility with code written for older processors.

Affected flags are: All other flags are undefined.
 * OF  ≔ higher part of product  ≠ 0
 * CF  ≔ higher part of product  ≠ 0

Signed Multiplication
This instruction is almost like, but it treats the sign bit (the MSB), differently.

The  instruction also accepts two other formats:

This multiplies destination by multiplicand and puts the result, the product, in destination.

This multiplies multiplier by multiplicand and places it into product.

Division
This divides the value in the dividend register(s) by divisor, see table below.

As, only signed.

The circle (￮) means concatenation. With divisor size 4, this means that  are the bits 32-63 and   are bits 0-31 of the input number (with lower bit numbers being less significant, in this example).

As you typically have 32 or 64-bit input values for signed division, you often need to use CDQ or CQO to sign-extend  into   or  into   just before the division.

If quotient does not fit into quotient register, arithmetic overflow interrupt occurs. All flags are in undefined state after the operation.

Sign Inversion
Arithmetically negates the argument (i.e. two's complement negation).

Carry Arithmetic Instructions
Add with carry. Adds  +   to , storing result in. Usually follows a normal add instruction to deal with values twice as large as the size of the register. In the following example,  contains a 64-bit number which will be added to.

Subtract with borrow. Subtracts  +   from , storing result in. Usually follows a normal sub instruction to deal with values twice as large as the size of the register.

Increment
This instruction increments the register value augend by. It performs much faster than, but it does not affect the CF.

Operation
Decrements the value in minuend by 1, but this is much faster than the semantically equivalent.

Operands
Minuend may be either a register or memory operand.

Application

 * Some programming language represent Boolean values with either all bits zero, or all bits set to one. When you are programming Boolean functions you need to take account of this. The  instruction can help you with this. Very often you set the final (Boolean) result based on flags. By choosing an instruction that is opposite of the intended and then decrementing the resulting value you will obtain a value satisfying the programming language’s requirements. Here is a trivial example testing for zero.  If you intend to set false the “erroneously” set   will be “fixed” by  . If you intend to set true, which is represented by −1, you will decrement the value zero, the “underflow” of which causing all bits to flip. Note, some architectures execute   slowly, because of the fact that the flags register is overwritten only partially. It therefore is usually more efficient to use   which will affect the CF too, though.
 * Since  and   do not affect the CF, you can use these instructions to update a loop’s counting variable without overwriting some information stored in it. If you need an instruction that does not affect any flags while implicitly also performing a , you could use the rather slow.

Pointer arithmetic
The  instruction can be used for arithmetic, especially on pointers. See chapter “data transfer”, § “load effective address”.

title: X86 Assembly/Arithmetic


text:
User:Kookykman~enwikibooks

Wikis
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title: User:Kookykman~enwikibooks


text:
X86 Assembly/Logic

Logical instructions
The instructions on this page deal with bit-wise logical instructions. For more information about bit-wise logic, see Digital Circuits/Logic Operations.

All logical instructions presented in this section are executed in the, as the name already suggests, the arithmetic logic unit.

binary operations
These instructions require two operands.

operation
performs a bit-wise  of the two operands, and stores the result in destination.

side effects
See below.

application

 * An  can be used to calculate the intersection of two “sets”, or a value representing a “mask”. Some programming language require that Boolean values are stored exactly as either   or  . An   will ensure only the LSB is set, or not set.
 * If partial register addressing is not available in the desired size, an  can be used for a $$\text{destination}\!\!\!\!\mod\text{mask}$$ operation, that is the remainder of integer division. For that, mask has to contain the value $$2^n-1$$ (i. e. all lower bits set until a certain threshold), where $$2^n$$ equals your desired divisor.

operation
The  instruction performs a bit-wise   of the two operands, and stores the result in destination.

side effects
See below.

application

 * An  can be used to calculate the union of two “sets”, or a value representing a “mask”.

operation
Performs a bit-wise  of the two operands, and stores the result in destination.

side effects
See below.

application

 * (or any GPR twice) will clear all bits. It is a specially recognized word. However, since  affects flags it might introduce bogus dependencies.

side effects for,, and

 * OF ≔ 0
 * CF ≔ 0
 * SF becomes the value of the most significant bit of the calculated result
 * ZF ≔ result = 0
 * PF is set according to the result

operation
Performs a bit-wise inversion of argument.

side-effects
None.

application

 * is frequently used to get a register with all bits set.

title: X86 Assembly/Logic


text:
X86 Assembly/Shift and Rotate

Logical Shift Instructions
In a logical shift instruction (also referred to as unsigned shift), the bits that slide off the end disappear (except for the last, which goes into the carry flag), and the spaces are always filled with zeros. Logical shifts are best used with unsigned numbers.

Logical shift  to the right by   bits.

Logical shift  to the left by   bits.

Examples (GAS Syntax):

Arithmetic Shift Instructions
In an arithmetic shift (also referred to as signed shift), like a logical shift, the bits that slide off the end disappear (except for the last, which goes into the carry flag). But in an arithmetic shift, the spaces are filled in such a way to preserve the sign of the number being slid. For this reason, arithmetic shifts are better suited for signed numbers in two's complement format.

Arithmetic shift  to the right by   bits. Spaces are filled with sign bit (to maintain sign of original value), which is the original highest bit.

Arithmetic shift  to the left by   bits. The bottom bits do not affect the sign, so the bottom bits are filled with zeros. This instruction is synonymous with SHL.

Examples (GAS Syntax):

Extended Shift Instructions
The names of the double precision shift operations are somewhat misleading, hence they are listed as extended shift instructions on this page.

They are available for use with 16- and 32-bit data entities (registers/memory locations). The  operand is always a register, the   operand can be a register or memory location, the   operand is an immediate byte value or the CL register. In 64-bit mode it is possible to address 64-bit data as well.

The operation performed by  is to shift the most significant   bits out of , but instead of filling up the least significant bits with zeros, they are filled with the most significant   bits of.

Likewise, the  operation shifts the least significant   bits out of , and fills up the most significant   bits with the least significant bits of the   operand.

Intel's nomenclature is misleading, in that the shift does not operate on double the basic operand size (i.e. specifying 32-bit operands doesn't make it a 64-bit shift): the  operand always remains unchanged.

Also, Intel's manual states that the results are undefined when  is greater than the operand size, but at least for 32- and 64-bit data sizes it has been observed that shift operations are performed by, with n being the data size.

Examples (GAS Syntax):

Other examples (decimal numbers are used instead of binary number to explain the concept)

Rotate Right
In a rotate instruction, the bits that slide off the end of the register are fed back into the spaces.

Rotate to the right by  bits. Here is a graphical representation how this looks like: ╭─────────────────╮ %al old     │ 0 0 1 0'0 1 1 1 │ ror 1, %al ╰─╮╲ ╲ ╲ ╲ ╲ ╲ ╲╰─╯ %al new       1 0 0 1'0 0 1 1 The number of bits to rotate is masked to the lower 5 bits (or 6 bits in 64-bit mode). This is equivalent to a $$\text{offset}\!\!\!\!\mod 32$$ operation, i. e. the remainder of integer division (note: $$2^5 = 32$$). This means, you can never do one or more “complete” rotations.

Operands

 * has to be a register or memory location.
 * can be either
 * an immediate value (where the value  has a dedicated opcode),
 * or the  register (that is the lowest byte of  ).

Modified Flags
only alters flags if the masked is non-zero. The CF becomes the most recently rotated bit, so in the case of  the result ’s MSB (the “sign”).

Furthermore, if the masked  = 1, OF  ≔  result [MSB] ⊻  result [MSB−1], so the OF tells us, whether “the sign” has changed.

Rotate Left
Rotate to the left by  bits.

Operands and modified flags are pretty much the same as for. However, in the case that the masked  = 1, the OF is defined differently, although it has effectively same meaning. For  the OF  ≔  result [MSB] ⊻  result [LSB].

Note that the CF contains the LSB in the case of.

Rotate With Carry Instructions
Like with shifts, the rotate can use the carry bit as the "extra" bit that it shifts through.

Rotate  to the right by   bits with carry.

Rotate  to the left by   bits with carry.

Number of arguments
Unless stated, these instructions can take either one or two arguments. If only one is supplied, it is assumed to be a register or memory location and the number of bits to shift/rotate is one (this may be dependent on the assembler in use, however). is equivalent to   (GAS syntax).

title: X86 Assembly/Shift and Rotate


text:
X86 Assembly/Other Instructions

Stack Instructions
There are dedicated instructions for interacting with the stack.

Generic
This instruction decrements the stack pointer and stores the data specified as the argument into the location pointed to by the stack pointer.

This instruction loads the data stored in the location pointed to by the stack pointer into the argument specified and then increments the stack pointer. For example:

GPRs
This instruction pushes all the general purpose registers onto the stack in the following order: AX, CX, DX, BX, SP, BP, SI, DI. The value of SP pushed is the value before the instruction is executed. It is useful for saving state before an operation that could potentially change these registers.

This instruction pops all the general purpose registers off the stack in the reverse order of PUSHA. That is, DI, SI, BP, SP, BX, DX, CX, AX. Used to restore state after a call to PUSHA.

This instruction works similarly to pusha, but pushes the 32-bit general purpose registers onto the stack instead of their 16-bit counterparts.

This instruction works similarly to popa, but pops the 32-bit general purpose registers off of the stack instead of their 16-bit counterparts.

Flags
Because a good deal of all instructions somehow alter flags, the flags register is considered to be very volatile. As a consequence in microprocessor architecture design, it cannot be queried, nor altered directly (except for a few individual flags, such as the DF). Instead, a dedicated  and   instruction (attempts to) retrieve or store a value to and from the stack. Using them is “slow”, because, as there is only one flags register, all pending (potential) writes or reads must be executed first, before the actual value can be obtained or overwritten. Furthermore, what can be read or overwritten depends on privileges.

This instruction decrements the stack pointer and then loads the location pointed to by the stack pointer with a masked copy of the flags register’s contents. The RF and VM flag are always cleared in the copy. Under certain conditions a GPF may arise.

This instruction attempts, as far as possible, loading the flag register with the contents of the memory location pointed to by the stack pointer and then increments the contents of the stack pointer. Some flags may pertain their original values, even if requested to do so. If there is a lack of privileges to change certain or any values at all, a GPF occurs.

Outside OS development (like threading), a standard usage case of these instructions is to check, whether the  instruction is available. If you can alter the ID flag in the EFLAGS register, the  instruction is supported.

Flags instructions
While the flags register is used to report on results of executed instructions (overflow, carry, etc.), it also contains flags that affect the operation of the processor. These flags are set and cleared with special instructions.

Interrupt Flag
The IF flag tells a processor if it should accept hardware interrupts. It should be kept set under normal execution. In fact, in protected mode, neither of these instructions can be executed by user-level programs.

Sets the interrupt flag. If set, the processor can accept interrupts from peripheral hardware.

Clears the interrupt flag. Hardware interrupts cannot interrupt execution. Programs can still generate interrupts, called software interrupts, and change the flow of execution. Non-maskable interrupts (NMI) cannot be blocked using this instruction.

Direction Flag
The DF flag tells the processor which way to read data when using string instructions. That is, whether to decrement or increment the  and   registers after a   instruction.

Sets the direction flag. Registers will decrement, reading backwards.

Clears the direction flag. Registers will increment, reading forwards.

Carry Flag
The CF flag is often modified after arithmetic instructions, but it can be set or cleared manually as well.

Sets the carry flag.

Clears the carry flag.

Complements (inverts) the carry flag.

Other
Stores the content of AH register into the lower byte of the flag register.

Loads the AH register with the contents of the lower byte of the flag register.

I/O Instructions
The IN instruction almost always has the operands AX and DX (or EAX and EDX) associated with it. DX (src) frequently holds the port address to read, and AX (dest) receives the data from the port. In Protected Mode operating systems, the IN instruction is frequently locked, and normal users can't use it in their programs.

The OUT instruction is very similar to the IN instruction. OUT outputs data from a given register (src) to a given output port (dest). In protected mode, the OUT instruction is frequently locked so normal users can't use it.

No-op Instructions
The x86 instruction set has a NOP (no operation) instruction mnemonic:

It has a single byte opcode,. This instruction has no side effects other than incrementing the instruction pointer (EIP). Despite its name, a "do nothing" instruction is useful for execution speed optimizations. It is routinely used by optimizing compilers/assemblers, and can be seen scattered around in disassembled code, but is almost never used in manually written assembly code.

For illustration, some applications of  instructions are:
 * aligning the following instruction to the start of a memory block;
 * aligning series of jump targets;
 * filling in space when binary patching an executable, e.g. removing a branch, instead of keeping dead code (code that is never executed).

System Instructions
These instructions were added with the Pentium II.

This instruction causes the processor to enter protected system mode (supervisor mode or "kernel mode").

This instruction causes the processor to leave protected system mode, and enter user mode.

Read time stamp counter
RDTSC was introduced in the Pentium processor, the instruction reads the number of clock cycles since reset and returns the value in EDX:EAX. This can be used as a way of obtaining a low overhead, high resolution CPU timing. Although with modern CPU microarchitecture(multi-core, hyperthreading) and  multi-CPU machines you are not guaranteed synchronized cycle counters between cores and CPUs. Also the CPU frequency may be variable due to power saving or dynamic overclocking. So the instruction may be less reliable than when it was first introduced and should be used with care when being used for performance measurements.

It is possible to use just the lower 32-bits of the result but it should be noted that on a 600 MHz processor the register would overflow every 7.16 seconds:

While using the full 64-bits allows for 974.9 years between overflows:

The following program (using NASM syntax) is an example of using RDTSC to measure the number of cycles a small block takes to execute:

In order to assemble, link and run the program we need to do the following:

title: X86 Assembly/Other Instructions


text:
People's Tactics/Scenario Editor/Research

To edit the research for a scenario, select any hex with a unit and click the research button.

Add researchfield [editor only] button
Click this button to add a research field. The following parameters must be entered.

 * “Research Field #” – research fields are numbered; choose a free number unless you want to overwrite an existing research field. The research field numbers are displayed next to the “NR:”.
 * “Research field name” – the name of the research field. This is displayed in the “Current knowledge” and “Possible new buys” areas. A maximum of 33 characters will be displayed, but try to not to exceed 20.
 * “Field 1 needed” – the research field number of the first prerequisite research field. Leave blank for no prerequisite.
 * “Field 2 needed” – the research field number of the second prerequisite research field. Leave blank for no prerequisite.
 * “PP cost” – the cost of the research field in political points
 * “Research field memo” – the text that will be displayed. This is limited to approximately 254 characters, including spaces.

Change name
This button allows the name of a research field to be changed without re-entering all the data. The “Research Field #” and “Research field name” must be entered.

Change need
This button allows the prerequisites of a research field to be changed without re-entering all the data. The “Research Field #”, “Field 1 needed” and “Field 2 needed” must be entered.

Delete button
Clicking this button brings up a window prompting you to enter a number. Enter the number of the of the research field you want to delete. Changes made via deletion are not automatically updated, so exit the research window and re-enter to see changes.

Delete [editor only]
This button removes the research field selected in the “Current knowledge area” from the “Current knowledge area”. Changes made via deletion are not automatically updated, so exit the research window and re-enter to see changes.

Buy this research field
This button gives the research field selected in the “Possible new buys” to the regime who’s hex was selected when the research button was clicked. No political points are subtracted from the regime.


text:
General Chemistry/Table of the Chemical Elements and their Properties

(*) Phase at STP, where S is solid, L is liquid, and G is gas. X is for synthetic (laboratory) elements, and D is for diatomic elements.

(**) Most common oxidation states, not an exhaustive list.

Atomic weights in parentheses are the atomic weights for the most stable isotope. Tabellensammlung Chemie/ Übersicht über die chemischen Elemente


text:
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title: User talk:Jun-Dai


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Learn Electronics/Inductors

=Inductors=

Introduction

 * Electric circuits include resistors, capacitors, inductors, etc. A piece of wire has a very small amount of inductance, but usually we talk about inductors when we think about coils, which are a lot of wire wound in near-circles around a core which is some kind of magnetic material, such as iron. That core magnifies the inductance of the coil.
 * While the wire has some resistance, the coil has not only that resistance, but also reactance. Reactance is proportional to frequency, and coils are used mainly in AC circuits for that reason. Usually the reactance(L) (in Ohms) is much higher than the resistance(R) of the inductor (also in Ohms), with the L/R ratio being important.

Saturation
There is a limit to the strength of the magnetic field of an inductor, and therefore also a limit to the inductance of the inductor. Saturation is reached when a small increase in the electric current creating the magnetic field no longer causes an increase in the magnitude of the magnetic field. This is done intentionally in "Saturable reactors".

Previous chapter ../Capacitors/ | Next chapter: ../Semiconductors/ | Go back to Index

title: Learn Electronics/Inductors


text:
Talk:Embedded Systems/VLSI/Hardware-Description Languages/Verilog

the book Programming:Verilog has been merged here. -- 21:37, 8 December 2005 (UTC)


text:
User talk:Lemony~enwikibooks

Hello and welcome to Wikibooks!

Here are some tips to help you get started:
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 * Explore, be bold in editing pages, and have fun!

You will find more resources in Community Portal. If you want to ask a question, visit the Study help desk, the Staff lounge, or ask me personally on my talk page.

Good luck! -- LV (Dark Mark) 21:47, 8 December 2005 (UTC)

Your account will be renamed
Hello,

The developer team at Wikimedia is making some changes to how accounts work, as part of our on-going efforts to provide new and better tools for our users like cross-wiki notifications. These changes will mean you have the same account name everywhere. This will let us give you new features that will help you edit and discuss better, and allow more flexible user permissions for tools. One of the side-effects of this is that user accounts will now have to be unique across all 900 Wikimedia wikis. See the announcement for more information.

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Yours, Keegan Peterzell Community Liaison, Wikimedia Foundation 23:22, 17 March 2015 (UTC)

Renamed
 This account has been renamed as part of single-user login finalisation. If you own this account you can |log in using your previous username and password for more information. If you do not like this account's new name, you can choose your own using this form after logging in: . -- Keegan (WMF) (talk) 05:11, 19 April 2015 (UTC)

title: User talk:Lemony~enwikibooks


text:
User talk:71.127.193.165

Please stop adding nonsense to Wikibooks. It is considered vandalism. If you would like to experiment, use the sandbox. Thank you. -- LV (Dark Mark) 21:47, 8 December 2005 (UTC)

title: User talk:71.127.193.165


text:
User talk:169.237.90.196

Please stop. If you continue to blank pages, you will be blocked from editing.

title: User talk:169.237.90.196


text:
User talk:Valdezg66

Copyright problem with Image:Fig 1a ckt.jpeg
--Derbeth talk 18:20, 29 November 2005 (UTC)

 * Can you fix information about Image:Reflectionpic1.JPG? --Derbeth talk 22:42, 8 December 2005 (UTC)

title: User talk:Valdezg66


text:
User talk:Doktorcik

Copyright problem with Image:Movingcoil.jpg
--Derbeth talk 22:43, 8 December 2005 (UTC)

title: User talk:Doktorcik


text:
Handbook of Genetic Counseling/Osteogenesis Imperfecta (OI)

Osteogenesis Imperfecta (OI)

Contracting

 * What questions or concerns would you like us to address today?
 * What has your experience been like with OI?
 * Explanation of what will occur during the session
 * Confirm family history
 * We have some medical records, but will want to confirm some of his med history
 * Dr. will come in to examine him
 * And we will discuss what we think regarding whether we think he has OI and why we have come to the conclusions we have
 * We will then answer any questions you might have

Overview of OI

 * OI is a genetic disorder. Eight types of OI can be distinguished. Most cases are caused by dominant mutations in the COL1A1 and COL1A2 genes. Some are caused by recessive mutations.
 * It is due to a lack of or poor quality of type 1 collagen (Collagen is the major protein of the body's connective tissue)
 * Extreme variations in severity from one individual to another
 * Clinical diagnosis is often grouped into four types based on severity and characteristics

Inheritance

 * As a genetic disorder, OI has historically been viewed as an autosomal dominant disorder of type I collagen. Most cases have been caused by mutations in the COL1A1 and COL1A2 genes. In the past several years, there has been the identification of autosomal recessive forms.
 * Most cases of OI are caused by new mutation (especially type II)
 * If spontaneous (parents unaffected) then empiric recurrence is 6-7% (Marini JC and Chernoff EJ)
 * Empiric recurrence increases to 28% if more than one affected child has been born to unaffected parent
 * Recurrence is caused by gonadal mosaicism (or even somatic mosaicism in a parent where parent is only mildly affected)
 * 18 cases of mosaicism in literature (12 paternal and 6 maternal)
 * approximately 1/3 of these parents were mildly affected
 * determining proportion of mutation in sperm can be most accurate way to obtain recurrence risk for mosaic fathers
 * Affected individual has 50% chance of passing mutation on to each child (if dominant form)

Genetics
Geneotype Phenotype correlation (Not well understood)
 * Caused by an alteration in COL1A1 gene on chromosome 17 or COL1A2 gene on chromosome 7
 * Over 200 mutations recognized (most unique to an individual family)
 * Even in families there is considerable phenotypic heterogeneity
 * Unrelated individuals with identical mutations may have similar or distinct phenotype
 * Individuals with near identical phenotypes often have different mutations
 * Lethal and nonlethal mutations are both represented about equally on alpha1 and alpha2 chains
 * Type I caused by inactivation of one copy of gene resulting in underproduction of collagen
 * More severe forms of OI generally result from structural mutations in gene that cause collagen fibers to become unstable
 * Type I collagen is a primary component of bone
 * Fibroblasts of patients show decrease in secretion of type I collagen into matrix
 * Since the proportions of the components are important for mineralization of bone lack of enough type I results in poor matrix deposition
 * Tissue specific difference in metabolism of mutant type I collagen may explain why mostly bone is affected

Incidence
(Marini JC and Chernoff EJ)
 * Between 1 in 20,000 and 1 in 30,000
 * Incidence in US is 1 in 20,000 if all diagnosed within 1 year of birth included
 * No preferential distribution by gender, race or ethnic group.
 * Brittle bone disease is un-cureable for the time being.

Clinical Features
(Vary widely within types and between types) (There are 4 types according to current classification, but an individual may not fit one category clearly)
 * Type I
 * Mildest type of OI
 * Bones predisposed to fracture, especially before puberty (postnatal onset of fractures usually without bony deformity)
 * Normal or near normal stature
 * Loose joints (hyperextensible)
 * Blue sclera
 * Triangular face
 * Spinal curvature
 * Teeth possibly brittle (dentinogenesis imperfecta)
 * Hearing loss in 20s or 30s
 * Type II
 * Most severe form
 * Usually fetal demise or death in the perinatal period
 * Numerous fractures and severe bone deformity
 * Length and weight SGA
 * Head large for body size
 * Usually blue-gray sclera
 * Markedly reduced ossification
 * Underdeveloped lungs
 * Type III (progressive deforming form)
 * Bones fracture easily - fractures present at birth
 * Bone deformity sometimes severe
 * Short stature
 * Blue sclera (thought to be due to differential scattering of light because of differences in the connective tissue) tends to whiten with age
 * Loose joints and poor muscle development
 * Barrel-shaped rib cage
 * Triangular face
 * Relative macrocephaly
 * intellectually normal
 * most are severely physically handicapped
 * Spinal curvature
 * Respiratory problems sometimes
 * Teeth brittle possibly
 * Hearing loss possible
 * Type IV
 * Between Type I and Type III in severity
 * Bones fracture easily, most before puberty
 * Mild to moderate bone deformity
 * Moderate osteoporosis and modeling abnormalities of the long bones
 * Shorter than average stature (moderately short)
 * Normal sclera (but some cases reported of blue sclerae that seem to fit this type better than type I)
 * Tendency toward spinal curvature
 * Barrel-shaped rib cage
 * Triangular face
 * Brittle teeth possible
 * Hearing loss possible

Management

 * Hearing loss
 * characteristic in type I OI and also occurs in types III and IV
 * Combined sensorineural and conductive deficits
 * Hearing aids help with conductive hearing loss more than sensorineural
 * Referral to center with experience in OI when hearing aid no longer enough
 * Surgical intervention with stapedectomy gives satisfactory long-term results in OI with severe loss (not routine) because won't relieve sensorineural component
 * Dental
 * May need orthodontic work for maloculsion
 * Other dental considerations for dentinogenesis imperfecta
 * Cardiovascular
 * Aortic root dilatation (12% of all affected individuals 28% in type III)
 * No standard regimen for evaluation
 * Aortic and mitral regurgitation occasionally noted
 * Respiratory
 * Pulmonary function evaluated by cardiology or pulmonology initially at young age (4-6 years) then reassessed every 2-3 if normal

Natural History

 * Type II
 * Frequently lethal at or shortly after birth due to respiratory problems
 * Those that survive perinatal period generally die from pneumonia or respiratory insufficiency
 * Some have lived for months or years, but bones are very porotic and no evidence of haversian canals or lamellar bone
 * Type I
 * rarely diagnosed at birth because it is mildest form
 * Type III
 * often causes fractures at birth, and fractures may occur in utero
 * Compatible with long life, but many die in infancy of respiratory difficulties or in childhood of pneumonia
 * Early intervention and rehab have improved prognosis

Development and behavior

 * Minimal delay in fine motor development
 * Significant delay in gross motor
 * Intelligence and language unaffected

Diagnosis/Testing

 * Can be diagnosed based on fractures, clinical features, and family history
 * Collagen testing
 * Study cells making type I collagen
 * Biopsy 1/8 to 1/16 of an inch of skin
 * Radiolabel and run on gel
 * In people with OI, also bands that migrate more slowly - abnormal collagen molecules
 * Does not identify 10-15% of individuals with mild OI
 * May not be possible to distinguish between types of OI
 * Usually used before molecular testing
 * Molecular testing
 * DNA sequencing
 * Most families have unique mutation
 * Does not identify mutation in about 5% of those with OI
 * Prenatal diagnosis
 * Ultrasound can often detect fractures, bowing, or other bone deformities in severe cases of OI (milder forms may be missed)
 * Type II OI identifiable as early as 15 weeks gestation
 * Type III OI not reliable until after 20 weeks (limb shortness may not be apparent until then)
 * Findings on U/S may include
 * CVS
 * Cells analyzed for abnormal collagen
 * DNA test for mutation if it has been identified in family
 * Amniocentesis
 * can identify genetic mutation (useful only if mutation has already been identified)

Management and Treatment Options

 * Currently is no cure
 * Management of fractures
 * Usually treated with short-term immobilization in lightweight casts, splints, or braces to allow movement as soon as possible
 * Physical therapy
 * Should begin as soon as muscle weakness identified
 * Goal is to give independence in life functions
 * Swimming, water therapy, and walking safe exercises to maintain bone and muscle mass
 * Rodding surgery
 * Metal rods inserted in long bones to control fractures and improve deformities
 * Two types of rods
 * Nonexpandable versatile but must be replaced when child grows
 * Expandable rods grow with child but only appropriate for longer bones
 * Very thick
 * Must be firmly anchored at both ends
 * Spinal rodding for severe scoliosis
 * If bones strong enough to support rods
 * Bisphosphonate drugs
 * Currently used to treat osteoporosis and bone complications in cancer
 * Study at Montreal Shriners Hospital
 * Administered pamindronate intravenously
 * Treatment cycle is 4 hour infusion for 3 successive days
 * Received cycle every 4 - 6 months
 * Prevents breakdown of bones by osteoclasts
 * Normally osteoblasts create new bone to replace older bone that is resorbed by osteoclasts
 * In OI bone is resorbed by osteoclasts more quickly because it is imperfect and osteoblasts become less efficient (produce less bone) because collagen is abnormal
 * Slowing down resorption of bone may strengthen skeleton
 * Study included 30 children with severe OI
 * Results showed increased bone density, reduction in bone pain, increased motility and decreased incidence of fractures
 * Only side effect was mild fever in 87% of children on second day of first treatment - did not occur again
 * Small study, no controls, and did not include patients with mild OI
 * Growth hormone (still under investigation)
 * Administration to those with type III and IV significantly increases linear growth rate in about half of individuals (type IV compose majority of responders)
 * Individuals with type I also usually are responsive to GH.
 * GH also increases muscle mass and strength.
 * GH does not worsen skeletal deformities, but there is increase in blood levels of all components of bone turnover due to an increased rate of whole body remodeling associated with rapid bone gain

Health tips for individuals with OI

 * Safe exercise
 * Nutritious diet
 * Calcium maintains bone density
 * Vitamin C promotes healing
 * Avoid smoking, excessive alcohol or caffeine, and steroid medications

Precautions to take when caring for someone with OI

 * Never pull or push on limb or bend it in awkward position
 * Don't lift baby under armpits or by ankles - put one hand under buttocks and other under shoulders and head
 * Covered foam or a pillow may be used to transport baby but be sure to hold and touch babies
 * Support infants in a variety of positions to develop muscles
 * Use caution when performing medical procedures
 * Minimize handling of limb when fracture suspected
 * Respect opinions or instructions of family members

Differentials
An important differential diagnosis of OI is child abuse, as both may present with multiple fractures in various stages of healing. Differentiating them can be difficult, especially when no other characteristic features of OI are present. Other differential diagnoses include rickets, osteomalacia, and other rare skeletal syndromes.

Psychosocial issues

 * Family attitudes depend on previous experience with OI
 * Surprise, shock, anger, guilt, depression, and mourning common in parents with new diagnosis
 * Families with a previous child may have already developed coping strategies and acceptance
 * May be overprotective and overindulgent with affected children
 * Frustration with medical personnel who don't handle child carefully
 * Anxiety, frustration if unexplained fractures and child abuse suspected
 * Affected individuals
 * Frustration with inaccessibility of school, work, social environments
 * Concerns about physical appearance, sexual development, and peer acceptance
 * Feelings of isolation, discrimination, frustration

Resources

 * Osteogenesis Imperfecta Foundation
 * 804 West Diamond Avenue, Suite 210
 * Gaithersburg, MD 20878
 * (800) 947-0456
 * Email: bonelink@oif.org
 * Internet: www.oif.org

Facts for me

 * Approximately 19 collagen types
 * Type I is most abundant and major constituent of most connective tissues, bone, tendon, skin, dentin, ligament, fascia, and many blood vessels
 * Composed of 3 alpha chains to form triple helix


text:
Talk:Polish/Plural

Untitled
What is mentioned about countability seems a bit strange. Are you sure that practically all Polish words can be said in a plural form? "Pogoda", "wiek" (age), "wiedza", "owłosienie", "karmel" etc.  I'm afraid, the rule here is more or less like in English, namely : you never know whether you can say something in plural or not ;-) And the example with "beers" is ridiculous as , obviously, exactly the same refers to English uncountables, of course one can say "two beers" in English. Two teas, three soaps or whatever if there exist implied counters. And similarly, many uncountable products can only be said in plural if you mean "types of...", e.g. "mąki", "cukry", "tłuszcze", etc. And again, same happens in English. So, generally, I think the paragraph on countability brings more unnecessary confusion rather than explanation

"Wiedza" doesn't have plural form, "pogoda", "owłosienie", "karmel" have plural, "wiek" too, but plural form only meaning "centuries".

You can say uncountable products in singular and plural form, so "mąka"-"mąki", "cukier"-"cukry"(only in meaning "carbohydrates"!), "tłuszcz"-"tłuszcze", "woda"-"wody", "ser"-"sery"(I never have understood, why cheese is uncontable in English ;p I'm polish) are correct.

title: Talk:Polish/Plural


text:
Handbook of Genetic Counseling/Osteosarcoma and Li-Fraumeni Syndrome

Osteosarcoma and Li-Fraumeni Syndrome

Contracting

 * What concerns do you have for yourself or for your family?
 * What questions do you have?
 * Overview of agenda
 * Elicit medical history
 * Review family history
 * Discuss genetics, testing, treatment and management

Osteosarcoma Background

 * Most common type of bone cancer
 * Arises in osteoid tissue in bones
 * Most common in knees, upper legs, and upper arms
 * Commonly affects people from ages 10-25
 * Accounts for about 5% of childhood tumors
 * 50% form in bones around knee
 * Only about 30% of patients with localized tumors survive free of relapse
 * Symptoms of bone cancer
 * Pain is most common symptom
 * Other symptoms depend on location and size of tumor
 * Tumors in or near joints may cause swelling or tenderness
 * Can interfere with normal ability to move
 * May weaken bones and make fractures more likely
 * General symptoms include fatigue, fever, weight loss, and anemia
 * Diagnosis
 * Alkaline phosphatase assay
 * Blood test to determine enzyme levels
 * Large amounts of alkaline phosphatase found in blood when cells of bone tissue are active
 * During childhood growth
 * During mending of broken bone
 * When tumor causes production of abnormal bone tissue
 * X-rays show location, size, and shape of tumor
 * Bone scan, CT, MRI, or angiogram may be recommended if X-ray suggests that a tumor is cancerous
 * Biopsy needed to determine for sure if tumor is cancer
 * Needle biopsy - make small hole in bone and remove tissue sample from tumor with needle-like instrument
 * Incisional biopsy - cut into tumor and remove sample of tissue
 * No staging system for osteosarcoma so use general terms
 * Localized
 * Metastatic - most often to lungs or other bones (20% of patients)
 * Recurrence - most often in the lungs (5 year survival is 20-40% following surgery)
 * Treatment
 * Depends on type, size, location, and stage of cancer
 * Surgery
 * Amputation of limb necessary in some cases
 * Pre or post-operative chemotherapy has improved success of limb-sparing surgery
 * May remove only cancerous section of bone and replace it with prosthesis
 * Chemotherapy and radiation may be used alone or together
 * Tumors are generally resistant to radiation
 * Degree of necrosis following chemotherapy predicts prognosis
 * Various clinical trials for surgeries, radiation therapies, and chemotherapies
 * Risk factors for bone cancers
 * Radiation or chemotherapy treatment in children or young adults for other conditions
 * Adults with Paget's disease are at increased risk for osteosarcoma
 * Hereditary factors

Li Fraumeni Syndrome Overview

 * Cancer predisposition syndrome
 * Associated with soft-tissue sarcomas, breast cancer, leukemia, osteosarcoma, melanoma, and cancer of the colon, pancreas, adrenal cortex, and brain
 * Increases risk for development of cancers
 * Diagnosis is made clinically and genetic testing is available

Genetic Etiology

 * Due to mutation in TP53 gene on 17p13 that codes for TP53 protein in more than 50% of cases
 * Tumor suppressor gene nicknamed "guardian of the genome"
 * Acts as checkpoint control following DNA damage by delaying cell cycle progression until damaged DNA is repaired or cell commits to apoptosis
 * Activates downstream genes to repair DNA
 * Signals molecule to confirm damage and proceed with apoptosis
 * Arrests cell cycle by mediating RB pathway
 * CHEK2 gene at 22q12.1 also associated with Li-Fraumeni syndrome
 * Reported in only a few families thus far
 * Putative tumor suppressor gene
 * Lies in TP53 pathway
 * One of checkpoint genes activated in response to DNA damage by phorsphorylating p53
 * Not known if cancer risks are different than those due to TP53 mutations
 * Mutations in this gene appear to be most common in osteosarcomas
 * Autosomal dominant inheritance
 * Offspring of affected individuals have 50% chance of inheriting mutation
 * Most individuals diagnosed have an affected parent
 * De novo mutation rate unknown
 * Fewer than 400 families reported worldwide
 * Association of malignancies with TP53 mutations
 * Less than 1% of all breast cancers
 * 2-10% of childhood brain tumors
 * 50-100% of childhood adrenocortical carcinomas
 * 2-3% of osteosarcomas
 * 9% of rhabdomyosarcomas
 * 7-20% of multiple primaries occurring at young ages
 * Penetrance
 * May be as high as 90%
 * About 25% of cancers occur before age 18
 * About 50% of individuals have malignancy by age 40
 * About 90% of individuals have malignancy by age 70
 * Different studies give different numbers - may be genetic heterogeneity

Clinical Features

 * Predisposes to a number of different types of tumors
 * Osteosarcomas (23/151)
 * Soft-tissue sarcomas (32/151)
 * Pre-menopausal breast cancers (36/151)
 * Brain tumors - neuroblastoma commonly (14/151)
 * Adrenal cortical tumors (4/151)
 * Leukemia - particularly acute leukemia (9/151)
 * Also associated with excess rates of other cancers
 * Melanoma
 * Stomach cancer
 * Colon cancer
 * Pancreatic cancer
 * Esophageal cancer
 * Gonadal germ cell tumors diagnosed at young ages
 * Wilm's tumor
 * Adult women have higher cancer risk than men because of high frequency of breast cancer
 * Also increases risk to develop multiple primary cancers
 * Up to 50% may develop second cancer
 * 4% develop third cancer
 * 2% develop four cancers
 * Survivors of childhood cancer have greatest risk to develop another primary
 * Radiation exposure appears to increase risk of second cancer
 * Genotype-phenotype correlation
 * R337H mutations associate with development of childhood adrenocortical carcinoma as low penetrance allele
 * 13964gc mutation in intron 6 in series of patients with breast cancer as low penetrance allele

Diagnosis

 * Clinical diagnostic criteria (LFS)
 * Proband with sarcoma diagnosed under 45 years of age
 * First-degree relative with any cancer under 45 years of age
 * Third family member who is first- or second-degree relative with cancer under 45 or sarcoma at any age
 * Li-Fraumeni-like syndrome (LFL)
 * Share some, but not all features of LFS
 * Birch's definition
 * Proband with any childhood cancer or sarcoma, brain tumor, or adrenal cortical tumor diagnosed under 45 years of age
 * First- or second-degree relative with a typical LFS cancer at any age
 * Additional first- or second-degree relative with any cancer under the age of 60
 * Eele's definition
 * Two first- or second-degree relatives with LFS-related malignancies
 * Can occur at any age
 * Molecular genetic testing
 * Identifies mutations in TP53 gene in about 70% of patients with LFS and 8-22% of families with LFL
 * DNA sequencing
 * Available clinically
 * Identifies mutations in about 75% of families
 * About 80% of identifiable mutations are in exons 5-8 so testing is often limited to only these exons
 * Full gene sequencing and protein function for novel missense mutations generally only offered on research basis
 * Chip-based DNA sequencing
 * Available on research basis only
 * Detects most of common single base pair mutations that have been identified
 * Sensitivity of 90-98% depending on how much of coding region is sequenced
 * Can test asymptomatic individuals once mutation is identified in the family
 * Cannot predict age of onset, severity, type of cancer, or rate of preogression
 * Lack of proven surveillance or prevention so not justified for management but may be useful for reproductive, financial, and career planning or peace of mind
 * Testing has been confined to individuals 18 and older since no proven management options
 * Prenatal testing is possible if mutation identified in family but requires careful genetic counseling
 * Potential risks of testing
 * May not be covered by insurance
 * Possible problems with health, life, and disability insurance coverage
 * Possible employment and educational discrimination
 * Changes in social and family interaction
 * Implications for other at-risk family members
 * Limitations in management options
 * Potential benefits of testing
 * Explanation for frequent/rare occurrence of cancer in family
 * Clarification of risk/relief if individual tests negative for known mutation
 * Help make decisions regarding medical management or life decisions
 * Clinical molecular testing
 * City of Hope
 * Sequencing of coding exons 2-11 and intron junctions
 * Sensitivity estimated to be greater than 95% for point mutations
 * Requires 6 cc of whole blood in yellow or lavender topped tube
 * Full mutation analysis - $450, known mutation analysis $250
 * Turn-around time is 4 weeks
 * University of Pennsylvania
 * Conformation sensitive gel electrophoresis (CSGE)
 * Shows differences in 2 alleles as small as single base substitution, insertion, deletion
 * Sensitivity estimated to be greater than 95% in coding sequence
 * Turn-around time is 4 weeks
 * Fairview Molecular Diagnostic Laboratory
 * Sequencing analysis
 * Requires 15 ml blood in yellow topped tube
 * Turn-around time is 4-8 weeks

Management

 * No surveillance except breast cancer screening has been show to reduce morbidity and mortality
 * At-risk individuals should pay attention to signs and symptoms
 * Lingering aches and illnesses
 * Headaches, bone pain, abdominal discomfort
 * Surveillance for at-risk children
 * Complete physical exam
 * Urinalysis
 * Complete blood count
 * Abdominal ultrasound examination
 * Additional organ-targeted surveillance based on family history
 * Surveillance for at-risk adults
 * Annual complete physical exam including skin, nervous system, rectum, and Pap smear for women
 * Consider scans of head and abdomen annually
 * Semi-annual clinical breast exam for women
 * Annual mammograms, breast ultrasonography, or MRI
 * Mammograms controversial because of increased sensitivity to radiation
 * Should begin screening by age 25-30
 * Additional organ-targeted surveillance based on family history

Differential Diagnosis

 * Hereditary breast/ovarian cancer syndrome
 * Retinoblastoma - Autosomal dominant
 * Due to mutations in RB1 gene at 13q14
 * RB1 protein is negative regulator of cell growth
 * Approximately 90% of retinoblastomas occur before age 3
 * Increases risk to develop osteosarcoma 500-fold
 * Rothmund-Thomson syndrome - Autosomal recessive
 * Due to mutations in RECQL4 gene at 8q24.3 in some families
 * Cancer risks increased but not quantified
 * Clinical features include:
 * Skin atrophy marbleized pigmentation
 * Telangiectasia
 * Cataracts
 * Osteosarcoma is most commonly reported malignancy
 * Werner syndrome - Autosomal recessive
 * Due to mutations in WRN (RECQL2) gene at 8p12
 * Cancer risk is 10% lifetime
 * Clinical features include:
 * Multiple complaints of problems associated with aging beginning in 20's and 30's
 * Cataracts, graying hair or balding, decreased muscle mass, arteriosclerosis, scleroderma, endocrine failure, and NIDDM
 * Also may have lack of growth spurt in puberty or dysmorphic features
 * Increased risk for osteosarcoma, soft-tissue sarcoma, melanoma, thyroid cancer, and hematological malignancies