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Microprocessor Design/Cache

Cache
A cache is a small amount of memory which operates more quickly than main memory. Data is moved from the main memory to the cache, so that it can be accessed faster. Modern chip designers put several caches on the same die as the processor; designers often allocate more die area to caches than the CPU itself. Increasing chip performance is typically achieved by increasing the speed and efficiency of chip cache.

The cache memory performance is the most significant factor in achieving high processor performance.

Cache works by storing a small subset of the external memory contents, typically out of it's original order. Data and instructions that are being used frequently, such as a data array or a small instruction loop, are stored in the cache and can be read quickly without having to access the main memory. Cache runs at the same speed as the rest of the processor, which is typically much faster than the external RAM operates at. This means that if data is in the cache, accessing it is faster than accessing memory.

Cache helps to speed up processors because it works on the principle of locality.

In this chapter, we will discuss several possible cache arrangements, in increasing order of complexity:
 * No cache, single-CPU, physical addressing
 * Single cache, single-CPU, physical addressing
 * Cache hierarchy: L1, L2, L3, etc.
 * cache replacement policies: associativity, random replacement, LRU, etc.
 * Split cache: I-cache and D-cache, on top of a unified cache hierarchy
 * caching with multiple CPUs
 * cache hardware that supports virtual memory addressing
 * the TLB as a kind of cache
 * how single-address-space virtual memory addressing interacts with cache hardware
 * how per-process virtual memory addressing interacts with cache hardware

No cache
Most processors today, such as the processors inside standard keyboards and mice, don't have any cache. Many historically important computers, such as Cray supercomputers, don't have any cache. The vast majority of software neither knows nor cares about the specific details of the cache, or if there is even a cache at all.

Processors without a cache are usually limited in performance by the main memory access time. Without a cache, the processor fetches each instruction, one at a time, from main memory, and every LOAD or STORE goes to main memory before executing the next instruction.

One way to improve performance is to substitute faster main memory. Alas, that usually has a financial limit: hardly anyone is willing to pay a penny a bit for a gigabyte of really fast main memory.

Even if money is no object, eventually one reaches physical limits to main memory access time. Even with the fastest possible memory money can buy, the memory access time for a unified 1 gigabyte main memory is limited by the time it takes a signal to get from the CPU to the most distant part of the memory and back.

Single cache
Using exactly the same technology, it takes less time for a signal to traverse a small block of memory than a large block of memory.

The performance of a processor with a cache is no longer limited by the main memory access time. The performance of a processor with a cache is usually limited in performance by the (much faster) cache memory access time: if the cache access time of a processor could be decreased, the processor would have higher performance. However, cache memory is generally much easier to speed up than main memory: really fast memory is much more affordable when we only buy small amounts of it. If it will improve the performance of a system significantly, lots of people are willing to pay a penny a bit for a kilobyte of really fast cache memory.

Principle of Locality
There are two types of locality, spatial and temporal. Modern computer programs are typically loop-based, and therefore we have two rules about locality:

 * Spatial Locality:When a data item is accessed, it is likely that data items in sequential memory locations will also be accessed. Consider the traversal of an array, or the act of storing local variables on a stack. In these cases, when one data item is accessed, it is a good idea to load the surrounding memory area into the cache at the same time.
 * Temporal Locality:When data item is accessed, it is likely that the same data item will be accessed again. For instance, variables are typically read and written to in rapid succession. It is a good idea to keep recently used items in the cache, and not over-write data that has been recently used.

Hit or Miss
A hit when talking about cache is when the processor finds data in the cache that it is looking for. A miss is when the processor looks for data in the cache, but the data is not available. In the event of a miss, the cache controller unit must gather the data from the main memory, which can cost more time for the processor.

Measurements of "the hit ratio" are typically performed on benchmark applications. The actual hit ratio varies widely from one application to another. In particular, video and audio streaming applications often have a hit ratio close to zero, because each bit of data in the stream is read once for the first time (a compulsory miss), used, and then never read or written again. Even worse, many cache algorithms (in particular, LRU) allow this streaming data fill the cache, pushing out of the cache information that will be used again soon (cache pollution).

Cache performance
A processor with a cache first looks in the cache for data (or instructions). On a miss, the processor then fetches the data (or instructions) from main memory. On a miss, this process takes *longer* than an equivalent processor without a cache.

There are three ways a cache gives better net performance than a processor without a cache:

 * A hit (read from the cache) is faster than the time it takes a processor without a cache to fetch from main memory. The trick is to design the cache so we get hits often enough that their increase in performance more than makes up for the loss in performance on the occasional miss. (This requires a cache that is faster than main memory).
 * Multiprocessor computers with a shared main memory often have a bottleneck accessing main memory. When a local cache succeeds in satisfying memory operations without going all the way to main memory, main memory bandwidth is freed up for the other processors, and the local processor doesn't need to wait for the other processors to finish their memory operations.
 * Many systems are designed so the processor often read multiple items from cache simultaneously -- either 3 separate caches for instruction, data, and TLB; or a multiported cache; or both -- which takes less time than reading the same items from main memory one at a time.

The last two ways improve overall performance even if the cache is no faster than main memory.

A processor without a cache has a constant memory reference time T of
 * $$T = T_m + E$$

A processor with a cache has an average memory access time of
 * $$T = mT_m + T_h + E$$

where
 * m is the miss ratio
 * Tm is the time to make a main memory reference
 * Th is the time to make a cache reference on a hit
 * E accounts for various secondary factors (memory refresh time, multiprocessor contention, etc.)

Flushing the Cache
When the processor needs data, it looks in the cache. If the data is not in the cache, it will then go to memory to find the data. Data from memory is moved to the cache and then used by the processor. Sometimes the entire cache contains useless or old data, and it needs to be flushed. Flushing occurs when the cache controller determines that the cache contains more potential misses than hits. Flushing the cache takes several processor cycles, so much research has gone into developing algorithms to keep the cache up to date.

Cache Hierarchy
Cache is typically divided between multiple levels. The most common levels are L1, L2, and L3. L1 is the smallest but the fastest. L3 is the largest but the slowest. Many chips do not have L3 cache. Some chips that do have an L3 cache actually have an external L3 module that exists on the motherboard between the microprocessor and the RAM.

Inclusive, exclusive, and other cache hierarchy
When there are several levels of cache, and a copy of the data in some location in main memory has been cached in the L1 cache, is there another copy of that data in the L2 cache?

 * No. Some systems are designed to have strictly exclusive cache levels: any particular location in main memory is cached in at most one cache level.

All the data in a L1 cache can also be found in L2 and L3 (and also in main memory).
 * Yes. Other systems are designed to have a strictly inclusive cache levels: whenever some location in main memory is cached in any one level, the same location is also cached in all higher levels. All the data in the L2 cache can also be found in L3 (and also in main memory).

 * Maybe. In some systems, such as the Intel Pentium 4, some data in the L1 cache is also in the L2 cache, while other data in the L1 cache is not in the L2 cache. This kind of cache policy does not yet have a popular name.

Size of Cache

There are a number of factors that affect the size of cache on a chip:

 * 1) Moore's law provides an increasing number of transistors per chip. After around 1989, more transistors are available per chip than a designer can use to make a CPU. These extra transistors are easily converted to large caches.
 * 2) Processor components become smaller as transistors become smaller. This means there is more area on the die for additional cache.
 * 3) More cache means fewer delays in accessing data, and therefore better performance.

Because of these factors, chip caches tend to get larger and larger with each generation of chip.

Cache Tagging
Cache can contain non-sequential data items in no particular order. A block of memory in the cache might be empty and contain no data at all. In order for hardware to check the validity of entries in the cache, every cache entry needs to maintain the following pieces of information:
 * 1) A status bit to determine if the block is empty or full
 * 2) The memory address of the data in the block
 * 3) The data from the specified memory address (a "block in the cache", also called a "line in the cache" )

When the processor looks for data in the cache, it sends a memory address to the cache controller. the cache controller checks the address against all the address fields in the cache. If there is a hit, the cache controller returns the data. If there is a miss, the cache controller must pass the request to the next level of cache or to the main memory unit.

The cache controller splits an effective memory address (MSB to LSB) into the tag, the index, and the block offset. Some authors refer to the block offset as simply the "offset" or the "displacement".

The memory address of the data in the cache is known as the tag.

Memory Stall Cycles
If the cache misses, the processor will need to stall the current instruction until the cache can fetch the correct data from a higher level. The amount of time lost by the stall is dependent on a number of factors. The number of memory accesses in a particular program is denoted as Am; some of those accesses will hit the cache, and the rest will miss the cache. The rate of misses, equal to the probability that any particular access will miss, is denoted rm. The average amount of time lost for each miss is known as the miss penalty, and is denoted as Pm. We can calculate the amount of time wasted because of cache miss stalls as:

 * $$\mbox{stall time} = A_m \times r_m \times P_m$$

Likewise, if we have the total number of instructions in a program, N, and the average number of misses per instruction, MPI, we can calculate the lost time as:

 * $$\mbox{stall time} = N \times MPI \times P_m$$

If instead of lost time we measure the miss penalty in the amount of lost cycles, the calculation will instead produce the number of cycles lost to memory stalls, instead of the amount of time lost to memory stalls.

Read Stall Times
To calculate the amount of time lost to cache read misses, we can perform the same basic calculations as above:

 * $$\mbox{read-stall time} = A_r \times r_r \times P_r$$

Ar is the average number of read accesses, rr is the miss rate on reads, and Pr is the time or cycle penalty associated with a read miss.

Write Stall Times
Determining the amount of time lost to write stalls is similar, but an additional additive term that represents stalls in the write buffer needs to be included:

 * $$\mbox{write-stall time} = A_w \times r_w \times P_w + T_{wb}$$

Where Twb is the amount of time lost because of stalls in the write buffer. The write buffer can stall when the cache attempts to synchronize with main memory.

Hierarchy Stall Times
In a hierarchical cache system, miss time penalties can be compounded when data is missed in multiple levels of cache. If data is missed in the L1 cache, it will be looked for in the L2 cache. However, if it also misses in the L2 cache, there will be a double-penalty. The L2 needs to load the data from the main memory (or the L3 cache, if the system has one), and then the data needs to be loaded into the L1. Notice that missing in two cache levels and then having to access main memory takes longer than if we had just accessed memory directly.

Design Considerations
L1 cache is typically designed with the intent of minimizing the time it takes to make a hit. If hit times are sufficiently fast, a sizable miss rate can be accepted. Misses in the L1 will be redirected to the L2 and that is still significantly faster than accesses to main memory. L1 cache tends to have smaller block sizes, but benefits from having more available blocks for the same amount of space. In order to make L1 hit times minimal, L1 are typically direct-mapped or even narrowly 2-way set associative.

L2 cache, on the other hand, needs to have a lower miss rate to help avoid accesses to main memory. Accesses to L2 cache are much faster than accesses to memory, so we should do everything possible to ensure that we maximize our hit rate. For this reason, L2 cache tends to be fully associative with large block sizes. This is because memory is typically read and written in sequential memory cells, so large block sizes can take advantage of that sequentiality.

L3 cache further continues this trend, with larger block sizes, and minimized miss rate.

block size
A very small cache block size increases the miss ratio, since a miss will fetch less data at a time. A very large cache block size also increases the miss ratio, since it causes the system to fetch a bunch of extra information that is used less than the data it displaces in the cache.

Associativity
In order to increase the read speed in a cache, many cache designers implement some level of associativity. An associative cache creates a relationship between the original memory location and the location in the cache where that data is stored. The relationship between the address in main memory and the location where the data is stored is known as the mapping of the cache. In this way, if the data exists in the cache at all, the cache controller knows that it can only be in certain locations that satisfy the mapping.

Direct-Mapped
A direct-mapped system uses a hashing algorithm to assign an identifier to a memory address. A common hashing algorithm for this purpose is the modulo operation. The modulo operation divides the address by a certain number, p, and takes the remainder r as the result. If a is the main memory address, and n is an arbitrary non-negative integer, then the hashing algorithm must satisfy the following equation:

 * $$a = p \times n + r$$

If p is chosen properly by the designer, data will be evenly distributed throughout the cache.

In a direct-mapped system, each memory address corresponds to only a single cache location, but a single cache location can correspond to many memory locations. The image above shows a simple cache diagram with 8 blocks. All memory addresses therefore are calculated as n mod 8, where n is the memory address to read into the cache. Memory addresses 0, 8, and 16 will all map to block 0 in the cache. Cache performance is worst when multiple data items with the same hash value are read, and performance is best when data items are close together in memory (such as a sequential block of program instructions, or a sequential array).

Most external caches (located on the motherboard, but external to the CPU) are direct-mapped or occasionally 2-way set associative, because it's complicated to build higher-associativity caches out of standard components. If there is such a cache, typically there is only one external cache on the motherboard, shared between all CPUs.

The replacement policy for a direct-mapped cache is the simplest possible replacement policy: the new data must go in the one and only one place in the cache it corresponds to. (The old data at the location in the cache, if its dirty bit is set, must be written to main memory first).

2-Way Set Associative
In a 2-way set associative cache system, the data value is hashed, but each hash value corresponds to a set of cache blocks. Each block contains multiple data cells, and a data value that is assigned to that block can be inserted anywhere in the block. The read speeds are quick because the cache controller can immediately narrow down its search area to the block that matches the address hash value.

The LRU replacement policy for a 2-way set associative cache is one of the simplest replacement policies: The new data must go in one of a set of 2 possible locations. Those 2 locations share a LRU bit that is updated whenever either one is read or written, indicating which one of the two entries in the set was the most-recently used. The new data goes in the *other* location (the least-recently used location). (The old data at that LRU location in the cache, if its dirty bit is set, must be written to main memory first).

2 way skewed associative
The 2-way skewed associative cache is "the best tradeoff for .... caches whose sizes are in the range 4K-8K bytes" -- André Seznec

Fully Associative
In a fully-associative cache, hash algorithms are not employed and data can be inserted anywhere in the cache that is available. A typical algorithm will write a new data value over the oldest unused data value in the cache. This scheme, however, requires the time an item is loaded or accessed to be stored, which can require lots of additional storage.

Cache Misses
There are three basic types of misses in a cache:
 * 1) Conflict Misses
 * 2) Compulsory Misses
 * 3) Capacity Misses

Conflict Misses

A conflict miss occurs in a direct-mapped and 2-way set associative cache when two data items are mapped to the same cache locations. In a data miss, a recently used data item is overwritten with a new data item.

Compulsory Misses

The image above shows the difference between a conflict miss and a compulsory miss. A compulsory miss is an instance where the cache must miss because it does not contain any data. For instance, when a processor is first powered-on, there is no valid data in the cache and the first few reads will always miss.

The compulsory miss demonstrates the need for a cache to differentiate between a space that is empty and one that is full. Consider when we turn the processor on, and we reset all the address values to zero, an attempt to read a memory location with a hash value of zero will hit. We do not want the cache to hit if the blocks are empty.

Capacity Misses
Capacity misses occur when the cache block is not large enough to hold the data item.

Cache Write Policy
Data writes require the same time delay as a data read. For this reason, caching systems typically will write data to the cache as well. However, when writing to the cache, it is important to ensure that the data is also written to the main memory, so it is not overwritten by the next cache read. If data in the cache is overwritten without being stored in main memory, the data will be lost.

It is imperative that caches write data to the main memory, but exactly when that data is written to the main memory is called the write policy. There are two write policies: write through and write back.

Write operations take as long to perform as read operations in main memory. Many cached processors therefore will perform write operations on the cache as well as read operations.

Write Through
When data is written to memory, a write request is sent simultaneously to the main memory and to the cache. This way, the result data is available in the cache before it can be written (and then read again) from the main memory. When writing to the cache, it's important to make sure the main memory and the cache are synchronized and they contain the same data.

In a write through system, data that is written to the cache is immediately written to the main memory as well. If many writes need to occur is sequential instructions, the write buffer may get backed up and cause a stall.

Write Back
In a write back system, the cache controller keeps track of which data items have been synchronized to main memory. The data items which have not been synchronized are called "dirty", and the cache controller prevents dirty data from being overwritten.

The cache controller will synchronize data during processor cycles where no other data is being written to the cache.

Write bypass
Some processors send writes directly to main memory, bypassing the cache. If that location is *not* already cached, then nothing more needs to be done. If that location *is* already cached, then the old data in the cache(s) needs to be marked "invalid" ("stale") so if the CPU ever reads that location, the CPU will read the latest value from main memory rather than some earlier value(s) in the cache(s).

Stale Data
It is possible for the data in main memory to be changed by a component besides the microcontroller. For instance, many computer systems have memory-mapped I/O, or a DMA controller that can alter the data. Some computer systems have several CPUs connected to a common main memory. It is important that the cache controller check that data in the cache is correct. Data in the cache that is old and may be incorrect is called "stale".

The three most popular approaches to dealing with stale data ("cache coherency protocols") are:
 * Use simple cache hardware that ignores what the other CPUs are doing.
 * Set all caches to write-through all STOREs (write-through policy). Use additional cache hardware to listen in ("snoop") whenever some other device writes to main memory, and invalidate local cache line whenever some other device writes to the corresponding cached location in main memory.

 * Design caches to use the MESI protocol.

With simple cache hardware that ignores what the other CPUs are doing, cache coherency is maintained by the OS software. The OS sets up each page in memory as either (a) exclusive to one particular CPU (which is allowed to read, write, and cache it); all other CPUs are not allowed to read or write or cache that page; (b) shared read/write between CPUs, and set to "non-cacheable", in the same way that memory-mapped I/O devices are set to non-cacheable; or (c) shared read-only; all CPUs are allowed to cache but not write that page.

Split cache
High-performance processors invariably have 2 separate L1 caches, the instruction cache and the data cache (I-cache and D-cache). This "split cache" has several advantages over a unified cache:
 * Wiring simplicity: the decoder and scheduler are only hooked to the I-cache; the registers and ALU and FPU are only hooked to the D-cache.
 * Speed: the CPU can be reading data from the D-cache, while simultaneously loading the next instruction(s) from the I-cache.

Multi-CPU systems typically have a separate L1 I-cache and L1 D-cache for each CPU, each one direct-mapped for speed.

Open question: To speed up running Java applications in a JVM (and similar interpreters and CPU emulators), would it help to have 3 separate caches -- a machine instruction cache indexed by the program counter PC, a byte code cache indexed by the VM's instruction pointer IP, and a data cache ?

On the other hand, in a high-performance processor, other levels of cache, if any -- L2, L3, etc. -- as well as main memory -- are typically unified, although there are several exceptions (such as the Itanium 2 Montecito). The advantages of a unified cache (and a unified main memory) are:
 * Some programs spend most of their time in a small part of the program processing lots of data. Other programs run lots of different subroutines against a small amount of data. A unified cache automatically balances the proportion of the cache used for instructions and the proportion used for data -- to get the same performance on a split cache would require a larger cache.
 * when instructions are written to memory -- by an OS loading an executable file from storage, or from a just-in-time compiler translating bytecode to executable code -- a split cache requires the CPU to flush and reload the instruction cache; a unified cache doesn't require that.

Error detection
Each cache row entry may have error detection bits. Since the cache only holds a copy of information in the main memory (except for the write-back queue), when an error is detected, the desired data can be re-fetched from the main memory -- treated as a kind of miss-on-invalid -- and the system can continue as if no error occurred. A few computer systems use Hamming error correction to correct single-bit errors in the "data" field of the cache without going all the way back to main memory.

Specialized cache features
Many CPUs use exactly the same hardware for the instruction cache and the data cache. (And, of course, the same hardware is used for instructions as for data in a unified cache. The revolutionary idea of a Von Neumann architecture is to use the same hardware for instructions and for data in the main memory itself). For example, the Fairchild CLIPPER used 2 identical CAMMU chips, one for the instruction cache and one for the data cache.

Because the various caches are used slightly differently, some CPU designers customize each cache in different ways.

 * Some CPU designers put the "branch history bits" used for branch prediction in the instruction cache. There's no point to adding such information to a data-only cache.
 * Many instruction caches are designed in such a way that the only way to deal with stale instructions is to invalidate the entire cache and reload. Data caches are typically designed with more fine-grained response, with extra hardware that can invalidate and reload only the particular cache lines that have gone stale.
 * The virtual-to-physical address translation process often has a lot of specialized hardware associated with it to make it go faster -- the TLB cache, hardware page-walkers, etc. We will discuss this in more detail in the next chapter, ../Virtual Memory/.

title: Microprocessor Design/Cache


text:
Minesweeper/Playing The Game

Minesweeper mostly consists of thinking and a little bit of luck. Though it is not a game of quick reflexes or action, players may find themselves making suspenseful decisions when executing an uncertain move.

Basics of Play
Minesweeper starts off with a blank board of tiles. The default is 9x9, but it can be any size. Each tile can be in three main states:

 * 1) It can be blank, with no information. (These are tiles that haven't been clicked on)
 * 2) It can have a number or remain blank.
 * 3) The number shows= how many mines are in the 8 tiles surrounding it.)
 * 4) It can be blank after clicking on it. This is effectively a number tile with the value of 0, indicating there are zero mines around it.
 * 5) It can be a bomb.

Example Game
You start off with a blank grid, and for your first tile, you must guess.

Here's an example below, of a 4x4 grid:

Now let's say, you clicked on the tile at (2,2)

That would tell us, "1" of the 8 tiles around it are a mine. Let's try clicking on two more:

We can tell that the tile in the top left corner has a mine, because it has to be a tile shared by all three ones. To illustrate this (? means possible mine):

Only one "X" is shared by all three ones, therefore, that must be our mine. Now that we know it's a mine, we can indicate that by right clicking on it. Right clicking on a tile will make it through a few of its states. The first one, would "flag" it, with a small red flag. The second, will replace the flag with a question mark (Shown above). And a third click would make it revert back to it's original state (as a blank tile).

Blank Tiles
The blank tiles show nothing on them. They can be hiding a number tile or a mine tile under them. A flag tile can also be played on it. In some versions of the game, there are also question mark tiles, which can also be played on blank tiles.

Number Tiles
The number tiles can have a number from 1 to 8. The numbers tell how many mine tiles are touching the number tile.

In some versions of the game, number tiles come in many colors, making it easier to distinguish them at a glance.

Mine Tiles
The mine tiles shows a mine on each one of them. When the player clicks on a Mine tile, then they loose the game.

Flag Tiles
The flag tiles shows a flag on them. These tiles can still be clicked on if the flag is taken off. The player can choose where to put the flags. The flags shows your guess on where the mine is, but the game will not stop the player from placing a flag where there is no actual mine. Because of this, it is a good idea to only use a flag when you are certain there is actually a mine. If you simply suspect a mine, a question mark is often a better representation of that uncertainty.

Question Mark Tiles
The Question mark tiles show a question mark on them. Only some versions of Minesweeper are equipped with this feature. This tile can be clicked on if the question mark is taken off. The player can choose where to put the question mark. The question mark shows where the player isn't sure what is under the blank tiles. When a player is certain a mine is beneath a tile, it is better to use a flag tile instead.

Mine Free Tiles
Mine free tiles have no picture on them, but have been clicked on. Distinguishing them from number tiles, this tile indicates that there are no mines around them.

title: Minesweeper/Playing The Game


text:
Radiation Oncology/Optic Pathway Glioma

Optic Pathway Glioma

Epidemiology

 * Low grade astrocytic tumors
 * Prevalence
 * 2% of cerebral gliomas
 * 5% of childhood brain tumors
 * 90% in children <20 years, 75% in <10 year olds; 10% in adults
 * Associated with neurofibromatosis
 * 30% of OPG patients have NF1 stigmata
 * Up to 25% of NF1 patients develop OPG (most common CNS tumor in NF1)
 * Location
 * Anterior (orbital, infracanalicular, prechiasmal) - common in prepubertal children
 * Posterior (chiasm, hypothalamus, anterior 3rd ventricle) - common in adolescents

Treatment

 * Optimal management of optic pathway gliomas is controversial
 * Patient age
 * Tumor location
 * Presence of NF1
 * Children should probably be managed with observation and close follow-up, if possible
 * Adults should be managed aggressively
 * Non-surgical treatment algorithm as per PMID 16411210
 * <3 years or 3-10 with unresectable lesion
 * Observe until radiographic or symptomatic progression
 * Packer regimen (carboplatin/vincristine); if no progression, observe; if progression, RT
 * >10 years
 * Proton RT if available, else stereotactic/conformal RT; if no progression, observe; if progression, protocol

Surgery

 * No consensus regarding optimal timing
 * Likely benefit:
 * Obstructive hydrocephalus
 * Single nerve involvement causing progressive disfiguring proptosis or blindness
 * Possible benefit: delaying RT in young children
 * Probable contra-indication:
 * Diffuse chiasmal involvement/broadly infiltrative disease
 * NF patients

Chemotherapy

 * No consensus; most are treated under Low Grade Glioma guidelines
 * UCSF study demonstrated activity of nitrosurea-based chemo (TPDCV)
 * George Washington study (Packer) demonstrated good outcomes with carboplatin/vincristine (now the most "standard" chemo)
 * French trial showed good long-term control, while avoiding RT
 * Children's Oncology Group trial CCG A9952 recently reported(essentially randomizing UCSF and GW protocols)

Published
 * CCG A9952 PMID 22665535 -- "Randomized study of two chemotherapy regimens for treatment of low-grade glioma in young children: a report from the Children's Oncology Group." (Ater JL, J Clin Oncol. 2012 Jul 20;30(21):2641-7.)
 * Prospective RCT. 274 patients < 10 years of age with progressive or residual LGG. Randomized to carboplatin and vincristine (CV) or thioguanine, procarbazine, lomustine, and vincristine (TPCV).
 * 5-year outcomes: EFS 39% (CV) vs. 52% (TPCV) (stratified log-rank test P = .10; cure model analysis P = .007)
 * Prognostic factors: younger age and tumor size greater than 3 cm2 (worse EFS and OS), thalamic tumors (worse OS)
 * Conclusion: Differences in toxicity may influence treatment decisions.

 * French Society of Pediatric Oncology, 2003 (1990-1998) PMID 14673044 -- "Progression-free survival in children with optic pathway tumors: dependence on age and the quality of the response to chemotherapy--results of the first French prospective study for the French Society of Pediatric Oncology." (Laithier V, J Clin Oncol. 2003 Dec 15;21(24):4572-8.)
 * Prospective. 85 children with progressive optic pathway tumors. Chemo: alternating procarbazine/carboplatin, etoposide/cisplatin, and vincristine/cyclophosphamide every 3 weeks. At relapse, 2nd line chemo before RT
 * 5-year outcomes: PFS 34%, OS 89%. RT-free survival 61%
 * Prognostic factors: age <1, NF1 associated with disease progression
 * Conclusion: RT can be avoided with prolonged chemotherapy, without compromising OS or visual function

 * Royal Marsden, 2003 (UK) PMID 12892235 -- "Tolerance of nitrosurea-based multiagent chemotherapy regime for low-grade pediatric gliomas." (Lancaster DL, J Neurooncol. 2003 Jul;63(3):289-94.)
 * Prospective. 10 children with low-grade gliomas, initially treated with carboplatin/vincristine, second line with TPCV
 * Conclusion: TPCV is appropriate as second line therapy

 * George Washington, 1997 PMID 9126887 -- "Carboplatin and vincristine chemotherapy for children with newly diagnosed progressive low-grade gliomas." (Packer RJ, J Neurosurg. 1997 May;86(5):747-54.)
 * Prospective. 78 children with progressive low-grade glioma (12 brainstem gliomas). Concurrent carboplatin/vincristine. Median F/U 2.5 years
 * 3-year PFS: 68%. No difference between NF1+ and NF1-. Objective response 56%
 * Prognostic factors: only age (<3 yo 74% vs. >3 yo 39%, SS)

 * UCSF, 1991 (1983-1989) PMID 1901597 -- "Management of chiasmal and hypothalamic gliomas of infancy and childhood with chemotherapy." (Petronio J, J Neurosurg. 1991 May;74(5):701-8.)
 * Retrospective. 19 children with chiasmal/hypothalamic gliomas. 12 treated immediately for progressive symptoms, 7 deferred. Chemo: TPDCV
 * Median time to progression: not reached at 20 months. No tumor-related deaths. Initial response/stabilization 15/18 patients
 * Salvage: RT
 * Conclusion: TPDCV allows RT to be deferred until progression of disease.

Radiation

 * Most favorable outcomes reported for 45-56 Gy, in 1.8 Gy/fx
 * Suggestion that posterior location tumors have worse outcomes
 * Proton RT is being explored

 * Harvard, 2005 (1992-1998) PMID 15667955 -- "Stereotactic radiotherapy for localized low-grade gliomas in children: final results of a prospective trial." (Marcus K, Int J Radiat Oncol Biol Phys. 2005 Feb 1;61(2):374-9.)
 * Prospective. 50 patients with localized low-grade glioma. RT for progression on/after chemo or surgery. Median F/U 6.9 years
 * RT: Removable head frame. 2-mm margin. Mean dose 52.2 Gy in 1.8 Gy/fx. Target delineation via CT/MRI fusion
 * 5-year outcome: PFS 83%, OS 98%; 6 patients with in-field progression, no marginal failures
 * Conclusion: stereotactic RT excellent local control, with limited margins

 * Heidelberg, 2005 (Germany) (1990-2003) PMID 15936565 -- "Fractionated stereotactic radiotherapy of optic pathway gliomas: tolerance and long-term outcome." (Combs SE, Int J Radiat Oncol Biol Phys. 2005 Jul 1;62(3):814-9.)
 * Retrospective. 15 patients. Median dose 52.2 Gy (45.2-57.6) in 1.8 Gy/fx. Median F/U 8 years
 * 5-year outcome: PFS 72%, OS 90%. No second malignancies
 * Conclusion: Good control, normal brain sparing. Longer f/u needed

 * Institut Curie, 1991 (1970-1986) PMID 1907959 -- "Chiasmal gliomas: results of irradiation management in 57 patients and review of literature." (Bataini JP, Int J Radiat Oncol Biol Phys. 1991 Aug;21(3):615-23.)
 * Retrospective. 57 patients, 37% chiasm, 63% extended to hypothalamus/posteriorly. RT 40-60 Gy. Mean F/U 7.5 years
 * 5-year (and 10-year) OS: 84%; response: CR 15%, PR 46%, SD 22%
 * Conclusion: RT effective in cases of rapidly developing visual, neurological, or endocrine symptoms

 * Neurological Institute, Columbia University, 1956 PMID 13323290 -- "The value of radiation therapy in the management of glioma of the optic nerves and chiasm." (Taveras JM, Radiology. 1956 Apr;66(4):518-28.)
 * Retrospective. 34 patients treated with RT
 * Survival: 23/34 at time of publication
 * Landmark study. Results deemed exceptional. Launched RT as a management strategy

RT Complications

 * Manchester/London, 2006 PMID 16735710 -- "Second primary tumors in neurofibromatosis 1 patients treated for optic glioma: substantial risks after radiotherapy." (Sharif S, J Clin Oncol. 2006 Jun 1;24(16):2570-5.)
 * Retrospective. 58/80 NF1 patients with OPG. 18/58 RT alone or in combination. Dose 25-50 Gy
 * Second CNS tumor: RT 9/18 (50%) developed 12 second tumors in 308 person-years of F/U; No RT 8/40 (20%) developed 9 second tumors in 721 person-years of F/U. RR 3 (SS). Median time-to-diagnosis 12 years. Risk of MPNST was increased RR 5.3 (SS) over non-OPG NF1 controls
 * Conclusion: Significantly increased 2nd CNS cancer risk in NF1 patients with OPG; RT should be used only if absolutely necessary

 * Toronto, 1993 (1971-1990) PMID 8315466 -- "Moyamoya phenomenon after radiation for optic glioma." (Kestle JR, J Neurosurg. 1993 Jul;79(1):32-5.)
 * Retrospective. 47 patients with OPG treated.
 * Moyamoya phenomenon: 0/19 no RT; 5/28 with RT; 2/23 NF1- vs. 3/5 NF1+ (SS)
 * Conclusion: High incidence of moyamoya in patients with NF1 and cranial RT
 * Note: Moyamoya disease is a progressive chronic cerebrovascular disease seen mainly in Asia characterized by bilateral stenosis/occlusion of the arteries in the circle of Willis with an unknown etiology that here used to describe post-radiation changes to the vascular system

Review

 * 2006 PMID 16411210 -- "Optic pathway gliomas." (Jahraus CD, Pediatr Blood Cancer. 2006 May 1;46(5):586-96.)

title: Radiation Oncology/Optic Pathway Glioma


text:
Radiation Oncology/Pilocytic Astrocytoma

Pilocytic Astrocytoma

Juvenile Pilocytic Astrocytoma

 * WHO Grade I tumors
 * Well-circumscribed, enhancing lesions typically located in the cerebellum; many are Optic Pathway Gliomas
 * Surgical resection alone results in favorable outcome, with 10-year OS >80%

Proton Therapy

 * Loma Linda; 2002 (1991-1997) PMID 11977386 -- "Conformal proton radiation therapy for pediatric low-grade astrocytomas." (Hug EB, Strahlenther Onkol. 2002 Jan;178(1):10-7.)
 * Retrospective. 27 patients, progressive or recurrent low-grade astrocytoma. Fractionated proton therapy 50.4-63 CGE in 1.8 CGE/fx. Mean F/U 3.3 years
 * Outcome: LC 78%, OS 85%
 * Toxicity: well tolerated; Moyamoya disease in one child with NF1; 6 patients with optic pathway tumors maintained/improved their vision
 * Conclusion: Proton RT is safe and efficacious; longer term follow-up needed

Adult Pilocytic Astrocytoma

 * Uncommon
 * Clinical presentation includes visual disturbances, seizures, and headaches. Papilledema common
 * Favorable prognosis both in terms of survival and neurologic function
 * Most remain stable after resection (gross or subtotal) only, and need no adjuvant RT with close follow-up
 * It may be reasonable to offer RT in unresectable disease, especially if causing neurologic symptoms
 * 10 year OS 95%

 * Intergroup NCCTG/RTOG (1986-1994)
 * Prospective. 20 adults with supratentorial pilocytic astrocytoma. If gross total (n=11) or subtotal (n=6) resection, observation. If biopsy only (n=3), RT 50.4 Gy to 2-cm edema margin
 * 10 years; 2004 PMID 15001258 -- "Adult patients with supratentorial pilocytic astrocytomas: a prospective multicenter clinical trial." (Brown PD, Int J Radiat Oncol Biol Phys. 2004 Mar 15;58(4):1153-60.) Median F/U 10 years
 * 10-year outcome: 95% alive. 1 patient died of unknown cause 2.1 years after enrollment; 1 patient progressed 1 month after enrollment and was salvaged with P-32 followed 1.5 years later by RT, now without evidence of progression at 9 years
 * Conclusion: Favorable prognosis; don't need RT after gross total or subtotal resection


text:
User talk:Bindhu

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Good luck! Mattb112885 (talk) 02:06, 4 April 2007 (UTC)

Image copyright problem with Image:Capillaryelectrophoresis.JPG
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title: User talk:Bindhu


text:
User talk:Jennydalby

Hello, and welcome to Wikibooks!

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You will find more resources in Community Portal. If you want to ask a question, visit the Study help desk, the Staff lounge, IRC channel or ask me personally on my talk page. For site news, see the Bulletin board. It might be a good idea to add this page to your "watchlist" so that you can see when any new information is posted there. You can do that by clicking the tab labeled "watch" at the top of the page.

Good luck! Mattb112885 (talk) 02:06, 4 April 2007 (UTC)

title: User talk:Jennydalby


text:
User talk:Annastanley

Hello, and welcome to Wikibooks!

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You will find more resources in Community Portal. If you want to ask a question, visit the Study help desk, the Staff lounge, IRC channel or ask me personally on my talk page. For site news, see the Bulletin board. It might be a good idea to add this page to your "watchlist" so that you can see when any new information is posted there. You can do that by clicking the tab labeled "watch" at the top of the page.

Good luck! Mattb112885 (talk) 02:06, 4 April 2007 (UTC)

title: User talk:Annastanley


text:
Radiation Oncology/Thyroid/Anaplastic

Epidemiology

 * 2% of thyroid cancers
 * 13-39% thyroid cancer deaths
 * F>M 3:1
 * Mean age of diagnosis is 65

Pathophysiology

 * Thought to be a de-differentiation of a previously differentiated thyroid cancer.
 * 20% have history of differentiated thyroid CA
 * 20-30% have concurrent papillary thyroid CA
 * loss of p53 thought to be a major step in de-differentiation.

Histologic Subtypes
Histologic subtype has not been found to affect prognosis.
 * Spindle Cell
 * Giant Cell
 * Squamoid

Staging
All anaplastic thyroid CA is considered stage IV.
 * see Staging for details.

Treatment

 * Monotherapy (surgery, chemo, xrt) have not shown to benefit overall survival.
 * Current treatment of choice is multi-modality. Upfront resection is preferred if tumor confined to thyroid.
 * Hyperfractionated xrt with adriamycin treatment of choice for locally advanced non-metastatic. Consider consolidative surgery if good response to chemoxrt.
 * Dose of 60 Gy in 40 fx over 4 wks.

Treatment Prognostic Factors

 * SEER Database Analysis, 2005 PMID 15739211 "Anaplastic thyroid carcinoma. Treatment outcome and prognostic factors," (Kebebew E, Cancer. 2005; 103(7):1330-5.)
 * 516 pts from SEER cancer registry tx'd for anaplastic thyroid CA from 1973-2000.
 * Overall cause-specific mortality at 6 mo's was 68.4% and at 12 mo's was 80.7%.
 * On multi-variate analysis age<60 and intrathyroid tumor (w/o mets) were independent predictors of lower cause-specific mortality.
 * Conclusion: given the majority of data for ATC derived from small single institution series which are subject to selection bias, this analysis identifies prognostic factors that may be used to triage more aggressive treatments to patients who may benefit.

Combined Modality Approach

 * SEER Database Analysis, 2008 (1983-2002) PMID 18838882 — "Surgery and radiotherapy improves survival in patients with anaplastic thyroid carcinoma: analysis of the surveillance, epidemiology, and end results 1983-2002." (Chen J, Am J Clin Oncol. 2008 Oct;31(5):460-4.)
 * 261 pts who had surgery performed or recommended
 * Median survival 4 months. On multivariate analysis, distant disease, tumor size > 7 cm, and treatment with surgery (+/- RT) were significant related to survival. The addition of RT to surgery resulted in improved survival for pts with disease extending into adjacent tissue but not for those with disease limited to the capsule or with distant metastatic disease
 * Conclusion: surgery and radiotherapy improves survival.

 * Princess Margaret, 2001 PMID 11413523 "Completely resected anaplastic thyroid carcinoma combined with adjuvant chemotherapy and irradiation is associated with prolonged survival," (Haigh PI, Cancer. 2001; 91(12):2335-42.)
 * 33 pts w/ anaplastic thyroid cancer retrospectively reviewed to determine prognostic factors. 64% w/ metastatic dz.  92% received adjuvant therapy.
 * Pts w/ curative resection w/ longer median survival.
 * Conclusion: Complete resection or maximum tumor debulking followed by adjuvant chemo/xrt resulted in some long term survivals.

 * Mayo Clinic, 2001 PMID 11742333 "Anaplastic thyroid carcinoma: a 50-year experience at a single institution," (McIver B, Surgery. 2001; 130(6):1028-34.)
 * 134 cases b/w 1949-99, mean age 67, 46% w/ mets at time of dx
 * 72% underwent surgery, 30% w/ complete resection
 * Neither surgery, chemo, nor radiation improved survival significantly. Combined modality approach was the only approach that led to long-term survivors.

Altered Fractionation of Radiotherapy

 * Princess Margaret, 2006 PMID 16967442 "Clinical outcome of anaplastic thyroid carcinoma treated with radiotherapy of once- and twice-daily fractionation regimens," (Wang Y, Cancer. 2006; 107(8):1786-92)
 * 47 pts w/ anaplastic thyroid CA tx'd b/w 1983-2004. Pts tx'd palliatively or w/ curative intent w/ goal to assess local control, survival, toxicity of once vs twice daily regimens.
 * 94% 6 mo local PFS if xrt w/ radical intent, 64% if palliative intent. Median OS 3.3 mo's longer if BID fractionation (13.6 vs 10.3 mo's)
 * Conclusion: twice daily fractionation appears to lead to better outcome.

 * Royal Marsden Pure Accelerated XRT, 1999 PMID 10225555 "Phase II evaluation of high dose accelerated radiotherapy for anaplastic thyroid carcinoma," (Mitchell G, Radiother Oncol. 1999; 50(1):33-8.)
 * 17 pts w/ anaplastic thyroid CA tx'd w/ BID xrt to 60.8 Gy (1.8 Gy in AM, 2 Gy in PM)
 * 3 pts w/ CR, 7 pts w/ partial response; toxicity from esophagitis/dysphagia high (40% grade 4 pharyngo-esophagitis, dysphagia)
 * Conclusions of the authors were that toxicities of pure acceleration were unacceptably high in spite of improved local control rate.

 * Sweden, 1994 PMID 8055459 "Combined doxorubicin, hyperfractionated radiotherapy, and surgery in anaplastic thyroid carcinoma. Report on two protocols. The Swedish Anaplastic Thyroid Cancer Group," (Tennvall J, Cancer. 1994; 74(4):1348-54. )
 * 33 pts w/ anaplastic thyroid CA tx'd w/ hyperfractionated xrt (30 Gy preop, 46 Gy postop), doxorubicin, surgery
 * 48% local control, 24% death from local failure, 4 pts survived 2 yrs

title: Radiation Oncology/Thyroid/Anaplastic


text:
Proteomics/Protein - Protein Interactions/new

Page Edited and Updated by: Christopher Fucile E-mail: cff8255@rit.edu

This Section:

Protein-Protein Interaction Network Visualization
Protein interaction network visualization is one of the most user-friendly features developed for the simulation process of protein protein interactions. Drawing of a protein may seem to be easy but generating the same protein with all the types of conformation that it can attain for a simulation process is quite difficult. In this context one of the greatest manually produced molecular structures of its time was done by Kurt Kohn's 1999 map of cell cycle control. In this paper around 1,548 proteins were linked together as determined by yeast two-hybrid assay.

Protein-protein interaction network visualization deals with territory that is very similar to that of protein-protein interaction prediction, but differs in several key ways. Foremost, visualization tools were developed simply for illustrating the big picture represented by protein-protein interaction data or expression data, for qualitative assessment, not necessarily for quantitative analysis or prediction. Expression and interaction experiments tend to be on such a large scale that it is difficult to analyze them, or indeed grasp the meaning of the results of any analysis. Visual representation of such large and scattered quantities of data allows trends that are difficult to pinpoint numerically to stand out and provide insight into specific avenues of protein functions and interactions that may be worth exploring first out of the bunch, either through confirmation or rejection and then later of significance or insignificance to the research problem at hand. With a few recent exceptions, visualization tools were not designed with the intent of being used for analysis so much as to show the workings of a molecular system more clearly.

Visualization tools also do not actually predict protein-protein interactions themselves or their characteristics. On the contrary, visualization tools only create a graphical representation of what is already "known" in literature and in molecular interaction repositories such as the Gene Ontology(GO). A side-effect of displaying interaction networks by treating some proteins as members of more general family groupings or going by interactions in different tissues or as analogues in other tissues or organisms is the apparent display of a protein-protein or other molecular interaction that is inferred but may or may not have actually been observed and documented, something that could be misconstrued as a predicted interaction. There is no statistical analysis involved; this phenomenon is merely a fluke of the annotation scheme used as a reference (albeit a useful fluke).

Perhaps the most significant difference between protein-protein interaction network visualization and protein-protein interaction prediction is the nature of the information it provides. Protein-protein interaction prediction is characterized by its concern with how proteins will interact, where they will interact, under what conditions they were interact, and what parts are necessary for their interaction. These characteristics are governed by physical and chemical properties of the proteins or other molecules involved, which may be actual molecules that have been described through extensive proteomics experiments or hypothetical, in silico generated species that are being investigated for pharmaceutical and other applications. Interaction network visualization tools are given no knowledge of physical or chemical properties of the proteins they are displaying other than their presence in the system and sometimes a normalized level of expression. As a result, the information they inadvertently impart concerns only whether or not certain proteins putatively interact with certain other proteins, not how they interact, when they interact, or why they interact.

Visualization Tools
Due to the ever increasing employment of interaction of network visualization to direct research, scientists decided to automate the process. Some of the automated visualization systems are as follows.

Osprey
Osprey is a visualization tool that represents genes as nodes and interactions between gene products as edges. It uses the GRID database to determine interactions by default, but can be configured in a number of ways to meet the user's needs. Osprey was developed in answer to the need to text-search the network of interactions and can output networks to a number of graphical formats.

A limited version is available at the BioGRID website: http://www.thebiogrid.org/

A full version for personal or non-profit use is downloadable from the Osprey site: http://biodata.mshri.on.ca/osprey/servlet/Index

VisANT
VisANT is a tool that creates a visual interface for mining gene/protein interaction data with a focus on being adaptable to new types of data, both in terms of interactions and interacting members. It taps into a number of databases including GenBank, KEGG, and SwissProt.

VisANT is available via web interface at the VisANT site: http://visant.bu.edu/

NAViGaTOR
NAViGaTOR is an interaction visualization tool that combines Java with OpenGL to deliver multi-platform 2D and 3D representations of physical protein-protein interaction networks. It includes options for color-coding network maps according to the GO and information in the literature. NAViGaTOR supports standard import and export formats such as GO and Proteomics Standards Initiative (PSI).

NAViGaTOR is available for download online at the NAViGaTOR site: http://ophid.utoronto.ca/navigator

Cytoscape
Cytoscape is primarily a visualization tool written in Java for molecular interaction networks. User-defined interactions are supported, as is the ability to record attributes of nodes, edges, and networks. Annotations can be imported from GO and KEGG. Cytoscape allows visualization of expression data on a network not just by user-defined color-coding, but also through border thickness and color and the option to display expression levels and p-values on the network. Methods for analysis can be added through plugins that allow filtering by expression level, identifying differentially expressed subnetworks, and identifying clusters of highly interconnected nodes (molecules).

Cytoscape is available for download at the Cytoscape site: http://www.cytoscape.org

yEd
yEd is a graph editor that allows users to edit existing graphs as well as generate new ones but is not limited to working with biological data and offers no analysis tools. It seems as though yEd might be of use chiefly as a tool for cleaning up and tweaking graphs generated by other, more biologically-specialized visualization tools to be used for posters or other publications. yEd does support widely-used import formats like GML and is available for a number of platforms.

yEd is available for download at the yEd site: http://www.yworks.com/en/products_yed_about.htm

NetPro
NetPro is a commercially developed and manually-curated protein-protein interactions database. The emphasis in NetPro is on facilitating the literature search and text-mining steps of investigating putative protein-protein interactions and their ramifications. Molecular Connections, the company that maintains and distributes NetPro, is also the producer of a handful of other visualization tools.

NetPro is not free, but more information is provided at the Molecular Connections site: http://www.gene-regulation.com/pub/databases/transpath/6.0/doc/netpro.html

References(Open Access)
1. Kohn, K. W. Molecular Interaction Map of the Mammalian Cell Cycle Control and DNA Repair Systems. Mol Biol Cell. 1999 August; 10(8): 2703–2734.

2. "Gene Ontology" Wikipedia, The Free Encyclopedia. Wikimedia Foundation, Inc. 30 March 2008. .

3. "OSPREY: Network Visualization System" Osprey Community. 30 March 2008.

4. "VisANT: An integrative platform for network/pathway analysis" Visant. 30 March 2008.

5. "NAViGaTOR (Network Analysis, Visualization, & Graphing, TORonto)" Ontario Cancer Institute. 30 March 2008.

6. "Cytoscape: Analyzing and Visualizing Network Data" Cytoscape Consortium. 30 March 2008.

7. "yEd - Java Graph Editor" yWorks. 30 March 2008.

8. "Biomedical text mining" Wikipedia, The Free Encyclopedia. Wikimedia Foundation, Inc. 30 March 2008.

9. "NetPro Documentation" NetPro. 30 March 2008.


text:
User talk:WOOda

Yay i have a wikibook!!!

title: User talk:WOOda


text:
MediaWiki:Blacklistedusername

Username disallowed

title: MediaWiki:Blacklistedusername


text:
Microsoft Certified Professional Developer/Exam 70-548

Contents at a Glance
1 Application Requirements and Design 2 Decompose Specifications for Developers 3 Design Evaluation 4 Define a Common User Interface Layout 5 Validation and User Feedback 6 Component Design 7 Component Development 8 Instrumenting Your Application 9 Building Components 10 Handling Exceptions 11 Application Configuration 12 Define and Evaluate a Testing Strategy 13 Creating Development Tests 14 Deploying an Application 15 Supporting an Application 16 Multimedia in Windows Applications


text:
User:Alva~enwikibooks

new pea

title: User:Alva~enwikibooks


text: User:Haleakalari

title: User:Haleakalari


text:
Horticulture/Prunus 'Okame'

Okame cherry is a hybrid tree, which is one of the earliest cherries to bloom, and thus is often planted in parks and gardens. The name "Okame" is Japanese, referring to a woman who is often depicted in statues.

Description
More or less vase-shaped crown, densely covered in pink flowers before the leaves emerge in the spring.

Growing conditions
Full sun to medium shade, often does fine under high canopies. The plant prefers deep, fertile soils. Somethat drought tolerant after established.

Uses
As a specimen or patio shade tree. Forces well, so can also be grown for cut flowers.

Maintenance
Pruning for crossing branches should be done every 2-4 years. The tree is often grafted, so basal suckers should be removed if present.

Propagation
Generally grafted.

Harvesting
For forcing, cut branches just as the buds begin to expand.

Pests and diseases
Usually problem-free. See ../Prunus/ for a list of pests and diseases.

title: Horticulture/Prunus 'Okame'


text:
Hacking/Tools/Network/Nmap

Hacker Fyodor (Gordon Lynn) wrote   to assist in port scanning and network analysis. He published the original source code in Phrack Magazine, Volume 7, Issue 51, Article 11, and now maintains the tool at Insecure.org. Security experts all over the world use  for simple network checks, detecting open ports and service versions; the NSA keeps a list of security tools and current versions—including , Snort, and Nessus—up on the big board.

does not only detect open ports; it detects services and operating system versions as well. You can use  to scan a default range of ports, or a specific subset; it can scan a single host, a range, or a set; and it can find out if hosts are up or down. can become a powerful tool in the hands of a skilled user, for good or for evil.

The  network scanning tool supplies a diverse set of options to control its behavior. It can scan multiple hosts and host ranges; utilize various scanning techniques; identify operating systems and service versions; and even perform stealth scanning to avoid triggering certain IDS and IPS utilities.

Usage Example :

Basic use
First, let's cover some basic use of. You should at the very least know how to scan hosts and check for specific ports; these fundamentals will show you what's open on the target network.

Scanning hosts
Basic use of  just involves scanning a target IP address or domain name. For example:

bluefox@ice-ldap:~$ nmap webserv1

Starting Nmap 4.10 ( http://www.insecure.org/nmap/ ) at 2007-04-01 15:52 EDT Interesting ports on webserv1 (192.168.30.11): Not shown: 1644 closed ports, 28 filtered ports PORT    STATE SERVICE 21/tcp  close  ftp 22/tcp  close  ssh 80/tcp  close  http 111/tcp close  rpcbind 199/tcp close  smux 443/tcp open  https 1008/tcp close ufsd

Nmap finished: 1 IP address (1 host up) scanned in 15.142 seconds

In this mode of operation,  shows the open ports and the common service carried on that port. will not show services moved to other ports accurately; http on port 21 will read as ftp, for example.

You can specify multiple hosts on 's command line as well:

bluefox@ice-ldap:~$ nmap dbserv1 webserv1

Starting Nmap 4.10 ( http://www.insecure.org/nmap/ ) at 2007-04-01 15:56 EDT Interesting ports on 192.168.40.11: Not shown: 1667 closed ports PORT    STATE    SERVICE 22/tcp  close     ssh 135/tcp filtered msrpc 136/tcp filtered profile 137/tcp filtered netbios-ns 138/tcp filtered netbios-dgm 139/tcp filtered netbios-ssn 199/tcp open     smux 445/tcp filtered microsoft-ds 1720/tcp filtered H.323/Q.931 3306/tcp open    mysql 3389/tcp filtered ms-term-serv 5631/tcp filtered pcanywheredata

Interesting ports on webserv1 (192.168.30.11): Not shown: 1644 closed ports, 28 filtered ports PORT    STATE SERVICE 21/tcp  close  ftp 22/tcp  close  ssh 80/tcp  close  http 111/tcp close  rpcbind 199/tcp close  smux 443/tcp open  https 1008/tcp close ufsd

Nmap finished: 2 IP addresses (2 hosts up) scanned in 17.001 seconds

As you can see, my Web server exposes too many ports and my MySQL server has a weak firewall; I ran this scan from a DMZ, which has to go through the firewall to enter my network. Here we can see the power of :  I know I should switch my firewall to default deny and allow only the services needed through explicitly. identifies filtered ports by a lack of response; closed ports send a TCP packet with a RST flag when you try to open them, indicating the server received the packet and would have allowed you to connect to any service listening on that port.

A useful option on the command line to nmap is the "Verbose" switch. Including -v or -vv on the command line will increase the amount of output nmap generates.

bluefox@ice-ldap:~$ nmap -vv webserv1

Advanced target specification
allows you to use IP address targets for various sets and ranges based on a simple syntax.

 * - Specify from x-y.  will scan 192.168.0.1, 192.168.1.1, 192.168.0.2, and 192.168.1.2
 * - Replaced with . Your shell will probably emit a bunch of file names, so just use.
 * - Specify  and  .   will scan 192.168.0.1, 192.168.0.2, and 192.168.0.4. Further,   will scan the same set of hosts.
 * - Scan CIDR notated subnets.  operates as   for example.

You can combine these notations in any form you want. For example, if you wanted to scan a few subnets on 192.168.0.0/12, you could use. Usually you will not want to do anything this drastic, and can stick to a single host; however, if you need it, you should know how to do it. Remember,  maps networks, not just hosts. ? " Vs " ss1

Scanning ports

 * Switches:

Sometimes you don't need to know everything open on a host, sometimes you just want to make sure proFTPd and Apache are up and the SMTP server hasn't died, and see if SSH is listening. For these situations, you can specify ports to scan. Port specification can be manipulated in the same way as target specification, using the  and   notations.

Scanning ports including Service Version (-V)
Includes Service versions for scanned ports:
 * Switches:   and   (Service version)

Basic Network ping Scanning
Basic network ping scanning for discovering host responding to icmp requests (ping).
 * Switches:, previosly and now deprecated

Service Scans

 * Switches: ,

has the ability to do service scans and RPC grinding; in other words, it can tell you what high level protocol, application, version, version of libssl if the service supplies an [(SSL)] connection, etc., listens on a port instead of matching the port number to the common service. also uses an RPC grinder, which makes RPC connections to ports running an RPC service; typically a single RPC portmapper port tells you which ports run RPC, but if the firewall blocks that then  will find it itself.

Let's take a look first at a scan against the server behind me. This server provides a profoundly good example because I've configured it to let me poke holes in my college's firewall, and thus it looks really strange. A typical  scan comes out well enough:

bluefox@icebox:/home/shared/qemu$ nmap 192.168.1.40

Starting Nmap 4.20 ( http://insecure.org ) at 2007-04-03 20:58 EDT Interesting ports on 192.168.1.40: Not shown: 1688 closed ports PORT   STATE SERVICE 21/tcp close  ftp 22/tcp close  ssh 53/tcp filter  domain 80/tcp close  http 81/tcp close  hosts2-ns 139/tcp close netbios-ssn 389/tcp close ldap 443/tcp open https 445/tcp close microsoft-ds

Nmap finished: 1 IP address (1 host up) scanned in 0.971 seconds

The above shows FTP, DNS, hosts2-ns, HTTP/SSL, and Microsoft Directory Services (Active Directory). We can take a closer look with an  service scan using. The below output gives us something quite different.

bluefox@icebox:/home/shared/qemu$ nmap -sV 192.168.1.40

Starting Nmap 4.20 ( http://insecure.org ) at 2007-04-03 21:01 EDT Interesting ports on 192.168.1.40: Not shown: 1688 closed ports PORT   STATE SERVICE     VERSION 21/tcp open  ssh         OpenSSH 4.3p2 Debian 5ubuntu1 (protocol 2.0) 22/tcp open  ssh         OpenSSH 4.3p2 Debian 5ubuntu1 (protocol 2.0) 53/tcp open  ssh         OpenSSH 4.3p2 Debian 5ubuntu1 (protocol 2.0) 80/tcp open  http        Apache httpd 2.0.55 ((Ubuntu) PHP/5.1.6) 81/tcp open  http        Apache httpd 2.0.55 ((Ubuntu) PHP/5.1.6) 139/tcp open netbios-ssn Samba smbd 3.X (workgroup: MSHOME) 389/tcp open ldap        OpenLDAP 2.2.X 443/tcp open  ssh         OpenSSH 4.3p2 Debian 5ubuntu1 (protocol 2.0) 445/tcp open netbios-ssn Samba smbd 3.X (workgroup: MSHOME) Service Info: OS: Linux

Service detection performed. Please report any incorrect results at http://insecure.org/nmap/submit/. Nmap finished: 1 IP address (1 host up) scanned in 13.747 seconds

So it seems this server really has Apache serving http on two ports; OpenSSH serving over the FTP, DNS, and HTTPS ports; and Samba providing SMB connections. Further, we can see that the server uses SSH 2.0 protocol on OpenSSH 4.3p2 Debian 5ubuntu1, a native Ubuntu .deb rather than a custom build. We can guess with relative accuracy that this server runs Ubuntu, even without an OS scan; either that or the administrator really doesn't have a clue what he's doing, or has managed to change banners with a rewrite proxy to fool us.

Worth note, the  switch activates service scanning as well.

Advanced Port Scans
You can run many types of advanced port scans with. Aside from the standard  port scan,   requires root access to perform these advanced scans because it needs to create raw sockets and construct raw TCP/IP packets.

Using nmap with root (-A)
The  program obtains different information with and without root access. With root access,  can perform advanced TCP/IP scans; operating system detection; and MAC address identification.

First, let's check out a normal user utilizing  with the   option. activates operating system and service scanning, in the same way as. Operating system detection requires root access, so OS detection won't work at all. I've performed the below scan against a Linksys WRT54G wireless router.

bluefox@icebox:~$ nmap -A -p80,1 192.168.1.1

Starting Nmap 4.20 ( http://insecure.org ) at 2007-04-04 12:18 EDT Interesting ports on 192.168.1.1: PORT  STATE  SERVICE VERSION 1/tcp closed tcpmux 80/tcp open  http    Linksys wireless-G WAP http config (Name Icelink) Service Info: Device: WAP

Service detection performed. Please report any incorrect results at http://insecure.org/nmap/submit/. Nmap finished: 1 IP address (1 host up) scanned in 6.199 seconds

As you can see,  simply skips the OS detection phase. When we put  into operation as root, however, we see that it can also look up a lot more information. Below, we see it discovered the MAC address and identified the vendor owning that MAC space; the operating system and details about the OS; the uptime; and the network distance. It also gave us a device type;  sees a Linux OS used for desktops, wireless routers, or network storage, and thus classifies the device as either general purpose, WAP, or storage.

bluefox@icebox:~$ sudo nmap -A -p80,1 192.168.1.1

Starting Nmap 4.20 ( http://insecure.org ) at 2007-04-04 12:18 EDT Interesting ports on 192.168.1.1: PORT  STATE  SERVICE VERSION 1/tcp closed tcpmux 80/tcp open  http    Linksys wireless-G WAP http config (Name Icelink) MAC Address: 00:13:10:7D:06:C6 (Cisco-Linksys) Device type: general purpose|WAP|storage-misc Running: Linux 2.4.X, Linksys Linux 2.4.X, Asus Linux 2.4.X, Maxtor Linux 2.4.X OS details: Linux 2.4.20 - 2.4.32, Linux-based embedded device (Linksys WRT54GL WAP, Buffalo AirStation WLA-G54 WAP, Maxtor Shared Storage Drive, or Asus Wireless Storage Router) Uptime: 29.285 days (since Tue Mar 6 04:28:28 2007) Network Distance: 1 hop Service Info: Device: WAP

OS and Service detection performed. Please report any incorrect results at http://insecure.org/nmap/submit/. Nmap finished: 1 IP address (1 host up) scanned in 7.833 seconds

becomes much more powerful with root access; however, for security reasons you should not haphazardly give  the SUID permission. You can allow users to run  specifically via , but be aware that anything that allows a user to gain root access—SUID bits,  , etc.—represents a security risk.

Operating system detection

 * Switches:

The  switch enables   operating system detection. OS detection attempts to use characteristics of the target's TCP/IP stack to fingerprint the remote operating system; usually it can identify Linux, Windows, and BSD, and find a general range of versions and families like Windows NT/XP or 95/98/ME. A typical OS Detection scan looks like the below.

bluefox@ice-ldap:~$ sudo nmap -O 192.168.1.105 -P0

Starting Nmap 4.10 ( http://www.insecure.org/nmap/ ) at 2007-04-05 18:43 EDT Warning: OS detection will be MUCH less reliable because we did not find at least 1 open and 1 closed TCP port Interesting ports on 192.168.1.105: Not shown: 1677 filtered ports PORT   STATE SERVICE 139/tcp open netbios-ssn 445/tcp open microsoft-ds MAC Address: 00:0C:76:96:A5:DC (Micro-star International CO.) Device type: general purpose Running: Microsoft Windows NT/2K/XP OS details: Microsoft Windows XP SP2

Nmap finished: 1 IP address (1 host up) scanned in 32.272 seconds

TCP connect Scan

 * Switches:

allows a TCP connect scan in all cases, administrative access or not; when you specify other scan types without root access,  automatically substitutes this scan type.

In this scanning mode,  opens a connection to the port in the same way a Web browser or FTP client does and checks to see how the TCP/IP stack responds. The following results arise from this scan:

 * open:   was able to complete a connection, and then closed the port.
 * closed:   tried to connect and got an error informing it that the port was closed (the OS got a RST packet).
 * filtered:   tried to connect and the OS gave it some other error, like host or port unreachable or connection time-out.

TCP connect scans work with all privilege levels, but can execute slowly and produce excess packets. They also usually create more logs on the target, and can crash really poorly programmed services.

TCP SYN Scan

 * Switches:

The  TCP SYN scan uses a simple SYN packet to connect to a port to determine its status. uses this by default whenever it has raw socket privileges.

The TCP SYN scan sends a SYN packet as if opening a connection, and checks the result. The following statuses come from this test:

 * open:   got a SYN/ACK from the host on that port.    does not have to take further action; the OS has no record of the connection, and responds to the SYN/ACK with a RST, tearing down the connection on the target.
 * closed:   got a RST from the host on that port.
 * filtered:   got something else, or nothing.

TCP SYN scans execute very quickly, create fewer logs, and act in a more stealthy manner.

Scanning Firewalls
You can use  to penetrate firewalls as well. can perform scans useful for determining whether a firewall uses stateful filtering or not; and which ports a firewall allows through. You can scan targets behind the firewall with this and discover the firewall rules, allowing more targeted scans and possibly evading firewall logging.

TCP ACK Scan

 * Switches:

Stealth Scans
Unfortunately, if you scan through certain IPS or IDS machines, you get loads of fluff from proxy ports. This presents a minor annoyance. I had to trim below output, as it contained thousands of lines of text. I've obscured the host I scanned below; I had chosen a live machine on the Internet to scan for this, because I don't have the IPS hardware they use.

Starting Nmap 4.10 ( http://www.insecure.org/nmap/ ) at 2007-04-01 16:14 EDT Stats: 0:00:02 elapsed; 0 hosts completed (1 up), 1 undergoing Connect Scan Connect Scan Timing: About 20.95% done; ETC: 16:14 (0:00:09 remaining) Interesting ports on %%% (%%%): Not shown: 861 closed ports PORT     STATE    SERVICE 2/tcp    open     compressnet 3/tcp    open     compressnet 7/tcp    open     echo 10/tcp   open     unknown 12/tcp   open     unknown 14/tcp   open     unknown 15/tcp   open     netstat 18/tcp   open     msp 19/tcp   open     chargen 20/tcp   open     ftp-data 21/tcp   open     ftp 25/tcp   open     smtp 27/tcp   open     nsw-fe 28/tcp   open     unknown 29/tcp   open     msg-icp 30/tcp   open     unknown 31/tcp   open     msg-auth 32/tcp   open     unknown 33/tcp   open     dsp 34/tcp   open     unknown 35/tcp   open     priv-print 38/tcp   open     rap 39/tcp   open     rlp 40/tcp   open     unknown 41/tcp   open     graphics 43/tcp   open     whois 47/tcp   open     ni-ftp 56/tcp   open     xns-auth 58/tcp   open     xns-mail 59/tcp   open     priv-file 60/tcp   open     unknown 64/tcp   open     covia 66/tcp   open     sql*net ..... 134/tcp  open     ingres-net 135/tcp  filtered msrpc 136/tcp  filtered profile 137/tcp  filtered netbios-ns 138/tcp  filtered netbios-dgm 139/tcp  filtered netbios-ssn 141/tcp  open     emfis-cntl 143/tcp  open     imap 145/tcp  open     uaac 147/tcp  open     iso-ip 148/tcp  open     cronus 149/tcp  open     aed-512 150/tcp  open     sql-net 155/tcp  open     netsc-dev ..... 27001/tcp open    flexlm1 27002/tcp open    flexlm2 27005/tcp open    flexlm5 27007/tcp open    flexlm7 27008/tcp open    flexlm8 27009/tcp open    flexlm9 27010/tcp open    flexlm10 27374/tcp open    subseven 27665/tcp open    Trinoo_Master 31337/tcp filtered Elite 32775/tcp open    sometimes-rpc13 32777/tcp open    sometimes-rpc17 32779/tcp open    sometimes-rpc21 32787/tcp open    sometimes-rpc27 38037/tcp open    landesk-cba 43188/tcp open    reachout 47557/tcp open    dbbrowse 50000/tcp open    iiimsf 54320/tcp open    bo2k 61441/tcp open    netprowler-sensor 65301/tcp open    pcanywhere

Nmap finished: 1 IP address (1 host up) scanned in 23.251 seconds

Fortunately, you can perform a stealth scan to evade this; unfortunately, stealth scans take an order of magnitude longer. Usually a polite scan will do the trick, it causes only 150 packets/minute.

The  option takes one of five arguments, given by name or number. These are:

 * (0) - No parallel scanning. 5 minutes between sending packets.
 * (1) - No parallel scanning. 15 seconds between sending packets.
 * (2) - No parallel scanning. 0.4 seconds between sending packets.
 * (3) - Default scanning. Tries to be very fast without overloading the network.
 * (4) - Faster than normal, but loads the network.
 * (5) - Parallel scans, times out hosts in 15 minutes, won't wait more than 0.3 seconds for an individual probe. Loses a lot of information.

also provides options to control scan time-outs. Combining these with the above provides more fine-tuned scans, for example a scan doing 100 packets per minute:

Let's try the above scan again, politely.

bluefox@icebox:~$ nmap -T polite

Starting Nmap 4.20 ( http://insecure.org ) at 2007-04-02 19:52 EDT Interesting ports on %%% (%%%): Not shown: 1658 closed ports, 26 filtered ports PORT    STATE SERVICE 21/tcp  open  ftp 25/tcp  open  smtp 80/tcp  open  http 110/tcp open  pop3 143/tcp open  imap 389/tcp open  ldap 443/tcp open  https 1026/tcp open LSA-or-nterm 1027/tcp open IIS 1433/tcp open ms-sql-s 3389/tcp open ms-term-serv 8000/tcp open http-alt 9999/tcp open abyss

Nmap finished: 1 IP address (1 host up) scanned in 693.146 seconds

As we can see, this scan takes 693 seconds instead of 23, 30 times longer.

title: Hacking/Tools/Network/Nmap


text:
User talk:164.58.2.206

Please stop adding nonsense to Wikibooks. It is considered vandalism. If you would like to experiment, use the sandbox. Thank you. -- Herby talk thyme 16:41, 4 April 2007 (UTC)

Blocked - improve your behavior please -- Herby talk thyme 16:43, 4 April 2007 (UTC)

title: User talk:164.58.2.206


text:
Portuguese/Contents/L1/Lesson Ten - My House

Let's take a look at the conjugations for the verb TER.

TER - To Have

de:Portugiesisch: Lektionen: Mein Haus


text:
User talk:Dpr~enwikibooks

Hello, thanks for your message about the Persian language wikibook :)

Unfortunately my level of written Persian is poor and also I found when editing the font is very tiny so I didn't notice what I typed was wrong, so thank you for your help in pointing out the mistakes. In answer to your question "furniture" is pronounced "asas". "Chera" was also definitely spelled wrong, and I am just trying to correct the other misspellings now.

I am also interested in whether people think it is better to begin lessons in transcription and then gradually add the alphabet, or begin by introducing the whole alpahabet right at the beginning? I will open this topic on the talk page of the Persian/Contents.

It would be great if you might be interested in editing the book as well, and I am hoping to contact some Persian-speaking editors from Wikipedia to help. Poppy 19:19, 4 April 2007 (UTC)

Your account will be renamed
Hello,

The developer team at Wikimedia is making some changes to how accounts work, as part of our on-going efforts to provide new and better tools for our users like cross-wiki notifications. These changes will mean you have the same account name everywhere. This will let us give you new features that will help you edit and discuss better, and allow more flexible user permissions for tools. One of the side-effects of this is that user accounts will now have to be unique across all 900 Wikimedia wikis. See the announcement for more information.

Unfortunately, your account clashes with another account also called Dpr. To make sure that both of you can use all Wikimedia projects in future, we have reserved the name Dpr~enwikibooks that only you will have. If you like it, you don't have to do anything. If you do not like it, you can pick out a different name.

Your account will still work as before, and you will be credited for all your edits made so far, but you will have to use the new account name when you log in.

Sorry for the inconvenience.

Yours, Keegan Peterzell Community Liaison, Wikimedia Foundation 23:10, 17 March 2015 (UTC)

Renamed
 This account has been renamed as part of single-user login finalisation. If you own this account you can |log in using your previous username and password for more information. If you do not like this account's new name, you can choose your own using this form after logging in: . -- Keegan (WMF) (talk) 04:54, 19 April 2015 (UTC)

title: User talk:Dpr~enwikibooks


text:
Talk:Persian/Contents

Text Moved From Persian
The Contents page was moved here from Persian so some relevant discussion might be found at that talk page. Poppy 19:23, 4 April 2007 (UTC)

Transcription or Persian alphabet
Is it better to begin lessons in transcription and introduce the alphabet later or to begin with the alphabet and work from there? Poppy 19:23, 4 April 2007 (UTC)

Some encouragement
As someone trying to self-learn Persian, I've been happy to see any progress at all on the website. For anyone with knowledge of Persian, thanks for your contributions so far, and please keep it up!

title: Talk:Persian/Contents


text:
WebObjects/Development Tools/Running Through Apache

If you are accessing your application with URLs that look like http://localhost:45437/cgi-bin/WebObjects/AppName.woa/ (with the xxx:portnum instead of xxxx/-portnum) ... then you are using the Evil Direct Connect. See that page for why you don't want to be using Direct Connect. See this page for how to stop.

Turn on Apache
Go to System Preferences -> Sharing -> Services and turn on Personal Web Sharing if it is not already on.

Edit Apache Config
Note: Do NOT try to use the Bonjour / Rendezvous name of your machine in this step. It will cause you grief. Accept this and don't even try. You have been warned.

Edit /etc/httpd/httpd.conf, find the line containing ServerName and change it to this: ServerName localhost

That line may be commented out by default. You can simply uncomment it (remove the leading pound sign) and then restart apache:

sudo apachectl restart

Tell wotaskd to Use Localhost Too
Edit /System/Library/WebObjects/JavaApplications/wotaskd.woa/Contents/Resources/Properties

Add this line after the WOPort=1085 one: WOHost=localhost Now you need to restart wotaskd: sudo systemstarter stop "WebObjects Services" sudo systemstarter start "WebObjects Services"

or

restart wotaskd and womonitor with launchctl if your WebObjects install launches that way.

Finally, Configure your Application
Add or edit these launch parameters: –WODirectConnectEnabled false -WOHost localhost -WOAdaptorURL http://localhost/cgi-bin/WebObjects –WOPort 5555 The WOPort is optional, but useful if you want consistent URLs for bookmarks and such. You can use any number you want, but it needs to be unique for each application you launch (or rather, you can only run one app instance on a given WOPort at a time). In WOLips, WOPort, WODirectConnectEnabled, and WOAdaptorURL already exist and just need to be updated. WOHost does not, and needs to be added. The dash in front of the name ("-WOHost") is important and must be in the name for the setting to work properly.

You may want to set this in your global WOLips settings so you don't have to set it every time you make a new launch configuration. You will need to go back and modify existing launch configurations with these settings even if you set it globally. Global settings only apply to newly created launch configurations.


text:
Hacking/Background knowledge/Computer architecture/6502 assembly

6502 assembly contains a grand total of 151 valid opcodes; we can ignore the 105 undefined opcodes that some sources reference. Because of this small set, 6502 assembly language allows us to quickly conjure hypothetical machines based on non-existent hardware, define memory mappings for this hardware, and then proceed to define simple programs for the hardware.

This page of the Hacking Wikibook takes advantage of this to submerge the reader deeper into the guts of a bare CPU; although other CPUs have different instruction sets, the core function of operating flags, registers, memory, and the stack remain the same. More advanced CPUs utilize protected memory; but even then, the function of delivering and handling a signal matches closely with the function of delivering and handling an interrupt.


text:
Latin/Lesson 2-Adjectives

=Adjectives=

Overview of Adjectives
An adjective is simply any word that describes a noun, such as an object or subject in a sentence. Of course, whole phrases may be used to describe nouns, but adjectives are individual words. In English, for example:

The red dog attacked the crazy fox.

An adjective can also be used in a sentence opposite a form of "to be." (called a predicate adjective)

The boy is good.

In Latin, the same is true.

Adjectives in Latin
Like nouns, adjectives in Latin are declined. The vast majority take either the first and second declension (antiquus -a -um) or the third declension (ferox, ferocis). All such adjectives must agree with the nouns they describe in gender, number, and case.

Most third declension adjectives do not have separate masculine and feminine forms. (Neuter adjectives follow the third declension neuter pattern.)

First and second declension adjectives have three distinct genders. Feminine adjectives require the first declension, masculine the second (masculine pattern), and neuter the second (neuter pattern).

These words will look like the adjective antiquus (old, ancient):
 * antiquus (masculine), antiqua (feminine), antiquum (neuter).

Third declension adjectives typically look more like ferox, ferocis (wild, bold).

Adjectives often come after the word they describe. Since word order is not central to the meaning of a Latin sentence the adjective may appear anywhere within the sentence. In poetry, for example, several words often separate an adjective from the noun it modifies.

For example:

 * (1) amāre, [to] love. amat, [he] loves.
 * (2) canis, dog (masc.)
 * (3) ferox, ferocis, wild. ferocem (acc.)

Bonus, a first and second declension adjective, is masculine, nominative, and singular to agree with puer, the word it is describing.

Ferocem, a third declension adjective, is masculine, accusative, and singular to agree with canem. Canem is accusative because it is the object of amat.

Here is an example of plural adjectives:

The words bonus and ferocem become boni and feroces to agree with the plurals pueri and canes.

However, if a girl (puella) happened to love that boy:

Bonus must become bona in order to modify puella, which is feminine.

Finally, if the girl isn't good, but rather wild:

Even though puella is first declension, ferox remains third declension. In the same way, a good lion would be bonus leo.

Adjectives must agree in gender, number, and case, but not necessarily in declension.

The Positive, Comparative, and Superlative Adjectives
The positive form of the adjective is the plain form of the adjective (e.g. good), the comparative form is used to compare two things (e.g. better), and the superlative form is used to compare more than two things (e.g. best).

To make most Latin adjectives comparative you add -ior to the adjective. To translate back into English you would say either the adjective -er (e.g. taller) or more the adjective (e.g. more tall). To form the superlative you add -issmus. This translates to either the adjective -est (e.g. strongest) or most the adjective (e.g. most strong).

However not all adjectives follow this rule; the following are irregular adjectives and their English translations:

title: Latin/Lesson 2-Adjectives


text:
Uzbek/Lesson Two

 << Previous Lesson - Index - Next Lesson >>

This lesson is divided up into several sections. After your done you'll be ready to have your very first conversation in Uzbek. Sure, it'll be real simple—but you'll know how to greet somebody, introduce yourself, ask some polite questions, and say goodbye. If you want to do it intensive (which I'd recommend) you can do this all as one lesson. If you don't have much time the dialogues are broken up into four sections—just do one. (Eventually I think we'll merge all four tiny dialogues)

Cultural Notes
For many years Soviet histories portrayed Central Asia as a backward area with no tradition of scholarship and learning. In fact, education in the region was widespread and well developed long before the nineteenth century Russian conquest. There existed a large network of "old style" primary (maktab) and higher (madrasa) schools, which taught religious subjects. In those days many children studied at maktabs in their own neighborhoods. Some continued their studies for another ten years at a madrasa.

After the Russian conquest, the tsarist administration established schools with instruction in Russian for the indigenous nationalities. These trained a small number of Central Asians to serve the tsarist administration. Around the turn of the century, reform minded local intelligentsia called iadids opened "new style" schools (usul-i jadid). Unlike the "old style" schools, the jadid schools taught secular subjects.

Both the "old style" and the "new style" schools disappeared in the 1920s. Today Uzbekistan has educational institutions developed after the Soviet model, including primary and secondary schools, specialized technical schools, and institutes and universities. . . '''--The rest of the information from the peace corps manual is dated. Any important cultural fact about education can go here--'''

For Dialogue 1
In Uzbek the infinitive is formed by adding the suffix -moq to the verbal stem:

Without the infinitive or any other suffix, the Uzbek verbal stem is identical to the second person singular or imperative which is used in familiar or sometimes impolite situations:

To express the imperative for singular and plural in a polite manner, the suffix -ing is added to a verbal stem ending in a consonant. The suffix -ng is added to a stem ending in a vowel:

In the sentence gapni yozing the suffix -ni indicates the accusative case and expresses the idea of a definite quality. It is equivalent to English 'the':

Pronunciation Notes
Pronounce the letters ng as one sound as in the American English ng in the word song, and not as two sounds n and g as in English 'in good standing'.

Imperative sentences are pronounced in Uzbek with a falling intonation on the last syllable:

For Dialogue 2
The negative of a verb is formed by adding the suffix -ma to the stem of the verb before adding any of the tense or person suffixes:

The word tushunmayman is a negative verb in the present-future tense and can mean 'I do not understand' or 'I will not understand.' It is formed by adding the suffix -i to the negative form of the verb:

As in English, an adjective always stands before the noun it qualifies:

Aytishingiz mumkin (you can say) consists of a verbal noun aytishingiz (your saying) and a verbal predicate mumkin (it is possible).

The expression Sogʻ boʻling! (Be healthy) is used by Uzbeks to wish each other well when saying goodbye.

For Dialogue 3
The locative case suffix -da is attached to nouns and has the meaning of 'at,' 'in,' 'on':

The verbal forms of oʻqidim (I read), qildingiz (you did) etc. .. contain the definite past tense suffix -di. This suffix is added to the verb stem and indicates in a factual manner that an action was completed in the recent past:

Sentence Patterns
When a word needs to be emphasized, it is usually placed immediately before the predicate:

Recap
Congratulations! You can now have your first ever conversation in Uzbek--and that wasn't that hard either? Was it?

In future editions of this book we might have exercises and such, so that you can practice what you learned, and really get it to soak in--and also so you can double check and make sure you know it. But they aren't available just yet :)

 << Previous Lesson - Index - Next Lesson >>

title: Uzbek/Lesson Two


text: Template:Persian/Large Text

title: Template:Persian/Large Text


text:
Wikijunior talk:What can you use math for?/Video Games

To-do

 * Create more eye-pleasing format
 * Add pictures


text:
Latin/Lesson 1-Imperative

=Imperative=

English
In English (and in Latin), the positive imperative is a command. For example:

 * Just Do it!
 * Stop, hammer time!
 * Take me out to the ballgame!

Latin
In Latin, the imperative singular is found by taking the last two letters off of the infinitive. The six exceptions to this rule are dicere (dic), ducere (duc), facere (fac), velle, malle (infinitives not used) and nolle (noli). Ferre (fer) and esse (es) are often considered irregular due to the lack of a vowel at the end but we can see that applying the rule of removing the last two letters forms the imperatives correctly.

Examples:
Run, boy!
 * Curre, puer! (from curro, currere; to run)

Go!
 * I! (from eo, ire; to go)

Questions
Write out:

 * 1) Love me, Octavia! (to love = amo, amare)
 * 2) Come to Rome! (to come = venio, venire; Rome = Roma, Romae, f.)

Plural
To form the plural imperative in Latin, take the 2nd person plural present form of the verb (eg. amatis, sedetis, regitis, venitis) and replace the is at the end with e. The only exceptions to the rule are velle, malle (imperatives not used) and nolle (nolite). Ferre (ferte) and esse (este) are often considered irregular but applying the rule (fertis -> ferte, estis -> este) correctly forms the imperatives.

Go home, boys!
 * Ite domum, pueri.

Stay, all of you!
 * Manete, omnes!

Exercises
Write out:

 * 1) Take them, men! (to take = adripio, adripere)
 * 2) Fear me, children! (to fear = timeo, timere; children = liberi)

English
In English, we use the word "don't" for prohibitions, or negative imperatives. For example:
 * Don't do it!
 * Don't say that!

Latin
Similarly, in Latin the negative imperative is formed with two words, the imperative of nolo, nolle and the infinitive.

Nolo by itself means "I do not want," but in its imperative it means "do not...!" Some teachers of Latin point out that literally you are saying "Be unwilling to ..." - a very polite way of giving an order!

Nolle is irregular, and its imperative forms are noli and nolite.

Examples
Do not fear me!
 * Noli me timere!

Don't build the aqueduct there, soldiers!
 * Nolite aquaeductum ibi aedificare, milites!

Don't wash the dog, boys!
 * Nolite, pueri, canem lavare!

title: Latin/Lesson 1-Imperative