text:
Circuit Idea/Philosophy

<<< discussion - contribution - page stage >>>

Philosophy behind the Book

Imagination is more important than knowledge...  Albert Einstein

The classical approach

As a rule, classic electronics courses follow a traditional "scenario": first, authors present electronic circuits in their complete, final and perfect form; then, authors analyze accurately circuits by using abstract formal methods. This classical teaching approach predominates in electronics education. Just look around and you will see that it is everywhere: in books, magazines and web sites authors present ready-made circuit solutions; in lecture halls teachers try to explain qualitative circuit phenomena by using quantitative tools; in educational laboratories, students carry out "ascertaining" experiments that only confirm the rightness of predominating circuit ideas.

Ultimately, there is no place for revealing basic circuit ideas. Nobody shows what we, human beings, actually need - what basic circuit ideas are, where new circuit ideas come from and how they have been evolving through years, in order to be able not only to understand but even to invent new circuits. In this way, relying mainly on logical reasoning, education suppresses the most human capability that we possess owing to our imagination - to create and even invent things, which do not exist in nature. Thus education does not induce creativity in student minds.

For example, nobody shows us the relation between the passive and active versions of same circuits. First, they present passive electric circuits (e.g., the passive RC integrator in the upper figure on the right) as ready-made circuit solutions and persuade us how imperfect they are. Then, they give us active electronic circuits (e.g., the op-amp inverting RC integrator in the lower figure) and persuade us now how perfect they are. Only, although they present passive and active versions separately, we guess that they are related. So, nobody shows us what we actually need - how to transform imperfect passive circuits into almost ideal active electronic circuits. If we only know how, we will be able to understand and even invent more new electronic circuits!

A need of human-friendly circuit philosophy

Only, we are not robots or computers but ordinary human beings; no cold engine oil but warm human blood flows in our veins. When еxamining complicated mixtures of electronic components we try to discern desperately simpler circuit building blocks and to associate the abstract circuit idea with well-known everyday situations. For example, we might think that the popular circuit of an op-amp inverting amplifier is composed of two simpler converters: a passive voltage-to-current converter and an active current-to-voltage converter unified by the famous virtual ground phenomenon.

We human beings, do not think in terms of formal analysis when understanding, explaining and inventing circuits. We need first to understand qualitative things by qualitative means; then, to compute quantitative things by quantitative means. In electronics, that means first to understand, build and invent circuits by using human intuition, imagination and emotions; then, to define exactly the circuit parameters and to analyze thoroughly the circuit operation by using formal methods.

We need not only concrete technical explanations and calculations. First of all, we, human beings, need a human-friendly circuit philosophy.

Philosophy foundations
In this wikibook, we establish a novel circuit philosophy as an alternative to the classical formal approach. The new philosophy relies more on human imagination than on logical reasoning. It considers analog circuitry more as art than science and the creation of electronic circuits as a result of human fantasy, imagination and enthusiasm.

Reinventing electronic circuits
The best way of understanding and presenting unfamiliar circuits is to "invent" them again (reinvent). So, instead of presenting circuits as finished cut-and-dried solutions we may reinvent them including the very students in this "game". In this way, reproducing the inventing process, we can show the evolution of circuit ideas. This helps students to master a set of circuit design techniques and tricks, which enables them later to construct and... why not to invent new circuits?

Levels of implementation
In this book, we evolve the heuristic idea at three levels:
 * At a book level, we reveal circuit ideas generally by moving in a sequence passive > active > negative feedback circuits (see the main subtitles of the content's section Revealing circuit ideas).
 * At a page level, we expound the subject step-by-step by moving from simple to complex - imperfect to perfect, passive to active, transistor to op-amp circuits (see, for example, current-to-voltage converter)
 * At every step inside a story, we first reveal the basic circuit idea; then we show the concrete circuit solution.

A reinventing scenario
When we reinvent a circuit, we move from the beginning to end. Here is such a typical top-down scenario:

1. Posing the problem to be solved (improving a passive circuit, solving a circuit contradiction, etc.)

2. Revealing the basic idea in the non-electrical domain (looking for analogies, deriving a block-diagram and operation algorithm).

3. Applying the general idea in the electricity domain (building an equivalent and "man-controlled" electrical circuit).

4. Showing the passive circuit applications (building standalone and composite passive devices).

5. Revealing the passive circuit imperfections (revealing and evaluating inherent circuit deficiencies).

6. Improving the imperfect passive circuit and creating a perfect active version (converting the passive circuit into an active one).

7. Applying the idea in the electronics domain (building various active devices based on the same idea).

Typical examples of this top-down reinventing approach are the stories about passive and active voltage-to-current converter that we have derived from the elementary Ohm's electric circuit.

A building approach
Circuit idea is based on the belief that the truth about circuit phenomena is hidden rather in the movement from simple to complex circuits than in the final perfect circuit solutions. That is why, we do not present here circuits as ready-made solutions to be analyzed in their complete, final and perfect form. Instead, we build circuits step-by-step using more elementary building blocks that are already "invented". We connect these "bricks" according to the basic ideas that we have derived from real life.

Following this building approach, in the present book we present every new more complex circuit as based on the previous simpler one. First, we derive the most elementary passive building blocks from the basic electric circuits of Ohm, Kirchoff, Thevenin and Norton. Then, we use these "cubes" to build more complicated compound passive circuits. Further, adding active elements in accordance with suitable basic ideas, we build various transistor circuits. Finally, applying powerful negative feedback principle in all its variety, we metamorphose these circuits into almost ideal op-amp ones.

An example of this bottom-up building approach is the story about parallel voltage summer that evolves as follows. In the initial stories, we derive the elementary voltage-to-current converter, current-to-voltage converter and current summer. In the next story, we use them to build a compound passive voltage summer. Finally, we add an op-amp to this passive circuit thus converting it into an active parallel voltage summer.

Using associations
We begin learning from the day we are born. In this way, in the early years of our childhood, we accumulate a knowledge of life for visible (mechanical, hydraulic, pneumatic, social, etc.) phenomena of our world. But this world is arranged so interesting that apparently different phenomena obey the same laws; they are analogous.

Then, why do not we use associations as educational mainstays that convey the common knowledge about visible worldly phenomena to invisible abstract electric phenomena? Thus they will look familiar, elementary and accessible. This is so because we, human beings, begin understanding new unfamiliar things when we begin discerning something familiar inside them. We just consider new complex things as composed by a few simpler well-known components. Here are some examples of applying analogies.

When we "reinvent" the elementary electric circuits (voltage-to-current converter, current-to-voltage converter, etc.) and more complex electronic circuits (e.g., the op-amp inverting integrator on the right, Deboo integrator, etc.) we use various fluid analogies (pneumatic, hydraulic, thermal, diffusion, etc.) When we try to figure out what blocking capacitors really do in an AC transistor amplifying circuit, we will think of them as an electrical "shock-absorbers", which move the voltage "movements" (see the welcome circuit diagram at the top). Later, we will derive the simplest block diagram of a negative feedback system by using various driver, teacher, weight, economic, social, etc. analogies.

Visualization

According to the old proverb "A picture is worth a thousand words", we have to place as much as possible images in this book. When this is not possible, we will use an imaginative, figurative and colorful language to plot pictures in reader's mind.

Also, we can visualize the invisible electrical attributes voltage and current by analogous geometrical attributes bars and loops that are based on the famous water tower and fish tank hydraulic analogies. In this geometrical presentation, the height of the voltage bars is proportional to the corresponding voltages and the thickness of the current loop is proportional to the magnitude of the current.

Finally, we can present the circuit operation by a voltage diagram that represents the voltage distribution along a resistive film. In this attractive geometrical presentation, local bars with corresponding height represent the local voltage drops. For simplicity, we usually draw only the envelope of the voltage diagram.

Relying on causality
Revealing causality. Classical electronics courses do not reveal cause and effect relations in electronic circuits. For example, who cares if there is a causality and what causes what (what quantity is an input and what an output) in Ohm's law? Authors just suppose that voltage and current change simultaneously; they do not mind how the famous rule is written (I = V/R, V = I.R or R = V/I).

Only, we human beings consider every change in this world as a result of some cause (in electronics that means the output quantity is a result of the input one). We cannot imagine that the input and output quantities can change simultaneously. We know that always the input is first and the output is second; so, the output always follows (delays) the input.

Introducing causality. In the case when apparently there is no causality in electronic circuits, we can introduce it. Let's for concreteness consider the example above of Ohm's law. There, we first assume that voltage causes current (I = V/R) in a voltage supplied Ohm's circuit; thus we "invent" the simplest voltage-to-current converter.

Changing causality. But we know that this cause and effect relation is an arbitrary choice; so, we can change (reverse) it. This means we can assume with the same success that current causes voltage (V = I.R) in a current supplied Ohm's circuit; thus we "invent" the reverse current-to-voltage converter.

Evolving this powerful idea we will (re)invent a lot of useful and original circuits by using any accessible circuit points (including circuit outputs, supply terminals, etc.) and component parameters as an input. For example, varying with resistance as an input quantity we will obtain a resistance-to-current converter (in the case of a voltage supplied Ohm's circuit) and a resistance-to-voltage converter (in the case of a current supplied Ohm's circuit). Then, applying an input voltage to the output of an emitter follower we will "invent" the odd common-base transistor amplifying stage. Later, changing causality, we will transmute a digital-to-analog converter into a digital controlled amplifier.

Applying sensomotor activities
In order to "feel" how electronic circuits operate, we have to interact with them: first, to stimulate them and then, to perceive their reactions. Of course, the best way of doing that are real and simulated laboratory experiments. In this book, we will also carry out mental experiments to establish sensomotor notions into readers.

For example, when we explore the popular common-emitter transistor amplifying stage, we "raise" and "lower" mentally the base voltage. Then, when we "experiment" with the odd common-base stage, we apply an input voltage to the emitter and then "wiggle" it. Similarly, when we explore the classic differential transistor amplifier, we "move" (in the same and in the contrary directions) the both input voltages to observe the differential and common-mode operation.

A more sophisticated example is the ECL gate visualized by voltage bars and current loops:

A functional consideration
We may consider electronic components at various levels of abstraction. For example, we might explain how a transistor works at "micro level" presenting it in terms of semiconductor theory. Only that is not sufficient to explain how a particular electronic circuit works. In order to understand transistor circuits, we need to know not so much what the internal transistor structure is but how a transistor behaves in the circuit.

At this "macro level", we present the transistor operation by the well-known basic concepts of electricity (current source, non-linear resistor, current-to-current converter, rheostat, etc.). Thinking "functionally", we imagine where currents (not particular electrons or holes) flow, what voltages and resistances across the component terminals are, etc.

Evolving this functional approach, we will implement electronic circuits at various component levels. For example, we will present a voltage amplifier at these levels: single transistor amplifier, discrete transistor amplifier (built by a few transistors), integrated circuit amplifier (e.g., a single op-amp), negative feedback amplifier (here the op-amp is only a component of a system), an electronic device (now the negative feedback amplifier is only a component), etc.

Putting emotions to work
As you can see, in this book circuitry manifests more as an art than a science. Figuratively speaking, the book is a peculiar "theatre" where the particular circuit stories are "scenes", on which electronic circuits "play" our "scenarios":)

Emotions lie at the root of the art. We are human beings that possess emotions; we can feel, excite, love, hate, embarrass, suffer, envy, imagine, dream... but we cannot function blindly as a Turing machine when analyze circuits!

So, in this book, we will love our circuits... will get excited before their "premieres"... will suffer when they fail... and will triumph when a new circuit idea conceives in our minds!

External web resources
Build to understand circuits is the intro of a web based multimedia tutorial (Flash player needed) designed for Poptronics in 2003 (see also a paper).

Web-based building course on analog electronics - a teacher's story about implementing the philosophy.

Op-amp inverting summer is an animated tutorial (Flash player needed) that shows another implementation of the philosophy.

<<< top - discussion - contribution  - page stage  >>>

title: Circuit Idea/Philosophy


text:
User talk:60.53.57.41

Thanks for experimenting with Wikibooks. Your test worked, and has now been removed. Please use Sandbox for any other tests you want to do, since testing material in modules will normally be removed quickly. Please see the welcome page if you would like to learn more about contributing to our project. Thanks. -- Herby talk thyme 07:03, 31 May 2007 (UTC)

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: User talk:60.53.57.41


text:
User talk:Mike6271

Hello, welcome to Wikibooks!

You will find more resources in Community Portal. If you want to ask a question, visit the Study help desk, the Staff lounge, IRC channel or ask me personally on my talk page. For site news, see the Bulletin board. It might be a good idea to add this page to your "watchlist" so that you can see when any new information is posted there. You can do that by clicking the tab labeled "watch" at the top of the page.

Good luck! -- Herby talk thyme 07:05, 31 May 2007 (UTC)

First Aid contributions
Thanks for your help with the First Aid wikibook! The book's content is sadly lacking in some places and I don't have lots of time to give away for free, so keep it up. Mike.lifeguard 20:51, 31 May 2007 (UTC)
 * No problem! I will try to contribute whatever I can to make it better.  I'm still in school for a few more weeks, but after that I will be able to contribute more.  Sometime this summer I *might* be able to try to get some pictures to help to describe some treatments and illnesses/injuries.  Thank you for all of your contributions to the First Aid wikibook! Mike6271 23:05, 31 May 2007 (UTC)
 * I see you used one of those pics. I don't think that discussion actually does involve country-specific terminology, so I removed your edit. Please feel free to contribute to the discussion by adding comments at the bottom. I think some templates to make better use of those icons is a great idea. Suggestions for what those images should mean??  – Mike.lifeguard | talk 02:14, 6 July 2007 (UTC)
 * I like pretty much all of them. Maybe remove the bomb and just use the red X as a "never do this!" The clock one might be confusing...maybe a timer would be better?  I'm not really sure what you can use the lightning bolt for.  Mike6271 02:22, 6 July 2007 (UTC)
 * Take a look again.  – Mike.lifeguard | talk 02:30, 6 July 2007 (UTC)
 * They are a lot better! Good job finding them! Mike6271 02:36, 6 July 2007 (UTC)

No can do; no AIM. This'll work.  – Mike.lifeguard | talk 02:40, 6 July 2007 (UTC)
 * reset
 * Okey dokey. Anything you want me to work on in particular?  Maybe try to find spelling mistakes (I love firefox!) Mike6271 02:41, 6 July 2007 (UTC)

 * Actually there's plenty to do. Spelling is good too (I love firefox too!) Or you can try to do some of those templates. Template:FA Regional Note is already done, so have a look-see:

 *  – Mike.lifeguard | talk 02:55, 6 July 2007 (UTC)
 * I like the template...it looks really good. Also, plenty to do doesn't work :( Mike6271 02:58, 6 July 2007 (UTC)
 * Sorry. Fixed above links  – Mike.lifeguard | talk 03:02, 6 July 2007 (UTC)
 * Thanks! I will start working on them :). Mike6271 03:03, 6 July 2007 (UTC)

Attempt at consensus on this issue requires your input
I've requested an attempt at consensus here on the victim/patient/casualty terminology issue.  – Mike.lifeguard  | talk 00:32, 10 July 2007 (UTC)

What needs work? update
I just wanted you to know that I've updated First Aid/What needs to be done? page, and added a section for active discussions. Please feel free to weigh in on any of those topics on the appropriate talk page. Thanks!  – Mike.lifeguard  | talk 18:51, 17 July 2007 (UTC)

I replied to your comments on Talk:First Aid/Marine First Aid. You may want to voice an opinion at WB:FBN; I have nominated First Aid to be a featured book. Thanks for all your help in bringing it to where it is today! – Mike.lifeguard  | talk 02:53, 12 November 2007 (UTC)

"Assist with medication"
Wherever it says to assist with medication (or similar) it doesn't mean to administer it. It means to do things like None of those things are actually administering the medication; the victim must do that themselves. This should probably be explained in some central location towards the beginning of the book (Issues in Providing Care?) and linked to whenever that phrase is used. Your thoughts? – Mike.lifeguard  | talk 06:02, 12 November 2007 (UTC)
 * read the label to make sure they take the right dosage
 * help them take the lid off of pill bottles
 * find it in a purse or something
 * Ah, ok, I see what you mean. Yeah, that's a good idea, since "assist" could be interpreted as actually assist in administering it, such as an EMT-B would do with an inhaler.  Should we put it somewhere under legal liability or create a new page for assisting with medications and how to assist, etc? Mike6271 11:36, 12 November 2007 (UTC)
 * I'd say a section in Liability should be good. As long as it can't be misconstrued as you just described I'll be happy. It also needs to come before the first mention of assisting with medication.
 * Lately I feel like I'm saying "yes that'd be good" and such, but not contributing much myself. I'm planning on putting in some work over the winter break, including the section on spinal injury assessment in First Aid/Extended Assessment.
 * Out of curiosity, where are you getting the images you've been adding? I assume they're from Commons. Last time I checked, there weren't many good first aid (etc) images there (or at least they were poorly categorized). – Mike.lifeguard  | talk 03:49, 13 November 2007 (UTC)
 * Ok, I will put it in liability, maybe today.
 * Eh, I got the pictures from around. I will be a judge at this one Boy Scout first aid meet tomorrow...I might be able to get some pictures there...if any turn out especially good with the treatment, I could probably use them on here.  It is nice to have pictures, so I will try to get some more.  Thanks! Mike6271 11:38, 13 November 2007 (UTC)

title: User talk:Mike6271


text:
Blender 3D: Noob to Pro/Fireworks

[Note: In newer versions of Blender, the reactor particles are gone.]

[if you use 2.6x version of blender, then you could watch the YouTube video {particles from particles part1/2}. It's a great tutorial, but the part 2 of it uses compositing, which is described in this book a little later. Therefore, you could apply the knowledge you have learnt from this book to animate the explosions!]

How to create a firework from particles? We will use cascaded particle systems especially of the type Reactor. Abstract:
 * We create a emitter object in the appropriate size.
 * Than we use three successive particle systems:
 * the first of the type Emitter
 * the second of the type Reactor. This system reacts to the death of the emitter particles.
 * the third again of the type Reactor. This systems reacts to the proximity of the second systems and thus creates a "drag".
 * We create three different materials (one of them animated) and assign them to the three particle systems.

The Emitter
We use a Plane as emitter object. Scale it to your liking. I have used a relatively large particle system, so my plane has a length of 15 BU (Blender units).

A few particles (25) are created in the first 250 frames of the animation and emitted upwards. Gravitation, velocity and lifetime are adjusted so, that the particles reach the end of their lifetime at the topmost point of their trajectory.
 * Add a particle system (Fig 2a, left hand side).
 * Amount: 25
 * Sta: 1
 * End: 250
 * Emit from:
 * Random
 * Faces
 * Even
 * Random
 * Initial Velocity
 * Normal: 22
 * Random: 7
 * AccZ: -9.8
 * Visualisation: Line
 * Back: 1.1

The Line visualization lets the particles appear as long drawn-out line.

 * Bake the particle system. Use 500 as the End frame for bake. 300 would be sufficient here, but 500 do no harm.

Noob Note: Bake is in the Bake tab next to particle system tab in particle buttons window.

The plane will get a Halo material.
 * Activate Halo in the Links and Pipeline panel.
 * Halo: color red
 * Halo Size: 0.421
 * Hard: 35

I've adjusted the size and hardness of the halo so long until I liked it, so there is no specific reason to use these values.

Reactor 1
You just have created a second particle system. Rename this system, a good naming convention will help you a lot to keep the overview.
 * Click on the arrow next to 1 Part 1 in the Particle System panel.
 * The settings for the first particle system are no longer shown, now it reads 1 Part 2 (Fig. 2a, right hand side).
 * Click on Add New, now it reads 2 Part 2.

You don't have to set anything for the Target. It is not necessary to set the target object if it is the same object as the reactor. You just have to set the number of the target particle system eventually.
 * Activate React on: Death.
 * Life: 104
 * Emit from: Particles

The Reactor particles react on the Death of the particles of the target system. They will be emitted from the point that the particles occupy at their death.

To control the movement of the system, I have made following setting in the Physics panel: Because of the Reactor setting the star is moving away from the emitting particles. The Brown movement lets the trajectory appear trembling like affected by wind.
 * Particle: 0.345
 * Reactor: 10
 * AccZ: -0.09
 * Brown: 3.86

 * Set the material number to "2" in the Visualization panel.
 * Bake the system, again use 500 as end frame.

Material 2
The texture is actually superfluous here, but the next particle system is given the same texture, and colors should be adjusted a bit.
 * At first you have to assign a new material in the Link and Materials panel of the Editing Buttons.
 * Use the material settings from Fig. 3b,
 * The material also gets a Clouds texture with Noise depth "3", simply leave all other settings unchanged.

The second particle system is faded off relatively quickly, but the particles don't disappear suddenly.
 * Animate the Alpha value of the material.
 * Set the first Ipo key in frame 1 (Alpha=1). To do that move your mouse cursor over the Buttons window. Press I->Alpha (and change ipo type to material in the ipo curve editor if you are using that).
 * Set the second Ipo key in frame 86 (Alpha=0.75).
 * Set the third key in Frame frame 101 (Alpha=0.0).

Smoke Trail
The third (and last) particle system is again a Reactor system and is reacting to the second system. It's going to react to the Nearness of the particles. Without moving the variation of the particles is created with a texture and a random variation of their lifespan. What Blender considers as close can be changed with the particle Size.

 * Create a third particle system (like you created the second).
 * Use the settings from Fig. 4a. Important are the settings:
 * Amount: 100000
 * React on: Near
 * Emit from: Particles
 * Life: 75
 * Rand: 0.4
 * Target Sys: 2
 * Material: 3
 * Bake the system, again use 500 as end frame.

Material 3

 * At first you have to assign a new material (the third) to the object in the Link and Materials panel of the object buttons.
 * Assign the existing Clouds texture from material 2 also to material 3, but select a dark blue as target color (in the Map To panel).

Render

 * Render your animation, use end frame 500.

That's all. I hope you were able to follow the tutorial. Criticism and suggestions, write best on the talk page or improve the article directly.

title: Blender 3D: Noob to Pro/Fireworks


text:
Talk:Blender 3D: Noob to Pro/Fireworks

Update:: Blend file uploaded

^Where is the blend file? I can't seem to find it anywhere.

Replaced Text
The tutorial was not touched for over a year, and not finished either. So I'm going to replace it with my own tutorial. --SoylentGreen (talk) 16:05, 7 March 2009 (UTC)

Particles freezing and dissapearing after frame 250
After frame 250 all particle activity ceases - the particles already generated freeze in place and are removed one-by-one without fade.

Including a final blend file for the tutorial would be extremely useful for picking apart to see how the particle and material interactions are supposed to work.
 * Bake the particle system. Use 500 as the End frame for bake. 300 would be sufficient here, but 500 do no harm.. And so forth. The end frame for bake is important for the length of the simulation. --SoylentGreen (talk) 04:39, 5 June 2009 (UTC)

My thoughts
I was surprised by it a lot. Thank you. I think the reactor 1 particles should be more heavier. 98.117.125.221 (talk) 04:32, 18 June 2010 (UTC)

Alpha
This was one of my first tutorials i looked over in a while and it took way to long to figure out how to edit the alpha stuff.

title: Talk:Blender 3D: Noob to Pro/Fireworks


text:
Haskell/XML

There are several Haskell libraries for XML work, and additional ones for HTML. For more web-specific work, you may want to refer to the Haskell/Web programming chapter.

Libraries for parsing XML

 * The Haskell XML Toolbox (hxt) is a collection of tools for parsing XML, aiming at a more general approach than the other tools.
 * HaXml is a collection of utilities for parsing, filtering, transforming, and generating XML documents using Haskell.
 * HXML is a non-validating, lazy, space efficient parser that can work as a drop-in replacement for HaXml.
 * xml-conduit provides parsing and rendering functions for XML. For a tutorial see.

Libraries for generating XML

 * HSXML represents XML documents as statically typesafe s-expressions.

Other options

 * tagsoup is a library for parsing unstructured HTML, i.e. it does not assume validity or even well-formedness of the data.

Getting acquainted with HXT
In the following, we are going to use the Haskell XML Toolbox for our examples. You should have a working installation of GHC, including GHCi, and you should have downloaded and installed HXT according to the instructions.

With those in place, we are ready to start playing with HXT. Let's bring the XML parser into scope, and parse a simple XML-formatted string:

Prelude> :m + Text.XML.HXT.Parser.XmlParsec Prelude Text.XML.HXT.Parser.XmlParsec> xread " abc def " [NTree (XTag (QN {namePrefix = "", localPart = "foo", namespaceUri = ""}) []) [NTree (XText "abc") [],NTree (XTag (QN {namePrefix = "", localPart = "bar", namespaceUri = ""}) []) [],NTree (XText "def") []]]

We see that HXT represents an XML document as a list of trees, where the nodes can be constructed as an XTag containing a list of subtrees, or an XText containing a string. With GHCi, we can explore this in more detail:

Prelude> :m + Data.Tree.NTree.TypeDefs Prelude Text.XML.HXT.Parser.XmlParsec Text.XML.HXT.DOM> :i NTree data NTree a = NTree a (NTrees a)                                   -- Defined in Data.Tree.NTree.TypeDefs Prelude Text.XML.HXT.Parser.XmlParsec Text.XML.HXT.DOM> :i NTrees type NTrees a = [NTree a]      -- Defined in Data.Tree.NTree.TypeDefs

As we can see, an NTree is a general tree structure where a node stores its children in a list, and some more browsing around will tell us that XML documents are trees over an XNode type, defined as:

data XNode = XText String | XCharRef Int | XEntityRef String | XCmt String | XCdata String | XPi QName XmlTrees | XTag QName XmlTrees | XDTD DTDElem Attributes | XAttr QName | XError Int String

Returning to our example, we notice that while HXT successfully parsed our input, one might desire a more lucid presentation for human consumption. Lucky for us, the DOM module supplies this. Notice that xread returns a list of trees, while the formatting function works on a single tree.

Prelude Text.XML.HXT.Parser.XmlParsec> :m + Text.XML.HXT.DOM.FormatXmlTree Prelude Text.XML.HXT.Parser.XmlParsec Text.XML.HXT.DOM> putStrLn $ formatXmlTree $ head $ xread " abc def " ---XTag "foo" |    +---XText "abc" |    +---XTag "bar" |    +---XText "def"

This representation makes the structure obvious, and it is easy to see the relationship to our input string. Let's proceed to extend our XML document with some attributes (taking care to escape the quotes, of course):

Prelude Text.XML.HXT.Parser.XmlParsec> xread "abc def " [NTree (XTag (QN {namePrefix = "", localPart = "foo", namespaceUri = ""}) [NTree (XAttr (QN {namePrefix = "", localPart = "a1", namespaceUri = ""})) [NTree (XText "my") []],NTree (XAttr (QN {namePrefix = "", localPart = "b2", namespaceUri = ""})) [NTree (XText "oh") []]]) [NTree (XText "abc") [],NTree (XTag (QN {namePrefix = "", localPart = "bar", namespaceUri = ""}) []) [],NTree (XText "def") []]]

Notice that attributes are stored as regular NTree nodes with the XAttr content type, and (of course) no children. Feel free to pretty-print this expression, as we did above.

For a trivial example of data extraction, consider this small example using XPath:

Prelude> :set prompt "> " > :m + Text.XML.HXT.Parser.XmlParsec Text.XML.HXT.XPath.XPathEval > let xml = " AC " > let xmltree = head $ xread xml > let result = getXPath "//a" xmltree > result > [NTree (XTag (QN {namePrefix = "", localPart = "a", namespaceUri = ""}) []) [NTree (XText "A") []]] > :t result > result :: NTrees XNode

title: Haskell/XML


text:
User talk:Kleo.skywalker

Hello, welcome to Wikibooks!

You will find more resources in Community Portal. If you want to ask a question, visit the Study help desk, the Staff lounge, IRC channel or ask me personally on my talk page. For site news, see the Bulletin board. It might be a good idea to add this page to your "watchlist" so that you can see when any new information is posted there. You can do that by clicking the tab labeled "watch" at the top of the page.

Good luck! -- Herby talk thyme 09:38, 31 May 2007 (UTC)

Cookbook
G'day Kleo.skywalker, welcome to Wikibooks. You might be interested to read our Cookbook policy page, and talk to other Cookbook editors. Webaware talk 10:22, 31 May 2007 (UTC)

title: User talk:Kleo.skywalker


text: User:Yuriybrisk

title: User:Yuriybrisk


text:
Talk:Haskell/XML

Since I'm looking into some XML parsing at the moment, I thought I'd - more or less - type in my notes in the wikibook as I go along. Please do provide feedback whether this is acceptable and/or useful! --Ketil 09:44, 31 May 2007 (UTC)

Oh, damn. There is a tutorial I've somehow missed: []

title: Talk:Haskell/XML


text:
User:Ketil

Feel free to contact me at.

title: User:Ketil


text:
User talk:194.81.42.231

Welcome to Wikibooks. We invite everyone to contribute constructively to our collection. Take a look at the welcome page if you would like to learn more about contributing. However, unconstructive edits are considered vandalism, and if you continue in this manner you may be blocked from editing without further warning. Please stop, and consider improving rather than damaging the hard work of others. Thanks. -- Herby talk thyme 10:14, 31 May 2007 (UTC)

title: User talk:194.81.42.231


text:
A-level Chemistry/OCR (Salters)/Organic compounds

The organic compounds covered in Salters Advanced Chemistry can be classified as follows:

 * hydrocarbons
 * aliphatic hydrocarbons
 * alkanes
 * cycloalkanes
 * alkenes
 * alkynes
 * aromatic hydrocarbons (arenes)
 * haloalkanes
 * alcohols
 * alkoxides
 * ethers
 * amines
 * ammonium salts
 * nitriles
 * nitro compounds
 * diazonium salts
 * azo compounds
 * sulfonic acids
 * sulfonates
 * carbonyl compounds
 * aldehydes
 * ketones
 * carboxylic acids and their derivatives
 * carboxylic acids
 * carboxylates
 * acid anhydrides
 * acyl chlorides
 * esters
 * amides
 * amino acids

These groups of compounds each contain one functional group.


text:
User talk:74.113.140.130

Welcome to Wikibooks. We invite everyone to contribute constructively to our collection. Take a look at the welcome page if you would like to learn more about contributing. However, unconstructive edits are considered vandalism, and if you continue in this manner you may be blocked from editing without further warning. Please stop, and consider improving rather than damaging the hard work of others. Thanks. -- Herby talk thyme 11:29, 31 May 2007 (UTC)

title: User talk:74.113.140.130


text:
Ohio 7th Grade World History/Introduction

This book represents the beginning of a multi-year project to create a digital textbook based on the Ohio 7th grade social studies content standards. The first two chapters were completed by two different classes and represent information concerning the Middle Ages, Feudalism, the Renaissance and the Protestant Reformation. Students chose different topics that correspond to specific concepts outlined in Ohio’s curriculum standards. Students at Beachwood Middle School are creating this book. Beachwood City Schools are located in Beachwood, Ohio, a suburb of Cleveland. Beachwood Middle School incorporates technology in the classroom through a one-to-one laptop program. The information you read in this digital textbook is completely student-generated (excluding this introduction). Students spent several weeks brainstorming, reviewing their notes and previous projects, and collaborating in small groups. It is because of their dedication and achievement as life-long learners that this project is possible. These students also had the courage to take a risk with their teachers and use the last few weeks of school to do something truly unique. This textbook is the result of over a year of collaboration between several individuals. Garth Holman, the Social Studies department chair and 7th grade world history teacher envisioned this project as a way to engage students through the use of technology and help them see the “big picture” that is often lost, or ignored, in history classes. Beginning in the summer of 2006, Garth began working with a student teacher, Michael Pennington. Another member of this project was Angie White, an intervention specialist at Beachwood Middle School. Angie provided a strong knowledge of curriculum differentiation and techniques to include students of varying abilities. A project of this nature, allows students to disseminate knowledge in a digital format that is congruent to the world in which they live. Our students are digital natives and this new technological paradigm allows for the democratization of knowledge. Wiki technology and the ability to instantaneously communicate across cultures and physical boundaries means that nothing our students create is isolated. We not only want our students to learn, but understand how the puzzle pieces fit to create the world in which we live. It all started with a basic question, “how do you engage students and allow them to show what they know”. Burgeoning technologies require teachers to rethink assessment and adapt to their students. Teachers prepare students for their future, not our past. Life does not occur in a vacuum, yet too often textbooks and curriculum categorize and isolate historical episodes. Our students connected the historical dots using written summaries, hyper-links, digital imagery, and iMovie. The ultimate goal of this book is not only to explain important moments in history, but also understand the long-term effects of each moment.


text: Talk:Classical Mechanics/Introduction

title: Talk:Classical Mechanics/Introduction


text:
Geometry/Chapter 13

Complementary angles are angles that the sum of their measures is equal to 90º.

File:Complementary angles|thumbnail|center ]] Supplementary angles are angles that the sum of their measures is equal to 180º.

90º             __|__               90º _________________|__|__|____________________

Vertical Angles

In the above diagram, A and C are vertical angles, and B and D are vertical angles. Vertical angles are congruent.

title: Geometry/Chapter 13


text:
User:Puppies12

Hello! i am writing "how to write a good book for children" :)

title: User:Puppies12


text:
Cookbook talk:Kg

transwikid to kilogram

title: Cookbook talk:Kg


text:
Kdenlive/Image clips

Kdenlive/ Bildclips

As shown in the quick start guide, you just go to where you import clips, select image clip, and add to the project!

You then set the duration, etc.

Then drop it into the timeline, and there you have a picture!

title: Kdenlive/Image clips


text: Talk:Project+

title: Talk:Project+


text:
A-level Physics/Cosmology/How the universe may evolve

The question of whether the Universe is infinite or not depends crucially on the value of the quantity know as Ω. Such a value, although not determined yet, depends basically on the rate of expansion, or the Hubble Constant, of the Universe.

In simple terms, the quantity Ω is the ratio of the density of the universe (mass per unit volume) to the critical value which determines expansion or collapse. There are three possible outcomes from this value -
 * Steady State: the Universe will continue to expand up to a point, whereupon the Universe will stay in a constant state. This would occur if Ω = 1.
 * Continuous Expansion: The Universe will continue to expand. This will occur if Ω<1. The result of continuous expansion would be, according to the 1st Law of Thermodynamics, a Universe which would gradually cool down until the temperature became 0 Kelvin.
 * Regression: The Universe will grow, and then collapse on itself. This will occur if Ω>1. It has been postulated that if the Universe were to carry on this course, all matter would recondense into a singularity, and recreate another big bang.


text:
Cookbook:Eel Sauce

Eel sauce, also called unagi sauce or kabayaki sauce, is a Japanese condiment.

Characteristics
The sauce is dark brown and syrupy, with a deeply salty and savory flavor. The typical base ingredients are soy sauce, mirin, sake, and sugar, which are simmered together until thickened.

Selection and storage
Eel sauce can be purchased as a shelf-stable formulation or homemade.

Use
As the name indicates, eel sauce is primarily used as a glaze and dipping sauce for grilled eel in Japanese cuisine.  However, it can also be used with other foods, from sushi to various proteins.

title: Cookbook:Eel Sauce


text:
User:Miranda

  Welcome to Miranda's page!: Hello, my name is Miranda. I am an editor on English Wikipedia. I hope to add to this project with information that helps people. If you have any questions, please contact me on English Wikipedia

title: User:Miranda


text:
Talk:Blender 3D: Noob to Pro/Every Material Known to Man

Does this section makes any sense now? There is a blender material repository that contains public domain materials here http://repository.parastudios.de/.

I second this - at least we could mention this new repository in the page so people have something to look for more pre-fab materials. I like the existing entries here anyway, they are nicely illustrated and provide at least some insight into material creation. --80.109.73.21 08:30, 22 July 2007 (UTC)

I like this page's focus upon the various settings and methods. It should stay.

Every Material Known to Man Expansion
This section has an incredible amount of potential, and I believe it needs to be greatly expanded upon. Please do not delete the RED Links as they will be useful to help suggest to someone to contribute. If you think of more materials, even if you can't make it, add a link to an empty page for it as a hint to other contributors. Hopefully, we can get this page it's own Chapter, and then people will really visit it and it will REALLY expand!!! Thank you!--Bullercruz1 (talk) 22:48, 7 February 2009 (UTC)


text:
User talk:Miranda

Hello, welcome to Wikibooks!

You will find more resources in Community Portal. If you want to ask a question, visit the Study help desk, the Staff lounge, IRC channel or ask me personally on my talk page. For site news, see the Bulletin board. It might be a good idea to add this page to your "watchlist" so that you can see when any new information is posted there. You can do that by clicking the tab labeled "watch" at the top of the page.

Good luck! -- Herby talk thyme 18:56, 31 May 2007 (UTC)

title: User talk:Miranda


text:
Talk:Unicode/Character reference/1000-1FFF

Maybe the Unicode version colors should change to something more intuitive. For example, Unicode 1 can be blue and then Unicode 5 is red. Everything else in the middle is a color gradient from blue to green to red.
 * I am going to change that. Unicode 1 is red and then Unicode 5.x or 6 to be red. -- ✉ Hello World! 11:55, 11 November 2008 (UTC)
 * The following codes should use HTML entity because the Mediawiki alters them:
 * 0340-41, 0343-44, 0374, 037E, 0387, 0958-5F, 09DC-DD, 09DF, 0A33, 0A36, 0A59-5B, 0A5E, 0B5C-5D, 0F43, 0F4D, 0F52, 0F57, 0F5C, 0F69, 0F73, 0F75-76, 0F78, 0F81, 0F93, 0F9D, 0FA2, 0FA7, 0FAC, 0FB9
 * 1F71, 1F73, 1F75, 1F77, 1F79, 1F7B, 1F7D, 1FBB, 1FBE, 1FC9, 1FCB, 1FD3, 1FDB, 1FE3, 1FEB, 1FEE, 1FEF, 1FF9, 1FFB, 1FFD
 * 2126, 212A, 212B, 2329, 232A, 2ADC
 * FB1D, FB1F, FB2A-36, FB38-3C, FB3E, FB40-41, FB43-44, FB46-4E
 * 1D15E-1D164, 1D1BB-1D1C0
 * All CJK Compatibility Ideographs

-- ✉ Hello World! 11:55, 11 November 2008 (UTC)


text:
Logic for Computer Scientists/Propositional Logic/Analytic Tableaux

Analytic Tableaux
In this section we present a calculus, namely analytic tableau, which is an alternative to resolution. Although this calculus was developed independently from resolution, it will turn out that there are some interesting common features. The most obvious difference is, that analytic tableau work direct on formulae, there is no need to transform a formulae in a clausal normal form.

Tableaux - A Short History
The development of tableaux calculi started in the 1950th. The first authors to be mentioned are Beth (1955), Hintikka (1955) and Schütte (1956). Their goal was primarily to develop calculi without meta-language constructs. Later in the 1960th the idea of derivation trees and nodes in such a tree labeled by formulae became famous as the concept of analytic tableaux introduced by Smullyan 1968. The idea of mechanisation of tableaux calculi was then introduced by Kanger 1957, Prawitz 1960, Wang 1960, Davis 1960 and  Maslov 1968.

Later on the concept of analytic tableaux was modified and refined for its use in automated deduction by Loveland 1968 (Model elimination), Kowalski, Kuehner 1971 (SL-resolution) and Bibel 1975, Andrews 1976 (Connection or matings methods). Nowadays there are numerous high performance theorem provers based on this work.

The Calculus
One of the advantages of tableaux calculi is that can be defined without transforming the formula into clause normal form. Example Given a set of formulae $$\{\lnot P \land \lnot (Q \lor R), \lnot (Q \land \lnot R)\}$$. We are aiming at constructing a tree, whose branches contain nodes which are labeled with formulae.

For this it is important to analyse the formula according to its leading connective. Smullyan observed that some work can be saved if non-literal formulas are grouped into types which are treated identically: $$\alpha$$ for formulas of conjunctive type, $$\beta$$ for formulas of disjunctive type in the propositional case. Note that in the above example $$\lnot (Q \land \lnot R)$$ has to be treated as a formula of disjunctive type, because of the negation standing in front of the conjunction. Correspondence between formulas and their types is summarised in Table 1. The letters $$\alpha$$ and $$\beta$$ are used to denote formulas of (and only of) the appropriate type. Let us now define the basic data structure for tableaux calculi together with the corresponding extension rules.

Definition 13
A tableau for a logic $$L$$ is a finitely branching tree whose nodes are formulas from $$L$$. A branch in a tableau $$T$$ is a maximal path in$$T$$. When no confusion can arise, branches are frequently identified with the set of their nodes (formulas). Given a set $$\Phi$$ of formulae from $$L$$, a tableau for $$\Phi$$ is constructed by a (possibly infinite) sequence of applications of the following rules:
 * 1) The tree consisting of a single node $$true$$ is a tableau for $$\Phi$$ (initialisation rule).
 * 2) Let $$T$$ be a tableau for $$\Phi$$, $$B$$ a branch of $$T$$, and $$\psi$$ a formula in $$B\cup\Phi$$. If the tree $$T'$$ is constructed by extending $$B$$ by as many new linear subtrees as an instance of a tableau rule schema in Table 2 with premise $$\psi$$ has extensions, and the nodes of the new subtrees are the formulas in the extensions of the rule instance, then $$T'$$ is a tableau for $$\Phi$$ (expansion rule).

One tableau for our example is depicted in figure 2.

Definition 14
In a tableau $$T$$ for a set $$\Phi$$ of sentences a branch $$B$$ is closed iff $$B\cup\Phi$$ contains a pair $$\phi,\lnot\phi$$ of complementary formulas, or $$false$$; otherwise, it is open. A tableau is closed if all its branches are closed. A tableau proof for (the unsatisfiability of) a set $$\Phi$$ of formulae is a closed tableau $$T$$ for $$\Phi$$.

Problem 31 (Propositional)
Give a strict tableau proof for the following formulae:

$$\Box$$
 * 1) $$\lnot((A \downarrow B) \downarrow (A \lor B))$$
 * 2) $$((A \to B) \land (B \to C)) \to (\lnot (\lnot C \land A))$$

Clause Normalform Tableau
Let us now refine the calculus for the special case, that we deal with sets of clauses, which represent a formula in CNF. Note that in the case of conjunctive normal form clauses we only have literals, which are connected by $$\lor$$-junctors. Hence every clause is of $$\beta$$-type. In figure 3 a tableau for a set of clauses is given. The clauses from the given clause set form the initial tableau; then there is only the  $$\beta$$-rule applicable for further extensions of the tableau.

In the following formal definition of a clause normal form tableau we start with an initial tableau, which is formed by taking an arbitrary clause from the given clause set S. For further extensions of the tableau $$\beta$$-rule-applications with clauses from S can be used. Which of the clauses is allowed is controlled by a link condition.

Definition 15
A clause (normalform) tableau for a set of clauses $$S$$ is a tableau for $$S$$, whose nodes are literals from $$S$$ and which is constructed by a (possibly infinite) sequence of applications of the following rules:

 * 1) The tree consisting of root $$true$$ and immediate successors     $$L_1, \cdots, L_n$$, where $$C = L_1, \cdots , L_n \in S$$ is a tableau for $$S$$ (initialisation rule).
 * 2) Let $$T$$ be a tableau for $$S$$, $$B$$ a branch of $$T$$, and $$C=L_1, \cdots ,L_n \in S$$, such that the    link-condition (see below)  is satisfied.  If the tree $$T'$$ is constructed by extending $$B$$ by the $$n$$ subtrees $$L_i$$, then $$T'$$ is a tableau     for $$S$$ (expansion rule).

The following are three possible link conditions: In fact we have defined three different calculi:
 * 1) No condition.
 * 2) Weak link condition: There is a literal $$L \in B$$ and  $$\overline{L} \in C$$.
 * 3) Strong link condition: Let $$L$$ be the leaf of $$B$$,  then there is $$\overline{L} \in C$$.
 * Without link condition it is called clause normal form tableau,
 * with the weak link condition we call it connection calculus, and
 * with the strong link condition it is called model elimination.

An example for clause normal form tableau was given in figure 3. An example for a connection calculus tableau is

and finally a model elimination tableau is given by

Theorem 11
Clause normal form tableau are complete. Note that strong link condition do not allow for confluent

proof procedures. If no link condition (i.e. the empty one) is applied it is trivial to get a confluent version. For the case of weak link condition this is not obvious. In order to arrive at a decision procedure for propositional clauses we need an extra condition:

Definition 16
A branch $$B$$ of a tableau for a clause set $$S$$ is called regular, if no literal occurs more then once.

Theorem 12
Clause normal form tableau with regularity and link condition give a decision procedure for propositional logic.

Problem (diagnosis)
Consider this electronic circuit with two input lines and one output line:

Suppose, as depicted, that both input lines are "1" and that the output line is "1", thus contradicting the expected output value "0".
 * 1) First, formalize the circuit, i.e. the functionality of the three components and the two connections by neglecting the possibility of not correctly functioning components (i.e. do not use abnormal -Literals).
 * 2) Consider the value pairs "0-0",  "1-0" and "1-1" to be supplied to the input lines. For each of these, using the result from (1) compute the expected output value by means of analytic tableau.  How did you read off the results from the tableaux?
 * 3) Use your formalization and analytic tableau to prove that the output value "1" contradicts the expected behavior in case of input "1-1". How did you read off the result from the tableau?
 * 4) Now modify the formalization of the components in (1) by abnormal -literals as shown in class.  Use analytic tableau to compute all possible diagnosis for the input "1-1" and output "1". How did you read off the result from the tableau?


text:
User talk:195.229.236.218

Thanks for experimenting with Wikibooks. Your test worked, and has now been removed. Please use Sandbox for any other tests you want to do, since testing material in modules will normally be removed quickly. Please see the welcome page if you would like to learn more about contributing to our project. Thanks.

Xania talk 20:11, 31 May 2007 (UTC)

title: User talk:195.229.236.218


text:
Chip Design Made Easy

In this book Chip Design we tell how to build an integrated circuit ("chip") by integrating billions of transistors to achieve an application. An application could be suiting a particular requirement like microprocessor, router, cell phone,etc. An integrated circuit designed for a specific application is called as ASIC (Application Specific Integrated Circuits).

Today's ASIC Chips are pretty complex, packed with larger chunk of transistors targeted to a specific manufacturing process for fabricating the integrated circuits, in a sub nanometer regime, involving many challenges like knowledge of various protocols, architectures, models, formats, standards, knowledge about CMOS logic, Digital Design concepts, taming the EDA tool for the various design requirements like area, timing, power, thermal, noise, routability, lithography aware, knowledge about various variabilities like channel length, Vt, line width variations, lens aberrations, IR drop effects, inter-die and intra die-variations, effects, and various noise-effects like package noise, EMI noise, power grid noise, cross-talk noise, and ability to test and validate and know to model and characterize all these effects upfront in the design-phase, steps to increase profitability curve, with short span of time-to market to minimize the risk and maximize the predictability and an modular approach to success. Now let's delve in to the "Art of Chip Designing".

That is a lot of technical jargon, but there is nothing to worry about. You will soon learn what that means, and understand the concepts behind chip designing.

Before Designing a Chip? Need to Brain Storm

 * What market is the Chip targeted for?
 * What are the Protocols involved in the Chip?
 * What is going to be our Processor/Bus Architectures?
 * What is the power/IR-drop/timing/area/yield targets and how to budget it in the Chip?
 * What is the process in which the Chip is going to be manufactured?
 * What are the various third party IP's/Memory requirements?
 * What is our design flow, EDA tools and methodology involved?
 * What is the estimated Chip cost?
 * Above all, the bottom line of any business model is money. What is our Profit model? What is our estimated ROI (Return of investment)?

Analogy of Chip Design Architecture Vs Building Architecture.
Why an Analogy with Building Architecture? To understand the concepts of Chip designing in a better way, as we are very familiar with Building Architecture, then it will be easy for us to map Chip Design architecture.

VLSI (Very large scale Integration) flow was evolved similar to the flow involved in Building Construction. Now let us delve in to the construction flow to better understand the VLSI Chip design flow development.

Whenever we start to construct a building, we will have an architecture, how the building should look like, the exterior looks, etc. Similar to that we will be designing an architecture in the chip-design, based on the requirement of the product, what the product is addressed for and whom to serve what needs -the so called specification- of the different modules.

Now lets go in to the implementation part of both the Building & Chip.

We at first come with the floorplan of the building, similarly we come with the floorplan of the Chip. Based on the connectivity/accessibility/vaasthu we place our rooms, similarly we have the constraints to place the blocks. Like we build the building with bricks, windows and other modules, for Chip Design we have component libraries, which are like pre-designed bricks, for a specific functionality.

Now let us try to understand the power-structure or electrical connectivity in our building. Initially we have an electrical plan for our building, where we have a requirement that all our electrical gadgets needs to get power. Similar to that we have a Chip power requirement. The required power is supplied through the power-pads, over a ring-like topology to have a uniform distribution across all corners of the chip, and the supply has to reach all the standard-cells (bricks for Chip-Designing), this is called as power-grid topology in the Chip-Design. Now the requirement is how well we design our Power-grid to reduce the IR-drop, so that our standard-cells get proper power requirement.

I would not make justice if I don't discuss about clock and clock-tree in the Chip-Design flow. We have synchronous and asynchronous (more difficult to test and verify) ways of designing. The majority of chips follow a synchronous design, for which Static Timing Analysis is possible. For the relevancy of the flops, the clock signal from the crystal should reach at the same time -or within some skew targets- to different components within the chip. In order to make this happen, a step called clock-tree is performed after power-grid is created.

Let us try now to visualize the concept behind Place & Route in Chip Design, where the different components of the chip are physically placed and their pins properly inter-connected. To have a better understanding of this concept, let us assume a society where people speaking different languages are living together, and let us visualize how people talking the same language will tend to end up living in the same neighborhood, forming separated communities and making the communication between people much easier. In a similar way, in chip-designing, standard-cells having strong relationships are placed closer in the placement flow, forming separated areas. This process is called as regioning. Now, within the regions, the standard-cells which are really sharing data have to be placed close-by so that their timings match and are optimized. This step is called placement, while defining the connectivity across the standard-cells is called as routing, and the challenge is having optimized or reduced wire-lengths.

Now let us try to understand the concept behind Signal Integrity (SI) in the Chip-Design, often called as SI Effect. As our processes are shrinking day by day, and our silicon real estate is costly, we try to accommodate more and more standard-cells in a limited area, so the cells are placed in very close proximity, and the switching of one cell can have an impact over the others' behaviour, which can make the path to be faster or slower. This issue is called as signal-integrity. So similar way in our construction in order to maintain the integrity with in the house (neighbour free-zone), within the limited zone of modularity, we try to create fences across buildings, similarly we can think of a concept called as Shielding, the high frequency signal net with the power-nets running across. We perform spacing across the buildings, similar way we can perform spacing across the nets, which are in close proximities.

In order to validate the silicon from the manufacturability issues, the concept in the Chip Designing is Design for Test(DFT). One of the DFT techniques is scan-chain. To understand the concept of the scan-chain, we can visualize that we have a front-door entry and a back-door exit, and a person passes from the front-door and exits from the back-door exit of the building, that we are sure that there is no blocking within the rooms in the building, to make that person stuck, similar to this analogy the flip-flops are connected together creating a scan-chain and test-input values are passed from the scan-chain input of the chip and expected data is visualized in the scan-chain output of the chip, then the assumption is the chip is free from manufacturability issues like stuck-at faults(stuck-at one or stuck at zeros).

VLSI Design Flow
Step 1: Prepare a Requirement Specification

Step 2: Create a Micro-Architecture Document.

Step 3: RTL(Register Transfer Level) Design & Development of IP's(Intellectual Property)

Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly.

Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL

Step 4b: Perform Property Checking, to verify the RTL implementation and the specification understanding is matching.

Step 4c: Perform Clock Domain Crossing check, to verify that proper synchronization of control/data is there to ensure reliable cross domain data transfers.

Some people use "logical effort" to estimating the latency in the critical path of a CMOS circuit, and hence the maximum possible speed of the circuit.

Step 5: Prepare the Design Constraints file (clock definitions(frequency/uncertainty/jitter),I/O delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an SDC file(Synopsys constraint file, specific to Synopsys synthesis Tool (Design Compiler))

Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which synthesis needs to be targeted for, which has the functional/timing information available for the standard-cell library and the wire-load models for the wires based on the fanout length of the connectivity), RTL files and the Design Constraint files, So that the Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet the design-constraints requirements. After performing synthesis, as a part of the synthesis flow, need to build scan-chain connectivity based on the DFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds the scan-chain.

Step 7: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT) after synthesis.

Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting the power targets.

Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the functional requirements.

Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that the synthesis Tool has not altered the functionality.

Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format) file and synthesized netlist file, to check whether the Design is meeting the timing-requirements.

Step 7e: Perform Scan-Tracing, in the DFT(Design for Test) tool, to check whether the scan-chain is built based on the DFT requirement.

Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog format) and the SDC (constraints file) is passed as input files to the Placement and Routing Tool to perform the back-end Activities.

Step 9: The next step is floor-planning. Floor-planning means placing the IP's based on the connectivity, placing the memories, Create the pad ring (also called the pad frame), placing the Pads (Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements (Simultaneous Switching Noise) that when the high-speed bus is switching that it doesn't create any noise related activities, creating an optimised floorplan, where the design meets the utilization targets of the chip.

Step 9a : Release the floor-planned information to the package team, to perform the package feasibility analysis for the pad-ring.

Step 9b: To the placement tool, rows are cut, blockages are created where the tool is prevented from placing the cells, then the physical placement of the cells is performed based on the timing/area requirements. The power-grid is built to meet the power-target's of the Chip.

Step 10: The next step is to perform the Routing., at first the Global routing and Detailed routing, meeting the DRC(Design Rule Check) requirement as per the fabrication requirement.

Step 11: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF file is taken to the Extraction tool (to extract the parasitics (RLC) values of the chip in the SPEF format(Standard Parasitics Exchange Format), and the SPEF file is generated.

Step 12: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and Routing step.

Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design has met the power targets.

Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the design is meeting the functional requirement.

Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that the place & route Tool has not altered the functionality.

Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file, to check whether the Design is meeting the timing-requirements.

Step 12e: Perform Scan-Tracing, in the DFT tool, to check whether the scan-chain is built based on the DFT requirement, Perform the Fault-coverage with the DFT tool and Generate the ATPG test-vectors.

Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)

Step 12g: Perform DRC(Design Rule Check) verification called as Physical-verification, to confirm that the design is meeting the Fabrication requirements.

Step 12h: Perform LVS(Layout vs Schematic) check, a part of the verification which takes a routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two are matching.

Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is meeting the ERC requirement.

Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and proper guarding is there in case if we have both analog and digital portions in our Chip. We have separate Power and Grounds for both Digital and Analog Portions, to reduce the Substrate-noise.

Step 12k: Perform separate STA(Static Timing Analysis), to verify that the Signal-integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF file (parasitics including coupling capacitances values), are fed to the tool. This check is important as the signal-integrity effect can cause cross-talk delay and cross-talk noise effects, and hinder in the functionality/timing aspects of the design.

Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand the static and dynamic power-drops with in the design and the IR-drop is with-in the target limits.

Step 13: Once the routed design is verified for the design constraints, then now the next step is chip-finishing activities (like metal-slotting, placing de-coupling caps).

Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which the fab can understand, GDS file.

Step 15: After the GDS file is released, perform the LAPO check so that the database released to the fab is correct.

Step 16: Perform the Package wire-bonding, which connects the chip to the Package.

Deeper to Chip Architecture
This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge.

 * What is the targeted market for this Chip.
 * What are the competitor's to this Chip and Market Requirement and ROI
 * What is the Fabrication Unit the Chip is targeted for?
 * What is the Success rate and Yield numbers achieved in the Fabrication Unit
 * What is the technology Process targeted for
 * What is the correlation of the library models w.r.t. Silicon
 * What are the various Protocols the Chip is going to address
 * Hardware & Software Partitioning.
 * What is the processor/micro-controller suitable for this application.
 * What is the bus-architecture targeted
 * What are the performance targets for this bus architecture
 * What are the various Interfaces the Chip is having
 * Is the design going to be in single Vt or with Multi-Vt design
 * Is using Embedded macro's right choice or Memory Macros
 * What are the IP's are going to be Re-used
 * What are the IP's going to Hard-macro's
 * What is the Verification Status and corner-case coverage of the I.P's
 * What is the Die-size targeted/Estimated for the Chip
 * What are the Power targets
 * Is Power Management Unit a requirement in the chip to reduce Dynamic power
 * What are the mechanisms followed to reduce the leakage power
 * Is Module enables/clock-gating a part of the Methodology
 * Are resets going to synchronous or asynchronous
 * What are the various Synchronous Mechanisms for data-transfer's
 * How many clock-domains required for the Chip
 * How many PLL's are required or single PLL sufficient for all the clocks required
 * What is the thought process behind PAD's Is LVTTL/SSTL pads
 * Is the package going to wire-bond or Flip-chip
 * Methodology for Optimal Power-grid design
 * What are the noise reducing Mechanisms in case of analog integration
 * Is there any requirement of speed monitor's or process checking blocks
 * What is the type of fuses used laser fuse or effuses
 * Is there any requirement of Fib Cells in the Design
 * What are the mechanisms used to handle ESD
 * what is the reliability target of the Chip and how it is addressed
 * What are the Mechanisms used for Yield improvement
 * Is the chip tested at at-speed test
 * How much Memory-map is allocated for the IP's
 * What is the metric for spare-gates in the Chip for ECO's
 * Are repairable memories required
 * What is the tester targeted and the requirement to the Chip in terms of Scan-chain
 * Is test-vector compression mechanism's a requirement
 * What is the PLL(Phase Locked Loop) performance in terms of Jitter
 * What is the Interrupt handling mechanism within the Chip.
 * What is the ROM-Code for the Chip.
 * What are the Chip utilization targets
 * Will the chip be routable or any requirement for special libraries with different routing  tracks.
 * What is the Methodology for tools and versions
 * What is the Version control mechanism planned for data handling across multi Geographical Environments.
 * What are the sign-off criteria for the Chip
 * What are the frequency targets for the Chip.
 * Is there room for further revisions of the Chip.
 * If the Chip has DDR/SDR interface is there any requirement for DLL.
 * What are the limitations of the Tools in terms of Complexity/run-times/turn-around times/Computation Power requirements.
 * What is the Mechanisms/Steps taken for the various Variability in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.

Thought Process Involved in Bus-Architectures
what are various parameters to be looked in to for an optimal System bus architecture in an SoC, in order to have maximum performance possible.

 * System speed is not only dependent on the Processor/Micro-controller but also on the Bus speed the system operates.
 * Contention Prevention mechanism's across multiple drivers.
 * Bus Splitters: Hierarchical Bus structures, based on the speed targets {for example the AMBA bus from ARM, has two bus hierarchy levels : Advanced High Performance Bus[AHB] & Advanced Peripheral Bus[APB]. Split bus architectures has energy efficient transactions and concurrent data transactions over the conventional buses.
 * Reducing latency and crossbar utilization mechanisms.
 * Optimum Bridging Mechanisms for cross data Transfer's among the Buses.
 * Performance Enhancers by having Pipeline mechanism's and steps to prevent Stalling.
 * Arbitration Protocol schemes for shared buses {Fixed Priority Schemes, Round Robin Scheme, * Time Division Multiplexing Schemes}.
 * Mechanisms to reduce bus waiting time.
 * Synchronization mechanism's across the bus
 * Scheduling based on power-profiling.
 * Traffic based Dynamic Voltage and frequency scaling techniques for meeting power-targets.

Implementation Challenges and Solutions
The metric for today's ASIC Design is on one side of the coin is the maximum number of devices integrated, reduced die-size, optimal power, speed, thermal performance, addressing signal integrity, addressing reliability, enhanced yield techniques, reducing PLL jitters for reliable functionality, testability, integration of analog and digital in single SoC, Lithography friendly DRC, Functionality met, high speed interfaces to memories, the IO fabric, IO buffer analysis and selection, implementation to validate the silicon, ability to in-corporate last minute spec changes/functional & timing bugs Engineering Change Orders, Optimized package feasible, development phases involving multi-geographical multi-site, complex database handling, various models/abstractions/standards/formats/Protocols, advanced process, library characterization modelling silicon, higher degree of EDA tools, design re-use standards, building designs robust enough to deal with EMI noise/package noise/power-ground noise/cross-talk noise/substrate-noise/clock-jitter/process uncertainties/IR-drop/On-chip variation and on other side of the coin, how to address all these issues right from the design stage is the challenge of today's Chip Design Industry.

This tight bonding of integration across the domains/abstractions/tools/designers/process/protocols/standards/design re-use/decision in optimal trade-offs/design know-how's/cross-culture design community needs a modular uniform approach, to bring first pass silicon success. Now let's deal with the Implementation challenges and steps to achieve it in the design-phase.

Complex Database Handling/Multi-site Design & Development As now the designs are development in multi-site environment, as each site has some domain expertise and to use to the fullest it needs multi-site design and development stages, in order to maintain the database handling a proper version control management System (e.g., clearcase) is required to proper align the database, tag it with labels to know the database and finally after designing go through with proper reviews and checklist process to assure the quality of the delivery.

Designing an Optimal Padring Steps involved in designing an optimal padring

Make sure you have corner-pads, across all the corners of the padring This is mainly to have the power-continuity as well as the resistance is less Ensure that the Padring fulfills the ESD requirement, Identify the power-domains,split the domains, Ensure common ground across all the domains. Ensure that the design has sufficient core power-pads. Choose the Drive-strength of the pads based on the current requirements, timing. Ensure that there is separate analog ground and power pads. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O's.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with unconnected inputs, they consume power if the inputs float. Ensure that oscillator-pads are used for clock inputs. In-case if the design requirement for source synchronous circuits make sure that the clock and data pads are of same drive-strength. Breaker-pads are used to break the power-ring, and to isolate the power-structure Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin. Ensure that few pad-filler cells are placed near the corner pads to ease the substrate routing requirements. In case of source synchronous pads, like clock and data going out, Ensure that these pads are on the centre, as the leads at the center of the package is short compared to the leads on the corners of the package, which can reduce the impact of EMI.

Designing for Optimized Area As silicon real-estate is very costly and saving is directly proportional to the company's revenue generation lot of emphasize is to design which has optimal utilization in the area-front. The steps to reduce area are

If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets.

Designing an Optimized floorplan Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently, then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed, estimate the routability issues. Study the architecture and application, so that the blocks which will be enabled should be scattered, to reduce the power-ground noise.

Designing for Achieving Power-targets As Today's IC design power plays a major-role in the design win, achieving power-targets are the major concern. Some of the design best-practices are Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt's(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design, clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enables gives a lot of power-savings. As clock-tree's always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction. Incorporating Dynamic Voltage & Frequency scaling (DVFS) concepts based on the application, there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced.

Designing for Achieving Frequency targets. As ASIC designs are today rated by the clock frequency the design can achieve, brings with lot of performance within. The few design strategies to achieve the frequency targets.

Using logic restructuring for the areas to be timing met, Use the useful skew, if permissible by meeting the hold-time requirements. Use register retiming/time-borrowing concepts to meet the design timing requirements Use faster flip-flops for the timing-paths which are timing hungry. Use Low-Vt cells for the paths to meet the timing. Ensuring the design meets the frequency targets by performing STA, across all the functional and test modes, across all the corners, including the derating factors. Make sure that there exists common clock-tree paths and bifurcation happens only at the last-stage, so that the common clock-path can be removed in the delay calculation as over-head in the pessimism removal during de-rating. Incorporate programmable DLL(Delay locked loop) based design, for memory-controller designs, which involves round-trip delays.

Designing for Meeting Signal-integrity targets As more and more devices are getting packed, results in more congested areas, and coupling capacitances dominating the wire-capacitance, creates SI violations. Let's see now by what are all the measures we can reduce/solve it.

As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts. Shield the nets with power-nets for high frequency signal nets to prevent from SI. Enable SI aware routing, so that the tool takes care for SI Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements Route signals on different layers orthogonal to each other Minimize the parallel run-length wires, by inserting buffers.

Designing for Better Yield(DFY/DFM) Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranteeing the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge.

Create more powerful stringent runset files with pessimistic spacing/short rules. Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it. For via-reliability issues, use redundant vias, to reduce the chances for via-breakage. In order to design for yield-enhancement, design systems, which could have optimal redundancy, like repairable memories. Optimal placing of decoupling capacitances, reduces the power-surges. Doubling the width of the non-critical nets, clock-nets can increase the yield parameter. Ensure that the poly-orientation are maintained.

Designing for Optimal integration of Analog and Digital As today's IC has analog components also inbuilt, some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting close-by, to reduce the noise. Ensure that there exists separate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro's. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion.

Designing for Engineering Change Order As more and more complex the IC design is, and with lot of first time application , is more prone to last minute changes, there should be provision in the design-flow to accommodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO).

Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved.

Designing an Lithography friendly Design Designing for Manufacturability requires validating the design full-filling lithography rules

Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets.

Chip Verification methodologies
-"Anything that can go wrong - Will"-Murphy

What is my next step to be performed?

Now Lets start with an assumption that anything may go wrong

What are the various areas can things go wrong?

List down the areas in the flow that things can go wrong and derive a methodology to verify at each and every stage. List down all your uncertainties that could potentially happen and how to model it and how to constrain and verify up-front. Explore and re-visit each and every area in the Design flow to cover potential risk

Functional Verification (RT L level, Gate level) Formal Verification Static Timing Analysis Physical Verification Power Simulation Thermal Simulation Noise Simulation Test Simulation Emulation Hardware prototype Hardware Software co-simulation Transistor level Simulation Now lets Venture in to each area and insure it

Functional Verification:

TLM(Transaction Level Modeling) Linting RTL Simulation (Environment involving : stimulus generators, monitors, response checkers, transactors) Gate level Simulation Mixed-signal simulations Regression How Much Did I cover in the functional part - What is my Coverage Metric? and what are the methodologies used?

Is the verification tests covered pin-pointed tests or tests with random seeds to cover all the corner-cases. Code-coverage Line coverage Functional coverage

Formal Verification:

Equivalence checkers RTL versus Gate Pre-layout versus post-layout Net list Assertion based property checkers(Mathematical techniques to allow larger state space coverage)

Timing Verification:

With whom the Chip is talking to (To know the Interface Timing's) What is the Timing-budgets with in the chip, and how to constrain it within each I.P. and finally analyzing and signing for Timing-targets How to address the timing targets with varying process parameters(on-chip variation) what is the optimal de-rating number to be set so that variations are addressed. Steps to minimize the clock-jitter.

Physical Verification:

Is my design manufacturing process friendly ?

DRC (Design Rule Check) LVS Antenna Checks ERC ESD checks

Noise Simulation:

How Noisy is my design so need to perform noise simulations addressing these areas

Simultaneous Switching Noise (SSN) Package Noise EMI Noise Power-ground noise Cross-talk noise Analog Noise Substrate noise Power Simulations:

When a digital logic gate switches, it pulls a surge of current through the power and ground pins connected to it. The inductance of those pins (and their bond wires) converts that surge to an internal drop in supply voltage and rise in ground voltage on-chip (relative to a PCB ground plane). Those voltage fluctuations may not be enough to interfere with digital logic, but they can seriously interfere with the performance of analog circuits. There are several "tricks" to reduce the electromagnetic interference (EMI) of these surges.
 * An independent set of "I/O" power supply pins that is only connected to the output drivers on the I/O pads, separate from the "core" power supply pins that power internal digital logic. This helps prevent switching noise in a processor core from leaking out through the output pins, radiating off PCB traces like an antenna, and interfering with radio and television (and failing FCC testing).
 * An independent set of "analog" power supply pins that power the on-chip analog components (ADC, DAC, etc.) and analog output pads, separate from the "digital" power supply pins. This helps prevent switching noise in a processor core from interfering with the analog components.
 * I/O bus pins (address and data) that only toggle on I/O bus cycles, independent from memory bus pins. A single common bus for all external memory and I/O devices forces each memory access to toggle address and data lines all over the PCB connected to every I/O device, radiating much more noise.
 * spread spectrum clock
 * internal clock doubler or more general clock PLL -- this allows internal processor core to run at a high clock rate, without that high frequency being directly connected to any PCB traces.
 * Put some internal memory on-chip; clock only internal memory (cache RAM or flash memory) at high speeds; use a slower pace to read and write external memory devices.
 * Drive output pins with slower rise and fall times to reduce radiated EMI (even though the pins still have the same number of transitions/second); tolerate slower rise and fall times on input pins.
 * Prefer differential communication buses -- FireWire, USB, XDR DRAM, low-voltage differential signaling, etc. -- rather than inherently noisier single-ended buses -- RS-232, IEEE 1284, the ISA bus, etc.

Is my design meeting power-targets

IR drop analysis Dynamic power simulations

Power related methodologies

Optimum location for De-caps Multiple Voltage domains Multi Vt design DVFS (Dynamic Voltage and Frequency scaling) Clock-gating Techniques Power Management Unit (to shut-off when not required) Level-Shifters across cross-voltage domains

Thermal Simulations

Study the thermal targets and mechanism to reduce thermal problems.

The largest and most obvious thermal problem is permanent failure caused by overheating. One way to avoid that is ...

There are also more subtle problems, such as thermal gradients causing nonlinearity in analog chips. Computer simulations often leave out such subtle effects, creating a "simulations never fail" problem when the actual chip performs much worse than the simulations. Mask Designers carefully lay out amplifiers, placing critical components with symmetry and common-centroid layouts, in order to reject thermal gradients.

Test Simulations

Is my design testable once chip comes out, methodologies to identify the problematic areas

Boundary Scan Memory BIST simulations Tester specific vector generation and simulations Tester vector compression techniques to reduce tester time At-speed testing mechanism's Scan-shift and scan-capture methodologies IDDQ testing Wafer Level Burn-in Tests to know Known Good Dies(KGD) Wire pull tests DC parameter tests AC parameter tests Path-delay tests Delay tests Transition fault testing

Addressing DSM and Yield Issues

Redundant via's Spacing non critical areas to be lithography friendly Wire widening Metal Filling Metal Slotting

Emulation:

Emulates the functional behavior of the design. Synthesizable assertions are mapped to emulators to perform at system speeds.

Hardware prototype:

Prototyping the system requirements in a programmable FPGA's

In spite of all the Verification Methodologies and Strategies if things goes wrong, how to address that in the design - Methodologies to reduce cost & time

Spare-gates Redundant rows/columns in the memories Redundant vias Built-in self repair memories Focused Ion Beam Methodologies

Internal Links

 * Programmable Logic
 * Microprocessor Design
 * Nanotechnology/Nanoelectronics
 * Semiconductors

title: Chip Design Made Easy


text:
Talk:First Aid/Protective Precautions

removed info
The following info was removed because it goes beyond first aid. An N95 respirator is strongly advised to be worn when an individual has tuberculosis. Mike.lifeguard 20:40, 31 May 2007 (UTC)

Terminology
Can we come up with something a bit more... professional than 'people danger'?? Please?  – Mike.lifeguard  | talk 01:23, 16 July 2007 (UTC)
 * I changed it to "subject danger." Can we agree that this is suitable?--Nugger 03:13, 3 August 2007 (UTC)

 * I can't agree to that and i've reverted, because it is not just the subject who is dangerous. What about the person who may have inflicted the injuries on them?  I don't see the issue with the word people, it's a basic descriptive, with very few synonyms. Owain.davies 06:56, 3 August 2007 (UTC)

 * There are Victims (Those who need help), Suspects (Those who may have caused the injury), and Witnesses (Those who saw what took place, including medical personnel). Subjects are a generalization of everyone at the scene. It's used in report writing here in the states.--Nugger 02:43, 4 August 2007 (UTC)

 * It does in that case cause confusion as the common understanding in the UK would be that subject is either the person you're treating (as this is a first aid manual). In law enforcement subject would be the same as suspect in most useage.  If everyone is that keen on changing from people (and i still don't see why) we need to find an internationally agreeable term.  Regards Owain.davies 10:02, 4 August 2007 (UTC)

 * I think I've got one, Human Danger. Short, sweet, and to the point. When we add the definition to it, we keep it basic and professional. Not to mention it is international. So, agree?--Nugger 15:13, 4 August 2007 (UTC)

 * Happy with that, good solution. carry on.  Owain.davies 21:40, 4 August 2007 (UTC)

title: Talk:First Aid/Protective Precautions


text:
Change Issues in Curriculum and Instruction/Other Issues Worth Investigating/31 May, 2007

1. Teaching Ourselves and Our Students to Learn Through Trial and Error:  Self-Study, Fear of Risk, etc.

2. Individuality's Relationship to Isolation:  Does the "American way" set us up for isolation?

3.


text:
User:Xixtas/Sandbox/Glossary Test

The quick brown fox jumped over the lazy dog's back.

Glossary

title: User:Xixtas/Sandbox/Glossary Test


text: User:Xixtas/Sandbox/Glossary

title: User:Xixtas/Sandbox/Glossary


text:
User:Xixtas/Sandbox/Glossary//dog

Dog - A member of the genus Canis (probably descended from the common wolf) that has been domesticated by man for thousands of years; occurs in many breeds.

title: User:Xixtas/Sandbox/Glossary//dog


text:
User:Xixtas/Sandbox/Glossary/dog

Dog - A member of the genus Canis (probably descended from the common wolf) that has been domesticated by man for thousands of years; occurs in many breeds.

title: User:Xixtas/Sandbox/Glossary/dog


text:
User:Xixtas/Sandbox/Glossary/fox

Fox - A small carnivore (Vulpes vulpes), related to dogs and wolves, with red or silver fur and a bushy tail.

title: User:Xixtas/Sandbox/Glossary/fox


text:
User:Xixtas/Sandbox/Glossary/lazy

Lazy - Unwilling to do work or make an effort.

title: User:Xixtas/Sandbox/Glossary/lazy


text:
User:Xixtas/Sandbox/Glossary/quick

Quick - Moving with speed, rapidity or swiftness, or capable of doing so; rapid; fast.

title: User:Xixtas/Sandbox/Glossary/quick


text:
User talk:Emerika

This is a test: brad

title: User talk:Emerika


text:
User talk:VanillaXtract

Welcome message
Hello, welcome to Wikibooks!

You will find more resources in Community Portal. If you want to ask a question, visit the Study help desk, the Staff lounge, IRC channel or ask me personally on my talk page. For site news, see the Bulletin board. It might be a good idea to add this page to your "watchlist" so that you can see when any new information is posted there. You can do that by clicking the tab labeled "watch" at the top of the page.

Good luck!

You might also be interested to read our Cookbook policy page, and talk to other Cookbook editors. Webaware talk 23:27, 31 May 2007 (UTC)

title: User talk:VanillaXtract


text:
Bartending/Cocktails/Screaming Orgasm

Screaming Multiple Orgasm Recipe

Ingredients:
 * 1.0 Tbsp Galliano
 * 1.5 Tbsp Irish Cream
 * 2.0 Tbsp Milk
 * 1.5 Tbsp Triple sec

Screaming Orgasm Ingredients:
 * 1 Baileys
 * 1 Cointreau
 * 1 Galliano Liqueur (the yellow one)

title: Bartending/Cocktails/Screaming Orgasm


text:
User:Abdelazer

I'm Keith Fahlgren (that string should be unique enough to find me)

title: User:Abdelazer


text:
Renewable Energy

This book will attempt to explain the concept of renewable energy and give details of the various methods of harnessing renewable energy sources.

Contents

 * 1) /About/ this book
 * 2) /Introduction/ to Renewable Energy
 * 3) /Bio Energy/
 * 4) /Solar Thermal/
 * 5) /Geothermal/
 * 6) /Ocean Thermal/
 * 7) /Wind/
 * 8) /Hydro Energy/
 * 9) /Solar Photovoltaic (PV)/
 * 10) /Tidal Energy/
 * 11) /Wave Energy/
 * 12) /Energy Storage/
 * /Chemical/
 * /Mechanical/
 * /Thermal Energy/

 * 1) /More on Specific Renewable energy sources/
 * /Biofuels/
 * /Biofuel from Algae/
 * /Biofuel from Land Based Plants/
 * /External Links/

title: Renewable Energy


text:
User:Darklama/test.js

function glossary { $('div.glossary > dt').each( function {   var dt = $(this), id = dt.children(':first-child').text.replace(/^\s+|\s+$/, "").replace(/\s+/g, "_");    dt.before('');  } }

$(document).ready(glossary);

title: User:Darklama/test.js


text:
Algebra/Other Types of Graphs

Sample Graphs of Various Functions and Relations
y = |x|

y = x2

y = 1/x

y =x         y = -x           y = |x|         y=-|x|           y=x2 y=-x2        y=x3         y = 1/x       y=-1/(x-1)

y=x! other functions and relations in other sections

inequalities              parabolas              y=(10 or e) to the x        y = log x

polynomials

cubics and squares

what this means is that the graphs of y = x^N(even) and y = x^N (odd) will always look in certain ways.

Second Graphing section: translations    symmetries     +/- inversions     inverse relations     ellipse    circle     square roots    inequalities of these

Other functions and relations

Symmetry about: x-axis y-axis y=x y=-x

Translation (shift) in x and y directions

stretching about x-axis or y-axis

asymptotes

inverse functions (to be originally introduced in Functions, graphing aspects covered here)

circles

ellipses

inequalities in non-linear relations

stretching relations about x or y axes

Newton's method
 * Given 0=x^a y^b + x^c y^d etc, can deduce asymptotes/intersects from smallest polygon containing points (a,b) (c,d) etc

References:

1. ELEMENTARY GEOMETRY for College Students, 2nd Edition, by Daniel Alexander and
 * Geralyn Koeberlein, Houghton Mifflin Company, Boston, MA 1999.

2. ALGEBRA AND TRIGONOMETRY with Analytic Geometry, Ninth Edition, by Earl Swokowski
 * and Jeffery Cole, Brooks/Cole Publishing Company 1997.

Pie Chart
Pie charts are best used to compare parts to the whole by percentages. By measuring the number of degrees that a piece of the pie chart is, one can find the percentage it represents.

$$\mbox{degrees} = \mbox{percent} \cdot\frac{360}{100}$$

which simplifies to degrees * 18 / 5

Bar Chart
Bar charts are best for plotting the change in something over a period of time. It is nearly the same as a line chart, except that the points are not connected, and instead extend to the bottom of the chart.

title: Algebra/Other Types of Graphs


text:
Algebra/Probability

Probability is the chance that something will occur. For example, what are the chances that two dice rolled will equal 7? To solve this, a chart can be made of all the pairs of the integers {1, 2, 3, 4, 5, 6} that add up to 7.

 * 1 + 6
 * 2 + 5
 * 3 + 4
 * 4 + 3
 * 5 + 2
 * 6 + 1

note that the first three seem to be the same as the second three. This is because there are two dice, so when the first die gets number X and the second gets Y, it's a different outcome than the first being Y and the second X.

Next, we find out how many possibilities there are in total.

6 possibilities for the first die * 6 possibilities for the second = 36 combinations.

Since 6 out of the 36 combinations add up to 7, the answer is 1/6 or 16.6666666...% or 0.166666666... Usually, probabilities are measured in the first or second way.

Ratios
Quite often, ratios are used to show the probability of an event occurring compared to another event. Be careful! The ratio of heads to tails is 1:1 or 1/1, but the probability of heads is 1:2 or 1/2. Don't confuse these two ways of writing the same thing.

title: Algebra/Probability