text:
User:Linesdata

The Homeschool Curriculum Project is a Wikibooks project to create all the necessary highschool textbooks.

The first step will be deciding which books will are necessary. Please help!! I have started making the list, but please edit and update it. I'm not sure what is wanted for history, do we do a year first of General History, then a year of specific history (ie. American History/Australian History/British History/Spanish History/etc...), and then Government? Or? If that is correct is there only three years of history? Foreign language is a good idea, there should be at least a few options, including Latin, Greek, Hebrew, French, Spanish. Is English done every year?

After it has been decided and agreed what books make up the core curriculum, we probably should start with Public Domain books from Gutenberg and places like that, and update and rewrite them to fit our purposes.

All books are required to conform to Wikibooks policy. Some major policies to be aware of when contributing are WB:NPOV, WB:NOR, WB:COPY, WB:DP and WB:NP.
 * For help finding Public Domain books, read How to obtain public domain books.

Freshman Year (9th Grade)

 * Mathematics 1
 * General Science

Sophomore Year (10th Grade)

 * Mathematics 2
 * Biology

Junior Year (11th Grade)

 * Mathematics 3
 * Chemistry

Senior Year (12th Grade)

 * Mathematics 4
 * Physics

title: User:Linesdata


text:
XQuery/XQuery and XSLT

Motivation
You want to create a RESTful web service that executes an XSLT transform on an XML document.

Method
XQuery is superior to XSLT in many ways. XQuery is designed to be brief and concise programming language that interleaves XML and functional language statements. Therefore, XQuery programs are usually much smaller than XSLT. XQuery processors are also designed to use indexes so that XQueries over large data sets can run quickly. But unfortunately there are still some times when you must use XSLT. One example of this is in-browser transforms. The eXist database comes with an XQuery function that allows you to transform an XML file using XSLT.

Creating an XSLT service
eXist includes a function to call an XSLT transform is the following:

transform:transform($input as node?, $stylesheet as item, $params as node?) node?

where: $input is the node tree to be transformed $stylesheet is either a URI or a node to be transformed. If it is an URI, it can either point to an external location or to an XSL stored in the db by using the 'xmldb:' scheme. $params are the optional XSLT name/value parameters with the following structure:

The result is zero or one nodes. The namespace of the transform module is http://exist-db.org/xquery/transform.

The transform:transform function can be used to provide a service which accepts the url of an XML file, the url of an XSLT script and any other parameters which are passed to the stylesheet.

Currently output is text/html.

Checking XSLT Version
The following XSLT is useful for checking what version of XSLT you are running.

Form-based search
In this example, an XML file on one host is transformed by a XSLT script on another. The XSLT script defines a form to allow the use to select a subset of the entries in the XML file, followed by the search results, if any.
 * 1) Stylesheet
 * 2) Data
 * 3) Search Whisky data

A sequence diagram describes the interaction involved:

Sequence Diagram

Page Scraping Example
see ../Page scraping and Yahoo Weather/

Using XSLT Imports
XSLT allows you to call a stylesheet that imports a common library of other XSLT templates. But not all of the XSLT import path statements will work within eXist. In the following example we will use a XSLT style sheet that imports another style sheet. The following assumes you have a collection called /db/test/xslt and all the files are placed in that collection.

XQuery XSLT Test Program
return Demonstration of running XSLT within an XQuery Demonstration of running XSLT within an XQuery { transform:transform($input, doc("/db/test/xslt/style.xsl"), ) }

Top-Level Style.xsl
In the second line, the following imports do work as expected:

But you will note that using the following does not work:

XForms Example
You can also create a simple XForms example that serves as a front end to this script. See the XRX wikibook for an example of this XForms front end.

  XForms Test Program  Name:

let $serialization-options := 'method=xml media-type=text/xml omit-xml-declaration=yes indent=no'

let $params :=

return transform:transform($form, $transform, $params, $serialization-options)

Caching Management
By default, once a document has been transformed it resides in the cache. This is very good for performance reasons if a file needs to be retransformed but sometimes if the source file changes the transform needs to be rerun.

You can disable caching by changing the configuration file. In the file conf.xml change the @caching value from yes to no.:

http://demo.exist-db.org/exist/xquery.xml#N10375

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: XQuery/XQuery and XSLT


text:
Talk:XQuery/XQuery and XSLT

Cacheing seems to be a problem with this service

title: Talk:XQuery/XQuery and XSLT


text:
Minix 3/Minix 3 on VMware

Run MINIX 3 on VMWare

 * Download the latest Minix VMWare machine from

Installing VMWare
The following procedure was tested on Ubuntu. sudo ./vmware-install.pl
 * Install the VMWare server from (you will need a free VMWare serial number to install, you can obtain it from ).
 * To install the VMWare server type:
 * For a standard installation, hitting return for every question should work just fine.

Setting up the Virtual Machine
vmware
 * To start the VMWare server console type
 * Choose 'create a new virtual machine'
 * Create a custom virtual machine if the machine is on an external device, choose typical otherwise
 * When prompted for a virtual machine location, browse to the downloaded Minix 3 VMWare machine
 * You can now start Minix 3 from the VMWare server console

title: Minix 3/Minix 3 on VMware


text:
User:Prasuk historyk~enwikibooks

Hello I'm Prasuk, I live in Bydgoszcz Poland.

About me
My main hobbies are English, computer science, history, medicine, Harry Potter series, watching TV. My the biggest hobbies are English and computer science. I like playing computer games. From Harry Potter series my favourite book is Harry Potter and the Dealthly Hallows. My favourites characters from Harry Potter series are Hermione and Luna. In computer science my favourites domains are operating systems. In history my favourite domain is Polish history, because I'm from Poland. In medicine my favourite domain is Pulmonology. And I like watching "Braceface", my favourites characters from Braceface cartoon are Sharon and Alden. Next to I like watching "Na dobre i Na złe". Born many years ago. In September I'll have been learning English for eight years.

What would I like to do here? Here I add interwiki to other wikibooks, sometimes vote in RFA. And I am going to create articles in english.

pl:user:Prasuk historyk de:Benutzer:Prasuk historyk fr:Utilisateur:Prasuk historyk

title: User:Prasuk historyk~enwikibooks


text:
User talk:Muzzledmckay

Come introduce yourself at the new users page. If you have any questions, you can ask there or contact me personally.– Mike.lifeguard  | talk 14:52, 3 November 2007 (UTC)

Boy Scout Troop 159
I'm not sure if this page is appropriate for Wikibooks. WB is for textbooks, not encyclopedic articles. For more information, see WB:WIW. Hoogli (talk) 18:51, 13 January 2008 (UTC)

title: User talk:Muzzledmckay


text:
User talk:72.82.6.137

– Mike.lifeguard  | talk 15:15, 3 November 2007 (UTC)

title: User talk:72.82.6.137


text:
User talk:Prasuk historyk~enwikibooks

You may want to enable the email feature instead of having your email in plaintext on your userpage. Head to my preferences (top left) to do so. More useful stuff below:

Come introduce yourself at the new users page. If you have any questions, you can ask there or contact me personally.– Mike.lifeguard  | talk 15:17, 3 November 2007 (UTC)

User name change
Are you sure you want to change your username to "Prasuk historyk"? --Derbeth talk 22:15, 10 January 2008 (UTC)
 * Yes, I want change my username from HistoryckCKU to Prasuk historyk. HistoryczkCKU (talk) 10:39, 11 January 2008 (UTC)

Your account will be renamed
Hello,

The developer team at Wikimedia is making some changes to how accounts work, as part of our on-going efforts to provide new and better tools for our users like cross-wiki notifications. These changes will mean you have the same account name everywhere. This will let us give you new features that will help you edit and discuss better, and allow more flexible user permissions for tools. One of the side-effects of this is that user accounts will now have to be unique across all 900 Wikimedia wikis. See the announcement for more information.

Unfortunately, your account clashes with another account also called Prasuk historyk. To make sure that both of you can use all Wikimedia projects in future, we have reserved the name Prasuk historyk~enwikibooks that only you will have. If you like it, you don't have to do anything. If you do not like it, you can pick out a different name.

Your account will still work as before, and you will be credited for all your edits made so far, but you will have to use the new account name when you log in.

Sorry for the inconvenience.

Yours, Keegan Peterzell Community Liaison, Wikimedia Foundation 23:37, 17 March 2015 (UTC)

Renamed
 This account has been renamed as part of single-user login finalisation. If you own this account you can |log in using your previous username and password for more information. If you do not like this account's new name, you can choose your own using this form after logging in: . -- Keegan (WMF) (talk) 05:23, 19 April 2015 (UTC)

title: User talk:Prasuk historyk~enwikibooks


text:
Programmable Logic/VHDL Sequential Statement

Sequential statements are used in processes to specify how signals are assigned. The process is executed in order as a whole. After all the sequential statements in the process are executed the signals are assigned their new values.

Assignment
A signal is assigned as follows: This statement can be read as "assign sQ the value of sQ_next on the next simulation cycle.

So far, in the if statements only signals were used. The same rules apply when using variables, with a single difference. Like a signal, if a variable is assigned to only in some branches of the if statement, then the previous value is preserved by feedback. Unlike the case when a signal is used, the reading and writing of a variable in the same process will result in feedback only if the read occurs before the write. In this case, the value read is the previous value of the variable. In the case when a signal is used, a read and a write in the same process will always result in feedback. This observation may be used to create registers or counters using variables. Remember that a sequential process is interpreted by synthesis by placing a flip-flop or register on every signal assigned to in the process. This means that normally variables are not written to flip-flops or registers. However, if there is feedback of a previous variable value, then this feedback is implemented via a flip-flop or register to make the process synchronous. Example 6.21 describes a counter using the unsigned integer type. When a value of type unsigned is incremented, if the value is the highest value of the range, then the lowest value of the range is obtained.

Example 6.21 In this example, in the else branch of the if statement the previous value of the count variable is being read to calculate the next value. This results in a feedback. Note that in this example actually two registers are created. According to the feedback rules, variable count will be registered. Signal result will also be registered, because all signals assigned to in a sequential process will be registered. This extra register will always contain the same value as the register for variable count. The synthesis tool will normally eliminate this redundant register.

CASE Statements
A case statement is a way to describe a conditional assignment with a large number of choices. Case statements are often synthesized as multiplexers.


text: User talk:211.24.164.133

title: User talk:211.24.164.133


text:
Programmable Logic/VHDL General Syntax

VHDL's syntax is derived from ADA. It is strongly typed and case insensitive.

Identifiers
An identifier in VHDL must begin with a letter and can be any combination of letters, digits, and underscore (_).

Comments
A comment in VHDL is denoted with a "--": Everything after the "--" to the end of the line is considered a comment.

Keywords
The following words are VHDL keywords and cannot be used for identifiers (signal names, process names, entity names, etc...)

Top

VHDL 1987
This is an incomplete list...

Top

VHDL 1993
VHDL 1987 keywords and:

Top

VHDL 2000
VHDL 1993 and 1987 keywords, additionally:

Top

VHDL 2002
VHDL 1993, 1987 and 2000 keywords, additionally:

Top

VHDL 2008
VHDL 1993, 1987, 2000 and 2002 keywords, additionally:

Top

VHDL 2019
VHDL 1993, 1987, 2000, 2002 and 2008 keywords, additionally:

Alphabetical Reference

A
abs             access          after           alias           all             and             architecture    array

assert

attribute

B

begin

block

body

buffer

bus

C

case

component

configuration

constant

D

disconnect

downto

E

else

elsif

end

entity

exit

F

 file

 for

 function

G

 generate

 generic

 guarded

I

 if

 in

 inout

 is

L

 label

 library

 linkage

 loop

M

 map

 mod

N

 nand

 new

 next

 nor

 not

 null

O

 of

 on

 open

 or

 others

 out

P

 package

 port

 procedure

 process

R

 range

 record

 register

 rem

 report

 return

S

 select

 severity

 signal

 subtype

T

 then

 to

 transport

 type

U

 units

 until

 use

V

 variable

W

 wait

 when

 while

 with

X

 xor

Z

links to other references
https://peterfab.com/ref/vhdl/vhdl_renerta/source/vhd00001.htm

abs
- The abs command in VHDL is a predefined function that returns the absolute value of a numeric argument.
 * Introduction

For example,  returns , and   returns.

The abs command can be used with any numeric type, such as integer, real, or fixed-point.

The 1987 version of VHDL saw the introduction of abs.
 * Notes

The abs command is synthesiseable.

synthesizable, Rules, tips, common mistakes, related keywords etc

 * Syntax

Top

access
- In VHDL, an access type is like a pointer in other programming languages. It allows you to create and manipulate data that is created dynamically during simulation. This means that you can create new data on the fly, and the size of the data doesn’t have to be known in advance.
 * Introduction

For example, imagine you want to create a list of numbers, but you don’t know how many numbers there will be. You could use an access type to create a linked list, where each item in the list points to the next item. This way, you can add as many items to the list as you want, without having to know the size of the list beforehand.

Access types are very useful for modeling potentially large structures, like memories or FIFOs, but they are not supported by synthesis tools.

The 1987 version of VHDL saw the introduction of access.
 * Notes

Not synthesizable

See https://peterfab.com/ref/vhdl/vhdl_renerta/source/vhd00001.htm

 * Syntax

Top

after
- The VHDL command “after” is used to introduce a delay in the assignment of a signal. It is used to specify the time after which the signal should be assigned a new value. For example,  means that the signal x will be assigned the value '1' after 10 nanoseconds have passed.
 * Introduction

The 1987 version of VHDL saw the introduction of after.
 * Notes

Not Synthesisable.

Delays are not supported in functions.

It is important to note that the “after” command has to do with the delay model. In the default VHDL inertial delay, your second “slower” signal assignment statement cancels the future update of the first. You could schedule multiple updates in one statement to correct this, for example:.

see http://gmvhdl.com/delay.htm

 * Syntax

Top

alias
-
 * Introduction

Aliases, are alternative names for existing objects, such as signals, variables, constants, types, etc. Aliases can be useful for making your code more readable, avoiding name conflicts, or accessing parts of an array or a record.

You can also use a special syntax << ... >> to create external names, which are aliases that can access objects in other design units or hierarchy levels

The 1987 version of VHDL saw the introduction of alias.
 * Notes

Aliases are local to the declarative region where they are defined, and they cannot be redefined or overridden.

Aliases cannot be used as targets of assignments.

Aliases can be used in any place where the original name can be used, such as expressions, statements, or subprogram calls.

See https://peterfab.com/ref/vhdl/vhdl_renerta/mobile/source/vhd00003.htm

 * Syntax

Top

all
-
 * Introduction

The keyword "all" in a context declaration is a way to specify a set of libraries, packages, and entities that are used in a design unit.

For example, you can write:

This means that all the design units that reference this context will have access to the ieee library and the packages std_logic_1164 and numeric_std. The keyword "all" in this case means that all the design units in the current working library can use this context.

Since VHDL-2008, the keyword "all" is used to indicate that the sensitivity list of a process should be inferred by the tool, rather than explicitly specified by the designer.
 * Alternative

The sensitivity list is a list of signals that trigger the execution of the process when they change their values.

For example, consider the following process that implements a D flip-flop with asynchronous reset:

The sensitivity list of this process is (i_clk, i_rst), which means that the process will run whenever i_clk or i_rst changes. However, we can also use the keyword "all" to let the tool infer the sensitivity list for us:

This is equivalent to the previous process, as the tool will automatically determine that i_clk and i_rst are the only signals that affect the behavior of the process.

Using the keyword "all" can be convenient and less error-prone, as it avoids the need to manually update the sensitivity list when adding or removing signals from the process.

Some tools may not support this feature, or may generate different results depending on the sensitivity list inference algorithm so check the tool documentation and verify the synthesis and simulation results before using the keyword "all" in a clocked process.

The 1987 version of VHDL saw the introduction of all.
 * Notes

Top

and
-
 * Introduction

This keyword is used to represent the logical AND operation, which is a basic building block in digital logic circuits.

The `AND` operator performs a bitwise AND operation if the operands are vectors (arrays of bits like std_logic_vector) or performs a logical AND operation if the operands are of type bit or boolean.

If all inputs are ‘1’, the result is ‘1’. Otherwise, the result is ‘0’.

This behavior mimics the functionality of an AND gate in digital electronics.

The 1987 version of VHDL saw the introduction of and.
 * Notes

see

https://fpgatutorial.com/vhdl-logical-operators-and-signal-assignments-for-combinatorial-logic/
 * Syntax

In this example, signal  will be ‘1’ if both   and   are ‘1’. Otherwise,  will be ‘0’.

Top

architecture
-
 * Introduction

The term "Architecture" assumes a pivotal role. It serves as a formal blueprint associated with an entity declaration, tasked with elucidating the internal organization and operation of a design entity. In essence, an architecture delineates the behavior, data flow, or structural composition of the design entity with precision and rigor. This technical construct finds utility in describing the intricate relationships between input and output ports within a design, encompassing two primary components: declarations and concurrent statements. Declarations encompass various elements, including types, signals, constants, subprograms, components, and groups, while concurrent statements articulate how inputs interact with outputs, with diverse statement types allowing for flexibility in expressing design functionality. Architecture, in the context of VHDL, embodies a systematic and unambiguous approach to defining the fundamental characteristics of digital systems, laying the foundation for their subsequent implementation and analysis.

The architecture is used to detail the behavior, data flow, or structure of a design entity.

An architecture linked to an entity primarily delineates the inner relationships between the input and output ports of the entity. It consists of two primary components: declarations and concurrent statements.

The declarative part of an architecture encompasses various types of declarations, such as types, signals, constants, subprograms (functions and procedures), components, and groups. Detailed information on each of these can be found in their respective topics.

Concurrent statements, on the other hand, describe how inputs relate to outputs within the architecture. These relationships can be expressed through diverse types of statements, including concurrent signal assignments, process statements, component instantiations, concurrent procedure calls, generate statements, concurrent assertion statements, and block statements. These statements can be written in various styles, such as structural, dataflow, behavioral (functional), or mixed, depending on the intended design.

Structural descriptions rely on component instantiation and generate statements, enabling the creation of hierarchical projects that range from simple gates to intricate components, encompassing entire subsystems. These components connect through ports, as illustrated in Example 1 for a BCD decoder.

Dataflow descriptions employ concurrent signal assignment statements. Each statement can activate when any of its input signals change, describing the circuit's behavior and structure, as showcased in Example 2.

In contrast, a behavioral description, as demonstrated in Example 3, includes only one or more processes, each containing sequential statements. This approach focuses solely on the expected functionality of the circuit, without specifying hardware implementation details.

A mixed architecture description, as seen in Example 4, combines both behavioral and structural elements within the same architecture body. The 1987 version of VHDL saw the introduction of architecture.
 * Notes

An entity can have multiple architectures, but an architecture cannot be assigned to different entities.

An architecture must be associated with an entity.

All declarations within an entity are entirely visible and accessible within any architecture assigned to that entity.

Different types of statements, such as processes, blocks, concurrent signal assignments, component instantiations, etc., can coexist within the same architecture.

 * Syntax

Example 1:

Example 2:

Example 3:

Example 4:

Top

array
- Introduction to the Keyword "Array" in VHDL:
 * Introduction

In VHDL, the keyword "Array" is a versatile data type that plays a pivotal role in structuring and organising data. In VHDL, an array is formally defined as a type whose value consists of elements of the same subtype, making it ideal for managing homogeneous data sets. What distinguishes each element within an array is an index (or indices, for multidimensional arrays) associated with it. These indices are required to be values of a discrete type and must fall within the specified index range.

In simpler terms, an array is like a container that holds elements of a consistent type, and each element is uniquely identified by its index. The number of indices directly corresponds to the number of dimensions; for example, a one-dimensional array has one index, while a two-dimensional array has two.

Arrays in VHDL come in two flavors: constrained and unconstrained. A constrained array has a fixed size, determined either by a discrete type mark or a specified range. In contrast, an unconstrained array does not have a predefined size; its size is only determined when you declare an object of that type.

For instance, VHDL's Package STANDARD includes predefined unconstrained array types like STRING and BIT_VECTOR. These arrays are widely used, with STRING elements indexed by positive values and BIT_VECTOR elements indexed by natural values.

Arrays in VHDL can be manipulated using various techniques such as indexing, concatenation, aggregates, and slices. These methods provide flexibility in accessing and assigning values to array elements, making them a crucial component of VHDL programming.

It's worth noting that while arrays are a powerful tool in VHDL, not all synthesis tools support multidimensional arrays. There are exceptions, such as two-dimensional "vectors of vectors," and some synthesis tools allow limited support for two-dimensional arrays.

In summary, arrays in VHDL are fundamental data structures that allow you to efficiently manage and manipulate collections of data, making them a key element in VHDL programming.

The 1987 version of VHDL saw the introduction of array.
 * Notes
 * Syntax

Top

assert
-
 * Introduction

The 1987 version of VHDL saw the introduction of assert.
 * Notes
 * Syntax

Top

attribute
-
 * Introduction

The 1987 version of VHDL saw the introduction of attribute.
 * Notes
 * Syntax

Top

begin
-
 * Introduction

The 1987 version of VHDL saw the introduction of begin.
 * Notes
 * Syntax

Top

block
-
 * Introduction

The 1987 version of VHDL saw the introduction of block.
 * Notes
 * Syntax

Top

body
-
 * Introduction

The 1987 version of VHDL saw the introduction of body.
 * Notes
 * Syntax

Top

buffer
-
 * Introduction

The 1987 version of VHDL saw the introduction of buffer.
 * Notes
 * Syntax

Top

bus
-
 * Introduction

The 1987 version of VHDL saw the introduction of bus.
 * Notes
 * Syntax

Top

case
-
 * Introduction

The 1987 version of VHDL saw the introduction of case.
 * Notes
 * Syntax

Top

component
-
 * Introduction

The 1987 version of VHDL saw the introduction of component.
 * Notes
 * Syntax

Top

configuration
-
 * Introduction

The 1987 version of VHDL saw the introduction of configuration.
 * Notes
 * Syntax

Top

constant
-
 * Introduction

The 1987 version of VHDL saw the introduction of constant.
 * Notes
 * Syntax

Top

disconnect
-
 * Introduction

The 1987 version of VHDL saw the introduction of disconnect.
 * Notes
 * Syntax

Top

downto
-
 * Introduction

The 1987 version of VHDL saw the introduction of downto.
 * Notes
 * Syntax

Top

else
-
 * Introduction

The 1987 version of VHDL saw the introduction of else.
 * Notes
 * Syntax

Top

elsif
-
 * Introduction

The 1987 version of VHDL saw the introduction of elsif.
 * Notes
 * Syntax

Top

end
-
 * Introduction

The 1987 version of VHDL saw the introduction of end.
 * Notes
 * Syntax

Top

entity
-
 * Introduction

The 1987 version of VHDL saw the introduction of entity.
 * Notes
 * Syntax

Top

exit
-

 * Introduction

The 1987 version of VHDL saw the introduction of exit.
 * Notes
 * Syntax

Top

file
-

 * Introduction

The 1987 version of VHDL saw the introduction of file.
 * Notes
 * Syntax

Top

for
-

 * Introduction

The 1987 version of VHDL saw the introduction of for.
 * Notes
 * Syntax

Top

function
-

 * Introduction

The 1987 version of VHDL saw the introduction of function.
 * Notes
 * Syntax

Top

generate
-

 * Introduction

The 1987 version of VHDL saw the introduction of generate.
 * Notes
 * Syntax

Top

generic
-

 * Introduction

The 1987 version of VHDL saw the introduction of generic.
 * Notes
 * Syntax

Top

guarded
-

 * Introduction

The 1987 version of VHDL saw the introduction of guarded.
 * Notes
 * Syntax

Top

if
-

 * Introduction

The 1987 version of VHDL saw the introduction of if.
 * Notes
 * Syntax

Top

in
-

 * Introduction

The 1987 version of VHDL saw the introduction of in.
 * Notes
 * Syntax

Top

inout
-

 * Introduction

The 1987 version of VHDL saw the introduction of inout.
 * Notes
 * Syntax

Top

is
-

 * Introduction

The 1987 version of VHDL saw the introduction of is.
 * Notes
 * Syntax

Top

label
-

 * Introduction

The 1987 version of VHDL saw the introduction of label.
 * Notes
 * Syntax

Top

library
-

 * Introduction

The 1987 version of VHDL saw the introduction of library.
 * Notes
 * Syntax

Top

linkage
-

 * Introduction

The 1987 version of VHDL saw the introduction of linkage.
 * Notes
 * Syntax

Top

loop
-

 * Introduction

The 1987 version of VHDL saw the introduction of loop.
 * Notes
 * Syntax

Top

map
-

 * Introduction

The 1987 version of VHDL saw the introduction of map.
 * Notes
 * Syntax

Top

mod
-

 * Introduction

The 1987 version of VHDL saw the introduction of mod.
 * Notes
 * Syntax

Top

nand
-

 * Introduction

The 1987 version of VHDL saw the introduction of nand.
 * Notes
 * Syntax

Top

new
-

 * Introduction

The 1987 version of VHDL saw the introduction of new.
 * Notes
 * Syntax

Top

next
-

 * Introduction

The 1987 version of VHDL saw the introduction of next.
 * Notes
 * Syntax

Top

nor
-

 * Introduction

The 1987 version of VHDL saw the introduction of nor.
 * Notes
 * Syntax

Top

not
-

 * Introduction

The 1987 version of VHDL saw the introduction of not.
 * Notes
 * Syntax

Top

null
-

 * Introduction

The 1987 version of VHDL saw the introduction of null.
 * Notes
 * Syntax

Top

of
-

 * Introduction

The 1987 version of VHDL saw the introduction of of.
 * Notes
 * Syntax

Top

on
-

 * Introduction

The 1987 version of VHDL saw the introduction of on.
 * Notes
 * Syntax

Top

open
-

 * Introduction

The 1987 version of VHDL saw the introduction of open.
 * Notes
 * Syntax

Top

or
-

 * Introduction

The 1987 version of VHDL saw the introduction of or.
 * Notes
 * Syntax

Top

others
-

 * Introduction

The 1987 version of VHDL saw the introduction of others.
 * Notes
 * Syntax

Top

out
-

 * Introduction

The 1987 version of VHDL saw the introduction of out.
 * Notes
 * Syntax

Top

package
-

 * Introduction

The 1987 version of VHDL saw the introduction of package.
 * Notes
 * Syntax

Top

port
-

 * Introduction

The 1987 version of VHDL saw the introduction of port.
 * Notes
 * Syntax

Top

procedure
-

 * Introduction

The 1987 version of VHDL saw the introduction of procedure.
 * Notes
 * Syntax

Top

process
-

 * Introduction

The 1987 version of VHDL saw the introduction of process.
 * Notes
 * Syntax

Top

range
-

 * Introduction

The 1987 version of VHDL saw the introduction of range.
 * Notes
 * Syntax

Top

record
-

 * Introduction

The 1987 version of VHDL saw the introduction of record.
 * Notes
 * Syntax

Top

register
-

 * Introduction

The 1987 version of VHDL saw the introduction of register.
 * Notes
 * Syntax

Top

rem
-

 * Introduction

The 1987 version of VHDL saw the introduction of rem.
 * Notes
 * Syntax

Top

report
-

 * Introduction

The 1987 version of VHDL saw the introduction of report.
 * Notes
 * Syntax

Top

return
-

 * Introduction

The 1987 version of VHDL saw the introduction of return.
 * Notes
 * Syntax

Top

select
-

 * Introduction

The 1987 version of VHDL saw the introduction of select.
 * Notes
 * Syntax

Top

severity
-

 * Introduction

The 1987 version of VHDL saw the introduction of severity.
 * Notes
 * Syntax

Top

signal
-

 * Introduction

The 1987 version of VHDL saw the introduction of signal.
 * Notes
 * Syntax

Top

subtype
-

 * Introduction

The 1987 version of VHDL saw the introduction of subtype.
 * Notes
 * Syntax

Top

then
-

 * Introduction

The 1987 version of VHDL saw the introduction of then.
 * Notes
 * Syntax

Top

to
-

 * Introduction

The 1987 version of VHDL saw the introduction of to.
 * Notes
 * Syntax

Top

transport
-

 * Introduction

The 1987 version of VHDL saw the introduction of transport.
 * Notes
 * Syntax

Top

type
-

 * Introduction

The 1987 version of VHDL saw the introduction of type.
 * Notes
 * Syntax

Top

units
-

 * Introduction

The 1987 version of VHDL saw the introduction of units.
 * Notes
 * Syntax

Top

until
-

 * Introduction

The 1987 version of VHDL saw the introduction of until.
 * Notes
 * Syntax

Top

use
-

 * Introduction

The 1987 version of VHDL saw the introduction of use.
 * Notes
 * Syntax

Top

variable
-

 * Introduction

The 1987 version of VHDL saw the introduction of variable.
 * Notes
 * Syntax

Top

wait
-

 * Introduction

The 1987 version of VHDL saw the introduction of wait.
 * Notes
 * Syntax

Top

when
-

 * Introduction

The 1987 version of VHDL saw the introduction of when.
 * Notes
 * Syntax

Top

while
-

 * Introduction

The 1987 version of VHDL saw the introduction of while.
 * Notes
 * Syntax

Top

with
-

 * Introduction

The 1987 version of VHDL saw the introduction of with.
 * Notes
 * Syntax

Top

xor
-

 * Introduction

The 1987 version of VHDL saw the introduction of xor.
 * Notes

title: Programmable Logic/VHDL General Syntax


text:
Programmable Logic/FPGAs

FPGA

FPGA stands for "Field Programmable Gate Array", and is a type of VLSI that is programmable (and reprogrammable) in "the field". FPGAs can be programmed by using an HDL, and those programs get downloaded to the FPGA from a host computer system.

A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories.

A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer (hence the term "field programmable", i.e. programmable in the field) so that the FPGA can perform whatever logical function is needed.

FPGAs are generally slower than their application-specific integrated circuit (ASIC) counterparts, can't handle as complex a design, and draw more power. However, they have several advantages such as a shorter time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. The development of these designs is made on regular FPGAs and then migrated into a fixed version that more resembles an ASIC. Complex programmable logic devices, or CPLDs, are another alternative.

Applications
Applications of FPGAs include DSP, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas. FPGAs originally began as competitors to CPLDs and competed in a similar space, that of glue logic for PCBs. As their size, capabilities, and speed increased, they began to take over larger and larger functions to the state where some are now marketed as full systems on chips (SOC).

FPGAs especially find applications in any area or algorithm that can make use of the massive parallelism offered by their architecture. One such area is code breaking, in particular brute-force attack, of cryptographic algorithms.

FPGAs are also widely used for systems validation including pre-silicon validation, post-silicon validation, and firmware development. This allows chip companies to validate their design before the chip is produced in the factory, reducing the time to market.

Architecture
An application circuit must be mapinto an FPGA with adequate resources.

Logic block
The typical FPGA logic block consists of a 4-input lookup table (LUT), and a flip-flop.

There is only one output, which can be either the registered or the unregistered LUT output. The logic block has four inputs for the LUT and a clock input. Since clock signals (and often other high-fanout signals) are normally routed via special-purpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed.

Signal Routing
Each input is accessible from one side of the logic block, while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block.

Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it.

Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it.

Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch box, longer paths can be constructed. For higher speed interconnect, some FPGA architectures use longer routing lines that span multiple logic blocks.

Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.

FPGA design and programming
To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design. Common HDLs are VHDL and Verilog. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA.

In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to stimulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.

In an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level of the design. Companies such as Cadence, Synopsys and Celoxica are promoting SystemC as a way to combine high level languages with concurrency models to allow faster design cycles for FPGAs than is possible using traditional HDLs. Approaches based on standard C or C++ (with libraries or other extensions allowing parallel programming) are found in the Catapult C tools from Mentor Graphics, and in the Impulse C tools from Impulse Accelerated Technologies. Annapolis Micro Systems, Inc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry. Languages such as SystemVerilog, SystemVHDL, and Handel-C (from Celoxica) seek to accomplish the same goal, but are aimed at making existing hardware engineers more productive versus making FPGAs more accessible to existing software engineers.

Cores
Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into the silicon. Having these common functions embedded into the silicon reduces the area required and gives those functions increased speed compared to building them from primitives. Examples of these include multipliers, generic DSP blocks, embedded processors, high speed IO logic and embedded memories.

To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free, and typically released under proprietary licenses). Other predefined circuits are available from developer communities such as OpenCores.org (typically "free", and released under the GPL, BSD or similar license), and other sources.

Embedded Memory
Sram

Embedded processors
Embedded processors targetting FPGAs are provided as softcores IPs, described in an HDL, such as VHDL or Verilog. Most of the softcores are provided through FPGA vendors' proprietary design software and target their specific devices.

title: Programmable Logic/FPGAs


text:
Programmable Logic/CPLDs

CPLD stands for Complex Programmable Logic Device. They are similar in concept to FPGA, but operate using different methods.

title: Programmable Logic/CPLDs


text:
Programmable Logic/JTAG

JTAG
JTAG stands for "Joint Test Action Group" and is an industry standard interface for programming, testing and debugging.

Some microcontrollers can be programmed through their JTAG port.

title: Programmable Logic/JTAG


text:
More C++ Idioms/Resource Return

= Resource Return =

Intent
To convey ownership transfer (of a resource) explicitly in the return type of a factory function.

Motivation
Factory functions are often used to create new resources and return them to the caller. A new resource could be raw memory, dynamically allocated object, database cursors/connections, locks and so on. An important question about resources is who owns the resource and who releases it? Many times, interfaces are developed where the caller is implicitly responsible for resource release. If the caller is not aware of this fact or simply forgets to take correct steps, it gives rise to an easy-to-use-incorrectly kind of interface. Following code snippet shows an example.

Resource Return Idiom provides different alternatives to rectify the situation and results into (somewhat) hard-to-use-incorrectly interfaces.

Solution and Sample Code
The solution is to wrap the resource in a resource-management smart pointer and return the smart pointer instead of the raw pointers. Simplest form of Resource Return Idiom is shown in the code snippet below.

There are several issues to be considered while determining the type of resource-management smart pointer to use to return a resource. Possible options are:
 * std::auto_ptr
 * boost::shared_ptr / std::shared_ptr (as of C++11)
 * std::unique_ptr in C++0x
 * User defined Handle/Body idiom

An excellent discussion of pros and cons of choosing one over the other are discussed at length by Scott Meyers in his article The Resource Return Problem. As long as custom deletion functionality (other than plain old delete) is not required, auto_ptrs are a quick way to use the Resource Return idiom as shown above. auto_ptrs give exclusive but transferable ownership of resources which becomes very clear just by looking at the interface. For dynamically allocated pointer-returning factory functions, boost::shared_ptr is a also good choice because it offers normal copy-semantics (e.g., it can be stored in STL containers). It also allows changes to resource release policy from normal delete operation to custom deletion without disturbing clients.

When exclusive ownership is involved in case of Resource Return idiom, Move Constructor idiom is often useful while transferring ownership of resources.

Related Idioms

 * Resource Acquisition Is Initialization (RAII)
 * Move Constructor

title: More C++ Idioms/Resource Return


text:
User:MaxSem

 * m:User:MaxSem
 * w:ru:User:MaxSem
 * w:en:User:MaxSem

title: User:MaxSem


text:
Muggles' Guide to Harry Potter/Characters/Nagini

Overview
Nagini is a snake, a large one, and Lord Voldemort's pet.

Goblet of Fire
We first see Nagini in Riddle Manor, to which Lord Voldemort has returned while he prepares for his full revival. Nagini, out hunting, returns to Voldemort, passing Frank Bryce in the hall, and reports on Frank's presence to Voldemort, whereupon Voldemort has Wormtail bring Frank into the room. Voldemort then kills Frank. The conversation between Voldemort and Wormtail leads us to believe that Wormtail is milking Nagini for something, most likely venom, which is keeping Voldemort alive.

When Harry is bound to the gravestone in the climactic battle at the end of the book, Nagini circles around him; Voldemort, now returned, promises Nagini that she will be allowed to eat Harry after the evening's proceedings are done.

Order of the Phoenix
While it is never stated explicitly, it is almost certain that Nagini is the snake that attacks Arthur Weasley just before Christmas Day.

Half-Blood Prince
In discussing the probable artifacts that have been turned into Horcruxes, Professor Dumbledore suggests to Harry that Voldemort's pet snake is acting rather suspiciously un-snake-like, and quite possibly is carrying a Horcrux. Harry asks if living creatures can be Horcruxes, and Dumbledore says that they can, although it is risky, of course, as living things can be killed.

Deathly Hallows
Nagini is present at the council meeting with Voldemort and his Death Eaters. Voldemort, testing Lucius Malfoy's wand, kills Charity Burbage, then tells Nagini that it is dinner time. Nagini then consumes Charity's dead body.

When Harry and Hermione are visiting Godric's Hollow, they meet with Bathilda Bagshot. Bathilda invites them to her house, then gets Harry to follow her to a room upstairs. It turns out that Bathilda is, in fact, dead, and is being animated by Nagini who is inside her. Nagini notifies Voldemort that she has trapped Harry, then emerges from the remains of Bathilda and attacks. While she bites Harry, her instructions are to hold him, so she does not poison him. With Hermione's help, Harry manages to escape from Nagini.

When Voldemort learns that his Horcruxes are being systematically stolen and destroyed, he tells Nagini that she will have to stay close by him for a while. Apparently, she is with him as he checks the places where his Horcruxes had been hidden.

In the Shrieking Shack, when we see Voldemort, Nagini is by his side, twining restlessly within an apparent protective spell. Severus Snape is summoned to Voldemort's presence, and Voldemort says that the Elder Wand, which he has taken from Dumbledore's tomb, is not working as well as he had expected. Voldemort has come to the conclusion that, because Snape had killed Dumbledore, the wand owed its allegiance to Snape, and would do so until someone killed Snape. Whereupon, he throws Nagini, protective spell and all, at Snape. Snape is bitten viciously, and Voldemort and Nagini leave, allowing Harry time to receive memories from the fallen Snape. In Snape's memories, we see Dumbledore telling Snape that at some point, Voldemort will suddenly start being very protective of Nagini, keeping her always by his side. Then, and only then, will it be time to tell Harry all that Dumbledore has told Snape.

As Harry heads out of the school for his meeting with Voldemort, he runs into Neville Longbottom. Thinking of Dumbledore and his backup plans, Harry tells Neville that it is vital that, should anything happen to Harry, Nagini must be killed. This is necessary before Voldemort could be defeated forever.

When Harry confronts Voldemort in the Forbidden Forest, he sees Nagini, still twining restlessly within the protective spells Voldemort has cast about her. He thinks about the possibility of killing her, but determines that it is too risky; with the protective spells, and the large number of Death Eaters present, he is unlikely to get an effective spell out in time.

As Voldemort is crowing before the school about his final victory over Harry, Harry notices that Nagini is no longer encased within the protective spell. Neville produces the Sword of Gryffindor out of the Sorting Hat and with it, decapitates Nagini, killing her.

Strengths
Being a snake, Nagini has all the strengths of snakes: venom, physical strength, ability to travel through small apertures, maneuverability. Additionally, sharing some of Voldemort's soul, she also retains some of his intelligence, and due to her large size and possibly magically-enhanced venom, her bite is powerful enough to kill a full-grown man in seconds, or cause one to bleed to death in minutes.

Weaknesses
Being a snake, her intelligence and ability to plan are limited, despite her sharing of Voldemort's soul and part of his intellect.

Relationships with Other Characters
Nagini is Voldemort's pet, and contains one of his soul fragments. As such, she is extremely close to him. Towards most others, she is very much aloof, though she is likely to attack those who are in her, or Voldemort's, way.


text:
Programmable Logic/Integrated Logic Analyzers

An integrated logic analyzer is a useful tool for debugging FPGA designs. Integrated logic analyzers allow the capture and examination of signals in a design while using the actual hardware device. It is very useful for finding and solving unforeseen issues with large and complex designs.

Both Xilinx and Altera have designed ILAs for their respective chips. Xilinx's ILA is called Chipscope. In addition to an ILA it also has a VIO (virtual IO core) for changing signals in real time, embedded processor bus analyzers, and high speed serial bit rate tests.

Altera's ILA is called Signal Tap.

Integrated logic analyzers use FPGA resources when instantiated. The logic analyzer is created using FPGA fabric and the samples are often stored using the hard core RAM blocks in the FPGA. Using an ILA can prevent these resources from being used by the actual design and inclusion of a ILA can make the design harder to meet timing during a place and route.


text: Programmable Logic/Simulators

title: Programmable Logic/Simulators


text:
Manx

Ayndagh

 * Toshiaght (Introduction)
 * Abbyrlhit as Fockley-magh (Alphabet and Pronunciation)
 * Lessoon 1: Bannaghtyn! (Lesson 1: Greetings!)
 * Lessoon 2: C'raad t'ou cummal? (Lesson 2: Where do you live?)
 * Lessoon 3: Nane, Jees, Tree (Lesson 3: One, Two, Three)
 * Online resources

Authors: Girdi —— Recording: Girdi

title: Manx


text:
Talk:The Seven Wonders of the World

I saw a powerpoint that had the seven wonders of the world - more abstract concepts of hearing, seeing, tasting, smell, touch, laugh, and love It might make a nice compare / contrast in the book - Just an idea.

I'd recommend some sort of "looking forward" section, that goes through some of the more prominent things put forward as "modern wonders of the world", such as the Taj Mahal (not all that recent, but certainly more recent that greek times), the Grand Canyon, and others. Riffraffselbow (talk) 03:08, 3 October 2009 (UTC)

title: Talk:The Seven Wonders of the World


text:
General Anatomy/Skeletal System

=Introduction= There are 206 bones in the human body. A bone is made up of several tissues which work together such as bone, osseous tissue, cartilage, dense connective tissues, epithelium, adipose tissue and nervous tissue. For this reason each individual bone is classified as an organ.

Bone tissue is complex and has dynamic living qualities. The entire framework of bones, joints, cartilages and ligaments constitute the skeletal system. The skeletal system provides an internal framework for the body whilst protecting the delicate internal organs, and provides anchorage for skeletal muscles so that muscle contraction is possible, which in turn creates movement.

Bone Function
The functions of the skeletal system entail support, protection, movement, mineral storage and blood cell formation. The bones provide an internal framework which allow support and anchorage for soft organs. The leg bones support the upper body when standing and the ribs extend from the spinal cord to support thoracic contents. The brain and all internal components of the spinal cord are encased in bone and vital organs are given essential protection against accidental damage by external forces. The body has a wide and flexible range of movement because the skeletal muscles attach to bones via tendons. Bones store fat and essential minerals like calcium and phosphorus and are also the site of red blood cell formation. The bone marrow inside the hip bones produces most of the white blood cells.

Bone Types
The bones in the human body can be classified into four main shapes with their names providing an indication of their shape. Long bones - longer than wide with a shaft and 2 ends. They are mostly made of compact bone but a significant amount is spongy. Nearly all the limb bones are long bones. Short bones such as the wrist and ankle are more cube shaped and are mostly spongy bone matter. Flat bones like the sternum, skull and ribs are flatter and thinner with a slight curve. Irregular bones do not fall into any of the above caterogries and include bones such as the vertebrae and hip.

Divisions of the skeleton
The skeleton is divided into two (2) main sections, the 'Axial' and the 'Appendicular'.

Axial Skeleton The axial part of the skeleton is made up of 80 bones, though the main bones are the cranial (skull) and facial bones, the vertebral column (spine) and the bony thorax (ribs and sternum), although one bone that is often forgotten is the Hyoid bone, which is situated just above the larynx. The Axial Skeleton picked up its name as it forms the 'longitudinal axis' of the body. The cranial and facial bones work together but are considered to be separate parts. The cranial bones include the frontal bone, parietal, temporal and occipital. Whereas the facial bones are made up of many smaller bones, the main ones include the mandible, maxilla, zygomatic, lacrimal, nasal, vomer, inferior nasal conchae, and the ethmoid bones. The vertebral column is made up of thirty-three (33) vertebrae, which are categorized in five (5) sections. These are the Cervical (7 vertebrae), Thoracic (12 vertebrae), Lumbar (5 vertebrae), Sacrum (5 fused vertebrae) and Coccyx (4 fused vertebrae). Lastly is the bony thorax, this is made up of the ribs and sternum. The bony thorax has twelve (12) ribs (7 true and 5 false, 2 of which are called 'floating ribs'), the ribs are fixed to the spinal column and are there to protect the body's vital organs such as the heart, lungs and kidneys. The sternum is a fusion of three (3) bones, the jugular notch, sternal angle and xiphisternal joint.

Appendicular Skeleton The Appendicular skeleton is made up of all 126 other bones in the body. Primarily it includes the shoulder girdle (including clavicle and scapula), arms (humerus, radius, ulna, carpals, metacarpals, and phalanges), the pelvic bones (pelvic girdle, including the ilium), and the legs (femur, patella, fibula, tibia, tarsals, metatarsals and phalanges). Each shoulder girdle (pectoral girdle) consists of a scapula and a clavicle (collarbone). If the clavicle is broken, the whole shoulder region will collapse, as the girdle acts as a supporting structure. The pelvic Girdle mainly consists of two 'coxal bones' (hips), which are formed by the ilium, pubic bone, ischium, iliac crest, sacroiliac joint, pelvic brim, ischial spine, acetabulum and pubic symphysis, the bones are all fused together making up a single hip.

Microscopic Structure
The structure unit within the compact bone is the Haversian system. The Lamella column like matrix tube made mostly of collagen which gives bone their strength and allow weight bearing. There is central canal which provides blood and nerve supply to the cell. A channel within each cell provides blood supply and nerve fibres that support the cell. Volkmann's canals are channels that assist with blood and nerve supply from the periosteum to the Haversian canal. Osteocytes are mature bone cells and are found within Lacunae. The Canaliculi are hair-like canals and allow all the bone cells to receive their nutrient supply.

Bone Membranes
Periosteum is a double-layered protective member covering the shaft or diaphysis. The outer fibrous layer is dense, irregular connective tissue. Its inner osteogenic layer composed of Osteoblasts (bone forming cells, responsible for new bone growth and repair) and Osteoclasts(bone-destroying cells, important for bone restoration). The delicate membrane covering the internal surface of the bone is called Endosteum.

Articulation
Articulations, also known as joints, have two major functions in the body. They hold bones together whilst allowing the bones to move. A joint can be classified in two ways, by its function and its structure. Structurally, there are the fibrous, cartilaginous and synovial joints, being classified based on whether fibrous, cartilage, or a joint cavity separated the bony regions of the joint.

Fibrous joints
These are the bones which are connected by fibrous tissues. In sutures the bones have irregular edges and they are bound tightly together by connective fibrous tissue.

Cartilaginous joints
These are bones that are connected by cartilage.

Synovial joints

Are the joints where the articulating bone ends are separated by a joint cavity which contains synovial fluid. Synovial joints account for all joints of limbs. All synovial joints have formed distinguishing features, articular cartilage which cover the ends of the bones forming the joint, fibrous articular which are joints surface which are enclosed by a sleeve or capsule of fibrous connective tissue, joint cavity the articular capsule encloses a cavity, reinforcing ligaments which is that the fibrous capsule is usually reinforced with ligaments. Types of the synovial joints are based on the shapes and can be classified as plane, hinge, pivot, condyloid,saddle and ball and socket.
 * Plane: articulating surfaces are usually flat to allow slipping and gliding properties.
 * Hinge: the cylindrical end of a bone fits into a trough shaped surface of another bone, like that of an elbow joint.
 * Pivot: the rounded end of the bone fits into a sleeve or ring of bone.
 * Condyloid: is an egg shaped surface of a bone which fits in to a concavity in another.
 * Saddle: surface has both convex and concave areas.
 * Ball and socket: at the end of a bone there is a spherical head and at the other there is a round socket and this creates the ball and socket movement found in such places as the hip or shoulder.

Common Problems
The skeleton can have many problems, such as fractures, abnormalities and diseases. Below are some common problems associated with the skeketal system, that are still around today.

Abnormal Spinal Curvatures
There are three main types of abnormal curvatures in the spine. They are 'Scoliosis', 'Kyphosis' and 'Lordosis'. In scoliosis, the spine is curved too far to the lateral side, having an unbalanced appearance,also making everyday movement harder. Kyphosis is the abnormal curvature of the spine in the 'cervical region', appearing as an arched back. Lordosis, is the inward curvature of the spine, causing the back to look 'caved in'. Back and chest pain can be present in these conditions, but only show in severe cases.

Fractures
The skeletal system is made of hard bone, yet when enough pressure is exerted, they can break.When a break occurs, it is called a fracture. There are many types of fractures, most are due to extreme twisting of pressure, yet old age can play a large factor, as the bones are weakened and deteriorating, making breakages easier.

Fracture Types

 * Comminuted - Where the bone has fractures has resulted into many pieces
 * Compressed - Where the bone has been crushed
 * Depressed - The fracture leaves an indentation in the remaining bone
 * Impacted - Both ends of the fracture are protruding into each other
 * Spiral - The bone has a 'ragged' appearance and has been twisted
 * Greenstick - The bone only fracture part way through, occurs in children
 * Compound - The bone is protruding outside of the body
 * Simple - The bone remains inside the body and is cracked straight through

Rickets
Rickets is a disease mainly found in children who do not have a great enough calcium or vitamin D intake. This causes the bones to fail in calcification, making the bones weak and 'bendable'. It can also occur in infants, who are being 'nursed' (breast fed) by their mothers, who do not have a enough vitamin intake themselves.

Slipped Disk
Many people these days suffer from 'slipped disks', this is due to incorrect lifting techniques or sudden movement. The disks related to this are called spinal (or vertebral) disks. Spinal herniation is where the disc protrudes outward from its normal position in the vertebral column. This can cause a great amount of pain as the disk can press on the adjacent nerves.

Authors
Nursing Class of Geraldton, Western Australia
 * Jess Herriot
 * Mercie Ortiz
 * Michelle Stewart
 * Jill Saunders
 * Hamish Darby

title: General Anatomy/Skeletal System


text:
General Anatomy/Muscular System

 * Provides movement for the body
 * Helps create heat

Vertebral Column

The inferior and superior vertebral notches of two disks form the intervertebral foramen through which spinal nerves pass.

C1 Atlas: Has transverse processes on each side with an anterior tubercle process at the back. On the Articular facet, the occipital condyles move. Lateral are the transverse foramina which houses the vertebral artery

C2 Axis: Has another pair of articular facets lateral to the Dens-an odontoid process which projects upwards into the atlas. The transverse ligament run across this to keep it in place.

Spinal Vertebrae: Costal facet is posterior to the transverse costal facet (costal=rib).

Lumbar vertebrae: No costal facets, doesn't carry ribs.

Upper extremities: 60 bones: humerus, radius, ulna, carpals, metaparpals, phalanges.

Pelvic Girdle 2 ossa coxa each os coxa = three fused bones

Lower extremities: 60 bones: femur, tibia, fibula, patella, tarsals, metatarsals, phalanges (sing. phalanx)

Iliopsoas (2 parts) Iliacus Origin: Iliac Fossa, Insertion: Lesser trocanter femur, Function: Hip, medial rotation of femur. Psoas major Origin: Vertebra, Insertion: " ", Function: " "

Tensor Fasciae Latae Insertion: Origin: Iliac Crest, Insertion: Tibia, lat. condyle, Hip flexor muscle.

Gluteus maximus Origin: Ilium and sacrum, Insertion: Femur, Function: Abduction and lateral rotation.

Gluteus minimus, medius Origin: Ilium, Insertion: Greater Trochanter femur, Function: Abduction, medial rotation.

Adductor longus Pubis, Femur, adduct Femur

Gracilus Pubis, Tibia, adduct Femur

Quadriceps Rectus femoris: Ilium, Tibia, knee extension Vastus lateralis: Femur, Tibia, knee extension V. medialis: Femur, Tibia, knee extension V. Intermedius: Femur, Tibia, knee extension

Sartorius: Ilium, Tibia medial, Flexes knee.

Foot Gastrocnemius Femur, Calcaneous, Plantar Flexion

Soleus Tibia and fibula, calcaneous, plantar flexion

Tibialis anterior Tibia, Metatarsal 1, med. cuneiform, Dorsal flexion

Skeletal muscles: striated, multinucleated Epi, peri, endo mysium

Muscle fiber Saredemma: transverse Tubules Sarcoplasm: myofibrils, glycogen myoglobin (binds O2)

Myofibrils are organelles composed of chains of proteins called filaments. Myofilaments: filaments in the myofibrils

A triad of transverse structures around the bands of muscle. Transverse cisternae on the sides and tubule going down the middle

Actin: Rounded spiral protein Tropomyosin: wraps around the actin Troponin complex ball sitting on top of tropomyosin Myosin: protein bands that attract actin

title: General Anatomy/Muscular System


text: Programmable Logic/Terminology

title: Programmable Logic/Terminology


text:
Philately

 * /Preface/
 * /Introduction/

Philately as a Passion

 * From Stamp Collecting to Philately
 * Tools of the Trade

Technical Aspect of Philately

 * Introduction
 * Printing
 * Philatelic Terms

Specialization

 * Introduction
 * Pioneers
 * Areas of Specialization

Related Wiki Articles and Resources

 * Philately
 * w:Portal:Philately
 * w:Wikipedia:WikiProject Philately
 * commons:Category:Philately
 * Philately in Wikisource
 * Philately in Wikiquote

Authors

 * 1) Rey Adel

title: Philately


text: Programmable Logic/Synthesis

title: Programmable Logic/Synthesis


text: Programmable Logic/HDL Comparison

title: Programmable Logic/HDL Comparison


text:
Programmable Logic/Tools

Design

 * XILINX Vivado
 * XILINX ISE WebPACK (Discontinued - Legacy software)

Simulation

 * Icarus Verilog (Wikipedia article)
 * ModelSim
 * XILINX ISE WebPACK

Synthesis

 * XILINX ISE WebPACK

Implementation

 * XILINX ISE WebPACK

title: Programmable Logic/Tools


text:
Programmable Logic/Further Reading

Verilog Resources

 * Verilog on Wikipedia

VHDL Resources

 * VHDL
 * The Hamburg VHDL archive
 * VHDL Cookbook (PDF)
 * Ashenden, Peter J., "The Designer's Guide to VHDL", 2nd edition.
 * Designers Guide to VHDL - ISBN 9780120887859
 * www.opencores.org - A home of many open source VHDL and Verilog projects

SystemC Resources

 * SystemC on Wikipedia
 * SystemC.org

Wikibooks Resources

 * Embedded Systems
 * Digital Circuits
 * VHDL for FPGA Design - Principles and Practices
 * Semiconductors
 * Logic for Computer Science

title: Programmable Logic/Further Reading


text:
Programmable Logic/HDL Basics

 * Hardware Design Languages
 * HDL Comparison

title: Programmable Logic/HDL Basics


text:
Programmable Logic/VHDL

 * General Syntax
 * Data Types
 * Operators
 * Module Structure
 * Processes
 * Sequential Statements
 * Procedures
 * Coding and Project Style

VHDL-Tutorium Conception_et_VHDL

title: Programmable Logic/VHDL


text:
Programmable Logic/Verilog

 * Verilog Data Types
 * Verilog Operators
 * Verilog Always and Initial
 * Verilog Control Structures
 * Verilog Tasks
 * Verilog Module Structure

 * Verilog for Software Programmers
 * Verilog RTL Coding Guidelines

title: Programmable Logic/Verilog


text:
Programmable Logic/SystemC

SystemC

 * System C Library
 * System C Data Types
 * System C Library
 * System C Operators
 * System C Functions
 * Object Oriented Design
 * Dynamic Memory Allocation

title: Programmable Logic/SystemC


text:
Programmable Logic/Mixed-Language Programming

 * How to Program Mixed-Language
 * Problems with Mixed-Language


text:
Programmable Logic/Devices

Devices

 * PALs
 * GALs
 * Complex Programmable Logic Devices (CPLDs)
 * Field Programmable Gate Arrays (FPGAs)
 * Field Programmable Object Arrays (FPOAs)

title: Programmable Logic/Devices


text:
Programmable Logic/Device Programming

Device Programming

 * JTAG
 * EEPROMS
 * Reconfiguration

title: Programmable Logic/Device Programming


text:
More C++ Idioms/nullptr

= nullptr =

Intent
To distinguish between an integer 0 and a null pointer.

Motivation
For many years C++ had an embarrassment of not having a keyword to designate a null pointer. C++11 has eliminated that embarrassment. C++'s strong type checking makes C's NULL macro almost useless in expressions, e.g.:

Instead,

or

are valid definitions for NULL in C++. See below.

The crux of the matter, in fact, is that C++ disallows conversions from void *, even when the value is a constant zero, but, for constant zero, introduces a special case anyway: int to pointer (actually several of them: short to pointer, long to pointer, etc.). This is, in fact, even worse than allowing (for the constant case) the former exception, the more so given the support of function overloading in the language.

The use of the macro NULL has its own set of problems as well. C++ requires that macro NULL be defined as an integral constant expression having the value of 0. So unlike in C, NULL cannot be defined as (void *)0 in the C++ standard library. Furthermore, the exact form of definition is left to the particular implementation, which means that e.g. both 0 and 0L are viable options, among some others. This is a trouble as it can cause confusion in overload resolution. Worse, the way confusing overload resolution manifests itself will vary depending on the compiler and its settings used. An illustrative case is shown in this slight modification of the example above:

Solution and Sample Code
The nullptr idiom solves some of the above problems and can be put in reusable form, as a library solution. It is a very close approximation of a "null keyword", by using only pre-C++11 standard features.

The following is such a library solution as mostly found in Effective C++ by Scott Meyers, Second Edition, Item 25 (it is not present in the third edition of the book).

The following code illustrates some usage cases (and assumes the class template above has already been #included). Unfortunately, there seems to be a bug in gcc 4.1.1 compiler that does not recognize the comparison of nullptr with point to member function (pmf). The above code compiles on VC++ 8.0 and Comeau 4.3.10.1 beta.

Note that nullptr idioms makes use of the ../Return Type Resolver/ idiom to automatically deduce a null pointer of the correct type depending upon the type of the instance it is assigning to. For example, if nullptr is being assigned to a character pointer, a char type instantiation of the templatized conversion function is created.

Consequences
There are some disadvantages of this technique and are discussed in the N2431 proposal draft. In summary, the disadvantages are
 * A header must be included to use nullptr. In C++11, nullptr itself is a keyword and requires no headers (although std::nullptr_t does).
 * Compilers have historically produced (arguably) unsatisfactory diagnostics when using the code proposed.

Related Idioms

 * ../Return Type Resolver/

title: More C++ Idioms/nullptr


text:
Programmable Logic/Design Basics

Design Basics

 * Design Process
 * Parallel Execution
 * /Timing and Synchronization/

title: Programmable Logic/Design Basics


text:
Programmable Logic/Program Descriptions

Program Descriptions

 * Data-Flow Descriptions
 * Behavioral Descriptions
 * Structural Descriptions
 * RTL Descriptions
 * Switch-Level Descriptions

title: Programmable Logic/Program Descriptions


text:
Programmable Logic/Implementation Flow

Implementation Flow

 * Synthesis
 * Mapping
 * Placing
 * Routing

title: Programmable Logic/Implementation Flow


text:
Programmable Logic/Cores and IP

Programmable logic cores or IP are pre-designed logic blocks that implement a certain functionality. The can be blocks that are embedded in the FPGA fabric (Hard Cores) or predesigned and debugged blocks that are implemented using the FPGA fabric (Soft Cores).

Cores and IP

 * Hard Cores
 * Soft Cores

title: Programmable Logic/Cores and IP


text:
Programmable Logic/Debugging Designs

Debugging programmable logic designs is often a long and difficult task. HDLs give allow us to program PLDs with a the power of a higher level language. Unfortunately, the debugging of these designs is not as straight forward as debugging a C or Python program. There are some tools that help us in these departments, however. They are testbences, simulators, and integrated logic analyzers.
 * Testbenches
 * Simulators
 * Integrated Logic Analyzers (ILAs)

title: Programmable Logic/Debugging Designs


text: Category:Book:Galician

title: Category:Book:Galician


text:
User talk:MaxSem

Come introduce yourself at the new users page. If you have any questions, you can ask there or contact me personally.– Mike.lifeguard  | talk 22:10, 3 November 2007 (UTC)

title: User talk:MaxSem


text:
User talk:Ldvbin

Come introduce yourself at the new users page. If you have any questions, you can ask there or contact me personally.– Mike.lifeguard  | talk 22:11, 3 November 2007 (UTC)

title: User talk:Ldvbin


text: User talk:74.225.160.240

title: User talk:74.225.160.240


text:
Galician

Table of Contents

Introduction

Lesson 1

 * 1) Alphabet
 * 2) Numbers and Dates
 * 3) Articles
 * 4) Ser
 * 5) Estar
 * 6) Colours
 * 7) Family
 * 8) Exercises
 * 9) Reintegrationist Lesson

Lesson 2

 * 1) Introducing yourself
 * 2) Asking questions
 * 3) Plural
 * 4) Ter
 * 5) Haber
 * 6) School
 * 7) Jobs
 * 8) Exercises
 * 9) Reintegrationist Lesson

Appendices

 * Appendix A: Common Phrases

Gallego

title: Galician


text:
Galician/Introduction

Welcome to Wikibooks' Galician language textbook. This book should help you to learn the basics of Galician, even if you start out with no knowledge of the language.

What is the Galician language?

Galician, or Galego, is a romance language spoken in Galicia, an autonomous community in the Northwest of Spain recognised as historical nationality in 1978 Spanish Constitution. With a common base with Portuguese, as both languages have developed from the Galician-Portuguese branche of Western Ibero-Romances, is one of the four official languages of the Kingdom of Spain since 1981, when the Statute of Autonomy was passed in referendum.

Galician is spoken by more than 2 million people, mainly in Galicia, but also in another autonomous communities of Spain, Europe and Latin America because of diaspora, with many having left their homeland in the 1950s and 1960s.

Political and social situation
The situation between Portuguese and Galician is surprisingly similar to that of Bulgarian and Macedonian. Portuguese speakers (whether be in Portugal, Brazil or in southern Africa) will insist that Galician is a dialect of their own language, while most of the rest of the Iberian peninsula will tell you otherwise. The arguments include: written Galician resembles Spanish in many ways, but the differences between spoken Portuguese and spoken Galician are very blurry. They can speak and understand one another without the need of a translator.

Aims of this book
The goal of this book is to teach the reader about the Galician language.

title: Galician/Introduction


text:
User talk:Darrelljon

CC-BY compatibility
I know I just got done accepting that maybe CC-BY might be compatible with GFDL after all. Today someone else wondering about CC-BY compatible pointed out w:Wikipedia talk:FAQ/Copyright which suggests that even the Wikimedia Foundation's own legal counsel doesn't believe CC-BY and GFDL are compatible. http://www.fsf.org/licensing/licenses/index_html#OtherLicenses says the same thing. Perhaps as was said on the FAQ talk page, it is unwise after all to jump to conclusions either way if even the experts can't agree. --dark lama  20:17, 26 May 2009 (UTC)

Out of scope
Wikibooks does not host books written elsewhere - e.g., out of copyright books. These go on Wikisource. Wikibooks is for newly written textbooks, not stories or old texts. I have deleted your page accordingly. QuiteUnusual (discuss • contribs) 13:38, 28 May 2021 (UTC)

Query notice for Wikijunior:Play
I placed a query template on the page Wikijunior:Play, which you created. It looks like you may have abandoned the page before you added enough content for the book's scope to be determinable. If you don't add meaningful content to the page or explain its scope on its talk page within 7 days, it will become a candidate for speedy deletion. Evil Sith Lord (discuss • contribs) 08:46, 14 November 2021 (UTC)

title: User talk:Darrelljon


text:
More C++ Idioms/Include Guard Macro

= Include Guard Macro =

Intent
To allow inclusion of a header file multiple times.

Motivation
Including the same header file more than once in the same compilation unit can lead to the violation of a basic rule of C++: One Definition Rule (ODR). A header may get included multiple times because of direct and indirect inclusion.

Solution and Sample Code
Include Guard macro idiom is an old idiom, which is also applicable in a C program. It uses simple #define to allow the inclusion of a header file multiple times in a compilation unit. The idiom ensures that after preprocessing the guarded content of the header file is only seen once by the compiler. More precisely, the compiler gets to see the guarded content where the header file gets included for the very first time. The following macros are put at the very beginning and at very end of a header file:

Some compilers support as an efficient alternative to include guards. It does not require to open the header file more than once, unlike traditional include guard macro in some compilers. On many modern compilers like GCC4 or MSC++2008 #pragma once will not give better compile time performance as they recognize header guards.

Known Uses
Virtually all header files in the world!

Related Idioms

 * Inline Guard Macro
 * Export Guard Macro

title: More C++ Idioms/Include Guard Macro


text:
More C++ Idioms/Inline Guard Macro

= Inline Guard Macro =

Intent
To conveniently control inline-ness of functions using a compiler command line macro definition switch.

Motivation
For debugging purpose, it is often necessary to turn off inlining of functions throughout the program. But for release version, inline functions are desirable. This indicates a need of a quick way of turning inline-ness on/off as and when desired. Moreover, such functions should be defined in header files when they are inlined and otherwise should be in the source (.cpp) file. If non-inline functions are in header files, almost always it ends up creating multiple definitions of the function. On the other hand, if inline functions are not in header files then compilation units can't find them. In both the cases linker throws errors.

Therefore, a flexible way of inlining is often desirable but C++ language does not support it without some macro magic. The Inline Guard Macro idiom achieves this.

Solution and Sample Code
The solution is to put all the inline functions in a separate file called .ipp file and decorate each function with a macro INLINE. Header file and the implementation file is create as usual and the .ipp file in selectively included in one of the two files (header or implementation) depending upon whether inlining is desired. An example of a class Test is given below.

The effect of using Include Guard Macro is that depending upon whether MYPROJECT_INLINE_ENABLED is defined or not, test.ipp gets #included in either test.cpp or test.hpp. When it gets merged with test.cpp, functions are not inlined because INLINE is defined as an empty string. On the other hand when test.ipp is merged with test.hpp, INLINE is defined as inline (the keyword).

Now, what remains is to define the MYPROJECT_INLINE_ENABLED macro when desired. Generally, all modern C/C++ compilers allow defining macros at command line. For example to compile the above program on gcc using inlining, the argument -DMYPROJECT_INLINE_ENABLED option is added to the compiling command line. If no such macro is defined, the functions are automatically treated as non-inline and the program compiles OK.

Known Uses

 * ACE (Adaptive Communication Environment)
 * TAO (The ACE ORB)

Related Idioms

 * Include Guard Macro
 * Export Guard Macro

More C++ Idioms/inline ガードマクロ(Inline Guard Macro)

title: More C++ Idioms/Inline Guard Macro


text: Wikibooks:Requests for deletion/Chemical synthesis


text:
User talk:83.228.51.82

– Mike.lifeguard  | talk 02:42, 4 November 2007 (UTC)

title: User talk:83.228.51.82


text:
User talk:71.126.29.207

– Mike.lifeguard  | talk 02:43, 4 November 2007 (UTC)

title: User talk:71.126.29.207


text:
User talk:Fryant

Come introduce yourself at the new users page. If you have any questions, you can ask there or contact me personally.– Mike.lifeguard  | talk 02:43, 4 November 2007 (UTC)

title: User talk:Fryant


text:
Blender 3D Reference Guide/Windows Reference/File Browser

The Blender File Browser is, of course, used to open Blender-native (".blend") files. It provides simple GUI widgets to navigate your computer's file system, and easy selection of files. The same basic UI element is used for the File menu "Append or Link" item, as well as, "Save As...", "Save Image...", and "Save Runtime..." menu items.

When "Open..." is selected in the "File" menu, the window that the cursor is over becomes a File Browser window. There are two text fields at the top for the currently selected directory, and the currently selected file. To the left, a button, labeled "P" will navigate to the parent of the currently selected directory. Also, there is a menu pop-up button which will offer directories from which files have recently been opened, allowing quick return to directories being used in the current project. To the right, there are buttons to open the selected file, and a "Cancel" button which aborts the File Browser completely, returning the window to its previous state. (Note that the "ESC" key can be used to abort as well.)

In the file list, which appears below these widgets, files that Blender recognizes are tagged with a small colored square icon to indicate that they may be opened. Depending on how many files are listed, there may be scroll bars for vertical and/or horizontal scrolling of the file list. The File Browser recognizes files with the ".blend" extension as compatible Blender files. It also recognizes ".blend.gz" as compressed Blender files (at least OSX version), and will open them, performing the decompression on-the-fly.

Like every Blender "window", there is a window "header", in this case, across the bottom of the window. The widget/icons here provide, in left-to-right order, the following additional function to the File Browser window:

 The normal Blender window type selector button Toggle full screen mode for the File Browser window Four buttons for the sort-order of the files: Sort by name Sort by extension Sort by date Sort by size Two buttons to select info and hidden files: Toggle brief/extended information Toggle appearance of hidden "dot" files
 Two buttons to select paths and UI inclusion:
Toggle relative path use. Files saved with relative paths to their constituent parts, and can later be opened on a different system, with relative paths enabled, and the constituent parts will be found on the local drive

Toggle loading the user interface (UI) from the blend file. If not selected, the scene is read into the current UI configuration.