text:
User talk:Ebbixx

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Good luck! -- Herby talk thyme 20:01, 23 January 2007 (UTC)

title: User talk:Ebbixx


text:
Chess Opening Theory/1. d4/1...Nf6/2. c4/2...e6/3. Nc3/3...Bb4/4. Qc2

= Nimzo-Indian Defence:Classical Variation = The Classical Variation, 4.Qc2, aims to address two main problems posed by the Nimzo-Indian defence. On c2 the white queen protects the knight on c3, meaning that Black will no longer be able to double White's pawns by exchanging bishop for knight. At the same time, the queen hits the important e4 square.

A note on strategy and rules of thumb: Beginning chess players are often told not to move the queen too early in the opening. While as a general rule this advice is valuable, it is not sacrosanct. The Classical Nimzo provides an excellent opportunity to examine this rule, and its limitations, more closely. The admonition against early queen moves stems partly from the fact that the opposing player may be able to harass the queen simply by making useful developing moves. While one player is struggling to return his queen to safety, the second is gaining a decisive lead in development. In the Classical Variation, however, the queen's deployment to c2 is hardly a brazen sortie into enemy territory. It is unlikely that Black will be able to easily attack the queen anytime soon, so White's move is not considered risky.

A second reason to delay the queen's development is that the queen does not work well without the assistance of the minor pieces, and it is not clear until the knights and bishops are deployed where the queen will be most useful. With 4.Qc2, it is true that White neglects to develop a kingside piece or even to open lines for development, but it is clear that the queen will perform a useful function on c2. The fight for the e4 square is always a significant theme in Nimzo-Indian games, and the queen contributes to this fight. She also bolsters White's position on the queenside by protecting the pawn structure, and at the same time she takes aim at Black's kingside. White should not have a problem deploying the queen from c2 to whatever theater of battle requires her services.

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/


text:
ERP Internals/Glossary/Enterprise

An enterprise is a group of people organized for some long-term (i.e. multi-year) purpose. Most, but not all, enterprises are for-profit businesses.

title: ERP Internals/Glossary/Enterprise


text:
ERP Internals/Data Tables/Supplier

This includes a group of tables. They are listed below:

 * Supplier
 * Supplier Interaction
 * Supplier Person

title: ERP Internals/Data Tables/Supplier


text:
ERP Internals/Data Tables/Supplier/Supplier

This table contains one record for every supplier.

Used by: Accounts Payable, Purchasing

Key: Supplier Number

Fields:
 * Supplier Number (a unique identifier assigned by the user)
 * Type
 * Organization/Individual (individual must have exactly one person record)
 * Active (Yes/No)
 * Group (used to group national accounts together)
 * Name
 * Address 1
 * Address 2
 * City
 * State/Province
 * Country
 * Zip/Postal Code
 * Telephone
 * FAX
 * E-mail
 * Website
 * Alternative Supplier Number
 * Tax ID
 * NAICS
 * 1099 Exempt (Y/N)
 * 1099 Number
 * Language
 * Usual Currency
 * Usual Terms
 * Usual FOB
 * Usual Ship Via
 * Bank Code
 * Duplicate Invoice Checking (Yes/No)
 * Credit Limit (this is the limit the supplier is imposing on the enterprise, used by Purchasing)
 * Hold (Yes/No) (If "yes", no transactions can be entered)
 * Holdback Percentage
 * Holdback Days
 * Current Accounts Payable Balance (a calculated field that the user cannot change)
 * YTD Volume (a calculated field that the user cannot change)
 * Supplier's Number for Us (this is the customer number that the supplier has assigned to us)
 * GL Distribution Group (contains all the postable account numbers)
 * Notes


text:
ERP Internals/Data Tables/Supplier/Supplier Interaction

This table contains one record for every interaction between the enterprise and the supplier. This table is key to Supplier Relationship Marketing.

Used by: Accounts Payable, Purchasing

Key: Supplier Number, Date/Time

Fields:
 * Supplier Number
 * Date/Time
 * Type (Telephone,Face-to-face,etc.)
 * Employee Number(s)
 * Location
 * Supplier Attendees
 * Notes


text:
ERP Internals/Data Tables/Supplier/Supplier Person

This table contains one record for every person at every supplier.

Used by: Accounts Payable, Purchasing

Key: Supplier Number, Person Number

Fields:
 * Supplier Number
 * Person Number (a unique identifier assigned by the user)
 * Last Name
 * First Name
 * Informal Name
 * Job Title
 * Department
 * Title (Mr/Ms/Mrs/etc.)
 * Address 1
 * Address 2
 * City
 * State/Province
 * Country
 * Zip/Postal Code
 * Business Telephone
 * Telephone Extension
 * 1-800 Number
 * Home Telephone
 * FAX
 * Mobile
 * Pager
 * E-mail
 * Language
 * Notes


text:
Talk:Taxation in the United Kingdom/Legislation/Section 38 of the Income and Corporation Taxes Act 1988

I think you're missing a word in the sentence about subsection 5. It reads as a sentence fragment right now. Kellen T 20:54, 23 January 2007 (UTC)


text:
ERP Internals/Data Tables/Item

This includes a group of tables. They are listed below:

 * Item
 * Item MPN
 * Item Location
 * Item Price

title: ERP Internals/Data Tables/Item


text:
ERP Internals/Data Tables/Item/Item

This table contains one record for every Inventory item.

Used by: Inventory, Order Entry/Invoicing, Purchasing, Quotation/Estimation

Key: Item Number

Fields:
 * Item Number (a unique Identifier assigned by the user)
 * Type (Item/Service/Time Billing)
 * Category (Hardware/Raw Material/Finished Goods)
 * Class (user-defined)
 * Active (Yes/No)
 * Description
 * Long Description
 * Picture
 * Thumbnail
 * BOM Number
 * Configurable (Yes/No)
 * Stocking UOM
 * Selling UOM
 * Buying UOM
 * Conversion Factors between UOMs
 * Weight
 * Dimensions (length,width,height, thickness)
 * Shape (rod, sheet, etc.)
 * Alloy (Aluminum, Stainless Steel, etc.)
 * On-Hand (sum of all locations)
 * On-Order
 * Allocated
 * Minimum
 * Re-order Quantity
 * EOQ
 * Lead Time (Days)
 * Lot Number
 * Serial Number
 * Cycle Count
 * Last Count Date
 * Duty Percentage (used to calculate anticipated duty on receipts)
 * Costing Type
 * Last Cost
 * Average Cost
 * Standard Cost
 * Selling Price
 * YTD Units
 * YTD Amount
 * GL Distribution Group (contains all the postable account numbers)
 * Notes

title: ERP Internals/Data Tables/Item/Item


text:
ERP Internals/Data Tables/Item/Item MPN

This table contains one record for every MPN for every item.

Used by: Inventory, Purchasing

Key: Item Number, Supplier Number, MPN

Fields:
 * Item Number
 * Supplier Number
 * MPN (Manufacturer's Part Number)
 * Lead Days
 * Unit Cost
 * Minimum Quantity
 * Notes

title: ERP Internals/Data Tables/Item/Item MPN


text:
User talk:205.211.96.100

Welcome to Wikibooks. We invite everyone to contribute constructively to our collection. Take a look at the welcome page if you would like to learn more about contributing. However, unconstructive edits are considered vandalism, and if you continue in this manner you may be blocked from editing without further warning. Please stop, and consider improving rather than damaging the hard work of others. Thanks. -- Herby talk thyme 21:02, 23 January 2007 (UTC)

Please stop adding nonsense to Wikibooks. It is considered vandalism. If you would like to experiment, use the sandbox. Thank you. Iamunknown 20:30, 9 February 2007 (UTC)

You have been blocked from editing Wikibooks  as a result of your .  Please note that page blanking, addition of random text or spam, deliberate misinformation, privacy violations, personal attacks; and repeated, blatant violations of our neutral point of view policy are considered vandalism. If you wish to make useful contributions, you are welcome to come back after the block expires. – Mike.lifeguard  | talk 16:23, 12 September 2007 (UTC)

Welcome to Wikibooks. We invite everyone to contribute constructively to our collection. Take a look at the welcome page if you would like to learn more about contributing. However, unconstructive edits are considered vandalism, and if you continue in this manner you may be blocked from editing without further warning. Please stop, and consider improving rather than damaging the hard work of others. Thanks. – Mike.lifeguard  | talk 14:29, 17 September 2007 (UTC)

Blocked
Νεοπτόλεμος ( talk | email | contribs ) 16:16, 11 April 2008 (UTC)

title: User talk:205.211.96.100


text:
ERP Internals/Data Tables/Item/Item Location

This table contains one record for each location of each item.

Used by: Inventory

Key: Item Number, Location

Fields:
 * Item Number
 * Location
 * Quantity
 * Lot


text:
User:ChardingLLNL

I'm not going to type in the same stuff over again, so if you are interested in knowing who I am, see my user page on WikiPedia.

title: User:ChardingLLNL


text:
User talk:ChardingLLNL

Talk to me already!!

title: User talk:ChardingLLNL


text:
Template:Miskito/Title

Title template for Miskito language course
 * parameter 1: lesson number
 * parameter 2: lesson title
 * parameter 3: translation of lesson title
 * parameter 4: previous page/lesson (format: "Lesson X", "Introduction"...)
 * parameter 5: next page/lesson (format: "Lesson X", "Introduction")

title: Template:Miskito/Title


text:
Haskell/The Curry–Howard isomorphism

The Curry–Howard isomorphism is a striking relationship connecting two seemingly unrelated areas of mathematics — type theory and structural logic.

Introduction
The Curry–Howard isomorphism, hereafter referred to as simply CH, tells us that in order to prove any mathematical theorem, all we have to do is construct a certain type which reflects the nature of that theorem, then find a value that has that type. This seems extremely weird at first: what do types have to do with theorems? However, as we shall see, the two are very closely related. A quick note before we begin: for these introductory paragraphs, we ignore the existence of expressions like  and   whose denotational semantics are ⊥. These have an extremely important role, but we will consider them separately in due time. We also ignore functions that bypass the type system like.

We can build incredibly complicated types using Haskell's higher-order functions feature. We might want to ask the question: given an arbitrary type, under what conditions does there exist a value with that type (we say the type is inhabited)? A first guess might be 'all the time', but this quickly breaks down under examples. For example, there is no function with type, because we have no way of turning something of type   into something of a completely different type   (unless we know in advance which types   and   are, in which case we're talking about a monomorphic function, such as  ).

Incredibly, it turns out that a type is only inhabited when it corresponds to a true theorem in mathematical logic. But what is the nature of this correspondence? What does a type like  mean in the context of logic?

A crash course in formal logic
We need some background on formal logic before we can begin to explore its relationship to type theory. This is a very brief introduction; for a wider grounding we recommend you consult an introductory textbook on the subject matter.

In everyday language we use a lot of 'If... then...' sentences. For example, 'If the weather is nice today, then we'll walk into town'. These kinds of statements also crop up in mathematics; we can say things like 'If x is positive, then it has a (real) square-root'. Formal logic is a way of representing statements which approximate English meanings with a Boolean logic on which we can do computations. We use the A→B sign (read as 'A implies B') to indicate that B is true whenever A is true. For example, our earlier statement could be recast as ' x is positive → x has a real square-root ', meaning the number's positivity implies the existence of the desired kind of root. We'll often use letters to stand for entire statements, so for example if W is the statement 'the weather is nice', and T is the statement 'we'll walk into town', then we could say W → T.

Our definition of P→Q has some flaws. If Q is some statement that is always true, no matter what the circumstances — like 'the sun is hot' — then it doesn't matter what P is. P could even be a false statement, Q would still be true if P were true, so the implication P → Q is not considered to be proved wrong. P → Q is defined to be true whenever P is false and whenever Q is true. So → doesn't really represent any kind of cause-effect relationship; things like 'the sky is pink → the sun is hot' are defined to be true. There are other logical algebras besides Boolean logic which try to fix these "problems" and we can also construct them in Haskell.

Other things that crop up lots in both everyday language and mathematics are things called conjunctions and disjunctions. The former represent statements involving an 'and', the latter statements involving an 'or'. We could represent the statement 'I will buy this magazine if it's in stock and I have enough money' by the symbolism $$(M \wedge S) \to B$$, where M = 'I have enough money', S = 'The magazine is in stock', B = 'I will buy the magazine'. Essentially, one can just read the symbol $$\wedge$$ as 'and'. Similarly, one can read the symbol $$\vee$$ as 'or', so that the statement 'I will either walk or get the train to work or both' could be represented as $$W \vee T$$, where W = 'I will walk to work', and T = 'I will get the train to work'.

Using these symbols, and a few more which will be introduced as we go, we can produce arbitrarily complicated symbol strings. There are two classes of these symbol strings: those that represent true statements, often called the theorems; and those which represent false statements, called the nontheorems. Note that whether a symbol string is a theorem or nontheorem depends on what the letters stand for, so $$P \vee Q$$ is a theorem if, for example, P represents the statement 'It is daytime' and Q represents the statement 'It is night time' (ignoring exceptions like twilight), but it would be a nontheorem if P were 'Trees are blue' and Q were 'All birds can fly'. We'll often call a symbol string a proposition if we don't know whether it's a theorem or not.

There are many more subtleties to the subject of logic (including the fact that when we say 'If you eat your dinner you'll get dessert' we actually mean 'Only if you eat your dinner will you get dessert'). If this is a subject that interests you, there are many textbooks around that comprehensively cover the subject.

Propositions are types
So, given a type, what does that mean in terms of symbolistic logic? Handily, it simply means that a → b. Of course, this only makes sense if  and   are types which can further be interpreted in our symbolistic logic. This is the essence of CH. Furthermore, as we mentioned before, a → b is a theorem if and only if  is an inhabited type.

Let's see this using one of the simplest of Haskell functions. has the type. Translated into logic, we have that a → b → a. This must be a theorem, as the type  is inhabited by the value. Now, another way of expressing a → b is that 'If we assume a is true, then b must be true.' So a → b → a means that if we assume a is true, then if we further assume that b is true, then we can conclude a. This is of course a theorem; we assumed a, so a is true under our assumptions.

The problem with ⊥
We've mentioned that a type corresponds to a theorem if that type is inhabited. However, in Haskell, every type is inhabited by the value. Indeed, more generally, anything with type, a value with denotational semantics of ⊥, is a problem. ⊥ in type theory corresponds to inconsistency in logic; we can prove any theorem using Haskell types because every type is inhabited. Therefore, Haskell's type system actually corresponds to an inconsistent logic system. However, if we work with a limited subset of Haskell's type system, and in particular disallow polymorphic types, we have a consistent logic system we can do some cool stuff in. Hereafter it is assumed we are working in such a type system.

Now that we have the basics of CH, we can begin to unpack a little more the relationship between types and propositions.

Logical operations and their equivalents
The essence of symbolic logic is a set of propositions, such as P and Q, and different ways of combining these propositions such as Q → P or $$P \vee Q$$. These ways of combining propositions can be thought of as operations on propositions. By CH, propositions correspond to types, so we should have that the CH equivalents of these proposition combinators are type operations, more normally known as type constructors. We've already seen an example of this: the implication operator → in logic corresponds to the type constructor. The rest of this section proceeds to explore the rest of the proposition combinators and explain their correspondence.

Conjunction and Disjunction
In order for $$A \wedge B$$ to be a theorem, both A and B must be theorems. So a proof for $$A \wedge B$$ amounts to proving both A and B. Remember that to prove a proposition A we find a value of type, where A and   are CH correspondents. So in this instance we wish to find a value that contains two sub-values: the first whose type corresponds to A, and the second whose type corresponds to B. This sounds remarkably like a pair. Indeed, we represent the symbol string $$A \wedge B$$ by, where   corresponds to A and   corresponds to B.

Disjunction is opposite to conjunction. In order for $$A \vee B$$ to be a theorem, either A or B must be a theorem. Again, we search for a value which contains either a value of type  or a value of type. This is. is the type which corresponds to the proposition $$A \vee B$$.

Falsity
It is occasionally useful to represent a false statement in our logic system. By definition, a false statement is one that can't be proven. So we're looking for a type which isn't inhabited. Although none of these types exist in the default libraries (don't get confused with the  type, which has precisely one value), we can define one (or for older versions of GHC that does not support Haskell2010, we turn on the   flag):

data Void

The effect of omitting the constructors means that  is an uninhabited type. So the  type corresponds to a nontheorem in our logic. There are a few handy corollaries here:

  and  are both uninhabited types for any type , corresponding to the fact that $$F \wedge A$$ and $$A \wedge F$$ are both nontheorems if F is a nontheorem.   and  are essentially the same as   for any type , corresponding to the fact that $$F \vee A$$ and $$A \vee F$$, where F is a nontheorem, are theorems only if A is a theorem.   Any type that corresponds to a nontheorem can be replaced with. This is because any nontheorem-type must be uninhabited, so replacing it with  everywhere doesn't change anything. is really equivalent to any nontheorem type.   As we remarked in the first section, the implication P → Q is true if Q is true, regardless of the truth value of P. So we should be able to find a term with type. In fact one does exist, but it's somewhat complicated to explain: the answer is the empty function. We can define a function  as a (probably infinite) set of pairs whose first element is an element of   (the domain) and second element is  's output on this term, an element of   (the codomain). For example, the successor function on the naturals is represented as. Note that in order to be a (total and well-defined) function, we must have precisely one pair  for each term   with type.

The empty function, let's call it  is represented in this way by the empty set. But as we must have a pair for each element of the domain, and there no pairs in our representation, the domain type must be empty, i.e. . What about the range type? never produces any output, so there are no restrictions placed on the range type. Thus, it is valid to assume that the range type has any type, so we can say. Unfortunately, it's not possible to write this function in Haskell; we'd ideally like to write something like:

empty :: Void -> a

And stop there, but this is illegal Haskell. The closest we can come is the following:

empty :: Void -> a empty _ = undefined

Alternatively:

empty :: Void -> a empty = empty

Another reasonable way would be to write (valid in GHC with EmptyCase extension):

empty x = case x of { }

The case statement is perfectly well formed since it handles every possible value of.

Note that this is perfectly safe, since the right-hand side of this function can never be reached (since we have nothing to pass it). So, the conclusion of all this is that  is an inhabited type, just as P → Q is true if P is false.

Negation
The ¬ operation in logic turns theorems into nontheorems and vice versa: if A is a theorem then ¬A is a nontheorem; if A is a nontheorem then ¬A is a theorem. How can we represent this in Haskell? The answer's a sneaky one. We define a type synonym:

type Not a = a -> Void

So for a type,   is just. How does this work? Well, if  was a theorem-type, then   must be uninhabited: there's no way any function could return any value, because the return type,   has no values (The function has to provide values for all inhabitants of A)! On the other hand, if  was a nontheorem, then   can be replaced with   as we explored in the last section. Then the function  is an inhabitant of , so   is a theorem as required (The function doesn't have to provide any values, since there are no inhabitants in its domain. Nevertheless it's a function — with an empty graph).

Axiomatic logic and the combinatory calculus
So far we've only used some very basic features from Haskell's type system. Indeed, most of the features of logic we've mentioned can be explored using a very basic 'programming language', the combinator calculus. To fully appreciate how closely CH ties together these two areas of mathematics, we need to axiomatise both our discussion of formal logic and our discussion of programming languages.

Axiomatic logic
We start with two axioms about how the → operation should behave (from now on, we assume that → is a right-associative function, i.e. A → B → C means A → (B → C)):

 * 1) A → B → A
 * 2) (A → B → C) → (A → B) → A → C

The first axiom says that given any two propositions A and B, if we assume both A and B, we know that A is true. The second says that if A implies that B implies C (or equivalently, if C is true whenever A and B are true), and A itself implies B, then knowing A is true would be enough to conclude that C is true. This may seem complicated, but a bit of thought reveals it to be common sense. Imagine we have a collection of boxes of various colours, some with wheels, some with lids, such that all the red boxes with wheels also have lids, and all the red boxes have wheels. Pick one box. Let A = 'The box under consideration is red', B = 'The box under consideration has wheels', C = 'The box under consideration has a lid'. Then the second law tells us that, as A → B → C (all red boxes with wheels also have lids), and A → B (all red boxes have wheels), then if A (if the box is red), then C must be true (the box has a lid).

We also allow one inference law, called modus ponens:

 * 1) If A → B, and A, then B.

This law allows us to create new theorems given old one. It should be fairly obvious; it is essentially the definition of what → means. This small basis provides a simple enough logic system which is expressive enough to cover most of our discussions. Here's a sample proof of the law A → A in our system:

Firstly, we know the two axioms to be theorems: You'll notice that the left-hand side of the second axiom looks a bit like the first axiom. The second axiom guarantees that if we know that A → B → C, then we can conclude (A → B) → A → C. In this case, if we let C be the same proposition as A, then we have that if A → B → A, then (A → B) → A → A. But we already know A → B → A, that was the first axiom. Therefore, we have that (A → B) → A → A is a theorem. If we further let B be the proposition C → A, for some other proposition C, then we have that if A → C → A, then A → A. But, again, we know that A → C → A (it's the first axiom again), so A → A, as we wanted.
 * A → B → A
 * (A → B → C) → (A → B) → A → C

This example demonstrates that given some simple axioms and a simple way to make new theorems from old, we can derive more complicated theorems. It may take a while to get there — here we had several lines of reasoning to prove just that the obvious statement A → A is a theorem! — but we get there in the end. This kind of formalisation is attractive because we have essentially defined a very simple system, and it is very easy to study how that system works.

Combinator calculus
The lambda calculus is a way of defining a simple programming language from a very simple basis. If you haven't already read the chapter that was just linked to, we recommend you read at least the introductory sections on the untyped version of the calculus. Here's a refresher in case you're feeling dusty. A lambda term is one of three things:

 * A value, v.
 * A lambda abstraction $$\lambda x. t$$, where t is another lambda term.
 * An application $$(t_1 t_2)$$, where $$t_1$$ and $$t_2$$ are lambda terms.

There is one reduction law, too, called beta-reduction:

 * $$((\lambda x. t_1) t_2)$$ → $$t_1[x := t_2]$$, where $$t_1[x := t_2]$$ means $$t_1$$ with all the free occurrences of x replaced with $$t_2$$.

As mentioned in the lambda calculus article, the difficulty comes when trying to pin down the notion of a free occurrence of an identifier. The combinator calculus was invented by the American mathematician Haskell Curry (after whom a certain programming language is named) because of these difficulties. There are many variants on the basic combinator calculus, but we consider one of the simplest here. We start with two so-called combinators:

 * K takes two values and returns the first. In the lambda calculus, $$\mathbf{K} = \lambda xy.\ x$$.
 * S takes a binary function, a unary function and a value, and applies that value and the value passed into the unary function to the binary function. again, in the lambda calculus: $$\mathbf{S} = \lambda xyz.\ xz(yz)$$.

The first function you should recognise as. The second is more complicated, it is the monadic function  in the   monad (which is essentially Reader). These two combinators form a complete basis for the entire lambda calculus. Every lambda calculus program can be written using just these two functions.

Intuitionistic vs classical logic
So far, all of the results we have proved are theorems of intuitionistic logic. Let's see what happens when we try to prove the basic theorem of classical logic,. Recall that this translates as. So, given a function of type  we need a function of type A. Now a function of type   exists precisely if type   is uninhabited, or in other words if type A is inhabited. So we need a function which takes any inhabited type, and returns an element of that type. Although it is simple enough to do this on a computer - we need only find the "simplest" or "first" inhabitant of each type - there is no way to do this using standard lambda-calculus or combinator techniques. So we see that this result cannot be proved using these two techniques, and hence that the underlying logic is intuitionistic rather than classical.

Instead, consider a traditional error handling function which calls  when an error occurs, transferring computation to. The  function cancels any return value from the original function, so it has type , where   is the type of its arguments. The  function then takes the   function as its argument, and, if the   triggers (i.e. returns a  ) will return the argument of the   function. So the type of  is.

title: Haskell/The Curry–Howard isomorphism


text:
ERP Internals/Modules/Employee Scheduling

Employee Scheduling handles shift allocations for enterprises that have more than one shift per day or operate more than five days per week. This involves defining what shifts have to be covered, the type and number of staff required, and the rules (min/max hours, seniority) for allocating employees to the shifts. Employee Scheduling then produces schedules for a specified number of periods into the future. Manufacturing and Employee Scheduling may interact. Many low-end ERP packages do not have an Employee Scheduling module.

 * Functions
 * Reports

Data Exchange
Employee Scheduling does not send or receive transactions to/from other modules but it uses information from the HR Planned Days Off table to update its Staff Availability table.

Transactions
Employee Scheduling


text:
Welsh/Authors

This page is meant to provide information about people who feel they have made a contribution to this book and wish to cooperate on its development.

Please feel free to add yourself here if you match the description above. Use  *  to add a name.

Authors

 * Kijog
 * AledJames - Aled was born in Wales, and has fluently spoke the language since he was 5 and now attends a fully Welsh speaking school.
 * Brenin_yr_elyrch

title: Welsh/Authors


text:
ERP Internals/Glossary/Return Material Authorization

Return Material Authorization means the return of goods previously sold and shipped to customers. It may cause credit memos to be issued to Accounts Receivable and may return goods to Inventory. Both of these activities result in data being sent to General Ledger. Each return is assigned a unique number and information is gathered which can be tracked until there is a satisfactory resolution.


text:
The Computer Revolution/Internet/Crime

The main Internet security concerns are the computer crimes committed through either gaining unauthorized access (hacking, war driving, interception of communication) or through unauthorized use(using the computer for unauthorized activities).

Some of the measures taken to protect against unauthorized access and use are the use of Access control systems: possessed knowledge access systems (passwords, PINs), possessed object access systems (smart cards, badges, magnetic cards), biometric access systems (using biological characteristics) and controlling access to wireless networks.

On top on these tools, some other measures can be taken to prevent illegal access to a computer such as using firewalls, encryption, VPN’s.

Another type of crime is the computer sabotage using malware (viruses, worms, Trojan horses, mobile malware), denial of service attacks and Data/Program/site alterations. The best methods to protect against computer sabotage is by using security software.

The third type of crime is online theft/fraud by which data, information and money are being stolen. The most common crime in this category is Identity theft often enabled by phishing and pharming. The best measures to protect against theft/fraud are to guard personal info, use credit cards for online purchases, avoid clicking on links in e-mail messages to update personal info.

Spam
Unsolicited e-mail that an individual does not want and doesn't have the time to read. It is unavoidable because of online transactions. Nowadays people are involved in many online activities which helps spam to get into an email address. It is always in the form of bulk mail. It can help virus to enter into the computer. We should never open any unknown email in order to protect our computer from all threats. There are different forms of spam such as web based spam and email based spam. E-mail spam enters through email addresses and web based spam can enter in different ways like when we visit some web sites the message box pops up and ask to register for some online activities for free. It is usually in the form of advertising or chain letters, junk mail, ads, and other un-wanted materials.

Spam filters are available for those who do not want to receive spam.

It is important to reject or ignore spam by:

 * delete immediately without opening it. (No peeking)
 * It is a bad idea to respond to the spam. (It could cause you VIRUSES or steal your money!)
 * Opt out! (no means no. Say no to spam)
 * When in doubt always ask for help. Ask your internet access provider. And get a spam filter (if you know what's good for you)
 * Stop the Spam Bully Now! Fight back. email www.abuse.net  No one needs to get sand (oops I mean spam) kicked in their face.

Software Piracy

Software piracy is the illegal reproduction or copying of a computer program, typically with the intent of redistributing or selling to other users. In 2009 a report from the Business Software Alliance (BSA) stated that about 41% of all software in use on personal computers is installed illegally (Deborah Morley, Charles S. Parker. The Understanding Computers Today and Tomorrow 13th Editions. Boston: Course Technology, 2011. Page 603). Software Piracy includes DVD’s, CD’s and programs. There are also several sites that use Torrent files that can be downloaded and share with other users.

Torrents

A Torrent file isn’t actually a file itself but is a collection of locations where pieces of the file can be obtained. This allows a user to download large files at an extremely fast rate by downloading several piece of the file from different sources. One of the most popular sites that is located in Sweden is called Pirate Bay. Pirate Bay provides millions of torrents that include operating systems, movies, books, music albums and all types of programs for free. Pirate Bay is just one of several sites available to access Illegal software and they all reside in countries that do not have anti-piracy laws in place. Although Majority of ISP providers do log and monitor this illegal activity there are several ways to avoid being caught using these sites to download Torrents (BitTorrent and µTorrent Software Surpass 150 Million User Milestone". Bittorrent.com. 2012-01-09. http://www.bittorrent.com/intl/es/company/about/ces_2012_150m_users. Retrieved 2012-29-11).

title: The Computer Revolution/Internet/Crime


text:
The Computer Revolution/Internet/Connections

Narrowband
Narrowband is also known as dial up modem. It is low speed and inexpensive. It uses telephone modems to connect computers to the Internet. Telephone lines are widely available. Therefore, many home computer users still use this type of Internet connection.

Narrowband is also known as voiceband and used for regular telephone communication, which includes speech, faxes and data. Dial up modems use the same bandwidth that is used for telephone communications, which is 100 kilobits per second or less. Bandwidth is used for short distances.

Because narrowband is somewhat slow, fewer people in the world are accessing the Internet using a narrowband connection. Nielsen/Net Ratings' latest figures show that 77.4m people in the US used a dial-up connection from home in December. This is down 10 per cent from the previous year. By comparison, 33.6m - an annual increase of almost 60 per cent - used a broadband connection from home to access the Net. Broadband connection is characterized by a bandwidth of very high speed.

"2002 marked an entire year of decline for narrowband usage at home," said Greg Bloom, senior Internet analyst, Nielsen//NetRatings. "As the broadband infrastructure continues to expand across the US, we expect to see the mainstream online population convert to higher speeds," he said. http://www.theregister.co.uk/2003/01/16/narrowband_net_use_declines/

The research also found that broadband users do more online than their narrowband counterparts. Narrowband usage will likely continue to decrease in popularity as speed becomes more important when accessing the internet.

Cable
Trjiririjdk hrough the use of an underground coaxial cable, internet connection speeds vary between 12 and 30 Mbps, considerably faster than other broadband connections such as DSL. Cable although, is only available where there is cable television providing previously dug underground coaxial cables. Despite it being averaged at about $40 to $60 per month, it is the most used broadband connection.

ISP
Internet Service Provider (ISP) is a company that provides Internet access, usually for a fee. This includes conventional and mobile telephone companies like AT&T, Verizon and Sprint this are just some. There are different classifications of ISPs. ISP servers are continually connected to a larger network, called a regional network.

Introduction to Network Access Protection
Network Access Protection (NAP) is a platform that allows to better protect network assets.NAP has an infrastructure and an API set for extending its functionality. Software developers can use the API(Application programming interface), which provides information and services to application programs and users can write their own programs for use with a specific product. taken from url: http://www.microsoft.com/technet/itsolutions/network/nap/default.mspx Network Access Protection Platform Architecture Internet Protocol Security Enforcement in the Network Access Protection Platform Network Access Protection Partners To find out about the leaders in the industry that have supported NAP click on the link url:http://www.microsoft.com/windowsserver2003/partners/nappartners.mspx
 * In other words NAP is a platform to perform computer health policy validation, ensure ongoing compliance with health policies, and does not allow unhealthy computers to access the system, or computers that do not comply with the policies. NAP has a client and a server architecture. taken fromurl: http://www.microsoft.com/technet/itsolutions/network/nap/naparch.mspx
 * Internet Protocol security (IPsec) is a system of rules and standards that protects the Internet traffic. IPsec support in the NAP platform protects the computers in a way that unhealthy computers that do not comply with the regulations can not send information to computers that are healthy and eliminates the possibility of viruses. taken from url: http://www.microsoft.com/technet/itsolutions/network/nap/napipsec.mspx

Internet2
'''The term "Internet" simply refers to a network of computers. The one that most of us use is Internet1, or the "commodity Internet." '''

Internet2 or UCAID (University Corporation for Advanced Internet Development) is a non-profit cooperative university/business education and research project that enables high-end users to quickly and reliably move huge amounts of data over high-speed networks, both nationally and internationally. Internet2 is a separate network from Internet1. Led by the research and education community since 1996, Internet2 adds "toll lanes" to the older Internet to speed things up. The purpose is to advance videoconferencing, research, and academic collaborations-to enable a kind of "virtual university."

What makes Internet2 so different?

It has many fewer users and much faster connections. Internet2 moves data 100 to 1,000 times faster than the old-fashioned Internet. Internet2 is led by 207 universities [1] in the United States and partners from the networking (Cisco Systems), publishing (Prous Science) and technology industries (such as Comcast, Intel, Sun Microsystems). Some of the technologies it has developed include IPv6, IP multi-casting and quality of service. Internet2 is a registered trademark. Organizations that want to join up must demonstrate a research-related purpose, pay dues, and meet minimum technical requirements so they don't slow down the rest of the Internet2 empire. A typical university would pay about $200,000 a year. Internet2 is also a service engine for 60 companies and a handful of organizations and government agencies. http://en.wikipedia.org/wiki/Internet2 and taken from page 62 in the text "Using Information Technology" Williams/Sawyer.

Beyond just providing network capacity, Internet2 actively engages our community in the development of important new technology including middleware, security, network research and performance measurement capabilities which are critical to the progress of the Internet. http://www.internet2.edu/about/

Will Internet2 ever be open to the public?

Probably not. But the technologies developed in Internet2 will gradually be transferred to the original Internet, making it faster and more stable. The goal is to "create the next-generation Internet," says network director Brian Buege of the University of Missouri-Rolla. http://www.usatoday.com/tech/news/techinnovations/2005-04-13-qa-internet2_x.htm


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The Computer Revolution/Internet/Security

Internet security falls into categories of software that have been developed to ensure that we all enjoy ourselves on the internet. There are three major areas of concern surrounding internet security : Authentication of the information (the information is authentic), authorization (the user has permission to use it), and confidentiality. Confidentiality is a area of major concern because many people shop online, bank online etc. We need to know that our information will not be published to the masses when we enter a site. There is an institutes that has compiled a database and training program for the internet called CERT. The security is some times important since it can lead your life in danger, you may create a new email but for sure you cannot delete the information which is stolen.

Malware
Malware is a type of software that intentionally or ‘maliciously’ damages a computer. It can perform its task in a matter of seconds that it was installed. In order for the malware to be installed is fairly easy; a simple action like a key stroke will do the trick. Malware can damage programs, slow the computer, erase files, and delete the whole hard drive and so on. The unfortunate thing about malware is that anyone can post the malware code on the web and no legal actions will take place. Also it is very time consuming to fix the malware. One specific type of malware is called spyware.

Spyware
Spyware is when a software program is installed without the user’s knowledge. This software program secretly gathers information about the user and takes it through his or her internet connection. This program is sometimes used for advertisers to gather information for marketing purposes. For example, what advertisements were selected on a page and how they should be formatted on that page to make it look more interesting. This software is not used for personal identification but can be a threat because people do not know that the software is on their computers. This kind of software is getting worse and harsher. Now stealthware is being used to deliberately change all of the settings and basically hijacking your settings. Criminals can get a hold of your personal information and can do various things with it. So spyware can be very bad for your computer slowing it down and everything making it an inconvenience for you.

Access Controls Systems
A way to protect against unauthorized access of a network or an individual web site is to have an Access Control System. The Access Control System works in two ways. One, it can be an identification system which means that it verifies that the person trying to access the site or network is on the authorized list of users. Second, the access control system can be an authentication system where it verifies that the person trying to access the network or web site is actually who they say they are. A Possessed Knowledge Access System uses passwords and cognitive authorization. With this system an individual needs to provide personal information such as, city of birth to gain access to the site or network. Another access system is the possessed object access this system uses access cards to allow access. The Biometric Access system identifies users by a particular biological characteristic. Biometric systems include iris recognition, face recognition, fingerprint recognition and hand geometry.

To further increase security, you can combine methods to authenticate a user to create a two-factor authentication. This method would include possessed knowledge along with a possessed object or a biometric feature, this makes it more difficult for hackers since they would have to gain access to both factors. Two-factor authentication use is growing rapidly in the United States since a 2007 federal guideline went into effect that instructs financial institutions to start using this method in place of single-factor authentication systems. Some banks are even offering an OTP (one-time password) access card to be used as the second step in your online authentication log-in process. (Morley, Deborah, and Charles S. Parker. Understanding Computers: Today and Tomorrow. 13th ed. Boston: Course Technology/Cengage Learning, 2011. Print.)

Computer Security is extremely important ! Passwords or pass codes help protect hackers from getting onto your computer and stealing any information that may be saved on the computer. There are two types of passwords. Biometric Characteristics is like using your finger prints in order to access the computer. The other one is just a simple password that locks your desktop until the correct pass code is entered. You can also purchase security software like firewall which will help protect against unauthorized people.

Information Privacy

Privacy is the state of being free from unauthorized intrusion, something that is a main concern when talking about computer security. The most important aspect of security in relation to computers is information privacy. Information privacy refers to the rights of individuals to control how information about them is collected and used. Individuals today are often concerned about the privacy of their web site activity and e-mail. Other privacy concerns are spam, electronic surveillance and electronic monitoring.


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The Computer Revolution/Internet/VoIP

VoIP
Voip is the method in which the internet can carry voice transmission from one source to another. These may include PC to PC in which two computers use microphones. Another idea is PC to phone. Anyone can call from a personal PC to any phone line anywhere in the world.

(http://voip.teleclick.ca/voip-internet-telephony.php)

Voice over Internet Protocol (VoIP)
VoIP is the process of placing phone calls over the Internet. One example of this is a computer to computer call via the “Skype” service, which allows you to connect and talk with someone from another computer. Vonage is a VoIP provider which is a permanent setup designed to take the place of traditional landline phones. One advantage of this type of service is that it is low cost. The big disadvantage, is that it cannot function during a power outage, or if your Internet connection goes down.

title: The Computer Revolution/Internet/VoIP


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Microprocessor Design/ALU

Microprocessors tend to have a single module that performs arithmetic operations on integer values. This is because many of the different arithmetic and logical operations can be performed using similar (if not identical) hardware. The component that performs the arithmetic and logical operations is known as the Arithmetic Logic Unit, or ALU.

The ALU is one of the most important components in a microprocessor, and is typically the part of the processor that is designed first. Once the ALU is designed, the rest of the microprocessor is implemented to feed operands and control codes to the ALU.

Tasks of an ALU
ALU units typically need to be able to perform the basic logical operations (AND, OR) and the addition operation. The inclusion of inverters on the inputs enables the same ALU hardware to perform the subtraction operation (adding an inverted operand), and the operations NAND and NOR.

A basic ALU design involves a collection of "ALU Slices", which each can perform the specified operation on a single bit. There is one ALU slice for every bit in the operand.

Example: 2-Bit ALU
This is an example of a basic 2-bit ALU. The boxes on the right hand side of the image are multiplexers and are used to select between various operations: OR, AND, XOR, and addition.

Notice that all the operations are performed in parallel, and the select signal ("OP") is used to determine which result to pass on to the rest of the datapath. Notice that the carry signal, which is only used for addition, is generated and passed out of the ALU for every operation, so it is important that if we aren't performing addition that we ignore the carry flag.

Example: 4-Bit ALU
Here is a circuit diagram of a 4 bit ALU.

Additional Operations
Logic and addition are some of the easiest, but also the most common operations. For this reason, typical ALUs are designed to handle these operations specially, and other operations, such as multiplication and division, are handled in a separate module.

Notice also that the ALU units that we are discussing here are only for integer datatypes, not floating-point data. Luckily, once integer ALU and multiplier units have been designed, those units can be used to create floating-point units (FPU).

ALU Configurations
Once an ALU is designed, we need to define how it interacts with the rest of the processor. We can choose any one of a number of different configurations, all with advantages and disadvantages. Each category of instruction set architecture (ISA) -- stack, accumulator, register-memory, or register-register-load-store -- requires a different way of connecting the ALU. In all images below, the orange represents memory structures internal to the CPU (registers), and the purple represents external memory (RAM).

Accumulator

An accumulator machine has one special register, called the accumulator. The accumulator stores the result of every ALU operation, and is also one of the operands to every instruction. This means that our ISA can be less complicated, because instructions only need to specify one operand, instead of two operands and a destination. Accumulator architectures have simple ISAs and are typically very fast, but additional software needs to be written to load the accumulator with proper values. Unfortunately, accumulator machines are difficult to pipeline.

One example of a type of computer system that is likely to use an accumulator is a common desk calculator.

Register-to-Register

One of the more common architectures is a Register-to-register architecture, also called a 3 register operand machine. In this configuration, the programmer can specify both source operands, and a destination register. Unfortunately, the ISA needs to be expanded to include fields for both source operands and the destination operands. This requires longer instruction word lengths, and it also requires additional effort (compared to the accumulator) to write results back to the register file after execution. This write-back step can cause synchronization issues in pipelined processors (we will discuss pipelining later).

Register Stack

A register stack is like a combination of the Register-to-Register and the accumulator structures. In a register stack, the ALU reads the operands from the top of the stack, and the result is pushed onto the top of the stack. Complicated mathematical operations require decomposition into Reverse-Polish form, which can be difficult for programmers to use. However, many computer language compilers can produce reverse-polish notation easily because of the use of binary trees to represent instructions internally. Also, hardware needs to be created to implement the register stack, including PUSH and POP operations, in addition to hardware to detect and handle stack errors (pushing on a full stack, or popping an empty stack).

The benefit comes from a highly simplified ISA. These machines are called "0-operand" or "zero address machines" because operands don't need to be specified, because all operations act on specified stack locations.

In the diagram at right, "SP" is the pointer to the top of the stack. This is just one way to implement a stack structure, although it might be one of the easiest.

Register-and-Memory

One complicated structure is a Register-and-Memory structure, like that shown at left. In this structure, one operand comes from a register file, and the other comes from external memory. In this structure, the ISA is complicated because each instruction word needs to be able to store a complete memory address, which can be very long. In practice, this scheme is not used directly, but is typically integrated into another scheme, such as a Register-to-Register scheme, for flexibility.

Some CISC architectures have the option of specifying one of the operands to an instruction as a memory address, although they are typically specified as a register address.

Complicated Structures
There are a number of other structures available, some of which are novel, and others are combinations of the types listed above. It is up to the designer to decide exactly how to structure the microprocessor, and feed data into the ALU.

Example: IA-32
The Intel IA-32 ISA (x86 processors) use a register stack architecture for the floating point unit, but it uses a modified Register-to-Register structure for integer operations. All integer operations can specify a register as the first operand, and a register or memory location as the second operand. The first operand acts as an accumulator, so that the result is stored in the first operand register. The downside to this is that the instruction words are not uniform in length, which means that the instruction fetch and decode modules of the processor need to be very complex.

A typical IA-32 instruction is written as:

ADD AX, BX

Where AX and BX are the names of the registers. The resulting equation produces AX = AX + BX, so the result is stored back into AX.

Example: MIPS
MIPS uses a Register-to-Register structure. Each operation can specify two register operands, and a third destination register. The downside is that memory reads need to be made in separate operations, and the small format of the instruction words means that space is at a premium, and some tasks are difficult to perform.

An example of a MIPS instruction is:

ADD R1, R2, R3

Where R1, R2 and R3 are the names of registers. The resulting equation looks like: R1 = R2 + R3.

title: Microprocessor Design/ALU


text:
Microprocessor Design/Basic Components

Basic Components
There are a number of components in a common microprocessor that designers should be familiar with before attempting a design. For an overview of these components, see Digital Circuits.

Registers
A register is a storage element typically composed of an array of smaller, 1-bit storage elements called flip-flops. The number of bits that the register is composed of equals the number of bits that the register can store at any given time. For example, a 1-bit register can store 1 bit, and a 32-bit register can hold 32 bits, etc. Registers can be any length.

A register has two inputs, a data input and a clock input. The clock input is typically called the "enable". When the enable signal is high, the register stores the data input. When the clock signal is low, the register value stays the same.

Register File
A register file is a whole collection of registers, typically all of which are the same length. A register file takes three inputs, an index address value, a data value, and an enable signal. A signal decoder is used to pass the data value from the register file input to the particular register with the specified address. We talk more about register files in a later section of this book, ../Register File/.

Multiplexers

A multiplexer is an input selector. A multiplexer has an output, a control input, and several data inputs. For ease, we number multiplexer inputs from zero, at the top. If the control signal is "0", the 0th input is moved to the output. If the control signal is "3", the 3rd input is moved to the output.

A multiplexer with N control signal bits can support 2N inputs. For example, a multiplexer with 3 control signals can support 23 = 8 inputs.

Multiplexers are typically abbreviated as "MUX", and will be abbreviated as such throughout the rest of this book.

There can be decoders implemented in the components. Decoder ( inverse functionality of Encoder) can have multiple inputs and depending upon the inputs one of the output signals can go high.

For a 2 input decoder there will be 4 output signals. /|- O0 i0---| |- O1  i1---| |- O2        \|- O3

suppose input i is having value 00 then output signal O0 will go high and remaining other three lines O1 to O3 will be low. In same fashion if i is having value 2 then output O2 will be high and remaining other three lines will be low.

title: Microprocessor Design/Basic Components


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Microprocessor Design/Program Counter

The Program Counter (PC) is a register structure that contains the address pointer value of the current instruction. Each cycle, the value at the pointer is read into the instruction decoder and the program counter is updated to point to the next instruction. For RISC computers updating the PC register is as simple as adding the machine word length (in bytes) to the PC. In a CISC machine, however, the length of the current instruction needs to be calculated, and that length value needs to be added to the PC.

Updating the PC
The PC can be updated by making the enable signal high. After each instruction cycle the PC needs to be updated to point to the next instruction in memory. It is important to know how the memory is arranged before constructing your PC update circuit.

Harvard-based systems tend to store one machine word per memory location. This means that every cycle the PC needs to be incremented by 1. Computers that share data and instruction memory together typically are byte addressable, which is to say that each byte has its own address, as opposed to each machine word having its own address. In these situations, the PC needs to be incremented by the number of bytes in the machine word.

In this image, the letter M is being used as the amount by which to update the PC each cycle. This might be a variable in the case of a CISC machine.

Branching
Branching occurs at one of a set of special instructions known collectively as "branch" or "jump" instructions

. In a branch or a jump, control is moved to a different instruction at a different location in instruction memory.

During a branch, a new address for the PC is loaded, typically from the instruction or from a register. This new value is loaded into the PC, and future instructions are loaded from that location.

Non-Offset Branching
A non-offset branch, frequently referred to as a "jump" is a branch where the previous PC value is discarded and a new PC value is loaded from an external source.

In this image, the PC value is either loaded with an updated version of itself, or else it is loaded with a new Branch Address. For simplification we do not show the control signals to the MUX.

Offset Branching
An offset branch is a branch where a value is added (or subtracted) to the current PC value to produce the new value. This is typically used in systems where the PC value is larger then a register value or an immediate value, and it is not possible to load a complete value into the PC. It is also commonly used to support relocatable binaries which may be loaded at an arbitrary base address.

In this image there is a second ALU unit. Notice that we could simplify this circuit and remove the second ALU unit if we use the configuration below:

These are just two possible configurations for this circuit.

Offset and Non-Offset Branching
Many systems have capabilities to use both offset and non-offset branching. Some systems may differentiate between the two as "near jump" and "far jump" respectively, although this terminology is archaic.

title: Microprocessor Design/Program Counter


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Microprocessor Design/Instruction Decoder

The Instruction Decoder reads the next instruction in from memory, and sends the component pieces of that instruction to the necessary destinations.

For each machine-language instruction, the control unit produces the sequence of pulses on each control signal line required to implement that instruction (and to fetch the next instruction).

If you are lucky, when you design a processor you will find that many of those control signals can be "directly decoded" from the instruction register. For example, sometimes a few output bits from the instruction register IR can be directly wired to the "which function" inputs of the ALU. Even if those bits mean something completely unrelated in non-ALU instructions, it's OK if the ALU performs, say, a bogus SUBTRACT, while the rest of the processor is executing a STORE instruction.

The remaining control signals that cannot be decoded from the instruction register -- if you are unlucky, all the control signals -- are generated by the control unit, which is implemented as a [Moore machine][2] or a [Mealy machine][3]. There are many different ways to implement the control unit.

If you design a processor with a Princeton architecture -- your processor normally pulls instructions from the same single-ported memory used to read and write data -- then you are forced to have at least LOAD and STORE take more than one clock cycle to execute. (One cycle for the data, and another cycle to read the next instruction). (Many processors are designed with "single-cycle execution", either very simple Harvard architecture processors, or complicated high-performance processors with a separate instruction cache).

RISC Instruction Decoder
The philosophy behind a RISC machine is that instruction execution is kept extremely fast and simple. Thus the instruction decoder, such as there is one must be as streamlined as possible. The tradeoff is that more instructions must be executed to perform the more complex machine functions. All low-level abstraction must be provided in the machine code compiler.

There are generally two variations to a RISC decoder.

In the first variant the bits of the instruction code are fed directly to the hardware components so there really is no decoder at all. All timing requirements must be met by careful programming of the machine code and there is no delay in execution from an instruction decoder. The necessary control line 'waveforms' are created directly by the sequence of instructions. As soon as the instruction is presented the hardware begins to respond. The bits in the instruction set directly represent the actual physical controls of the hardware components.

The second variant includes a simple (fast) decoder between the instruction code and the hardware components. This decoding is usually implemented by discrete logic gates. The primary purpose of this decoder is to allow a 'cleaner' instruction set representation. As with the direct variant, each instruction still represents a single machine function but the use of a decoder will often significantly reduce the number of bits needed in the machine code word. This in turn may allow several hardware functions to be initiated in a single machine instruction.

CISC Instruction Decoder
Decoding a CISC instruction word is much more difficult than the RISC case, and the increased complexity of the decoder is a common reason people cite when they choose to use RISC over CISC in their designs.

A CISC decoder commonly uses a state machine set up as a random length sequencer. The machine reads the opcode field to determine what type of instruction it is, and where the other data values are as needed. The instruction word may even be read in piece by piece, so decisions may be made at each stage as to how the remainder of the instruction word and any included data will be read.

This decoder sequences through a number of states of the machine hardware as opposed to the case of the RISC decoder. The instruction code selects which sequence is to be executed and the sequencer controls the timing of this performance. One 'step' in this performace may include fetching more input from the instruction code, whether this input is further instructions or needed data values.

Perhaps the easiest way to understand this decoder type is to conceive it as a very wide control store ROM. The program in this ROM is the microcode for the decoder/sequencer. A part of the instruction register is used to form part of the address to this ROM. Several bits of the address are feedback from the ROM itself. Most of the ROM's outputs are used to control the system hardware.

The feedback address portion forms a loop that will step through a random sequence as programmed into the ROM. This loop operates as fast as the access time of the ROM allows and is typically a single system clock. The feedback address is usually programmed to increment by 1 for each successive state of the sequencer. The number of feedback bits determines the maximum length of the microcoded sequence.

-

A pipeline register latches all the output bits of the control store ROM every clock cycle.

Each clock cycle the pipeline register latches a new set of bits.

The output of the sequencer has 2 components:

Control bits that go out to the hardware components of the processor. The "microPC" that feeds back to some of the address inputs of the control store ROM. Some people hardwire the carry flag to one of the address inputs of the control store ROM.

Every time a new opcode is fetched from main memory, typically the high bits of the microPC are loaded with the opcode, and the low bits of the microPC reset to zero. (To make things easier to debug, some designers load the opcode into both a separate instruction register IR as well as the microPC register, at least in the initial prototypes. Once the design is debugged, it might turn out that some or all the bits from the IR or the microPC register or both are never used, and so can be left out of the final design). During execution of the instruction, each clock cycle the pipeline register loads a new microPC address from the control store and a new set of control bits from the control store. Typically the person who writes the microprogram -- burned into the control store ROM -- designs the next-address output bits of that ROM to sequentially increment for the first few cycles of the implementation of that opcode. Then the microprogram for every "normal" opcode eventually jumps to one common section of the control store ROM that handles fetch-next-instruction.


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Microprocessor Design/Microcode

RISC units are typically faster and more efficient than CISC units. For this reason, many CISC processors have complicated instruction decoders that actually convert the CISC machine code into a RISC-like set of internal instructions known as microcodes. These microcodes are then fed into the internal core of the processor, which is based on the RISC design.

The most common way to implement memory-memory architecture CPUs (even with single-chip microprocessors, not just wire-wrapped machines) uses a small "control store" ROM. The output data bits of the control store are latched in the microinstruction register (reminiscent of the way instructions fetched from RAM are latched in the instruction register). The clock signal determining the cycle time of the system primarily clocks the microinstruction register. The bits stored in the microinstruction register directly control everything that goes on in the CPU. (In some processors, the microinstruction register is the only thing connected to the clock signal. Later we will discuss "pipelining", a technique involving pipeline registers connected to the clock signal).

Some of the bits in the microinstruction register do nothing but drive some of the address bits of the control store. Those bits -- that sub-field of the pipeline register -- is sometimes called the "microprogram counter", even though it is merely a latch -- typically the control store is programmed such that those bits increment on every clock cycle, and reset to zero when a new instruction is loaded into the instruction register. The instruction register directly drives some of the address lines of the control store ROM. A few more address lines of the control store ROM are driven by status bits such as the Z flag and the C flag.

Some CPUs, such as the ECOMIPS, the Intel Core 2 and the Intel Xeon, use "writable microcode" -- rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a Writable Control Store or WCS.

title: Microprocessor Design/Microcode


text:
Microprocessor Design/FPU

Similar to the ALU is the Floating-Point Unit, or FPU. The FPU performs arithmetic operations on floating point numbers.

An FPU is complicated to design, although the IEEE 754 standard helps to answer some of the specific questions about implementation. It isn't always necessary to follow the IEEE standard when designing an FPU, but it certainly does help.

Floating point numbers
This section is just going to serve as a brief refresher on floating point numbers. For more information, see the Floating Point book.

Floating point numbers are specified in two parts: the exponent (e), and the mantissa (m). The value of a floating point number, v, is generally calculated as:

 * $$v = m \times 2^e$$

IEEE 754
IEEE 754 format numbers are calculated as:

 * $$v = (1 + m) \times 2^e$$

The mantissa, m, is "normalized" in this standard, so that it falls between the numbers 1.0 and 2.0.

Floating Point Multiplication
Multiplying two floating point numbers is done as such:

 * $$v_1 \times v_2 = (m_1 \times m_2) \times 2^{(e_1 + e_2)}$$

Likewise, division can be performed by:

 * $$\frac{v_1}{v_2} = \frac{m_1}{m_2} \times 2^{(e_1 - e_2)}$$

To perform floating point multiplication then, we can follow these steps:

 * 1) Separate out the mantissa from the exponent
 * 2) Multiply (or divide) the mantissa parts together
 * 3) Add (or subtract) the exponents together
 * 4) Combine the two results into the new value
 * 5) Normalize the result value (optional).

Floating Point Addition
Floating point addition—and by extension, subtraction— is more difficult than multiplication. The only way that floating point numbers can be added together is if the exponents of both numbers are the same. This means that when we add two numbers together, we need first to scale the numbers so that they have the same exponent. Here is the algorithm:

 * 1) Separate the mantissa from the exponent of each number
 * 2) Compare the two exponents, and determine the difference between them.
 * 3) Add the difference to the smaller exponent, to make both exponents the same.
 * 4) Logically right-shift the mantissa of the number with the smaller exponent a number of spaces equal to the difference.
 * 5) Add the two mantissas together
 * 6) Normalize the result value (optional).

Floating Point Unit Design
As we have seen from the two algorithms above, an FPU needs the following components:

 * For addition/Subtraction:
 * A comparator (subtractor) to determine the difference between exponents, and to determine the smaller of the two exponents.
 * An adder unit to add that difference to the smaller exponent.
 * A shift unit, to shift the mantissa the specified number of spaces.
 * An adder to add the mantissas together

 * For multiplication/division:
 * A multiplier (or a divider) for the mantissa part
 * An adder for the exponent parts.

Both operation types require a complex control unit.

Both algorithms require some kind of addition/subtraction unit for the exponent part, so it seems likely that we can use just one component to perform both tasks (since both addition and multiplication won't be happening at the same time in the same unit). Because the exponent is typically a smaller field than the mantissa, we will call this the "Small ALU". We also need an ALU and a multiplier unit to handle the operations on the mantissa. If we combine the two together, we can call this unit the "Large ALU". We can also integrate the fast shifter for the mantissa into the large ALU.

Once we have an integer ALU designed, we can copy those components almost directly into our FPU design.

title: Microprocessor Design/FPU


text:
Microprocessor Design/Register File

Registers are temporary storage locations inside the CPU that hold data and addresses.

The register file is the component that contains all the general purpose registers of the microprocessor. A few CPUs also place special registers such as the PC and the status register in the register file. Other CPUs keep them separate.

When designing a CPU, some people distinguish between "architectural features" and the "implementation details". The "architectural features" are the programmer visible parts; if someone makes a new system where any of these parts are different from the old CPU, then suddenly all the old software won't work on the new CPU. The "implementation details" are the parts that, although we put even more time and effort into getting them to work, one can make a new system that has a different way of implementing them, and still keep software compatibility -- some programs may run a little faster, other programs may run a little slower, but they all produce the same results as on the earlier machine.

The programmer-visible register set has more impact on software compatibility than any other part of the datapath, and perhaps more than any other part in the entire computer. The architectural features of the programmer-visible register set are the number of registers, the number of bits in each register, and the logical organization of the registers. Assembly language programmers like to have many registers. Early microprocessors had painfully few registers, limited by the area of the chip. Today, many chips have room for huge numbers of registers, so the number of programmer-registers is limited by other constraints: More programmer-visible registers requires bigger operand fields. More programmer-visible registers requires more time saving and restoring registers on an interrupt or context switch. Software compatibility requires keeping exactly the same number, size, and organization of programmer-visible registers. Assembly language programmers like a "flat" address space, where the full address of any location in (virtual) memory fits in a single address register. And so the amount of (virtual) memory desired by an architect sets a minimum width to each address register.

The idea of "general registers" -- a group of registers, any one of which can, at different times, operate as a stack pointer, index register, accumulator, program counter, etc. was invented around 1971.

While registers can be implemented as a bank of flip-flop registers, SRAM-based full-custom register files use less area and power.

The overall performance of many single-chip CPUs is limited by the speed of the read operation of the register file.

Register File
A simple register file is a set of registers and a decoder. The register file requires an address and a data input.

However, this simple register file isn't useful in a modern processor design, because there are some occasions when we don't want to write a new value to a register. Also, we typically want to read two values at once and write one value back in a single cycle. Consider the following equation:

 * $$C = A + B$$

To perform this operation, we want to read two values from the register file, A and B. We also have one result that we want to write back to the register file when the operation has completed. For cases where we do not want to write any value to the register file, we add a control signal called Read/Write. When the control signal is high, the data is written to a register, and when the control signal is low, no new values are written.

In this case, it is likely advantageous for us to specify a third address port for the write address:

Many people choose to use a 3-port register file for their pipelined microprocessor so it can execute such an ALU instructions every cycle. Every cycle the CPU reads values from 2 registers in the register file to prepare for operating on them as directed by one instruction, and simultaneously the CPU writes the results from some previous instruction into some other register in the register file. (../Superscalar Processors/ and VLIW require a register file with 6 or more ports).

(Does a microprocessor with operand forwarding ever read from a register and write to the same register during the same clock cycle?)

Full-custom register files often start with a SRAM design. Like SRAM chips, SRAM-based register files include a differential pair of bit-lines for each port -- but instead of a single SRAM read/write port, register files typically have at least one dedicated write port and several dedicated read ports. A typical register file repeats this process every instruction cycle: First, the two bit-lines of a differential pair of each read port are shorted to each other and charged to Vdd/2 during a pre-charge phase. Then the word-line connects one bit cell to those lines -- slightly imbalancing the charge on those long bit lines. Finally, the CPU enables the sense amplifier which magnifies the slight imbalance to normal digital logic levels.

More registers than you can shake a stick at
Consider a situation where the machine word is very small, and therefore the available address space for registers is very limited. If we have a machine word that can only accommodate 2 bits of register address, we can only address 4 registers. However, register files are small to implement, so we have enough space for 32 registers. There are several solutions to this dilemma -- several ways of increasing performance by using many registers, even though we don't quite have enough bits in the instruction word to directly address all of them.

Some of those solutions include: and
 * special-purpose registers that are always used for some specific instruction, and so that instruction doesn't need any bits to specify that register.
 * In almost every CPU, the program counter PC and the status register are treated differently than the other registers, with their own special set of instructions.
 * separating registers into two groups, "address registers" and "data registers", so an instruction that uses an address needs enough bits to select one out of all the address registers, which is 1 less bit than one out of every register.
 * register windowing as on SPARC
 * using a "register bank".

Register Bank
The term "register bank" is used in two different senses. Some CPUs have several different groups (or "banks") of registers, rather than one monolithic register file.

One kind of "register banking" is similar to (main memory) bank switching. Because this kind is visible to the assembly language programmer, in this chapter we'll call it "architectural banked registers". Other kinds of "register banking" allow a CPU to run exactly the same software as a single-bank implementation (invisible to the assembly language programmer), so in in this chapter we'll call them "microarchitectural banked registers" -- these implementation options have various advantages over a monolithic register file implementation.

architectural banked registers
Consider a situation where the machine word is very small, and therefore the available address space for registers is very limited. If we have a machine word that can only accommodate 2 bits of register address, we can only address 4 registers. However, register files are small to implement, so we have enough space for 32 registers. The solution to this dilemma is to utilize a register bank which consists of a series of register files combined together.

A register bank contains a number of register files or pages. Only one page can be active at a time, and there are additional instructions added to the ISA to switch between the available register pages. Data values can only be written to and read from the currently active register page, but instructions can exist to move data from one page to another.

As can be seen in this image, the gray box represents the current page, and the page can be moved up and down on the register bank.

If the register bank has N registers, and a page can only show M registers (with N > M), we can address registers with two values, n and m respectively. We can define these values as:

 * $$n = \log_2(N)$$
 * $$m = \log_2(M)$$

In other words, n and m are the number of bits required to address N and M registers, respectively. We can break down the address into a single value as such:

Where p is the number of bits reserved to specify the current register page. As we can see from this graphic, the current register address is simply the concatenation of the page address and the register address.

microarchitectural banked registers
There are several techniques that divide up the physical registers into several physical register files ("banks"), using control logic to make the CPU as a whole still software-compatible to other implementations of the same CPU architecture that only use one monolithic register file. In modern high-performance CPU, such techniques are used to build software-compatible CPUs that run at higher speed, use less power, and require less area than implementing the same CPU architecture with a single conventional multiported register file.

Replicating the entire register file, as in the POWER2 and the Alpha 21264 and the Alpha 21464, is the simplest kind of microarchitectural register banking. These CPUs implemented their register file internally with 2 copies of the entire (architectural) register file, and connect half the functional units to each copy. This requires each register file to have the same number of write ports as a monolithic register file (since all writes are sent to *both* copies to keep them in sync), but each register file requires only half the number of read ports as a monolithic register file.

title: Microprocessor Design/Register File


text:
Microprocessor Design/Memory Unit

Microprocessors rely on memory for storing the instructions and the data used by software programs. The memory unit is responsible for communicating with the system memory.

Actions of the Memory Unit
All von Neumann CPUs store their instructions in memory.

In a Harvard architecture, the data memory unit and the instruction memory unit are two different units. However, in a Princeton architecture the two memory units are combined into a single module. Most modern PC computer systems are Princeton, not Harvard, so the memory unit must handle all instruction and data transactions. This can serve as a bottleneck in the design.

Timing Issues
The memory unit is typically one of the slowest components of a microcontroller, because the external interface with RAM is typically much slower than the speed of the processor.

title: Microprocessor Design/Memory Unit


text:
Microprocessor Design/Control Unit

The control unit reads the opcode and instruction bits from the machine code instruction, and creates a series of control codes to activate and operate the various components to perform the desired task.

Simple Control Unit
In its most simple form, a control unit can take the form of a lookup table. The machine word opcode is used as the index into the table, and the various control signals are output to the respective destinations.

Complex Control Unit
A more complex version of a control unit is implemented as a finite state machine (FSM). Multi-cycle, pipelined, and other advanced processor designs may require an FSM-based control unit.

title: Microprocessor Design/Control Unit