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Internet Engineering Task Force

The Internet Engineering Task Force (IETF) is a standards organization for the Internet and is responsible for the technical standards that make up the Internet protocol suite (TCP/IP). It has no formal membership roster or requirements and all its participants are volunteers. Their work is usually funded by employers or other sponsors.

The IETF was initially supported by the federal government of the United States but since 1993 has operated under the auspices of the Internet Society, a non-profit organization with local chapters around the world.

Organization
There is no membership in the IETF. Anyone can participate by signing up to a working group mailing list, or registering for an IETF meeting.

The IETF operates in a bottom-up task creation mode, largely driven by Working Groups. Each working group has an appointed chairperson (or sometimes several co-chairs); a charter that describes its focus; and what it is expected to produce, and when. It is open to all who want to participate and holds discussions on an open mailing list or at IETF meetings, where the entry fee in 2024 was between US$875 (Early Registration) and $1200 per person for the week. Significant discounts are available for students and remote participants. Because the majority of the IETF's work is done via mailing lists, meeting attendance is not required for contributors.

Rough consensus is the primary basis for decision making. There are no formal voting procedures. Each working group is intended to complete work on its topic and then disband. In some cases, the working group will instead have its charter updated to take on new tasks as appropriate.

The working groups are grouped into areas by subject matter. Current areas are Applications, General, Internet, Operations and Management, Real-time Applications and Infrastructure, Routing, Security, and Transport. Each area is overseen by an area director (AD), with most areas having two co-ADs. The ADs are responsible for appointing working group chairs. The area directors, together with the IETF Chair, form the Internet Engineering Steering Group (IESG), which is responsible for the overall operation of the IETF.

The Internet Architecture Board (IAB) oversees the IETF's external relationships and relations with the RFC Editor. The IAB provides long-range technical direction for Internet development. The IAB is also jointly responsible for the IETF Administrative Oversight Committee (IAOC), which oversees the IETF Administrative Support Activity (IASA), which provides logistical, etc. support for the IETF. The IAB also manages the Internet Research Task Force (IRTF), with which the IETF has a number of cross-group relations.

A Nominating Committee (NomCom) of ten randomly chosen volunteers who participate regularly at meetings is vested with the power to appoint, reappoint, and remove members of the IESG, IAB, IASA, and the IAOC. To date, no one has been removed by a NomCom, although several people have resigned their positions, requiring replacements.

In 1993 the IETF changed from an activity supported by the US Federal Government to an independent, international activity associated with the Internet Society, a US-based 501(c)(3) organization. Because the IETF itself does not have members, nor is it an organization per se, the Internet Society provides the financial and legal framework for the activities of the IETF and its sister bodies (IAB, IRTF). IETF activities are funded by meeting fees, meeting sponsors and by the Internet Society via its organizational membership and the proceeds of the Public Interest Registry.

In December 2005, the IETF Trust was established to manage the copyrighted materials produced by the IETF.

Steering group
The Internet Engineering Steering Group (IESG) is a body composed of the Internet Engineering Task Force (IETF) chair and area directors. It provides the final technical review of Internet standards and is responsible for day-to-day management of the IETF. It receives appeals of the decisions of the working groups, and the IESG makes the decision to progress documents in the standards track.

The chair of the IESG is the director of the General Area, who also serves as the overall IETF Chair. Members of the IESG include the two directors of each of the following areas:
 * Applications Area (app)
 * Internet Area (int)
 * Operations & Network Management Area (ops)
 * Routing Area (rtg)
 * Real-time Applications and Infrastructure Area (rai)
 * Security Area (sec)
 * Transport and Services Area (tsv) – frequently also referred to as the "Transport Area"

Liaison and ex officio members include:
 * IETF Executive Director
 * IAB Chair
 * Appointed Liaison from the IAB
 * Liaison from the Internet Assigned Numbers Authority (IANA)
 * Liaison from the Request for Comments (RFC) Editor

Early leadership and administrative history
The Gateway Algorithms and Data Structures (GADS) Task Force was the precursor to the IETF. Its chairman was David L. Mills of the University of Delaware.

In January 1986, the Internet Activities Board (IAB; now called the Internet Architecture Board) decided to divide GADS into two entities: an Internet Architecture (INARC) Task Force chaired by Mills to pursue research goals, and the IETF to handle nearer-term engineering and technology transfer issues. The first IETF chair was Mike Corrigan, who was then the technical program manager for the Defense Data Network (DDN). Also in 1986, after leaving DARPA, Robert E. Kahn founded the Corporation for National Research Initiatives (CNRI), which began providing administrative support to the IETF.

In 1987, Corrigan was succeeded as IETF chair by Phill Gross.

Effective March 1, 1989, but providing support dating back to late 1988, CNRI and NSF entered into a Cooperative Agreement No. NCR-8820945, wherein CNRI agreed to create and provide a "secretariat" for the "overall coordination, management and support of the work of the IAB, its various task forces and, particularly, the IETF."

In 1992, CNRI supported the formation and early funding of the Internet Society, which took on the IETF as a fiscally sponsored project, along with the IAB, the IRTF, and the organization of annual INET meetings. Phill Gross continued to serve as IETF chair throughout this transition. Cerf, Kahn, and Lyman Chapin announced the formation of ISOC as "a professional society to facilitate, support, and promote the evolution and growth of the Internet as a global research communications infrastructure". At the first board meeting of the Internet Society, Vint Cerf, representing CNRI, offered, "In the event a deficit occurs, CNRI has agreed to contribute up to USD102000 to offset it." In 1993, Cerf continued to support the formation of ISOC while working for CNRI, and the role of ISOC in "the official procedures for creating and documenting Internet Standards" was codified in the IETF's.

In 1995, IETF's describes ISOC's role in the IETF as being purely administrative, and ISOC as having "no influence whatsoever on the Internet Standards process, the Internet Standards or their technical content".

In 1998, CNRI established Foretec Seminars, Inc. (Foretec), a for-profit subsidiary to take over providing Secretariat services to the IETF. Foretec provided these services until at least 2004. By 2013, Foretec was dissolved.

In 2003, IETF's described IETFs role in appointing 3 board members to the ISOC's board of directors.

In 2018, ISOC established The IETF Administration LLC, a separate LLC to handle the administration of the IETF. In 2019, the LLC issued a call for proposals to provide secretariat services to the IETF.

Meetings
The first IETF meeting was attended by 21 US Federal Government-funded researchers on 16 January 1986. It was a continuation of the work of the earlier GADS Task Force. Representatives from non-governmental entities (such as gateway vendors ) were invited to attend starting with the fourth IETF meeting in October 1986. Since that time all IETF meetings have been open to the public.

Initially, the IETF met quarterly, but from 1991, it has been meeting three times a year. The initial meetings were very small, with fewer than 35 people in attendance at each of the first five meetings. The maximum attendance during the first 13 meetings was only 120 attendees. This occurred at the 12th meeting held during January 1989. These meetings have grown in both participation and scope a great deal since the early 1990s; it had a maximum attendance of 2,810 at the December 2000 IETF held in San Diego, California. Attendance declined with industry restructuring during the early 2000s, and is currently around 1,200.

The location for IETF meetings vary greatly. A list of past and future meeting locations can be found on the IETF meetings page. The IETF strives to hold its meetings near where most of the IETF volunteers are located. For many years, the goal was three meetings a year, with two in North America and one in either Europe or Asia, alternating between them every other year. The current goal is to hold three meetings in North America, two in Europe and one in Asia during a two-year period. However, corporate sponsorship of the meetings is also an important factor and the schedule has been modified from time to time in order to decrease operational costs.

The IETF also organizes hackathons during the IETF meetings. The focus is on implementing code that will improve standards in terms of quality and interoperability.

Operations
The details of IETF operations have changed considerably as the organization has grown, but the basic mechanism remains publication of proposed specifications, development based on the proposals, review and independent testing by participants, and republication as a revised proposal, a draft proposal, or eventually as an Internet Standard. IETF standards are developed in an open, all-inclusive process in which any interested individual can participate. All IETF documents are freely available over the Internet and can be reproduced at will. Multiple, working, useful, interoperable implementations are the chief requirement before an IETF proposed specification can become a standard. Most specifications are focused on single protocols rather than tightly interlocked systems. This has allowed the protocols to be used in many different systems, and its standards are routinely re-used by bodies which create full-fledged architectures (e.g. 3GPP IMS).

Because it relies on volunteers and uses "rough consensus and running code" as its touchstone, results can be slow whenever the number of volunteers is either too small to make progress, or so large as to make consensus difficult, or when volunteers lack the necessary expertise. For protocols like SMTP, which is used to transport e-mail for a user community in the many hundreds of millions, there is also considerable resistance to any change that is not fully backward compatible, except for IPv6. Work within the IETF on ways to improve the speed of the standards-making process is ongoing but, because the number of volunteers with opinions on it is very great, consensus on improvements has been slow to develop.

The IETF cooperates with the W3C, ISO/IEC, ITU, and other standards bodies.

Statistics are available that show who the top contributors by RFC publication are. While the IETF only allows for participation by individuals, and not by corporations or governments, sponsorship information is available from these statistics.

Chairs
The IETF Chairperson is selected by the Nominating Committee (NomCom) process for a 2-year renewable term. Before 1993, the IETF Chair was selected by the IAB.

A list of the past and current Chairs of the IETF follows:

 * Mike Corrigan (1986)
 * Phill Gross (1986–1994)
 * Paul Mockapetris (1994–1996)
 * Fred Baker (1996–2001)
 * Harald Tveit Alvestrand (2001–2005)
 * Brian Carpenter (2005–2007)
 * Russ Housley (2007–2013)
 * Jari Arkko (2013–2017)
 * Alissa Cooper (2017–2021)
 * Lars Eggert (2021–2024)
 * Roman Danyliw (2024–)

Topics of interest
The IETF works on a broad range of networking technologies which provide foundation for the Internet's growth and evolution.

Automated network management
It aims to improve the efficiency in management of networks as they grow in size and complexity. The IETF is also standardizing protocols for autonomic networking that enables networks to be self managing.

Internet of things
It is a network of physical objects or things that are embedded with electronics, sensors, software and also enables objects to exchange data with operator, manufacturer and other connected devices. Several IETF working groups are developing protocols that are directly relevant to IoT.

New transport technology
Its development provides the ability of internet applications to send data over the Internet. There are some well-established transport protocols such as TCP (Transmission Control Protocol) and UDP (User Datagram Protocol) which are continuously getting extended and refined to meet the needs of the global Internet.

IETF areas
It divides its work into a number of areas that have Working groups that have a relation to an area's focus. Area Directors handle the primary task of area management. Area Directors may be advised by one or more Directorates. The area structure is defined by the Internet Engineering Steering Group. The Nominations Committee can be used to add new members.

Token Binding Protocol
In October 2018, Microsoft and Google engineers introduced a plan to create the Token Binding Protocol in order to stop replay attacks on OAuth tokens.

title: Internet Engineering Task Force


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ISM radio band

The ISM radio bands are portions of the radio spectrum reserved internationally for industrial, scientific, and medical (ISM) purposes, excluding applications in telecommunications. Examples of applications for the use of radio frequency (RF) energy in these bands include RF heating, microwave ovens, and medical diathermy machines. The powerful emissions of these devices can create electromagnetic interference and disrupt radio communication using the same frequency, so these devices are limited to certain bands of frequencies. In general, communications equipment operating in ISM bands must tolerate any interference generated by ISM applications, and users have no regulatory protection from ISM device operation in these bands.

Despite the intent of the original allocations, in recent years the fastest-growing use of these bands has been for short-range, low-power wireless communications systems, since these bands are often approved for such devices, which can be used without a government license, as would otherwise be required for transmitters; ISM frequencies are often chosen for this purpose as they already must tolerate interference issues. Cordless phones, Bluetooth devices, near-field communication (NFC) devices, garage door openers, baby monitors, and wireless computer networks (Wi-Fi) may all use the ISM frequencies, although these low-power transmitters are not considered to be ISM devices.

Definition
The ISM bands are defined by the ITU Radio Regulations (article 5) in footnotes 5.138, 5.150, and 5.280 of the Radio Regulations. Individual countries' use of the bands designated in these sections may differ due to variations in national radio regulations. Because communication devices using the ISM bands must tolerate any interference from ISM equipment, unlicensed operations are typically permitted to use these bands, since unlicensed operation typically needs to be tolerant of interference from other devices anyway. The ISM bands share allocations with unlicensed and licensed operations; however, due to the high likelihood of harmful interference, licensed use of the bands is typically low. In the United States, uses of the ISM bands are governed by Part 18 of the Federal Communications Commission (FCC) rules, while Part 15 contains the rules for unlicensed communication devices, even those that share ISM frequencies. In Europe, the ETSI develops standards for the use of short-range devices, some of which operate in ISM bands. The use of the ISM bands is regulated by the national spectrum regulation authorities that are members of the CEPT.

Frequency allocations
The allocation of radio frequencies is provided according to Article 5 of the ITU Radio Regulations (edition 2012).

In order to improve harmonisation in spectrum utilisation, the majority of service allocations stipulated in this document were incorporated in national tables of frequency allocations and utilisations which are within the responsibilities of the appropriate national administrations. The allocation might be primary, secondary, exclusive, or shared. Exclusive or shared utilization is within the responsibility of administrations.

 * ITU frequency allocations :

Type A (footnote 5.138) = frequency bands are designated for ISM applications. The use of these frequency bands for ISM applications shall be subject to special authorization by the administration concerned, in agreement with other administrations whose radiocommunication services might be affected. In applying this provision, administrations shall have due regard to the latest relevant ITU-R Recommendations.

Type B (footnote 5.150) = frequency bands are also designated for ISM applications. Radiocommunication services operating within these bands must accept harmful interference which may be caused by these applications.

ITU RR, (Footnote 5.280) = In Germany, Austria, Bosnia and Herzegovina, Croatia, North Macedonia, Liechtenstein, Montenegro, Portugal, Serbia, Slovenia and Switzerland, the band 433.05–434.79 MHz (center frequency 433.92 MHz) is designated for ISM applications. Radio communication services of these countries operating within this band must accept harmful interference which may be caused by these applications.

History
The ISM bands were first established at the International Telecommunications Conference of the ITU in Atlantic City, 1947. The American delegation specifically proposed several bands, including the now commonplace 2.4 GHz band, to accommodate the then nascent process of microwave heating; however, FCC annual reports of that time suggest that much preparation was done ahead of these presentations.

The report of the August 9th 1947 meeting of the Allocation of Frequencies committee includes the remark:

"The delegate of the United States, referring to his request that the frequency 2450 Mc/s be allocated for I.S.M., indicated that there was in existence in the United States, and working on this frequency a diathermy machine and an electronic cooker, and that the latter might eventually be installed in transatlantic ships and airplanes. There was therefore some point in attempting to reach world agreement on this subject."

Radio frequencies in the ISM bands have been used for communication purposes, although such devices may experience interference from non-communication sources. In the United States, as early as 1958 Class D Citizens Band, a Part 95 service, was allocated to frequencies that are also allocated to ISM. [1]

In the U.S., the FCC first made unlicensed spread spectrum available in the ISM bands in rules adopted on May 9, 1985. The FCC action was proposed by Michael Marcus of the FCC staff in 1980 and the subsequent regulatory action took five more years. It was part of a broader proposal to allow civil use of spread spectrum technology and was opposed at the time by mainstream equipment manufacturers and many radio system operators.

Many other countries later developed similar regulations, enabling use of this technology.

Applications
 Industrial, scientific and medical (ISM) applications (of radio frequency energy) (short: ISM applications) are – according to article 1.15 of the International Telecommunication Union's (ITU) ITU Radio Regulations (RR) – defined as «Operation of equipment or appliances designed to generate and use locally radio frequency energy for industrial, scientific, medical, domestic or similar purposes, excluding applications in the field of telecommunications.»

The original ISM specifications envisioned that the bands would be used primarily for noncommunication purposes, such as heating. The bands are still widely used for these purposes. For many people, the most commonly encountered ISM device is the home microwave oven operating at 2.45 GHz which uses microwaves to cook food. Industrial heating is another big application area; such as induction heating, microwave heat treating, plastic softening, and plastic welding processes. In medical settings, shortwave and microwave diathermy machines use radio waves in the ISM bands to apply deep heating to the body for relaxation and healing. More recently hyperthermia therapy uses microwaves to heat tissue to kill cancer cells.

However, as detailed below, the increasing congestion of the radio spectrum, the increasing sophistication of microelectronics, and the attraction of unlicensed use, has in recent decades led to an explosion of uses of these bands for short range communication systems for wireless devices, which are now by far the largest uses of these bands. These are sometimes called "non ISM" uses since they do not fall under the originally envisioned "industrial", "scientific", and "medical" application areas. One of the largest applications has been wireless networking (Wi-Fi). The IEEE 802.11 wireless networking protocols, the standards on which almost all wireless systems are based, use the ISM bands. Virtually all laptops, tablet computers, computer printers and cellphones now have 802.11 wireless modems using the 2.4 and 5.7 GHz ISM bands. Bluetooth is another networking technology using the 2.4 GHz band, which can be problematic given the probability of interference. Near-field communication (NFC) devices such as proximity cards and contactless smart cards use the lower-frequency 13 and 27 MHz ISM bands. Other short-range devices using the ISM bands are: wireless microphones, baby monitors, garage door openers, wireless doorbells, keyless entry systems for vehicles, radio control channels for UAVs (drones), wireless surveillance systems, RFID systems for merchandise, and wild animal tracking systems.

Some electrodeless lamp designs are ISM devices, which use RF emissions to excite fluorescent tubes. Sulfur lamps are commercially available plasma lamps, which use 2.45 GHz magnetrons to heat sulfur into a brightly glowing plasma.

Long-distance wireless power systems have been proposed and experimented with which would use high-power transmitters and rectennas, in lieu of overhead transmission lines and underground cables, to send power to remote locations. NASA has studied using microwave power transmission on 2.45 GHz to send energy collected by solar power satellites back to the ground.

Also in space applications, a helicon double-layer ion thruster is a prototype spacecraft propulsion engine which uses a 13.56 MHz transmission to break down and heat gas into plasma.

Common non-ISM uses
In recent years ISM bands have also been shared with (non-ISM) license-free error-tolerant communications applications such as wireless sensor networks in the 915 MHz and 2.450 GHz bands, as well as wireless LANs and cordless phones in the 915 MHz, 2.450 GHz, and 5.800 GHz bands. Because unlicensed devices are required to be tolerant of ISM emissions in these bands, unlicensed low-power users are generally able to operate in these bands without causing problems for ISM users. ISM equipment does not necessarily include a radio receiver in the ISM band (e.g. a microwave oven does not have a receiver).

In the United States, according to 47 CFR Part 15.5, low power communication devices must accept interference from licensed users of that frequency band, and the Part 15 device must not cause interference to licensed users. Note that the 915 MHz band should not be used in countries outside Region 2, except those that specifically allow it, such as Australia and Israel, especially those that use the GSM-900 band for cellphones. The ISM bands are also widely used for radio-frequency identification (RFID) applications with the most commonly used band being the 13.56 MHz band used by systems compliant with ISO/IEC 14443 including those used by biometric passports and contactless smart cards.

In Europe, the use of the ISM band is covered by Short Range Device regulations issued by European Commission, based on technical recommendations by CEPT and standards by ETSI. In most of Europe, LPD433 band is allowed for license-free voice communication in addition to PMR446.

Wireless network devices use wavebands as follows:
 * IEEE 802.11/Wi-Fi 2450 MHz and 5800 MHz bands
 * Bluetooth 2450 MHz band falls under WPAN
 * ANT / ANT+ (originates from Adaptive Network Topology) is a proprietary (but open access) multicast wireless sensor network technology designed and marketed by ANT Wireless. ANT devices may use any RF frequency from 2400MHz to 2524MHz, with the exception of 2457MHz, which is reserved for ANT+ devices.
 * IEEE 802.15.4Zigbee and other personal area networks may use the 915 MHz and 2450 MHz ISM bands because of frequency sharing between different allocations.

Wireless LANs and cordless phones can also use bands other than those shared with ISM, but such uses require approval on a country by country basis. DECT phones use allocated spectrum outside the ISM bands that differs in Europe and North America. Ultra-wideband LANs require more spectrum than the ISM bands can provide, so the relevant standards such as IEEE 802.15.4a are designed to make use of spectrum outside the ISM bands. Despite the fact that these additional bands are outside the official ITU-R ISM bands, because they are used for the same types of low power personal communications, they are sometimes incorrectly referred to as ISM bands as well.

Several brands of radio control equipment use the 2.4 GHz band range for low power remote control of toys, from gas powered cars to miniature aircraft.

Worldwide Digital Cordless Telecommunications or WDCT is a technology that uses the 2.4 GHz radio spectrum.

Google's Project Loon used ISM bands (specifically 2.4 and 5.8 GHz bands) for balloon-to-balloon and balloon-to-ground communications.

Pursuant to 47 CFR Part 97 some ISM bands are used by licensed amateur radio operators for communicationincluding amateur television.

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: ISM radio band


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Series (mathematics)

In mathematics, a series is, roughly speaking, the operation of adding infinitely many quantities, one after the other, to a given starting quantity. The study of series is a major part of calculus and its generalization, mathematical analysis. Series are used in most areas of mathematics, even for studying finite structures (such as in combinatorics) through generating functions. In addition to their ubiquity in mathematics, infinite series are also widely used in other quantitative disciplines such as physics, computer science, statistics and finance.

For a long time, the idea that such a potentially infinite summation could produce a finite result was considered paradoxical. This paradox was resolved using the concept of a limit during the 17th century. Zeno's paradox of Achilles and the tortoise illustrates this counterintuitive property of infinite sums: Achilles runs after a tortoise, but when he reaches the position of the tortoise at the beginning of the race, the tortoise has reached a second position; when he reaches this second position, the tortoise is at a third position, and so on. Zeno concluded that Achilles could never reach the tortoise, and thus that movement does not exist. Zeno divided the race into infinitely many sub-races, each requiring a finite amount of time, so that the total time for Achilles to catch the tortoise is given by a series. The resolution of the paradox is that, although the series has an infinite number of terms, it has a finite sum, which gives the time necessary for Achilles to catch up with the tortoise.

In modern terminology, any (ordered) infinite sequence $$(a_1,a_2,a_3,\ldots)$$ of terms (that is, numbers, functions, or anything that can be added) defines a series, which is the operation of adding the $a_{i}$ one after the other. To emphasize that there are an infinite number of terms, a series may be called an infinite series. Such a series is represented (or denoted) by an expression like

$$a_1+a_2+a_3+\cdots,$$

or, using the summation sign,

$$\sum_{i=1}^\infty a_i.$$

The infinite sequence of additions implied by a series cannot be effectively carried on (at least in a finite amount of time). However, if the set to which the terms and their finite sums belong has a notion of limit, it is sometimes possible to assign a value to a series, called the sum of the series. This value is the limit as $n$ tends to infinity (if the limit exists) of the finite sums of the $n$ first terms of the series, which are called the $n$th partial sums of the series. That is,

$$\sum_{i=1}^\infty a_i = \lim_{n\to\infty} \sum_{i=1}^n a_i.$$

When this limit exists, one says that the series is convergent or summable, or that the sequence $$(a_1,a_2,a_3,\ldots)$$ is summable. In this case, the limit is called the sum of the series. Otherwise, the series is said to be divergent.

The notation $\sum_{i=1}^\infty a_i$ denotes both the series—that is the implicit process of adding the terms one after the other indefinitely—and, if the series is convergent, the sum of the series—the result of the process. This is a generalization of the similar convention of denoting by $$a+b$$ both the addition—the process of adding—and its result—the sum of $a$ and $b$.

Commonly, the terms of a series come from a ring, often the field $$\mathbb R$$ of the real numbers or the field $$\mathbb C$$ of the complex numbers. In this case, the set of all series is itself a ring (and even an associative algebra), in which the addition consists of adding the series term by term, and the multiplication is the Cauchy product.

Basic properties
An infinite series or simply a series is an infinite sum, represented by an infinite expression of the form

$$a_0 + a_1 + a_2 + \cdots, $$

where $$(a_n)$$ is any ordered sequence of terms, such as numbers, functions, or anything else that can be added (an abelian group). This is an expression that is obtained from the list of terms $$a_0,a_1,\dots$$ by laying them side by side, and conjoining them with the symbol "+". A series may also be represented by using summation notation, such as

$$\sum_{n=0}^{\infty} a_n. $$

If an abelian group $A$ of terms has a concept of limit (e.g., if it is a metric space), then some series, the convergent series, can be interpreted as having a value in $A$, called the sum of the series. This includes the common cases from calculus, in which the group is the field of real numbers or the field of complex numbers. Given a series $s=\sum_{n=0}^\infty a_n$, its $k$th partial sum is

$$s_k = \sum_{n=0}^{k}a_n = a_0 + a_1 + \cdots + a_k.$$

By definition, the series $\sum_{n=0}^{\infty} a_n$ converges to the limit $L$ (or simply sums to $L$), if the sequence of its partial sums has a limit $L$. In this case, one usually writes

$$L = \sum_{n=0}^{\infty}a_n.$$

A series is said to be convergent if it converges to some limit, or divergent when it does not. The value of this limit, if it exists, is then the value of the series.

Convergent series
A series $Σa_{n}$ is said to converge or to be convergent when the sequence $(s_{k})$ of partial sums has a finite limit. If the limit of $s_{k}$ is infinite or does not exist, the series is said to diverge. When the limit of partial sums exists, it is called the value (or sum) of the series

$$\sum_{n=0}^\infty a_n = \lim_{k\to\infty} s_k = \lim_{k\to\infty} \sum_{n=0}^k a_n.$$

An easy way that an infinite series can converge is if all the $a_{n}$ are zero for $n$ sufficiently large. Such a series can be identified with a finite sum, so it is only infinite in a trivial sense.

Working out the properties of the series that converge, even if infinitely many terms are nonzero, is the essence of the study of series. Consider the example

$$ 1 + \frac{1}{2}+ \frac{1}{4}+ \frac{1}{8}+\cdots+ \frac{1}{2^n}+\cdots.$$

It is possible to "visualize" its convergence on the real number line: we can imagine a line of length 2, with successive segments marked off of lengths 1, 1/2, 1/4, etc. There is always room to mark the next segment, because the amount of line remaining is always the same as the last segment marked: When we have marked off 1/2, we still have a piece of length 1/2 unmarked, so we can certainly mark the next 1/4. This argument does not prove that the sum is equal to 2 (although it is), but it does prove that it is at most 2. In other words, the series has an upper bound. Given that the series converges, proving that it is equal to 2 requires only elementary algebra. If the series is denoted $S$, it can be seen that

$$S/2 = \frac{1+ \frac{1}{2}+ \frac{1}{4}+ \frac{1}{8}+\cdots}{2} = \frac{1}{2}+ \frac{1}{4}+ \frac{1}{8}+ \frac{1}{16} +\cdots.$$

Therefore,

$$S-S/2 = 1 \Rightarrow S = 2.$$

The idiom can be extended to other, equivalent notions of series. For instance, a recurring decimal, as in

$$x = 0.111\dots, $$

encodes the series

$$\sum_{n=1}^\infty \frac{1}{10^n}.$$

Since these series always converge to real numbers (because of what is called the completeness property of the real numbers), to talk about the series in this way is the same as to talk about the numbers for which they stand. In particular, the decimal expansion 0.111... can be identified with 1/9. This leads to an argument that 9 × 0.111... = 0.999... = 1, which only relies on the fact that the limit laws for series preserve the arithmetic operations; for more detail on this argument, see 0.999....

Examples of numerical series

 * A geometric series is one where each successive term is produced by multiplying the previous term by a constant number (called the common ratio in this context). For example: $$1 + {1 \over 2} + {1 \over 4} + {1 \over 8} + {1 \over 16} + \cdots=\sum_{n=0}^\infty{1 \over 2^n} = 2.$$

In general, the geometric series

$$\sum_{n=0}^\infty z^n$$

converges if and only if $|z| < 1$, in which case it converges to $ {1 \over 1 - z}$.

 * The harmonic series is the series $$1 + {1 \over 2} + {1 \over 3} + {1 \over 4} + {1 \over 5} + \cdots = \sum_{n=1}^\infty {1 \over n}.$$

The harmonic series is divergent.

 * An alternating series is a series where terms alternate signs. Examples: $$1 - {1 \over 2} + {1 \over 3} - {1 \over 4} + {1 \over 5} - \cdots =\sum_{n=1}^\infty {\left(-1\right)^{n-1} \over n}=\ln(2) \quad $$

(alternating harmonic series) and

$$-1+\frac{1}{3} - \frac{1}{5} + \frac{1}{7} - \frac{1}{9} + \cdots =\sum_{n=1}^\infty \frac{\left(-1\right)^n}{2n-1} = -\frac{\pi}{4}$$
 * A telescoping series $$\sum_{n=1}^\infty (b_n-b_{n+1})$$

converges if the sequence bn converges to a limit L—as n goes to infinity. The value of the series is then b1 − L.

 * An arithmetico-geometric series is a generalization of the geometric series, which has coefficients of the common ratio equal to the terms in an arithmetic sequence. Example: $$3 + {5 \over 2} + {7 \over 4} + {9 \over 8} + {11 \over 16} + \cdots=\sum_{n=0}^\infty{(3+2n) \over 2^n}.$$
 * The p-series $$\sum_{n=1}^\infty\frac{1}{n^p}$$

converges for p > 1 and diverges for p ≤ 1, which can be shown with the integral criterion described below in convergence tests. As a function of p, the sum of this series is Riemann's zeta function.

 * Hypergeometric series: $$_rF_s \left[ \begin{matrix}a_1, a_2, \dotsc, a_r \\ b_1, b_2, \dotsc, b_s \end{matrix}; z \right] := \sum_{n=0}^{\infty} \frac{(a_1)_n (a_2)_n \dotsb (a_r)_n}{(b_1)_n (b_2)_n \dotsb (b_s)_n \; n!} z^n$$

and their generalizations (such as basic hypergeometric series and elliptic hypergeometric series) frequently appear in integrable systems and mathematical physics.

 * There are some elementary series whose convergence is not yet known/proven. For example, it is unknown whether the Flint Hills series $$\sum_{n=1}^\infty \frac{1}{n^{3}\sin^{2} n}$$  converges or not. The convergence depends on how well $$\pi$$ can be approximated with rational numbers (which is unknown as of yet). More specifically, the values of n with large numerical contributions to the sum are the numerators of the continued fraction convergents of $$\pi$$, a sequence beginning with 1, 3, 22, 333, 355, 103993, ... . These are integers n that are close to $$m\pi$$ for some integer m, so that $$\sin n$$ is close to $$\sin m\pi = 0$$ and its reciprocal is large.

Pi
$$ \sum_{i=1}^{\infty} \frac{1}{i^2} = \frac{1}{1^2} + \frac{1}{2^2} + \frac{1}{3^2} + \frac{1}{4^2} + \cdots = \frac{\pi^2}{6}$$

$$ \sum_{i=1}^\infty \frac{(-1)^{i+1}(4)}{2i-1} = \frac{4}{1} - \frac{4}{3} + \frac{4}{5} - \frac{4}{7} + \frac{4}{9} - \frac{4}{11} + \frac{4}{13} - \cdots = \pi$$

Natural logarithm of 2
$$\sum_{i=1}^\infty \frac{(-1)^{i+1}}{i} = \ln 2$$

$$\sum_{i=0}^\infty \frac{1}{(2i+1)(2i+2)} = \ln 2$$

$$\sum_{i=0}^\infty \frac{(-1)^i}{(i+1)(i+2)} = 2\ln(2) -1$$

$$\sum_{i=1}^\infty \frac{1}{i \left(4i^2-1\right)} = 2\ln(2) -1$$

$$ \sum_{i=1}^\infty \frac{1}{2^{i}i} = \ln 2$$

$$ \sum_{i=1}^\infty \left(\frac{1}{3^i}+\frac{1}{4^i}\right)\frac{1}{i} = \ln 2$$

$$ \sum_{i=1}^\infty \frac{1}{2i(2i-1)} = \ln 2$$

Natural logarithm base e
$$\sum_{i = 0}^\infty \frac{(-1)^i}{i!} = 1-\frac{1}{1!}+\frac{1}{2!}-\frac{1}{3!}+\cdots = \frac{1}{e}$$

$$ \sum_{i = 0}^\infty \frac{1}{i!} = \frac{1}{0!} + \frac{1}{1!} + \frac{1}{2!} + \frac{1}{3!} + \frac{1}{4!} + \cdots = e $$

Calculus and partial summation as an operation on sequences
Partial summation takes as input a sequence, (an), and gives as output another sequence, (SN). It is thus a unary operation on sequences. Further, this function is linear, and thus is a linear operator on the vector space of sequences, denoted Σ. The inverse operator is the finite difference operator, denoted Δ. These behave as discrete analogues of integration and differentiation, only for series (functions of a natural number) instead of functions of a real variable. For example, the sequence (1, 1, 1, ...) has series (1, 2, 3, 4, ...) as its partial summation, which is analogous to the fact that $\int_0^x 1\,dt = x.$

In computer science, it is known as prefix sum.

Properties of series
Series are classified not only by whether they converge or diverge, but also by the properties of the terms an (absolute or conditional convergence); type of convergence of the series (pointwise, uniform); the class of the term an (whether it is a real number, arithmetic progression, trigonometric function); etc.

Non-negative terms
When an is a non-negative real number for every n, the sequence SN of partial sums is non-decreasing. It follows that a series Σan with non-negative terms converges if and only if the sequence SN of partial sums is bounded.

For example, the series

$$\sum_{n = 1}^\infty \frac{1}{n^2}$$

is convergent, because the inequality

$$\frac1 {n^2} \le \frac{1}{n-1} - \frac{1}{n}, \quad n \ge 2,$$

and a telescopic sum argument implies that the partial sums are bounded by 2. The exact value of the original series is the Basel problem.

Grouping
When you group a series reordering of the series does not happen, so Riemann series theorem does not apply. A new series will have its partial sums as subsequence of original series, which means if the original series converges, so does the new series. But for divergent series that is not true, for example 1-1+1-1+... grouped every two elements will create 0+0+0+... series, which is convergent. On the other hand, divergence of the new series means the original series can be only divergent which is sometimes useful, like in Oresme proof.

Absolute convergence
A series

$$\sum_{n=0}^\infty a_n$$

converges absolutely if the series of absolute values

$$\sum_{n=0}^\infty \left|a_n\right|$$

converges. This is sufficient to guarantee not only that the original series converges to a limit, but also that any reordering of it converges to the same limit.

Conditional convergence
A series of real or complex numbers is said to be conditionally convergent (or semi-convergent) if it is convergent but not absolutely convergent. A famous example is the alternating series

$$\sum\limits_{n=1}^\infty {(-1)^{n+1} \over n} = 1 - {1 \over 2} + {1 \over 3} - {1 \over 4} + {1 \over 5} - \cdots,$$

which is convergent (and its sum is equal to $$\ln 2$$), but the series formed by taking the absolute value of each term is the divergent harmonic series. The Riemann series theorem says that any conditionally convergent series can be reordered to make a divergent series, and moreover, if the $$a_{n}$$ are real and $$S$$ is any real number, that one can find a reordering so that the reordered series converges with sum equal to $$S$$.

Abel's test is an important tool for handling semi-convergent series. If a series has the form

$$\sum a_n = \sum \lambda_n b_n$$

where the partial sums $$B_{n} = b_{0} + \cdots + b_{n}$$ are bounded, $$\lambda_{n}$$ has bounded variation, and $$\lim \lambda_{n} b_{n}$$ exists:

$$\sup_N \left| \sum_{n=0}^N b_n \right| < \infty, \ \ \sum \left|\lambda_{n+1} - \lambda_n\right| < \infty\ \text{and} \ \lambda_n B_n \ \text{converges,}$$

then the series $\sum a_{n}$ is convergent. This applies to the point-wise convergence of many trigonometric series, as in

$$\sum_{n=2}^\infty \frac{\sin(n x)}{\ln n}$$

with $$0 < x < 2\pi$$. Abel's method consists in writing $$b_{n+1}=B_{n+1}-B_{n}$$, and in performing a transformation similar to integration by parts (called summation by parts), that relates the given series $\sum a_{n}$ to the absolutely convergent series

$$ \sum (\lambda_n - \lambda_{n+1}) \, B_n.$$

Evaluation of truncation errors
The evaluation of truncation errors is an important procedure in numerical analysis (especially validated numerics and computer-assisted proof).

Alternating series
When conditions of the alternating series test are satisfied by $S:=\sum_{m=0}^\infty(-1)^m u_m$, there is an exact error evaluation. Set $$s_n$$ to be the partial sum $s_n:=\sum_{m=0}^n(-1)^m u_m$ of the given alternating series $$S$$. Then the next inequality holds: $$|S-s_n|\leq u_{n+1}.$$

Taylor series
Taylor's theorem is a statement that includes the evaluation of the error term when the Taylor series is truncated.

Hypergeometric series
By using the ratio, we can obtain the evaluation of the error term when the hypergeometric series is truncated.

Matrix exponential
For the matrix exponential:

$$\exp(X) := \sum_{k=0}^\infty\frac{1}{k!}X^k,\quad X\in\mathbb{C}^{n\times n},$$

the following error evaluation holds (scaling and squaring method):

$$T_{r,s}(X) := \left[\sum_{j=0}^r\frac{1}{j!}(X/s)^j\right]^s,\quad \|\exp(X)-T_{r,s}(X)\|\leq\frac{\|X\|^{r+1}}{s^r(r+1)!}\exp(\|X\|).$$

Convergence tests
There exist many tests that can be used to determine whether particular series converge or diverge.
 * n-th term test: If $\lim_{n \to \infty} a_n \neq 0$, then the series diverges; if $\lim_{n \to \infty} a_n = 0$ , then the test is inconclusive.
 * Comparison test 1 (see Direct comparison test): If $\sum b_n$ is an absolutely convergent series such that $$\left\vert a_n \right\vert \leq C \left\vert b_n \right\vert$$ for some number $$C$$ and for sufficiently large $$n$$, then $\sum a_n$  converges absolutely as well. If $\sum \left\vert b_n \right\vert$  diverges, and $$\left\vert a_n \right\vert \geq \left\vert b_n \right\vert$$  for all sufficiently large $$n$$, then $\sum a_n$  also fails to converge absolutely (though it could still be conditionally convergent, for example, if the $$a_n$$ alternate in sign).
 * Comparison test 2 (see Limit comparison test): If $\sum b_n$ is an absolutely convergent series such that $$\left\vert \frac{a_{n+1}}{a_{n}} \right\vert \leq \left\vert \frac{b_{n+1}}{b_{n}} \right\vert$$ for sufficiently large $$n$$, then $\sum a_n$  converges absolutely as well. If $\sum \left| b_n \right|$  diverges, and $$\left\vert \frac{a_{n+1}}{a_{n}} \right\vert \geq \left\vert \frac{b_{n+1}}{b_{n}} \right\vert$$ for all sufficiently large $$n$$, then $\sum a_n$  also fails to converge absolutely (though it could still be conditionally convergent, for example, if the $$a_n$$ alternate in sign).
 * Ratio test: If there exists a constant $$C < 1$$ such that $$\left\vert \frac{a_{n+1}}{a_{n}} \right\vert < C$$ for all sufficiently large $$n$$, then $\sum a_{n}$ converges absolutely. When the ratio is less than $$1$$, but not less than a constant less than $$1$$, convergence is possible but this test does not establish it.
 * Root test: If there exists a constant $$C < 1$$ such that $$\left\vert a_{n} \right\vert^{\frac{1}{n}} \leq C$$ for all sufficiently large $$n$$, then $\sum a_{n}$ converges absolutely.
 * Integral test: if $$f(x)$$ is a positive monotone decreasing function defined on the interval $$[1,\infty)$$ with $$f(n)=a_{n}$$ for all $$n$$, then $\sum a_{n}$  converges if and only if the integral $\int_{1}^{\infty} f(x) \, dx$  is finite.
 * Cauchy's condensation test: If $$a_{n}$$ is non-negative and non-increasing, then the two series $\sum a_{n}$ and $\sum 2^{k} a_{(2^{k})}$  are of the same nature: both convergent, or both divergent.
 * Alternating series test: A series of the form $\sum (-1)^{n} a_{n}$ (with $$a_{n} > 0$$) is called alternating. Such a series converges if the sequence $$a_{n}$$ is monotone decreasing and converges to $$0$$. The converse is in general not true.
 * For some specific types of series there are more specialized convergence tests, for instance for Fourier series there is the Dini test.

Series of functions
A series of real- or complex-valued functions

$$\sum_{n=0}^\infty f_n(x)$$

converges pointwise on a set E, if the series converges for each x in E as an ordinary series of real or complex numbers. Equivalently, the partial sums

$$s_N(x) = \sum_{n=0}^N f_n(x)$$

converge to ƒ(x) as N → ∞ for each x ∈ E.

A stronger notion of convergence of a series of functions is the uniform convergence. A series converges uniformly if it converges pointwise to the function ƒ(x), and the error in approximating the limit by the Nth partial sum,

$$|s_N(x) - f(x)|$$

can be made minimal independently of x by choosing a sufficiently large N.

Uniform convergence is desirable for a series because many properties of the terms of the series are then retained by the limit. For example, if a series of continuous functions converges uniformly, then the limit function is also continuous. Similarly, if the ƒn are integrable on a closed and bounded interval I and converge uniformly, then the series is also integrable on I and can be integrated term-by-term. Tests for uniform convergence include the Weierstrass' M-test, Abel's uniform convergence test, Dini's test, and the Cauchy criterion.

More sophisticated types of convergence of a series of functions can also be defined. In measure theory, for instance, a series of functions converges almost everywhere if it converges pointwise except on a certain set of measure zero. Other modes of convergence depend on a different metric space structure on the space of functions under consideration. For instance, a series of functions converges in mean on a set E to a limit function ƒ provided

$$\int_E \left|s_N(x)-f(x)\right|^2\,dx \to 0$$

as N → ∞.

Power series

A power series is a series of the form

$$\sum_{n=0}^\infty a_n(x-c)^n.$$

The Taylor series at a point c of a function is a power series that, in many cases, converges to the function in a neighborhood of c. For example, the series

$$\sum_{n=0}^{\infty} \frac{x^n}{n!}$$

is the Taylor series of $$e^x$$ at the origin and converges to it for every x.

Unless it converges only at x=c, such a series converges on a certain open disc of convergence centered at the point c in the complex plane, and may also converge at some of the points of the boundary of the disc. The radius of this disc is known as the radius of convergence, and can in principle be determined from the asymptotics of the coefficients an. The convergence is uniform on closed and bounded (that is, compact) subsets of the interior of the disc of convergence: to wit, it is uniformly convergent on compact sets.

Historically, mathematicians such as Leonhard Euler operated liberally with infinite series, even if they were not convergent. When calculus was put on a sound and correct foundation in the nineteenth century, rigorous proofs of the convergence of series were always required.

Formal power series
While many uses of power series refer to their sums, it is also possible to treat power series as formal sums, meaning that no addition operations are actually performed, and the symbol "+" is an abstract symbol of conjunction which is not necessarily interpreted as corresponding to addition. In this setting, the sequence of coefficients itself is of interest, rather than the convergence of the series. Formal power series are used in combinatorics to describe and study sequences that are otherwise difficult to handle, for example, using the method of generating functions. The Hilbert–Poincaré series is a formal power series used to study graded algebras.

Even if the limit of the power series is not considered, if the terms support appropriate structure then it is possible to define operations such as addition, multiplication, derivative, antiderivative for power series "formally", treating the symbol "+" as if it corresponded to addition. In the most common setting, the terms come from a commutative ring, so that the formal power series can be added term-by-term and multiplied via the Cauchy product. In this case the algebra of formal power series is the total algebra of the monoid of natural numbers over the underlying term ring. If the underlying term ring is a differential algebra, then the algebra of formal power series is also a differential algebra, with differentiation performed term-by-term.

Laurent series
Laurent series generalize power series by admitting terms into the series with negative as well as positive exponents. A Laurent series is thus any series of the form

$$\sum_{n=-\infty}^\infty a_n x^n.$$

If such a series converges, then in general it does so in an annulus rather than a disc, and possibly some boundary points. The series converges uniformly on compact subsets of the interior of the annulus of convergence.

Dirichlet series

A Dirichlet series is one of the form

$$\sum_{n=1}^\infty {a_n \over n^s},$$

where s is a complex number. For example, if all an are equal to 1, then the Dirichlet series is the Riemann zeta function

$$\zeta(s) = \sum_{n=1}^\infty \frac{1}{n^s}.$$

Like the zeta function, Dirichlet series in general play an important role in analytic number theory. Generally a Dirichlet series converges if the real part of s is greater than a number called the abscissa of convergence. In many cases, a Dirichlet series can be extended to an analytic function outside the domain of convergence by analytic continuation. For example, the Dirichlet series for the zeta function converges absolutely when Re(s) > 1, but the zeta function can be extended to a holomorphic function defined on $$\Complex\setminus\{1\}$$ with a simple pole at 1.

This series can be directly generalized to general Dirichlet series.

Trigonometric series
A series of functions in which the terms are trigonometric functions is called a trigonometric series:

$$\frac12 A_0 + \sum_{n=1}^\infty \left(A_n\cos nx + B_n \sin nx\right).$$

The most important example of a trigonometric series is the Fourier series of a function.

Development of infinite series
Greek mathematician Archimedes produced the first known summation of an infinite series with a method that is still used in the area of calculus today. He used the method of exhaustion to calculate the area under the arc of a parabola with the summation of an infinite series, and gave a remarkably accurate approximation of π.

Mathematicians from the Kerala school were studying infinite series c. 1350 CE.

In the 17th century, James Gregory worked in the new decimal system on infinite series and published several Maclaurin series. In 1715, a general method for constructing the Taylor series for all functions for which they exist was provided by Brook Taylor. Leonhard Euler in the 18th century, developed the theory of hypergeometric series and q-series.

Convergence criteria
The investigation of the validity of infinite series is considered to begin with Gauss in the 19th century. Euler had already considered the hypergeometric series

$$1 + \frac{\alpha\beta}{1\cdot\gamma}x + \frac{\alpha(\alpha+1)\beta(\beta+1)}{1 \cdot 2 \cdot \gamma(\gamma+1)}x^2 + \cdots$$

on which Gauss published a memoir in 1812. It established simpler criteria of convergence, and the questions of remainders and the range of convergence.

Cauchy (1821) insisted on strict tests of convergence; he showed that if two series are convergent their product is not necessarily so, and with him begins the discovery of effective criteria. The terms convergence and divergence had been introduced long before by Gregory (1668). Leonhard Euler and Gauss had given various criteria, and Colin Maclaurin had anticipated some of Cauchy's discoveries. Cauchy advanced the theory of power series by his expansion of a complex function in such a form.

Abel (1826) in his memoir on the binomial series

$$1 + \frac{m}{1!}x + \frac{m(m-1)}{2!}x^2 + \cdots$$

corrected certain of Cauchy's conclusions, and gave a completely scientific summation of the series for complex values of $$m$$ and $$x$$. He showed the necessity of considering the subject of continuity in questions of convergence.

Cauchy's methods led to special rather than general criteria, and the same may be said of Raabe (1832), who made the first elaborate investigation of the subject, of De Morgan (from 1842), whose logarithmic test DuBois-Reymond (1873) and Pringsheim (1889) have shown to fail within a certain region; of Bertrand (1842), Bonnet (1843), Malmsten (1846, 1847, the latter without integration); Stokes (1847), Paucker (1852), Chebyshev (1852), and Arndt (1853).

General criteria began with Kummer (1835), and have been studied by Eisenstein (1847), Weierstrass in his various contributions to the theory of functions, Dini (1867), DuBois-Reymond (1873), and many others. Pringsheim's memoirs (1889) present the most complete general theory.

Uniform convergence
The theory of uniform convergence was treated by Cauchy (1821), his limitations being pointed out by Abel, but the first to attack it successfully were Seidel and Stokes (1847–48). Cauchy took up the problem again (1853), acknowledging Abel's criticism, and reaching the same conclusions which Stokes had already found. Thomae used the doctrine (1866), but there was great delay in recognizing the importance of distinguishing between uniform and non-uniform convergence, in spite of the demands of the theory of functions.

Semi-convergence
A series is said to be semi-convergent (or conditionally convergent) if it is convergent but not absolutely convergent.

Semi-convergent series were studied by Poisson (1823), who also gave a general form for the remainder of the Maclaurin formula. The most important solution of the problem is due, however, to Jacobi (1834), who attacked the question of the remainder from a different standpoint and reached a different formula. This expression was also worked out, and another one given, by Malmsten (1847). Schlömilch (Zeitschrift, Vol.I, p. 192, 1856) also improved Jacobi's remainder, and showed the relation between the remainder and Bernoulli's function

$$F(x) = 1^n + 2^n + \cdots + (x - 1)^n.$$

Genocchi (1852) has further contributed to the theory.

Among the early writers was Wronski, whose "loi suprême" (1815) was hardly recognized until Cayley (1873) brought it into prominence.

Fourier series
Fourier series were being investigated as the result of physical considerations at the same time that Gauss, Abel, and Cauchy were working out the theory of infinite series. Series for the expansion of sines and cosines, of multiple arcs in powers of the sine and cosine of the arc had been treated by Jacob Bernoulli (1702) and his brother Johann Bernoulli (1701) and still earlier by Vieta. Euler and Lagrange simplified the subject, as did Poinsot, Schröter, Glaisher, and Kummer.

Fourier (1807) set for himself a different problem, to expand a given function of x in terms of the sines or cosines of multiples of x, a problem which he embodied in his Théorie analytique de la chaleur (1822). Euler had already given the formulas for determining the coefficients in the series; Fourier was the first to assert and attempt to prove the general theorem. Poisson (1820–23) also attacked the problem from a different standpoint. Fourier did not, however, settle the question of convergence of his series, a matter left for Cauchy (1826) to attempt and for Dirichlet (1829) to handle in a thoroughly scientific manner (see convergence of Fourier series). Dirichlet's treatment (Crelle, 1829), of trigonometric series was the subject of criticism and improvement by Riemann (1854), Heine, Lipschitz, Schläfli, and du Bois-Reymond. Among other prominent contributors to the theory of trigonometric and Fourier series were Dini, Hermite, Halphen, Krause, Byerly and Appell.

Asymptotic series
Asymptotic series, otherwise asymptotic expansions, are infinite series whose partial sums become good approximations in the limit of some point of the domain. In general they do not converge, but they are useful as sequences of approximations, each of which provides a value close to the desired answer for a finite number of terms. The difference is that an asymptotic series cannot be made to produce an answer as exact as desired, the way that convergent series can. In fact, after a certain number of terms, a typical asymptotic series reaches its best approximation; if more terms are included, most such series will produce worse answers.

Divergent series
Under many circumstances, it is desirable to assign a limit to a series which fails to converge in the usual sense. A summability method is such an assignment of a limit to a subset of the set of divergent series which properly extends the classical notion of convergence. Summability methods include Cesàro summation, (C,k) summation, Abel summation, and Borel summation, in increasing order of generality (and hence applicable to increasingly divergent series).

A variety of general results concerning possible summability methods are known. The Silverman–Toeplitz theorem characterizes matrix summability methods, which are methods for summing a divergent series by applying an infinite matrix to the vector of coefficients. The most general method for summing a divergent series is non-constructive, and concerns Banach limits.

Summations over arbitrary index sets
Definitions may be given for sums over an arbitrary index set $$I.$$ There are two main differences with the usual notion of series: first, there is no specific order given on the set $$I$$; second, this set $$I$$ may be uncountable. The notion of convergence needs to be strengthened, because the concept of conditional convergence depends on the ordering of the index set.

If $$a : I \mapsto G$$ is a function from an index set $$I$$ to a set $$G,$$ then the "series" associated to $$a$$ is the formal sum of the elements $$a(x) \in G $$ over the index elements $$x \in I$$ denoted by the

$$\sum_{x \in I} a(x).$$

When the index set is the natural numbers $$I=\N,$$ the function $$a : \N \mapsto G$$ is a sequence denoted by $$a(n) = a_n.$$ A series indexed on the natural numbers is an ordered formal sum and so we rewrite $\sum_{n \in \N}$ as $\sum_{n=0}^{\infty}$  in order to emphasize the ordering induced by the natural numbers. Thus, we obtain the common notation for a series indexed by the natural numbers

$$\sum_{n=0}^{\infty} a_n = a_0 + a_1 + a_2 + \cdots.$$

Families of non-negative numbers
When summing a family $$\left\{a_i : i \in I\right\}$$ of non-negative real numbers, define

$$\sum_{i\in I}a_i = \sup \left\{ \sum_{i\in A} a_i\, : A \subseteq I, A \text{ finite}\right\} \in [0, +\infty].$$

When the supremum is finite then the set of $$i \in I$$ such that $$a_i > 0$$ is countable. Indeed, for every $$n \geq 1,$$ the cardinality $$\left|A_n\right|$$ of the set $$A_n = \left\{i \in I : a_i > 1/n\right\}$$ is finite because

$$\frac{1}{n} \, \left|A_n\right| = \sum_{i \in A_n} \frac{1}{n} \leq \sum_{i \in A_n} a_i \leq \sum_{i \in I} a_i < \infty.$$

If $$I$$ is countably infinite and enumerated as $$I = \left\{i_0, i_1, \ldots\right\}$$ then the above defined sum satisfies

$$\sum_{i \in I} a_i = \sum_{k=0}^{+\infty} a_{i_k},$$ provided the value $$\infty$$ is allowed for the sum of the series.

Any sum over non-negative reals can be understood as the integral of a non-negative function with respect to the counting measure, which accounts for the many similarities between the two constructions.

Abelian topological groups
Let $$a : I \to X$$ be a map, also denoted by $$\left(a_i\right)_{i \in I},$$ from some non-empty set $$I$$ into a Hausdorff abelian topological group $$X.$$ Let $$\operatorname{Finite}(I)$$ be the collection of all finite subsets of $$I,$$ with $$\operatorname{Finite}(I)$$ viewed as a directed set, ordered under inclusion $$\,\subseteq\,$$ with union as join. The family $$\left(a_i\right)_{i \in I},$$ is said to be if the following limit, which is denoted by $$\sum_{i\in I} a_i$$ and is called the  of $$\left(a_i\right)_{i \in I},$$ exists in $$X:$$

$$\sum_{i\in I} a_i := \lim_{A \in \operatorname{Finite}(I)} \ \sum_{i\in A} a_i = \lim \left\{\sum_{i\in A} a_i \,: A \subseteq I, A \text{ finite }\right\}$$ Saying that the sum $$S := \sum_{i\in I} a_i$$ is the limit of finite partial sums means that for every neighborhood $$V$$ of the origin in $$X,$$ there exists a finite subset $$A_0$$ of $$I$$ such that

$$S - \sum_{i \in A} a_i \in V \qquad \text{ for every finite superset} \; A \supseteq A_0.$$

Because $$\operatorname{Finite}(I)$$ is not totally ordered, this is not a limit of a sequence of partial sums, but rather of a net.

For every neighborhood $$W$$ of the origin in $$X,$$ there is a smaller neighborhood $$V$$ such that $$V - V \subseteq W.$$ It follows that the finite partial sums of an unconditionally summable family $$\left(a_i\right)_{i \in I},$$ form a, that is, for every neighborhood $$W$$ of the origin in $$X,$$ there exists a finite subset $$A_0$$ of $$I$$ such that

$$\sum_{i \in A_1} a_i - \sum_{i \in A_2} a_i \in W \qquad \text{ for all finite supersets } \; A_1, A_2 \supseteq A_0,$$ which implies that $$a_i \in W$$ for every $$i \in I \setminus A_0$$ (by taking $$A_1 := A_0 \cup \{i\}$$ and $$A_2 := A_0$$).

When $$X$$ is complete, a family $$\left(a_i\right)_{i \in I}$$ is unconditionally summable in $$X$$ if and only if the finite sums satisfy the latter Cauchy net condition. When $$X$$ is complete and $$\left(a_i\right)_{i \in I},$$ is unconditionally summable in $$X,$$ then for every subset $$J \subseteq I,$$ the corresponding subfamily $$\left(a_j\right)_{j \in J},$$ is also unconditionally summable in $$X.$$

When the sum of a family of non-negative numbers, in the extended sense defined before, is finite, then it coincides with the sum in the topological group $$X = \R.$$

If a family $$\left(a_i\right)_{i \in I}$$ in $$X$$ is unconditionally summable then for every neighborhood $$W$$ of the origin in $$X,$$ there is a finite subset $$A_0 \subseteq I$$ such that $$a_i \in W$$ for every index $$i$$ not in $$A_0.$$ If $$X$$ is a first-countable space then it follows that the set of $$i \in I$$ such that $$a_i \neq 0$$ is countable. This need not be true in a general abelian topological group (see examples below).

Unconditionally convergent series
Suppose that $$I = \N.$$ If a family $$a_n, n \in \N,$$ is unconditionally summable in a Hausdorff abelian topological group $$X,$$ then the series in the usual sense converges and has the same sum,

$$\sum_{n=0}^\infty a_n = \sum_{n \in \N} a_n.$$

By nature, the definition of unconditional summability is insensitive to the order of the summation. When $$\sum a_n$$ is unconditionally summable, then the series remains convergent after any permutation $$\sigma : \N \to \N$$ of the set $$\N$$ of indices, with the same sum,

$$\sum_{n=0}^\infty a_{\sigma(n)} = \sum_{n=0}^\infty a_n.$$

Conversely, if every permutation of a series $$\sum a_n$$ converges, then the series is unconditionally convergent. When $$X$$ is complete then unconditional convergence is also equivalent to the fact that all subseries are convergent; if $$X$$ is a Banach space, this is equivalent to say that for every sequence of signs $$\varepsilon_n = \pm 1$$, the series

$$\sum_{n=0}^\infty \varepsilon_n a_n$$

converges in $$X.$$

Series in topological vector spaces
If $$X$$ is a topological vector space (TVS) and $$\left(x_i\right)_{i \in I}$$ is a (possibly uncountable) family in $$X$$ then this family is summable if the limit $$\lim_{A \in \operatorname{Finite}(I)} x_A$$ of the net $$\left(x_A\right)_{A \in \operatorname{Finite}(I)}$$ exists in $$X,$$ where $$\operatorname{Finite}(I)$$ is the directed set of all finite subsets of $$I$$ directed by inclusion $$\,\subseteq\,$$ and $x_A := \sum_{i \in A} x_i.$

It is called absolutely summable if in addition, for every continuous seminorm $$p$$ on $$X,$$ the family $$\left(p\left(x_i\right)\right)_{i \in I}$$ is summable. If $$X$$ is a normable space and if $$\left(x_i\right)_{i \in I}$$ is an absolutely summable family in $$X,$$ then necessarily all but a countable collection of $$x_i$$’s are zero. Hence, in normed spaces, it is usually only ever necessary to consider series with countably many terms.

Summable families play an important role in the theory of nuclear spaces.

Series in Banach and seminormed spaces
The notion of series can be easily extended to the case of a seminormed space. If $$x_n$$ is a sequence of elements of a normed space $$X$$ and if $$x \in X$$ then the series $$\sum x_n$$ converges to $$x$$ in $$X$$ if the sequence of partial sums of the series $\left(\sum_{n=0}^N x_n\right)_{N=1}^{\infty}$ converges to $$x$$ in $$X$$; to wit,

$$\left\|x - \sum_{n=0}^N x_n\right\| \to 0 \quad \text{ as } N \to \infty.$$

More generally, convergence of series can be defined in any abelian Hausdorff topological group. Specifically, in this case, $$\sum x_n$$ converges to $$x$$ if the sequence of partial sums converges to $$x.$$

If $$(X, |\cdot|)$$ is a seminormed space, then the notion of absolute convergence becomes: A series $\sum_{i \in I} x_i$ of vectors in $$X$$ converges absolutely if

$$ \sum_{i \in I} \left|x_i\right| < +\infty$$

in which case all but at most countably many of the values $$\left|x_i\right|$$ are necessarily zero.

If a countable series of vectors in a Banach space converges absolutely then it converges unconditionally, but the converse only holds in finite-dimensional Banach spaces (theorem of ).

Well-ordered sums
Conditionally convergent series can be considered if $$I$$ is a well-ordered set, for example, an ordinal number $$\alpha_0.$$ In this case, define by transfinite recursion:

$$\sum_{\beta < \alpha + 1} a_\beta = a_{\alpha} + \sum_{\beta < \alpha} a_\beta$$

and for a limit ordinal $$\alpha,$$

$$\sum_{\beta < \alpha} a_\beta = \lim_{\gamma\to\alpha} \sum_{\beta < \gamma} a_\beta$$

if this limit exists. If all limits exist up to $$\alpha_0,$$ then the series converges.

Examples
\begin{cases} 0 & x\neq a, \\ f(a) & x=a, \\ \end{cases} $$
 * 1) Given a function $$f : X \to Y$$ into an abelian topological group $$Y,$$ define for every $$a \in X,$$ $$f_a(x)=

a function whose support is a singleton $$\{a\}.$$ Then

$$f = \sum_{a \in X}f_a$$

in the topology of pointwise convergence (that is, the sum is taken in the infinite product group $$Y^X$$).

 * 1) In the definition of partitions of unity, one constructs sums of functions over arbitrary index set $$I,$$ $$ \sum_{i \in I} \varphi_i(x) = 1.$$

While, formally, this requires a notion of sums of uncountable series, by construction there are, for every given $$x,$$ only finitely many nonzero terms in the sum, so issues regarding convergence of such sums do not arise. Actually, one usually assumes more: the family of functions is locally finite, that is, for every $$x$$ there is a neighborhood of $$x$$ in which all but a finite number of functions vanish. Any regularity property of the $$\varphi_i,$$ such as continuity, differentiability, that is preserved under finite sums will be preserved for the sum of any subcollection of this family of functions.

 * 1) On the first uncountable ordinal $$\omega_1$$ viewed as a topological space in the order topology, the constant function $$f : \left[0, \omega_1\right) \to \left[0, \omega_1\right]$$ given by $$f(\alpha) = 1$$ satisfies $$\sum_{\alpha \in [0,\omega_1)}f(\alpha) = \omega_1$$

(in other words, $$\omega_1$$ copies of 1 is $$\omega_1$$) only if one takes a limit over all countable partial sums, rather than finite partial sums. This space is not separable.

title: Series (mathematics)


text:
Interrupt

In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to interrupt currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, the processor will suspend its current activities, save its state, and execute a function called an interrupt handler (or an interrupt service routine, ISR) to deal with the event. This interruption is often temporary, allowing the software to resume normal activities after the interrupt handler finishes, although the interrupt could instead indicate a fatal error.

Interrupts are commonly used by hardware devices to indicate electronic or physical state changes that require time-sensitive attention. Interrupts are also commonly used to implement computer multitasking and system calls, especially in real-time computing. Systems that use interrupts in these ways are said to be interrupt-driven.

History
Hardware interrupts were introduced as an optimization, eliminating unproductive waiting time in polling loops, waiting for external events. The first system to use this approach was the DYSEAC, completed in 1954, although earlier systems provided error trap functions.

The UNIVAC 1103A computer is generally credited with the earliest use of interrupts in 1953. Earlier, on the UNIVAC I (1951) "Arithmetic overflow either triggered the execution of a two-instruction fix-up routine at address 0, or, at the programmer's option, caused the computer to stop." The IBM 650 (1954) incorporated the first occurrence of interrupt masking. The National Bureau of Standards DYSEAC (1954) was the first to use interrupts for I/O. The IBM 704 was the first to use interrupts for debugging, with a "transfer trap", which could invoke a special routine when a branch instruction was encountered. The MIT Lincoln Laboratory TX-2 system (1957) was the first to provide multiple levels of priority interrupts.

Types
Interrupt signals may be issued in response to hardware or software events. These are classified as hardware interrupts or software interrupts, respectively. For any particular processor, the number of interrupt types is limited by the architecture.

Hardware interrupts
A hardware interrupt is a condition related to the state of the hardware that may be signaled by an external hardware device, e.g., an interrupt request (IRQ) line on a PC, or detected by devices embedded in processor logic (e.g., the CPU timer in IBM System/370), to communicate that the device needs attention from the operating system (OS) or, if there is no OS, from the bare metal program running on the CPU. Such external devices may be part of the computer (e.g., disk controller) or they may be external peripherals. For example, pressing a keyboard key or moving a mouse plugged into a PS/2 port triggers hardware interrupts that cause the processor to read the keystroke or mouse position.

Hardware interrupts can arrive asynchronously with respect to the processor clock, and at any time during instruction execution. Consequently, all incoming hardware interrupt signals are conditioned by synchronizing them to the processor clock, and acted upon only at instruction execution boundaries.

In many systems, each device is associated with a particular IRQ signal. This makes it possible to quickly determine which hardware device is requesting service, and to expedite servicing of that device.

On some older systems, such as the 1964 CDC 3600, all interrupts went to the same location, and the OS used a specialized instruction to determine the highest-priority outstanding unmasked interrupt. On contemporary systems, there is generally a distinct interrupt routine for each type of interrupt (or for each interrupt source), often implemented as one or more interrupt vector tables.

Masking
To mask an interrupt is to disable it, so it is deferred or ignored by the processor, while to unmask an interrupt is to enable it.

Processors typically have an internal interrupt mask register, which allows selective enabling (and disabling) of hardware interrupts. Each interrupt signal is associated with a bit in the mask register. On some systems, the interrupt is enabled when the bit is set, and disabled when the bit is clear. On others, the reverse is true, and a set bit disables the interrupt. When the interrupt is disabled, the associated interrupt signal may be ignored by the processor, or it may remain pending. Signals which are affected by the mask are called maskable interrupts.

Some interrupt signals are not affected by the interrupt mask and therefore cannot be disabled; these are called non-maskable interrupts (NMIs). These indicate high-priority events which cannot be ignored under any circumstances, such as the timeout signal from a watchdog timer. With regard to SPARC, the Non-Maskable Interrupt (NMI), despite having the highest priority among interrupts, can be prevented from occurring through the use of an interrupt mask.

Missing interrupts
One failure mode is when the hardware does not generate the expected interrupt for a change in state, causing the operating system to wait indefinitely. Depending on the details, the failure might affect only a single process or might have global impact. Some operating systems have code specifically to deal with this.

As an example, IBM Operating System/360 (OS/360) relies on a not-ready to ready device-end interrupt when a tape has been mounted on a tape drive, and will not read the tape label until that interrupt occurs or is simulated. IBM added code in OS/360 so that the VARY ONLINE command will simulate a device end interrupt on the target device.

Spurious interrupts
A spurious interrupt is a hardware interrupt for which no source can be found. The term "phantom interrupt" or "ghost interrupt" may also be used to describe this phenomenon. Spurious interrupts tend to be a problem with a wired-OR interrupt circuit attached to a level-sensitive processor input. Such interrupts may be difficult to identify when a system misbehaves.

In a wired-OR circuit, parasitic capacitance charging/discharging through the interrupt line's bias resistor will cause a small delay before the processor recognizes that the interrupt source has been cleared. If the interrupting device is cleared too late in the interrupt service routine (ISR), there will not be enough time for the interrupt circuit to return to the quiescent state before the current instance of the ISR terminates. The result is the processor will think another interrupt is pending, since the voltage at its interrupt request input will be not high or low enough to establish an unambiguous internal logic 1 or logic 0. The apparent interrupt will have no identifiable source, hence the "spurious" moniker.

A spurious interrupt may also be the result of electrical anomalies due to faulty circuit design, high noise levels, crosstalk, timing issues, or more rarely, device errata.

A spurious interrupt may result in system deadlock or other undefined operation if the ISR does not account for the possibility of such an interrupt occurring. As spurious interrupts are mostly a problem with wired-OR interrupt circuits, good programming practice in such systems is for the ISR to check all interrupt sources for activity and take no action (other than possibly logging the event) if none of the sources is interrupting. They may even lead to crashing of the computer in adverse scenarios.

Software interrupts
A software interrupt is requested by the processor itself upon executing particular instructions or when certain conditions are met. Every software interrupt signal is associated with a particular interrupt handler.

A software interrupt may be intentionally caused by executing a special instruction which, by design, invokes an interrupt when executed. Such instructions function similarly to subroutine calls and are used for a variety of purposes, such as requesting operating system services and interacting with device drivers (e.g., to read or write storage media). Software interrupts may also be triggered by program execution errors or by the virtual memory system.

Typically, the operating system kernel will catch and handle such interrupts. Some interrupts are handled transparently to the program - for example, the normal resolution of a page fault is to make the required page accessible in physical memory. But in other cases such as a segmentation fault the operating system executes a process callback. On Unix-like operating systems this involves sending a signal such as SIGSEGV, SIGBUS, SIGILL or SIGFPE, which may either call a signal handler or execute a default action (terminating the program). On Windows the callback is made using Structured Exception Handling with an exception code such as STATUS_ACCESS_VIOLATION or STATUS_INTEGER_DIVIDE_BY_ZERO.

In a kernel process, it is often the case that some types of software interrupts are not supposed to happen. If they occur nonetheless, an operating system crash may result.

Terminology
The terms interrupt, trap, exception, fault, and abort are used to distinguish types of interrupts, although "there is no clear consensus as to the exact meaning of these terms". The term trap may refer to any interrupt, to any software interrupt, to any synchronous software interrupt, or only to interrupts caused by instructions with trap in their names. In some usages, the term trap refers specifically to a breakpoint intended to initiate a context switch to a monitor program or debugger. It may also refer to a synchronous interrupt caused by an exceptional condition (e.g., division by zero, invalid memory access, illegal opcode), although the term exception is more common for this.

x86 divides interrupts into (hardware) interrupts and software exceptions, and identifies three types of exceptions: faults, traps, and aborts. (Hardware) interrupts are interrupts triggered asynchronously by an I/O device, and allow the program to be restarted with no loss of continuity. A fault is restartable as well but is tied to the synchronous execution of an instruction - the return address points to the faulting instruction. A trap is similar to a fault except that the return address points to the instruction to be executed after the trapping instruction; one prominent use is to implement system calls. An abort is used for severe errors, such as hardware errors and illegal values in system tables, and often does not allow a restart of the program.

Arm uses the term exception to refer to all types of interrupts, and divides exceptions into (hardware) interrupts, aborts, reset, and exception-generating instructions. Aborts correspond to x86 exceptions and may be prefetch aborts (failed instruction fetches) or data aborts (failed data accesses), and may be synchronous or asynchronous. Asynchronous aborts may be precise or imprecise. MMU aborts (page faults) are synchronous.

RISC-V uses interrupt as the overall term as well as for the external subset; internal interrupts are called exceptions.

Triggering methods
Each interrupt signal input is designed to be triggered by either a logic signal level or a particular signal edge (level transition). Level-sensitive inputs continuously request processor service so long as a particular (high or low) logic level is applied to the input. Edge-sensitive inputs react to signal edges: a particular (rising or falling) edge will cause a service request to be latched; the processor resets the latch when the interrupt handler executes.

Level-triggered
A level-triggered interrupt is requested by holding the interrupt signal at its particular (high or low) active logic level. A device invokes a level-triggered interrupt by driving the signal to and holding it at the active level. It negates the signal when the processor commands it to do so, typically after the device has been serviced.

The processor samples the interrupt input signal during each instruction cycle. The processor will recognize the interrupt request if the signal is asserted when sampling occurs.

Level-triggered inputs allow multiple devices to share a common interrupt signal via wired-OR connections. The processor polls to determine which devices are requesting service. After servicing a device, the processor may again poll and, if necessary, service other devices before exiting the ISR.

Edge-triggered
An edge-triggered interrupt is an interrupt signaled by a level transition on the interrupt line, either a falling edge (high to low) or a rising edge (low to high). A device wishing to signal an interrupt drives a pulse onto the line and then releases the line to its inactive state. If the pulse is too short to be detected by polled I/O then special hardware may be required to detect it. The important part of edge triggering is that the signal must transition to trigger the interrupt; for example, if the signal was high-low-low, there would only be one falling edge interrupt triggered, and the continued low level would not trigger a further interrupt. The signal must return to the high level and fall again in order to trigger a further interrupt. This contrasts with a level trigger where the low level would continue to create interrupts (if they are enabled) until the signal returns to its high level.

Computers with edge-triggered interrupts may include an interrupt register that retains the status of pending interrupts. Systems with interrupt registers generally have interrupt mask registers as well.

Processor response
The processor samples the interrupt trigger signals or interrupt register during each instruction cycle, and will process the highest priority enabled interrupt found. Regardless of the triggering method, the processor will begin interrupt processing at the next instruction boundary following a detected trigger, thus ensuring:
 * The processor status is saved in a known manner. Typically the status is stored in a known location, but on some systems it is stored on a stack.
 * All instructions before the one pointed to by the PC have fully executed.
 * No instruction beyond the one pointed to by the PC has been executed, or any such instructions are undone before handling the interrupt.
 * The execution state of the instruction pointed to by the PC is known.

There are several different architectures for handling interrupts. In some, there is a single interrupt handler that must scan for the highest priority enabled interrupt. In others, there are separate interrupt handlers for separate interrupt types, separate I/O channels or devices, or both. Several interrupt causes may have the same interrupt type and thus the same interrupt handler, requiring the interrupt handler to determine the cause.

System implementation
Interrupts may be fully handled in hardware by the CPU, or may be handled by both the CPU and another component such as a programmable interrupt controller or a southbridge.

If an additional component is used, that component would be connected between the interrupting device and the processor's interrupt pin to multiplex several sources of interrupt onto the one or two CPU lines typically available. If implemented as part of the memory controller, interrupts are mapped into the system's memory address space.

In systems on a chip (SoC) implementations, interrupts come from different blocks of the chip and are usually aggregated in an interrupt controller attached to one or several processors (in a multi-core system).

Shared IRQs
Multiple devices may share an edge-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or pull-up resistor so that when not actively driven it settles to its inactive state, which is the default state of it. Devices signal an interrupt by briefly driving the line to its non-default state, and let the line float (do not actively drive it) when not signaling an interrupt. This type of connection is also referred to as open collector. The line then carries all the pulses generated by all the devices. (This is analogous to the pull cord on some buses and trolleys that any passenger can pull to signal the driver that they are requesting a stop.) However, interrupt pulses from different devices may merge if they occur close in time. To avoid losing interrupts the CPU must trigger on the trailing edge of the pulse (e.g. the rising edge if the line is pulled up and driven low). After detecting an interrupt the CPU must check all the devices for service requirements.

Edge-triggered interrupts do not suffer the problems that level-triggered interrupts have with sharing. Service of a low-priority device can be postponed arbitrarily, while interrupts from high-priority devices continue to be received and get serviced. If there is a device that the CPU does not know how to service, which may raise spurious interrupts, it will not interfere with interrupt signaling of other devices. However, it is easy for an edge-triggered interrupt to be missed - for example, when interrupts are masked for a period - and unless there is some type of hardware latch that records the event it is impossible to recover. This problem caused many "lockups" in early computer hardware because the processor did not know it was expected to do something. More modern hardware often has one or more interrupt status registers that latch interrupts requests; well-written edge-driven interrupt handling code can check these registers to ensure no events are missed.

The Industry Standard Architecture (ISA) bus uses edge-triggered interrupts, without mandating that devices be able to share IRQ lines, but all mainstream ISA motherboards include pull-up resistors on their IRQ lines, so well-behaved ISA devices sharing IRQ lines should just work fine. The parallel port also uses edge-triggered interrupts. Many older devices assume that they have exclusive use of IRQ lines, making it electrically unsafe to share them.

There are three ways multiple devices "sharing the same line" can be raised. First is by exclusive conduction (switching) or exclusive connection (to pins). Next is by bus (all connected to the same line listening): cards on a bus must know when they are to talk and not talk (i.e., the ISA bus). Talking can be triggered in two ways: by accumulation latch or by logic gates. Logic gates expect a continual data flow that is monitored for key signals. Accumulators only trigger when the remote side excites the gate beyond a threshold, thus no negotiated speed is required. Each has its speed versus distance advantages. A trigger, generally, is the method in which excitation is detected: rising edge, falling edge, threshold (oscilloscope can trigger a wide variety of shapes and conditions).

Triggering for software interrupts must be built into the software (both in OS and app). A 'C' app has a trigger table (a table of functions) in its header, which both the app and OS know of and use appropriately that is not related to hardware. However do not confuse this with hardware interrupts which signal the CPU (the CPU enacts software from a table of functions, similarly to software interrupts).

Difficulty with sharing interrupt lines
Multiple devices sharing an interrupt line (of any triggering style) all act as spurious interrupt sources with respect to each other. With many devices on one line, the workload in servicing interrupts grows in proportion to the square of the number of devices. It is therefore preferred to spread devices evenly across the available interrupt lines. Shortage of interrupt lines is a problem in older system designs where the interrupt lines are distinct physical conductors. Message-signaled interrupts, where the interrupt line is virtual, are favored in new system architectures (such as PCI Express) and relieve this problem to a considerable extent.

Some devices with a poorly designed programming interface provide no way to determine whether they have requested service. They may lock up or otherwise misbehave if serviced when they do not want it. Such devices cannot tolerate spurious interrupts, and so also cannot tolerate sharing an interrupt line. ISA cards, due to often cheap design and construction, are notorious for this problem. Such devices are becoming much rarer, as hardware logic becomes cheaper and new system architectures mandate shareable interrupts.

Hybrid
Some systems use a hybrid of level-triggered and edge-triggered signaling. The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time.

A common use of a hybrid interrupt is for the NMI (non-maskable interrupt) input. Because NMIs generally signal major – or even catastrophic – system events, a good implementation of this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period of time. This 2-step approach helps to eliminate false interrupts from affecting the system.

Message-signaled
A message-signaled interrupt does not use a physical interrupt line. Instead, a device signals its request for service by sending a short message over some communications medium, typically a computer bus. The message might be of a type reserved for interrupts, or it might be of some pre-existing type such as a memory write.

Message-signalled interrupts behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition. Interrupt-handling software treats the two in much the same manner. Typically, multiple pending message-signaled interrupts with the same message (the same virtual interrupt line) are allowed to merge, just as closely spaced edge-triggered interrupts can merge.

Message-signalled interrupt vectors can be shared, to the extent that the underlying communication medium can be shared. No additional effort is required.

Because the identity of the interrupt is indicated by a pattern of data bits, not requiring a separate physical conductor, many more distinct interrupts can be efficiently handled. This reduces the need for sharing. Interrupt messages can also be passed over a serial bus, not requiring any additional lines.

PCI Express, a serial computer bus, uses message-signaled interrupts exclusively.

Doorbell
In a push button analogy applied to computer systems, the term doorbell or doorbell interrupt is often used to describe a mechanism whereby a software system can signal or notify a computer hardware device that there is some work to be done. Typically, the software system will place data in some well-known and mutually agreed upon memory locations, and "ring the doorbell" by writing to a different memory location. This different memory location is often called the doorbell region, and there may even be multiple doorbells serving different purposes in this region. It is this act of writing to the doorbell region of memory that "rings the bell" and notifies the hardware device that the data are ready and waiting. The hardware device would now know that the data are valid and can be acted upon. It would typically write the data to a hard disk drive, or send them over a network, or encrypt them, etc.

The term doorbell interrupt is usually a misnomer. It is similar to an interrupt, because it causes some work to be done by the device; however, the doorbell region is sometimes implemented as a polled region, sometimes the doorbell region writes through to physical device registers, and sometimes the doorbell region is hardwired directly to physical device registers. When either writing through or directly to physical device registers, this may cause a real interrupt to occur at the device's central processor unit (CPU), if it has one.

Doorbell interrupts can be compared to Message Signaled Interrupts, as they have some similarities.

Multiprocessor IPI
In multiprocessor systems, a processor may send an interrupt request to another processor via inter-processor interrupts (IPI).

Performance
Interrupts provide low overhead and good latency at low load, but degrade significantly at high interrupt rate unless care is taken to prevent several pathologies. The phenomenon where the overall system performance is severely hindered by excessive amounts of processing time spent handling interrupts is called an interrupt storm.

There are various forms of livelocks, when the system spends all of its time processing interrupts to the exclusion of other required tasks. Under extreme conditions, a large number of interrupts (like very high network traffic) may completely stall the system. To avoid such problems, an operating system must schedule network interrupt handling as carefully as it schedules process execution.

With multi-core processors, additional performance improvements in interrupt handling can be achieved through receive-side scaling (RSS) when multiqueue NICs are used. Such NICs provide multiple receive queues associated to separate interrupts; by routing each of those interrupts to different cores, processing of the interrupt requests triggered by the network traffic received by a single NIC can be distributed among multiple cores. Distribution of the interrupts among cores can be performed automatically by the operating system, or the routing of interrupts (usually referred to as IRQ affinity) can be manually configured.

A purely software-based implementation of the receiving traffic distribution, known as receive packet steering (RPS), distributes received traffic among cores later in the data path, as part of the interrupt handler functionality. Advantages of RPS over RSS include no requirements for specific hardware, more advanced traffic distribution filters, and reduced rate of interrupts produced by a NIC. As a downside, RPS increases the rate of inter-processor interrupts (IPIs). Receive flow steering (RFS) takes the software-based approach further by accounting for application locality; further performance improvements are achieved by processing interrupt requests by the same cores on which particular network packets will be consumed by the targeted application.

Typical uses
Interrupts are commonly used to service hardware timers, transfer data to and from storage (e.g., disk I/O) and communication interfaces (e.g., UART, Ethernet), handle keyboard and mouse events, and to respond to any other time-sensitive events as required by the application system. Non-maskable interrupts are typically used to respond to high-priority requests such as watchdog timer timeouts, power-down signals and traps.

Hardware timers are often used to generate periodic interrupts. In some applications, such interrupts are counted by the interrupt handler to keep track of absolute or elapsed time, or used by the OS task scheduler to manage execution of running processes, or both. Periodic interrupts are also commonly used to invoke sampling from input devices such as analog-to-digital converters, incremental encoder interfaces, and GPIO inputs, and to program output devices such as digital-to-analog converters, motor controllers, and GPIO outputs.

A disk interrupt signals the completion of a data transfer from or to the disk peripheral; this may cause a process to run which is waiting to read or write. A power-off interrupt predicts imminent loss of power, allowing the computer to perform an orderly shut-down while there still remains enough power to do so. Keyboard interrupts typically cause keystrokes to be buffered so as to implement typeahead.

Interrupts are sometimes used to emulate instructions which are unimplemented on some computers in a product family. For example floating point instructions may be implemented in hardware on some systems and emulated on lower-cost systems. In the latter case, execution of an unimplemented floating point instruction will cause an "illegal instruction" exception interrupt. The interrupt handler will implement the floating point function in software and then return to the interrupted program as if the hardware-implemented instruction had been executed. This provides application software portability across the entire line.

Interrupts are similar to signals, the difference being that signals are used for inter-process communication (IPC), mediated by the kernel (possibly via system calls) and handled by processes, while interrupts are mediated by the processor and handled by the kernel. The kernel may pass an interrupt as a signal to the process that caused it (typical examples are SIGSEGV, SIGBUS, SIGILL and SIGFPE).

title: Interrupt