text:
Database management systems

Course Purpose
1) The aim is to present the general principles of the database systems with a practical focus, and some implementation assignments. Those assignments may or may not include some programming

2)The course assumes that students have some programming or strong logical reasoning skills in programming languages like C or C++. Some programing data structures such as (heap files, buffer manager, B+ trees, hash indexes, varoius goin methodes) are used in the course

3) The course concentrates on issues of the design, tuning, and implementation of the databases

The object of Database

 * A database is a collection of information, which describes the activities of one of more related organizations. The performance and productivity of organization depends on their abilities to acquire accurate and up to time data, and manage it. The amount of the data organization is exponentially growing and hard to manage by hand, so the database management system comes to help.
 * For example, if the database is about a food store, the information in database can be characterized as
 * Entities, such as products, salespeople, etc
 * Relationships between the entities such as products, and salesmen who are selling them.
 * Database management system, or DBMS is a software that assists people in managing the database information.And well as its performance
 * The basic operations of the database systems can be characterized as
 * Database Design: This is the way the user describes the real world issue in terms of the DBMS system
 * Data Analysis:How a user can address the problem of analyzing information upon a request by the company, and doing it efficiently.
 * Concurrency: How the DBMS can handle multiple requests accurately at the same time.

Describing and storing data in the database

 * Is the issue of translating the real world structure of the business into the data model. Data model is a collection of high-level presented data. The database software allows user to define data which will be stored in DBMS. Most of the databases use the relational data model. Semantic data model is a more complicated mind map of the database needed to tolerate given situation.
 * The semantic data model is also called the Entity Relationship model

Chapter 1: Relational Model
Data is formatted in tables, where each row represents an entry. For example, in a table of salespeople each row represents information about each particular salesperson. This data includes his/her name, age, address, etc. Such a single row of information is called a record.
 * The record can be treated as an array of an information, with its components treated as fields.

Relation is rule which relates different records of different tables. For example: records exist in a table of salespeople, as well as in a table of products. So it is possible to assign each salesperson as a specialist in each product. Such an assignment can be characterized as a relation.
 * A database query is a program which presents particular information from the DBMS upon users request.
 * A stored procedure is a program which performs data maintenance other than a query.

Relational Model Concepts
Relation is often represented as a table. Each table consists of several rows with many related values. One such row is called a tuple. In formal relational model a table is called table, the column headers are called attributes.

Chapter 2: File Organization and Indexing
Even though the database shows us data in the form of relations we must understand that it is just a logical representation. Finally all the data needs to be stored on the hard disk as files. It is very important in performance point of view that this organization should allow the database software to access data quickly and in an efficient way.

 * A Primary Storage is that storage that is directly accessible to the CPU and is limited. The data to be processed is usually brought from secondary storage to primary storage as and when needed. It is very fast but size is limited.
 * A Secondary Storage includes magnetic discs, tapes, optical media etc. In short the mass storage devices.
 * A Buffering is done to copy data from secondary storage to primary storage. In case the secondary storage is magnetic disk data is copied in units called blocks. Often a block is of same size as a cluster.

Records
Data is stored in files in the form of records. Records are related type of data. Ex. Details of one employee. However the data types too are important while storing data. The various data types are integer, text, date and time etc. Once they are recorded to a file while retrieving them back we must know their correct data type. With the latest databases we have a huge number of data types. To store binary data like program files and images we have a data type called BLOBs.

Fixed Length v/s Variable Length Records
Files are accessed sequentially hence to retrieve each record we must know its size. If the records are known to be of fixed size the work is very simple. Consider a list of mobile numbers where each number is exactly 10 digits long. Retrieving number will be simple here because we can read 10 characters at a time. But consider a list of names. How do we know the size of names? They can vary. To make matters more complex we can have records of certain number of fixed length entries and some variable length entries. Variable length records can be separated by a delimiter or separator such as a comma ',' or new line. Comma Separated Values or CVS is one such file based database. If every record in the file has exactly the same size (in bytes) the file is said to be made up of Fixed length records. if different records in the file have different sizes,the file is made up of variable length records.

Records on Disk: Spanned v/s Unspanned
Records need to be stored on a disk. Read and Write operations on disk are usually done in disk blocks. If the block size is greater than one record we might record many records in a single block and vice versa. In any case if the block size is not exactly divisible by the size of each records or to put in better terms the number of records that can be stored in a block is not a natural number a part of record will get stored on one block and remaining on some other disk block. In such a case there will be a pointer at the end of the disk block that will point to the next block. Such a organization is called Spanned. If Records are not allowed to cross block boundaries we call them unspanned.

Related materials
School:Computer Science:
 * Introduction to Databases
 * Introduction to SQL
 * Topic:Databases
 * Topic:Object-relational databases

title: Database management systems


text:
Wikiversity talk:Interlingual Beta Club

CQ's original post at the English Wikiversity Colloquium :
 * I have been pathetically monolingual since I was in the first grade. I've been challenged to learn a different language for years, but I must admit, it's intimidating as all getout. I've been on this quest for a while,but since I joined V:, it all seems a bit more plausible now. I started with a little "multilingual worksheet" approaching the task (of translating the Pen Pal Wiki) with a "holistic" strategy hoping for some university-styled guidance. It has escalated into an all-out offensive against isolation and the feeling of utter helplessness culminating in this attempt to employ some interlingual dialog. CQ 15:30, 22 October 2006 (UTC)

I guess I'd like to help...
...but perhaps what we need is just a set of assignments to translate and willing translators to take them on. You could even prod we multilinguals by making some form of "unfree knowledge" anti-barnstar on their talk pages. Evil, but who knows. If you want Japanese or French translated, I'll give it a go. I don't read Japanese as well as I speak it tho.--Dnjkirk 17:24, 23 October 2006 (UTC)
 * I'm not clear at all on what the "unfree knowledge" anti-barnstar might be, but any help on Japanese or French translation will be appreciated. CQ 05:10, 3 December 2006 (UTC)

Interlingual navigation
We now have a French version of Wikiversity. I think it's time now to start building some interlingual navigation for building common context. A good place to start I think, is to become familiar with the main, welcome and colloquium pages, so I started making these templates:

 * 1) InterlingualMainNavEn
 * 2) InterlingualMainNavDe
 * 3) InterlingualMainNavEs
 * 4) InterlingualMainNavFr

InterlingualMainNavEn:

Please lend me a hand on checking the templates establishing harbingers on the other Wikversity version sites using native language page titles, "Interlingual Beta Club" and "community service project to support Wikiversity Beta and to promote Multilingualism and Interlingual discourse [[Image:Rosetta Stone.jpg|200px|right]]

Summary
The Wikiversity Beta website coordinates all of the Wikiversity projects for speakers of different languages. This coordination is guided by the Wikiversity mission that was approved by the Wikimedia Foundation.

The Wikiversity Beta website is a central location for discussion of general guidelines for all Wikiversities. The prime example:
 * The Board of Trustees has requested that the Wikiversity community develops a policy for original research during the first six months of the project. This pesents the dreaded (conceptualization) of the deadline. So where on the Wikiversity Roadmap is this presumed "dead line"? Who gives a *** ??? fig

Wikiversity Beta is an incubator for new Wikiversities in several languages. Wikiversity Beta needs help translating documents into the many different languages spoken and written by Wikiversity participants (Wikiversitans).

Likewise many documents in many languages need to be written and translated into English, German, Spanish, Portugese, Korean, Chinese, Hawaiian, Cherokee and Klingon... for this Wikiversity.

A Wikiversity Beta support network called the Interlingual Beta Club (IBC) has been framed (from the grass roots, in the spirit of your Beta Club back on Earth. (...but out here your As and Bs come from within you.)

Goals
This learning project offers learnings activities that give participants experience in performing translations. Experienced translators are providing comparitive texts, descriptions of the tools of the trade, (machine translation, computer-assisted translation, etc. ) and are there to "show you the ropes" of the Art / Science of Translation.

Right now (24 October 2006) There is a draft version of a Translator's Handbook being worked on collaboratively by the IBC and the Translation Taskforce. The new Translation learning group is starting up a three-language program to translate documents between English, German and Spanish.

Learning materials

 * Wikiversity translations/Recruiting translators
 * Wikiversity translations/Training translators

 * Topic:German Language • German deu
 * Topic:English Language • English eng
 * Topic:Spanish • Spanish spa
 * add the other 6492 languages here

Activities

 * English to German, translate: Scope of research, Research, Original research, Secondary research, Project reports.

Translation requests

 * High priority German to English (source)

Ich stimme Purodha zu und möchte für eine generelle Freigabe der original research / empirischen Forschung anführen, das deren Regeln entscheidend sind: jede empirische Forschung sollte nicht nur vom Ergebnis, sondern auch von der Beschreibung der Durchführung bzw. der Herkunft der Ergebnisse so präzise dokumentiert sein, das sie eindeutig reproduziert werden kann. Umgekehrt: Ein Versuch, der aufgrund ungenauer Beschreibung nicht reproduziert werden kann, falsifiziert das Ergebnis des ersten Versuches ebenso wie ein abweichendes Ergebnis bei präziser Wiederholung. Dietrich 18:09, 12. Nov 2006 (CEST)

 * Machine translation (needs human attention!):

 * I agree Purodha and would like for a general release of the original research / research of empirical cite, that are its rules decisively: each empirical research should be documented not only by the result, but rather also by the description of the execution and/or the origin of the results so precise, unambiguously reproduced will can that it. Reversed:  An attempt, that cannot be reproduced based on inexact description, falsifiziert the result of the first attempt just as as a deviating result in precise repetition.

 * I agree with Purodha and would like to state, in general, crucially, that: each piece empirical research should contain not only the result, but also the precise documentation of execution and/or the origin of the research, so as to allow others to reproduce the results. Turned around: An attempt, which cannot be reproduced due to inaccurate description, falsifises the result, in the same way as result deviations under a more precise attempt. (translation by Hillgentleman)

 * on-going: Scope of research and related pages at Wikiversity Beta.
 * completed translations Wikiversity translations/De to En archive (please check/improve)

Interlingual collaboration
The Wikiversity Beta incubator site is coming along, but could use a lot more participation. Multilingual Studies at this version of Wikiversity is working on communicating directly with the German and Spanish Wikiversities and the main Beta incubator. We hope to establish communication lines directly with versions (those with subdomains and working interwiki links):
 * de.wikiversity.org - de:Hauptseite
 * en.wikiversity.org - Main Page
 * es.wikiversity.org - es:Portada
 * fr.wikiversity.org - fr:Accuel
 * ..next..

Other language wikiversities may exist as betas. See the nav bar at the top of Beta Wikiversity for versions under development.

 * Technical note: - For some odd reason, beta.wikiversity is not mapped into the local Interwiki map. This may be a job for the MediaWiki Project.

Parallel texts
We are developing two methods for dealing with parallel texts:
 * 1) bilingual comparative texts - A simple method by which two versions of a block of text are presented on a single page. (learning projects such as German to English, Japanese to English...)
 * 2) Topic:Multilingual Studies - A socio-technical approach to Multilingual collaboration and translation (Challenging but rewarding! See the Challenges section below)

 * We are in the process of organizing Language departments, building on the massive efforts at Wikipedia, Wiktionary, Wikibooks, Meta and many other projects inside and outside of Wikimedia. The Translation process is a strange and wonderful study for those with enough patience to pursue it. The Interlingual Beta Club and the Wikiversity Embassy are looking at the social and academic prospects for evaluating and rewarding such effort. (Again, see the Challenges section below)

Corpus linguistics
Computational linguistics combines Computer Science and Linguistics to develop a model of a natural language. As an institution, Wikiversity Proper (all versions present and future) is developing its own universal context: Keywords like these must be translated immediately for the application to function effectively across languages. The table below is concentrated on English, German, Spanish and French language articles that can be synchronized on the four established Wikiversity versions. The selected articles are about translation itself and were chosen to expedite the establishment of Multilingual Studies Divisions with native language and translation departments for fast-track translation:
 * 1) Technical context: MediaWiki-specific terminology inherited from the application — Help: Category: User: Template: Special: etc.
 * 2) Academic context: Schools, Departments, Divisions, Topics, Courses, etc.

 * Note: The Translator's Handbook has no "master" copy. Each local copy residing in the Wikiversity project space on the three established Wikiversities are "draft" versions. Once the native speakers of English, German and Spanish are satisified with their version, it goes to the Wikiversity project space at Beta for review and editing by French, Chinese, Dutch, Portuguese, Russian, Korean, Italian and many other native language users. It is a living document. Join the Interlingual Beta Club if you dare. (It's not for the faint-of-heart.)

See the Wikiversity Divisions and Departments subsection below

Taskforce objectives
To reiterate: the Local Translation Taskforce (English Language Wikiversity) is focused on a German/English/Spanish/French translation matrix. If you have translation interests and abilities beyond those four languages, please do not add language versions to translators until their subdomain resolves. (see Template_talk:Translators for more information) Please participate at Translation taskforce at Beta or Multilingualism at Meta instead.

 * Social Note: Keep in mind that it is OK to be anglocentric here at the English Language Wikiversity. Please get rid of that when you go to Wikiversity Beta.

Translation Projects
Spanish to English
 * Sugar in the times of cholera - translating an historical document from Spanish

English to French
 * Telemedicine in French-speaking Africa - help translate public health information into French.

Multilingual Studies:
 * Wikiversity the Movie/multi-lingual - create publicity materials for Wikiversity, including sound and video production.

Language orientation
English, German, Spanish and now French are primary departments, simply because those are the initial language implementations of Wikiversity. We can't stop there. These pages and the secondary ones Chinese, Dutch, Portugese and the other hundreds of languages will have an English disambiguation and Native redirects (examples: Deutsch -> German, Español -> Spanish, 中文 -> Chinese) to their proper local learning/teaching group here. English speakers who "reside" here will also follow Wikiversity fellows to other language Wikiversities where they should find an English-friendly area for Orientation. A good entry point for those who are on this learning path may be translation, which is the core module of the beta version of the Corpus mentioned above.

 * Special Note: Repeating... It is natural, acceptable and predicatable to be anglocentric here at the English Language Wikiversity. This is perceived to be the host with the most. As you learn and grow, you might consider a more circular conceptualization of the role and character of your particular language and culture.

Naming conventions
Naming conventions need to be consulted to homogonize the disambiguation pages, redirects, and language departments which point to things like German, English as a second language, Category:Spanish Language Division, German to English, Zh:中文, or Learning to speak Cherokee. This will make it easier for Non-English visitors and newcomers to find what they're looking for. See the Multilingual worksheet for more insight. discuss

Repeting...The technical context of MediaWiki requires an absolute treatment of namespaces and linkage all the way down to the case and character level. The technical aspects of interlinking contexts (not simply content) is staggering when your aim is to be inclusive. Wikiversity is, by definition non-exclusive in terms of who can participate and at what level. This culture of "liberty" (libre) is technically challenging and can be politically disturbing. Most would agree that Wikiversity is "standing upon the shoulders of giants".

 * Terms from the application — Help: Category: User: Template: Special: etc.
 * Terms from the institution — Schools, Departments, Divisions, Topics, Projects, Courses, etc.

''American Challenge: Now, translate those across Eastern and Western character sets and propogate Wikiversity to all languages and cultures without starting WWIII. Let's learn to balence convention against innovation when dealing with Naming conventions. What works "here" may not work "there" at all.''

Wikiversity Divisions and Departments
A myriad of work needs to be done:
 * 1) Translations for Wikiversity departments.
 * 2) Portal pages in every language at Wikiversity Beta.

If there is a Wikimedia project in language:X, there should be a page written in that language at Wikiversity Beta explaining what Wikiversity is and how to use Wikiversity Beta as an incubator for efforts leading to the creation of a Wikiversity domain specific protocol for language:X.

Readings
Each activity has a suggested associated background reading selection. You have the collective resources of the whole Wikimedia Foundation at your disposal. Use them!
 * Multilingualism system at Wikiversity Beta.
 * Consider your self a resident in training at The Wikiversity School of Medicene. You're on the verge of discovering a cure for Leukemia.

Culture shock
The name "Interlingual Beta Club" may be innapropriate for non-Americans. Might need to back up and punt. The goal is to foster dialog and learn to translate. Whatever works. Use WV:BUT (WikiVersity:Beta Universal Translator) CQ 12:05, 3 December 2006 (UTC)
 * So, how about then including some other words like: communication, teamwork,... ? E.g. "Wikiversity Communication Center". --Erkan Yilmaz 12:30, 3 December 2006 (UTC)

Glossary
Hi, I would propose to make something like a glossary for often used terms: e.g. Translation department, Schools,... Because such terms are perhaps not used in the different Wikiversities (because of their own structures, or they are not so far developed,...), so this helps people faster to understand an article. Could someone generate this and we will translate in the languages? --Erkan Yilmaz 14:02, 3 December 2006 (UTC)
 * e.g. Practicum: Kurs (I did not find yet an explanation for Kurs, so I made a link to the list of all courses) --Erkan Yilmaz 14:24, 3 December 2006 (UTC)
 * e.g. Translation departments: Übersetzungsinstitute --Erkan Yilmaz 14:44, 3 December 2006 (UTC)
 * I have started some work in this area through the Computational linguistics department. See the lexicography and Corpus linguistics sections. We need to immediately come up with a table for translations of the namespaces equivalent to School: Portal: Topic:, etc. Please check the example translation table at beta. BTW, Erkan and Daanschr, Thanks for the excellent translating work you've already done! CQ 18:20, 4 December 2006 (UTC)
 * Hi CQ, thx for the nice words. At the moment I was a little busy - also with other projects, so will read again tomorrow. --Erkan Yilmaz 23:02, 4 December 2006 (UTC)

German translation
Hi, the German translation of the IBC-page is translated here. I am reviewing it now for adapting things to the German wikiversity. I also added on the German, English, French, Spanish IBC-pages links to the other IBC-pages. --Erkan Yilmaz 14:36, 3 December 2006 (UTC)

 * I will add a Dutch translation.--Daanschr 14:50, 3 December 2006 (UTC)
 * great, we are growing already that fast. IBCs all over the world let's unite. :-) --Erkan Yilmaz 14:55, 3 December 2006 (UTC)
 * Vier Teilnehmer ist nicht viel.--Daanschr 16:50, 3 December 2006 (UTC)
 * Of course: 4 participants is not much yet, but more than 4 weeks ago. It is always a point of view (half empty or half full). :-) Probably we will have to do much more work now, but let`s see. --Erkan Yilmaz 16:55, 3 December 2006 (UTC)
 * It is probably my Dutch calvinist pessimism that always presends the bottle as half empty (while i am roman catholic, but the minorties always take over the culture of the majority).:-)--Daanschr 17:28, 3 December 2006 (UTC)
 * I guess you would probably be a good tester with such a pessimism. So, nevertheless keep up the pessimism. Better than non-pessimism. --Erkan Yilmaz 17:46, 3 December 2006 (UTC)
 * Thanks Erkan.--Daanschr 07:55, 4 December 2006 (UTC)

Freestyle / Freistil
Hi,

Erkan contacted me on de.wikibooks. I have started two language projects, namely Freistil and Freestyle that shall help learners of English resp. German acquire the language by reading annotated texts written by native speakers.

Erkan suggested to combine these projects with the IBC. What do you think? Answer here, I'll check by regularly.

Best wishes, Bitbert alias Florian
 * Those are right on target for Transwiki-versity, Bitbert! See also German to English and help write English to German, and the others. We could use your help at the Translation TaskForce! -- CQ 00:09, 15 April 2007 (UTC)

Wikimedia Commons, Transwiki and Interwiki linking
I've started a learning activity to help make better use of the Wikimedia Commons, while improving Multilingualism in general. Our Upload page here at the English Wikiversity will attempt to direct more files and images toward the Commons so that they can be shared by all languages and sisterprojects. I made sure that Wikiversity was represented a bit better at Category:CommonsRoot and Wikiversity pages there. As Bryan and I were updating CommonsRoot for the top-level categories we found these:

en:Category:Categories de:Kategorie:!Hauptkategorie es:Categoría:Categorías fr:Catégorie:Principale

With your tabbed browser please follow along to each of the top-level category pages:
 * en:Category:Categories
 * de:Kategorie:!Hauptkategorie
 * es:Categoría:Categorías
 * fr:Catégorie:Principale

I made sure that the top-level Category:Categories on all four Wikiversities were fully interlinked. Much more of this kind of work can be done to interlink equivilent pages across languages. To do this we should consider Multilingualism, Transwiki, and Interwiki linking at Meta. Using advice from there we move along...

Category:Transwiki is built on all four Wikiversities as a subcategory of Category:Wikiversity. So before we do that, we have to get the correct syntax for Category:Wikiversity. Follow along in your tabbed browser to:
 * This was confusing, since 'transwiki' is a well-defined notion across the projects, meaning to move something from one wiki to another.  I've moved the related pages to Multilingual communication and reclaimed the 'transwiki' template to flag pages that need to be transwiki'ed to another project. –SJ + > 01:10, 7 April 2010 (UTC)

en:Category:Wikiversity de:Kategorie:Wikiversity es:Categoría:Wikiveridad fr:Catégorie:Appareil:Racine

We wanna make sure these are individually placed in the respective Category:Categories and all interlinked via Interwiki linking, so, if it's not there or incomplete, we paste in the code:

en:Category:Wikiversity de:Kategorie:Wikiversity es:Categoría:Wikiveridad fr:Catégorie:Appareil:Racine

Next, we'll create a pseudo-namespace, Transwiki: by first giving it a category page with a link to a main Transwiki page. Transwiki is a language-neutral word, so the page title will be the same on all versions. The equivilents of Category:Transwiki all contain the code:

en:Transwiki - en:Category:Transwiki de:Transwiki - de:Kategorie:Transwiki es:Transwiki - es:Categoría:Transwiki fr:Transwiki - fr:Catégorie:Transwiki

en:Category:Transwiki de:Kategorie:Transwiki es:Categoría:Transwiki fr:Catégorie:Transwiki

These are individually placed in the respective Category:Wikiversity by a local participant and again all interlinked via interwiki linking per the advice from Meta-Help:Transwiki. Follow along in your tabbed browser to: en:Transwiki - en:Category:Transwiki de:Transwiki - de:Kategorie:Transwiki es:Transwiki - es:Categoría:Transwiki fr:Transwiki - fr:Catégorie:Transwiki

Next we build the main namespace Transwiki index pages using a similar method, moving down the Category tree:

Transwiki Transwiki Transwiki Transwiki Now we'll work on building the Template: objects, transwiki and interwiki in the Template: namespace on all four languages:

en:Template:Transwiki de::Transwiki es::Transwiki fr::Transwiki

...where the curly bracketed text is replaced with the appropriate syntax for Template. transwiki contains code something like: en:Transwiki - en:Category:Transwiki de:Transwiki - de:Kategorie:Transwiki es:Transwiki - es:Categoría:Transwiki fr:Transwiki - fr:Catégorie:Transwiki

Not real pretty (we can beautify it later), but it ubiquitously interlinks the other language Transwiki index pages, which dynamically track translation projects within the Transwiki: interlingual buffer zone.

Other namespace prefixes still need to be translated to build and expand transwiki and interwiki. Translation of Special:, Help:, User:, Portal:, School:, Topic:, etc. pages with some elementary translation and cultural appropriation as well as for main namespace articles will expedite cross-language content development.

We will also eventually do some work on beta.wikiversity.org once it gets into the interwiki map. We shall also help further the use of the Meta:Language select tool. People will be able to use their native language freely within the Transwiki:Namespace on all versions of Wikiversity. Hopefully this practice will propogate as our metacommunity expands to include an ever-growing array of languages and cultures. CQ 23:01, 14 April 2007 (UTC)
 * This was not being used, in addition to being confusing; since removed. –SJ + > 01:10, 7 April 2010 (UTC)

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: Wikiversity talk:Interlingual Beta Club


text:
Wikiversity talk:Essay Contests

Can you provide an example of what you expect as an essay? --JWSchmidt 02:03, 23 October 2006 (UTC)

IBC Essay Contest
The Interlingual Beta Club would like entries that answer the question: The winning entry will be used as the introduction to the Translator's Handbook. This essay should encourage, inspire, inform and motivate those who are, or wish to become translators at Wikiversity. Announce and post a link to your essay at Wikiversity talk:Interlingual Beta Club. Good Luck! CQ 15:46, 23 October 2006 (UTC)
 * Why is language translation important?
 * Maybe We could display the winner at the Community Portal or something as well.--Rayc 00:41, 24 October 2006 (UTC)

title: Wikiversity talk:Essay Contests


text:
Theory of Programming Languages

This is a core course in the Computer Science Core Courses

Introduction
Welcome to the course! Understanding the underlying logic behind programming languages is vital for comprehending Computer Science concepts - ranging from programming to systems design. This course is designed to acquaint you with the subject matter and give you a groundwork for further study.

Due to the open nature of Wikiversity you are free to browse through these courses at whatever pace you desire. However, before you begin this course you should consider reviewing the material covered in the perquisite courses (listed below) to ensure that you are prepared to learn this content.

In each lesson there is an objective at the top of the page, review these points and keep them in mind as you go through the lesson. At the end there is an assignment to test your understanding and further explain the material. Once you have finished the entire course you may move on to the next course in the computer science category.

(Note: Many of these lessons are stubs, and they need a lot of help. Please excuse the mess - and help out if you can!).

Prerequisites
''Prerequisites are courses it is suggested you understand before you attempt this course. If you're having a hard time understanding the material in this course, make sure you understand these prerequisites first.''
 * Introduction to Computer Science
 * Introductory Discrete Mathematics for Computer Science

Lessons

 * 1) Introduction to Theory of Programming Languages
 * 2) General Syntactic Structure
 * 3) Imperative Programming
 * 4) Static Programs
 * 5) Flow Control in Programming
 * 6) Object Oriented Programming
 * 7) Functional Programming
 * 8) Logic Programming
 * 9) Conclusion

Textbooks

 * Programming Languages Via Wikibooks.

Next Course
Introduction to Theory of Computation

Active Participants
Despite the best efforts of the authors, the material in this course is imperfect. If you have a question or otherwise need help with this course, please post on the Help Page.

You may also contact those involved with developing this course below. When new active participants sign in please use 4 tildes (~) to correctly display the username. We also encourage you to join as an instructor. If you can't teach the course anymore, please remove your name from the list of active participants.
 * Azotochtli (talk) 20:44, 28 July 2012 (UTC)

Related Wikiversity resources

 * Discrete Mathematics for Computer Science
 * Introduction to Computer Science
 * Introduction to Information Technology – needs work. Will you help out?

title: Theory of Programming Languages


text: File:Straightbevelgears.jpg

title: File:Straightbevelgears.jpg


text:
Talk:Quenya

Introduction to Quenya
Consider having multiple Quenya courses (part of the Elvish Stream, perhaps), and turning this into "Introduction to Quenya" or "Basic Quenya" or "Beginning Quenya". The Jade Knight 05:01, 23 October 2006 (UTC)

 * Are you interested in this learning Project? Enroll you!

 * It wasn't my original idea because Quenya cannot be understood or learned as a normal language. Quenya is a language we have no (or very few) extensive grammar description, but only notes and a corpus. The most of Quenya Grammar is infered, supposed. In my opinion is not possible to understood Quenya if a learner doesn't have any idea of why we use, for exemple, -mmë as 1st pl. exclusive even if there's a text that explicitly say that it is 1st dual inclusive. Or if he doesn't know anything about Qenya. Quenya is a languiage that has continuosly evolved since 1914/1915 to Tolkien's death (1973).

 * However I understood that some people may prefer only know the basic grammar in order to be able to write simple sentence in that language. For this reason every lesson will be divided in two parts "Basic" and "Advanced", so that a learner may be able to choose if he wants to procede to the next topic, or knowing only the basic.

 * Or may be dividing this in two parts Quenya I and Quenya II. That is the same of making an "Introduction to Quenya"....

 * Or, at least, these are my ideas. However I can change it ;-)

 * Other courses in the future will be about the External Evolution of Quenya (from the Qenya of the Qenyaqetsa) and maybe, always about quenya, lectures on the Corpus. --Elistir 15:21, 23 October 2006 (UTC)

 * I don't entirely understand what your point is in your 2nd paragraph. How does that relate to my suggestion?

 * What is the difference between "basic" and "advanced" options? The Jade Knight 18:55, 26 October 2006 (UTC)

There is also a Wikijunior article on Quenya: Wikijunior Languages/Quenya. Also, I've added a few links around to other things on Wikibooks. The Jade Knight 18:55, 26 October 2006 (UTC)

title: Talk:Quenya


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Introduction to psychology/Methodology and Statistics

Gossip and rumours will often be used describe someone's behavior. They aren't acceptable to psychologists because psychologists because they require more reliable measures and accurate reports, their methods are established to meet those requirements. This lecture describes those methods and the statistics used to report, analyze and interperet this data.

Experimental method
Considered the most disciplined method. Using this method, an experimentor manipulates a variable to be studied, chooses the response to be measured, and controls exraneous influences that might inappropriately affect the results of the experiment. A variable is a characteristic of anything that can have two or more values.

Case study method
Using this method, a single participant is studied to further detail than the experimental method. While the data collected is more detailed and is relevent to the participant, generalising the data to a larger group of people is generally not possible. Examples of uses for case studies are for cognitive research with someone with brain damage, whose condition is known yet unique or for treatment of mental problems such as phobias.


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Talk:Filmmaking Basics/Thumbnail Storyboard/Step by Step/aa

I think this article lacks the basic info whats it about.--80.221.27.231 06:50, 23 October 2006 (UTC)


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Root Finding in one Dimension

Summary
This course belongs to the track Numerical Algorithms in the Department of Scientific Computing in the School of Computer Science.

In this course, students will learn how to solve problems of the type $$f(x)=0\,\;$$ numerically. Convergence rates, termination criteria and implementation details are discussed.

Introduction

 * Why do we want to solve $$f(x)=0\,\;$$?
 * Why do we want to solve it numerically?
 * Formal definition of the problem.
 * Maybe a bit of history?

Binomial Search

 * Derivation
 * The Algorithm
 * Convergence

Secant Method

 * Derivation
 * The Algorithm
 * Convergence
 * Iterative form

Iterative Methods

 * $$x_{n+1} = F(x_n)\,\;$$
 * Convergence rates

Newton's Method

 * Derivation
 * The Algorithm
 * Convergence

Halley's Method

 * Derivation
 * The Algorithm
 * Convergence
 * Generalization

title: Root Finding in one Dimension


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Filmmaking Basics/Thumbnail Storyboard/Examples/Example 4

{| cellpadding="10" cellspacing="5" style="width: 99%; background-color: inherit; margin-left: auto; margin-right: auto"
 * style="background-color: BlanchedAlmond; border: 1px solid #777777; vertical-align: top; -moz-border-radius-topleft: 8px; -moz-border-radius-bottomleft: 8px; -moz-border-radius-topright: 8px; -moz-border-radius-bottomright: 8px; height: 200px;"|

This is an example Thumbnail Storyboard

 * Start with a close-up of the poster
 * In this example, we start with a side view. In this view we see the two people looking at something on the wall.  Then we look at what they are looking at which is the movie poster.

 * In FrameFrge 3D Studio, I represent the poster by creating a window and putting a wall behind it. This looks like this. (below)

 * style="width: 370px; background-color: #ffffdd; border: 1px solid #777777; vertical-align: top; -moz-border-radius-topleft: 8px; -moz-border-radius-bottomleft: 8px; -moz-border-radius-topright: 8px; -moz-border-radius-bottomright: 8px;" rowspan="3" |

Thumbnail storyboard for Seduced by the Dark Side!
EXTERIOR - The local movie theater - NIGHT

Fade In Cut To   Dolly To

(1) The Young Person and Old Person stand looking at the movie poster outside the theater.

 * I want to get the attention of the audience so I immediately show the poster. Then I quickly cut to the young person and dolly out to see the old person as well.  All this time, the Star War's theme is playing.  By starting with the poster, I can have much longer Star War's music.  Then the music cuts to total silence and there is an awkward pause with just street noise.

(2) Young Person: "That was a great movie..."

 * I want the movie to start very slowly. Therefore, the two actors will just stand there barely moving while the camera is static.

(3) Young Person (contined): "but I do not understand one thing."

(4) Old Person: "What's that?"

Cut To

(5) Young Person: "How can anyone be seduced by the Dark Side?"

 * Once the young person says this, I want a cord from the Star Wars music to play faintly in the background while the man thinks.

Cut To

(6) The old person thinks for a while.

(7) Old Person: "What computer do you have at home?"

Cut To

(8) Young Person (eagerly): "A Macintosh!"

-

Cut To

(9) Old Person: "But what computer does your father use at work?"

Cut To

(10) The young person thinks for a moment.

(11) Young Person (amazed and excited): "Seduced by the Dark Side!"

Cut To

(12) The Old Person smiles.

Cut To Zoom out

(13) Old Person and the Young Person walk toward home together.

(14) Fade to Black.

The End

Point Of Reference:
This scene will be filmed Inside the line. (Next to the poster = In the green area). Therefore, the camera will never cross the line. The Floor Plan for the Movie
 * }
 * }
 * }

{| cellpadding="10" cellspacing="5" style="width: 99%; background-color: inherit; margin-left: auto; margin-right: auto"
 * style="width: 50%; background-color: Cornsilk; border: 1px solid #777777; -moz-border-radius-topleft: 8px; -moz-border-radius-bottomleft: 8px; -moz-border-radius-topright: 8px; -moz-border-radius-bottomright: 8px;" ,!--rowspan="2"--> |

The Next Page [[Image:Crystal Clear action loopnone.png|32px]]

 * Look at the other examples by going to the index at the top of this page.

 * Or continue this lesson at What software for thumbnail storyboards? to learn how to get started storyboarding.

 * }


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Coastal Engineering

Wikiversity Department of Marine Engineering

Content summary
The course will deal with basic Coastal Engineering concepts such as water waves, their propagation and transformation, statistical representation of the sea state, tides and currents, sediment transport, coastal processes and beach dynamics, coastal structures, wave-structure interaction, environmental issues near coastal zones.

Goals
To help the reader to appreciate Coastal Engineering methods with a firm understanding of the underlying theoretical principles.

Learning materials
Learning materials and learning projects are located in the main Wikiversity namespace. Simply make a link to the name of the lesson (lessons are independent pages in the main namespace) and start writing!

You should also read about the Learning model. Lessons should center on learning activities for Wikiversity participants. Learning materials and learning projects can be used by multiple projects. Cooperate with other departments that use the same learning resource.

Texts

 * Ocean Surface Waves: Their Physics and Prediction (2nd Edition) by Massel Stanislaw Ryszard, Inst of Oceanology of the Polish Academy of Sciences, Sopot, Poland. (ISBN 978-9810-2-1686-3 (hardcover), 978-9810-2-2109-6 (paperback)).
 * Coastal Dynamics by Willem T. Bakker, Delft Hydraulics, Netherlands. (ISBN 978-9812-7-0373-6)
 * Random Seas and Design of Maritime Structures (3rd Edition) by Yoshimi Goda. (ISBN 978-9814-2-8239-0 (hardcover), 978-9814-2-8240-6 (paperback))

Lessons
a) Waves in the Ocean and their Significance           a) Interaction of Wind and Ocean Waves a) Refer to text - Tsunami: To Survive from Tsunami (published by World Scientific, ISBN 9789814277471 (hardcover))
 * Lesson 1: /Water Wave Theories/
 * Lesson 2: Wave Transformation
 * Lesson 3: Wave Pressure and Forces
 * Lesson 4: Wave-Structure Interaction
 * Lesson 5: Currents
 * Lesson 6: Wave-Current Interaction
 * Lesson 7: Tides
 * Lesson 8: Solitary Waves
 * Lesson 9: Tidal Inlets
 * Lesson 10: Basin Circulation
 * Lesson 11: Rubble-Mound Breakwaters
 * Lesson 12: Submerged Breakwaters
 * Lesson 13: Groynes
 * Lesson 14: Detached Breakwater
 * Lesson 15: Sand Nourishment
 * Lesson 16: Assessing Coastal Management Techniques
 * Lesson 17: Revetment
 * Lesson 18: Vertical Breakwaters
 * Lesson 19: Wave-Foundation Interaction
 * Lesson 20: Sediment Transport
 * Lesson 21: Wave Spectral Analysis
 * Lesson 22: Construction of Coastal Defenses
 * Lesson 23: Storm Surge
 * Lesson 24: Tsunami
 * Lesson 25: Wave Maker Theories
 * Lesson 26: Physical Modeling
 * Lesson 27: Numerical Modeling
 * Lesson 28: EIA for Coastal Engineering Projects

Activities

 * Plan out a Breakwater using the proper materials
 * Breakwaters are often build using 1/6T rocks and cobbled with No. 3 (smaller size) (See State Stds. Sect. 72)
 * Implement a 3D Computer Model visualization of a section of Coastline near you
 * Demonstrate the effects of sea level rise with visualization tools (Modelling sea level rise)
 * Activity 1.
 * etc.

Readings
Each activity has a suggested associated background reading selection.
 * Reading 1.
 * Study guide:
 * Wikipedia article: __Article Name__
 * etc.

Active participants
Active participants in this Learning Group

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Games in Development/Liberal Diplomacy

Introduction
These are a set of rules in development for a variant of Diplomacy that is slightly less in the Realist camp of International Relations and more firmly entrenched in the Liberal school of thought. By way of introduction - and as a chance for a pithy commentary about the ongoing state of disagreement between these two philosophies - I'd just like to say that Diplomacy, at its very core, is zero-sum and cutthroat. The game is about winning, and winning means being the girl (or guy) with the most resource centres at the end of the game. This means that, while you might slow your expansion, cooperate with others, or engage in fruitful intelligence sharing, you have no intention of long-term partnership; on the contrary, partnership in Diplomacy (the game) is strictly for the purposes of short-term gain. Self-interest still overrides the impulse to cooperate long-term. It is thus an excellent example of the Realist school of International Relations. Painfully, however, the game does not take economics into account. To be more precise, the kind of economics the game takes into account are protectionist economics, meaning the international economy can effectively be factored out of game-play altogether without much loss of realism (no capital R!). It is precisely this factor that is the cause for a loss of the interest in medium to long-term cooperation, and precisely this factor that I wish to remedy with the creation of a more Liberal-friendly Diplomacy.

The Phases of Development
This game development is being used as an example of the Spiral Method of game development. It's also an exploration of the Spiral Method, as I've never tried the idea before in a reasonably rigourous context. Below are listed the phases of development for those who are following this game for the purposes of studying the Spiral Method.
 * Phase 1: The Initial Idea - where did this hare-brained scheme come from in the first place?
 * Phase 2: The Essentials - the first phase of the Spiral Method is the development and testing of the first fundamental principles of your project.
 * Phase 3: The Board - Once the basics are ironed out, start adding bits incrementally!
 * Phase 4: ...

The Game
If all you really wanted to know about was the rules for the variant, look no further! They will appear here when they are done!

title: Games in Development/Liberal Diplomacy


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Game Creation Guidelines/Spiral Model of Game Development

Introduction
The Spiral Model of Game Development is the extraction of the Spiral Model proper for use in Game Development. This part of the Game Design Project looks at exploration of the Spiral Method as a means to game development, and asks the question: when should I employ the Spiral Method in developing my games?

The Spiral Model
The Spiral Model is an iterative development method. Iteration means the steps are performed over and over again. This means the project is conceived, designed, prototyped, tested, and the test results are put into the next iteration of the same steps. The Spiral Model is thus an evolutionary process.

The design process starts in the centre of the spiral with an idea. It proceeds outward clockwise through each of the five phases of design. Every return of the spiral to the "define" position starts a new iteration. Each iteration produces a deliverable or prototype, and each prototype is closer and closer to the final production model in complexity and degree of completion. The process begins when you have an idea for a game. First, you:
 * 1) define - define the new idea, make an outline, and hash out the basics of your design.
 * 2) design - get down to work writing the rules for the core mechanic, make the basics workable.
 * 3) prototype - build a working model, start to get the look and feel of the physical features of the game.
 * 4) playtest - you can do a solo playtest, an internal playtest, or a blind playtest.
 * 5) feedback - gather, collate, and synthesize your feedback.
 * 6) redefine - go back to the drawing board with what you learned and change your outline...

A major theme of the Spiral Model in software development and defence appropriations is Risk Management. The risks of game development, however, are few. The main risk to be avoided is wasting your time on a flawed design. The Spiral Model forces you to produce an early proof of concept, and if you've got a strong theme and weak mechanic, it will show readily. In this way, the Risk Management is subsumed by definition: if, after testing, the prototype was found to be unworkable, you don't have to go any further, but you can back pocket what was useful and hopefully use it again someday.

Commentary
Be bold and tell us what you think about the Spiral Model!

Exploration of the Spiral Model
A place for articles, songs, poems, diagrams, and games about and created by the Spiral Model.
 * Liberal Diplomacy - dnjkirk experiments with the Spiral Model to produce a Diplomacy variant!


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Category:Wikiversity Essay Contests

This category is for new and archived Essay Contests. See Essay Contest for details on how to list and conduct a new contest.

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Category:Interlingual Beta Club

Project Page: Interlingual Beta Club

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Pillars of Game Development

Part of Board Game Design

Introduction
These are considered to be the essentials of board game design.

The Pillars

 * /Parsimony/ - a game should be no more complex than it has to be

 * /Excitement/ - there should be some inherent interest and excitement throughout the game

 * /Theme-Mechanic Balance/ - the mechanic and theme should work together harmoniously

 * /Perfect Potential/ - at the start, any player should be able to win the game

 * /Simplicity/ - while the concept can be complex, the language of the rules should be very simple and straightforward

 * /Replayability/ - players should not experience the same game twice

 * /Beauty/ - a finished game should have a good look and feel

 * Much of a game lies in its beauty. Playing a game is an aesthetic experience - just like art, even if different - and it is propelled by our desire of beauty, expressed in the form of fun.

 * The "toys" should be therefore nice and adequate to the theme: we all know the difference between playing with plastic vs. metal car models or plastic vs. tissue dolls.

 * /Player Control/ - chance should only be used where it adds to the game

title: Pillars of Game Development


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Pillars of Game Development/Parsimony

Part of Board Game Design>Pillars of Game Development

Parsimony in Game Development
Parsimony is the concept of doing only what is necessary to achieve the desired effect. Through the process of playtesting, refining, and tightening your game design, you hopefully achieve parsimony that makes it easier to understand and enjoy the central theme and mechanics of your game.

title: Pillars of Game Development/Parsimony


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Games in Development/Liberal Diplomacy/Idea

The idea for this concept was originally floated by me after a particularly rousing game of Diplomacy at the conclusion of a graduate level Strategic Studies course. The basic concept is that Armies and Navies in Diplomacy should not be thought to represent concrete military forces, but instead, the capacity of a nation to undertake national policy. They could be thought of as a fundamental representation of GNP. While this can express itself as military force, it does not have to do so. Certainly, during the late nineteenth centry, the bulk of a nation's money was spent on the military, and this is in part due to the necessity for militaries, the fact that the social safety net (and other major areas of modern national expenditure) was as of yet not fully developed, and that the revenue base of most economies depended on strong economic chokepoints (tariffs and the like) rather than the difficult to administer income tax we have today. Additionally, while the nations of Europe had very strong regular military forces, a large bulk of their force was formed up of conscripts. This meant that the standing army was but a partial expression of their full military force, and the active military could be expanded and contracted as needed (though WWI proved that contraction is sometimes harder than expansion). This is all a gross simplification, but one can see where this idea is going (and games of this nature are gross simplifications in any case). Those little stars on the Diplomacy board are no longer fighting men per se, but an expression of the nation's power to put people in uniforms on the march. Soldiers can even be trained and ready for battle, and the nation not have enough financial, fuel, material, etc. resources to put them into action. The little stars on the board are therefore also expressions of the nation's ability to invest in infrastructure, foster industrial growth, and prime the proverbial Keynesian Pump. How, then, do we represent economies in a parsimonious way on the board such that gameplay is not negatively impacted and we achieve our ends of Liberal Diplomacy? Well, that's what this Spiral Model experience is all about, but I am going to start out with some unpolished ideas:
 * Pieces as an expression of capacity to make policy - I think we discussed this enough above
 * Trade - Both international and intranational trade should be part of this game. Trade creates a win-win situation that makes it useful to cooperate. I intend for trade to only occur between production centres, which means that a major rule of diplomacy will be broken: one centre, one unit. I want trade to be delicate, something that requires continued dedication to cooperation. I want it to walk the fine balance of being annoying to create and maintain, but with just an adequate payoff to compensate. If possible, I want to refine a way to make trade possibly more beneficial to one player than another. Trade also gives us the grand opportunity of outside interference in perfectly peaceful trade. Shipping lines can be raided, rail lines cut. You know, the general havoc that ensues when armies are set to marching.
 * Hinterland - It makes sense that, since one centre may have the ability to produce and support more than one unit, there should be a limitation to expansion. It may also be useful if this limit to expansion also put a check on cooperation, making this still a competitive variant. I think that the use of hinterland (you know, those empty spaces on your Diplomacy board - the ones you thought were only good for moving through?) would do both. Only playtesting will tell, but the concept of needing one "territory" of hinterland for every unit over one you produce in a single centre does a couple things. Not only does it put a check on maximum expansion of individual centres, but it gives particularly strong centres Achilles' Heels: enemy occupation of a hinterland hinders that centre's production.

So, we have a general concept, an idea that creates an advantage to cooperation, and something that makes cooperation at the same time more troublesome and potentially dangerous. We should move on to the next phase of development before the idea has time to cool down!


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Games in Development/Liberal Diplomacy/Essentials

The next step! So, it's clear what the three concepts are that I want to add. What has to be decided now is how I'm going to make the first prototype of the game. The Spiral Method demands numerous prototypes and repeated testing, so I need to decide on what the kernel of this game is and test that first. Luckily, doing a variant on such a well-established (and venerable) game, the basic rules are firmly established and have been playtested over decades. However, given the changes I want to make, I am going to have to decide whether I want to take all of the game or just some of it for the basis of this variant.

Movement: So far as I am concerned, the elegant movement and orders system of Diplomacy is what sets it apart from other strategy games. These simple instructions should form the solid core of my bare essentials. So, I want to include the basic orders Move, Stand, Support, and Convoy in this first prototype. For those unfamiliar with these rules, they are available from the owners here.

Orders: Diplomacy's system of giving orders on slips of paper and resolving movement simultaneously is essential to the operation of this game.

Turns: The seasons of Spring and Fall give a great deal of tension to the game, as waiting for one's builds is something that gets players chomping at the bit for Fall to come around. Spring and Fall seasons are a good part of the game to maintain, and the year can start at 1890.

Builds: Where I may begin to deviate from the game is that - though I believe in building being somehow connected to centres - I don't know how to resolve my "stronger centres" problem. I want to keep builds in the Fall season, but I realize that some players may have more than one build per centre in that turn, and that may create problems.

So, where does that leave us?

Well, we can briefly sum up the kernel of rules I want to port over from Diplomacy proper. They are:  Rules

Stuff!


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User:Sanbeiji~enwikiversity

http://sanbeiji.com/

title: User:Sanbeiji~enwikiversity


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Atomic structure

Atomic theory
An Atom is a small part of an element that takes part in chemical reactions. It is made up of three subatomic structures called Protons, Neutrons, and Electrons. Subatomic structures: __________________________________     Particle:               Charge:              Mass: Proton                    +1                1 *u Neutron                    0                1 *u Electron                  -1              1 / 1836*u Positron                  +1. 1 / 1836*u The Nucleus, in the center of the atom, consists of protons and neutrons. Orbiting around the nucleus are the electrons.

Atomic Structure
The nucleus, in the center of an atom, consists of protons and neutrons. Orbiting around the nucleus are the electrons. Each unique element has an Atomic Number equal to the number of protons it contains. There are 94 naturally occurring elements (1-94) and others which have been artificially created (95+..) Each element has an Atomic Weight for the most commonly found isotope. Atomic Weight = number of protons + number of neutrons; see: The Periodic table. In a stable uncharged atom the number of electrons will equal the number of protons. If the number of electrons is changed the atom will become ionized and gain either a positive (fewer electrons) or negative (greater electrons) charge.

Isotopes
The same element can exist in different forms, each form having the same atomic number, but different mass numbers. These forms are called isotopes. Isotopes that cannot decay during a defined period are called stable isotopes. And isotopes that can decay during a defined period are called unstable (or radioactive) isotopes. For example : 1              2                        3            1H             1H                       1H Protium. Deuterium. Tritium.

Tritium is an unstable isotope of hydrogen.

In accordance with the Bohr Model, electrons are considered to move around the nucleus in fixed shells (orbits), at various energy levels. These levels may be designated K L M N shells (or 1 2 3 4 orbits). The first level contains only 2 electrons. The second level can hold 6 electrons. The number of maximum electrons that can occupy one shell is defined by the formula of 2nî or 2n square, where n is the number of the shell.

When the electrons are excited, they can transfer between the shells. As we move away from the nucleus, the energy levels increase. Electrons have their own energy and the energy increases with increasing the n value or orbit.

Excited state of atom
The configuration of electrons occupying the least amount of space (in the Bohr model) is called the ground state. But when electrons are excited (by getting electricity, heat), they jump to a higher level.

This condition of the atom is called an excited state. When the electrons return to the ground state they give off energy.

Levels and sublevels
All energy levels contain sublevels known as s p  d  f.

S sub level can contain 2 electrons. (One pair.)

P can contain 6 electrons. (Three pairs.)

D can contain 10 electrons. (Five pairs.)

F can contain 14 electrons. (Seven pairs.)

The first shell has only the sublevel s and therefore has only 2 electrons The second shell has both the sublevel s & p and can hold 8 electrons The third shell has the sublevel s,p & d and can hold 18 electrons The fourth and the last shell has the sublevel s,p,d & f and can hold 32 electrons.

Orbital

 * The regions around a nucleus where the probability of finding an electron of a particular energy level is highest are called orbitals.
 * An Orbital can hold only two electrons. They are spinning opposite ways. They are called orbital pairs. 'n' represents principal quantum number or simply the number of the shell. So nth shell contains n^2 number of orbitals hence 2*n^2 number of electrons.
 * The shape of orbital depends on the sublevel.

Valence

 * Valence electrons revolve in valence shells.
 * Electrons that can enter into a reaction are only at the last level.
 * These electrons are called valence electrons. The maximum number

of valence electrons is 8. The Valence determines how many electrons the atom has to borrow or lend. All parts of atoms except the last orbit are called a kernel. Examples:. .                 . N. The dotted formula of the nitrogen. .
 * The electron dot formula represents the valence electrons.

Ionization energy
Ionization energy is the amount of energy needed to remove or add an electron from a gaseous atom or ion. Ionization energy depends on the number of protons in the nucleus and the shielding (screening) of the inner electrons.

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Radioactivity

Radioactivity
The nuclei of some atoms spontaneously disintegrate from one form of isotope to another until they reach a stable form. These atoms emit particles (alpha & beta) & photons (gamma rays) which are different in charge, size, penetrating power and ionization energy.

Half life of the isotope
The half - life of an isotope is the time needed to decay until half of it's mass remains. Here is an example. 50 grams of the radioactive isotope Carbon 14 with a half-life of 5,730 years after 5,730 years, 25 grams will remain. After another 5,730 years only 12.5 grams will remain and so on. When a radioactive isotope completely decays into a daughter isotope, it may decay into another isotope, or remain the same, depending on whether it is stable or radioactive.

Types of decay
There are three main types of radioactive decay; these include Alpha, Beta, & Gamma Radiation. Alpha and Beta decay are released in particles, while Gamma radiation is released in rays.

Gamma radiation is more penetrating than alpha & beta. An alpha particle can be stopped by a thin piece of paper and a beta particle can be stopped by a sheet of aluminium foil Gamma radiation can penetrate both with ease. The most efficient way to stop gamma rays is with and apron of lead (hence the wearing of a lead covering when you get a dental X-Ray). Here are some common radiation emitters: Americium-241
 * Alpha

Radon Strontium-90 Uranium-238
 * Beta
 * Gamma

Example of alpha decay

 * $${}^{226}_{88}Ra$$
 * $${}^{222}_{86}Rn$$
 * $${}^4_2He$$

Additional resources

 * Isotope lists, 97+

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User:Dfrauzel

Interested in contributing to topics on Networking and Computer Science in general.

Articles I am contributing to / watching

 * Topic:Networking
 * Topic:Networking_Intro
 * Networking_Intro/About_this_course

Articles I am drafting

 * User:Dfrauzel/Networking_Intro

Useful links

 * Editing Help
 * Sandbox
 * Computer Network
 * Web_Design/Emerging_Technologies_Research_Activities
 * Examples

title: User:Dfrauzel


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Bonding and chemical structure

Chemical Bonding
The force that holds two or more atoms together is called a chemical bond. The process by which bonds are formed is called chemical bonding. When a bond is formed, a chemical reaction takes place. The result of a reaction is the formation of two or more substances.

Valence electrons
Chemical bonds are formed by sharing or transferring electrons. In general, most main group elements react in order to achieve a full valence shell. Elements in Group 18 (sometimes referred to as the noble gases) will usually not react, since their valence shell is already full.
 * The highest principal shell of an atom, in which there is at least one electron, is called the valence shell.
 * The electrons on the valence shell are called valence electrons.
 * Main group elements can hold a maximum of eight electrons in their valence shell. A full valence shell is known as an "octet".

Ionic bonding
Ionic (or electrovalent) bonding is the process by which electrons can transfer between valence shells of atoms. Since electrons are negatively charged, the loss or gain of an electron leads to charged atoms, called "ions".
 * A cation is a positively charged ion. It is formed when an atom of neutral charge loses one or more electrons.
 * An anion is a negatively charged ion. It is formed when an atom of neutral charge gains one or more electrons.
 * The amount of energy that is needed to remove the most loosely bound electron from a neutral atom in the gas phase is called the First Ionization Energy. The amount of energy needed to remove the second electron is called the Second Ionization Energy.  The amount of energy needed to remove the third electron is called the Third Ionization Energy.

Covalent bonding
One rule for predicting when an ionic bond will take place is when the difference between electronegativities is 1.7 or greater. In other cases, atoms bond by sharing electrons on the valence shells. The force that holds two atoms together in this case is called a covalent bond. A covalent bond can be described as the mutual attraction that positive nuclei have for the shared, negatively charged bonding electrons. The process, by which electrons are sharing is called covalent bonding.  The group of atoms held together by covalent bonds is called a molecule.
 * The substances that are held by covalent bonds are molecular substances.
 * Substances that are held by ionic bonds are ionic substances.

Diatomic molecules

 * Molecules that consist of two atoms shared covalently, such us Cl2, H2 (1e), F2, O2, N2, etc.
 * Covalent bonding may be presented in three ways:
 * 1. Nonpolar. The difference between electronegativities equal 0.
 * 2. Polar. The difference between electronegativities not equal 0.
 * 3. Coordinate. When a lone pair of electrons is shared.

Ionic substances

 * 1. Have a high melting point.
 * 2. Good conductors of heat and electricity when melted or dissolved.
 * 3. Ionic substances readily dissolve in water to form neutral solutions.

Molecular substances
Examples: H2O, NH3,  C6H12O6.
 * 1. They are soft.
 * 2. They are poor conductors of heat and electricity.
 * 3. They have a low melting point.

Network solids
Examples: diamond, graphite, SiC, SiO2. (They have 4 valence electrons). i
 * 1. They are hard.
 * 2. Poor conductors of heat and electricity.
 * 3. Good insulators.
 * 4. Very high melting point.

title: Bonding and chemical structure


text:
Computer Architecture Lab

This course is a hands-on introduction into computer architecture. The main target is to build a simple, pipelined microprocessor and run it in an FPGA. This course is associated with a real course at the Technical University of Denmark.

Martin Schoeberl

The Challenge
In this course you will design and develop extensions to the T-CREST time-predictable multicore processor and implement it in an FPGA.

The Rules
There are only two rules for your design:

 * 1) The design has to be pipelined
 * 2) The design has to run in an FPGA

Everything else is up to you. Be creative!

Additional Pages

 * 1) Projects
 * 2) Spring 2022
 * 3) Patmos at GitHub

Older Pages

 * 1) /FPGA Hello World Example/
 * 2) /HOWTO/
 * 3) /Processor Project/

Grading
The lab work and the project are part of the final grade.

Following points are given for individual parts:

 * Instruction Set (RISC-V and comparison): 20 points
 * FPGA Design Flow: 5 points
 * Chisel UART example: 5 points
 * Project design and implementation: 50 points
 * Project documentation (academic research paper style, maximum 8 pages): 20 points

Assignments
Several assignments will help you to get started. We will start on a weekly basis and loosen it up at the end when the main activity is your project.

As a first action add a template for your project and your name at the  Student page.

Week 1-2: Instruction Set Comparison

 * Describe the RISC-V, Patmos, and a third processor's instruction set (summary)
 * Compare these three ISAs against each other
 * About 2-3 pages A4
 * Deadline: Su 20/2/2022 @23:59

Week 1: FPGA Design Flow
To get started using an FPGA start with following small projects:

A Simple Blinking LED

Use the Chisel examples repository and the flow as described in the Chisel slides:

 * https://github.com/schoeberl/chisel-examples
 * https://github.com/schoeberl/chisel-book/wiki

The FPGA Hello World Example describes the FPGA design flow with Quartus.

Week 2: Combinational Circuits in Chisel (Simulation)
We adapt the lab for the remote/home office learning

 * Lab 2 from the Chisel lab: https://github.com/schoeberl/chisel-lab/tree/master/lab2

Week 2: UART in Chisel (FPGA)
UART Output

A UART will enable you to communicate between a PC and your processor. Therefore, this is our first real Chisel/VHDL example. For this experiment, connect a serial cable between the FPGA board and the serial port on your PC. Start a terminal program (gtkterm on Linux or Hyperterm on Windows) with baud rate 115200 and no handshake.

Extend the blinking LED example with a UART and write 0 and 1 to the serial line when the LED is off and on.

The Chisel code for the UART transmit is available as part of the Chisel examples at To simplify your design use an additional buffer as shown in the Sender example:

The VHDL code for a UART is available here: sc_uart.vhd and fifo.vhd. The UART is connected via the SimpCon interface.

With the slow output of characters (two per second) you can just write the data to the UART transmit register.

Extend the example by writing repeated numbers 0-9 as fast as the baud rate allows. In this case you have to extend your state machine to poll the UART status to check if the transmit buffer is free.

UART Input (optional)

Implement a state machine that receives characters from the UART. Switch the LED on and off with two different commands received on the serial line.

ModelSim UART print out (optional, not with Chisel)

There is a faster simulation version of the UART available that prints the output to the ModelSim console: sim_sc_uart.vhd.

Having mastered this UART examples gives you a great tool to debug your processor design. The UART output will probably be the only way to communicate with your processor.

For further tips see /HOWTO/.

Week 3: Chisel Exercises (Simulation)
Exercises from Chisel lab3: https://github.com/schoeberl/chisel-lab/tree/master/lab3

Week 3: Chisel Exercises (FPGA)
Continue with Chisel exercises (UART, ALU example, project from scratch)

Week 4: Chisel Testing
Exercises from the Verify lab: https://github.com/chiselverify/class2020/tree/master/lab1 and https://github.com/chiselverify/class2020/tree/master/lab2

Week 5: Patmos Exercise
Explore Patmos with the provided VM.

Exercise document: Getting Started with Patmos section in the Patmos Reference Handbook

Week 7: Present Project Idea
A brief presentation of your project idea and the plan how to execute the idea.

Documentation
A conference-style paper on their project, two-column format, maximum of 8 pages

Demonstration
You will present your initial project idea at the project start and the finished project in the last week (presentation and demonstration).

Hardware
To implement your design you can use any decent FPGA board. A serial interface (UART) will help for debugging. If you need more memory than the few KB on-chip the board should contain memory chips connected to the FPGA. I suggest using a board with SRAMs as they are easy to connect to the processor.

Students Katleho
Add yourself to this list for this semester. It is strongly suggested for the students from DTU.

Spring 2022

The former student pages:

Spring 2021

Winter 2020

Spring 2020

Spring 2019

Spring 2018

Spring 2017

Spring 2016

Spring 2015

Spring 2014

Spring 2013

Spring 2012

Spring 2011

Winter 2008

Winter 2007

Winter 2006

Summer 2006

TO DO
a short list of open issues:

 * nothing open at the moment

title: Computer Architecture Lab


text:
Computer Architecture Lab/FPGA Hello World Example

When one starts to use a new language or environment the first program written is usually the famous 'Hello World' example. What is the 'Hello World' program in hardware, in an FPGA? The smallest project that produces dynamic output is a blinking LED. We will show the steps for a blinking LED example using Altera/Intel's Quartus and an FPGA board.

Design Flow
All your design files (VHDL and/or Verilog files) make up a project in Quartus. A Quartus II project is defined in Quartus II with just three files: projectname.qpf, projectname.qsf , and projectname.cdf (Close your Quartus II project before editing the files).

Create a New Project
Start Quartus II and create a new project with:

 * 1) File -- New Project Wizard...
 * 2) Select a project directory and select a project name. The project name is usually the name of the top-level design entity. In our case hello_world (make sure to name the project this exactly, or you will have compilation problems).
 * 3) In the next dialog box the VHDL source files can be added to the project. As we have no VHDL files at the moment we will skip this step
 * 4) We have to select the target device. Choose the right family and device depending on your board.
 * 5) We leave the EDA tools settings blank
 * 6) Press Finish at the summary window

Device and Pin Options
At the default setting the unused pins drive ground. As the default settings in Quartus II for a device are dangerous we specify more details for our target device:

 * 1) Assignments -- Device to open the device properties
 * 2) Press the button Device & Pin Options...
 * 3) Important! At the tab Unused Pins select As input tri-stated.
 * 4) The LVCMOS, selected in tab Voltage, is the better IO standard to interface e.g. SRAM devices
 * 5) Close the dialog box and the next with OK

Hello World in Chisel
To get started with Chisel there is a Hello World example in Chisel available at: Chisel Hello World

The following code shows the Hello World hardware in Chisel.

import Chisel._

/** * The blinking LED component. */

class Hello extends Module { val io = new Bundle { val led = UInt(OUTPUT, 1) } val CNT_MAX = UInt(50000000 / 2 - 1);

val cntReg = Reg(init = UInt(0, 32)) val blkReg = Reg(init = UInt(0, 1))

cntReg := cntReg + UInt(1) when(cntReg === CNT_MAX) { cntReg := UInt(0) blkReg := ~blkReg } io.led := blkReg }

/** * An object containing a main to invoke chiselMain * to generate the Verilog code. */ object Hello { def main(args: Array[String]): Unit = { chiselMain(Array("--backend", "v"), => Module(new Hello)) } }

Compile and generate the Verilog hardware description with a simple

make

For FPGA synthesize you can either use your project you setup before or the Quartus project that is part of the Chisel hello world repository.

The Hello World VHDL Example
Add a VHDL file to the project with File -- New... and select VHDL File. Enter the following code and save the file with filename hello_world.

--   --  hello_world.vhd --   --  The 'Hello World' example for FPGA programming. --   --  Author: Martin Schoeberl (martin@jopdesign.com) --   --  2006-08-04  created --

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity hello_world is

port (       clk     : in std_logic;        led     : out std_logic    ); end hello_world;

architecture rtl of hello_world is

constant CLK_FREQ : integer := 20000000; constant BLINK_FREQ : integer := 1; constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1;

signal cnt     : unsigned(24 downto 0); signal blink   : std_logic;

begin

process(clk) begin

if rising_edge(clk) then if cnt=CNT_MAX then cnt <= (others => '0'); blink <= not blink; else cnt <= cnt + 1; end if; end if;

end process;

led <= blink;

end rtl;

The not yet famous VHDL 'Hello World' example

Compiling and Pin Assignment
The analysis, synthesize, map, and place & route processes are all started with Processing -- Start Compilation. The compiler did not know that our PCB is already done, so the compiler assigned any pin numbers for the inputs and outputs.

If Full Compilation fails you may try to manually correct the toplevel entity.

However, the pin numbers are fixed for the board. We have to assign the pin numbers for our two ports clk and led. Open the pin assignment window with Assignments -- Pins. Our two ports are already listed in the All Pins window. Double click the field under Location and select the pin number. Enter following assignments:

clk look up in board docu led look up in board docu

With the correct pin assignment restart the compilation with Processing -- Start Compilation (or use the play button) and check the correct assignment in the compilation report under Fitter -- Pin-Out-File. The clk pin should be located at nn and led at mm; all unused pins should be listed as RESERVED_INPUT.

FPGA Configuration
Downloading your hardware project into the FPGA is called configuration. There are several ways an FPGA can be configured. Here we describe configuration via JTAG.

UsbBlaster
This section describes configuration via UsbBlaster connected to the printer port.

 * 1) Connect your UsbBlaster to the PC and FPGA board
 * 2) Start the programmer with Tools -- Programmer
 * 3) Press the button Auto Detect and the programmer window should list the correct device.
 * 4) Double click for the filename of the FPGA device and select hello_world.sof.
 * 5) Select the checkbox under Program/Configure for the FPGA and press the Start button to configure the FPGA

The LED should now blink!

Further Experiments
Play with the code and do following changes:

 * Change the blinking frequency.
 * Have the on shorter than the off time of the LED.

Tips

 * The Chisel or VHDL source files and the project files do not have to be in the same directory. Keeping them in separate directories is a better organization and simplifies reuse
 * Use relative paths wherever possible to enable project sharing
 * In general choose the entity name as filename. However, with different files (and names) for different versions of an entity a project can be easily configured just with different Quartus II projects

Quartus File Types
The most important file types used by Quartus:

 * .qpf: Quartus II Project File. Contains almost no information.
 * .qsf: Quartus II Settings File defines the project. VHDL files that make up your project are listed. Constraints such as pin assignments and timing constraints set here.
 * .cdf: Chain Description File. This file stores device name, device order, and programming file name information for the programmer.
 * .tcl: Tool Command Language. Can be used in Quartus to automate parts of the design flow (e.g. pin assignment).
 * .sof: SRAM Output File. Configuration for Altera devices. Used by the Quartus programmer or by quartus_pgm . Can be converted to various (or too many) different format. Some are listed below.

Links

 * Quarts II Web Edition - VHDL synthesis, place and route for Altera FPGAs


text:
Computer Architecture Lab/HOWTO

A collection of some tips for your microprocessor design

Memory
You will probably need some memory for your processor. The simplest way to start is using the small on-chip memory blocks in the FPGA. You can instantiate the vendor-specific components (e.g. altsyncram . However, to get a vendor-independent design it is also possible to use plain VHDL.

Note: In actual FPGAs you cannot use memories in an asynchronous mode. At the minimum the address, data input and write enable are registered.

ROM
A ROM can be described by a simple VHDL case statement:

-- -- rom.vhd -- -- generic VHDL version of ROM -- --     DONT edit this file! --     it is automatically generated --

library ieee; use ieee.std_logic_1164.all;

entity rom is generic (width : integer; addr_width : integer);   -- for compatibility port (   clk         : in std_logic;    address     : in std_logic_vector(9 downto 0);    q           : out std_logic_vector(7 downto 0) ); end rom;

architecture rtl of rom is

signal areg    : std_logic_vector(9 downto 0); signal data    : std_logic_vector(7 downto 0);

begin

process(clk) begin

if rising_edge(clk) then areg <= address; end if;

end process;

q <= data;

process(areg) begin

case areg is

when "0000000000" => data <= "10000000"; when "0000000001" => data <= "10000000"; when "0000000010" => data <= "11000000"; when "0000000011" => data <= "10000000"; when "0000000100" => data <= "00011011"; when "0000000101" => data <= "11000001"; ....       when "1111011011" => data <= "10000000"; when "1111011100" => data <= "10000000"; when "1111011101" => data <= "10000000"; when "1111011110" => data <= "10000000";

when others => data <= "00000000"; end case; end process;

end rtl;

Write a small program to generate this VHDL file from your assembler output or even let your assembler write the output as VHDL (see as exmple Jopa.java).

Another tool to generate a ROM VHDL file (romgen.cpp) is available in pacman_003.zip.

RAM
Even dual ported memories can now (with careful VHDL coding) be instantiated from plain VHDL as the following example shows:

-- --	sdpram.vhd -- --	Simple dual port ram with read and write port --		and independent clocks -- --	When using different clocks following warning is generated: --		Functionality differs from the original design. --	Read during write at the same address is undefined. -- --	Author: Martin Schoeberl (mschoebe@mail.tuwien.ac.at) -- --	2006-08-03	adapted from simulation only version --

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity sdpram is generic (width : integer := 32; addr_width : integer := 7); port (	wrclk		: in std_logic;	data		: in std_logic_vector(width-1 downto 0);	wraddress	: in std_logic_vector(addr_width-1 downto 0);	wren		: in std_logic;

rdclk		: in std_logic; rdaddress	: in std_logic_vector(addr_width-1 downto 0); dout		: out std_logic_vector(width-1 downto 0) ); end sdpram ;

architecture rtl of sdpram is

signal reg_dout			: std_logic_vector(width-1 downto 0);

subtype word is std_logic_vector(width-1 downto 0); constant nwords : integer := 2 ** addr_width; type ram_type is array(0 to nwords-1) of word;

signal ram : ram_type;

begin

process (wrclk) begin if rising_edge(wrclk) then if wren='1' then ram(to_integer(unsigned(wraddress))) <= data; end if; end if; end process;

process (rdclk) begin if rising_edge(rdclk) then reg_dout <= ram(to_integer(unsigned(rdaddress))); dout <= reg_dout; end if; end process;

end rtl;

Use a single clock connected to wrclk and rdclk for your design

External Memory
For the 32 bit 1 MB SRAM on the FPGA board you can use the SimpCom compatible memory interface (sc_sram32.vhd) that is provided with JOP.

General
This RAM implementation enables you to use the XILINX Block RAMs within your design. It is based on the code from the XILINX XST Manual. For small RAMs (e.g. address bus width = 3) distributed RAM is used since for such small memories it needs less logic cells. The code was synthesised using ISE Webpack 8.2i03 and tested on a Micromodule from Trenz Elektronik (carring a XC3S1000-4). The testroutine fills the RAM using a serial port and reads back the RAM contents. It is not included in the Wiki since it only works with additional hardware (serial port). Additionally the code was synthesised using QuartusII 6.0sp1 WebPack and tested on the LAB hardware.

Implementation Summary
TBD...to be done

Simple Dual-Port RAM
The following code is compiled to on-chip memory, which is prefered for the register file.

-- -- -- This file is a part of JOP, the Java Optimized Processor -- -- Copyright (C) 2006, Martin Schoeberl (martin@jopdesign.com) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by --  the Free Software Foundation, either version 3 of the License, or --  (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . --

-- --	sdpram.vhd -- --	Simple dual port ram with read and write port --		and independent clocks --	Read and write address, write data is registered. Output is not --	registered. Read enable gates the read address. Is compatible --	with SimpCon. -- --	When using different clocks following warning is generated: --		Functionality differs from the original design. --	Read during write at the same address is undefined. -- --	If read enable is used a discrete output register is synthesized. --	Without read enable the -- --	Author: Martin Schoeberl (martin@jopdesign.com) -- --	2006-08-03	adapted from simulation only version --	2008-03-02	added read enable --

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity sdpram is generic (width : integer := 32; addr_width : integer := 7); port (	wrclk		: in std_logic;	data		: in std_logic_vector(width-1 downto 0);	wraddress	: in std_logic_vector(addr_width-1 downto 0);	wren		: in std_logic;

rdclk		: in std_logic; rdaddress	: in std_logic_vector(addr_width-1 downto 0); rden		: in std_logic; dout		: out std_logic_vector(width-1 downto 0) ); end sdpram ;

architecture rtl of sdpram is

signal reg_dout			: std_logic_vector(width-1 downto 0);

subtype word is std_logic_vector(width-1 downto 0); constant nwords : integer := 2 ** addr_width; type ram_type is array(0 to nwords-1) of word;

signal ram : ram_type;

begin

process (wrclk) begin if rising_edge(wrclk) then if wren='1' then ram(to_integer(unsigned(wraddress))) <= data; end if; end if; end process;

process (rdclk) begin if rising_edge(rdclk) then if rden='1' then reg_dout <= ram(to_integer(unsigned(rdaddress))); end if; end if; end process;

dout <= reg_dout;

end rtl;

Single Port RAM
- -- -- Filename: sp_ram.vhd -- ========= -- -- Short Description: -- ================== --  Single port ram. -- -- Description: -- ============ --  Implementation of a single port ram. --  Based on the ram code described in the Xilinx XST Manual. -- --  The memory uses low active control signals. The following --  combinations are possible: -- --   nwr | ncs | Description --  --     0  |  0  | Write access --    1  |  0  | Read access --    X  |  1  | Inactive -- --  The address and data bus width can be specified using --  the generic map. The default is eight bit data bus and --  eight bit address bus. -- -- Verification: -- ============= --  Simulated using ISE Webpack 8.2.03i running on Ubuntu Linux 6.10. --  Synthesized using ISE Webpack 8.2.03i running on Ubuntu Linux 6.10. --  Tested on a XC3S1000-4 -- -

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity sp_ram is generic (   DATA_WIDTH : integer := 8;    ADDR_WIDTH : integer := 8  ); port (   clk : in std_logic;    addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);    data_w : in std_logic_vector(DATA_WIDTH - 1 downto 0);    data_r : out std_logic_vector(DATA_WIDTH - 1 downto 0);    nwr : in std_logic;    ncs : in std_logic  ); end sp_ram;

architecture beh of sp_ram is subtype ram_entry is std_logic_vector(DATA_WIDTH - 1 downto 0); type ram_type is array(0 to (2 ** ADDR_WIDTH) - 1) of ram_entry; signal ram : ram_type; begin process(clk) begin if rising_edge(clk) then if ncs = '0' then if nwr = '0' then ram(to_integer(unsigned(addr))) <= data_w; else data_r <= ram(to_integer(unsigned(addr))); end if; end if; end if; end process; end beh;

Dual Port RAM with one Write Port
- -- -- Filename: dp_ram_1w.vhd -- ========= -- -- Short Description: -- ================== --  Dual port ram with only one writing port. -- -- Description: -- ============ --  Implementation of a dual port ram with only one writing port. --  Based on the ram code described in the Xilinx XST Manual. -- --  Both ports are using the same clock! --  The memory uses low active control signals. The following --  combinations are possible: -- --  Port 1: --   nwr1 | nsc1 | Description --  --      0  |   0  | Write access --     1  |   0  | Read access --     X  |   1  | Inactive -- --  Port 2: --   nsc2 | Description --  - --      0  | Read access --     1  | Inactive -- --  The address and data bus width can be specified using --  the generic map. The default is eight bit data bus and --  eight bit address bus. -- -- Verification: -- ============= --  Simulated using ISE Webpack 8.2.03i running on Ubuntu Linux 6.10. --  Synthesized using ISE Webpack 8.2.03i running on Ubuntu Linux 6.10. -- -

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity dp_ram_1w is generic (   DATA_WIDTH : integer := 8;    ADDR_WIDTH : integer := 8  ); port (   clk : in std_logic;    addr1 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);    data_w1 : in std_logic_vector(DATA_WIDTH - 1 downto 0);    data_r1 : out std_logic_vector(DATA_WIDTH - 1 downto 0);    nwr1 : in std_logic;    ncs1 : in std_logic;    addr2 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);    data_r2 : out std_logic_vector(DATA_WIDTH - 1 downto 0);    ncs2 : in std_logic  ); end dp_ram_1w;

architecture beh of dp_ram_1w is subtype ram_entry is std_logic_vector(DATA_WIDTH - 1 downto 0); type ram_type is array(0 to (2 ** ADDR_WIDTH) - 1) of ram_entry; signal ram : ram_type; begin process(clk) begin if rising_edge(clk) then if ncs1 = '0' then if nwr1 = '0' then ram(to_integer(unsigned(addr1))) <= data_w1; else data_r1 <= ram(to_integer(unsigned(addr1))); end if; end if; end if; end process;

process(clk) begin if rising_edge(clk) then if ncs2 = '0' then data_r2 <= ram(to_integer(unsigned(addr2))); end if; end if; end process; end beh;

Dual Port RAM with two Write Ports
- -- -- Filename: dp_ram.vhd -- ========= -- -- Short Description: -- ================== --  Dual port ram with two writing ports. -- -- Description: -- ============ --  Implementation of a dual port ram with two writing ports. --  Based on the ram code described in the Xilinx XST Manual. -- --  Both ports are using the same clock! --  The memory uses low active control signals. The following --  combinations are possible: -- --   nwrx | nscx | Description --  --      0  |   0  | Write access --     1  |   0  | Read access --     X  |   1  | Inactive -- --  The address and data bus width can be specified using --  the generic map. The default is eight bit data bus and --  eight bit address bus. -- -- Verification: -- ============= --  Simulated using ISE Webpack 8.2.03i running on Ubuntu Linux 6.10. --  Synthesized using ISE Webpack 8.2.03i running on Ubuntu Linux 6.10. -- -

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity dp_ram is generic (   DATA_WIDTH : integer := 8;    ADDR_WIDTH : integer := 8  ); port (   clk : in std_logic;    addr1 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);    data_w1 : in std_logic_vector(DATA_WIDTH - 1 downto 0);    data_r1 : out std_logic_vector(DATA_WIDTH - 1 downto 0);    nwr1 : in std_logic;    ncs1 : in std_logic;    addr2 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);    data_w2 : in std_logic_vector(DATA_WIDTH - 1 downto 0);    data_r2 : out std_logic_vector(DATA_WIDTH - 1 downto 0);    nwr2 : in std_logic;    ncs2 : in std_logic  ); end dp_ram;

architecture beh of dp_ram is subtype ram_entry is std_logic_vector(DATA_WIDTH - 1 downto 0); type ram_type is array(0 to (2 ** ADDR_WIDTH) - 1) of ram_entry; shared variable ram : ram_type; begin process(clk) begin if rising_edge(clk) then if ncs1 = '0' then if nwr1 = '0' then ram(to_integer(unsigned(addr1))) := data_w1; else data_r1 <= ram(to_integer(unsigned(addr1))); end if; end if; end if; end process;

process(clk) begin if rising_edge(clk) then if ncs2 = '0' then if nwr2 = '0' then ram(to_integer(unsigned(addr2))) := data_w2; else data_r2 <= ram(to_integer(unsigned(addr2))); end if; end if; end if; end process; end beh;

Automation
When your processor build process gets more complex a more batch oriented build process will come handy. make will be your friend. Following listing shows how to use Quartus II from within a Makefile:

qsyn: echo $(QBT) echo "building $(QBT)" -rm -r quartus/$(QBT)/db -rm quartus/$(QBT)/jop.sof -rm jbc/$(QBT).jbc -rm rbf/$(QBT).rbf quartus_map quartus/$(QBT)/jop quartus_fit quartus/$(QBT)/jop quartus_asm quartus/$(QBT)/jop quartus_tan quartus/$(QBT)/jop
 * 1) 	Quartus build process
 * 2) 		called by jopser, jopusb,...
 * 1) 		called by jopser, jopusb,...

The example is taken from the Makefile for JOP.

JOP as an Example
If you want to see a Java processor (JOP) running on the board follow the instructions in Jopwiki Getting started. The processor is open-source and you can borrow some ideas from it.

Latex2wiki
For the ones who prefer Latex over wiki-code for documentation, this tool might be interesting: Latex2wiki.

title: Computer Architecture Lab/HOWTO


text:
Computer Architecture Lab/Summer2006

Project page for the course in summer 2006.

The page presents the results from the Summer 2006 course. See the microprocessor built below.

The Conditional Microprocessor 2.0
Christof Pitter Heinz Deinhart

Our summary about three desgins is located here.

Information about our Work on TCMP2.0 can be found here.

VRIPU - Very Reduced Instructions Processing Unit
Project members: Andreas Czink, Michael Pokorny, Stefan Resch

Instruction Set Summary for Z80, ATMega8, and PIC16F627

Click here to visit our project page.

title: Computer Architecture Lab/Summer2006


text:
Computer Architecture Lab/Summer2006/CzinkPokornyResch/VRIPU

This is the project page for VRIPU (Very Reduced Instructions Processing Unit) microprocessor.

Short description
The goal of the VRIPU project is to design a pipelined RISC microprocessor which will only have a few instructions (about twenty).

VRIPU Datasheet
The datasheet for VRIPU can be found here.