text:
Computer Architecture Lab/Summer2006/PitterDeinhart/TCMP2.0

The Concept
The design is based on a 16bit load/store architecture. All instructions need two bytes space. A rather unusal (but already existing in some chips) idea is, that every opcode can be flagged as conditional.

Memory
Instruction and data memory are separated. Instructions are read from ROM data can be read and written to the RAM.

Since all instructions consist of 2 bytes the ROM can adress 128 kilobytes. The instruction pointer counts words. Constants can be loaded from ROM using the LDI* opcodes (see below).

Since RAM can be accessed byte per byte it can store only 64 kilobytes of data.

Registers
There are 16 general purpose registers. Their size is 16 bits and they are called ax, bx, cx, .. px.

Additionally there exists the 1 bit sized conditional flag (CF).

Conditionals
A conditional bit is added to each instruction. If this bit is 1, then the instruction is considered conditional and is only executed if conditional flag is set. The conditional flag can be modified by CMP* or by calling clear conditional flag (CCF). Those can be conditional instructions, too.

Load & Store
''MS: you will need an indierct load and store (LD (ax), ST (AX)). Without'' ''those instructions you will be VERY limited. Then you will think again'' about a register size which is less than the address size - one of the big issues in the 8086..80286 (the segementation was a real pain) ;-)

The heart of our load/store architecture are these two commands. Actually one could argue that they are 32 commands, because they have the register number hardcoded into the opcode.

LD	   loads a word from RAM into a register ST	   stores a word from a register into the RAM LDIL,LDIH loads an immediate byte from ROM into a register

Comparison
All comparison instructions set the conditional flag as a result.

CMPEQ	 tests if two registers are equal CMPNE	 tests if two registers are not equal CMPGT	 tests if register 1 > register 2 CMPLT	 tests if register 1 < register 2 CMPEZ	 tests if register is equal to zero CMPNZ	 tests if register is not equal to zero

''Is there any way to set the conditional flag when register 1 <= register 2 ? Or do we need a CMPLE ?''

Is there any difference at all between GMPGT R1, R2 or GMPLT R2, R1 ?

Branching
JMP	 loads a registers value into the instruction pointer

ALU operations
ADD	 adds registers 1 to register 2 ADDI	 adds immediate value to register SUB	 subtracts registers 1 to register 2 SUBI	 subtracts immediate value from register AND	 bitwise locigally ands register 1 to register 2 OR	 bitwise locigally ors register 1 to register 2 XOR	 bitwise locigally xors register 1 to register 2 SHL	 shifts the register specified bits left SHR	 shifts the register specified bits right NOT	 bitwise logically nots register

Others
CCF	 clears the conditional flag NOP	 null operation, justs waits a cycle

Instruction Set Encoding
a .. ALU operation number c .. conditional flag (CF) i .. immediate value s .. source register number d .. destination register number m .. memory pointer register number j .. jump pointer register number _ .. don't care

ALUOPS c1aaaaaa ssssdddd

LDIL  c000iiii iiiidddd LDIH  c001iiii iiiidddd

LD    c0100000 mmmmdddd ST    c0100001 mmmmdddd

JMP   c0100010 ____jjjj

CCF   c0100110 ________ NOP   c0100111 ________

optional and reserved for future use:

LOOP  c0101iii iiiiiiii LDX   c011iiii mmmmdddd

ALU ops
operations that do not modify CF: 0xxxxx

000000 ADD 000001 SUB 000010 AND 000011 OR 000100 XOR 000101 NOT 000110 SHL 000111 SHR 001000 ASR

operations that do modify CF: 1xxxxx

100000 CMPEQ 100001 CMPNE 100010 CMPGT 100011 CMPLT 100100 CMPEZ (d = dont care) 100101 CMPNZ (d = dont care)

The Assembler and Simulator
The assembler/simulator package can be downloaded from http://www.nix.at/sw/tcmp/

Note that only versions >= 0.1 only support TCMP2.0 while versions 0.0.* only support TCMP1. The version that represents the state at the end of the computer architecture course is 0.2.4.

The pacakge consists of the assembler and 3 different simulator programs, which are all described below. Read the INSTALL file in the package for installation hints/requirements.

The package is written in Objective Caml, wich is a really greate computer language. It will generate byte code and object code executables (if supported on your architecture). So if you find an executable called e.g. asm.opt you may call it instead of just asm and it will do the same, but a lot faster.

The assembler: tcmp/asm
The assembler can output text (to verify parser and some calculations), binary output (mainly used for simulation) and vhdl code (can be used as or in a ROM implementation).

When u call it with no arguments or with -h it will give you instruction how to use it: asm: usage: ./asm (-b|-r|-t) -b binary output (better not to stdout..) -r vhdl rom code output -t asm text output (to verify parser)

Line Layout
The assembler layout is similar to nasm, its lines consist of up to three parts:

label:   instruction operands        ; comment

All three components are optional. Operands are separated by a ','.

The main difference is that there is an optional '?' that can be written directly before the instruction. That marks the instruction to be a conditional one.

Mnemonics
The mnemonics are lower case variants of the instructions.

There are some macro like mnemonics that will expand to several instructions when used:

jump reg,label  ; this will jmp to label using reg for address generation

Example Program 1: Blinking around
This little example program blinks with the boards LED.

;; blink led ; begin: ;; counter delta ldil cx,1 ldih cx,0 ;; high word ldil bx,70    ; change this to adjust frequency ldih bx,0 bigloop: ;; low word ldil ax,0x20 ldih ax,0xa1 smallloop: sub cx,ax cmpnz ax       ?jump (fx),smallloop ;       sub cx,bx cmpnz bx       ?jump (fx),bigloop doblink: not ox,ox jump (fx),begin

Example Program 2: Blinking around with changing frequency
This is a modification to the previous example, with variable frequency.

;; blink led ;       ;; counter delta ldil cx,1 ldih cx,0 begin: ;; meta freq ldil ex,70 ldih ex,0 metaloop: ;; high word ldil bx,0    ; change this to adjust frequency ldih bx,0 bigloop: ;; low word ldil ax,0x20 ldih ax,0xa1 smallloop: sub cx,ax cmpnz ax       ?jump (fx),smallloop ;       add cx,bx cmpne bx,ex ?jump (fx),bigloop doblink: not ox,ox sub cx,ex cmpnz ex       ?jump (fx),metaloop jump (fx),begin

Example Program 3: Instruction tester
Not really useful, but it covers all instructions.

; comment ldil ax,10             ;  low byte of ax := 10 nop ldih ax,0              ;  high byte of ax := 10 st ax,(bx)             ;  Memory[ax] := bx        ld ax,(bx)              ;  ax := Memory[bx] ccof jump (fx),l1           ;  fx := AddressOf(l1); ip := fx        jmp (ax)                ;  ip := ax        ccof                    ;  c := 0 nop                    ;  no operation add ax,bx              ;  bx := ax + bx        sub ax,bx               ;  bx := ax - bx        and ax,bx               ;  bx := ax and bx        not ax,bx               ;  bc : = not ax        or ax,bx                ;  bx := ax or bx        xor ax,bx               ;  bx := ax xor bx        shl ax                  ;  ax := ax shl 1 shr bx                 ;  bx := ax shr 1 asr cx                 ;  cx := cx asr 1 cmpeq ax,bx            ;  c := ax == bx        cmpne ax,bx             ;  c := ax != bx        cmpgt ax,bx             ;  c := ax > bx        cmplt ax,bx             ;  c := bx < ax        cmpez ax                ;  c := ax == 0 cmpnz ax               ;  c := ax != 0 l1: nop ?not bx       cmpez ax l2: ccof l3: l3b:  not ax        sub cx,ax jump (fx),l2 l4: jump (fx),l4

The simulator: tcmp/sim
This simulator takes an assembler program and simulates it instruction by instruction. You can optionally specify how much cycles it will simluate. It has its own little help screen, too:

./sim: usage: ./sim []

If you simulate the first instruction of blink.asm you will get this output:

./sim blink.bin 1 | awk '{ printf " ";print}' registers:    ax=00 cx=00 ex=00 gx=00 ix=00 kx=00 mx=00 ox=00 ip=0 bx=00 dx=00 fx=00 hx=00 jx=00 lx=00 nx=00 px=00 cof=false RAM: 0000: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 001a:  0000 0000 0000 ROM: 0000: 0012 2700 1002 0011 2700 1001 0010 2700 1000 2700 4120 2700 6500 000d:  2700 80a5 a700 9005 a700 a205 2700 4121 2700 6510 2700 8065 a700 001a: 9005 a700 a205 2700 45ee 0005 2700 1005 2700 2205 executing instruction: -> ldil        cx,1     (0000000000010010=0x0012) registers:    ax=00 cx=01 ex=00 gx=00 ix=00 kx=00 mx=00 ox=00 ip=1 bx=00 dx=00 fx=00 hx=00 jx=00 lx=00 nx=00 px=00 cof=false RAM: 0000: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 001a:  0000 0000 0000 ROM: 0000: 0012 2700 1002 0011 2700 1001 0010 2700 1000 2700 4120 2700 6500 000d:  2700 80a5 a700 9005 a700 a205 2700 4121 2700 6510 2700 8065 a700 001a: 9005 a700 a205 2700 45ee 0005 2700 1005 2700 2205

Please note that you won't see any hazards here, as this simulator knows nothing about pipelining at all. This can be useful to verify the correctness of the pipeline engine (or the builtin hazard prevention freature of the assembler).

The pipelined simulator: tcmp/psim
This is another simulator, which is completly different from the previous one. While it should give the same results it simulates the complete TCMP pipeline. So it will corrupt registers or RAM if there are hazards. In short: It will (try to) act like the processor in hardware.

While its internals are completly different, the usage is equal to the non pipelined simulator:

./psim: usage: ./psim []

If we simlate 5 clock cycles of blink.asm we get:

RST IF: ip=0001 ID: cof=false rom[0000]=0012 that is ldil    cx,1 EX: s23op=NOP s23rda=0 rd1=0000 rd2=0000 s23aluops=0 s23ldiv=00 s23ldiop=0 reg.file: ax=0000 cx=0000 ex=0000 gx=0000 ix=0000 kx=0000 mx=0000 ox=0000 bx=0000 dx=0000 fx=0000 hx=0000 jx=0000 lx=0000 nx=0000 px=0000 WB: s34op=NOP s34rda=0 ram[0000]=0000 s34aluout=0000 s34ldiout=0000 CLK IF: ip=0002 ID: cof=false rom[0001]=2700 that is nop EX: s23op=LDI s23rda=2 rd1=0000 rd2=0000 s23aluops=0 s23ldiv=01 s23ldiop=0 reg.file: ax=0000 cx=0000 ex=0000 gx=0000 ix=0000 kx=0000 mx=0000 ox=0000 bx=0000 dx=0000 fx=0000 hx=0000 jx=0000 lx=0000 nx=0000 px=0000 WB: s34op=NOP s34rda=0 ram[0000]=0000 s34aluout=0000 s34ldiout=0000 CLK IF: ip=0003 ID: cof=false rom[0002]=1002 that is ldih    cx,0 EX: s23op=NOP s23rda=0 rd1=0000 rd2=0000 s23aluops=27 s23ldiv=70 s23ldiop=0 reg.file: ax=0000 cx=0000 ex=0000 gx=0000 ix=0000 kx=0000 mx=0000 ox=0000 bx=0000 dx=0000 fx=0000 hx=0000 jx=0000 lx=0000 nx=0000 px=0000 WB: s34op=LDI s34rda=2 ram[0000]=0000 s34aluout=0000 s34ldiout=0001 CLK IF: ip=0004 ID: cof=false rom[0003]=0011 that is ldil    bx,1 EX: s23op=LDI s23rda=2 rd1=0000 rd2=0001 s23aluops=10 s23ldiv=00 s23ldiop=1 reg.file: ax=0000 cx=0001 ex=0000 gx=0000 ix=0000 kx=0000 mx=0000 ox=0000 bx=0000 dx=0000 fx=0000 hx=0000 jx=0000 lx=0000 nx=0000 px=0000 WB: s34op=NOP s34rda=0 ram[0000]=0000 s34aluout=3039 s34ldiout=0070 CLK IF: ip=0005 ID: cof=false rom[0004]=2700 that is nop EX: s23op=LDI s23rda=1 rd1=0000 rd2=0000 s23aluops=0 s23ldiv=01 s23ldiop=0 reg.file: ax=0000 cx=0001 ex=0000 gx=0000 ix=0000 kx=0000 mx=0000 ox=0000 bx=0000 dx=0000 fx=0000 hx=0000 jx=0000 lx=0000 nx=0000 px=0000 WB: s34op=LDI s34rda=2 ram[0000]=0000 s34aluout=3039 s34ldiout=0001 CLK IF: ip=0006 ID: cof=false rom[0005]=1001 that is ldih    bx,0 EX: s23op=NOP s23rda=0 rd1=0000 rd2=0000 s23aluops=27 s23ldiv=70 s23ldiop=0 reg.file: ax=0000 cx=0001 ex=0000 gx=0000 ix=0000 kx=0000 mx=0000 ox=0000 bx=0000 dx=0000 fx=0000 hx=0000 jx=0000 lx=0000 nx=0000 px=0000 WB: s34op=LDI s34rda=1 ram[0000]=0000 s34aluout=0000 s34ldiout=0001

RST and CLK are the reset and the clock signal.

The graphical pipelined simulator: tcmp/gpsim
This is a graphical frontend to the pipelined simulator (psim). It accepts no option, instead it will show you a file dialog to choose some binary code to load.

The interface is quite simple and self explaining. Just take a look at this screenshot:

Pipeline Architecture
The TCMP2.0 pipeline consists of 4 stages:

 * Instruction fetch
 * Instruction decode
 * Execute
 * Write back

If you have not by now, please take a look at the picture in the gpsim section to get an overview. The line colors are showing from which stage the signals are coming (Cyan, Bue, Red, Green).

At this time there is no processor builtin hazard prevention, but a smart nop generateion at assembler level. Due to our not too unclever design, there is no need to delay the processor for more than one nop at once. Of course one could implement e.g. bypassing but to our luck that was not in the mandatory scope of computer architecture.

But maybe by the time you read this, it is already implemented in the simulator or even at vhdl level. So be sure to check the download packages!

VHDL Implementation
The VHDL implementation was generated by first creating the black boxes like ALU and register file. Then we basically translated the code from the pipelined simulator (can be found in pipeline.ml) into VHDL. Once that seemed to be complete we simulated the whole thing in Modelsim.

After a few fixes, mainly dangling signals, we downloaded the processor to the FPGA. To our suprise it nearly instantly worked. Maybe it was a good idea to simulate a lot with tcmp/*sim and Modelsim. On the other side, maybe we just had lots of luck :)

The full vhdl files can be downloaded here: [http://www.nix.at/tcmp2/vhdl.zip vhdl.zip].

Additionally a couple of testbenches were created to simulate some building blocks of the processor in ModelSim. The following screenshot describes a simulation of the processor running the blink2.asm program.


text:
Computer Architecture Lab/Summer2006/PitterDeinhart/ThreeDesigns

Quellen:
http://www.ecs.tuwien.ac.at/spear/downloads/papers/Handbook.pdf

SPEAR bedeutet Scaleabel Processor for Embedded Applications in Real-Time Environments. Wurde auf TU Wien E182-2 mit besonderen Augenmerk auf Anpassbarkeit und EchtzeitfÃ¤higkeit entwickelt.

Blockschaltbild:
[INSERT spear-blockschalt.png]

Speicher:
Bis zu 128KB addressierbar. Im Prozessorkern selber 4KB Befehls- und Datenspeicher.

Maschinenbefehle und Daten sind immer 16 Bit breit, Speicher wird Wortweise angesprochen.

Register:
Es gibt 32 Register auf die alle Befehle zugreifen koennen, 6 davon haben spezielle Aufgaben (3x Framepointer, 2x Unterprogramme, 1x Trap/ISR

Pipeline:
Der SPEAR hat eine 3-stufige Pipeline.

Befehlssatz:
Es gibt 80 Befehle, einige davon sind bedingte Befehle. Alle sind 16 Bit breit. Mit diesen kann man z.b. ein Register mit einem anderen oder einer Konstante vergleichen (CMP_EQ). Abhaengig vom ergebnis kann man dann z.b. ein bedingtes move verwenden (MOV_CT bzw. MOV_CF .. Contition True/False).

Es gibt 2 load Befehle: LDL: 000nnnnnnnnrrrrr LDH: 001nnnnnnnnrrrrr

Es gibt 29 Befehle die mit 2 Registern oder einem Register und einer 5Bit Konstante arbeiten, z.b.:

MOV_CT: 100011rrrrrRRRRR (contitional move) ADDI_CT: 100100nnnnnrrrrr (Contitional add)

Weitere 7 Befehle arbeiten mit einer 4Bit Konstante und einem Register, z.b.:

BCLR r1,n4: 1010001nnnnRRRRR (clears n4-th bit in r1)

Weitere 32 Befehle operieren nur auf einem Register, z.b.:

NOT:   10110000000rrrrr NOT_CT: 10111100000rrrrr (conditional not)

Dazu gibt es noch 3 Jump Befehle, die ein 10Bit Offset verwenden, z.b.:

JMPI_CT: 111010aaaaaaaaaa (continal relative jump)

Schliesslich gibt es noch 3 Befehle um den Program Counter aus einem bestimmten register neu zu setzen (return from subroutine). z.b.:

RTSX: 1011111101011101 (register 29 -> program counter)

Zuletzt sind noch NOP(No Operation) und IllOp(Illegal Opcode) zu erwähnen: NOP:  1111111000000000 IllOp: 1111111111111111

Quellen:

 * ecs.tuwien.ac.at/lehre/Microcontroller/Docs/ATmega16/AVR_Instruction_Set.pdf (link is to archive of original displayed page location)
 * circuitcellar.com/avr2006/devices.html

Blockschaltbild:
[INSERT atmega16-blockschalt.png]

Speicher:
Der ATmega16 hat 16KB flash, 512B EEPROM, 1KB SRAM.

Register:
32 8Bit breite General Purpose Working Registers, wobei 6 davon als 3 16Bit registern (X,Y,Z) verwendet werden koennen. Diese koennen z.b. zur Addressierung benutzt werden.

Dazu gibt es noch ein Status Register und einen Stack Pointer.

Pipeline:
Die Pipeline hat nur einen einzigen Schritt.

Befehlssatz:
Der ATMEGA16 hat 131 Befehle, die meisten davon kann er in einem einzigen Clock-Cycle verarbeiten.

Die meisten Befehle sind 16 Bit breit. Nur JMP und CALL sind 32 Bit breit, und brauchen daher einen Clock-Cycle mehr:

JMP: 1001010kkkkk110k kkkkkkkkkkkkkkkk (jumps to any address in 4M words program memory) CALL: 1001010kkkkk111k kkkkkkkkkkkkkkkk

Die normale, 16 Bit breiten Instructionen sehen z.b. so aus:

IN:  10110AAdddddAAAA (loads data from io space A into register d) OUT:  10111AArrrrrAAAA INC: 1001010ddddd0011 (increments register d)

Was auffällt ist, dass die einzelnen Bits etwas verstreut angeordnet sind. TODO FIXME: warum ist das so?

Quellen:

 * http://www.goblack.de/desy/mc8051chip/
 * http://www.win.tue.nl/~aeb/comp/8051/instruction-set.pdf#search=%22Instruction%20Set%208051%22

Der Befehlssatz ist stark auf die Lösung von Steuerungsaufgaben zugeschnitten, doch neben speziellen Befehlen zur Einzelbitverarbeitung stehen auch Befehle zur Multiplikation und Division zur Verfügung.

Blockschaltbild:
[INSERT 8051.png]

Speicher:
384 Bytes internes RAM. 256 Bytes davon beherrbergen die Registerbänke und den Stack. Weiters ist der 128 Bytes umfassende SFR-Speicherbereich darin enthalten. Darin befinden sich die Prozessorregister und die Steuerregister für die Tore, die Interruptlogik, die Timer und die D/A und A/D-Wandler.

Der Programmspeicher kann maximal 65535 Speicherzellen = 64kByte umfassen.

Die Prozessorregister der 8051 CPU:
Die Prozessorregister gehören schaltungstechnisch zu der CPU, jedoch liegen sie bei der 8051 CPU im Adreßraum des RAM-Speichers, der sich auf dem Chip befindet. Dadurch ergibt sich die besondere Möglichkeit, die Register einmal über die zugehörigen Sonderbefehle zu erreichen, aber auch über Adressen des internen Speicherraumes. Die Register sind 8-Bit lang, Ausnahme der DPTR und der nur indirekt zugängliche PC, beide sind 16-Bit lang.

 * A	Der Akkumulator (SFR)
 * B  	Das Hilfsregister bei Multiplikation und Division (SFR)
 * R0-R7	Die Speicher der Registerbänke 0-3 (unterer interner RAM)
 * PSW	Das ProgramStatusWord (SFR)
 * SP	Der Stackpointer (SFR)
 * DPTR	Der 16 Bit Datenpointer, bestehend aus DPL und DPH (SFR)

Im ProgramStatusWord der 8051-Controller befinden sich folgende flags:

 * C	Das CarryFlag (Übertrag), z.B.: C=1, bei Übertrag von Bit 7 nach Bit'8'
 * AC	Das AuxilliaryCarry (HilfsÜbertragsflag), z.B.: AC=1, bei Übertrag von Bit 3 nach Bit 4
 * F0	Freies Flag für Benutzer
 * RS1	Registerbank_Selekt_Bit 1 zum Umschalten der aktiven Registerbank
 * RS0	Registerbank_Selekt_Bit 0 zum Umschalten der aktiven Registerbank
 * OV	Das OverflowFlag, z.B.: OV=1, bei ungleiche Überträge von 7-'8' und 6-7
 * F1	Freies Flag für Benutzer
 * P	Das ParityFlag, z.B.: P=1, wenn Anzahl der 1 Bits in A gerade

1. Transportbefehle

 * Register <-> Registerbefehle, z.B. mov R0, A
 * Register <-> Speicher, z.B. mov @R0, A
 * Register <-> Ein-/Ausgabe, z.B. mov SBUF, R3
 * Speicher <-> Ein-/Ausgabe, z.B. mov @R0, P0
 * Bit <-> Bit, z.B. mov C, P3.4

2. Arithmetische und logische Befehle

 * Addition, Subtraktion, Inkrement und Dekrement, z.B. addc A,40H
 * Multiplikation, Division, z.B. mul AB
 * Logische Funktionen, z.B. orl A,B

3. Sprungbefehle

 * Unbedingte Sprünge, z.B. ajmp addr11
 * Bedingte Sprünge, z.B. jnz
 * Unbedingte Unterprogrammaufrufe, z.B. acall addr11
 * Beendigung von Unterprogrammen, z.B. ret

Die 5 Adressierungsarten des 8051:
Die Adressierungsarten werden an dem Befehl mov (move - bewege nach) erläutert, der bei der Intel-Assemblermnemonik in folgender Weise benutzt wird, mov Ziel, Quelle

 * Registeradressierung: z.B. mov A, R3 (Register wird in den Accu geladen)
 * Direkte Adressierung: z.B. mov 40h, #77h (Die Konstante 70h wird auf den internen Speicherplatz 40h geschrieben)
 * Registerindirekte Adressierung: z.B. mov A, @R0 (Der Inhalt auf den R0 zeigt, wird in den Accu gebracht)
 * Die unmittelbare Adressierung: z.B. mov A, #77h (Konstante wird direkt in den Accu geschrieben)
 * Adressierung über Basis- plus Indexregister: z.B. movc A, A+@DPTR (Für Zugriff auf Programmspeicher. Indexregister = Accumulator, Basisregister kann PC oder DPTR sein)

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/


text:
Computer Architecture Lab/Summer2006/cpr/Z80 ATM8 PIC16F627

Instruction Set Summary for Z80, PIC16F627, and ATMega8
We compare the following three systems: While Z80 is a microprocessor, PIC16F627 and ATMega8 are microcontrollers.
 * Zilog Z80
 * Microchip Technology PIC16F627
 * Atmel ATMega8

Let us compare the instruction sets of our 3 CPUs which are hardware dependent (they reside in the chips). As an example, we want to calculate c = a + b + 3, where a, b and c are registers and 3 is a constant value (an immediate).

ADD A, 3         ; A + 3 ADDC A, B        ; A + 3 + B + Carry Bit LD  C, A         ; -> C
 * Z80:

 * PIC16F627

MOVF 0x30, 0     ; 3 + register ADDLW 3 MOVWF 0x30 MOVF 0x30, 0     ; a + b -> c ADDWF 0x31, 0 MOVWF 0x32

 * ATMega8

SUBI 0x30, -3    ; 3 + register MOV  0x30, 0x32  ; a + b -> c ADD   0x32, 0x31

As one can see, Z80 and ATMega8 CPUs, which are using the registers directly, need fewer instructions compared to PIC16F627's to execute the same task. Thus the instructions of the Z80 and ATMega8 are more complex, and so these two CPUs have larger instruction sets. The PIC16F627's relatively smaller instruction set means it often requires more instructions to perform the same operations. While the microcontrollers have a Harvard architecture, the Z80 has a von Neumann.

Memory
The Z80, as every microprocessor, only has its internal registers which can be accessed directly or indirectly. The two microcontrollers also have internal RAM for data, while they use FLASH memory to store the program code. While the PIC16F627 separates its memory in four banks which are selected with two bits in the status register, the ATMega8 has only one address space, however the SRAM can only be accessed through indirect addressing. Both access the program memory through a program counter. Comparing the Stack there is also a difference between the microcontrollers. Usually the stack pointer of the ATMega8 is set to point to the end of the SRAM. Whenever a PUSH instruction is executed the stack pointer is decremented. The PIC16F627 has an extra eight-level stack which is organized as a loop, on overflow it is overwritten without affecting any flag.

Dataflow
Z80 with its Von Neumann architecture only has one bus for Data and Program, while the microcontrollers, following the Harvard architecture, have two separate busses one for Program and one for Data.

Registers
The ATMega8 has 32 general purpose registers and 64 special registers, which are used for counters, external pins, etc.. As already mentioned the PIC16F627 organizes its registers in four banks with 224 bytes for general purpose. The Z80 can use its 6 general purpose registers either as six eight-bit or three 16-bit registers. All together it has got 26 registers.

Pipelining
ATMega8 and PIC16F627 utilize a two-stages, fetch and execute, pipelining mechanism, whereas the Z80 does not have any pipelining capabilities at all. In 2001, the eZ80 was introduced, which is an enhanced version of the Z80, using also a two-stages pipelining mechanism.

Execution times
Most of the ATMega8's and PIC16F627's instructions need one clock cycle to execute, only instructions affecting the program counter take longer. Additionally ATMega8 has instructions which simply need more time due to higher complexity. The Z80's execution times vary due to no pipelining, from 1 to 6 cycles.


text:
Computer Architecture Lab/WS2006

Project page for the course in winter 2006. Results of 6 real working processors can be found here.

RISE (Rarest Instruction Set Ever)
Urban Stadler Harald Trinkl Jakob Lechner Christian Walter

Our discussion about three processor architectures can be found here. We have choosen to evaluate the following processors with respect to their intstruction set

 * 8Bit Xilinx Microblaze embeddedable processor suitable for FPGA synthesis. See http://www.xilinx.com/picoblaze for more detail.
 * The 64Bit Alpha 21x64 RISC CPU.
 * AVR ATMega. See http://www.atmel.com/products/AVR.

Our discussion workplace where whe are working on our draft for our CPU.

MatPRO
Marcus Jeitler Josef Mosser Hermann Frühwirth Stephan Ramberger

What's MatPRO?
MatPRO is a pipelined CoProzessor that handels 4x4 Matrix-Operations like addition or multiplication. It's equipped with a SimpCom-Interface to ensure an easy transport connection to existing SoC-Solutions.

 * current Development of ISA and Assembler
 * current source files

Discussion about three processor architectures
Our discussion about three processor architectures is done. Stop by to see what´s it about!

SISP (Spartanic Instruction Set Processor)
Thomas Polzer, Philipp Jahn, Thomas Flanitzer

Architecture Review
We have chosen the following three architectures:
 * Intel 8bit micro processor platform (Representative: 8088)
 * Atmel Atmega 8bit micro controller family (Representative: Atmega128)
 * Motorola 68k family (Representative: 68008)

Our discussion about those three processor can be found here.

Instruction Set and Processor details
Details about our planned processor as well as the instruction set definition can be viewed here.

Tools
The following tools have been developed for our processor:
 * Assembler
 * Instruction simulator
 * VHDL code generator

Samples
Sample assembler files can be found here.

iMISC (invertable Minimized Instruction Set Computer)
Michael Pöttschacher Maximilian Rosenblattl Andreas Wolf

We have choosen to compare the following architectures by their instruction sets

 * Atmel AVR architecture
 * 64Bit DEC Alpha architecture
 * Infineon TriCore architecture

See Details here.

Details about iMISC

marca - McAdam's RISC Computer Architecture
Roland Kammerer Wolfgang Puffitsch Kenan Bilic

For our comparison of three microprocessors go here.

 * SPEAR
 * Alpha 21264/EV6
 * ATmega 16

The VHDL sources, the assembler and the documentation are available here. Reversing a line works fine in hardware, feel free to try out other programs.

NORISK
Oliver Hoeftberger Simon Pirker Bernhard Weirich Yilin Huang

Our three examples of RISC ISA are the following:

 * ARM
 * PowerPC 405
 * PICmicro

You might be interested in the our  NORISK Processor Design. The VHDL codes, Assembler and Instruction Set Simulator are here.

Group 6
Ljatifi & Arfan

The examples

Here is our instruction set.

title: Computer Architecture Lab/WS2006


text:
Computer Architecture Lab/Winter2006/HoeftPirkWeir/InstructionSetI

ARM
32-bit RISC Prozessor, der sich vor allem durch gute Energieeffizienz auszeichnet, weswegen er in einer Vielzahl von Embedded Systems seinen Einsatz findet.

Instruction Set
Im normalen Modus ist eine Instruktion 32-bit lang, es gibt aber auch den Thumb Modus der einen reduzierten 16-bit Befehlssatz aufweist. Es wird hier nur auf den 32-bit Basisbefehlssatz eingegangen.

Register
Es gibt 15 General-Purpose Register, von denen 2 als Stack bzw. Rückkehradressen genützt werden. Zur effizienteren Interrupt-Behandlung sind diese 2 Register für jeden Prozessormodus ein Mal vorhanden.

Bedingte Ausführung
Jede Instruction beinhaltet 4 Bit, die eine Ausführung abhängig vom "Program Status Register" erlauben.

Branches
Relative Sprünge um bis zu 32MB als auch absolute Sprünge zu einer Adresse in einem Register sind möglich. Es gibt auch jeweils eine Version bei der der aktualle PC ins Rückkehradressenregister geladen wird.

Datenmanipulation
Unterstützte Operationen sind logisches UND, (exklusives) ODER, Subtraktion (mit Carry), Addition (mit Carry), Invertierung.

Ein Eingangswert kommt aus dem Shifter, der geshiftete oder rotierte 8-bit immediate Werte oder Registerwerte zur Verfügung stellt. Die Anzahl der geshifteten Bits ist entweder ein direkter 5-bit Wert oder ein Registerwert. Der 2. Eingangswert (sofern vorhanden) ist immer ein Register. Das Ergebnis wird in einem Register abgelegt, für UND, exklusives ODER, Subtraktion und Addition gibt es eine Version, die nur das PSR dem Ergebnis entsprechend anpasst.

Weiters gibt es Multiply und Multiply-Accumulate Befehle, mit Varianten die 32-bit, 64-bit vorzeichenlose, 64-bit vorzeichenbehaftete Ergebnisse liefern.

Speicherzugriff
Die Adressierung erfolgt durch ein Basisregister und einen Offset. Der Offset kann ein direkter 12-bit Wert, ein Register oder ein geshiftetes Register sein. Weiters kann das Basisregister nach Zugriff durch den Wert von Basisregister+Offset ersetzt werden, um einfach über Speicherblöcke iterieren zu können. Es gibt außerdem Befehle die mehrere Worte auf einmal in beliebige Register laden/speichern.

Andere Befehle
Der Befehl SWP erlaubt Laden und Speichern eines Wertes im Speicher innerhalb einer Instruktion, wodurch Prozesse leichter synchronisiert werden können. Der Software Interrupt Befehl dient dem Zugriff von User Mode Programmen auf Priviledged Code. Ein Breakpoint Befehl ist ebenfalls vorhanden.

PowerPC 405
PowerPC 405 is a 32-bit implementation of the PowerPC embedded-environment architecutre providing up to 400 MHz and 608 DMIPS performance.

Key Features

 * 32-bit architecture
 * Thirty-two 32-bit general purpose registers (GPRs), r0~r31
 * A number of 32-bit special purpose registers (SPRs)
 * Most are accessed only by privileged software
 * A few are accessed by all software
 * Flexible memory management
 * Enhanced debug capabilities
 * 64-bit time base
 * 3 timers: programmable interval timer, fixed interval timer, and watchdogtimer
 * 5-stage pipeline with single-cycle execution of most instructions, including loads and stores
 * Support for unaligned loads and unaligned stores to cache arrays, main memory and on-chip memory
 * Minimized interrupt latency
 * Integrated instruction-cache and data-cache:
 * 16 KB each, 2-way set associative
 * 8 words (32 bytes) per cacheline
 * Support for both big-endian and little-endian addressing
 * 4 GB of flat (non-segmented) address space
 * Dual-level interrupt

General Purpose Registers
32 GPRs (r0~r31) are the source and destination of all integer operations and are the source for address operands for all load/store operations. They also provide access to SPRs.

Floating Point Registers
FPRs here refer to FPRs and Floating-Point Status and Control Register (FPSCR). 32 FPRs (FPR0 - FPR31) are the source and destination operands of all floating-point operations and can contain 32-bit and 64-bit signed and unsigned integer values, as well as single and double-precision floating-point values. They also provide access to the FPSCR.

The FPSCR captures status and exceptions resulting from floating-point operations, and the FPSCR also provides control bits for enabling specific exception types, as well as for selecting one of the four rounding modes. Access to the FPSCR is through the FPRs.

Embedded microprocessors are frequently implemented without direct hardware support for the PPC floating-point instruction set, or only provide an interface to attach floating-point hardware. Many applications have little or no need for floating-point arithmetic, and software emulation of PPC floating-point instruction execution is usually more than adequate. The chip area and power savings of not implementing floating-point in hardware can be critical.

Special Purpose Registers
SPRs give status and control of resources within the processor core.

 * Instruction Address Register (IAR): known to programmers as the program counter or instruction pointer.
 * Link Register (LR): holds the address to return to at the end of a function call.
 * Fixed-Point Exception Register (XER): contains carry and overflow information from integer arithmetic operations, as well as carry input to certain integer arithmetic operations and the number of bytes to transfer during load and store string instructions, lswx and stswx.
 * Count Register (CTR): holds a loop counter that is decremented on certain branch operations.
 * Condition Register (CR): contains 8 fields, where each field is 4 bits. When an instruction's Rc bit (bit 31) is 1:
 * In integer operations, the CR field 0 is set to reflect the result of operation result: Equal, Greater Than, Less Than, and Summary Overflow.
 * In floating-point operations, the CR field 1 is set to reflect the state of the exception status bits in the FPSCR.
 * Any CR field can be the target of an integer or floating-point comparison instruction. The CR field 0 is also set to reflect the result of a conditional store instruction (stwcx or stdcx). Certain instructions can manipulate the CR.

 * Processor Version Register (PVR): a 32-bit read-only register that identifies the version and revision level of the processor.

Instruction Set
The POWER architecture has over two hundred defined instructions. Most instructions execute in a single cycle and typically perform a single operation (such as loading storage to a register, or storing a register to memory). Similar to most of the other 32-bit RISC ISAs, all PPC instructions are four bytes long and are word aligned. Bits 0:5 contain the primary opcode. Some instruction forms define an extended opcode field for specifying additional instructions.

Four Primary Formats

 * Register-register
 * {|border="2" cellpadding="4" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"

 * -align="center"
 * style="width:60px;background:#E6E6FA" |Op6
 * style="width:50px" |Rd5
 * style="width:50px" |Rs15
 * style="width:50px" |Rs25
 * style="width:110px;background:#E6E6FA" |Opx11
 * }
 * Register-immediate
 * {|border="2" cellpadding="4" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"

 * -align="center"
 * style="width:60px;background:#E6E6FA" |Op6
 * style="width:50px" |Rd5
 * style="width:50px" |Rs15
 * style="width:169px;background:#F5DEB3" |Const16
 * }
 * Branch
 * {|border="2" cellpadding="4" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"

 * -align="center"
 * style="width:60px;background:#E6E6FA" |Op6
 * style="width:50px;background:#E6E6FA" |Opx5
 * style="width:50px" |Rs15
 * style="width:133px;background:#F5DEB3" |Const14
 * style="width:20px;background:#E6E6FA" |Opx2
 * }
 * Jump/call
 * {|border="2" cellpadding="4" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"

 * -align="center"
 * style="width:60px;background:#E6E6FA" |Op6
 * style="width:252px;background:#F5DEB3" |Const24
 * style="width:20px;background:#E6E6FA" |Opx2
 * }

Integer arithmetic instructions

 * add, add carrying - addc, add extended - adde, add immediate carrying - addic, add to minus one extended - addme
 * devide word - divw, devide word unsigned -divwu
 * multiply low immediate - mulli, multiply high word - mulhw, multiply cross halfword to word unsigned - mulchwu
 * subtract from - subf, subtract from extended - subfe, subtract from zero extended
 * negate - neg

Logical, rotate, and shift instructions

 * and, or, nor, xor, equivalent - eqv, and with complement - andc
 * count leading zeros doubleword - cntlzd, extend sign halfword - extsh
 * rotate left doubleword then clear - rldc, rotate left word then and with mask - rlwnm
 * shift right doubleword - srd, shift right word immediate - srwi

Floating-point and FPSCR manipulation instructions

 * FP move - fmr, FP negate - fneg, FP compare ordered - fcmpo, FP select - fsel
 * move to CR from FPSCR - mcrfs, move to FPSCR bit 1 - mtfsb1

Branch instructions

 * branch - b
 * branch conditional - bc
 * branch conditional to count register - bcctr
 * branch conditional to link register - bclr

Uniqueness

 * Link Register: PPC puts the return address into the link register instead of one of the GPRs. It makes the return jump faster since the hardware need not go through the register read pipeline stage for return jumps.
 * Counter Register: It is used in for loops of a fixed number of times, therefore the the branch hardware can quickly determine if a branch is likely to take place.
 * Register 0: r0 is not hardwired to the value 0. Although it can not be used as a base register, however in base+index addressing it can be used as the index.
 * Load multiple and store multiple save or restore up to 32 registers in a single instruction.
 * CBTLZ counts leading zeros.
 * Logical shifted immediate instructions shift the 16-bit immediate to the left 16 bits before performing AND, OR, or XOR.
 * Etc.

PICmicro
Is a family of microcontrollers made by Microchip Technology with a reduced instruction set (RISC). It is also known as simply PIC microcontrollers.

Features

 * 80 memory ram positions, implemented as 8 bit registers. 12 special purpose registers and 68 general purpose registers.
 * 11 bit instruction address
 * 8 bit literals
 * 8/16 bit Modified Harvard Architecture
 * Flash and ROM Memory options
 * I/O Ports
 * 8/16 bit Timers
 * Several sleep modes
 * A/D converters
 * Serial peripherals
 * Voltage comparators
 * Internal EEPROM Memory
 * Motor control
 * USB, Ethernet, CAN, LIN, ... controller support

PICmicro MID-RANGE MCU FAMILY
Each midrange instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. There are three basic categories: All instructions are executed in one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.In these cases, the execution takes two instruction cycles with the second cycle executed as an NOP. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 us. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 us.
 * Byte-oriented operations
 * Bit-oriented operations
 * Literal-oriented operations

General instruction format
The possible formats for the instructions are listet in the figure.

the opcode portion of the instruction word varies from 3-bits to 6-bits of information. This is what allows the midrange instruction set to have 35 instructions.

Register manipulation
instruction set allows read and write of all file registers, including special function registers. If an instruction writes to the STATUS register, the Z, C, DC and OV bits may be set or cleared as a result of the instruction and overwrite the original data bits written. All bit manipulation instructions will first read the entire register, operate on the selected bit and then write the result back (read-modify-write (R-M-W)) the specified register.

Supported instructions
There are several groups of instrucions. Those can be divided into: Example: Mnemonic: movf fr, d Description: Move file register Function: fr => d Example: oprwf fr,d Mnemonic: logic / arithmetic operation with a file register and W Description: Function: fr opr W => d Example: Mnemonic: oprlw k Description: logic / arimetic operation with a literal and W Function: k opr W => W Example: Mnemonic: clrw   Description: Clear accumulator W  Function: 0 => W Example: Mnemonic: goto    addr Description: branch to addr Function: addr => PC(0:10) Example: Mnemonic: addcf fr, d Description: Add carry to fr Function: btfsc 3,0 incf f,d
 * Copy value from/to file register or literal to/from w
 * Logic / arithmetic instructions with a file register and w
 * Logic / arithmetic instructions with a literal and w
 * One operand logic / arithmetic instructions
 * Branch, Skip and Call instructions
 * Buit-in macros for commonly used logic / arithmetic operations


text:
Computer Architecture Lab/Winter2006/JeitMossFrühRamb/ThreeMicroDiscussion

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text:
Computer Architecture Lab/Winter2006/KammPuffBili/ThreeMicroDiscussion

SPEAR
16-Bit Load/Store-Architektur mit 32 Integer-Registern und einer dreistufigen Pipeline, die jeweils bis zu 128 kB Code- und Datenspeicher unterstützt. Arithmetische Befehle wie Addition und Subtraktion haben zwei Operanden, Shift/Rotate-Operationen verschieben den Operanden um jeweils 1 Bit. Speicherzugriffe ohne Offset sind mit jedem Register möglich, Speicherzugriffe mit konstantem Offset sind mit den Registern r26-r28 möglich.

Besonderheiten

 * Eine Reihe von Befehlen gibt es auch als konditionales Befehle, die in Abhängigkeit von einem "condition flag" ausgeführt werden. Der Hintergedanke dabei ist, die möglichen Ausführungspfade zu verringern bzw. idealerweise mit einem einzigen auszukommen und so die Ausführungszeit konstant zu halten.
 * Jeder Befehl benötigt genau einen Zyklus, was natürlich die Analysierbarkeit in Sachen "worst case execution time" erleichtert.
 * Es sind zwei (anstatt wie üblich nur einem) Register für Rücksprungadressen vorgesehen, sowie eines für die Rücksprungadressen von Interrupts.
 * Die Register r26 bis r28 unterstützen Speicherzugriffe mit konstantem Offset und sind daher für Stack- bzw. Framepointer prädestiniert.
 * Nur 16-Bit Speicherzugriffe werden unterstützt ("char" ist anstatt der üblichen 8 also 16 Bit weit).
 * Zur Erweiterung der Funktionalität des Prozessors können Hardware-Module in den Speicher gemappt werden (z.B. zur Implementation von Multiplikation und Division).

Branches
Für bedingte Sprünge wird zuerst die Bedingung getestet und das condition flag entsprechend gesetzt, und danch der Sprung in Abhängigkeit von diesem Flag (Bedingung wahr oder falsch) ausgeführt. Diese Vorgehensweise hat den Vorteil, weniger Opcodes für bedingte Befehle zu verbrauchen, allerdings werden 32- oder 64-Bit Vergleiche komplizierter (mann benötigt für jedes Register zwei Vergleichs- und zwei Sprungbefehle, anstatt einem Vergleichs- und zwei Sprungbefehlen).

Alpha 21264/EV6
64-Bit Load/Store-Architektur mit 32 Integer- und 32 Floating-Point-Registern. Die Bezeichnung als "RISC"-Architektur ist etwas irreführend, da eine relativ große Anzahl von Befehlen implementiert sind. Arithmetische Befehle wie Addition und Subtraktion haben drei Operanden, Speicherzugriffe mit konstantem Offset werden mit jedem (Integer-)Register unterstützt. Die Architektur nützt - neben einer 7-stufigen Pipeline - weitere fortgeschrittene Techniken wie die parallele Abarbeitung von bis zu vier Befehlen, Caching und Out-of-Order Execution.

Besonderheiten

 * teilweise sind stark spezialisierte Befehle wie "cttz" (count trailing zeros) teil des Befehlssatzes, die Divisions-Operation (und eine Reihe weiterer Operationen) wird jedoch vom Assembler in entsprechende Befehlssequenzen übersetzt, da der Prozessor die Operation nicht in Hardware implementiert.
 * Speicherzugriffe können prinzipiell nur "aligned" i.e. an 64-Bit Grenzen erfolgen; "unaligned" Zugriffe werden - wenn entsprechend deklariert - vom Assembler entsprechend umgesetzt, oder aber - wenn sie eben nicht als solche deklariert wurden - sie führen zu Laufzeitfehlern.
 * Die Architektur lesitet sich den "Luxus" eines eigenen Registers für die Konstante Null (r31).

Branches
Bei bedingten Sprüngen wird die Sprungbedingung in den Sprungbefehl kodiert, was in kompaktem Code und - da keine Flags geschrieben werden müssen - besserer Parallelisierbarkeit resultiert. Andererseits bringt das aber einen in Hardware vergleichsweise komplexen Befehl mit sich bringt. Subtraktion (bei größer/kleiner/gleich-Vergleichen), Auswertung der Flags und Laden des Sprungziels sind hier ein einziger Befehl.

ATmega 16
Hierbei handelt es sich um eine 8-Bit "RISC"-Architektur mit 32 General-Purpose-Registern. Das Instruction-Set besteht aus 131 Befehlen wovon die meisten in einem Zyklus durchgeführt werden können. In der mir vorliegenden Version kann der CPU mit bis zu 16 MHz getacktet werden. Er besitzt 16K Byte Flashspeicher, 512 Byte EEPROM und 1K Byte SRAM. Arithmentische und Logische Anweisungen haben entweder einen oder zwei Operanden. Klassische Befehle wie "ADD", "SUB", "AND" und dergleichen haben zwei, während "NEG" nur ein Register als Argument annimmt. Die Pipeline ist beim ATmega 16 nur einstufig.

Besonderheiten

 * Alle 32 Register sind direkt mit der ALU verbunden, wodurch eine Anweisung die auf zwei verschiedene Register zugreift, in einem Zyklus ausgeführt werden kann.
 * Der Chip besitzt einen eigenen on-board Multiplikator, der die Berechnung in 2 Zyklen durchführen kann.
 * Es gibt 6 Register, die als drei von einander getrennte 16-Bit Register angesprochen werden köennen (X,Y,Z). Sie dienen zum indirekten adressieren des Datenspeichers.
 * Mehrere Modi um Strom zu sparen. Bei "Power-Down" werden die Register gespeichert und der Oszillator eingefrohren. Bei "Power-Save" läuft der asynchrone Timer weiter. Insgesamt kann der ATmega 16 mit sechs Stromsparmodi aufwarten.
 * Konditionale Befehle die in Abhängigkeit von verschiedenen Flags ausgeführt werden (Zero, Carry, Halfcarry, Negative, T, Overflow).

Branches
Das Instruction-Set des ATmega 16 unterstützt bedingte Sprünge durch eine Vielzahl an Befehlen. Stellvertretend sei hier "BRCC" genannt, der den Sprung durchführt, wenn das Carry-Flage nicht gesetzt ist (Branch if Carry Cleared). Des Weiteren gibt es noch Befehle die auf das Zero-, Carry-, Halfcarry-, Negative-, T- beziehungswiese das Overflowflag Rücksicht nehmen.


text:
Computer Architecture Lab/Winter2006/LechnerWalterStadlerTrinkl/ThreeMicroDiscussion

1. Xilinx PicoBlaze (www.xilinx.com/picoblaze)
Xilinx Picoblaze is an 8-bit RISC microcontroller core optimized for the Spartan- and Virtex-FPGAs. PicoBlaze is delivered as free source level VHDL and can be used royalty-free. It was designed for low power consumption and low resource usage.

Memory
1K of instruction loaded during FPGA configuration and 64-byte internal RAM

I/O
256 input and 256 outport ports where each is 8-bit width. The individual output ports are addressed with the 8-bit address value. Data can be transferred from registers to ports or vice versa.

Registers
The processor support 16 general-purpose 8-bit registers.

Pipeline
The processor has no pipelining.

Interrupts
The interrupt vector is located at address 0xFF. When an interrupt occurs and interrupts are enabled the PC is set to this address. An interrupt pushes the program counter and the values of the Carry and Zero flags on the stack. They are restored by the RETURNI instruction.

Instruction set
The instruction set is grouped into the Program Control Group, Logical Group, Arithemtic Group, Shift and Rotate Group, Input/Output Group and Interrupt Group. In total the processor supports 59 instructions counting all variants, i.e. JUMP and JUMPZ are counted as different instructions. All instructions execute in 2 clock cycles and are of 16bit width. A list of all instructions is given below:

Programm control group
The programm control group includes instructions for branching (JUMP), calling subroutines (CALL) and returning from subroutines(RETURN) and interrupts(RETURNI). All instructions support an optional argument like Z(zero), NZ(not zero), C(carry) and NC(no carry) which make the instructions conditional. An example of the JUMP instruction is given below.

The JUMP instruction is conditional an can be skipped if either the CARRY or ZERO flag is set. The address space is fixed to 256 locations making the PC 8-bits wide.

JUMP instruction Bit 12 ... 0 = UNCONDITIONAL, 1 = CONDITIONAL

Bit 11:10 ( 00 = If Zero, 01 = If not Zero, 10 = If Carry, 11 = If not carry )

Logical Group
The logical group includes boolean functions like AND(0001), OR(0010) and XOR(0011). In addtion a LOAD instruction is available which loads a register either with a constant or the value from another register. The instruction code is somewhat strange because the four bits which identify the instruction are either bit 12:15 or bit 0:3.

AND, OR, XOR and LOAD using constant as source.

AND, OR, XOR and LOAD using other register are source.

Arithmetic Group
This group includes the arithmetic functions ADD(0100) and SUB(0110). Both instructions supports registers and constants. In addtion two variants ADDCY(0101) and SUBCY(0111) supporting the carry bit are available. The coding is the same as for the instruction of the logical group and is therefore not repeated here.

Shift and Rotate Group
The shift and rotate group includes four logical shift instructions SR0(110), SR1(111), SL0(110) and SL1(111). The shift either to the right (R) or to the left(L) where the value shifted in is either 0 or 1. In addition a Rotate Right RR(100) and Rotate Left (RL) instruction is available. Furthermore one arithmetic variant SLA(000) and SRA(000) and a special instruction SLX(100) and SRX(100) is present. The purpose of the SRX and SLX instruction is doubtful to the author because it shifts either to the right or to the left but uses the highest bit as shift value.

Left/Right Shift and Rotate instructions

Input and Output Group
The INPUT(1010 for constant, 1011 for register) transfers data values from the external interface to the PicoBlaze core. The port address is in the range from 0 to 255. The address is either a constant or specified in a register.

Input instruction using constant as source

Input instruction using register as source

The OUTPUT(1110) instruction has the same conding but the destination register is now the source register for the value written to the port.

Memory
The ATMega8 has 8K Bytes of In-System Self-Programmable Flash, 512 Bytes EEPROM and 1K Byte Internal SRAM

I/O
The microcontroller has 23 programmable IO pins which can be used for various functions. These include for example a UART interface, a master/slave SPI interface, ADC converters and a 2 wire interface (I²C). It also does have external interrupt sources.

Registers
The microcontroller supports 32 x 8 general purpose working registers. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing

Pipeline
The processor is single level pipelined, meaning that one instruction is beeing executed while another one is beeing fetched from the programm memory.

Instruction set
The instruction lenght varies from 16 to 32 Bit although most instructions are 16 Bit wide. It consists of 130 instructions which are grouped into the following sections: Arithmetic and logic instructions, Branch instructions, Data transfer instructions, Bit and Bit-test instructions and MCU control instructions. Most instructions are executed in a single cycle but it can take up to 5 cycles for certain instructions to execute. An example is given for each group.

Arithmetic and Logic instructions
The MUL instruction performs an unsigned multiplication with register Rd and register Rr. The 16 Bit output is saved to R1 (Highbyte) and R0 (Lowbyte);

Branch instructions
The RJMP instruction executes a relative jump to an address within PC - 2k + 1 and PC + 2k.

Data transfer instructions
The MOV instruction copies the content of one register into another.

Bit and Bit-test instructions
The SBI instruction sets s specifed bit in an I/O register. The instruction operates on the lower 32 I/O registers addresses 0-31.

MCU control instructions
This instruction sets the device into sleep mode for one cycle.

3. Alpha 21x64
The Alpha architecture is a 64 bit architecture, where all operations are performed on 64 bit wide registers. As all typical RISC processors Alpha constitutes a Load/Store architecture, i.e. data is loaded from memory into registers, then an operation is executed on these registers and finally results are written back on memory. Alpha processors were superscalar from the beginning.

Memory
First Alpha processors had 8K instruction cache and 8K data cache. Later models (e.g. the EV6 versions) had 64K for I-cache and D-cache, respectively.

I/O
The EV4 processor had 290 I/O pins, the EV6 models had 389 pins and the latest Alpha processors that were shipped (EV7) came up with 1443 pins.

Registers
Each Alpha processor has 32 Integer registers and 32 registers for floating point operations.

Pipeline
The first Alpha processor (EV4) already contained two pipelines: one for integer instructions (7 stages) and one for floating point instructions (10 stages).

Instruction Set
The Alpha ISA is a 3-address archictecture, i.e. most operations have two source registers and one destination registers.

All Alpha instructions are 32 bit wide. There are four different instruction formats. All formats start with a 6 Bit long opcode. Because the register set counts 32 registers (either integer or floating point registers), registers can be addressed with five Bits.

Load and store Instructions
Memory access Instructions contain two registers (Ra and Rb) and a memory displacement. The displacement ist added to the second register (Rb) and the sum forms the memory address that is accessed with the operation.

E.g.: ldq Ra, disp(Rb) Meaning: Load data from memory addess Rb+disp and store it into register Ra.

Conditional Branch Instructions
Branch instructions are needed to jump to a specified instruction of the program. The instruction tests the data contained in register Ra and modifies the program counter with the given displacement.

E.g.: beq Ra, label Meaning: If Ra equals zero then goto the instruction that the label points on.

Operate Instructions
This group of instructions is basically formed by arithmetic and byte manipulation operations. Two source registers and one destination register can be specified. One source register can bit replaced by an eight bit immediate number that is directly encoded within the instruction word.

E.g.: addq Ra, Rb/immediate, Rc Meaning: Add value of Ra and Rb (or immediate value) and write result into register Rc.

PALCode instructions
The abbreviation PAL stand for Priviledged Architecture Library. This instruction format used to specify extended processor functions. The 26 bit wide PALCode function field specifies the operation that should be executed.


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Computer Architecture Lab/Winter2006/LechnerWalterStadlerTrinkl/Workplace

Design decisions
We have choose to do a RISC processor featuring a typical load/store architecture. The only powerful instructions are the load (LD) and store instructions (ST) where we focused on a single-cycle implementation. Some parts of the instructions has been inspired by the ARM architecture which has similar load/store operations. All operations can be conditional. We have chosen to use only general purpose registers where we have given the register R13 to R15 special meanings. Please not that all registers share the same location with the exception of the register R15'.

Register file of RISE processor

Notes: The Link Register R13 is updated with the value of the program counter PC + 2 if the Jump Subroutine instruction is executed. This effectively places the return address in the link register. Notes SR: The Status Register is special because is contains a lot of flags. The lower byte is used to store conditionals and the high byte is used for interrupt handling (Not implemented):

Status Register

Pipeline stages

 * Instruction fetch: Fetches instructions from program memory.
 * Instruction decode and Register fetch
 * Execution
 * Memory Access
 * Write back

Instruction decode and Argument fetch stages could probably be combined in one single stage.

Interrupt Handling (Feature)
The processor supports eight external interrupt sources INT0 to INT7. If an external interrupt pin is high the value of the interrupt source is compared with the priority level in the status register. If it is greater than or equal to the level and the global Disable Interrupt bit in the status registers is cleared an interrupt is generated.

Interrupt are only handled at the end of the currently executing instruction. If an interrupt is handled the return address is placed in the link register (LR) and the current value of the status register (SR) is copied into the backup status register (R15'). In the next step the processor loads the address stored at 0x0000 + 2*IRQ_NR into its program counter. In addition the interrupt disable flag in the status register (Bit 15) is set which disables any further interrupts. IRQ_HANDLE: st sr, [sp] add sp, #1 st r1, [sp] add sp, #1

/* do something here touching only r1*/ sub sp, #1 ld r1, [sp] sub sp, #1 ld sr, [sp]    /* Restore status register from stack. */ ldm pc, lr      /* Return from ISR with mode switch (copies backup SR (R15') to SR */

The conditional flags
Almost all instructions support the usage of conditonals. Conditionals specify if the instruction should be executed depending on the current value of the status registers. The following conditionals are supported:
 * 000b: Uncoditional:
 * 001b: NZ ( Not Equal != 0 )
 * 010b: Z ( Equal = 0)
 * 011b: C ( Carry )
 * 100b: N ( Negative < 0)
 * 101b: O ( Overflow )
 * 110b: Z, N (Zero or Negative)

Open Questions
These Questions are open and must be worked out:

 * What about interrupt support in the feature. If an interrupt occurs it must be possible to save the processor status register and the other registers on something like a stack without corrupting the other registers.

Load Immediate
The load immediate instruction loads a 8-Bit constant into the destination register. Depending upon the value of lhb (Load High Byte) the value is either stored in the high or low byte of the register. If the low byte is accessed the high byte is set to zero. Otherwise loading of small constants, which is very frequent, couldn't be done in one instruction. If the high byte is written the low byte remains unchanged.

Format of Load Immediate instruction

Semantics: If lhb(Load High Byte) is zero the value is stored in the low byte of rX. If lhb is set the value is stored in the high byte of rX. This functions does not affect the status register. For example to load ANY 16-Bit constant the following assembler code is sufficient: ld  rX, #LO8(IMM16) ; Load low byte of IMM16 into rX. ldhb rX, #HI8(IMM16) ; Load high byte of IMM16 into rX.

Syntax: ld rX, #IMM8 to load an 8-Bit immediate into rX.  ldhb rX, #IMM8 to load an 8-Bit immediate into the high byte of rX.

Load Indirect with Displacement
The Load Indirect with Displacement instruction, abbr. ld rX, rZ[rY] adds the value of rZ to the value of the register rY. The resulting address is then used to fetch the operand from memory with the result beeing stored in rX.

Format of Load Indirect with Displacement

Notes: Only the lower 2bits of rZ are encoded in the instruction. On instruction decode the value is constructed by using the value rZ prefixed by 00b. That is valid registers value for rZ are r0:r3 = 00XX. Semantics: The value of rZ is added to the value of rY. The resulting address is then used to fetch an operand from memory and the result is stored in rX. Depending upon cond the function is either conditional or not. Syntax: ld{COND} rX, rZ[rY]

Load Indirect with Displacement and Mode Switch
The Load Indirect with Displacement and Mode Switch instruction works equally to the Load Indirect with Displacement instruction. But additionally this instruction copies the backup SR (R15') into the real SR. This is needed i.e. when leaving an interrupt service routine.

Format of Load Indirect with Displacement and Mode Switch

Syntax: ldm{COND} rX, rZ[rY]

Load Indirect {with Mode Switch}
This Load Indirect function, abbr. ld{m} rX, [rY] is implemented by the Load Indirect with Displacement function by using r0 as displacement register. This functionallity is implemented into the assembler which generates a instruction for ld{m} rX, r0[rY].

Load Register Register
The Load Register with Register instruction, abbr. ld rX, rY stores the value of rY in rX.

Format of Load Register with Register

Semantics: The value of rY is copied into rX. Depending upon cond the instruction is either conditional or not. Syntax: ld{COND} rX, rY Note: Please note that the instruction format is the same as for the general instructions but because it is a load instruction is has been placed here.

Store Indirect
This Store Indirect function, abbr. st rX, [rY] is implemented by the Store Indirect with Displacement function by using r0 as displacement register. This functionallity is implemented into the assembler which generates a instruction for st rX, r0[rY].

Store Indirect with Displacement
The Store Indirect with Displacement instruction, abbr. st rX, rZ[rY] adds the value of rZ to the value of the register rZ. The resulting address is then used to store the value of rX.

Format of Store Indirect with Displacement

Notes: Only the lower 2bits of rZ are encoded in the instruction. On instruction decode the value is constructed by using the value rZ prefixed by 10b. That is valid registers value for rZ are r11:r8 = 10XX. Semantics: The value of rZ is added to the value of rY. The resulting address is then used to store the value of rX to. Depending upon cond the function is either conditional or not. Syntax: st{COND} rX, rZ[rY]

Other instructions
All other instructions are of the format shown below.

General instruction for Register-Register Operation

or

General instruction for Register-Immediate Operation

Arithmetic
All arithmetic instructions work on 16-bit signed values.

Arithmetic Instructions

Notes: Arithmetic left shift instruction seems to be redundant since the produced result doesn't differ from a logical left shift. Though we think a arithmetic left shift make sense because a logical left shift wouldn't update the overflow bit in the status register.

Logical
Logical Instructions

Program Control
Subroutine instructions

Other
Other Instructions

Tool Chain
We have ported the GNU binutils which include assembler, linker and other tools for our processor. You can get download our patch from here (patch-rise-1.5.gz). In addition some assembler source are available my here.

Installing the port (Users)
Download binutils 2.17 and unpack it into a directory. Switch to this directory and apply our patch and build the toolchain. $ tar -jxf binutils-2.17.tar.bz2 $ cd binutils-2.17 $ patch -p1 < ../patch-rise-1.3 ... $ ./configure --prefix=/opt/gcc-rise --target=rise $ make && make install

Installing the port (Developers)
The port uses CGEN as a framework for building the assembler, disassembler. Non CGEN specific parts include BFD/ELF support and Autoconf/Automake stuff but changeing them is rarely necessary. First download cgen and unpack it into a directory. Then copy the subdirectory 'cgen' into the binutils directory. Finally configure must be called with --enable-cgen-main to support updating the processor description. $ tar -jxf ../sources/cgen-20061014.tar.bz2 $ cp -Rpf src/cgen binutils-2.17 $ ./configure --prefix=/opt/gcc-rise --target=rise --enable-cgen-maint $ make && make install Now build the toolchain to test if everything worked out okay.

Adding new opcodes
In this example we are going to add a new opcode for loading an immediate value into a register to the processor. Open the file 'cpu/rise.cpu' in an editor and add the following piece of code at the end: (dni ldid "Load Indirect with Displacement"     "ld${cond1} $dr,$dr2[$sr]"   (+ OPC_3_LD_IN_DISP cond1 dr2 dr sr )   (nop)    ) The second line is the assembler syntax and the third list is the actual encoding of the instruction. cond1, $dr, %dr2 and $sr are defined as operands in rise.cpu. OPC_3 is defined as an enum type. If you have finished updating the CPU file change to the opcode directory and call 'make stamp-rise'. This calls CGEN and rebuilds the input source files for the GNU assembler. $ make stamp-rise ... Generating rise desc.h ... Generating rise desc.c ... Generating rise-opc.h ... Generating rise-opc.c ... Generating rise-ibld.in ... Generating rise-asm.in ... Generating rise-dis.in ... Generating rise-opinst.c ... touch stamp-rise make[1]: Leaving directory `binutils-2.17/opcodes' $ Now switch to the top-level directory and rebuild the tools. You can test the new tools without installing them by calling 'gas/as-new' and 'binutils/objdump'.

Common problems

 * Changes in the BFD (e.g. archures.c) subdirectory require calling 'make headers' within this directory.
 * If you get an error like .././opcodes/cgen.sh: line 96: guile: command not found during make stamp-rise you have to install guile.

Using it
You can test the port with the following assembler source code. .text ld     r5,addrlo(stack) ldhb   r5,addrhi(stack)

/* an absolute call. */   ld      r2,addrlo(func1) ldhb   r2,addrhi(func1) ld     pc, r2

/* a PC relative call. */   ld      r2, #( ( 1f - func2 ) & 0xFF ) ldhb   r2, #( ( ( 1f - func2 ) >> 8 ) & 0xFF ) /* store return address in link register */ ld     lr, #(1f + 0x02) 1:   ld      pc, r2[pc]

nop

func1: ld     pc, lr

func2: ld     pc, lr The source file must then be compiled by the assembler rise-as and liked with rise-ld to resolve the symbols. This is done with the following steps: $ rise-as simple.s -o simple.o $ rise-ld simple.o -o simple The result can then be disassembling again by calling rise-objdump. $ ./binutils/objdump -d demo.o

demo.o:    file format elf32-rise

Disassembly of section .text:

00000000 : 0:  85 00           ld R5,#0x0 2:  8d 00           ldhb R5,#0x0 4:  80 12           ld R0,#0x12 6:  88 00           ldhb R0,#0x0 8:  10 38           ld R7,R0 a:  80 fa           ld R0,#0xfa c:  88 ff           ldhb R0,#0xff e:  a1 c7           ld R7,R0[R7] ...

00000012 : 12:   10 3e           ld R7,R6

00000014 : 14:   10 3e           ld R7,R6 $

Another demo program for testing the compiler:

.text /* an absolute call. */   ld      r2,addrlo(func1) ldhb   r2,addrhi(func1) jmp    r2

nop nop

/* a PC relative call. */   ld      r2, #( ( func2 - 1f ) & 0xFF ) ldhb   r2, #( ( ( func2 - 1f ) >> 8 ) & 0xFF )

/* store return address in link register */ ld     lr, #(1f + 0x02) 1:   ld      pc, r2[pc]

nop

/* arithmetic test block */ func1: /* add r1 with Immediate 0x03 */ add    r1,#03 ars	   r2,r1 neg	   r3,r2 /* add if r3 negative */ addn   r3,r2 ars    r4,r3 /* sub if r4 not zero */ subnz  r4,#01 neg    r4,r4 sub    r2,r4 ld     pc, lr

/* logical test block */ func2: and    r1,r2 /* not if overflow */ noto   r2,r1 ld     r3,#03 tst    r2    /* right shift if zero or negative */ rszn   r2,r3 eor    r3,r2 ld     r4,#64 tst    r3    eorz    r3,r4 ld     r5,#01 ls     r3,r5 ld     pc, lr

Port Details
The following files have been modified for this port to work:

BFD specific parts
A BFD ELF backend is required for storing object files on the disc. In additions it handles all the low levels stuff like relocations, ...

 * bfd/aclocal.m4, bfd/configure, bfd/doc/Makefile.in, bfd/Makefile.in, bfd/po/Makefile.in, bfd/config.h, bfd/targmatch.h, bfd/elf32-target.h: Autogenerated
 * bfd/configure.in: Add support for or --target=rise.
 * bfd/config.bfd: Add target vector
 * bfd/cpu-rise.c: CPU architecture and name
 * bfd/elf32-rise.c: ELF specific stuff for the architecture.
 * bfd/targets.c: Architecture vector.
 * bfd/Makefile.am: Add sources and dependencies for compilation.
 * bfd/reloc.c: Add support for relocations (Used by high/low bytes of 16-bit addresses).
 * bfd/archures.c: Architecture declaration
 * bfd/bfd.h bfd/bfd-in2.h bfd/bfd-in3.h bfd/bfdver.h: autogenerated by calling make headers in BFD.
 * include/elf/common.h
 * include/elf/rise.h

CGEN/CPU specific parts
This defines the types of instructions and how they are encoded.
 * opcodes/aclocal.m4, opcodes/configure, opcodes/configure.in, opcodes/Makefile.in, opcodes/po/Makefile.in: Autogenerated
 * opcodes/Makefile.am: Add support for our target.
 * opcodes/disassemble.c: Call disassemble function for our target.
 * cpu/rise.cpu: CPU description - Most important file. Add new instructions here.
 * cpu/rise.opc: Special handling/parsing for opcodes.
 * include/dis-asm.h: Prototype for disassemble function.
 * opcodes/rise-asm.c opcodes/rise-desc.c opcodes/rise-desc.h opcodes/rise-dis.c opcodes/rise-ibld.c opcodes/rise-opc.c opcodes/rise-opc.h opcodes/rise-opinst.c: Auto generated by CGEN from rise.cpu and rise.opc for our CPU.

GNU assembler specific parts

 * gas/aclocal.m4, gas/configure: Autogenerated
 * gas/configure.in: Add support for or --target=rise.
 * gas/configure.tgt: Add the cpu and the generic target. Define the endianness and the BFD format.
 * gas/Makefile.am: Add sources.
 * gas/config/tc-rise.c: Special assembler handling for our target and CGEN setup.
 * gas/config/tc-rise.h: Defines for our target.
 * gas/config/tc-rise.h: Defines for our target.

GNU ld

 * ld/aclocal.m4, ld/Makefile.in
 * ld/configure.tgt
 * ld/Makefile.am
 * ld/emulparams/riseelf.sh: Generates a linker script for our target.

Other parts

 * binutils/readelf.c: Support for disassembling ELF objects for our target.
 * bootstrap.sh
 * config.sub, configure


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Computer Architecture Lab/Winter2006/PoettschacherRosenblattlWolf/ThreeMicroDiscussion

Atmel AVR
AVR stands for „Advanced Virtual RISC“. The AVR is a 8-bit RISC architecture which was designed by the 2 norwegian students Alf-Egil Bogen and Vegard Wollan. It is generally used in microcontrollers.

Details
The AVR uses a Harvard architecture with separate memories and buses for program and data. It implements a single level pipelining. Most operations are performed in a single clock cylce.

Like other RISC architectures, the AVR offers 32 8-bit general purpose working registers (R0 – R31) with single cycle access time. This allows single-cycle ALU operations. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the general purpose working registers can be used as three 16-bit indirect address register pointers for Data Space addressing

The AVR offers conditional and unconditional jump and call instructions, with which the whole address space can be addressed directly.

Instruction set
The AVR’s instruction set is register-register type. It can be divided into 5 categories.
 * ARITHMETIC AND LOGIC INSTRUCTIONS
 * BRANCH INSTRUCTIONS
 * DATA TRANSFER INSTRUCTIONS
 * BIT AND BIT-TEST INSTRUCTIONS
 * MCU CONTROL INSTRUCTIONS

Giving a total of 130 instructions.

The AVR uses two-address format, so the result of the operation performed overwrites one of the operands. Most AVR instructions have a single 16-bit word format and most of them are executed in a single clock cycle.

General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. To achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: Most of the instructions operating on the Register File have direct access to all registers.
 * One 8-bit output operand and one 8-bit result input.
 * Two 8-bit output operands and one 8-bit result input.
 * Two 8-bit output operands and one 16-bit result input.
 * One 16-bit output operand and one 16-bit result input.

DEC Alpha
DEC Alpha is a 64-Bit RISC load-store von Neumann architecture, used in PCs, Workstations and Servers until further development was cancelled in 2003. In contrast to the others, the Alpha architecture is not designed for microcontrollers, so it has no integrated peripherals (e.g. like timers/counters).

Details
Like other non-embedded microprocessors, Alpha is a von Neumann architecture without separation of data and program bus. It has 29 general-purpose integer registers (R0-R28), 31 general-purpose floating-point registers (F0-F31), one data frame pointer register (R29) one stack pointer register (R30) and two special registers (R31 and F31) reading always as integer and floating-point zero. All registers and busses are 64 bit wide, allowing to address up to 16 exabyte of memory. The floating-point registers follow the IEEE 754-1985 format for single and double precision.

A feature of the Alpha architecture is the lack of a program status register. All instructions operate on registers only, allowing instruction parallelisation without the bottleneck of a single flag register. Together with 7-13 pipeline steps (version-dependent) and the ability of out-of-order execution in version EV6 and above, Alpha was one of the fastest systems available until further development was cancelled.

Implementations of Alpha stared with version EV4 (developed by Digital Equipment Corp) in 1992 running at 192 MHz and ended with Version EV7z (developed by HP) in 2002 running at up to 1300 MHz.

For details, see http://en.wikipedia.org/wiki/DEC_Alpha and The Alpha Architecture Handbook

Instruction Set
Every instruction is 32 Bits wide and exist in four flavours, described below:

PALcodes
The Priviledged Architecture Library (PAL) is an operating-system-dependent set of subroutines, callable by software or hardware.

Branches
Depending on the value of the register Ra, a branch is executed according to the displacement parameter.

Memory Access
One of the registers Ra or Rb is the base address of the memory accessed, possibly extendend by the Displacement. The other register is either loaded with the value of the memory address or stored to the memory address.

Operations
Alpha uses three-address format, so the three registers Ra, Rb and Rc are accessed. All registers used have to be either integer registers or floating-point registers.

Infineon TriCore
The Infineon TriCore architecture is very complex and has a huge feature set, which includes
 * 32-bit architecture
 * RISC with DSP instructions
 * Little-endian byte ordering
 * 4-GByte virtual or physical data, program, and input/output address spaces
 * Full-featured memory management system
 * Memory protection
 * 16-/32-bit instructions for reduced code size
 * Fast automatic context switching between two tasks
 * Multiply-accumulate unit
 * Saturating integer arithmetic
 * Bit handling
 * Byte and bit addressing
 * Packed data operations
 * Zero-overhead loop
 * Low interrupt latency
 * Flexible interrupt prioritization scheme
 * Flexible power management

Currently, there exist two versions of the TriCore architecture, we will deal with version 1.3, which is also used in the current microcontrollers like the TC1796.

All TriCore microcontrollers have large on-chip memory blocks of RAM, ROM, DRAM, OTP, FLASH of different types.

Details
The architecture is mainly a harvard architecture, although the busses are not strictly separated and have bridges for flexible data exchange (with performance penalty). As example we looked at the TC1796, the biggest and most powerful microcontroller of the TriCore family.

The CPU has a 64 bit wide bus to the program memory interface (PMI) which has 48 kb of scratch pad ram and 16 kb of instruction cache which runs with full cpu speed (up to 150 MHz). Both memories are optionally parity protected. Over the program local memory bus the PMI is connected to the program memory unit as well as to the data memory unit and the external bus unit. The program local memory bus also runs at full cpu speed and is 64 bit wide.

The program memory unit hast 64 bit wide access to the 2 MB program flash as well as to the 128 KB data flash, 8 KB boot ROM and 8 KB test ROM. All flash ROMs are ECC protected using 8 ECC bits for each block of 64 bits of data, enabling correction of one bit error and detection of two bit errors per block.

Two 64 bit wide buses connect the CPU with the data memory interface (DMI) which has 56 KB of local data RAM and 8 KB of dual ported ram which is connected to the second master channel of the onboard DMA controller. Both memories are optionally parity protected. Via the data local memory bus, the DMI can access the data memory unit which has 64 KB of SRAM and 16 KB of Stand-by RAM. Also, both are optionally parity protected.

Internal peripherals are connected to the system peripherals bus and can be accessed either by the CPU slave interface or the data local memory bus over the LFI-Bridge. Both, the interface and the bridge can be master of the bus as well as the first master channel of the onboard DMA controller. The second master channel of the DMA controller is connected to the remote peripheral bus which connects additional onboard peripherals and the dual ported ram of the DMI. The system peripheral bus and the remote peripheral bus run with the system clock, which runs at the same speed or at a fraction of the CPU speed. The maximum speed is 75 MHz.

For details, see http://www.infineon.com/cgi-bin/ifx/portal/ep/programView.do?channelId=-64423&programId=33110&programPage=%2Fep%2Fprogram%2Fdocument.jsp&pageTypeId=17099

Instruction set
The instruction set splits up into eight categories with a total of more than 150 instructions.
 * Branch
 * Arithmetic (Integer, DSP and SIMD Packed Arithmetic)
 * Load/Store
 * Comparison
 * System
 * Bit Manipulation
 * 16-Bit Subset
 * Address Arithmetic and Address Comparison

Most instructions are 32 bit wide, some are 16 bit. Most instructions have two or three operands.

CPU internals
The CPU has 16 32 bit data registers and 16 32 bit address registers as well as three status and program counter registers. All registers are also refered to be the context of the running task and can be saved to and loaded from the local data ram for context switching. There exist shadow registers to enable fast context switching.

Most instructions are executed within one CPU cycle, some within 2 or 3 cycles. Branches are executed within 1, 2 or 3 cycles, depending on the branch prediction.

Pipelines
Instructions are fetched by the instruction fetch unit which directs the instruction to the appropriate pipeline. The three pipelines are: The integer and the load/store pipeline have four stages (fetch, decode, execute and write-back), the loop pipeline has two stages (decode and write-back). All pipelines work in parallel, enabling three instructions to be executed within one clock cycle.
 * Integer pipeline
 * Load/store pipeline
 * Loop pipeline


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Computer Architecture Lab/Winter2006/PoettschacherRosenblattlWolf/iMISC

iMISC - invertable Minimized Instruction Set Computer
The basic idea is to design a microprocessor that is able to perform all mandatory operations while reducing the usually rather rich RISC instruction set to a minimum.

Features

 * CPU Architecture: RISC
 * Memory Architecture: Harvard
 * Number of Opcodes: 14
 * Number of Commands: 21
 * Pipeline Stages: 4 + Writeback
 * Branch Delay: 1 Cycle
 * Command execution: 1 Tick
 * Data Width: 16 bit
 * Registers: 32 16-bit Registers (29 for general purpose)
 * Addressable object size: 16-bit word
 * Ram address width: 16 bit
 * Ram size: up to 128 kb
 * Rom address width: 16 bit
 * Rom size: up to 128 kb

Specifications on Target (Altera Cyclone EP1C12Q240C8):
 * Logic Cells: about 1100 (with UART, depending on ROM size)
 * Total Memory Bits: 8704 + Rom
 * f_max: about 84 MHz (with most optimizations, depending on ROM size)

Design Decisions
To minimize the instruction set we decided to use only three bits for the opcode, limiting them to eight different opcodes. To keep the overall design simple, we have chosen to implement a load/store harvard architecture. Currently, the design specifies a 16 bit cpu with 16 bit address space and 32 16 bit registers, 29 of them are general purpose. Another simplification is the lack of a program status word which normally holds some flags like the carry flag or an overflow flag. Also, there is no dedicated stack pointer. Jumps are performed by writing to the program counter which is a special register.

Registers
The registers are numbered consecutively with a leading R character. The first register is R00. The three special registers are: They have the mnemonics ZERO, IP and PIP.
 * R29 ... Zero register (ZERO)
 * R30 ... Instruction Pointer (IP)
 * R31 ... Previous Instruction Pointer (PIP)

Instruction Set
For the given design, the following instructions are mandatory: also, some form of conditional operation is needed, like
 * MV ... copys the value of one register to another register
 * LD ... loads a value from the given address to the given register
 * ST ... stores a value from a given register to the given address
 * AND, OR, NAND or NOR ... performs a logical (N)AND/(N)OR operation on the two given registers and store the value to a given register
 * ADD or SUB ... adds/subtracts the value of the second register to/from the first register
 * LSL ... performs a left shift on a register
 * LSR ... performs a right shift on a register
 * SKIP ... skips next operation

Although this are just 7 different instructions, we need some more instructions by several reasons. First, we use a harvard architecture, thus we want to separate access to the program memory (FLASH) from access to the data memory (SRAM). To simplify the load/store instructions, we limit them to the data memory, thus we need some way to get constants into a register as the data memory is not initialized. Therefore, we also need an instruction as
 * LDI ... loads a constant to a given register.

Another design decision is that we want to fit every instruction into 16 bit. As three bit are taken by the opcode, 13 bits are left for the parameters. We use 32 registers, thus we need 5 bits per register. This limits the number of parameters to 2, if both parameters of an instruction are register numbers. So instruction like NAND write the result to one of the given source registers. Additionally the LDI instructions cant load a 16 bit constant, so we decided to limit the size of the constant parameter to 8 bit and added a high byte/low byte flag. This leaves only 4 bits left for the register number, so constants can only be loaded into the lower 16 registers. To speed up execution, the AND, OR and NOR instructions are a good idea, although they could be done by software using NAND operations.

Memory-mapped I/O
We implemented access to peripherals as the LED or the UART memory-mapped in the address range from 0x0200 to 0x0203, with the following special addresses:

 * 0x0200: The LED. If the bit 0 of this word is set, the LED goes on, otherwise, it goes off. A read has no effect.
 * 0x0201: UART read. If a byte is received by the UART hardware, it is read at this address in the low byte, with the high byte set to 0x01. If no byte is available, this is always read as 0x0000. A write has no effect.
 * 0x0202: UART write. If the UART write queue is not full, the lower byte of the word written here is transmitted. A read has no effect.
 * 0x0203: UART status. Bit 0 signals the possiblity to write to the UART, bit 1 signals if a byte is ready to be received.

invertability
Finally, and not just to do something different than other designs, we enabled to invert instructions. This just means that by setting the inverted flag (by the SINV instruction), an opposite operation to the next instructions is performed, if possible. This enables to reduce the number of opcodes and enables further optimization within the pipeline. For example, the opposite operation of the LD instruction is the ST instruction. If the inverted flag is not set, only LD is possible, therefore no write back interferance within the pipeline is possible. If the iverted flag is set by the SINV instruction, all following LD instructions become ST instructions, therefore only write back operations may be possible.

Instruction Set of the iMISC architecture
As the mnemonics are used as the following:
 * 0 ... one bit with value zero
 * 1 ... one bit with value one
 * C ... one bit of constant
 * Rs ... one bit of the number of the source register
 * Rd ... one bit of the number of the destination register
 * H/L ... one bit signaling if high or low byte, H is equivalent to 1 and L to 0

Diagram
The following Diagram shows the actual architecture: imisc_architecture.gif

Assembler
The Assembler is the basic instrument to feed the iMISC architecture with machinecode. It is able to output text, binary or vhdl rom code. Also, it performs basic checks on the code. When using a C-Precompiler, assembler code becomes more readable as the iMISC-Assembler was not made to make code looking nice...

Language
The assembler language is mostly comparable to the structure of the binary code, although there are some differences. Mainly, the assembler uses what it gets from the input file and converts it to the binary codeword which is written to the output. As the semantic of a codeword depends on the state of the InvertedFlag, it does not depend which of its representations is used. The basic syntax of an assembler command is as follows: CMD SRC, DST Here, CMD is the command name, SRC is the source may be a register or constant, depending on the command and DST is the destination and therefore again a register. Constants may be in decimal or hexadecimal format (either with leading 0x or h). The registers are named R00 to R31. The use of the special registers may be restricted depending on their meaning. R29 (ZERO) and R31 (PIP) must not be the destination register. R30, the instruction pointer register, may only be written through a move command where the source register is R00. Labels can be placed at the begin of a line and are delimited by a colon. They can be treated like constants (they are converted to 16-bit-addresses). The commands are as follows:

File Structure
A very basic assembler file may look like that: final: LDI HIGH(final), R00 LDI LOW(final), R00 MV R00,R30 This is a simple endless loop which should be placed at the end of every assembler file to prevent the processor to execute unwanted code.

As usual, semicolon can be used for comments. When using a C-Precompiler, some defines may be useful:

 * Convenience defines
 * Convenience defines

 * 1) define ZERO r29
 * 2) define JMP MV R00,R30

final: LDI HIGH(final), R00 LDI LOW(final), R00 JMP

Usage
$ ./as-iMISC.exe --help iMISC assembler, reads from stdin, writes to stdout switches: -t --text  ... create human readable assembler output from input -b --binary ... create binary text from input -v --vhdl  ... create VHDL output from input (default) To run the C preprocessor before assembling (recommended): gcc -x c -E -C -P | ./as-iMISC

Files
All files related to this project are available at http://stud4.tuwien.ac.at/~e0325880/iMISC/. As there are:
 * assembler


text:
Computer Architecture Lab/Winter2006/PolzerJahn/Design

Basic data

 * 16bit RISC CPU
 * 16 internal registers
 * von Neumann architecture
 * 16bit address bus
 * 32bit external data bus
 * two instruction widths (16 bit, 32bit)
 * External memory: 128 kB
 * Connection to a PC: standard serial interface (RS-232)
 * Number format: little endian
 * Signed arithmetic (two's complement)

Instruction set
Note: Instructions which take up 32 bit have an opcode higher than or equal to 0x20.
 * Basic operations:
 * Logical operations:
 * Arithmetic operations:
 * Shift operations:
 * Compare operations:
 * Input/output operations:
 * Jump operations:

Instruction format
8-bit Opcode, two 4-bit register numbers 8-bit Opcode, 4-bit register number (optional), 16 bit immediate value
 * Standard Instruction
 * Extended instruction

Pipeline
SIPS uses a four stage pipeline:
 * fetch
 * decode
 * execute
 * write back

This file contains a detailed graphical description of each stage.


text:
Computer Architecture Lab/Winter2006/PolzerJahn/ThreeMicroDiscussion

Abstract
This document was written for the lecture LU Computer Architecture at the Vienna University of Technology. The aim of this document is to compare three different processor architectures regarding their instruction set and their design.

We have chosen the following three architectures:
 * Intel 8bit micro processor platform (Representative: 8088)
 * Atmel Atmega 8bit micro controller family (Representative: Atmega128)
 * Motorola 68k family (Representative: 68008)

8088, 68008
Those two processors are based on the von Neumann architecture. This architecture uses a common program and data memory. The advantage is that fewer pins are needed on the package with the disadvantage of the so called von Neumann bottleneck.

The problem is that there can be a conflict while accessing the memory. This happens if the processor wants to access the data memory while loading an instruction.

Further on both processors are members of the CISC family. Their philosophy is to support multiple versions of each instruction. Each version uses different operands (registers, intermediates or memory).

This results in a big dispersion of the instructions execution time.

Atmega128
This processor is based on the Harvard architecture. The advantage of this architecture is that there are dedicated program and data memories. Because of this the bottleneck of the von Neumann architecture is avoided.

The Atmega128 is member of the RISC processor family. This family is also known as load/store architecture. The base idea of it is that there are only a few versions of each instruction. Normally the instructions can only applied on registers. Additional there is a load and a store instruction to read and write the register values to the memory.

Because of this architecture the spreading of the instructions execution time is smaller than the one of CISC processors. Further on each instruction has a very short execution time (normally one clock cycle). But there are much more instructions needed to produce the same result as a CISC processor.

A RISC processor normally has a lot of data registers. They are needed because of the instruction's operand limitations.

8088
The Intel 8088 is based on the 8086 as a low-cost-chip, like Celeron today. The prefetch queue was reduced to 4 instead of 6 bytes. It was introduced 1979 and used in the original IBM PC.

The length of an instruction is between one and four bytes long. The first byte contains the operation code and flags. The following bytes contain the operands (register, memory address (different addressing schemes)).

The instructions are sorted to the following groups:
 * Arithmetic
 * Logic
 * String manipulation
 * Control (Comparison and jumps)
 * Processor control (e.g. clearing the flags)

For further details take a look at home.comcast.net/~fbui/intel.html

Atmega128
The length of an instruction is 16 or 32 bit. The first 16 bit contain the opcode and the operands. If a memory location is used literally then the second 16 bits are used as well.

The instructions are sorted to the following groups:
 * Arithmetic
 * Logic & Bit manipulation
 * Transfer
 * Control (Comparison and jumps)

For further details take a look at the Atmel Homepage

68008
The 68008 belongs to the 68k family of Motorola. It is narrowed to the 68000 with a smaller address-bus and data-bus. See the details in the summary-table. The instructions are divided into operations and address modes. Almost all address modes are available for almost all instructions. The minimal instruction size is 16bit. A lot of instructions need extra words to be appended for addresses, address-mode bits, etc. So an instruction consist of at least one word, but some have as many as 11 words. The first word is called "simple effective address operation word" which specifies the length of the instruction, the effective addressing mode, and the operation to be performed. The other words are called "brief and full extension words" which are specifying the instruction and operands.

 * SINGLE EFFECTIVE ADDRESS OPERATION WORD (ONE WORD, SPECIFIES OPERATION AND MODES)
 * SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS)
 * IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS)
 * DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS)

The 68008 provides 14 different address modes and instructions are sorted to the following groups:
 * Arithmetic
 * Logic & Bit manipulation
 * Multiprocessing control
 * Flow of control

For further details take a look at the Freescale Homepage


text:
Wikiversity:Computer Architecture Lab

Note: this section was ust imported from wikibooks. All pages of this project should appear at the same name, but without the "Wikiversity:" at the beginning.

Main page is now Computer Architecture Lab. If more pages exist and need to be imported, leave a note on my talk page on wikibooks. --SB_Johnny | talk 23:18, 23 October 2006 (UTC)

This page should be removed as soon as the templates are corrected on the wikibooks side.

title: Wikiversity:Computer Architecture Lab


text: Category:Hunter-gatherers project

title: Category:Hunter-gatherers project


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Template:Sampletest/A

This will be A's answer

title: Template:Sampletest/A


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User:Ferrous~enwikiversity

I am me. That's about all you need to know.

I wrote the Properties of Matter page for the School of Chemistry. Please take a look and feel free to add on.

title: User:Ferrous~enwikiversity


text:
Template:Sampletest/D

This will be D's answer

title: Template:Sampletest/D


text:
Template:Sampletest/C

This will be C's answer

title: Template:Sampletest/C


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Template:Sampletest/B

This will be B's answer

title: Template:Sampletest/B


text:
Template talk:Sampletest

What I am trying to do twith this thing:

Once I get the code working, this can serve as an exampole of how to create other template based tests. When a teacher wishes to give a test, the Question subpages can be edited, and the template placed on the user pages of the test takers. Once the test takers have edited accordingly, the "teacher" can then edit the answers in and take grades by looking at the revision of the students template at the time the answers were given. Eventually, with the random question function, random test could be generated, and the exp class could be used to calculate scores.... that is if i can figure out why it won't work.--Rayc 00:40, 24 October 2006 (UTC)

title: Template talk:Sampletest


text:
Emergency medical responder (EMR)/Human anatomy

The human anatomy for the EMR has not yet been started. Study the Anatomical Terminology module which does not exceed the scope of the EMR.