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Trisomy

A trisomy is a type of polysomy in which there are three instances of a particular chromosome, instead of the normal two. A trisomy is a type of aneuploidy (an abnormal number of chromosomes).

Description and causes
Most organisms that reproduce sexually have pairs of chromosomes in each cell, with one chromosome inherited from each parent. In such organisms, a process called meiosis creates cells called gametes (eggs or sperm) that have only one set of chromosomes. The number of chromosomes is different for different species. Humans have 46 chromosomes (i.e. 23 pairs of chromosomes). Human gametes have only 23 chromosomes.

If the chromosome pairs fail to separate properly during cell division, the egg or sperm may end up with a second copy of one of the chromosomes. (See non-disjunction.) If such a gamete results in fertilization and an embryo, the resulting embryo may also have an entire copy of the extra chromosome.

Terminology
The number of chromosomes in the cell where trisomy occurs is represented as, for example, 2n+1 if one chromosome shows trisomy, 2n+1+1 if two show trisomy, etc.
 * "Full trisomy", also called "primary trisomy", means that an entire extra chromosome has been copied.
 * "Partial trisomy" means that there is an extra copy of part of a chromosome.
 * "Secondary trisomy" - the extra chromosome has quadruplicated arms (the arms are identical; it is an "isochromosome").
 * "Tertiary trisomy" - the extra chromosome is made up of copies of arms from two other chromosomes.

Trisomies are sometimes characterised as "autosomal trisomies" (trisomies of the non-sex chromosomes) and "sex-chromosome trisomies." Autosomal trisomies are described by referencing the specific chromosome that has an extra copy. Thus, for example, the presence of an extra chromosome 21, which is found in Down syndrome, is called trisomy 21.

Human trisomy
Trisomies can occur with any chromosome, but often result in miscarriage, rather than live birth. For example, Trisomy 16 is the most common trisomy in human pregnancies, occurring in more than 1% of pregnancies; only those pregnancies in which some normal cells occur in addition to the trisomic cells, or mosaic trisomy 16, survive. This condition, however, usually results in spontaneous miscarriage in the first trimester.

The most common types of autosomal trisomy that survive to birth in humans are:

 * Trisomy 21 (Down syndrome)
 * Trisomy 18 (Edwards syndrome)
 * Trisomy 13 (Patau syndrome)
 * Trisomy 9
 * Trisomy 8 (Warkany syndrome 2)

Of these, Trisomy 21 and Trisomy 18 are the most common. In rare cases, a fetus with Trisomy 13 can survive, giving rise to Patau syndrome. Autosomal trisomy can be associated with birth defects, intellectual disability and shortened life expectancy.

Trisomy of sex chromosomes can also occur and include:

Compared to trisomy of the autosomal chromosomes, trisomy of the sex chromosomes normally has less severe consequences. Individuals may show few or no symptoms and have a normal life expectancy.
 * XXX (Triple X syndrome)
 * XXY (Klinefelter syndrome)
 * XYY (Jacobs syndrome)

title: Trisomy


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Wikipedia:Federal Standard 1037C terms/telecommunication network terms

This is a list of telecommunication network terms derived from the Glossary of Telecommunication Terms published as Federal Standard 1037C. Please see the Federal Standard article for copyright-related issues, as not all parts of the source document are in the public domain.

LANs, MANs and WANs
baseband local area network -- bridge -- brouter -- carrier sense -- Channel service unit -- domain name server -- Ethernet -- fiber distributed data interface (FDDI) -- head end -- Extensible Messaging and Presence Protocol -- LAN application (software) -- lobe attaching unit -- local area network (LAN) -- logical link control sublayer (LLC) -- metropolitan area network (MAN) -- network control program (NCP) -- network interface device (NID) -- network topology -- physical signaling sublayer (PLS) -- ring latency -- ring network -- server -- S interface -- slotted-ring network -- switched multimegabit data services (SMDS) -- tail circuit -- token -- token-bus network -- token passing -- token ring adapter -- truncated binary exponential backoff -- wide area network (WAN)

Layered systems and open architecture
abstract syntax -- encapsulation -- expedited data unit -- GOSIP -- high-level control -- intermediate system -- LAP-B -- layer -- layered system -- logical link control sublayer (LLC) -- medium access control sublayer (MAC) -- n-entity -- network termination 1 (NT1) -- network termination 2 (NT2) -- n-user -- open system -- open systems architecture -- Open Systems Interconnection (OSI) -- Open Systems Interconnection (OSI)--architecture -- Open Systems Interconnection Specification (OSI)--Protocol -- Open Systems Interconnection--Reference Model (OSI--RM) -- Open Systems Interconnection Definitions (OSI)--Service -- Open Systems Interconnection Management (OSI)--Systems -- peer entity -- peer group -- physical signaling sublayer (PLS) -- protocol (computing) -- protocol-control information -- protocol data unit (PDU) -- protocol hierarchy -- service -- service access point (SAP) -- service data unit (SDU) -- SONET -- standardized profile -- Transmission Control Protocol (TCP) -- TCP/IP -- TCP/IP Suite -- terminal endpoint functional group (TE) -- virtual terminal (VT) -- wrapping

Networking
access group -- address field -- asynchronous network -- backbone -- branching network -- client -- closed user group -- commercial refile -- control station -- delayed-delivery facility -- democratically synchronized network -- despotically synchronized network -- differentiating network -- directed net -- distributed control -- distributed network -- distributed-queue dual-bus (DQDB) -- endpoint node -- equivalent network -- free net -- gateway -- global address -- GOSIP -- group address -- hierarchical computer network -- hierarchically synchronized network -- hotline -- hybrid communications network -- hypermedia -- intelligent network (IN) -- intelligent peripheral (IP) -- interconnection -- intermediate element -- internetworking -- interworking functions -- leg -- link -- logical topology -- loop transmission -- maritime broadcast communications net -- master station -- mediation function -- multicast -- multichannel -- multilevel precedence and preemption (MLPP) -- multilink operation -- multiple media -- multipoint access -- net operation -- network -- network control program (NCP) -- network engineering -- network interface -- network interface card -- network topology -- noncentralized operation -- nonsynchronous network -- open network architecture (ONA) -- overhead information -- packet switching -- path -- PCS -- physical topology -- point-to-point link -- polling -- port -- portability -- POSIX -- precedence -- primary channel -- primary station -- public data network (PDN) -- public switched network (PSN) -- radio net -- relay -- remote access -- remote logon -- route -- routine message -- seizing -- server -- service termination point -- signal center -- signal transfer point (STP) -- sliding window -- slot -- slotted-ring network -- slot time -- sublayer -- subnetwork -- switched circuit -- symmetrical channel -- synchronous data link control (SDLC) -- synchronous network -- synchronous transmission -- system failure transfer -- system follow-up -- system signaling and supervision -- tandem -- teleconference -- Terminal Access Controller (TAC) -- terminal adapter -- terminal endpoint functional group (TE) -- through group -- through supergroup -- T-interface -- token-bus network -- token passing -- token-ring network -- trace packet -- unidirectional operation -- U interface -- Universal Personal Telecommunications (UPT) -- virtual network -- virus -- wrapping

Network management
accounting management -- administrative management complex (AMC) -- attribute -- customer management complex -- fault management -- managed object -- network administration -- network management -- network manager -- operations system -- performance management -- security management -- system management -- telecommunications management network (TMN) -- teletraffic engineering

Networks
ARPANet -- Automatic Digital Network (AUTODIN) -- Automatic Secure Voice Communications Network (AUTOSEVOCOM) -- Automatic Voice Network (AUTOVON) -- command net -- common user network -- communications net -- communications network -- computer network -- Defense Communications System (DCS) -- Defense Data Network (DDN) -- Defense Switched Network (DSN) -- Emergency Broadcast System (EBS) -- integrated digital network (IDN) -- The Internet -- joint multichannel trunking and switching system -- Joint Tactical Information Distribution System (JTIDS) -- National Communications System (NCS) -- National Information Infrastructure (NII) -- value-added network (VAN)

Network topology and architecture
client-server architecture -- network architecture -- network connectivity -- network topology -- node -- physical topology -- ring network

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/


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Wikipedia:Federal Standard 1037C terms/telephony terms

This is a list of telephony terms derived from the Glossary of Telecommunication Terms, published as Federal Standard 1037C. Please see the Federal Standard article for copyright-related issues, as not all parts of the source document are in the public domain.

ISDN
access contention – B channel – bearer service – broadband ISDN (B-ISDN) – circuit transfer mode – contribution – customer access – D channel – demand service – digital subscriber line (DSL) – distribution – distribution service – event – frame – functional signaling – H channel – hybrid interface structure – interactive service – interface functionality – interface payload – ISDN – labeled channel – labeled interface structure – labeled multiplexing – labeled statistical channel – LAP-D – messaging service – network element (NE) – network termination – network termination 1 (NT1) – network termination 2 (NT2) – positioned channel – post-production processing – primary rate interface (PRI) – reference configuration – reference point – reserved circuit service – retrieval service – R interface – Signaling System No. 7 (SS7) – S interface – synchronous transfer mode – teleaction service – terminal adapter – T-interface – transfer mode – transit delay – T reference point – U interface – V reference point – wide area network (WAN)

Switching
analog switch – broadband exchange (BEX) – burst switching – call progress signal – circuit-switched data transmission service – circuit switching – class of office – common control – congestion – crosspoint – digital switching – distributed switching – electronic switching system (ESS) – fast packet switching – first-in last-out (FIFO) – interrupted continuous wave (ICW) – joint multichannel trunking and switching system – message switching – multiple access – multiple homing – nonblocking switch – off-hook signal – one-way trunk – pilot-make-busy circuit (PMB) – private exchange (PX) – public switched network (PSN) – public switched NS/EP telecommunications services – public switched telephone network (PSTN) – queuing delay – rotary hunting – seizing – semiautomatic switching system – signal transfer point (STP) – space-division switching – spill forward – split homing – step-by-step switching system (SXS) – switch – switchboard – switch busy hour – switching – synchronous transfer mode – Tactical Automatic Digital Switching System (TADSS) – thin-film optical switch – three-way calling – time-division switching – trunk – wink pulsing

Telephony hardware
acoustic coupler – aerial cable – aerial insert – applique – central office (C.O.) – combined distribution frame (CDF) – common battery – conditioned loop – connecting arrangement – cord circuit – cord lamp – cordless switchboard – crossbar switch – cross-connection – cross-office trunk – customer office terminal (COT) – customer service unit (CSU) – dial switching equipment – digital access and cross-connect system (DACS) – digital circuit patch bay – digital loop carrier (DLC) – digital primary patch bay – digital switch – distribution frame – drop – DSA board – D-type patch bay – electrically powered telephone – embedded base equipment – embedded customer-premises equipment – end instrument – end office – entrance facility – entrance point – entrance room – equal-level patch bay – equipment room – equipment side – exchange – exchange facilities – extension bell – four-wire repeater – grandfathered systems – grandfathered terminal equipment – group distribution frame (GDF) – high-frequency distribution frame (HFDF) – individual line – inside plant – integrated station – intercom – intermediate distribution frame (IDF) – interoffice trunk – interposition trunk – interswitch trunk – intertoll trunk – intraoffice trunk – key set – key telephone system (KTS) – K-type patch bay – limited-protection voice equipment – line side – local battery – local exchange loop – local side – main distribution frame (MDF) – main station – master frequency generator – MM patch bay – new customer premises equipment – office classification – off-premises extension (OPX) – on-premises extension – orderwire multiplex – outside plant – patch and test facility (PTF) – plant – private exchange (PX) – private line – proration – protected distribution system (PDS) – public switched telephone network (PSTN) – rack – repertory dialer – rotary dial – SECORD – semiautomatic switching system – signal center – sound-powered telephone – special grade access line – splice closure – station battery – STU – supergroup distribution frame (SGDF) – switchboard – switched circuit – switched loop – tandem center – tandem office – technical control facility (TCF) – Telecommunications Device for the Deaf (TDD) – telecommunications facilities – telephone – terminal equipment – through-group equipment – through-supergroup equipment – tie trunk – translator – tributary office – videophone – vodas – vogad – voice frequency primary patch bay (VF)


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Talk:Tiling

need to mention Roger Penrose's work on tilings

This has been done a while ago, see tiling page. Karlscherer3 01:35, 19 Jun 2005 (UTC)

" Alternating tilings A tiling {T} of a shape S is called alternating if {T} is the union of two disjoint sets {T1} and {T2} of tiles such that any tile T adjacent to a tile T1 in {T1} is in {T2} and, vice versa, any tile T adjacent to a tile T2 in {T2} is in {T1}. Example : If we want to tile the plane with squares and dominoes in an alternating way, then we must find a way that the plane is fully covered without gaps or overlaps (otherwise it is not a tiling at all) and such that no two squares have a side or a part of a side in common (but having a point in common is allowed) and such that no two dominoes have a side or a part of a side in common (but having a point in common is allowed)1,2. " ''Do all the squares have to be the same size? Do all the dominoes have to be the same size? If so, I don't see how this can be done - can someone expand please.'' -- SGBailey 23:06 Apr 3, 2003 (UTC)

Since this restriction is not requested, I cannot see why you assume that it is to be imposed. If additional restrictions are needed, they would be stated. There is no need to state that some restrictions are NOT given. Using differently sized squares, of course there are solutions to this problem. Karlscherer3 00:09, 19 Jun 2005 (UTC)

What about invariants? For instance, Dehn's invariant can be used to show that three dimensional Euclidean space cannot be tiled with regular tetrahedra. PML.

This article needs pictures and drawings! 213.236.117.2 11:14, 8 Sep 2004 (UTC)

They are coming! I have added already more than 100 images to the pages the "types of tilings" list points to. (see pages on "convex tiling" and "tetrad (tiling)". It all takes a while, since I had to write about 100 pages on puzzles as well. I would like to see more people suppling images! It is also so easy to ask for more... why don't you provide images? Karlscherer3 00:25, 19 Jun 2005 (UTC)

article meandering and off
this article is quite meandering and off. The main issues are not discussed:

 * definition of a tiling.
 * definition of vertexs, edges, and tiles.

 * k-hedral. A tiling is k-hedral if it has k prototiles.
 * k-gonal. A tiling is k-gonal if it has k types of vertices.
 * k-toxal. A tiling is k-toxal if it has k types of edges.

 * consider the number of types of tiles, vertices, edges, with respect to the tiling's symmetry, we have k-isogonal, k-isohedral, k-isotoxal tilings. That is, if the symmetry of the tiling maps the prototiles into k classes, then that tiling is k-isohedral.

Xah Lee 02:53, 2004 Sep 1 (UTC)
 * definition of regular tilings.
 * definition of archimedean tilings.
 * the problem of a tiling of r prototiles admits m number of tilings. If r==m==1, it the prototile is said to be isomorphic. If r==m, it's r-morphic.
 * topological class of tilings.
 * duality
 * aperiodic tilings.

Good suggestions, so why didn't you add them in? I will add your suggestions, but maybe you can help edit the tiling page, because you seem very knowledgable in this area. Any help is welcome and more constructive than suggestions. By the way, aperiodic tilings have their own page, and the link is there. Karlscherer3 00:25, 19 Jun 2005 (UTC)

All fixed now, apart from:
 * the problem of a tiling of r prototiles admits m number of tilings. If r==m==1, it the prototile is said to be isomorphic. If r==m, it's r-morphic.
 * topological class of tilings.
 * duality

First topic: unclear, please explain. All topics: Please give sources where to find these topics in wiki or otherwise. Can someone please fill in the gaps here? Thank you. Karlscherer3 01:31, 19 Jun 2005 (UTC)

Tessellation
What is the difference between tiling and tessellation? --Henrygb 00:36, 25 Mar 2005 (UTC)

This has been answered in the amended tiling page now. Karlscherer3 23:54, 18 Jun 2005 (UTC)

wallpaper groups
There exists an article on Wallpaper groups. The tiling article and Wallpaper groups should mention each other. Dmharvey 19:35, 30 May 2005 (UTC)

Thanks for the reference. I will do this. Karlscherer3 23:55, 18 Jun 2005 (UTC)

Alhambra symmetries
The article says examples of all 17 wallpaper groups can be found at the Alhambra. Does this rely on coloring to break a higher geometric symmetry? Can we confirm this with photographs?

B. Grünbaum, and later B. Grünbaum, Z. Grünbaum, & G. C. Shephard, assert that p2 and p3m1 are not found at the Alhambra, but do appear nearby in Toleda from about the same period; however pg and pgg are completely missing from Islamic art of the time. Contradicting this is an article by R. Pérez-Gómez entitled "The four regular mosaics missing in The Alhambra", asserting that the missing groups are not missing.

Not having copies of these articles, nor photographs to support the claim of 17, unlike the claim of 13, I'd like to see something definitive.

Anyone? KSmrq 21:38, 10 Jun 2005 (UTC)

Good news, partly. I found online a comment by Coxeter saying he accepts that 16 of the 17 groups appear, based on the Pérez-Gómez article. The only copy of that article I have found has pictures which are impossible to decipher; but I'm willing to trust this expert opinion. And given that the final missing group is reported nearby in Toledo, I'll let the current claim stand. KSmrq 18:05, 25 Jun 2005 (UTC)

Terminology
With regard to the notice about "abnormal terminology", I think the proper source for choosing preferred terminology would be Grünbaum and Shephard, Tilings and Patterns, which still serves as the standard work in the area although largely written in the 1970s. For example, "Neat tilings" should be "edge-to-edge", "Nowhere-neat tilings" should probably be "unilateral", "Polysquares" should be "Polyominoes" without mention of the nonstandard term "Polysquares" (there is no tiling content in that section at present, but tiling with polyominoes is a legitimate topic to discuss here), "Pure tilings" should be "monohedral", and concepts described in the article which are not discussed in Tilings and Patterns may not be important enough to cover unless referenced to multiple articles reviewed in Math Reviews. Joseph Myers 19:09, 23 Jun 2005 (UTC)

Note
Karl Scherer's edits to Wikipedia appear to be predominantly original research, and have been removed in accordance with VfD at
 * Votes for deletion/Karl Scherer
 * Votes for deletion/Zillions games

3 July 2005 17:42 (UTC)

title: Talk:Tiling


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Moore's law

Moore's law is the observation that the number of transistors in an integrated circuit (IC) doubles about every two years. Moore's law is an observation and projection of a historical trend. Rather than a law of physics, it is an empirical relationship linked to gains from experience in production.

The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and Intel (and former CEO of the latter), who in 1965 posited a doubling every year in the number of components per integrated circuit, and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years, a compound annual growth rate (CAGR) of 41%. While Moore did not use empirical evidence in forecasting that the historical trend would continue, his prediction has held since 1975 and has since become known as a "law".

Moore's prediction has been used in the semiconductor industry to guide long-term planning and to set targets for research and development, thus functioning to some extent as a self-fulfilling prophecy. Advancements in digital electronics, such as the reduction in quality-adjusted microprocessor prices, the increase in memory capacity (RAM and flash), the improvement of sensors, and even the number and size of pixels in digital cameras, are strongly linked to Moore's law. These ongoing changes in digital electronics have been a driving force of technological and social change, productivity, and economic growth.

Industry experts have not reached a consensus on exactly when Moore's law will cease to apply. Microprocessor architects report that semiconductor advancement has slowed industry-wide since around 2010, slightly below the pace predicted by Moore's law. In September 2022, Nvidia CEO Jensen Huang considered Moore's law dead, while Intel CEO Pat Gelsinger was of the opposite view.

History
In 1959, Douglas Engelbart studied the projected downscaling of integrated circuit (IC) size, publishing his results in the article "Microelectronics, and the Art of Similitude". Engelbart presented his findings at the 1960 International Solid-State Circuits Conference, where Moore was present in the audience.

In 1965, Gordon Moore, who at the time was working as the director of research and development at Fairchild Semiconductor, was asked to contribute to the thirty-fifth anniversary issue of Electronics magazine with a prediction on the future of the semiconductor components industry over the next ten years. His response was a brief article entitled "Cramming more components onto integrated circuits". Within his editorial, he speculated that by 1975 it would be possible to contain as many as 65,000 components on a single quarter-square-inch (~1.6 square-centimeter) semiconductor.

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."

Moore posited a log-linear relationship between device complexity (higher circuit density at reduced cost) and time. In a 2015 interview, Moore noted of the 1965 article: "...I just did a wild extrapolation saying it's going to continue to double every year for the next 10 years." One historian of the law cites Stigler's law of eponymy, to introduce the fact that the regular doubling of components was known to many working in the field.

In 1974, Robert H. Dennard at IBM recognized the rapid MOSFET scaling technology and formulated what became known as Dennard scaling, which describes that as MOS transistors get smaller, their power density stays constant such that the power use remains in proportion with area. Evidence from the semiconductor industry shows that this inverse relationship between power density and areal density broke down in the mid-2000s.

At the 1975 IEEE International Electron Devices Meeting, Moore revised his forecast rate, predicting semiconductor complexity would continue to double annually until about 1980, after which it would decrease to a rate of doubling approximately every two years. He outlined several contributing factors for this exponential behavior:
 * The advent of metal–oxide–semiconductor (MOS) technology
 * The exponential rate of increase in die sizes, coupled with a decrease in defective densities, with the result that semiconductor manufacturers could work with larger areas without losing reduction yields
 * Finer minimum dimensions
 * What Moore called "circuit and device cleverness"

Shortly after 1975, Caltech professor Carver Mead popularized the term "Moore's law". Moore's law eventually came to be widely accepted as a goal for the semiconductor industry, and it was cited by competitive semiconductor manufacturers as they strove to increase processing power. Moore viewed his eponymous law as surprising and optimistic: "Moore's law is a violation of Murphy's law. Everything gets better and better." The observation was even seen as a self-fulfilling prophecy.

The doubling period is often misquoted as 18 months because of a separate prediction by Moore's colleague, Intel executive David House. In 1975, House noted that Moore's revised law of doubling transistor count every 2 years in turn implied that computer chip performance would roughly double every 18 months (with no increase in power consumption). Mathematically, Moore's law predicted that transistor count would double every 2 years due to shrinking transistor dimensions and other improvements. As a consequence of shrinking dimensions, Dennard scaling predicted that power consumption per unit area would remain constant. Combining these effects, David House deduced that computer chip performance would roughly double every 18 months. Also due to Dennard scaling, this increased performance would not be accompanied by increased power, i.e., the energy-efficiency of silicon-based computer chips roughly doubles every 18 months. Dennard scaling ended in the 2000s. Koomey later showed that a similar rate of efficiency improvement predated silicon chips and Moore's law, for technologies such as vacuum tubes.

Microprocessor architects report that since around 2010, semiconductor advancement has slowed industry-wide below the pace predicted by Moore's law. Brian Krzanich, the former CEO of Intel, cited Moore's 1975 revision as a precedent for the current deceleration, which results from technical challenges and is "a natural part of the history of Moore's law". The rate of improvement in physical dimensions known as Dennard scaling also ended in the mid-2000s. As a result, much of the semiconductor industry has shifted its focus to the needs of major computing applications rather than semiconductor scaling. Nevertheless, leading semiconductor manufacturers TSMC and Samsung Electronics have claimed to keep pace with Moore's law    with 10, 7, and 5 nm nodes in mass production.

Moore's second law
As the cost of computer power to the consumer falls, the cost for producers to fulfill Moore's law follows an opposite trend: R&D, manufacturing, and test costs have increased steadily with each new generation of chips. The cost of the tools, principally EUVL (Extreme ultraviolet lithography), used to manufacture chips doubles every 4 years. Rising manufacturing costs are an important consideration for the sustaining of Moore's law. This led to the formulation of Moore's second law, also called Rock's law (named after Arthur Rock), which is that the capital cost of a semiconductor fabrication plant also increases exponentially over time.

Major enabling factors

Numerous innovations by scientists and engineers have sustained Moore's law since the beginning of the IC era. Some of the key innovations are listed below, as examples of breakthroughs that have advanced integrated circuit and semiconductor device fabrication technology, allowing transistor counts to grow by more than seven orders of magnitude in less than five decades.

 * Integrated circuit (IC): The raison d'être for Moore's law. The germanium hybrid IC was invented by Jack Kilby at Texas Instruments in 1958, followed by the invention of the silicon monolithic IC chip by Robert Noyce at Fairchild Semiconductor in 1959.
 * Complementary metal–oxide–semiconductor (CMOS): The CMOS process was invented by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.
 * Dynamic random-access memory (DRAM): DRAM was developed by Robert H. Dennard at IBM in 1967.
 * Chemically amplified photoresist: Invented by Hiroshi Ito, C. Grant Willson and J. M. J. Fréchet at IBM circa 1980, which was 5–10 times more sensitive to ultraviolet light. IBM introduced chemically amplified photoresist for DRAM production in the mid-1980s.
 * Deep UV excimer laser photolithography: Invented by Kanti Jain at IBM circa 1980.  Prior to this, excimer lasers had been mainly used as research devices since their development in the 1970s.  From a broader scientific perspective, the invention of excimer laser lithography has been highlighted as one of the major milestones in the 50-year history of the laser.
 * Interconnect innovations: Interconnect innovations of the late 1990s, including chemical-mechanical polishing or chemical mechanical planarization (CMP), trench isolation, and copper interconnects—although not directly a factor in creating smaller transistors—have enabled improved wafer yield, additional layers of metal wires, closer spacing of devices, and lower electrical resistance.

Computer industry technology road maps predicted in 2001 that Moore's law would continue for several generations of semiconductor chips.

Recent trends

One of the key technical challenges of engineering future nanoscale transistors is the design of gates. As device dimension shrinks, controlling the current flow in the thin channel becomes more difficult. Modern nanoscale transistors typically take the form of multi-gate MOSFETs, with the FinFET being the most common nanoscale transistor. The FinFET has gate dielectric on three sides of the channel. In comparison, the gate-all-around MOSFET (GAAFET) structure has even better gate control.

 * A gate-all-around MOSFET (GAAFET) was first demonstrated in 1988, by a Toshiba research team led by Fujio Masuoka, who demonstrated a vertical nanowire GAAFET which he called a "surrounding gate transistor" (SGT). Masuoka, best known as the inventor of flash memory, later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along with Tohoku University.
 * In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device at the time, based on FinFET technology.
 * In 2010, researchers at the Tyndall National Institute in Cork, Ireland announced a junctionless transistor. A control gate wrapped around a silicon nanowire can control the passage of electrons without the use of junctions or doping. They claim these may be produced at 10-nm scale using existing fabrication techniques.
 * In 2011, researchers at the University of Pittsburgh announced the development of a single-electron transistor, 1.5 nm in diameter, made out of oxide-based materials. Three "wires" converge on a central "island" that can house one or two electrons. Electrons tunnel from one wire to another through the island. Conditions on the third wire result in distinct conductive properties including the ability of the transistor to act as a solid state memory. Nanowire transistors could spur the creation of microscopic computers.
 * In 2012, a research team at the University of New South Wales announced the development of the first working transistor consisting of a single atom placed precisely in a silicon crystal (not just picked from a large sample of random transistors). Moore's law predicted this milestone to be reached for ICs in the lab by 2020.
 * In 2015, IBM demonstrated 7 nm node chips with silicon-germanium transistors produced using EUVL. The company believed this transistor density would be four times that of the then current 14 nm chips.
 * Samsung and TSMC plan to manufacture 3nm GAAFET nodes by 2021–2022. Note that node names, such as 3nm, have no relation to the physical size of device elements (transistors).
 * A Toshiba research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing three-dimensional integrated circuit (3D IC) packages in 2001. In April 2007, Toshiba introduced an eight-layer 3D IC, the 16GB THGAM embedded NAND flash memory chip which was manufactured with eight stacked 2GB NAND flash chips. In September 2007, Hynix introduced 24-layer 3D IC, a 16GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.
 * V-NAND, also known as 3D NAND, allows flash memory cells to be stacked vertically using charge trap flash technology originally presented by John Szedon in 1967, significantly increasing the number of transistors on a flash memory chip. 3D NAND was first announced by Toshiba in 2007. V-NAND was first commercially manufactured by Samsung Electronics in 2013.
 * In 2008, researchers at HP Labs announced a working memristor, a fourth basic passive circuit element whose existence only had been theorized previously. The memristor's unique properties permit the creation of smaller and better-performing electronic devices.
 * In 2014, bioengineers at Stanford University developed a circuit modeled on the human brain. Sixteen "Neurocore" chips simulate one million neurons and billions of synaptic connections, claimed to be 9,000 times faster as well as more energy efficient than a typical PC.
 * In 2015, Intel and Micron announced 3D XPoint, a non-volatile memory claimed to be significantly faster with similar density compared to NAND. Production scheduled to begin in 2016 was delayed until the second half of 2017.
 * In 2017, Samsung combined its V-NAND technology with eUFS 3D IC stacking to produce a 512GB flash memory chip, with eight stacked 64-layer V-NAND dies. In 2019, Samsung produced a 1TB flash chip with eight stacked 96-layer V-NAND dies, along with quad-level cell (QLC) technology (4-bit per transistor), equivalent to 2trillion transistors, the highest transistor count of any IC chip.
 * In 2020, Samsung Electronics planned to produce the 5 nm node, using FinFET and EUV technology.
 * In May 2021, IBM announced the creation of the first 2 nm computer chip, with parts supposedly being smaller than human DNA.

Microprocessor architects report that semiconductor advancement has slowed industry-wide since around 2010, below the pace predicted by Moore's law. Brian Krzanich, the former CEO of Intel, announced, "Our cadence today is closer to two and a half years than two." Intel stated in 2015 that improvements in MOSFET devices have slowed, starting at the 22 nm feature width around 2012, and continuing at 14 nm. Pat Gelsinger, Intel CEO, stated at the end of 2023 that "we're no longer in the golden era of Moore's Law, it's much, much harder now, so we're probably doubling effectively closer to every three years now, so we've definitely seen a slowing."

The physical limits to transistor scaling have been reached due to source-to-drain leakage, limited gate metals and limited options for channel material. Other approaches are being investigated, which do not rely on physical scaling. These include the spin state of electron spintronics, tunnel junctions, and advanced confinement of channel materials via nano-wire geometry. Spin-based logic and memory options are being developed actively in labs.

Alternative materials research
The vast majority of current transistors on ICs are composed principally of doped silicon and its alloys. As silicon is fabricated into single nanometer transistors, short-channel effects adversely change desired material properties of silicon as a functional transistor. Below are several non-silicon substitutes in the fabrication of small nanometer transistors.

One proposed material is indium gallium arsenide, or InGaAs. Compared to their silicon and germanium counterparts, InGaAs transistors are more promising for future high-speed, low-power logic applications. Because of intrinsic characteristics of III-V compound semiconductors, quantum well and tunnel effect transistors based on InGaAs have been proposed as alternatives to more traditional MOSFET designs.
 * In the early 2000s, the atomic layer deposition high-κ film and pitch double-patterning processes were invented by Gurtej Singh Sandhu at Micron Technology, extending Moore's law for planar CMOS technology to 30 nm class and smaller.
 * In 2009, Intel announced the development of 80-nm InGaAs quantum well transistors. Quantum well devices contain a material sandwiched between two layers of material with a wider band gap. Despite being double the size of leading pure silicon transistors at the time, the company reported that they performed equally as well while consuming less power.
 * In 2011, researchers at Intel demonstrated 3-D tri-gate InGaAs transistors with improved leakage characteristics compared to traditional planar designs. The company claims that their design achieved the best electrostatics of any III-V compound semiconductor transistor. At the 2015 International Solid-State Circuits Conference, Intel mentioned the use of III-V compounds based on such an architecture for their 7 nm node.
 * In 2011, researchers at the University of Texas at Austin developed an InGaAs tunneling field-effect transistors capable of higher operating currents than previous designs. The first III-V TFET designs were demonstrated in 2009 by a joint team from Cornell University and Pennsylvania State University.
 * In 2012, a team in MIT's Microsystems Technology Laboratories developed a 22 nm transistor based on InGaAs which, at the time, was the smallest non-silicon transistor ever built. The team used techniques used in silicon device fabrication and aimed for better electrical performance and a reduction to 10-nanometer scale.

Biological computing research shows that biological material has superior information density and energy efficiency compared to silicon-based computing.

Various forms of graphene are being studied for graphene electronics, e.g. graphene nanoribbon transistors have shown promise since its appearance in publications in 2008. (Bulk graphene has a band gap of zero and thus cannot be used in transistors because of its constant conductivity, an inability to turn off. The zigzag edges of the nanoribbons introduce localized energy states in the conduction and valence bands and thus a bandgap that enables switching when fabricated as a transistor. As an example, a typical GNR of width of 10 nm has a desirable bandgap energy of 0.4 eV. ) More research will need to be performed, however, on sub-50 nm graphene layers, as its resistivity value increases and thus electron mobility decreases.

Forecasts and roadmaps
In April 2005, Gordon Moore stated in an interview that the projection cannot be sustained indefinitely: "It can't continue forever. The nature of exponentials is that you push them out and eventually disaster happens." He also noted that transistors eventually would reach the limits of miniaturization at atomic levels: "In terms of size [of transistors] you can see that we're approaching the size of atoms which is a fundamental barrier, but it'll be two or three generations before we get that far—but that's as far out as we've ever been able to see. We have another 10 to 20 years before we reach a fundamental limit. By then they'll be able to make bigger chips and have transistor budgets in the billions."In 2016 the International Technology Roadmap for Semiconductors, after using Moore's Law to drive the industry since 1998, produced its final roadmap. It no longer centered its research and development plan on Moore's law. Instead, it outlined what might be called the More than Moore strategy in which the needs of applications drive chip development, rather than a focus on semiconductor scaling. Application drivers range from smartphones to AI to data centers.

IEEE began a road-mapping initiative in 2016, "Rebooting Computing", named the International Roadmap for Devices and Systems (IRDS).

Some forecasters, including Gordon Moore, predict that Moore's law will end by around 2025. Although Moore's Law will reach a physical limit, some forecasters are optimistic about the continuation of technological progress in a variety of other areas, including new chip architectures, quantum computing, and AI and machine learning. Nvidia CEO Jensen Huang declared Moore's law dead in 2022; several days later, Intel CEO Pat Gelsinger countered with the opposite claim.

Consequences
Digital electronics have contributed to world economic growth in the late twentieth and early twenty-first centuries. The primary driving force of economic growth is the growth of productivity, which Moore's law factors into. Moore (1995) expected that "the rate of technological progress is going to be controlled from financial realities". The reverse could and did occur around the late-1990s, however, with economists reporting that "Productivity growth is the key economic indicator of innovation." Moore's law describes a driving force of technological and social change, productivity, and economic growth.

An acceleration in the rate of semiconductor progress contributed to a surge in U.S. productivity growth,  which reached 3.4% per year in 1997–2004, outpacing the 1.6% per year during both 1972–1996 and 2005–2013. As economist Richard G. Anderson notes, "Numerous studies have traced the cause of the productivity acceleration to technological innovations in the production of semiconductors that sharply reduced the prices of such components and of the products that contain them (as well as expanding the capabilities of such products)."

The primary negative implication of Moore's law is that obsolescence pushes society up against the Limits to Growth. As technologies continue to rapidly "improve", they render predecessor technologies obsolete. In situations in which security and survivability of hardware or data are paramount, or in which resources are limited, rapid obsolescence often poses obstacles to smooth or continued operations.

Because of the intensive resource footprint and toxic materials used in the production of computers, obsolescence leads to serious harmful environmental impacts. Americans throw out 400,000 cell phones every day, but this high level of obsolescence appears to companies as an opportunity to generate regular sales of expensive new equipment, instead of retaining one device for a longer period of time, leading to industry using planned obsolescence as a profit centre.

An alternative source of improved performance is in microarchitecture techniques exploiting the growth of available transistor count. Out-of-order execution and on-chip caching and prefetching reduce the memory latency bottleneck at the expense of using more transistors and increasing the processor complexity. These increases are described empirically by Pollack's Rule, which states that performance increases due to microarchitecture techniques approximate the square root of the complexity (number of transistors or the area) of a processor.

For years, processor makers delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification. Now, to manage CPU power dissipation, processor makers favor multi-core chip designs, and software has to be written in a multi-threaded manner to take full advantage of the hardware. Many multi-threaded development paradigms introduce overhead, and will not see a linear increase in speed versus number of processors. This is particularly true while accessing shared or dependent resources, due to lock contention. This effect becomes more noticeable as the number of processors increases. There are cases where a roughly 45% increase in processor transistors has translated to roughly 10–20% increase in processing power.

On the other hand, manufacturers are adding specialized processing units to deal with features such as graphics, video, and cryptography. For one example, Intel's Parallel JavaScript extension not only adds support for multiple cores, but also for the other non-general processing features of their chips, as part of the migration in client side scripting toward HTML5.

Moore's law has affected the performance of other technologies significantly: Michael S. Malone wrote of a Moore's War following the apparent success of shock and awe in the early days of the Iraq War. Progress in the development of guided weapons depends on electronic technology. Improvements in circuit density and low-power operation associated with Moore's law also have contributed to the development of technologies including mobile telephones and 3-D printing.

Other formulations and similar observations
Several measures of digital technology are improving at exponential rates related to Moore's law, including the size, cost, density, and speed of components. Moore wrote only about the density of components, "a component being a transistor, resistor, diode or capacitor", at minimum cost.

Transistors per integrated circuit – The most popular formulation is of the doubling of the number of transistors on ICs every two years. At the end of the 1970s, Moore's law became known as the limit for the number of transistors on the most complex chips. The graph at the top of this article shows this trend holds true today. , the commercially available processor possessing the highest number of transistors is the 48 core Centriq with over 18 billion transistors.

Density at minimum cost per transistor
This is the formulation given in Moore's 1965 paper. It is not just about the density of transistors that can be achieved, but about the density of transistors at which the cost per transistor is the lowest.

As more transistors are put on a chip, the cost to make each transistor decreases, but the chance that the chip will not work due to a defect increases. In 1965, Moore examined the density of transistors at which cost is minimized, and observed that, as transistors were made smaller through advances in photolithography, this number would increase at "a rate of roughly a factor of two per year".

Dennard scaling – This posits that power usage would decrease in proportion to area (both voltage and current being proportional to length) of transistors. Combined with Moore's law, performance per watt would grow at roughly the same rate as transistor density, doubling every 1–2 years. According to Dennard scaling transistor dimensions would be scaled by 30% (0.7x) every technology generation, thus reducing their area by 50%. This would reduce the delay by 30% (0.7x) and therefore increase operating frequency by about 40% (1.4x). Finally, to keep electric field constant, voltage would be reduced by 30%, reducing energy by 65% and power (at 1.4x frequency) by 50%. Therefore, in every technology generation transistor density would double, circuit becomes 40% faster, while power consumption (with twice the number of transistors) stays the same. Dennard scaling ended in 2005–2010, due to leakage currents.

The exponential processor transistor growth predicted by Moore does not always translate into exponentially greater practical CPU performance. Since around 2005–2007, Dennard scaling has ended, so even though Moore's law continued after that, it has not yielded proportional dividends in improved performance. The primary reason cited for the breakdown is that at small sizes, current leakage poses greater challenges, and also causes the chip to heat up, which creates a threat of thermal runaway and therefore, further increases energy costs.

The breakdown of Dennard scaling prompted a greater focus on multicore processors, but the gains offered by switching to more cores are lower than the gains that would be achieved had Dennard scaling continued. In another departure from Dennard scaling, Intel microprocessors adopted a non-planar tri-gate FinFET at 22 nm in 2012 that is faster and consumes less power than a conventional planar transistor. The rate of performance improvement for single-core microprocessors has slowed significantly. Single-core performance was improving by 52% per year in 1986–2003 and 23% per year in 2003–2011, but slowed to just seven percent per year in 2011–2018.

Quality adjusted price of IT equipment – The price of information technology (IT), computers and peripheral equipment, adjusted for quality and inflation, declined 16% per year on average over the five decades from 1959 to 2009. The pace accelerated, however, to 23% per year in 1995–1999 triggered by faster IT innovation, and later, slowed to 2% per year in 2010–2013.

While quality-adjusted microprocessor price improvement continues, the rate of improvement likewise varies, and is not linear on a log scale. Microprocessor price improvement accelerated during the late 1990s, reaching 60% per year (halving every nine months) versus the typical 30% improvement rate (halving every two years) during the years earlier and later. Laptop microprocessors in particular improved 25–35% per year in 2004–2010, and slowed to 15–25% per year in 2010–2013.

The number of transistors per chip cannot explain quality-adjusted microprocessor prices fully. Moore's 1995 paper does not limit Moore's law to strict linearity or to transistor count, "The definition of 'Moore's Law' has come to refer to almost anything related to the semiconductor industry that on a semi-log plot approximates a straight line. I hesitate to review its origins and by doing so restrict its definition."

Hard disk drive areal density – A similar prediction (sometimes called Kryder's law) was made in 2005 for hard disk drive areal density. The prediction was later viewed as over-optimistic. Several decades of rapid progress in areal density slowed around 2010, from 30 to 100% per year to 10–15% per year, because of noise related to smaller grain size of the disk media, thermal stability, and writability using available magnetic fields.

Fiber-optic capacity – The number of bits per second that can be sent down an optical fiber increases exponentially, faster than Moore's law. Keck's law, in honor of Donald Keck.

Network capacity – According to Gerald Butters, the former head of Lucent's Optical Networking Group at Bell Labs, there is another version, called Butters' Law of Photonics, a formulation that deliberately parallels Moore's law. Butters' law says that the amount of data coming out of an optical fiber is doubling every nine months. Thus, the cost of transmitting a bit over an optical network decreases by half every nine months. The availability of wavelength-division multiplexing (sometimes called WDM) increased the capacity that could be placed on a single fiber by as much as a factor of 100. Optical networking and dense wavelength-division multiplexing (DWDM) is rapidly bringing down the cost of networking, and further progress seems assured. As a result, the wholesale price of data traffic collapsed in the dot-com bubble. Nielsen's Law says that the bandwidth available to users increases by 50% annually.

Pixels per dollar – Similarly, Barry Hendy of Kodak Australia has plotted pixels per dollar as a basic measure of value for a digital camera, demonstrating the historical linearity (on a log scale) of this market and the opportunity to predict the future trend of digital camera price, LCD and LED screens, and resolution.

The great Moore's law compensator (TGMLC), also known as Wirth's law – generally is referred to as software bloat and is the principle that successive generations of computer software increase in size and complexity, thereby offsetting the performance gains predicted by Moore's law. In a 2008 article in InfoWorld, Randall C. Kennedy, formerly of Intel, introduces this term using successive versions of Microsoft Office between the year 2000 and 2007 as his premise. Despite the gains in computational performance during this time period according to Moore's law, Office 2007 performed the same task at half the speed on a prototypical year 2007 computer as compared to Office 2000 on a year 2000 computer.

Library expansion – was calculated in 1945 by Fremont Rider to double in capacity every 16 years, if sufficient space were made available. He advocated replacing bulky, decaying printed works with miniaturized microform analog photographs, which could be duplicated on-demand for library patrons or other institutions. He did not foresee the digital technology that would follow decades later to replace analog microform with digital imaging, storage, and transmission media. Automated, potentially lossless digital technologies allowed vast increases in the rapidity of information growth in an era that now sometimes is called the Information Age.

Carlson curve – is a term coined by The Economist to describe the biotechnological equivalent of Moore's law, and is named after author Rob Carlson. Carlson accurately predicted that the doubling time of DNA sequencing technologies (measured by cost and performance) would be at least as fast as Moore's law. Carlson Curves illustrate the rapid (in some cases hyperexponential) decreases in cost, and increases in performance, of a variety of technologies, including DNA sequencing, DNA synthesis, and a range of physical and computational tools used in protein expression and in determining protein structures.

Eroom's law – is a pharmaceutical drug development observation which was deliberately written as Moore's Law spelled backwards in order to contrast it with the exponential advancements of other forms of technology (such as transistors) over time. It states that the cost of developing a new drug roughly doubles every nine years.

Experience curve effects says that each doubling of the cumulative production of virtually any product or service is accompanied by an approximate constant percentage reduction in the unit cost. The acknowledged first documented qualitative description of this dates from 1885. A power curve was used to describe this phenomenon in a 1936 discussion of the cost of airplanes.

Edholm's law – Phil Edholm observed that the bandwidth of telecommunication networks (including the Internet) is doubling every 18 months. The bandwidths of online communication networks has risen from bits per second to terabits per second. The rapid rise in online bandwidth is largely due to the same MOSFET scaling that enabled Moore's law, as telecommunications networks are built from MOSFETs.

Haitz's law predicts that the brightness of LEDs increases as their manufacturing cost goes down.

Swanson's law is the observation that the price of solar photovoltaic modules tends to drop 20 percent for every doubling of cumulative shipped volume. At present rates, costs go down 75% about every 10 years.

title: Moore's law


text:
Right triangle

A right triangle or right-angled triangle, sometimes called an orthogonal triangle or rectangular triangle, is a triangle in which two sides are perpendicular forming a right angle ($C$ turn or 90 degrees).

The side opposite to the right angle is called the hypotenuse (side $$c$$ in the figure). The sides adjacent to the right angle are called legs (or catheti, singular: cathetus). Side $$a$$ may be identified as the side adjacent to angle $$B$$ and opposite (or opposed to) angle $$A,$$ while side $$b$$ is the side adjacent to angle $$A$$ and opposite angle $$B.$$

Every right triangle is half of a rectangle which has been divided along its diagonal. When the rectangle is a square, its right-triangular half is isosceles, with two congruent sides and two congruent angles. When the rectangle is not a square, its right-triangular half is scalene.

Every triangle whose base is the diameter of a circle and whose apex lies on the circle is a right triangle, with the right angle at the apex and the hypotenuse as the base; conversely, the circumcircle of any right triangle has the hypotenuse as its diameter. This is Thales' theorem.

The legs and hypotenuse of a right triangle satisfy the Pythagorean theorem: the sum of the areas of the squares on two legs is the area of the square on the hypotenuse, $$a^2 + b^2 = c^2.$$ If the lengths of all three sides of a right triangle are integers, the triangle is called a Pythagorean triangle and its side lengths are collectively known as a Pythagorean triple.

The relations between the sides and angles of a right triangle provides one way of defining and understanding trigonometry, the study of the metrical relationships between lengths and angles.

Sides

The three sides of a right triangle are related by the Pythagorean theorem, which in modern algebraic notation can be written

 * $$a^2 + b^2 = c^2,$$

where $$c$$ is the length of the hypotenuse (side opposite the right angle), and $$a$$ and $$b$$ are the lengths of the legs (remaining two sides). Pythagorean triples are integer values of $$a, b, c$$ satisfying this equation. This theorem was proven in antiquity, and is proposition I.47 in Euclid's Elements: "In right-angled triangles the square on the side subtending the right angle is equal to the squares on the sides containing the right angle."

Area
As with any triangle, the area is equal to one half the base multiplied by the corresponding height. In a right triangle, if one leg is taken as the base then the other is height, so the area of a right triangle is one half the product of the two legs. As a formula the area $$T$$ is
 * $$T=\tfrac{1}{2}ab$$

where $$a$$ and $$b$$ are the legs of the triangle.

If the incircle is tangent to the hypotenuse $$AB$$ at point $$P,$$ then letting the semi-perimeter be $$s = \tfrac12(a+b+c),$$ we have $$|PA| = s-a$$ and $$|PB| = s-b,$$ and the area is given by
 * $$T= |PA| \cdot |PB| = (s-a)(s-b).$$

This formula only applies to right triangles.

Altitudes
If an altitude is drawn from the vertex with the right angle to the hypotenuse then the triangle is divided into two smaller triangles which are both similar to the original and therefore similar to each other. From this: In equations,
 * The altitude to the hypotenuse is the geometric mean (mean proportional) of the two segments of the hypotenuse.
 * Each leg of the triangle is the mean proportional of the hypotenuse and the segment of the hypotenuse that is adjacent to the leg.
 * $$f^2=de,$$ (this is sometimes known as the right triangle altitude theorem)
 * $$b^2=ce,$$
 * $$a^2=cd$$

where $$a,b,c,d,e,f$$ are as shown in the diagram. Thus
 * $$f=\frac{ab}{c}.$$

Moreover, the altitude to the hypotenuse is related to the legs of the right triangle by
 * $$\frac{1}{a^2} + \frac{1}{b^2} = \frac{1}{f^2}.$$

For solutions of this equation in integer values of $$a,b,c,f,$$ see here.

The altitude from either leg coincides with the other leg. Since these intersect at the right-angled vertex, the right triangle's orthocenter—the intersection of its three altitudes—coincides with the right-angled vertex.

Inradius and circumradius
The radius of the incircle of a right triangle with legs $$a$$ and $$b$$ and hypotenuse $$c$$ is
 * $$r = \frac{a+b-c}{2} = \frac{ab}{a+b+c}.$$

The radius of the circumcircle is half the length of the hypotenuse,
 * $$R = \frac{c}{2}.$$

Thus the sum of the circumradius and the inradius is half the sum of the legs:

 * $$R+r = \frac{a+b}{2}.$$

One of the legs can be expressed in terms of the inradius and the other leg as
 * $$a=\frac{2r(b-r)}{b-2r}.$$

Characterizations
A triangle $$\triangle ABC$$ with sides $$a \le b < c$$, semiperimeter $s = \tfrac12(a+b+c)$, area $$T,$$ altitude $$h_c$$ opposite the longest side, circumradius $$R,$$ inradius $$r,$$ exradii $$r_a, r_b, r_c$$ tangent to $$a,b,c$$ respectively, and medians $$m_a, m_b, m_c$$ is a right triangle if and only if any one of the statements in the following six categories is true. Each of them is thus also a property of any right triangle.

Sides and semiperimeter

 * $$a^2+b^2=c^2\quad (\text{Pythagorean theorem})$$
 * $$(s-a)(s-b) = s(s-c)$$
 * $$s=2R+r.$$
 * $$a^2+b^2+c^2=8R^2.$$

Angles

 * $$A$$ and $$B$$ are complementary.
 * $$\cos{A}\cos{B}\cos{C}=0.$$
 * $$\sin^2{A}+\sin^2{B}+\sin^2{C}=2.$$
 * $$\cos^2{A}+\cos^2{B}+\cos^2{C}=1.$$
 * $$\sin{2A}=\sin{2B}=2\sin{A}\sin{B}.$$

Area

 * $$T=\frac{ab}{2}$$
 * $$T=r_ar_b=rr_c$$
 * $$T=r(2R+r)$$
 * $$T=\frac{(2s-c)^2-c^2}{4}=s(s-c)$$
 * $$T=|PA| \cdot |PB|,$$ where $$P$$ is the tangency point of the incircle at the longest side $$AB.$$

Inradius and exradii

 * $$r=s-c=(a+b-c)/2$$
 * $$r_a=s-b=(a-b+c)/2$$
 * $$r_b=s-a=(-a+b+c)/2$$
 * $$r_c=s=(a+b+c)/2$$
 * $$r_a+r_b+r_c+r=a+b+c$$
 * $$r_a^2+r_b^2+r_c^2+r^2=a^2+b^2+c^2$$
 * $$r=\frac{r_ar_b}{r_c}.$$

Altitude and medians

 * $$h_c=\frac{ab}{c}$$
 * $$m_a^2+m_b^2+m_c^2=6R^2.$$
 * The length of one median is equal to the circumradius.
 * The shortest altitude (the one from the vertex with the biggest angle) is the geometric mean of the line segments it divides the opposite (longest) side into. This is the right triangle altitude theorem.

Circumcircle and incircle

 * The triangle can be inscribed in a semicircle, with one side coinciding with the entirety of the diameter (Thales' theorem).
 * The circumcenter is the midpoint of the longest side.
 * The longest side is a diameter of the circumcircle $$(c=2R).$$
 * The circumcircle is tangent to the nine-point circle.
 * The orthocenter lies on the circumcircle.
 * The distance between the incenter and the orthocenter is equal to $$\sqrt{2}r$$.

Trigonometric ratios
The trigonometric functions for acute angles can be defined as ratios of the sides of a right triangle. For a given angle, a right triangle may be constructed with this angle, and the sides labeled opposite, adjacent and hypotenuse with reference to this angle according to the definitions above. These ratios of the sides do not depend on the particular right triangle chosen, but only on the given angle, since all triangles constructed this way are similar. If, for a given angle α, the opposite side, adjacent side and hypotenuse are labeled $$O,$$ $$A,$$ and $$H,$$ respectively, then the trigonometric functions are
 * $$\sin\alpha =\frac {O}{H},\,\cos\alpha =\frac {A}{H},\,\tan\alpha =\frac {O}{A},\,\sec\alpha =\frac {H}{A},\,\cot\alpha =\frac {A}{O},\,\csc\alpha =\frac {H}{O}.$$

For the expression of hyperbolic functions as ratio of the sides of a right triangle, see the hyperbolic triangle of a hyperbolic sector.

Special right triangles
The values of the trigonometric functions can be evaluated exactly for certain angles using right triangles with special angles. These include the 30-60-90 triangle which can be used to evaluate the trigonometric functions for any multiple of $$\tfrac16\pi,$$ and the isosceles right triangle or 45-45-90 triangle which can be used to evaluate the trigonometric functions for any multiple of $$\tfrac14\pi.$$

Kepler triangle
Let $$H,$$ $$G,$$ and $$A$$ be the harmonic mean, the geometric mean, and the arithmetic mean of two positive numbers $$a$$ and $$b$$ with $$a > b.$$ If a right triangle has legs $$H$$ and $$G$$ and hypotenuse $$A,$$ then

\frac{A}{H} = \frac{A^{2}}{G^{2}} = \frac{G^{2}}{H^{2}} = \phi, \qquad \frac{a}{b} = \phi^{3}, $$

where $$\phi = \tfrac12\bigl(1 + \sqrt{5}\bigr)$$ is the golden ratio. Since the sides of this right triangle are in geometric progression, this is the Kepler triangle.

Thales' theorem
Thales' theorem states that if $$BC$$ is the diameter of a circle and $$A$$ is any other point on the circle, then $$\triangle ABC$$ is a right triangle with a right angle at $$A.$$ The converse states that the hypotenuse of a right triangle is the diameter of its circumcircle. As a corollary, the circumcircle has its center at the midpoint of the diameter, so the median through the right-angled vertex is a radius, and the circumradius is half the length of the hypotenuse.

Medians
The following formulas hold for the medians of a right triangle:
 * $$m_a^2 + m_b^2 = 5m_c^2 = \frac{5}{4}c^2.$$

The median on the hypotenuse of a right triangle divides the triangle into two isosceles triangles, because the median equals one-half the hypotenuse.

The medians $$m_a$$ and $$m_b$$ from the legs satisfy

 * $$4c^4+9a^2b^2=16m_a^2m_b^2.$$

Euler line
In a right triangle, the Euler line contains the median on the hypotenuse—that is, it goes through both the right-angled vertex and the midpoint of the side opposite that vertex. This is because the right triangle's orthocenter, the intersection of its altitudes, falls on the right-angled vertex while its circumcenter, the intersection of its perpendicular bisectors of sides, falls on the midpoint of the hypotenuse.

Inequalities
In any right triangle the diameter of the incircle is less than half the hypotenuse, and more strongly it is less than or equal to the hypotenuse times $$(\sqrt{2}-1).$$

In a right triangle with legs $$a,b$$ and hypotenuse $$c,$$

 * $$c \geq \frac{\sqrt{2}}{2}(a+b)$$

with equality only in the isosceles case.

If the altitude from the hypotenuse is denoted $$h_c,$$ then

 * $$h_c \leq \frac{\sqrt {2}}{4}(a+b)$$

with equality only in the isosceles case.

Other properties
If segments of lengths $$p$$ and $$q$$ emanating from vertex $$C$$ trisect the hypotenuse into segments of length $$\tfrac13 c,$$ then
 * $$p^2 + q^2 = 5\left(\frac{c}{3}\right)^2.$$

The right triangle is the only triangle having two, rather than one or three, distinct inscribed squares.

Given any two positive numbers $$h$$ and $$k$$ with $$h > k.$$ Let $$h$$ and $$k$$ be the sides of the two inscribed squares in a right triangle with hypotenuse $$c.$$ Then
 * $$\frac{1}{c^2} + \frac{1}{h^2} = \frac{1}{k^2}.$$

These sides and the incircle radius $$r$$ are related by a similar formula:

 * $$\frac{1}{r}=-{\frac{1}{c}}+\frac{1}{h}+\frac{1}{k}.$$

The perimeter of a right triangle equals the sum of the radii of the incircle and the three excircles:

 * $$a+b+c=r+r_a+r_b+r_c.$$

title: Right triangle