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SPICE

SPICE ("Simulation Program with Integrated Circuit Emphasis") is a general-purpose, open-source analog electronic circuit simulator. It is a program used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.

Introduction
Unlike board-level designs composed of discrete parts, it is not practical to breadboard integrated circuits before manufacture. Further, the high costs of photolithographic masks and other manufacturing prerequisites make it essential to design the circuit to be as close to perfect as possible before the integrated circuit is first built.

Simulating the circuit with SPICE is the industry-standard way to verify circuit operation at the transistor level before committing to manufacturing an integrated circuit. The SPICE simulators help to predict the behavior of the IC under different operating conditions, such as different voltage and current levels, temperature variations, and noise.

Board-level circuit designs can often be breadboarded for testing. Even with a breadboard, some circuit properties may not be accurate compared to the final printed wiring board, such as parasitic resistances and capacitances, whose effects can often be estimated more accurately using simulation. Also, designers may want more information about the circuit than is available from a single mock-up. For instance, circuit performance is affected by component manufacturing tolerances. In these cases it is common to use SPICE to perform Monte Carlo simulations of the effect of component variations on performance, a task which is impractical using calculations by hand for a circuit of any appreciable complexity.

Circuit simulation programs, of which SPICE and derivatives are the most prominent, take a text netlist describing the circuit elements (transistors, resistors, capacitors, etc.) and their connections, and translate this description into equations to be solved. The general equations produced are nonlinear differential algebraic equations which are solved using implicit integration methods, Newton's method and sparse matrix techniques.

Origins
SPICE was developed at the Electronics Research Laboratory of the University of California, Berkeley by Laurence Nagel with direction from his research advisor, Prof. Donald Pederson. SPICE1 is largely a derivative of the CANCER program, which Nagel had worked on under Prof. Ronald Rohrer. CANCER is an acronym for "Computer Analysis of Nonlinear Circuits, Excluding Radiation", a hint to Berkeley's liberalism in the 1960s: at these times many circuit simulators were developed under contracts with the United States Department of Defense that required the capability to evaluate the radiation hardness of a circuit. When Nagel's original advisor, Prof. Rohrer, left Berkeley, Prof. Pederson became his advisor. Pederson insisted that CANCER, a proprietary program, be rewritten enough that restrictions could be removed and the program could be put in the public domain.

SPICE1 was first presented at a conference in 1973. SPICE1 is coded in FORTRAN and to construct the circuit equations uses nodal analysis, which has limitations in representing inductors, floating voltage sources and the various forms of controlled sources. SPICE1 has relatively few circuit elements available and uses a fixed-timestep transient analysis. The real popularity of SPICE started with SPICE2 in 1975. SPICE2, also coded in FORTRAN, is a much-improved program with more circuit elements, variable timestep transient analysis using either the trapezoidal (second order Adams-Moulton method) or the Gear integration method (also known as BDF), equation formulation via modified nodal analysis (avoiding the limitations of nodal analysis), and an innovative FORTRAN-based memory allocation system. Ellis Cohen led development from version 2B to the industry standard SPICE 2G6, the last FORTRAN version, released in 1983. SPICE3 was developed by Thomas Quarles (with A. Richard Newton as advisor) in 1989. It is written in C, uses the same netlist syntax, and added X Window System plotting.

As an early public domain software program with source code available, SPICE was widely distributed and used. Its ubiquity became such that "to SPICE a circuit" remains synonymous with circuit simulation. SPICE source code was from the beginning distributed by UC Berkeley for a nominal charge (to cover the cost of magnetic tape). The license originally included distribution restrictions for countries not considered friendly to the US, but the source code is currently covered by the BSD license.

The birth of SPICE was named an IEEE Milestone in 2011; the entry mentions that SPICE "evolved to become the worldwide standard integrated circuit simulator". Nagel was awarded the 2019 IEEE Donald O. Pederson Award in Solid-State Circuits for the development of SPICE.

Open-source successors
No newer versions of Berkeley SPICE have been released after version 3f5 in 1993. Since then, the open-source or academic continuations of SPICE include: XSPICE, developed at Georgia Tech, which added mixed analog/digital "code models" for behavioral simulation; CIDER (previously CODECS), developed by UC Berkeley and Oregon State University, which added semiconductor device simulation; Ngspice, based on SPICE 3f5; WRspice, a C++ re-write of the original spice3f5 code. Other open-source simulators not developed by academics are QUCS, QUCS-S, Xyce, and Qucsator.

Commercial versions and spinoffs
Berkeley SPICE inspired and served as a basis for many other circuit simulation programs, in academia, in industry, and in commercial products. The first commercial version of SPICE is ISPICE, an interactive version on a timeshare service, National CSS. The most prominent commercial versions of SPICE include HSPICE (originally commercialized by Ashawna and Kim Hailey of Meta Software, but now owned by Synopsys) and PSPICE (now owned by Cadence Design Systems). The integrated circuit industry adopted SPICE quickly, and until commercial versions became well developed many IC design houses had proprietary versions of SPICE.

Today a few IC manufacturers, typically the larger companies, have groups continuing to develop SPICE-based circuit simulation programs. Among these are ADICE and LTspice at Analog Devices, QSPICE at Qorvo, MCSPICE, followed by Mica at Freescale Semiconductor, now NXP Semiconductors, and TINA-TI at Texas Instruments. Both LTspice and TINA-TI come bundled with models from their respective company. Other companies maintain internal circuit simulators which are not directly based upon SPICE, among them PowerSpice at IBM, TITAN at Infineon Technologies, Lynx at Intel Corporation, and Pstar at NXP Semiconductors also.

Program features and structure
SPICE became popular because it contained the analyses and models needed to design integrated circuits of the time, and was robust enough and fast enough to be practical to use. Precursors to SPICE often had a single purpose: The BIAS program, for example, did simulation of bipolar transistor circuit operating points; the SLIC program did only small-signal analyses. SPICE combined operating point solutions, transient analysis, and various small-signal analyses with the circuit elements and device models needed to successfully simulate many circuits.

Analyses
SPICE2 includes these analyses:
 * AC analysis (linear small-signal frequency domain analysis)
 * DC analysis (nonlinear quiescent point calculation)
 * DC transfer curve analysis (a sequence of nonlinear operating points calculated while sweeping an input voltage or current, or a circuit parameter)
 * Noise analysis (a small signal analysis done using an adjoint matrix technique which sums uncorrelated noise currents at a chosen output point)
 * Transfer function analysis (a small-signal input/output gain and impedance calculation)
 * Transient analysis (time-domain large-signal solution of nonlinear differential algebraic equations)

Since SPICE is generally used to model circuits with nonlinear elements, the small signal analyses are necessarily preceded by a quiescent point calculation at which the circuit is linearized. SPICE2 also contains code for other small-signal analyses: sensitivity analysis, pole-zero analysis, and small-signal distortion analysis. Analysis at various temperatures is done by automatically updating semiconductor model parameters for temperature, allowing the circuit to be simulated at temperature extremes.

Other circuit simulators have since added many analyses beyond those in SPICE2 to address changing industry requirements. Parametric sweeps were added to analyze circuit performance with changing manufacturing tolerances or operating conditions. Loop gain and stability calculations were added for analog circuits. Harmonic balance or time-domain steady state analyses were added for RF and switched-capacitor circuit design. However, a public-domain circuit simulator containing the modern analyses and features needed to become a successor in popularity to SPICE has not yet emerged.

It is very important to use appropriate analyses with carefully chosen parameters. For example, application of linear analysis to nonlinear circuits should be justified separately. Also, application of transient analysis with default simulation parameters can lead to qualitatively wrong conclusions on circuit dynamics.

Device models
SPICE2 includes many semiconductor device compact models: three levels of MOSFET model, a combined Ebers–Moll and Gummel–Poon bipolar model, a JFET model, and a model for a junction diode. In addition, it had many other elements: resistors, capacitors, inductors (including coupling), independent voltage and current sources, ideal transmission lines, active components and voltage and current controlled sources.

SPICE3 added more sophisticated MOSFET models, which were required due to advances in semiconductor technology. In particular, the BSIM family of models were added, which were also developed at UC Berkeley.

Commercial and industrial SPICE simulators have added many other device models as technology advanced and earlier models became inadequate. To attempt standardization of these models so that a set of model parameters may be used in different simulators, an industry working group was formed, the Compact Model Council, to choose, maintain and promote the use of standard models. The standard models today include BSIM3, BSIM4, BSIMSOI, PSP, HICUM, and MEXTRAM.

Spice can use device models from foundry PDKs.

Input and output: Netlists, schematic capture and plotting
SPICE2 takes a text netlist as input and produces line-printer listings as output, which fits with the computing environment in 1975. These listings are either columns of numbers corresponding to calculated outputs (typically voltages or currents), or line-printer character "plots". SPICE3 retains the netlist for circuit description, but allows analyses to be controlled from a command-line interface similar to the C shell. SPICE3 also added basic X plotting, as UNIX and engineering workstations became common.

Vendors and various free software projects have added schematic capture frontends to SPICE, allowing a schematic diagram of the circuit to be drawn and the netlist to be automatically generated and transferred to various SPICE backends. Also, graphical user interfaces were added for selecting the simulations to be done and manipulating the voltage and current output vectors. In addition, very capable graphing utilities have been added to see waveforms and graphs of parametric dependencies. Several free versions of these extended programs are available.

SPICE usage beyond electronic simulation
As SPICE generally solves non-linear differential algebraic equations, it may be applied to simulating beyond the electrical realm.

Most prominent are thermal simulations, as thermal systems may be described by lumped circuit elements mapping onto the electronic SPICE elements (heat capacity → capacitance, thermal conductance/resistance → conductance/resistance, temperature → voltage, heat flow or heat generated → current ). As thermal and electronic systems are closely linked by power dissipation and cooling systems, electro-thermal simulation today is supported by semiconductor device manufacturers offering (transistor) models with both electrical and thermal nodes. So one may obtain electrical power dissipation, resulting in self-heating causing parameter variations, and cooling system efficiency in a single simulation run.

SPICE may very well simulate the electronics part of a motor drive. However it will equally well describe the electro-mechanical model of the motor. Again this is achieved by mapping mechanical onto the electrical elements (torque → voltage, angular velocity → current, coefficient of viscous friction → resistance, moment of inertia → inductance). So again the final model consists of only SPICE compatible lumped circuit elements, but one gains mechanical together with electrical data during simulation.

Electromagnetic modeling is accessible to a SPICE simulator via the PEEC (partial element equivalent circuit) method. Maxwell's equations have been mapped, RLC, Skin effect, dielectric or magnetic materials and incident or radiated fields have been modelled.

However, as of 2019, SPICE cannot be used to "simulate photonics and electronics together in a photonic circuit simulator", and thus it is not yet considered as a test simulator for photonic integrated circuits.

Micro-fluidic circuits have been modelled with SPICE by creating a pneumatic FET.

SPICE has been applied to model the interface between biological and electronic systems, e.g. as a design tools for synthetic biology and for the virtual prototyping of biosensors and lab-on-chip.

SPICE has been applied in operations research to evaluate perturbed supply chains.

Histories, original papers

 * The original SPICE1 paper
 * L. W. Nagel's dissertation (SPICE2)
 * Thomas Quarles' dissertation (SPICE3)
 * A brief history of SPICE
 * SPICE2 and SPICE3 at UC Berkeley
 * Cider at UC Berkeley
 * SPICE: how to choose an analysis

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Stellation

In geometry, stellation is the process of extending a polygon in two dimensions, a polyhedron in three dimensions, or, in general, a polytope in n dimensions to form a new figure. Starting with an original figure, the process extends specific elements such as its edges or face planes, usually in a symmetrical way, until they meet each other again to form the closed boundary of a new figure. The new figure is a stellation of the original. The word stellation comes from the Latin stellātus, "starred", which in turn comes from the Latin stella, "star". Stellation is the reciprocal or dual process to faceting.

Kepler's definition
In 1619 Kepler defined stellation for polygons and polyhedra as the process of extending edges or faces until they meet to form a new polygon or polyhedron.

He stellated the regular dodecahedron to obtain two regular star polyhedra, the small stellated dodecahedron and the great stellated dodecahedron. He also stellated the regular octahedron to obtain the stella octangula, a regular compound of two tetrahedra.

Stellating polygons
Stellating a regular polygon symmetrically creates a regular star polygon or polygonal compound. These polygons are characterised by the number of times m that the polygonal boundary winds around the centre of the figure. Like all regular polygons, their vertices lie on a circle. m also corresponds to the number of vertices around the circle to get from one end of a given edge to the other, starting at 1.

A regular star polygon is represented by its Schläfli symbol {n/m}, where n is the number of vertices, m is the step used in sequencing the edges around it, and m and n are coprime (have no common factor). The case m = 1 gives the convex polygon {n}. m also must be less than half of n; otherwise the lines will either be parallel or diverge, preventing the figure from ever closing.

If n and m do have a common factor, then the figure is a regular compound. For example {6/2} is the regular compound of two triangles {3} or hexagram, while {10/4} is a compound of two pentagrams {5/2}.

Some authors use the Schläfli symbol for such regular compounds. Others regard the symbol as indicating a single path which is wound m times around $n⁄m$ vertex points, such that one edge is superimposed upon another and each vertex point is visited m times. In this case a modified symbol may be used for the compound, for example 2{3} for the hexagram and 2{5/2} for the regular compound of two pentagrams.

A regular n-gon has $n – 4⁄2$ stellations if n is even (assuming compounds of multiple degenerate digons are not considered), and $n – 3⁄2$ stellations if n is odd.

Like the heptagon, the octagon also has two octagrammic stellations, one, {8/3} being a star polygon, and the other, {8/2}, being the compound of two squares.

Stellating polyhedra
A polyhedron is stellated by extending the edges or face planes of a polyhedron until they meet again to form a new polyhedron or compound. The interior of the new polyhedron is divided by the faces into a number of cells. The face planes of a polyhedron may divide space into many such cells, and as the stellation process continues then more of these cells will be enclosed. For a symmetrical polyhedron, these cells will fall into groups, or sets, of congruent cells – we say that the cells in such a congruent set are of the same type. A common method of finding stellations involves selecting one or more cell types.

This can lead to a huge number of possible forms, so further criteria are often imposed to reduce the set to those stellations that are significant and unique in some way.

A set of cells forming a closed layer around its core is called a shell. For a symmetrical polyhedron, a shell may be made up of one or more cell types.

Based on such ideas, several restrictive categories of interest have been identified.
 * Main-line stellations. Adding successive shells to the core polyhedron leads to the set of main-line stellations.
 * Fully supported stellations. The underside faces of a cell can appear externally as an "overhang." In a fully supported stellation there are no such overhangs, and all visible parts of a face are seen from the same side.
 * Monoacral stellations. Literally "single-peaked." Where there is only one kind of peak, or vertex, in a stellation (i.e. all vertices are congruent within a single symmetry orbit), the stellation is monoacral. All such stellations are fully supported.
 * Primary stellations. Where a polyhedron has planes of mirror symmetry, edges falling in these planes are said to lie in primary lines. If all edges lie in primary lines, the stellation is primary. All primary stellations are fully supported.
 * Miller stellations. In "The Fifty-Nine Icosahedra" Coxeter, Du Val, Flather and Petrie record five rules suggested by Miller. Although these rules refer specifically to the icosahedron's geometry, they have been adapted to work for arbitrary polyhedra.  They ensure, among other things, that the rotational symmetry of the original polyhedron is preserved, and that each stellation is different in outward appearance. The four kinds of stellation just defined are all subsets of the Miller stellations.

We can also identify some other categories:
 * A partial stellation is one where not all elements of a given dimensionality are extended.
 * A sub-symmetric stellation is one where not all elements are extended symmetrically.

The Archimedean solids and their duals can also be stellated. Here we usually add the rule that all of the original face planes must be present in the stellation, i.e. we do not consider partial stellations. For example the cube is not usually considered a stellation of the cuboctahedron.

Generalising Miller's rules there are:
 * 4 stellations of the rhombic dodecahedron
 * 187 stellations of the triakis tetrahedron
 * 358,833,097 stellations of the rhombic triacontahedron
 * 17 stellations of the cuboctahedron (4 are shown in Wenninger's Polyhedron Models)
 * An unknown number of stellations of the icosidodecahedron; there are 7071671 non-chiral stellations, but the number of chiral stellations is unknown. (20 are shown in Wenninger's Polyhedron Models)

Seventeen of the nonconvex uniform polyhedra are stellations of Archimedean solids.

Miller's rules
In the book The Fifty-Nine Icosahedra, J.C.P. Miller proposed a set of rules for defining which stellation forms should be considered "properly significant and distinct".

These rules have been adapted for use with stellations of many other polyhedra. Under Miller's rules we find:
 * There are no stellations of the tetrahedron, because all faces are adjacent
 * There are no stellations of the cube, because non-adjacent faces are parallel and thus cannot be extended to meet in new edges
 * There is 1 stellation of the octahedron, the stella octangula
 * There are 3 stellations of the dodecahedron: the small stellated dodecahedron, the great dodecahedron and the great stellated dodecahedron, all of which are Kepler–Poinsot polyhedra.
 * There are 58 stellations of the icosahedron, including the great icosahedron (one of the Kepler–Poinsot polyhedra), and the second and final stellations of the icosahedron. The 59th model in The fifty nine icosahedra is the original icosahedron itself.

Many "Miller stellations" cannot be obtained directly by using Kepler's method. For example many have hollow centres where the original faces and edges of the core polyhedron are entirely missing: there is nothing left to be stellated. On the other hand, Kepler's method also yields stellations which are forbidden by Miller's rules since their cells are edge- or vertex-connected, even though their faces are single polygons. This discrepancy received no real attention until Inchbald (2002).

Other rules for stellation
Miller's rules by no means represent the "correct" way to enumerate stellations. They are based on combining parts within the stellation diagram in certain ways, and don't take into account the topology of the resulting faces. As such there are some quite reasonable stellations of the icosahedron that are not part of their list – one was identified by James Bridge in 1974, while some "Miller stellations" are questionable as to whether they should be regarded as stellations at all – one of the icosahedral set comprises several quite disconnected cells floating symmetrically in space.

As yet an alternative set of rules that takes this into account has not been fully developed. Most progress has been made based on the notion that stellation is the reciprocal or dual process to facetting, whereby parts are removed from a polyhedron without creating any new vertices. For every stellation of some polyhedron, there is a dual facetting of the dual polyhedron, and vice versa. By studying facettings of the dual, we gain insights into the stellations of the original. Bridge found his new stellation of the icosahedron by studying the facettings of its dual, the dodecahedron.

Some polyhedronists take the view that stellation is a two-way process, such that any two polyhedra sharing the same face planes are stellations of each other. This is understandable if one is devising a general algorithm suitable for use in a computer program, but is otherwise not particularly helpful.

Many examples of stellations can be found in the list of Wenninger's stellation models.

Stellating polytopes
The stellation process can be applied to higher dimensional polytopes as well. A stellation diagram of an n-polytope exists in an (n − 1)-dimensional hyperplane of a given facet.

For example, in 4-space, the great grand stellated 120-cell is the final stellation of the regular 4-polytope 120-cell.

Naming stellations
The first systematic naming of stellated polyhedra was Cayley's naming of the regular star polyhedra (nowadays known as the Kepler–Poinsot polyhedra). This system was widely, but not always systematically, adopted for other polyhedra and higher polytopes.

John Conway devised a terminology for stellated polygons, polyhedra and polychora (Coxeter 1974). In this system the process of extending edges to create a new figure is called stellation, that of extending faces is called greatening and that of extending cells is called aggrandizement (this last does not apply to polyhedra). This allows a systematic use of words such as 'stellated', 'great', and 'grand' in devising names for the resulting figures. For example Conway proposed some minor variations to the names of the Kepler–Poinsot polyhedra.

Stellation to infinity
Wenninger noticed that some polyhedra, such as the cube, do not have any finite stellations. However stellation cells can be constructed as prisms which extend to infinity. The figure comprising these prisms may be called a stellation to infinity. By most definitions of a polyhedron, however, these stellations are not strictly polyhedra.

Wenninger's figures occurred as duals of the uniform hemipolyhedra, where the faces that pass through the center are sent to vertices "at infinity".

From mathematics to art

Alongside from his contributions to mathematics, Magnus Wenninger is described in the context of the relationship of mathematics and art as making "especially beautiful" models of complex stellated polyhedra.

The Italian Renaissance artist Paolo Uccello created a floor mosaic showing a small stellated dodecahedron in the Basilica of St Mark, Venice, c. 1430. Uccello's depiction was used as the symbol for the Venice Biennale in 1986 on the topic of "Art and Science". The same stellation is central to two lithographs by M. C. Escher: Contrast (Order and Chaos), 1950, and Gravitation, 1952.

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

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Talk:Stellation

Old comment
it is a process to construct new poligons ( in two dimensions) and to construct new polyhedra in three dimensions. The process consist in extending the facial planes of the polyhedron untill they meet each other...the resulting polyhedron is the new stellated polyhedron. by IP 194.183.69.146 at 03:44, February 7, 2003

Stellation of polygons? (1D stellation diagrams?)
It seems like stellation of polygons ought to work like stellations of polyhedra. In polyhedra there's one face plane (stellation diagram) for every type of face, and each shows all the intersection boundaries, and each domain can be ON or OFF. In polygons, or especially regular polygons, a stellation diagram is a line with intersection points dividing domains. So a general polygonal stellation ought to have some sort of binary ON/OFF for each segment between points. Tom Ruen (talk) 22:31, 5 February 2015 (UTC)

Here are two examples of stellations of an octagon. I say "truncated square" rather than octagon because I wanted half symmetry, 2 types of edges to stellate, but unsure if that's really needed in these cases. I colored edges green and purple that represent the boundary of the stellation and showed the linear diagrams on the bottom Tom Ruen (talk) 22:57, 5 February 2015 (UTC)
 * Stellations_of_truncated_squares.png

 * This is another area where it is easy to be misled by bright ideas and poor resources. Coxeter's treatment of stellation was fundamentally different from his predecessors - Bradwardine, Kepler, Poinsot, Cauchy, Cayley. This has not been helped by Coxeter's use of their definition before blithely presenting his own work as if it were consistent. Bradwardine studied only cyclic polygons, Kepler expanded the idea to polyhedra by extending the sides or faces continuously from the original. Wheeler studied stellation diagrams more closely and observed the way that the face planes divided space into cells, whose edges are segments of the lines of intersection. Coxeter then took this cell-based approach to its logical conclusion, apparently unaware that it was not consistent with Kepler. For example one of his fifty-nine icosahedra is just a loose gaggle of small shards floating in space and entirely disconnected from each other: hardly an "extension" of a core figure which is not even present. Technically one could say that a "stellation diagram" of a polygon is a set of collinear points with some segments drawn in, but it is pretty trivial and non-encyclopedic. If you want to explore them for yourself then I would suggest a uniform or quasiregular polygon, since it has two (alternating) kinds of edge, but I will not be discussing further anything non-encyclopedic. — Cheers, Steelpillow (Talk) 12:28, 6 February 2015 (UTC)
 * My primary interest if I support including something is to aid understanding of the 3D stellations, so if its trivial, that makes it a good candidate for teaching something new. But I admit the messy disconnected stellations (59 icosahedra) never much attracted me, only those that showed the relations to the regular polyhedra and compounds. Tom Ruen (talk) 20:22, 6 February 2015 (UTC)

Graphic of enneagon
I guess I'm just a bit confused about the designation {9/2} etc. I can see how having 9 points and going to the 4th one around can make the star shape shown, but why is the same shape shown with different numbers? All the shapes are {9/4}, just coloured differently. The examples with 7 sided shapes going around at different rates make perfect sense. Can any one explain??

Thanks WesT (talk) 04:08, 13 March 2015 (UTC)

 * Yes, The star polygons named {9/p} are the colored ones with the full stellation, the black one. Maybe it would be more clear if the black edges were recolored to be less prominent as lighter gray? Tom Ruen (talk) 09:51, 13 March 2015 (UTC)

 * The confusion arises because the graphic is misleading. The Large black-lined figure repeated four times is not the enneagon itself but the stellation diagram (technically the black lines extend to infinity). The enneagon is the coloured bit in the middle. Either the accompanying caption should make this clear (and the stellation diagrams made less prominent through thinning), or the stellation diagrams removed and just the enneagons left in. — Cheers, Steelpillow (Talk) 10:11, 13 March 2015 (UTC)
 * I lightened the outline, maybe that'll help. Tom Ruen (talk) 11:27, 13 March 2015 (UTC)

Thanks for the efforts, but the caption still doesn't seem to fit in with the examples to the left. On the left example, there are pictures showing how each n-gon is formed. It is clear how the numbers in braces show the total number of points and the number skipped to get to the next connected point. In fact it specifically says that the {6,2} is two triangles, which is shown. The problem with the 9-gon is that the caption says the {9,3} is three triangles, yet none of the pictures with the coloured areas are anything but variations on the {9,4}. If, as the caption says, the {9,3} is three triangles, then where are the three triangles in the picture labelled as {9,3}?? WesT (talk) 17:29, 17 April 2015 (UTC)
 * I have clarified the caption a bit. Any better? — Cheers, Steelpillow (Talk) 05:15, 18 April 2015 (UTC)

It looks like small mistake: The enneagon (nonagon) {3} has 3.... I think, must be:The enneagon (nonagon) {9} has 3...Jumpow (talk) 09:01, 23 November 2015 (UTC)
 * Thank you. Now corrected. — Cheers, Steelpillow (Talk) 11:40, 23 November 2015 (UTC)

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 * Academ Stellated dodecagon.svg

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Adalberto Rodríguez

Adalberto Rodríguez (January 22, 1934 – April 16, 1995), better known as Machuchal, was a Puerto Rican actor and comedian.

Rodríguez was born in the town of Sabana Grande, in southwest Puerto Rico. In his boyhood years he imitated animal sounds for his elementary school peers. His "Machuchal" stage name is that of the Sabana Grande barrio where he grew up. He enjoyed calling himself "El alcalde de Machuchal", (the Mayor of Machuchal). The joke not only prevailed, it also helped launch him into stardom.

At age 17 and following high school, (1951), Adalberto Rodríguez moved to Río Piedras to enter the University of Puerto Rico with a view to obtaining a bachelor's degree in business administration, and then, to pursue the career of attorney. Shortly after and at the same time, he worked as an announcer on radio station WIAC.

Machuchal was drafted to the military service in 1953 and served in the United States Army with the 82nd Airborne Division in Fort Bragg, North Carolina. He also fought in the Korean War. After his discharge in 1955 Rodríguez went back to Puerto Rico and resumed his studies in business administration at UPR, which he finished in 1957.

Rodríguez played the role of Puerto Rico's mountain man, known as Jíbaro. He would wear the typical Jíbaro straw hat and the farmer's typical shirt for many years on his daily appearances on Telemundo Puerto Rico's midday show, El Show de las 12.

Rodríguez also participated in La Taberna India, (The "India" Tavern), a show that was sponsored for many years by the Puerto Rican beer of the same name. When La Taberna India moved to WAPA-TV in 1985-having by then become "La Taberna Budweiser", Machuchal also moved to Telemundo Puerto Rico's fiercest rival.

Rodríguez once prompted Mexican comedian Cantinflas to compliment him, saying that nobody in the world made him laugh like Machuchal did. Machuchal also participated in some movies, including Machuchal En Nueva York and El Agente 0.

Rodríguez also worked alongside other Puerto Rican show business figures, such as Tommy Muñiz, José Miguel Agrelot, Elin Ortiz, Sonia Noemí, and Eddie Miró.

Filmography
Rodriguez participated in many movies, most of them Puerto Rican productions but also in Mexican-Puerto Rican co-productions. He often played "Machuchal" or versions of the "Machuchal" character in them.

 * Lamento Borincano
 * El Alcalde de Machuchal (1964, as Triburcio Perez)
 * Los Expatriados (1964)
 * Millonario a Go Go (1965, as "Machuchal")
 * C.65 (1965, short film)
 * Rosa, La Tequilera (1967, he played two roles, those of "Machuchal" and of Graziano)
 * El Curandero del Pueblo (1968, as Machuchal)
 * Machuchal, Agente O en New York (1970, as "Machuchal", this time a policeman)
 * Poor But Honest (1973)
 * Mulato (1974)
 * Eva, ¿qué hace ese hombre en tu cama? (1975)

Death
Adalberto Rodríguez died on April 16, 1995, in Hato Rey, Puerto Rico. He was buried at the Sabana Grande Masonic Cemetery in his hometown Sabana Grande, Puerto Rico. It's unknown the cause of Machuchal's passing.

title: Adalberto Rodríguez


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Talk:Map projection

Classification of old maps without projection?
In Commons we have problem with old maps and their projections. Wise advices will be needed in here: Commons:Commons:Categories for discussion/2018/01/Category:Maps with unidentified projection--Estopedist1 (talk) 10:39, 29 November 2021 (UTC)

Gigantic
"The projections are described in terms of placing a gigantic surface in contact with the Earth" - violation of NPOV? Who defined the surface as gigantic? Is that encyclopedic? Euro2023 (talk) 23:54, 9 January 2023 (UTC)

 * Do you believe that the use of English adverbs and adjectives is automatically unencyclopedic, and that encyclopedic language should be limited only to nouns, verbs, and connecting words? —David Eppstein (talk) 00:06, 10 January 2023 (UTC)
 * I changed the wording to convey the same meaning. Gigantic is relative, and map projection is not only limited to the Earth.  GeogSage  ( ⚔Chat?⚔ ) 00:23, 10 January 2023 (UTC)

light shining through a globe - then the spacing of parallels would follow a very limited set of possibilities
"If maps were projected as in light shining through a globe onto a developable surface, then the spacing of parallels would follow a very limited set of possibilities." - How that? Why should there be a limitation? Is there projection of a particular point on a surface that cannot be reached by "light shining through a globe"? Euro2023 (talk) 15:45, 10 January 2023 (UTC)
 * The set of projections defined by projective geometry is grossly limited compared to the the set that is possible from more general mathematical transformations permitted in the common definition of cylindrical projection. Strebe (talk) 19:24, 10 January 2023 (UTC)
 * "in the common definition of cylindrical projection" isn't contained in the claim, or the text next to it, that I copied from the article. And where is the evidence that such a "common definition of cylindrical projection" exists? https://en.wikipedia.org/w/index.php?search=%22common+definition+of+cylindrical+projection%22&title=Special:Search&profile=advanced&fulltext=1&ns0=1 : "There were no results matching the query." Euro2023 (talk) 19:36, 10 January 2023 (UTC)

 * The common definition, whatever it is or isn’t, does encompass the Mercator projection, as per all the literature in existence. Meanwhile, the Mercator projection cannot be represented just by “light shining through a globe onto a developable surface”. Therefore, given that we have an example (and scores more) of cylindrical projections that cannot be represented by “light shining through a globe onto a developable surface”, the statement is fine. Strebe (talk) 21:33, 10 January 2023 (UTC)

WikiProject
I have created a proposal page for Map projections. Please feel free to add your name to the support section, discuss, disseminate, and otherwise edit. Thanks. Strebe (talk) 01:26, 12 January 2023 (UTC)

See also, ,
See also, geoinformatics has 2 commas in a row separated by a space. I can't figure out if there's something missing or how to remove one of them. 82.135.221.10 (talk) 15:41, 7 July 2024 (UTC)
 * Fixed, thanks! The extra commas were part of the geoinformatics article's short description. Just plain Bill (talk) 16:02, 7 July 2024 (UTC)

title: Talk:Map projection


text:
Fairchild Semiconductor

Fairchild Semiconductor International, Inc. was an American semiconductor company based in San Jose, California. It was founded in 1957 as a division of Fairchild Camera and Instrument by the "traitorous eight" who defected from Shockley Semiconductor Laboratory. It became a pioneer in the manufacturing of transistors and of integrated circuits. Schlumberger bought the firm in 1979 and sold it to National Semiconductor in 1987; Fairchild was spun off as an independent company again in 1997. In September 2016, Fairchild was acquired by ON Semiconductor.

The company had locations in the United States at San Jose, California; San Rafael, California; South Portland, Maine; West Jordan, Utah; and Mountaintop, Pennsylvania. Outside the US, it operated locations in Australia; Singapore; Bucheon, South Korea; Penang, Malaysia; Suzhou, China; and Cebu, Philippines, among others.

1950s

In 1955, William Shockley founded Shockley Semiconductor Laboratory, funded by Beckman Instruments in Mountain View, California; his plan was to develop a new type of "4-layer diode" that would work faster and have more uses than then-current transistors. At first he attempted to hire some of his former colleagues from Bell Labs, but none were willing to move to the West Coast or work with Shockley again at that time. Shockley then founded the core of the new company with what he considered the best and brightest graduates coming out of American engineering schools.

While Shockley was effective as a recruiter, he was less effective as a manager. A core group of Shockley employees, later known as the traitorous eight, became unhappy with his management of the company. The eight men were Julius Blank, Victor Grinich, Jean Hoerni, Eugene Kleiner, Jay Last, Gordon Moore, Robert Noyce, and Sheldon Roberts. Looking for funding on their own project, they turned to Sherman Fairchild's Fairchild Camera and Instrument, an Eastern U.S. company with considerable military contracts. In 1957 the Fairchild Semiconductor division was started with plans to make silicon transistors at a time when germanium was still the most common material for semiconductor use.

According to Sherman Fairchild, Noyce's impassioned presentation of his vision was the reason Sherman Fairchild had agreed to create the semiconductor division for the traitorous eight. Noyce advocated the use of silicon as substrate – since the material costs would consist of sand and a few fine wires, the major cost would be in the manufacturing process. Noyce also expressed his belief that silicon semiconductors would herald the start of disposable appliances that, due to cheap electronic components, would not be repaired but merely discarded when worn out.

Their first transistors were of the silicon mesa variety, innovative for their time, but exhibiting relatively poor reliability.

Fairchild's first marketed transistor was the 1958 2N697, a mesa transistor developed by Moore, and it was a success. The first batch of 100 was sold to IBM for $150 apiece in order to build the computer for the B-70 bomber. More were sold to Autonetics to build the guidance system for the Minuteman ballistic missile.

At the same time Jean Hoerni developed the planar process which was a major improvement – transistors could be made more easily, at a lower cost and with greater performance and reliability.

The planar process made most other transistor processes obsolete. One such casualty was Philco's transistor division, whose newly built $40 million plant to make their germanium PADT process transistors became nonviable. Within a few years, every other transistor company paralleled or licensed the Fairchild planar process. Hoerni's 2N1613 was a major success, with Fairchild licensing the design across the industry.

In 1960, Fairchild built a circuit with four transistors on a single wafer of silicon, thereby creating the first silicon integrated circuit (Texas Instruments' Jack Kilby had developed an integrated circuit made of germanium on September 12, 1958, and was awarded a U.S. patent, however Kilby's method was not scalable and the semiconductor industry adopted Fairchild's process to manufacture integrated circuits). The company grew from twelve to twelve thousand employees, and was soon making $130 million a year.

1960s
Fairchild's Noyce and Texas Instrument's Kilby had independently invented the integrated circuit (IC) based on bipolar technology. In 1960, Noyce invented the planar integrated circuit. The industry preferred Fairchild's invention over Texas Instruments' because the transistors in planar ICs were interconnected by a thin film deposit, whereas Texas Instruments' invention required fine wires to connect the individual circuits. Noyce's invention was enabled by the planar process developed by Jean Hoerni. In turn, Hoerni's planar process was inspired by the surface passivation method developed by Mohamed Atalla at Bell Labs in 1957.

In the early 1960s, Fairchild R&D began experimenting with the MOSFET (metal–oxide–semiconductor field-effect transistor), also known as the MOS transistor. The first MOSFET was invented by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959, and demonstrated in early 1960, but was initially overlooked and ignored by Bell Labs. However, the MOSFET generated significant interest at Fairchild. Inspired by the first MOSFET, Chih-Tang Sah built an MOS-controlled tetrode at Fairchild later that year. MOS devices were later commercialized by Fairchild in 1964, with p-channel devices for logic and switching applications. The experiments led to Fairchild's development of MOS integrated circuits.

In 1963, Fairchild hired Robert Widlar to design analog operational amplifiers using Fairchild's process. Since Fairchild's processes were optimized for digital circuits, Widlar collaborated with process engineer Dave Talbert. The collaboration resulted in two revolutionary products – μA702 and μA709. Hence, Fairchild dominated the analog integrated circuit market, having introduced the first IC operational amplifiers, or "op-amps", Bob Widlar's μA702 (in 1964) and μA709. In 1968, Fairchild introduced David Fullagar's μA741, which became the most popular IC op amp of all time.

By 1965, Fairchild's process improvements had brought low-cost manufacturing to the semiconductor industry – making Fairchild nearly the only profitable semiconductor manufacturer in the United States. Fairchild dominated the market in DTL, op-amps and mainframe computer custom circuits. In 1965, Fairchild opened a semiconductor assembly plant on the Navajo Nation in Shiprock, New Mexico. At its peak, the plant employed over a thousand Navajos, the majority of whom were women. In The Shiprock Dedication Commemorative Brochure released by the Fairchild company, the Diné (Navajo) women circuit makers were celebrated as "culture workers who produced circuits as part of the 'reproductive' labor of expressing Navajo culture, rather than merely for wages." This claim was based on the opinion that circuits of the electronic chips had a mere resemblance with the complex geometric patterns on the Navajo rugs. Paul Driscoll, the Shiprock plant manager, spoke of the "untapped wealth of natural characteristics of the Navajo...the inherent flexibility and dexterity of the Indians." Although highly successful during its operation, the plant was closed in 1975. While the Fairchild corporation claims the Diné women were chosen to work in the Shiprock plant due to their "'nimble fingers'" as previously noted, the women of the Shiprock reservation were actually chosen as the workforce due to a lack of labor rights asserted by the women in addition to "cheap, plentiful workers and tax benefits".

Fairchild had not done well in the digital integrated circuit market. Their first line of ICs was the "micrologic" resistor–transistor logic (RTL) line which was used in the Apollo Guidance Computer. It had the advantage of being extremely simple – each inverter consisted of just one transistor and two resistors. The logic family had many drawbacks that had made it marginal for commercial purposes, and not well suited for military applications: the logic could only tolerate about 100 millivolts of noise – far too low for comfort. It was awhile before Fairchild relied on more robust designs, such as diode–transistor logic (DTL) which had much better noise margins.

Sales due to Fairchild semiconductor division had doubled each year and by the mid-1960s comprised two-thirds of total sales of the parent company. In 1966, Fairchild's sales were second to those of Texas Instruments, followed in third place by Motorola. Noyce was rewarded with the position of corporate vice-president and hence became the de facto head of the semiconductor division.

However, internal trouble at Fairchild began to surface with a drop in earnings in 1967. There was increasing competition from newer start-ups. The semiconductor division, situated in Mountain View and Palo Alto, California, was actually managed by executives from Syosset, New York, who visited the California sites once a year, even though the semiconductor division earned most of the profits of the company. Fairchild's president at that time, John Carter, had used all the profits to fund acquisitions of unprofitable ventures.

Noyce's position on Fairchild's executive staff was consistently compromised by Sherman Fairchild's faction. Charles E. Sporck was Noyce's operations manager. Sporck was reputed to run the tightest operation in the world. Sporck, Pierre Lamond and most managers had grown upset and disillusioned with corporate focus on unprofitable ventures at the expense of the semiconductor division. Executives at the semiconductor division were allotted substantially fewer stock options compared to other divisions. In March 1967, Sporck was hired away by Peter J. Sprague to National Semiconductor. Sporck brought with him four other Fairchild personnel. Actually, Lamond had previously assembled a team of Fairchild managers in preparation to defect to Plessey, a British company. Lamond had recruited Sporck to be his own boss. When negotiations with Plessey broke down over stock options, Lamond and Sporck succumbed to Widlar's and Talbert's (who were already employed at National Semiconductor) suggestion that they look to National Semiconductor. Widlar and Talbert had earlier left Fairchild to join Molectro, which was later acquired by National Semiconductor.

In the fall of 1967, Fairchild suffered a loss for the first time since 1958 and announced write-offs of $4 million due to excess capacity, which contributed to a total loss of $7.6 million. Profits had sunk to $0.50 a share, compared to $3 a share the previous year, while the value of the stock dropped in half. In October 1967, the board ordered Carter to sell off all of Fairchild's unprofitable ventures. Carter responded to the order by resigning abruptly.

Furthermore, Fairchild's DTL technology was being overtaken by Texas Instruments's faster TTL (transistor–transistor logic).

While Noyce was considered the natural successor to Carter, the board decided not to promote him. Sherman Fairchild led the board to choose Richard Hodgson. Within a few months Hodgson was replaced by a management committee led by Noyce, while Sherman Fairchild looked for a new CEO other than Noyce. In response, Noyce discreetly planned a new company with Gordon Moore, the head of R&D. They left Fairchild to found Intel in 1968 and were soon joined by Andrew Grove and Leslie L. Vadász, who took with them the revolutionary MOS Silicon Gate Technology (SGT), recently created in the Fairchild R&D Laboratory by Federico Faggin who also designed the Fairchild 3708, the world’s first commercial MOS integrated circuit using SGT. Fairchild MOS Division was slow in understanding the potential of the SGT which promised not only faster, more reliable, and denser circuits, but also new device types that could enlarge the field of solid state electronics – for example, CCDs for image sensors, dynamic RAMs, and non-volatile memory devices such as EPROM and flash memories. Intel took advantage of the SGT for its memory development. Federico Faggin, frustrated, left Fairchild to join Intel in 1970 and design the first microprocessors using SGT. Among the investors of Intel were Hodgson and five of the founding members of Fairchild.

Sherman Fairchild hired Lester Hogan, who was the head of Motorola semiconductor division. Hogan proceeded to hire another hundred managers from Motorola to entirely displace the management of Fairchild.

The loss of these iconic executives, coupled with Hogan's displacement of Fairchild managers demoralized Fairchild and prompted the entire exodus of employees to found new companies.

Many of the original founders, otherwise known as the "fairchildren", had left Fairchild in the 1960s to form companies that grew to prominence in the 1970s. Robert Noyce and Gordon Moore were among the last of the original founders to leave, at which point the brain-drain of talents that had fueled the growth of the company was complete.

A Fairchild advertisement of the time showed a collage of the logos of Silicon Valley with the annotation "We started it all". It was later, in 1971, Don Hoefler popularizated the name "Silicon Valley USA" in Electronic News. He notes he did not invent the name. See also Gregory Gromov and TechCrunch 2014 update of Hoefler's article.

1970s
Hogan's action to hire from Motorola had Motorola file a lawsuit against Fairchild, which the court then decided in Fairchild's favor in 1973. Judge William Copple ruled that Fairchild's results were so unimpressive that it was impossible to assess damages "under any theory". Hogan was dismissed as president the next year, but remained as vice chairman.

In 1973, Fairchild became the first company to produce a commercial charge-coupled device (CCD) following its invention at Bell Labs. Digital image sensors are still produced today at their descendant company, Fairchild Imaging. The CCD had a difficult birth, with the devastating effects on Fairchild of the 1973–75 recession that followed on the 1973 oil crisis.

After Intel introduced the 8008 8-bit microprocessor, Fairchild developed the Fairchild F8 8-bit microprocessor, which was according to the CPU Museum "in 1977 the F8 was the world's leading microprocessor in terms of CPU sales."

In 1976, the company released the first video game system to use ROM cartridges, the Fairchild Video Entertainment System (or VES) later renamed Channel F, using the F8 microprocessor. The system was successful initially, but quickly lost popularity when the Atari 2600 Video Computer System (or VCS) was released.

By the end of the 1970s they had few new products in the pipeline, and increasingly turned to niche markets with their existing product line, notably "hardened" integrated circuits for military and space applications and isoplanar ECL products used in exotic applications like Cray Computers. Fairchild was being operated at a loss, and the bottomline subsisted mostly from licensing of its patents.

In 1979, Fairchild Camera and Instrument was purchased by Schlumberger Limited, an oil field services company, for $425 million. At this time, Fairchild's intellectual properties, on which Fairchild had been subsisting, were expiring.

1980s
In 1980, under Schlumberger management, the Fairchild Laboratory for Artificial Intelligence Research (FLAIR) was started within Fairchild Research. In 1985 the lab was separated to form Schlumberger Palo Alto Research (SPAR).

Fairchild research developed the Clipper architecture, a 32-bit RISC-like computer architecture, in the 1980s, resulting in the shipping of the C100 chip in 1986. The technology was later sold to Intergraph, its main customer.

Schlumberger sold Fairchild to National Semiconductor in 1987 for $200 million. The sale did not include Fairchild's Test Division, which designed and produced automated test equipment (ATE) for the semiconductor manufacturing industry, nor did it include Schlumberger Palo Alto Research.

In the early 1980s, Fairchild was one of several silicon valley tech companies involved in a lawsuit brought on by residents of San Jose, California. The case pertained to industrial solvent contamination of ground water and soil in San Jose's Los Paseos neighborhood. A settlement was reached and the area designated a superfund. Superfund site cleanup ended in 1998.

1990s
In 1997, the reconstituted Fairchild Semiconductor was reborn as an independent company, based in South Portland, Maine, with Kirk Pond as CEO.

On March 11, 1997, National Semiconductor Corporation announced the US$550 million sale of a reconstituted Fairchild to the management of Fairchild with the backing of Sterling LLC, a unit of Citicorp Venture Capital. Fairchild carried with it what was mostly the Standard Products group previously segregated by Gil Amelio.

The Fairchild Semiconductor Corporation announced November 27, 1997, that it would acquire the semiconductor division of the Raytheon Corporation for about $120 million in cash. The acquisition was completed on December 31, 1997.

In December 1998, Fairchild announced the acquisition of Samsung's power division, which made power MOSFETs, IGBTs, etc. The deal was finalized in April 1999 for $450 million. To this day, Fairchild remains an important supplier for Samsung.

In August 1999, Fairchild Semiconductor again became a publicly traded company on the New York Stock Exchange with the ticker symbol FCS. Fairchild's South Portland, Maine, and Mountaintop, Pennsylvania, locations are the longest continuously operating semiconductor manufacturing facilities in the world, both operating since 1960.

2000s
On March 19, 2001, Fairchild Semiconductor announced that it had completed the acquisition of Intersil Corporation's discrete power business for approximately $338 million in cash. The acquisition moved Fairchild into position as the second-largest power MOSFET supplier in the world, representing a 20 percent share of this $3 billion market that grew 40 percent last year.

On September 6, 2001, Fairchild Semiconductor announced the acquisition of Impala Linear Corporation, based in San Jose, California, for approximately $6 million in stock and cash. Impala brought with it expertise in designing analog power management semiconductors for hand-held devices like laptops, MP3 players, cell phones, portable test equipment and PDAs.

On January 9, 2004, Fairchild Semiconductor CEO Kirk Pond was appointed as a Director of the Federal Reserve Bank of Boston, elected by member banks to serve a three-year term.

On April 13, 2005, Fairchild announced appointment of Mark Thompson as CEO of the corporation. Thompson would also be President, Chief Executive Officer and a member of the board of directors of Fairchild Semiconductor International. He originally joined Fairchild as Executive Vice President, Manufacturing and Technology Group.

On March 15, 2006, Fairchild Semiconductor announced that Kirk P. Pond would retire as Chairman at the company's annual stockholders' meeting on May 3, 2006. Pond would continue as a member of the company’s board of directors. Mark Thompson (then CEO) became Chairman.

On September 1, 2007, New Jersey-based RF semiconductor supplier Anadigics acquired Fairchild Semiconductor's RF design team, located in Tyngsboro, Massachusetts, for $2.4 million.

2010s
In April 2011, Fairchild Semiconductor acquired TranSiC, a silicon carbide power transistor company originally based in Sweden.

On November 18, 2015, ON Semiconductor made an offer to acquire Fairchild Semiconductor for $2.4 billion (or $20 per share) after a few months of speculation that Fairchild was seeking a potential buyer.

On April 10, 2016, Fairchild Semiconductor moved its headquarters from San Jose (3030 Orchard Pkwy.) to Sunnyvale (1272 Borregas Ave.).

On September 19, 2016, ON Semiconductor and Fairchild Semiconductor jointly announced that ON Semiconductor had completed its announced $2.4 billion cash acquisition of Fairchild.

In the fall of 2016, the Fairchild 'ON' Semiconductor International closed the West Jordan, Utah, manufacturing plant.

Landmark status

On May 8, 1991, the State Historic Preservation Office designated the site of invention of the first commercially practicable integrated circuit as a California historical landmark #1000. A description on the commemorative plaque reads: "At this site in 1959, Dr. Robert Noyce of Fairchild Semiconductor Corporation invented the first integrated circuit that could be produced commercially. Based on 'planar' technology, an earlier Fairchild breakthrough, Noyce's invention consisted of a complete electronic circuit inside a small silicon chip. His innovation helped revolutionize 'Silicon Valley's' semiconductor electronics industry, and brought profound change to the lives of people everywhere."

Alumni

 * Gil Amelio
 * Julius Blank
 * Lee Boysel
 * Ron Brachman
 * Wilfred Corrigan
 * Alan L. Davis
 * Richard O. Duda
 * James M. Early
 * Kirk Ennis
 * Federico Faggin
 * Jack Gifford
 * Victor Grinich
 * Andrew Grove
 * Peter E. Hart
 * Jean Hoerni
 * Lester Hogan
 * Eugene Kleiner
 * Pierre Lamond
 * Hector Levesque
 * Richard F. Lyon
 * Gordon Moore
 * Robert Noyce
 * Stav Prodromou
 * Chih-Tang Sah
 * Jerry Sanders
 * Ed Turney
 * Leslie L. Vadász
 * Frank Wanlass
 * Bob Widlar
 * Andrew Witkin
 * Don Valentine

title: Fairchild Semiconductor