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Pentium 4

Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. It was removed from the official price lists starting in 2010, being replaced by Pentium Dual-Core.

All Pentium 4 CPUs are based on the NetBurst microarchitecture. The Pentium 4 Willamette (180 nm) introduced SSE2, while the Prescott (90 nm) introduced SSE3 and later 64-bit technology. Later versions introduced Hyper-Threading Technology (HTT).

The first Pentium 4-branded processor to implement 64-bit was the Prescott (90 nm) (February 2004), but this feature was not enabled. Intel subsequently began selling 64-bit Pentium 4s using the "E0" revision of the Prescotts, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit) to Intel 64. Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M.

Intel also marketed a version of their low-end Celeron processors based on the NetBurst microarchitecture (often referred to as Celeron 4), and a high-end derivative, Xeon, intended for multi-socket servers and workstations. In 2005, the Pentium 4 was complemented by the dual-core-brands Pentium D and Pentium Extreme Edition.

On December 7, 2007, Intel discontinued orders for the Pentium 4 processor. The last shipments were made on August 8, 2008, along with the Pentium D.

Microarchitecture
In benchmark evaluations, the advantages of the NetBurst microarchitecture were unclear. With carefully optimized application code, the first Pentium 4s outperformed Intel's fastest Pentium III (clocked at 1.13 GHz at the time), as expected. But in legacy applications with many branching or x87 floating-point instructions, the Pentium 4 would merely match or run slower than its predecessor. Its main downfall was a shared unidirectional bus. The NetBurst microarchitecture consumed more power and emitted more heat than any previous Intel or AMD microarchitectures.

As a result, the Pentium 4's introduction was met with mixed reviews: Developers disliked the Pentium 4, as it posed a new set of code optimization rules. For example, in mathematical applications, AMD's lower-clocked Athlon (the fastest-clocked model was clocked at 1.2 GHz at the time) easily outperformed the Pentium 4, which would only catch up if software was re-compiled with SSE2 support. Tom Yager of Infoworld magazine called it "the fastest CPU – for programs that fit entirely in cache". Computer-savvy buyers avoided Pentium 4 PCs due to their price premium, questionable benefit, and initial restriction to Rambus' RDRAM. In terms of product marketing, the Pentium 4's singular emphasis on clock frequency (above all else) made it a marketer's dream. The result of this was that the NetBurst microarchitecture was often referred to as a marchitecture by various computing websites and publications during the life of the Pentium 4. It was also called "NetBust", a term popular with reviewers who reflected negatively upon the processor's performance.

The two classical metrics of CPU performance are instructions per cycle (IPC) and clock speed. While IPC is difficult to quantify due to dependence on the benchmark application's instruction mix, clock speed is a simple measurement yielding a single absolute number. Unsophisticated buyers would simply consider the processor with the highest clock speed to be the best product, and the Pentium 4 had the fastest clock speed. Because AMD's processors had slower clock speeds, it countered Intel's marketing advantage with the "megahertz myth" campaign. AMD product marketing used a "PR-rating" system, which assigned a merit value based on relative performance to a baseline machine.

At the launch of the Pentium 4, Intel stated that NetBurst-based processors were expected to scale to 10 GHz after several fabrication process generations. However, the clock speed of processors using the NetBurst microarchitecture reached a maximum of 3.8 GHz. Intel had not anticipated a rapid upward scaling of transistor power leakage that began to occur as the die reached the 90 nm lithography and smaller. This new power leakage phenomenon, along with the standard thermal output, created cooling and clock scaling problems as clock speeds increased. Reacting to these unexpected obstacles, Intel attempted several core redesigns (Prescott most notably) and explored new manufacturing technologies, such as using multiple cores, increasing FSB speeds, increasing the cache size, and using a longer instruction pipeline along with higher clock speeds.

The code cache was replaced by a trace cache which contained decoded microoperations rather than instructions with advantage of eliminating instruction decoding bottleneck so that the design can use RISC technology. This came with a disadvantage of less compact cache taking up more chip space and consuming power.

These solutions failed, and from 2003 to 2005, Intel shifted development away from NetBurst to focus on the cooler-running Pentium M microarchitecture. On January 5, 2006, Intel launched the Core processors, which put greater emphasis on energy efficiency and performance per clock cycle. The final NetBurst-derived products were released in 2007, with all subsequent product families switching exclusively to the Core microarchitecture.

Testing and validation
According to Bob Bentley, presenting on behalf of Intel at the 38th annual Design Automation Conference, "The microarchitecture of the Pentium 4 processor is significantly more complex than any previous IA-32 microprocessor, so the challenge of validating the logical correctness of the design in a timely fashion was indeed a daunting one." He hired a team of 60 recent graduates to help with testing and validation.

Processor cores
Pentium 4 processors have an integrated heat spreader (IHS) that prevents the die from accidentally being damaged when mounting and unmounting cooling solutions. Prior to the IHS, a CPU shim was some times used by people worried about damaging the core. Overclockers sometimes removed the IHS from Socket 423 and Socket 478 chips to allow for more direct heat transfer. On Socket 478 Prescott processors and processors using the Socket LGA 775 (Socket T) interface, the IHS is directly soldered to the die or dies, making it difficult to remove.

Willamette

Willamette, the project codename for the first NetBurst microarchitecture implementation, experienced long delays in the completion of its design process. The project was started in 1998, when Intel saw the Pentium II as their permanent line. At that time, the Willamette core was expected to operate at frequencies up to about 1 GHz. However, the Pentium III was released while Willamette was still being finished. Due to the radical differences between the P6 and NetBurst microarchitectures, Intel could not market Willamette as a Pentium III, so it was marketed as the Pentium 4.

On November 20, 2000, Intel released the Willamette-based Pentium 4 clocked at 1.4 and 1.5 GHz. Most industry experts regarded the initial release as a stopgap product, introduced before it was truly ready. According to these experts, the Pentium 4 was released because the competing Thunderbird-based AMD Athlon was outperforming the aging Pentium III, and further improvements to the Pentium III were not yet possible. This Pentium 4 was produced using a 180 nm process and initially used Socket 423 (also called socket W, for "Willamette"), with later revisions moving to Socket 478 (socket N, for "Northwood"). These variants were identified by the Intel product codes 80528 and 80531 respectively.

On the test bench, the Willamette was somewhat disappointing to analysts in that not only was it unable to outperform the Athlon and the highest-clocked Pentium IIIs in all testing situations, but it was not superior to the budget segment's AMD Duron. Although introduced at prices of $644 (1.4 GHz) and $819 (1.5 GHz) for 1000 quantities to OEM PC manufacturers (prices for models for the consumer market varied by retailer), it sold at a modest but respectable rate, handicapped somewhat by the requirement for relatively fast yet expensive Rambus Dynamic RAM (RDRAM). The Pentium III remained Intel's top selling processor line, with the Athlon also selling slightly better than the Pentium 4. While Intel bundled two RDRAM modules with each boxed Pentium 4, it did not facilitate Pentium 4 sales and was not considered a true solution by many.

In January 2001, a still slower 1.3 GHz model was added to the range, but over the next twelve months, Intel gradually started reducing AMD's leadership in performance. In April 2001 a 1.7 GHz Pentium 4 was launched, the first model to provide performance clearly superior to the old Pentium III. July saw 1.6 and 1.8 GHz models and in August 2001, Intel released 1.9 and 2 GHz Pentium 4s. In the same month, they released the 845 chipset that supported much cheaper PC133 SDRAM instead of RDRAM. The fact that SDRAM was so much cheaper caused the Pentium 4's sales to grow considerably. The new chipset allowed the Pentium 4 to quickly replace the Pentium III, becoming the top-selling mainstream processor on the market.

The Willamette code name is derived from the Willamette Valley region of Oregon, where a large number of Intel's manufacturing facilities are located.

Northwood
In January 2002, Intel released Pentium 4s with a new core codenamed Northwood at speeds of 1.6 GHz, 1.8 GHz, 2 GHz and 2.2 GHz. Northwood (product code 80532) combined an increase in the L2 cache size from 256 KB to 512 KB (increasing the transistor count from 42 million to 55 million) with a transition to a new 130 nm fabrication process. Making the processor out of smaller transistors means that it can run at higher clock speeds and produce less heat. In the same month boards utilizing the 845 chipset were released with enabled support for DDR SDRAM which provided double the bandwidth of PC133 SDRAM, and alleviated the associated high costs of using Rambus RDRAM for maximal performance with Pentium 4.

A 2.4 GHz Pentium 4 was released on April 2, 2002, and the bus speed increased from 400 MT/s to 533 MT/s (133 MHz physical clock) for the 2.26 GHz, 2.4 GHz, and 2.53 GHz models in May, 2.66 GHz and 2.8 GHz models in August, and 3.06 GHz model in November. With Northwood, the Pentium 4 came of age. The battle for performance leadership remained competitive (as AMD introduced faster versions of the Athlon XP) but most observers agreed that the fastest-clocked Northwood-based Pentium 4 was usually ahead of its rival. This was particularly so in mid-2002, when AMD's changeover to its 130 nm production process did not help the initial "Thoroughbred A" revision Athlon XP CPUs to clock high enough to overcome the advantages of Northwood in the 2.4 to 2.8 GHz range.

The 3.06 GHz Pentium 4 enabled Hyper-Threading Technology that was first supported in Foster-based Xeons. This began the convention of virtual processors (or virtual cores) under x86 by enabling multiple threads to be run at the same time on the same physical processor. By shuffling two (ideally differing) program instructions to simultaneously execute through a single physical processor core, the goal is to best utilize processor resources that would have otherwise been unused from the traditional approach of having these single instructions wait for each other to execute singularly through the core. This initial 3.06 GHz 533FSB Pentium 4 Hyper-Threading enabled processor was known as Pentium 4 HT and was introduced to mass market by Gateway in November 2002.

On April 14, 2003, Intel officially launched the new Pentium 4 HT processor. This processor used an 800 MT/s FSB (200 MHz physical clock), was clocked at 3 GHz, and had Hyper-Threading technology. This was meant to help the Pentium 4 better compete with AMD's Opteron line of processors. Meanwhile, with the launch of the Athlon XP 3200+ in AMD's desktop line, AMD increased the Athlon XP's FSB speed from 333 MT/s to 400 MT/s, but it was not enough to hold off the new 3 GHz Pentium 4 HT.

The Pentium 4 HT's increase to a 200 MHz quad-pumped bus (200 x 4 = 800 MHz effective) greatly helped to satisfy the bandwidth requirements the NetBurst architecture desired for reaching optimal performance. While the Athlon XP architecture was less dependent on bandwidth, the bandwidth numbers reached by Intel were well out of range for the Athlon's EV6 bus. Hypothetically, EV6 could have achieved the same bandwidth numbers, but only at speeds unreachable at the time. Intel's higher bandwidth proved useful in benchmarks for streaming operations, and Intel marketing wisely capitalized on this as a tangible improvement over AMD's desktop processors. Northwood 2.4 GHz, 2.6 GHz and 2.8 GHz variants were released on May 21, 2003. A 3.2 GHz variant was launched on June 23, 2003 and the final 3.4 GHz version arrived on February 2, 2004.

Overclocking early stepping Northwood cores yielded a startling phenomenon. While core voltage approaching 1.7 V and above would often allow substantial additional gains in overclocking headroom, the processor would slowly (over several months or even weeks) become more unstable over time with a degradation in maximum stable clock speed before dying and becoming totally unusable. This became known as Sudden Northwood Death Syndrome (SNDS), which was caused by electromigration.

Pentium 4 M
Also based on the Northwood core, the Mobile Intel Pentium 4 Processor - M (also known as the Pentium 4 M) was released on April 23, 2002, and included Intel's SpeedStep and Deeper Sleep technologies. Its TDP is about 35 watts in most applications. This lowered power consumption was due to lowered core voltage, and other features mentioned previously.

Unlike the desktop Pentium 4, the Pentium 4 M did not feature an integrated heat spreader (IHS), and it operates at a lower voltage. The lower voltage means lower power consumption, and in turn less heat. However, according to Intel specifications, the Pentium 4 M had a maximum thermal junction temperature rating of 100 degrees C, approximately 40 degrees higher than the desktop Pentium 4.

Mobile Pentium 4
The Mobile Intel Pentium 4 Processor was released to address the problem of putting a full desktop Pentium 4 processor into a laptop, which some manufacturers were doing. The Mobile Pentium 4 used a 533 MT/s FSB, following the desktop Pentium 4's evolution. Oddly, increasing the bus speed by 133 MT/s (33 MHz) caused a massive increase in TDPs, as mobile Pentium 4 processors emitted 59.8–70 W of heat, with the Hyper-Threading variants emitting 66.1–88 W. This allowed the mobile Pentium 4 to bridge the gap between the desktop Pentium 4 (up to 115 W TDP), and the Pentium 4 M (up to 35 W TDP).

Intel's naming conventions made it difficult at the time of the processor's release to identify the processor model. There was the Pentium III mobile chip, the Pentium 4 M, the Mobile Pentium 4, and then the Pentium M, which itself was based on the Pentium III and was significantly faster and more power-efficient than the former three.

Northwood (Extreme Edition)
In September 2003, at the Intel Developer Forum, the Pentium 4 Extreme Edition (P4EE) was announced, just over a week before the launch of Athlon 64 and Athlon 64 FX. The design was mostly identical to Pentium 4 (to the extent that it would run in the same motherboards), but differed by an added 2 MB of level 3 cache. It shared the same Gallatin core as the Xeon MP, though in a Socket 478 form factor (as opposed to Socket 603 for the Xeon MP) and with an 800 MT/s bus, twice as fast as that of the Xeon MP.

While Intel maintained that the Extreme Edition was aimed at gamers, critics viewed it as an attempt to steal the Athlon 64's launch thunder, nicknaming it the "Emergency Edition". With a price tag of $1000, it was also referred to as the "Expensive Edition" and "Extremely Expensive".

The added cache generally resulted in a noticeable performance increase in most processor intensive applications. Multimedia encoding and certain games benefited the most, with the Extreme Edition outperforming the Pentium 4, and even the two Athlon 64 variants, although the lower price and more balanced performance of the Athlon 64 (particularly the non-FX version) led to it usually being seen as the better value proposition. Nonetheless, the Extreme Edition did achieve Intel's apparent aim, which was to prevent AMD from being the performance champion with the new Athlon 64, which was winning every single major benchmark over the existing Pentium 4s.

In January 2004, a 3.4 GHz version was released for Socket 478, and in Summer 2004 the CPU was released using the new Socket 775 (LGA 775). A slight performance increase was achieved in late 2004 by increasing the bus speed from 800 MT/s to 1066 MT/s, resulting in a 3.46 GHz Pentium 4 Extreme Edition. By most metrics, this was on a per-clock basis the fastest single-core NetBurst processor that was ever produced, even outperforming many of its successor chips (not counting the dual-core Pentium D). Afterwards, the Pentium 4 Extreme Edition was migrated to the Prescott core. The new 3.73 GHz Extreme Edition had the same features as a 6x0-sequence Prescott 2M, but with a 1066 MT/s bus. In practice however, the 3.73 GHz Pentium 4 Extreme Edition almost always proved to be slower than the 3.46 GHz Pentium 4 Extreme Edition, which is most likely due to the lack of an L3 cache and the longer instruction pipeline. The only advantage the 3.73 GHz Pentium 4 Extreme Edition had over the 3.46 GHz Pentium 4 Extreme Edition was the ability to run 64-bit applications since all Gallatin-based Pentium 4 Extreme Edition processors lacked the Intel 64 (then known as EM64T) instruction set.

Although never a particularly good seller, especially since it was released in a time when AMD was asserting near total dominance in the processor performance race, the Pentium 4 Extreme Edition established a new position within Intel's product line, that of an enthusiast oriented chip with the highest-end specifications offered by Intel chips, along with unlocked multipliers to allow for easier overclocking. In this role it has since been succeeded by the Pentium Extreme Edition (The Extreme version of the dual-core Pentium D), the Core 2 Extreme, the Core i7 and the Core i9.

Contrary to popular belief, however, the Socket 478 versions of the Pentium 4 Extreme Edition CPUs such as the Gallatin-based Pentium 4 Extreme Edition for Socket 478 all have a locked multiplier, meaning that they are not overclockable unless the front-side bus speeds are increased (which runs the potential risks of erratic behaviors such as reliability and stability issues). Only the Socket 775/LGA 775 versions of the Pentium 4 Extreme Edition, as well as the Pentium Extreme Edition (Smithfield) and Engineering Sample CPUs have unlocked multipliers.

Prescott
On February 1, 2004, Intel introduced a new core codenamed Prescott. The core used the 90 nm process for the first time, which one analyst described as "a major reworking of the Pentium 4's microarchitecture." Despite this overhaul, the performance gains were inconsistent. Some programs benefited from Prescott's doubled cache and SSE3 instructions, whereas others were harmed by its longer pipeline. The Prescott's microarchitecture allowed slightly higher clock speeds, but not nearly as high as Intel had anticipated. The fastest mass-produced Prescott-based Pentium 4s were clocked at 3.8 GHz. While Northwood ultimately achieved clock speeds 70% higher than Willamette, Prescott only scaled 12% beyond Northwood. Prescott's inability to achieve greater clock speeds was attributed to the very high power consumption and heat output of the processor. This led to the processor receiving the nickname "PresHot" on forums. In fact, Prescott's power and heat characteristics were only slightly higher than those of Northwood of the same speed and nearly equal to the Gallatin-based Extreme Editions, but since those processors had already been operating near the limits of what was considered thermally acceptable, this still posed a major issue.

The release of Prescott also coincided with the launch of LGA 775 and the BTX form factor, which were also criticized. Tests showed that a given Pentium 4 made for LGA 775 consumed more power and produced more heat than the exact same chip in a socket 478 package. The BTX form factor, meanwhile, showed signs of having been designed for the sole purpose of managing the Prescott's heat output at the expense of other components and concerns, such as blowing hot air from the CPU directly into the graphics card's heatsink/fan. These magnified the perception of Prescott as an excessively hot chip.

The Prescott Pentium 4 contains 125 million transistors and has a die area of 112 mm2. It was fabricated in a 90 nm process with seven levels of copper interconnect. The process has features such as strained silicon transistors and low-κ carbon-doped silicon oxide (CDO) dielectric, which is also known as organosilicate glass (OSG). The Prescott was first fabricated at the D1C development fab and was later moved to F11X production fab.

Originally, Intel released two Prescott lines on Socket 478: the E-series, with an 800 MT/s FSB and Hyper-Threading support, and the low-end A-series, with a 533 MT/s FSB and Hyper-Threading disabled. LGA 775 Prescott CPUs use a rating system, labeling them as the 5xx series (Celeron Ds are the 3xx series, while Pentium Ms are the 7xx series). The LGA 775 version of the E-series uses model numbers 5x0 (520–560), and the LGA 775 version of the A-series uses model numbers 5x5 and 5x9 (505–519). The fastest, the 570J and 571, is clocked at 3.8 GHz. Plans to mass-produce a 4 GHz Pentium 4 were cancelled by Intel in favor of dual core processors, although some European retailers claimed to be selling a Pentium 4 580, clocked at 4 GHz. The E-series Prescott, as well as the low-end 517 and 524, incorporates Hyper-Threading in order to speed up some processes that use multithreaded software, such as video editing.

The Prescott microarchitecture was designed to support Intel 64, Intel's implementation of the AMD-developed x86-64 64-bit extensions to the x86 architecture, but the initial models shipped with their 64-bit capability disabled. Intel stated that it did not intend to release 64-bit CPUs in retail channels, instead releasing the 64-bit capable F-series to OEMs only. However, they were later made available to the general public as the 5x1 series. A number of low-end Intel 64-enabled Prescotts, with 533 MHz FSB speed, were also released.

The E0 stepping of the Prescott series introduced the XD bit feature. This technology, introduced to the x86 architecture by AMD as NX (No eXecute), can help prevent certain types of malicious code from exploiting a buffer overflow to get executed. Models supporting XD bit include the 5x0J and 5x1 series as well as the low-end 5x5J and 5x6.

The Prescott processors are the first to support SSE3, along with all Pentium D processors.

Prescott 2M (Extreme Edition)
Intel, by the first quarter of 2005, released a new Prescott core with 6x0 numbering, codenamed Prescott 2M. It is also sometimes known by the name of its Xeon derivative, Irwindale. It features Hyper-Threading, Intel 64, the XD bit, EIST (Enhanced Intel SpeedStep Technology), Thermal Monitor 2 (for processors at 3.6 GHz and above), and 2 MB of L2 cache. However, AnandTech found that this resulted in 17% higher cache latency compared to Prescott, which combined with the lack of consumer-targeted programs requiring more cache, largely negated the advantage that added cache introduced. Rather than being a targeted speed boost the double size cache was intended to provide the same space and hence performance for 64-bit mode operations, due to the doubled word size compared to 32-bit mode.

On November 14, 2005, Intel released Prescott 2M processors with VT (Virtualization Technology, codenamed Vanderpool) enabled. Intel only released two models of this Prescott 2M category: 662 and 672, running at 3.6 GHz and 3.8 GHz, respectively.

Cedar Mill
The final revision of the Pentium 4 was Cedar Mill, released on January 5, 2006. This was a die shrink of the Prescott-based 600 series core to 65 nm, with no real feature additions but significantly reduced power consumption. The Cedar Mill is closely linked to the Pentium D Presler revision, with each Presler CPU consisting of two Cedar Mill cores on the same chip package. Cedar Mill had a lower heat output than Prescott, with a TDP of 86 W. The D0 stepping in late 2006 reduced this to 65 watts. It has a 65 nm core and features the same 31-stage pipeline as Prescott, 800 MT/s FSB, Intel 64, Hyper-Threading, but no Virtualization Technology. As with Prescott 2M, Cedar Mill also has a 2 MB L2 cache.

Intel initially announced four VT-x enabled Cedar Mill processors with model numbers 633 to 663, but these were later cancelled and replaced by models 631 to 661 without VT-x, the extra 1 added to the model number distinguishing them from the 90 nm Prescott cores operating at the same frequencies. Cedar Mill processors ranged in frequency from 3.0 to 3.6 GHz, down from the 3.8 GHz maximum of the Prescott-based 670 and 672. Overclockers managed to exceed 8 GHz with these processors using liquid nitrogen cooling.

The name "Cedar Mill" refers to Cedar Mill, Oregon, an unincorporated community near Intel's Hillsboro, Oregon facilities.

Successor
In March 2003, the Pentium 4 M, the mobile version of the Pentium 4, was discontinued after suffering from heat and power consumption problems and was replaced by the Pentium M. The Pentium M was part of the Intel Centrino platform-marketing brand.

In May 2005, Intel released dual-core processors under the Pentium D and Pentium Extreme Edition brands. These came under the code names Smithfield and Presler for the 90 nm and 65 nm parts respectively.

The original successor to the Pentium 4 was (codenamed) Tejas, which was scheduled for an early-mid-2005 release. However, it was cancelled a few months after the release of Prescott due to extremely high TDPs (a 2.8 GHz Tejas emitted 150 W of heat, compared to around 80 W for a Northwood of the same speed, and 100 W for a comparably clocked Prescott) and development on the NetBurst microarchitecture as a whole ceased, with the exception of the dual-core Pentium D, Pentium Extreme Edition and the Cedar Mill-based Pentium 4 HT.

The real successor to the Pentium 4 brand is the Pentium Dual-Core brand, released in 2006. The first chips implementing it (in 65 nm) were released in January 2007 with the Yonah mobile processors and are based on the Enhanced Pentium M architecture, in June 3, 2007 with the Allendale (and later Conroe) desktop processors and in late 2007 with the Merom mobile processors, with the underlying microarchitecture being the Core microarchitecture.

title: Pentium 4


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Pentium II

The Pentium II brand refers to Intel's sixth-generation microarchitecture ("P6") and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors (27.4 million in the case of the mobile Dixon with 256 KB on-die L2 cache), the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pro's.

In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based Celeron line of processors for low-end computers and the Pentium II Xeon line for servers and workstations. The Celeron was characterized by a reduced or omitted (in some cases present but disabled) on-die full-speed L2 cache and a 66 MT/s FSB. The Xeon was characterized by a range of full-speed L2 cache (from 512 KB to 2048 KB), a 100 MT/s FSB, a different physical interface (Slot 2), and support for symmetric multiprocessing.

In February 1999, the Pentium II was replaced by the nearly identical Pentium III, which only added the then-new SSE instruction set. However, the older family would continue to be produced until June 2001 for desktop units, September 2001 for mobile units, and the end of 2003 for embedded devices.

Overview
The Pentium II microprocessor was largely based upon the microarchitecture of its predecessor, the Pentium Pro, but with some significant improvements.

Unlike previous Pentium and Pentium Pro processors, the Pentium II CPU was packaged in a slot-based module rather than a CPU socket. The processor and associated components were carried on a daughterboard similar to a typical expansion board within a plastic cartridge. A fixed or removable heatsink was carried on one side, sometimes using its own fan.

This larger package was a compromise allowing Intel to separate the secondary cache from the processor while still keeping it on a closely coupled back-side bus. The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. However, its associativity was increased to 16-way (compared to 4-way on the Pentium Pro) and its size was always 512 KB, twice of the smallest option of 256 KB on the Pentium Pro. Off-package cache solved the Pentium Pro's low yield issues, allowing Intel to introduce the Pentium II at a mainstream price level.

Intel improved 16-bit code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap, by adding segment register caches. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The issues with partial registers was also addressed by adding an internal flag to skip pipeline flushes whenever possible. To compensate for the slower L2 cache, the Pentium II featured 32 KB of L1 cache, double that of the Pentium Pro, as well as 4 write buffers (vs. 2 on the Pentium Pro); these can also be used by either pipeline, instead of each one being fixed to one pipeline. The Pentium II was also the first P6-based CPU to implement the Intel MMX integer SIMD instruction set which had already been introduced on the Pentium MMX.

The Pentium II was a more consumer-oriented version of the Pentium Pro. It was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as Windows 9x, and multimedia applications. The slower and cheaper L2 cache's performance penalty was mitigated by the doubled L1 cache and architectural improvements for legacy code. General processor performance was increased while costs were cut.

All Klamath and some early Deschutes Pentium IIs use a combined L2 cache controller / tag RAM chip that only allows for 512 MB to be cached; while more RAM could be installed in theory, this would result in very slow performance. While this limit was practically irrelevant for the average home user at the time, it was a concern for some workstation or server users. Presumably, Intel put this limitation deliberately in place to distinguish the Pentium II from the more upmarket Pentium Pro line, which has a full 4 GB cacheable area. The '82459AD' revision of the chip on some 333 MHz and all 350 MHz and faster Pentium IIs lifted this restriction and also offered a full 4 GB cacheable area.

Klamath
The original Klamath Pentium II microprocessor (Intel product code 80522) ran at 233, 266, and 300 MHz and was produced in a 0.35 μm process. The 300 MHz version, however, only became available in large quantities later in 1997. These CPUs had a 66 MHz front-side bus and were initially used on motherboards equipped with the aging Intel 440FX Natoma chipset designed for the Pentium Pro. Pentium II-based systems using the Intel 440LX Balboa chipset widely popularized SDRAM (which was to replace EDO RAM and was already introduced with 430VX), and the AGP graphics bus.

On July 14, 1997, Intel announced a version of the Pentium II Klamath with 2× 72-bit ECC L2 cache for entry-level servers, as opposed to the 2× 64-bit non-ECC L2 cache on regular models. The extra bits give it error-correction capability built into hardware, without impacting performance. The variant can be determined through the CPU part number.

In Intel's "Family/Model/Stepping" scheme, Klamath CPUs are family 6, model 3.

Deschutes
The Deschutes core Pentium II (80523), which debuted at 333 MHz in January 1998, was produced with a 0.25 μm process and has a significantly lower power draw. The die size is 113 mm2. The 333 MHz variant was the final Pentium II CPU that used the older 66 MT/s front-side bus; all subsequent Deschutes-core models used a 100 MT/s FSB. Later in 1998, Pentium IIs running at 266, 300, 350, 400, and 450 MHz were also released. The Deschutes core introduced FXSAVE and FXRSTOR instructions for fast FPU context save and restore. Towards the end of its design life, Deschutes chips capable of 500 MHz within Intel cooling and design specifications were produced. However, these were not marketed. Rather than destroy already multiplier-locked units, those Deschutes units that had been tested and locked with a multiplier of 5 were sold as being 333 MHz. This was accomplished by disabling the 100 MHz bus option. Overclockers, upon learning of this, purchased the units in question and ran them well over 500 MHz; most notably, when overclocking, the final batch of "333 MHz" CPUs were capable of speeds much higher than CPUs sold at 350, 400, or 450 MHz.

Concurrent with the release of Deschutes cores supporting a 100 MT/s front-side bus was Intel's release of the 440BX Seattle chipset and its derivatives, the 440MX, 450NX, and 440ZX chipsets. Replacing the aged 66 MHz FSB, which had been on the market since 1993, the 100 MHz FSB resulted in solid performance improvements for the Pentium II lineup. Pentium II chips starting with 350 MHz were released in both SECC and SECC2 form factors. Late Pentium IIs also marked the switch to flip-chip based packaging with direct heatsink contact to the die, as opposed to traditional bonding.

While Klamath features 4 cache chips and simulates dual-porting through interleaving (2x 64-bit) for a slight performance improvement on concurrent accesses, Deschutes only sports 2 cache chips and offers slightly lower L2 cache performance at the same clockspeed. Furthermore, Deschutes always features ECC-enabled L2 cache.

The Pentium II Xeon was a high-end version of Deschutes core intended for use on workstations and servers. Principally, it used a different type of slot (Slot 2), case, board design, and more expensive full-speed custom L2 cache, which was off-die. Versions were produced with 512 KB, 1 MB or 2 MB L2 caches by varying the number of 512 KB chips incorporated on the board.

In Intel's "Family/Model/Stepping" scheme, Deschutes CPUs are family 6, model 5 and have the part number 80523.

Pentium II OverDrive
In 1998, the 0.25 μm Deschutes core was utilized in the creation of the Pentium II Overdrive processor, which was aimed at allowing corporate Pentium Pro users to upgrade their aging servers. Combining the Deschutes core in a flip-chip package with a 512 KB full-speed L2 cache chip from the Pentium II Xeon into a Socket 8-compatible module resulted in a 300 or 333 MHz processor that could run on a 60 or 66 MHz front-side bus. This combination brought together some of the more attractive aspects of the Pentium II and the Pentium II Xeon: MMX support/improved 16-bit performance and full-speed L2 cache, respectively. The later "Dixon" mobile Pentium II would emulate this combination with 256 KB of full-speed cache.

In Intel's "Family/Model/Stepping" scheme, the Pentium II OverDrive CPU identifies itself as family 6, model 3, though this is misleading, as it is not based on the family 6/model 3 Klamath core. As mentioned in the Pentium II Processor update documentation from Intel, "although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core."

Tonga
The 0.25 μm Tonga core was the first mobile Pentium II and had all of the features of the desktop models.

In Intel's "Family/Model/Stepping" scheme, Tonga CPUs are family 6, model 5.

Dixon
Later, in 1999, the 0.25; 0.18 (400 MHz) μm Dixon core with 256 KB of on-die full speed cache was produced for the mobile market. Reviews showed that the Dixon core was the fastest type of Pentium II produced.

In Intel's "Family/Model/Stepping" scheme, Dixon CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the Mendocino Celeron processors.

Klamath (80522)

 * L1 cache: 16 + 16 KB (Data + Instructions)
 * L2 cache: 512 KB, as external chips on the CPU module clocked at half the CPU frequency.
 * Packaging: Slot 1 module
 * MMX
 * Front-side bus: 66 MT/s, GTL+
 * VCore: 2.8 V
 * Process: 350 nm CMOS
 * First release: May 7, 1997
 * Clockrate: 233, 266, 300 MHz

Deschutes (80523)

 * L1 cache: 16 + 16 KB (Data + Instructions)
 * L2 cache: 512 KB, as external chips on the CPU module clocked at half the CPU frequency.
 * Packaging: Slot 1 module
 * MMX
 * Front-side bus: 66, 100 MT/s, GTL+
 * VCore: 2.0 V
 * Process: 250 nm CMOS
 * First release: January 26, 1998
 * Clockrate: 266–450 MHz
 * 66 MT/s FSB : 266, 300, 333 MHz
 * 100 MT/s FSB: 350, 400, 450 MHz

Deschutes (Pentium II Overdrive)

 * L1 cache: 16 + 16 KB (Data + Instructions)
 * L2 cache: 512 KB external chip on CPU module running at 100% of CPU speed
 * Socket: Socket 8
 * Front-side bus: 60 or 66 MT/s, GTL+
 * VCore: 3.1–3.3 V (Has on-board voltage regulator)
 * Fabrication: 250 nm
 * Based on the Deschutes-generation Pentium II
 * First release: 1998
 * Supports MMX technology
 * The sSpec number SL2KE denotes a Pentium II Overdrive sold with an integrated heatsink/fan combination for Socket 8. [Note that the sSpec number SL2EA denotes a Pentium II Overdrive sold with an integrated heatsink but no fan for Slot 1.]

Tonga (80523)
Mobile Pentium II
 * L1 cache: 16 + 16 KB (Data + Instructions)
 * L2 cache: 512 KB, as external chips on the CPU module clocked at half the CPU frequency.
 * Package: MMC-1, MMC-2, Mini-Cartridge
 * MMX
 * Front-side bus: 66 MT/s, GTL+
 * VCore: 1.6 V
 * Process: 250 μm CMOS
 * First release: April 2, 1998
 * Clockrate: 233, 266, 300 MHz

Dixon (80524)
Mobile Pentium II PE ("Performance Enhanced")
 * L1 cache: 16 + 16 KB (Data + Instructions)
 * L2 cache: 256 KB, on-die, full speed.
 * Package: BGA1, MMC-1, MMC-2, μPGA1 PPGA-B615
 * MMX
 * Front-side bus: 66, 100 MT/s, GTL+
 * VCore: 1.5, 1.55, 1.6, 2.0 V
 * Process: 250, 180 (400 MHz) nm CMOS
 * First release: January 25, 1999
 * Clockrate: 266, 300, 333, 366, 400 MHz
 * Containing 27.4 million transistors
 * Die size (semiconductor chip) is 10.36 mm x 17.36 mm = 179.85 mm2

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: Pentium II


text:
Pentium III

The Pentium III (marketed as Intel Pentium III Processor and Pentium !!!, informally PIII or P3) brand refers to Intel's 32-bit x86 desktop and mobile CPUs based on the sixth-generation P6 microarchitecture introduced on February 28, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded processors. The most notable differences were the addition of the Streaming SIMD Extensions (SSE) instruction set (to accelerate floating point and parallel calculations), and the introduction of a controversial serial number embedded in the chip during manufacturing.

Even after the release of the Pentium 4 in late 2000, the Pentium III continued to be produced with new models introduced up until early 2003. They were then discontinued in April 2004 for desktop units and May 2007 for mobile units.

Processor cores
Similarly to the Pentium II it superseded, the Pentium III was also accompanied by the Celeron brand for lower-end versions, and the Xeon for high-end (server and workstation) derivatives. The Pentium III was eventually superseded by the Pentium 4, but its Tualatin core also served as the basis for the Pentium M CPUs, which used many ideas from the P6 microarchitecture. Subsequently, it was the Pentium M microarchitecture of Pentium M branded CPUs, and not the NetBurst found in Pentium 4 processors, that formed the basis for Intel's energy-efficient Core microarchitecture of CPUs branded Core 2, Pentium Dual-Core, Celeron (Core), and Xeon.

Katmai
The first Pentium III variant was the Katmai (Intel product code 80525). It was a further development of the Deschutes Pentium II. The Pentium III saw an increase of 2 million transistors over the Pentium II. The differences were the addition of execution units and SSE instruction support, and an improved L1 cache controller (the L2 cache controller was left unchanged, as it would be fully redesigned for Coppermine anyway), which were responsible for the minor performance improvements over the "Deschutes" Pentium IIs. It was first released at speeds of 450 and 500 MHz on February 28, 1999. Two more versions were released: 550 MHz on May 17, 1999 and 600 MHz on August 2, 1999. On September 27, 1999, Intel released the 533B and 600B running at 533 & 600 MHz respectively. The 'B' suffix indicated that it featured a 133 MT/s FSB, instead of the 100 MT/s FSB of prior models.

The Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache (which adds 25 million transistors), and has dimensions of 12.3 mm by 10.4 mm (128 mm2). It is fabricated in Intel's P856.5 process, a 250 nm complementary metal–oxide–semiconductor (CMOS) process with five levels of aluminum interconnect. The Katmai used the same slot-based design as the Pentium II but with the newer Slot 1 Single Edge Contact Cartridge (SECC) 2 that allowed direct CPU core contact with the heat sink. There have been some early models of the Pentium III with 450 and 500 MHz packaged in an older SECC cartridge intended for original equipment manufacturers (OEMs).

A notable stepping level for enthusiasts was SL35D. This version of Katmai was officially rated for 450 MHz, but often contained cache chips for the 600 MHz model and thus usually can run at 600 MHz.

Coppermine
The second version, codenamed Coppermine (Intel product code: 80526), was released on October 25, 1999 running at 500, 533, 550, 600, 650, 667, 700, and 733 MHz. From December 1999 to May 2000, Intel released Pentium IIIs running at speeds of 750, 800, 850, 866, 900, 933 and 1000 MHz (1 GHz). Both 100 MT/s FSB and 133 MT/s FSB models were made. For models that were already available with the same frequency, an "E" was appended to the model name to indicate cores using the new 180 nm fabrication process. An additional "B" was later appended to designate 133 MHz FSB models, resulting in an "EB" suffix. In overall performance, Coppermine had a small advantage over the Advanced Micro Devices (AMD) Athlons it was released against, which was reversed when AMD applied their own die shrink and added an on-die L2 cache to the Athlon. Athlon held the advantage in floating-point intensive code, while the Coppermine could perform better when SSE optimizations were used, but in practical terms there was little difference in how the two chips performed, clock-for-clock. However, AMD were able to clock the Athlon higher, reaching speeds of 1.2 GHz before the launch of the Pentium 4.

In performance, Coppermine arguably marked a bigger step than Katmai by introducing an on-chip L2 cache, which Intel names Advanced Transfer Cache (ATC). The ATC operates at the core clock rate and has a capacity of 256 KB, twice that of the on-chip cache formerly on Mendocino Celerons. It is eight-way set-associative and is accessed via a Double Quad Word Wide 256-bit bus, four times as wide as Katmai's. Further, latency was dropped to a quarter compared to Katmai. Another marketing term by Intel was Advanced System Buffering, which encompassed improvements to better take advantage of a 133 MT/s system bus. These include 6 fill buffers (vs. 4 on Katmai), 8 bus queue entries (vs. 4 on Katmai) and 4 write-back buffers (vs. 1 on Katmai). Under competitive pressure from the AMD Athlon, Intel reworked the internals, finally removing some well-known pipeline stalls. As a result, applications affected by the stalls ran faster on Coppermine by up to 30%. The Coppermine contained 29 million transistors and was fabricated in a 180 nm process.

The Coppermine was available in 370-pin FC-PGA or FC-PGA2 for use with Socket 370, or in SECC2 for Slot 1 (all speeds except 900 and 1100). FC-PGA and Slot 1 Coppermine CPUs have an exposed die, however most higher frequency SKUs starting with the 866 MHz model were also produced in FC-PGA2 variants that feature an integrated heat spreader (IHS). This in itself did not improve thermal conductivity, since it added another layer of metal and thermal paste between the die and the heatsink, but it greatly assisted in holding the heatsink flat against the die. Earlier Coppermines without the IHS made heatsink mounting challenging. If the heatsink was not situated flat against the die, heat transfer efficiency was greatly reduced. Some heatsink manufacturers began providing pads on their products, similar to what AMD did with the "Thunderbird" Athlon to ensure that the heatsink was mounted flatly. The enthusiast community went so far as to create shims to assist in maintaining a flat interface.

A 1.13 GHz version (S-Spec SL4HH) was released in mid-2000 but famously recalled after a collaboration between HardOCP and Tom's Hardware discovered various instabilities with the operation of the new CPU speed grade. The Coppermine core was unable to reliably reach the 1.13 GHz speed without various tweaks to the processor's microcode, effective cooling, higher voltage (1.75 V vs. 1.65 V), and specifically validated platforms. Intel only officially supported the processor on its own VC820 i820-based motherboard, but even this motherboard displayed instability in the independent tests of the hardware review sites. In benchmarks that were stable, performance was shown to be sub-par, with the 1.13 GHz CPU equalling a 1.0 GHz model. Tom's Hardware attributed this performance deficit to relaxed tuning of the CPU and motherboard to improve stability. Intel needed at least six months to resolve the problems using a new cD0 stepping and re-released 1.1 GHz and 1.13 GHz versions in 2001.

Microsoft's Xbox game console uses a variant of the Pentium III/Mobile Celeron family in a Micro-PGA2 form factor. The sSpec designator of the chips is SL5Sx, which makes it more similar to the Mobile Celeron Coppermine-128 processor. It shares with the Coppermine-128 Celeron its 128 KB L2 cache, and 180 nm process technology, but keeps the 8-way cache associativity from the Pentium III.

Although its codename could give the impression that it used copper interconnects, in reality, its interconnects were aluminium.

Coppermine T
This revision is an intermediate step between Coppermine and Tualatin, with support for lower-voltage system logic present on the latter but core power within previously defined voltage specs of the former so it could work in older system boards.

Intel used the latest FC-PGA2 Coppermines with the cD0 stepping and modified them so that they worked with low voltage system bus operation at 1.25 V AGTL as well as normal 1.5 V AGTL+ signal levels, and would auto detect differential or single-ended clocking. This modification made them compatible to the latest generation Socket 370 boards supporting Tualatin CPUs while maintaining compatibility with older Socket 370 boards. The Coppermine T also had two way symmetrical multiprocessing capabilities, but only in Tualatin boards.

They can be distinguished from Tualatin processors by their part numbers, which include the digits "80533", e.g. the 1133 MHz SL5QK P/N is RK80533PZ006256, while the 1000 MHz SL5QJ P/N is RK80533PZ001256.

Tualatin
The third revision, Tualatin (80530), was a trial for Intel's new 130 nm process. Tualatin-based Pentium IIIs were released during 2001 until early 2002 at speeds of 1.0, 1.13, 1.2, 1.26, 1.33 and 1.4 GHz. A basic shrink of Coppermine, no new features were added, except for added data prefetch logic similar to Pentium 4 and Athlon XP for potentially better use of the L2 cache, although its use compared to these newer CPUs is limited due to the relatively smaller FSB bandwidth (FSB was still kept at 133 MHz). Variants with 256 and 512 KB L2 cache were produced, the latter being dubbed Pentium III-S; this variant was mainly intended for low-power consumption servers and also exclusively featured SMP support within the Tualatin line.

Although the Socket 370 designation was kept, the use of 1.25 AGTL signaling in place of 1.5 V AGTL+ rendered prior motherboards incompatible. This confusion carried over to the chipset naming, where only the B-stepping of the i815 chipset was compatible with Tualatin processors. A new VRM guideline was also designed by Intel, version 8.5, which required finer voltage steps and debuted load line Vcore (in place of fixed voltage regardless of current on 8.4). Some motherboard manufacturers would mark the change with blue sockets (instead of white), and were often also backwards compatible with Coppermine CPUs.

The Tualatin also formed the basis for the highly popular Pentium III-M mobile processor, which became Intel's front-line mobile chip (the Pentium 4 drew significantly more power, and so was not well-suited for this role) for the next two years. The chip offered a good balance between power consumption and performance, thus finding a place in both performance notebooks and the "thin and light" category.

The Tualatin-based Pentium III performed well in some applications compared to the fastest Willamette-based Pentium 4, and even the Thunderbird-based Athlons. Despite this, its appeal was limited due to the aforementioned incompatibility with existing systems, and Intel's only officially supported chipset for Tualatins, the i815, could only handle 512 MB RAM as opposed to 1 GB of registered RAM with the older, incompatible 440BX chipset. However, the enthusiast community found a way to run Tualatins on then-ubiquitous BX chipset based boards, although it was often a non-trivial task and required some degree of technical skills.

Tualatin-based Pentium III CPUs can usually be visually distinguished from Coppermine-based processors by the metal integrated heat-spreader (IHS) fixed on top of the package. However, the last models of Coppermine Pentium IIIs also featured the IHS — the integrated heat spreader is actually what distinguishes the FC-PGA2 package from the FC-PGA — both are for Socket 370 motherboards.

Before the addition of the heat spreader, it was sometimes difficult to install a heatsink on a Pentium III. One had to be careful not to put force on the core at an angle because doing so would cause the edges and corners of the core to crack and could destroy the CPU. It was also sometimes difficult to achieve a flat mating of the CPU and heatsink surfaces, a factor of critical importance to good heat transfer. This became increasingly challenging with the Socket 370 CPUs, compared with their Slot 1 predecessors, because of the force required to mount a socket-based cooler and the narrower, 2-sided mounting mechanism (Slot 1 featured 4-point mounting). As such, and because the 130 nm Tualatin had an even smaller core surface area than the 180 nm Coppermine, Intel installed the metal heatspreader on Tualatin and all future desktop processors.

The Tualatin core was named after the Tualatin Valley and Tualatin River in Oregon, where Intel has large manufacturing and design facilities.

Pentium III's SSE implementation
Since Katmai was built in the same 250 nm process as Pentium II "Deschutes", it had to implement Streaming SIMD Extensions (SSE) using minimal silicon. To achieve this goal, Intel implemented the 128-bit architecture by double-cycling the existing 64-bit data paths and by merging the SIMD-FP multiplier unit with the x87 scalar FPU multiplier into a single unit. To utilize the existing 64-bit data paths, Katmai issues each SIMD-FP instruction as two μops. To compensate partially for implementing only half of SSE's architectural width, Katmai implements the SIMD-FP adder as a separate unit on the second dispatch port. This organization allows one half of a SIMD multiply and one half of an independent SIMD add to be issued together bringing the peak throughput back to four floating point operations per cycle — at least for code with an even distribution of multiplies and adds.

The issue was that Katmai's hardware-implementation contradicted the parallelism model implied by the SSE instruction-set. Programmers faced a code-scheduling dilemma: "Should the SSE-code be tuned for Katmai's limited execution resources, or should it be tuned for a future processor with more resources?" Katmai-specific SSE optimizations yielded the best possible performance from the Pentium III family but was suboptimal for Coppermine onwards as well as future Intel processors, such as the Pentium 4 and Core series.

Controversy about privacy issues
The Pentium III was the first x86 CPU to include a unique, retrievable, identification number, called Processor Serial Number (PSN). A Pentium III's PSN can be read by software through the CPUID instruction if this feature has not been disabled through the BIOS.

On November 29, 1999, the Science and Technology Options Assessment (STOA) Panel of the European Parliament, following their report on electronic surveillance techniques asked parliamentary committee members to consider legal measures that would "prevent these chips from being installed in the computers of European citizens."

Intel eventually removed the PSN feature from Tualatin-based Pentium IIIs, and the feature was absent in Pentium 4 and Pentium M.

A largely equivalent feature, the Protected Processor Identification Number (PPIN) was later added to x86 CPUs with little public notice, starting with Intel's Ivy Bridge architecture and compatible Zen 2 AMD CPUs. It is implemented as a set of model-specific registers and is useful for machine check exception handling.

Pentium III RNG (Random Number Generator)
A new feature was added to the Pentium III: a hardware-based random number generator. It has been described as "several oscillators combine their outputs and that odd waveform is sampled asynchronously."

title: Pentium III


text:
Triple Alliance (1882)

The Triple Alliance was a defensive military alliance between Germany, Austria-Hungary, and Italy. It was formed on 20 May 1882 and renewed periodically until it expired in 1915 during World War I. Germany and Austria-Hungary had been closely allied since 1879. Italy was looking for support against France shortly after it lost North African ambitions to the French. Each member promised mutual support in the event of an attack by any other great power. The treaty provided that Germany and Austria-Hungary were to assist Italy if it was attacked by France without provocation. In turn, Italy would assist Germany if attacked by France. In the event of a war between Austria-Hungary and Russia, Italy promised to remain neutral.

When the treaty was renewed in February 1887, Italy gained an empty promise of German support of Italian colonial ambitions in North Africa in return for Italy's continued friendship. Austria-Hungary had to be pressured by German chancellor Otto von Bismarck into accepting the principles of consultation and mutual agreement with Italy on any territorial changes initiated in the Balkans or on the coasts and islands of the Adriatic and Aegean seas. Italy and Austria-Hungary did not overcome their basic conflict of interest in that region despite the treaty. In 1891, attempts were made to join Britain to the Triple Alliance, which, though unsuccessful, were widely believed to have succeeded in Russian diplomatic circles.

Shortly after renewing the Alliance in June 1902, Italy secretly extended a similar guarantee to France. By a particular agreement, neither Austria-Hungary nor Italy would change the status quo in the Balkans without previous consultation.

On 18 October 1883 Carol I of Romania, through his Prime Minister Ion C. Brătianu, had also secretly pledged to support the Triple Alliance, but he later remained neutral in the First World War due to viewing Austria-Hungary as the aggressor. On 1 November 1902, five months after the Triple Alliance was renewed, Italy reached an understanding with France that each would remain neutral in the event of an attack on the other.

When Austria-Hungary found itself at war in August 1914 with the rival Triple Entente, Italy proclaimed its neutrality, considering Austria-Hungary the aggressor. Italy also defaulted on the obligation to consult and agree to compensations before changing the status quo in the Balkans, as agreed in 1912 renewal of the Triple Alliance. Following parallel negotiation with both Triple Alliance (which aimed to keep Italy neutral) and the Triple Entente (which aimed to make Italy enter the conflict), Italy sided with the Triple Entente and declared war on Austria-Hungary.

Germany
The man chiefly responsible for the Triple Alliance was Otto von Bismarck, the Chancellor of Germany. His primary goal was to preserve the status quo in Europe after he had unified Germany in 1871. He was particularly concerned about France finding allies to help it regain Alsace-Lorraine. By promising to aid Austria-Hungary and Italy in the event of attack, Bismarck sought to make them somewhat dependent on Germany and therefore unsympathetic to French adventures.

Austria-Hungary
By the late 1870s, Austrian territorial ambitions in both the Italian Peninsula and Central Europe had been thwarted by the rise of Italy and Germany as new powers. With the decline and the failed reforms of the Ottoman Empire, Slavic discontent in the occupied Balkans grew, which both Russia and Austria-Hungary saw as an opportunity to expand in the region. In 1876, Russia offered to partition the Balkans, but the Hungarian statesman Gyula Andrássy declined because Austria-Hungary was already a "saturated" state and could not cope with additional territories. The whole empire was thus drawn into a new style of diplomatic brinkmanship, which was first conceived of by Andrássy, centering on the province of Bosnia and Herzegovina, a predominantly-Slav area that was still under the control of the Ottoman Empire.

On the heels of the Great Balkan Crisis, Austro-Hungarian forces occupied Bosnia and Herzegovina in August 1878, and Austria-Hungary eventually annexed Bosnia and Herzegovina in October 1908 as a common holding under the control of the finance ministry, rather than attaching it to either Austria or Hungary. The occupation of Bosnia-Herzegovina was a step taken in response to Russian advances into Bessarabia. Unable to mediate between the Ottoman and the Russian Empires over the control of Serbia, Austria–Hungary declared neutrality when the conflict between the empires escalated into war. To counter Russian and French interests in Europe, an alliance was concluded with Germany in October 1879 and with Italy in May 1882.

Italy

Italy had several motives for joining the existing Austro-German alliance. The Italian government at that time was controlled by conservatives, who sympathized ideologically with the two monarchies. Also, Catholic Austria was a traditional protector of the Vatican, which Italy wanted to absorb. However, perhaps most importantly, Italy was seeking potential allies against France. The Kingdom of Italy, like most of the other European powers, wanted to set up colonies and build up an overseas empire. Although France had supported Italian unification, Italy's colonial ambitions in Africa quickly brought it into a rivalry with France. That was reflected in anger at the French seizure of Tunisia in 1881, the so-called Schiaffo di Tunisi by Italian press, which many Italians had seen as a potential colony. By joining the Alliance, Italy hoped to guarantee itself support in case of foreign aggression. The main alliance compelled any signatory country to support the other parties if two other countries attacked. Germany had won a war against France in 1870 and was a natural ally for Italy. Thus, Italy found itself coming to terms with its historical enemy, Austria-Hungary, against which Italy had fought three wars in the 34 years before the signing of the first treaty.

However, Italian public opinion remained unenthusiastic about their country's alignment with Austria-Hungary, a past enemy of Italian unification and whose Italian-populated districts in the Trentino and Istria were seen as occupied territories by Italian irredentists. In the years before World War I, many distinguished military analysts predicted that Italy would attack its supposed ally in the event of a large scale conflict. On its own hand, the Austro-Hungarian General Staff maintained at least from 1903 plans for a possible war against Rome. Mutual suspicions led to reinforcement of the frontier and speculation in the press about a war between the two countries into the first decade of the 20th century. As late as 1911, Count Franz Conrad von Hötzendorf, the chief of the Austro-Hungarian General Staff, was advocating a preemptive strike against Austria's supposed Italian ally. That prediction was strengthened by Italy's invasion and annexation of Libya, bringing it into conflict with the German-backed Ottoman Empire.

Romania
King Carol I of Romania was of German ancestry, which, combined with his wish to turn Romania into a centre of stability in Southeastern Europe and his fear of Russian expansion and the competing claims on Bessarabia, led to Romania secretly joining the Triple Alliance on 18 October 1883. Only the King and a handful of senior Romanian politicians knew about it. Romania and Austria-Hungary pledged to help each other in the event of a Russian, Serbian or Bulgarian attack. There were, however, several disputes between Romania and Hungary, the most notable being the status and community rights of Romanians in Transylvania. Romania eventually managed to achieve the status of regional power in the aftermath of the Balkan Wars and the 1913 Treaty of Bucharest, but less than a year later, World War I started, and Romania, after a period of neutrality in which both the Central Powers and the Allies tried persuading Romania to join their respective sides, eventually joined the Allies in 1916, after it had been promised significant Romanian-inhabited Hungarian lands. Romania's official reason for not siding with the Triple Alliance when the war started was the same as Italy's: The Triple Alliance was a defensive alliance, but Germany and Austria-Hungary had taken the offensive.

title: Triple Alliance (1882)


text:
Pentium Pro

The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel and introduced on November 1, 1995. It introduced the P6 microarchitecture (sometimes termed i686) and was originally intended to replace the original Pentium in a full range of applications. Later, it was reduced to a more narrow role as a server and high-end desktop processor. The Pentium Pro was also used in supercomputers, most notably ASCI Red, which used two Pentium Pro CPUs on each computing node and was the first computer to reach over one teraFLOPS in 1996, holding the number one spot in the TOP500 list from 1997 to 2000.

While the Pentium and Pentium MMX had 3.1 and 4.5 million transistors, respectively, the Pentium Pro contained 5.5 million transistors. It was capable of both dual- and quad-processor configurations and only came in one form factor, the relatively large rectangular Socket 8. The Pentium Pro was succeeded by the Pentium II Xeon in 1998.

Microarchitecture

The lead architect of Pentium Pro was Fred Pollack who was specialized in superscalarity and had also worked as the lead engineer of the Intel iAPX 432.

Summary
The Pentium Pro incorporated a new microarchitecture, different from the Pentium's P5 microarchitecture. It has a decoupled, 14-stage superpipelined architecture which used an instruction pool. The Pentium Pro (P6) implemented many radical architectural differences mirroring other contemporary x86 designs such as the NexGen Nx586 and Cyrix 6x86. The Pentium Pro pipeline had extra decode stages to dynamically translate IA-32 instructions into buffered micro-operation sequences which could then be analysed, reordered, and renamed in order to detect parallelizable operations that may be issued to more than one execution unit at once. The Pentium Pro thus featured out-of-order execution, including speculative execution via register renaming. It also had a wider 36-bit address bus, usable by Physical Address Extension (PAE), allowing it to access up to 64 GB of memory.

The Pentium Pro has an 8 KB instruction cache, from which up to 16 bytes are fetched on each cycle and sent to the instruction decoders. There are three instruction decoders. The decoders are unequal in ability: only one can decode any x86 instruction, while the other two can only decode simple x86 instructions. This restricts the Pentium Pro's ability to decode multiple instructions simultaneously, limiting superscalar execution. x86 instructions are decoded into 118-bit micro-operations (micro-ops). The micro-ops are reduced instruction set computer (RISC)-like; that is, they encode an operation, two sources, and a destination. The general decoder can generate up to four micro-ops per cycle, whereas the simple decoders can generate one micro-op each per cycle. Thus, x86 instructions that operate on the memory (e.g., add this register to this location in the memory) can only be processed by the general decoder, as this operation requires a minimum of three micro-ops. Likewise, the simple decoders are limited to instructions that can be translated into one micro-op. Instructions that require more micro-ops than four are translated with the assistance of a sequencer, which generates the required micro-ops over multiple clock cycles. The Pentium Pro was the first processor in the x86 family to support upgradeable microcode under BIOS and/or operating system (OS) control.

Micro-ops exit the re-order buffer (ROB) and enter a reserve station (RS), where they await dispatch to the execution units. In each clock cycle, up to five micro-ops can be dispatched to five execution units. The Pentium Pro has a total of six execution units: two integer units, one floating-point unit (FPU), a load unit, store address unit, and a store data unit. One of the integer units shares the same ports as the FPU, and therefore the Pentium Pro can only dispatch one integer micro-op and one floating-point micro-op, or two integer micro-ops per a cycle, in addition to micro-ops for the other three execution units. Of the two integer units, only the one that shares the path with the FPU on port 0 has the full complement of functions such as a barrel shifter, multiplier, divider, and support for LEA instructions. The second integer unit, which is connected to port 1, does not have these facilities and is limited to simple operations such as add, subtract, and the calculation of branch target addresses.

The FPU executes floating-point operations. Addition and multiplication are pipelined and have a latency of three and five cycles, respectively. Division and square-root are not pipelined and are executed in separate units that share the FPU's ports. Division and square root have a latency of 18-36 and 29-69 cycles, respectively. The smallest number is for single precision (32-bit) floating-point numbers and the largest for extended precision (80-bit) numbers. Division and square root can operate simultaneously with adds and multiplies, preventing them from executing only when the result has to be stored in the ROB.

After the microprocessor was released, a bug was discovered in the floating point unit, commonly called the "Pentium Pro and Pentium II FPU bug" and by Intel as the "flag erratum". The bug occurs under some circumstances during floating point-to-integer conversion when the floating point number will not fit into the smaller integer format, causing the FPU to deviate from its documented behaviour. The bug is considered to be minor and occurs under such special circumstances that very few, if any, software programs are affected.

The Pentium Pro P6 microarchitecture was used in one form or another by Intel for more than a decade. The pipeline would scale from its initial 150 MHz start, all the way up to 1.4 GHz with the "Tualatin" Pentium III. The design's various traits would continue after that in the derivative core called "Banias" in Pentium M and Intel Core (Yonah), which itself would evolve into the Core microarchitecture (Core 2 processor) in 2006 and onward.

Instruction set
The Pentium Pro (P6) introduced new instructions into the Intel range; the CMOVxx (‘conditional move’) instructions can move a value that is either the contents of a register or memory location into another register or not, according to some predicate logical condition xx on the flags register, xx being a flags predicate code as given in the condition for conditional jump instructions. So for example CMOVNE moves a specified value into a register or not depending on whether the NE (not-equal) condition is true in the flags register ie Z flag = 0. This allows the evaluation of if-then-else operations and for example the ? : operation in C. These instructions give a performance boost by allowing the avoidance of costly jump and branch instructions. In eg CMOVxx destreg1, source_operand2 the first operand is the destination register, the second the source register or memory location. The second operand unfortunately can not be an immediate (in-line constant) value and such a constant would have to be placed in a register first. The predicate code xx can take the full range of values as allowed in conditional branches.

A second development was the documentation of the UD2 illegal instruction. This op code is reserved and guaranteed to cause an illegal instruction exception on the P6 and all later processors. This allows developers to easily crash the current program in a future-proof fashion when a bug is detected by software.

Performance
Despite being advanced for the time, the Pentium Pro's out-of-order register renaming architecture had trouble running 16-bit code and mixed code (8-bit with 16-bit (8/16), or 16-bit with 32-bit (16/32), as using partial registers cause frequent pipeline flushing. Specific use of partial registers was then a common performance optimization, as it incurred no performance penalty on pre-P6 Intel processors; also, the dominant operating systems at the time of the Pentium Pro's release were 16-bit DOS, and mixed 16/32-bit Windows 3.1x and Windows 95 (although the latter requires a 32-bit 80386 CPU as a minimum, much of its code is still 16-bit for performance reasons, such as the 16-bit Windows USER dynamic link library, user.exe). This, along with the high cost of Pentium Pro systems, led to tepid sales among PC buyers at the time. To fully use the Pentium Pro's P6 microarchitecture, a fully 32-bit operating system is needed, such as Windows NT, Linux, Unix, or OS/2. The performance issues on legacy code were later partly mitigated by Intel with the Pentium II.

Compared to RISC microprocessors, the Pentium Pro, when introduced, slightly outperformed the fastest RISC microprocessors on integer performance when running the SPECint95 benchmark, but floating-point performance was significantly lower, half that of some RISC microprocessors. The Pentium Pro's integer performance lead disappeared rapidly, first overtaken by the MIPS Technologies R10000 in January 1996, and then by Digital Equipment Corporation's EV56 variant of the Alpha 21164.

Reviewers quickly noted the very slow writes to video memory as the weak spot of the P6 platform, with performance here being as low as 10% of an identically clocked Pentium system in benchmarks such as VIDSPEED. Methods to circumvent this included setting VESA drawing to system memory instead of video memory in games such as Quake, and later on utilities such as FASTVID emerged, which could double performance in certain games by enabling the write combining features of the CPU. Memory type range registers (MTRRs) are set automatically by Windows video drivers starting from 1997, and from there the improved cache/memory subsystem and FPU performance caused it to outclass the Pentium clock-for-clock in the emerging 3D games of the mid–to–late 1990s, particularly when using Windows NT 4.0. However, its lack of MMX implementation reduces performance in multimedia applications that made use of those instructions.

Caching
Likely Pentium Pro's most noticeable addition was its on-package L2 cache, which ranged from 256 KB at introduction to 1 MB in 1997. At the time, manufacturing technology did not feasibly allow a large L2 cache to be integrated into the processor core. Intel instead placed the L2 die(s) separately in the package which still allowed it to run at the same clock speed as the CPU core. Additionally, unlike most motherboard-based cache schemes that shared the main system bus with the CPU, the Pentium Pro's cache had its own back-side bus (called dual independent bus by Intel). Because of this, the CPU could read main memory and cache concurrently, greatly reducing a traditional bottleneck. The cache was also "non-blocking", meaning that the processor could issue more than one cache request at a time (up to 4), reducing cache-miss penalties. (This is an example of MLP, Memory Level Parallelism.) These properties combined to produce an L2 cache that was immensely faster than the motherboard-based caches of older processors. This cache alone gave the CPU an advantage in input/output performance over older x86 CPUs. In multiprocessor configurations, Pentium Pro's integrated cache skyrocketed performance in comparison to architectures which had each CPU sharing a central cache.

However, this far faster L2 cache did come with some complications. The Pentium Pro's "on-package cache" arrangement was unique. The processor and the cache were on separate dies in the same package and connected closely by a full-speed bus. The two or three dies had to be bonded together early in the production process, before testing was possible. This meant that a single, tiny flaw in either die made it necessary to discard the entire assembly, which was one of the reasons for the Pentium Pro's relatively low production yield and high cost. All versions of the chip were expensive, those with 1024 KB being particularly so, since it required two 512 KB cache dies as well as the processor die.

Available models
Pentium Pro clock speeds were 150, 166, 180 or 200 MHz with a 60 or 66 MHz external bus clock. A prototype 133 MHz Pentium Pro was developed in its earliest stages of development but was never released. Some users chose to overclock their Pentium Pro chips, with the 200 MHz version often being run at 233 MHz, the 180 MHz version often being run at 200 MHz, and the 150 MHz version often being run at 166 MHz. The chip was popular in symmetric multiprocessing configurations, with dual and quad SMP server and workstation setups being commonplace.

Intel skipped out on providing a mobile version of the original Pentium Pro due to power draw and heat concerns. At least one vendor sold a portable computer with a Pentium Pro (Imperial Computer's 6200TLP).

In Intel's "Family/Model/Stepping" scheme, the Pentium Pro is family 6, model 1, and its Intel Product code is 80521.

Fabrication
The process used to fabricate the Pentium Pro processor die and its separate cache memory die changed, leading to a combination of processes used in the same package:
 * The 133 MHz Pentium Pro prototype processor die was fabricated in a 0.6 μm BiCMOS process.
 * The 150 MHz Pentium Pro processor die was fabricated in a 0.50 μm BiCMOS process.
 * The 166, 180, and 200 MHz Pentium Pro processor die was fabricated in a 0.35 μm BiCMOS process.
 * The 256 KB L2 cache die was fabricated in a 0.50 μm BiCMOS process.
 * The 512 and 1024 KB L2 cache die was fabricated in a 0.35 μm BiCMOS process.

Packaging
The Pentium Pro (up to 512 KB cache) is packaged in a ceramic multi-chip module (MCM). The MCM contains two underside cavities in which the microprocessor die and its companion cache die reside. The dies are bonded to a heat slug, whose exposed top helps the heat from the dies to be transferred more directly to cooling apparatus such as a heat sink. The dies are connected to the package using conventional wire bonding. The cavities are capped with a ceramic plate.

The Pentium Pro with 1 MB of cache uses a plastic MCM. Instead of two cavities, there is only one, in which the three dies reside, bonded to the package instead of a heat slug. The cavities are filled in with epoxy.

The MCM has 387 pins, of which approximately half are arranged in a pin grid array (PGA) and half in an interstitial pin grid array (IPGA). The packaging was designed for Socket 8.

Upgrade paths
In 1998, the 300/333 MHz Pentium II OverDrive processor for Socket 8 was released. Based on some of the technology used in the Deschutes Pentium II Xeon, it featured double L1 and 512 KB of full-speed L2 cache with MMX capabilities, and was produced by Intel as a drop-in upgrade option for owners of Pentium Pro systems. However, it only supported two-way glueless multiprocessing, not four-way or higher, which did not make it a usable upgrade for quad-processor systems. These specially packaged Pentium II OverDrive processors were also used to upgrade the ASCI Red supercomputer in 1999. This makes the ASCI Red supercomputer, the first computer to reach the one teraFLOPS performance mark with dual Pentium Pro processors in 1996, to now become the first computer overall to exceed the two teraFLOPS performance mark with the upgrade to dual Pentium II OverDrive processors in 1999. ASCI Red continued to use dual Pentium II OverDrive processors for the remainder of its lifespan before being decommissioned in 2006.

As Slot 1 motherboards became prevalent, several manufacturers released slotket (or slocket) adapters, such as the Tyan M2020, Asus C-P6S1, Tekram P6SL1, and the Abit KP6. These sockets allowed Pentium Pro processors to be used with Slot 1 motherboards. However, only a few number of chipsets supported these slotkets, and so did not see widespread use. The Intel 440FX chipset explicitly supported both Pentium Pro and Pentium II processors, however the Intel 440BX and later Slot 1 chipsets did not explicitly support the Pentium Pro. Slotkets eventually saw renewed popularity in the form of Socket 370 to Slot 1 adapters, when Intel introduced Socket 370 Celeron and Pentium III processors in the late 1990s. These form of slotkets allowed for lower costs for computer builders, especially with dual processor machines, and gave Slot 1 motherboards the ability to continue receiving CPU upgrades beyond the then-currently available Slot 1 CPUs.

Pentium Pro

 * L1 cache: 8, 8 KB (data, instructions)
 * L2 cache: 256, 512 KB (one die) or 1024 KB (two 512 KB dies) in a multi-chip module clocked at CPU-speed
 * Socket: Socket 8
 * Front-side bus: 60 and 66 MHz
 * VCore: 3.1–3.3 V
 * Fabrication: 0.50 μm or 0.35 BiCMOS
 * Clockrate: 150, 166, 180, 200 MHz, (capable of 233 MHz on some motherboards)
 * First release: November 1995

Pentium II Overdrive

 * L1 cache: 16, 16 KB (data + instructions)
 * L2 cache: 512 KB external chip on CPU module clocked at CPU-speed
 * Socket: Socket 8
 * Multiplier: Locked at 5×
 * Front-side bus: 60 and 66 MHz
 * VCore: 3.1–3.3 V (has on-board voltage regulator)
 * Fabrication: 0.25 μm
 * Clockrate: Based on the Deschutes-generation Pentium II
 * First release: 1997
 * Supports MMX technology

Bus and multiprocessor capabilities
The Pentium Pro used GTL+ signaling in its front-side bus. The Pentium Pro could be used by itself on up to four-way designs. Eight-way Pentium Pro computers were also built, but these used multiple buses.

The design of the Pentium Pro bus was influenced by Futurebus, the Intel iAPX 432 bus, and elements of the Intel i960 bus. Futurebus had been intended as an advanced bus to replace VMEbus used with the Motorola 68000 from the late 1970s, but it stagnated in standardization committee for more than a decade if you count all the twists and turns. Intel's iAPX 432 initiative was also a commercial failure, but in the process they did learn how to build a split-transaction bus to support a cacheless multiprocessor system. The i960 had further developed the split-transaction iAPX 432 bus to include a cache coherency protocol, ending up with a feature set highly reminiscent of the original Futurebus ambitions.

The lead architect of i960 was superscalarity specialist Fred Pollack who was also the lead engineer of the Intel iAPX 432 and the lead architect of the i686 chip, the Pentium Pro. He was no doubt intimately familiar with all this history. The Pentium Pro was designed to include the 4-way SMP split-transaction cache-coherent bus as a mandatory feature of every chip produced. This also served to deny competition access to the socket to produce cloned processors.

While the Pentium Pro was not successful as a machine for the masses due to poor 16-bit support for Windows 95 and many other 16-bit and mixed 16/32-bit operating systems, it did see significant successes in the file server space due to its advanced, integrated bus design, introducing many advanced features that had formerly only been available in the pricey workstation segment into the commodity marketplace.

Pentium Pro/6th generation competitors

 * AMD K5 and K6
 * Cyrix 6x86 and MII
 * IDT WinChip
 * Intel P5 Pentium, co-existed with Pentium Pro for several years

title: Pentium Pro