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Macromedia

Macromedia, Inc., was an American graphics, multimedia, and web development software company (1992–2005) headquartered in San Francisco, California, that made products such as Flash and Dreamweaver. It was purchased by its rival Adobe Systems on December 3, 2005.

History
Macromedia originated with the 1992 merger of Authorware Inc. (makers of Authorware) and MacroMind–Paracomp (makers of Macromind Director).

Director, an interactive multimedia-authoring tool used to make presentations, animations, CD-ROMs and information kiosks, served as Macromedia's flagship product until the mid-1990s. Authorware was Macromedia's principal product in the interactive learning market. As the Internet moved from a university research medium to a commercial network, Macromedia began working to web-enable its existing tools and develop new products like Dreamweaver. Macromedia created Shockwave, a Director-viewer plugin for web browsers. The first multimedia playback in Netscape's browser was a Director plug-in. Macromedia licensed Sun's Java Programming Language in October 1995. By 2002, Macromedia had produced more than 20 products and had 30 offices in 13 countries.

Acquisitions
In January 1995, Macromedia acquired Altsys Corporation after Adobe Systems announced a merger with Altsys' business partner, the Aldus Corporation. Altsys was the developer of the vector-drawing program FreeHand, which had been licensed by Aldus for marketing and sales. Because of the similarities with Adobe Illustrator, the Federal Trade Commission issued a complaint in October 1994 ordering the divestiture of FreeHand back to Altsys. With Macromedia's acquisition of Altsys, it received FreeHand thus expanding its product line of multimedia graphics software to include illustration and design graphics software. FreeHand's vector graphics rendering engine and other software components within the program would prove useful to Macromedia in the development of Fireworks.

In March 1996, Macromedia acquired iBand Software, makers of the Backstage HTML authoring tool and application server. Macromedia developed a new HTML-authoring tool, Dreamweaver, around portions of the Backstage codebase and released the first version in 1997. At the time, most professional web authors preferred to code HTML by hand using text editors because they wanted full control over the source. Dreamweaver addressed this with its "Roundtrip HTML" feature, which attempted to preserve the fidelity of hand-edited source code during visual edits, allowing users to work back and forth between visual and code editing. Over the next few years Dreamweaver became widely adopted among professional web authors, though many still preferred to hand-code, and Microsoft FrontPage remained a strong competitor among amateur and business users.

Macromedia acquired FutureWave Software, makers of FutureSplash Animator, in November 1996. FutureSplash Animator was an animation tool originally developed for pen-based computing devices. Because of the small size of the FutureSplash Viewer application, it was particularly suited for download over the Internet, where most users, at the time, had low-bandwidth connections. Macromedia renamed Splash to Macromedia Flash, and following the lead of Netscape, distributed the Flash Player as a free browser plugin in order to quickly gain market share. As of 2005, more computers worldwide had the Flash Player installed than any other Web media format, including Java, QuickTime, RealNetworks, and Windows Media Player. As Flash matured, Macromedia's focus shifted from marketing it as a graphics and media tool to promoting it as a Web application platform, adding scripting and data access capabilities to the player while attempting to retain its small footprint.

In December 1999, Macromedia acquired traffic analysis software company Andromedia Corporation. Web development company Allaire was acquired in 2001 and Macromedia added several popular servers and Web developments tools to its portfolio, including ColdFusion, a web application server based on the CFML language, JRun, a Java EE application server, and HomeSite, an HTML code editor that was also bundled with Dreamweaver.

In 2003, Macromedia acquired the web conferencing company Presedia and continued to develop and enhance their Flash-based online collaboration and presentation product offering under the brand Breeze. Later that year, Macromedia also acquired help authoring software company eHelp Corporation, whose products included RoboHelp and RoboDemo (now Adobe Captivate).

Purchase
On April 18, 2005, Adobe Systems announced an agreement to acquire Macromedia in a stock swap valued at approximately $3.4 billion on the last trading day before the announcement. The acquisition took place on December 3, 2005, and Adobe integrated the company's operations, networks, and customer care organizations shortly thereafter.

Lawsuits
On August 22, 1997, stockholders filed a class-action lawsuit in the California Superior Court in San Francisco, accusing Macromedia of misleading stockholders on the company's product success and financial health. A similar suit had been filed a month earlier. The class-action suit was dismissed by a federal judge on May 19, 1998.

On August 10, 2000, Adobe claimed that Macromedia violated two of its patents on tabbed palettes. Macromedia countered with a claim that Adobe infringed on Macromedia's patents for a draw-based editor for Web pages and a hierarchical structure editor for Web sites. In July 2002, Adobe and Macromedia reached an agreement that settled all claims in this series of patent suits. Eventually, Adobe acquired Macromedia 3 years later.

Leadership

 * 1992: Bud Colligan became co-founder and CEO of Macromedia, a position he held until 1997; he served as board chairman 1992–1998.
 * 1994: Altsys Corp and CEO James Von Ehr became a Macromedia vice-president, a position he held until 1997.
 * 1996: Robert K. Burgess was hired as President of Macromedia, and became CEO in 1997, a position he held until 2005; he served as Board Chairman 1998–2005, a position he held when the company was acquired by Adobe.
 * 1997: Betsey Nelson became Chief Financial Officer, a position she held until Macromedia was acquired by Adobe.
 * 2004: Stephen Elop became Chief Operating Officer.
 * 2005: Stephen Elop had been CEO for three months when Macromedia announced it would be acquired by Adobe.

Part of Adobe

 * Adobe Captivate (formerly RoboDemo)
 * Adobe ColdFusion
 * Adobe Connect (formerly Macromedia Breeze, Adobe Acrobat Connect Pro)
 * Adobe Dreamweaver
 * Adobe Flash
 * Adobe Animate (formerly Flash Professional)
 * Adobe Flash Media Server
 * Adobe RoboHelp

Discontinued products

 * Adobe Authorware
 * Adobe Contribute
 * Adobe Director
 * Adobe Fireworks
 * Adobe Flash
 * Adobe Flash Lite
 * Adobe Flash Player
 * Adobe Flex
 * Macromedia Flex Data Services (rebranded as Adobe LiveCycle Data Services)
 * Adobe JRun
 * Adobe Shockwave
 * Macromedia Aria
 * Macromedia Action!
 * Macromedia Aftershock
 * Macromedia Backstage (became the basis to Macromedia Dreamweaver)
 * Macromedia Central (replaced by AIR)
 * Macromedia Deck
 * Macromedia Drumbeat (replaced by Dreamweaver UltraDev)
 * Macromedia Extreme 3D
 * Macromedia FlashPaper
 * Macromedia Fontographer (sold to FontLab and became Fontographer)
 * Macromedia FreeHand
 * Macromedia Generator
 * Macromedia HomeSite
 * Macromedia Kawa
 * Macromedia KeyGrip/Macromedia Final Cut (sold to Apple and became Final Cut Pro)
 * Macromedia Likeminds
 * Macromodel
 * Macromedia MediaMaker
 * Macromedia Projector
 * Macromedia RoboInfo
 * Macromedia Shockmachine
 * Macromedia Sitespring
 * Macromedia SoundEdit 16
 * Macromedia Spectra
 * Macromedia Web Publishing System
 * Macromedia xRes

title: Macromedia


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Error function

In mathematics, the error function (also called the Gauss error function), often denoted by $erf$, is a function defined as: $$\operatorname{erf} z = \frac{2}{\sqrt\pi}\int_0^z e^{-t^2}\,\mathrm dt.$$

Some authors define $$\operatorname{erf}$$ without the factor of $$2/\sqrt{\pi}$$. This nonelementary integral is a sigmoid function that occurs often in probability, statistics, and partial differential equations. In many of these applications, the function argument is a real number. If the function argument is real, then the function value is also real.

In statistics, for non-negative values of $x$, the error function has the following interpretation: for a random variable $Y$ that is normally distributed with mean 0 and standard deviation $1⁄√2$, $erf x$ is the probability that $Y$ falls in the range $[−x, x]$.

Two closely related functions are the complementary error function ($erfc$) defined as $$\operatorname{erfc} z = 1 - \operatorname{erf} z,$$ and the imaginary error function ($erfi$) defined as $$\operatorname{erfi} z = -i\operatorname{erf} iz,$$ where $i$ is the imaginary unit.

Name
The name "error function" and its abbreviation $erf$ were proposed by J. W. L. Glaisher in 1871 on account of its connection with "the theory of Probability, and notably the theory of Errors." The error function complement was also discussed by Glaisher in a separate publication in the same year. For the "law of facility" of errors whose density is given by $$f(x) = \left(\frac{c}{\pi}\right)^{1/2} e^{-c x^2}$$ (the normal distribution), Glaisher calculates the probability of an error lying between $p$ and $q$ as: $$\left(\frac{c}{\pi}\right)^\frac{1}{2} \int_p^qe^{-cx^2}\,\mathrm dx = \tfrac{1}{2}\left(\operatorname{erf} \left(q\sqrt{c}\right) -\operatorname{erf} \left(p\sqrt{c}\right)\right).$$

Applications
When the results of a series of measurements are described by a normal distribution with standard deviation $σ$ and expected value 0, then $erf (a⁄σ √2)$ is the probability that the error of a single measurement lies between $−a$ and $+a$, for positive $a$. This is useful, for example, in determining the bit error rate of a digital communication system.

The error and complementary error functions occur, for example, in solutions of the heat equation when boundary conditions are given by the Heaviside step function.

The error function and its approximations can be used to estimate results that hold with high probability or with low probability. Given a random variable $X ~ Norm[μ,σ]$ (a normal distribution with mean $μ$ and standard deviation $σ$) and a constant $L > μ$, it can be shown via integration by substitution: $$\begin{align} \Pr[X\leq L] &= \frac{1}{2} + \frac{1}{2} \operatorname{erf}\frac{L-\mu}{\sqrt{2}\sigma} \\ &\approx A \exp \left(-B \left(\frac{L-\mu}{\sigma}\right)^2\right) \end{align}$$

where $A$ and $B$ are certain numeric constants. If $L$ is sufficiently far from the mean, specifically $μ − L ≥ σ√ln k$, then:

$$\Pr[X\leq L] \leq A \exp (-B \ln{k}) = \frac{A}{k^B}$$

so the probability goes to 0 as $k → ∞$.

The probability for $X$ being in the interval $[L_{a}, L_{b}]$ can be derived as $$\begin{align} \Pr[L_a\leq X \leq L_b] &= \int_{L_a}^{L_b} \frac{1}{\sqrt{2\pi}\sigma} \exp\left(-\frac{(x-\mu)^2}{2\sigma^2}\right) \,\mathrm dx \\ &= \frac{1}{2}\left(\operatorname{erf}\frac{L_b-\mu}{\sqrt{2}\sigma} - \operatorname{erf}\frac{L_a-\mu}{\sqrt{2}\sigma}\right).\end{align}$$

Properties
The property $exp(−z^{2})$ means that the error function is an odd function. This directly results from the fact that the integrand $erf z$ is an even function (the antiderivative of an even function which is zero at the origin is an odd function and vice versa).

Since the error function is an entire function which takes real numbers to real numbers, for any complex number $z$: $$\operatorname{erf} \overline{z} = \overline{\operatorname{erf} z} $$ where $erf (−z) = −erf z$ is the complex conjugate of z.

The integrand $e^{−t^{2}}|undefined$ and $\overline{z}$ are shown in the complex $z$-plane in the figures at right with domain coloring.

The error function at $f = exp(−z^{2})$ is exactly 1 (see Gaussian integral). At the real axis, $f = erf z$ approaches unity at $+∞$ and −1 at $erf z$. At the imaginary axis, it tends to $z → +∞$.

Taylor series
The error function is an entire function; it has no singularities (except that at infinity) and its Taylor expansion always converges, but is famously known "[...] for its bad convergence if $z → −∞$."

The defining integral cannot be evaluated in closed form in terms of elementary functions (see Liouville's theorem), but by expanding the integrand $±i∞$ into its Maclaurin series and integrating term by term, one obtains the error function's Maclaurin series as: $$\begin{align} \operatorname{erf} z &= \frac{2}{\sqrt\pi}\sum_{n=0}^\infty\frac{(-1)^n z^{2n+1}}{n! (2n+1)} \\[6pt] &= \frac{2}{\sqrt\pi} \left(z-\frac{z^3}{3}+\frac{z^5}{10}-\frac{z^7}{42}+\frac{z^9}{216}-\cdots\right) \end{align}$$ which holds for every complex number $z$. The denominator terms are sequence A007680 in the OEIS.

For iterative calculation of the above series, the following alternative formulation may be useful: $$\begin{align} \operatorname{erf} z &= \frac{2}{\sqrt\pi}\sum_{n=0}^\infty\left(z \prod_{k=1}^n {\frac{-(2k-1) z^2}{k (2k+1)}}\right) \\[6pt] &= \frac{2}{\sqrt\pi} \sum_{n=0}^\infty \frac{z}{2n+1} \prod_{k=1}^n \frac{-z^2}{k} \end{align}$$ because $erf(−z) = −erf z$ expresses the multiplier to turn the $k$th term into the $x > 1$th term (considering $z$ as the first term).

The imaginary error function has a very similar Maclaurin series, which is: $$\begin{align} \operatorname{erfi} z &= \frac{2}{\sqrt\pi}\sum_{n=0}^\infty\frac{z^{2n+1}}{n! (2n+1)} \\[6pt] &=\frac{2}{\sqrt\pi} \left(z+\frac{z^3}{3}+\frac{z^5}{10}+\frac{z^7}{42}+\frac{z^9}{216}+\cdots\right) \end{align}$$ which holds for every complex number $z$.

Derivative and integral
The derivative of the error function follows immediately from its definition: $$\frac{\mathrm d}{\mathrm dz}\operatorname{erf} z =\frac{2}{\sqrt\pi} e^{-z^2}.$$ From this, the derivative of the imaginary error function is also immediate: $$\frac{d}{dz}\operatorname{erfi} z =\frac{2}{\sqrt\pi} e^{z^2}.$$ An antiderivative of the error function, obtainable by integration by parts, is $$z\operatorname{erf}z + \frac{e^{-z^2}}{\sqrt\pi}.$$ An antiderivative of the imaginary error function, also obtainable by integration by parts, is $$z\operatorname{erfi}z - \frac{e^{z^2}}{\sqrt\pi}.$$ Higher order derivatives are given by $$\operatorname{erf}^{(k)}z = \frac{2 (-1)^{k-1}}{\sqrt\pi} \mathit{H}_{k-1}(z) e^{-z^2} = \frac{2}{\sqrt\pi} \frac{\mathrm d^{k-1}}{\mathrm dz^{k-1}} \left(e^{-z^2}\right),\qquad k=1, 2, \dots$$ where $H$ are the physicists' Hermite polynomials.

Bürmann series
An expansion, which converges more rapidly for all real values of $x$ than a Taylor expansion, is obtained by using Hans Heinrich Bürmann's theorem: $$\begin{align} \operatorname{erf} x &= \frac{2}{\sqrt\pi} \sgn x \cdot \sqrt{1-e^{-x^2}} \left( 1-\frac{1}{12} \left (1-e^{-x^2} \right ) -\frac{7}{480} \left (1-e^{-x^2} \right )^2 -\frac{5}{896} \left (1-e^{-x^2} \right )^3-\frac{787}{276 480} \left (1-e^{-x^2} \right )^4 - \cdots \right) \\[10pt] &= \frac{2}{\sqrt\pi} \sgn x \cdot \sqrt{1-e^{-x^2}} \left(\frac{\sqrt\pi}{2} + \sum_{k=1}^\infty c_k e^{-kx^2} \right). \end{align}$$ where $e^{−z^{2}}|undefined$ is the sign function. By keeping only the first two coefficients and choosing $−(2k − 1)z^{2}⁄k(2k + 1)$ and $(k + 1)$, the resulting approximation shows its largest relative error at $sgn$, where it is less than 0.0036127: $$\operatorname{erf} x \approx \frac{2}{\sqrt\pi}\sgn x \cdot \sqrt{1-e^{-x^2}} \left(\frac{\sqrt{\pi}}{2} + \frac{31}{200}e^{-x^2}-\frac{341}{8000} e^{-2x^2}\right). $$

Inverse functions

Given a complex number $z$, there is not a unique complex number $w$ satisfying $c_{1} = 31⁄200$, so a true inverse function would be multivalued. However, for $c_{2} = −341⁄8000$, there is a unique real number denoted $x = ±1.3796$ satisfying $$\operatorname{erf}\left(\operatorname{erf}^{-1} x\right) = x.$$

The inverse error function is usually defined with domain $(−1,1)$, and it is restricted to this domain in many computer algebra systems. However, it can be extended to the disk $erf w = z$ of the complex plane, using the Maclaurin series $$\operatorname{erf}^{-1} z=\sum_{k=0}^\infty\frac{c_k}{2k+1}\left (\frac{\sqrt\pi}{2}z\right )^{2k+1},$$ where $−1 < x < 1$ and $$\begin{align} c_k & =\sum_{m=0}^{k-1}\frac{c_m c_{k-1-m}}{(m+1)(2m+1)} \\[1ex] &= \left\{1,1,\frac{7}{6},\frac{127}{90},\frac{4369}{2520},\frac{34807}{16200},\ldots\right\}. \end{align}$$

So we have the series expansion (common factors have been canceled from numerators and denominators): $$\operatorname{erf}^{-1} z = \frac{\sqrt{\pi}}{2} \left (z + \frac{\pi}{12}z^3 + \frac{7\pi^2}{480}z^5 + \frac{127\pi^3}{40320}z^7 + \frac{4369\pi^4}{5806080} z^9 + \frac{34807\pi^5}{182476800}z^{11} + \cdots\right ).$$ (After cancellation the numerator/denominator fractions are entries / in the OEIS; without cancellation the numerator terms are given in entry .) The error function's value at $erf^{−1} x$ is equal to $|z| < 1$.

For $c_{0} = 1$, we have $±∞$.

The inverse complementary error function is defined as $$\operatorname{erfc}^{-1}(1-z) = \operatorname{erf}^{-1} z.$$ For real $x$, there is a unique real number $±1$ satisfying $|z| < 1$. The inverse imaginary error function is defined as $erf(erf^{−1} z) = z$.

For any real x, Newton's method can be used to compute $erfi^{−1} x$, and for $erfi(erfi^{−1} x) = x$, the following Maclaurin series converges: $$\operatorname{erfi}^{-1} z =\sum_{k=0}^\infty\frac{(-1)^k c_k}{2k+1} \left( \frac{\sqrt\pi}{2} z \right)^{2k+1},$$ where $erfi^{−1} x$ is defined as above.

Asymptotic expansion
A useful asymptotic expansion of the complementary error function (and therefore also of the error function) for large real $x$ is $$\begin{align} \operatorname{erfc} x &= \frac{e^{-x^2}}{x\sqrt{\pi}}\left(1 + \sum_{n=1}^\infty (-1)^n \frac{1\cdot3\cdot5\cdots(2n - 1)}{\left(2x^2\right)^n}\right) \\[6pt] &= \frac{e^{-x^2}}{x\sqrt{\pi}}\sum_{n=0}^\infty (-1)^n \frac{(2n - 1)!!}{\left(2x^2\right)^n}, \end{align}$$ where $erfi^{−1} x$ is the double factorial of $−1 ≤ x ≤ 1$, which is the product of all odd numbers up to $c_{k}$. This series diverges for every finite $x$, and its meaning as asymptotic expansion is that for any integer $(2n − 1)!!$ one has $$\operatorname{erfc} x = \frac{e^{-x^2}}{x\sqrt{\pi}}\sum_{n=0}^{N-1} (-1)^n \frac{(2n - 1)!!}{\left(2x^2\right)^n} + R_N(x)$$ where the remainder is $$R_N(x) := \frac{(-1)^N}{\sqrt\pi} 2^{1 - 2N}\frac{(2N)!}{N!}\int_x^\infty t^{-2N}e^{-t^2}\,\mathrm dt,$$ which follows easily by induction, writing $$e^{-t^2} = -(2t)^{-1}\left(e^{-t^2}\right)'$$ and integrating by parts.

The asymptotic behavior of the remainder term, in Landau notation, is $$R_N(x) = O\left(x^{- (1 + 2N)} e^{-x^2}\right)$$ as $(2n − 1)$. This can be found by $$R_N(x) \propto \int_x^\infty t^{-2N}e^{-t^2}\,\mathrm dt = e^{-x^2} \int_0^\infty (t+x)^{-2N}e^{-t^2-2tx}\,\mathrm dt\leq e^{-x^2} \int_0^\infty x^{-2N} e^{-2tx}\,\mathrm dt \propto x^{-(1+2N)}e^{-x^2}.$$ For large enough values of $x$, only the first few terms of this asymptotic expansion are needed to obtain a good approximation of $(2n − 1)$ (while for not too large values of $x$, the above Taylor expansion at 0 provides a very fast convergence).

Continued fraction expansion
A continued fraction expansion of the complementary error function is: $$\operatorname{erfc} z = \frac{z}{\sqrt\pi}e^{-z^2} \cfrac{1}{z^2+ \cfrac{a_1}{1+\cfrac{a_2}{z^2+ \cfrac{a_3}{1+\dotsb}}}},\qquad a_m = \frac{m}{2}.$$

Integral of error function with Gaussian density function
$$\int_{-\infty}^{\infty} \operatorname{erf} \left(ax+b \right) \frac{1}{\sqrt{2\pi \sigma^2}}\exp\left(-\frac{(x-\mu)^2}{2 \sigma^2} \right)\,\mathrm dx= \operatorname{erf} \frac{a\mu+b}{\sqrt{1+2 a^2 \sigma^2}}, \qquad a,b,\mu,\sigma \in \R$$ which appears related to Ng and Geller, formula 13 in section 4.3 with a change of variables.

Factorial series
The inverse factorial series: $$\begin{align} \operatorname{erfc} z &= \frac{e^{-z^2}}{\sqrt{\pi}\,z} \sum_{n=0}^\infty \frac{\left(-1\right)^n Q_n}{{\left(z^2+1\right)}^{\bar{n}}} \\[1ex] &= \frac{e^{-z^2}}{\sqrt{\pi}\,z} \left[1 -\frac{1}{2}\frac{1}{(z^2+1)} + \frac{1}{4}\frac{1}{\left(z^2+1\right) \left(z^2+2\right)} - \cdots \right] \end{align}$$ converges for $N ≥ 1$. Here $$\begin{align} Q_n &\overset{\text{def}}{{}={}} \frac{1}{\Gamma{\left(\frac{1}{2}\right)}} \int_0^\infty \tau(\tau-1)\cdots(\tau-n+1)\tau^{-\frac{1}{2}} e^{-\tau} \,d\tau \\[1ex] &= \sum_{k=0}^n \left(\frac{1}{2}\right)^{\bar{k}} s(n,k), \end{align}$$ $x → ∞$ denotes the rising factorial, and $erfc x$ denotes a signed Stirling number of the first kind. There also exists a representation by an infinite sum containing the double factorial: $$\operatorname{erf} z = \frac{2}{\sqrt\pi} \sum_{n=0}^\infty \frac{(-2)^n(2n-1)!!}{(2n+1)!}z^{2n+1}$$

Approximation with elementary functions
  Abramowitz and Stegun give several approximations of varying accuracy (equations 7.1.25–28). This allows one to choose the fastest approximation suitable for a given application. In order of increasing accuracy, they are: $$\operatorname{erf} x \approx 1 - \frac{1}{\left(1 + a_1x + a_2x^2 + a_3x^3 + a_4x^4\right)^4}, \qquad x \geq 0$$ (maximum error: $0.001$)

where $Re(z^{2}) > 0$, $z^{\overline{n}}|undefined$, $s(n,k)$, $a_{1} = 0.278393$

$$\operatorname{erf} x \approx 1 - \left(a_1t + a_2t^2 + a_3t^3\right)e^{-x^2},\quad t=\frac{1}{1 + px}, \qquad x \geq 0$$ (maximum error: $0$)

where $a_{2} = 0.230389$, $a_{3} = 0.000972$, $a_{4} = 0.078108$, $p = 0.47047$

$$\operatorname{erf} x \approx 1 - \frac{1}{\left(1 + a_1x + a_2x^2 + \cdots + a_6x^6\right)^{16}}, \qquad x \geq 0$$ (maximum error: $0$)

where $a_{1} = 0.3480242$, $a_{2} = −0.0958798$, $a_{3} = 0.7478556$, $a_{1} = 0.0705230784$, $a_{2} = 0.0422820123$, $a_{3} = 0.0092705272$

$$\operatorname{erf} x \approx 1 - \left(a_1t + a_2t^2 + \cdots + a_5t^5\right)e^{-x^2},\quad t = \frac{1}{1 + px}$$ (maximum error: $0$)

where $a_{4} = 0.0001520143$, $a_{5} = 0.0002765672$, $a_{6} = 0.0000430638$, $p = 0.3275911$, $a_{1} = 0.254829592$, $a_{2} = −0.284496736$

All of these approximations are valid for $a_{3} = 1.421413741$. To use these approximations for negative $x$, use the fact that $a_{4} = −1.453152027$ is an odd function, so $a_{5} = 1.061405429$.

 Exponential bounds and a pure exponential approximation for the complementary error function are given by $$\begin{align} \operatorname{erfc} x &\leq \frac{1}{2}e^{-2 x^2} + \frac{1}{2}e^{- x^2} \leq e^{-x^2}, &\quad x &> 0 \\[1.5ex] \operatorname{erfc} x &\approx \frac{1}{6}e^{-x^2} + \frac{1}{2}e^{-\frac{4}{3} x^2}, &\quad x &> 0. \end{align}$$

 The above have been generalized to sums of $N$ exponentials with increasing accuracy in terms of $N$ so that $x ≥ 0$ can be accurately approximated or bounded by $erf x$, where $$\tilde{Q}(x) = \sum_{n=1}^N a_n e^{-b_n x^2}.$$ In particular, there is a systematic methodology to solve the numerical coefficients $erf x = −erf(−x)$ that yield a minimax approximation or bound for the closely related Q-function: $erfc x$, $2Q̃(√2x)$, or ${(a_{n},b_{n})}N n = 1$ for $Q(x) ≈ Q̃(x)$. The coefficients $Q(x) ≤ Q̃(x)$ for many variations of the exponential approximations and bounds up to $Q(x) ≥ Q̃(x)$ have been released to open access as a comprehensive dataset.

 A tight approximation of the complementary error function for $x ≥ 0$ is given by Karagiannidis & Lioumpas (2007) who showed for the appropriate choice of parameters ${(a_{n},b_{n})}N n = 1$ that $$\operatorname{erfc} x \approx \frac{\left(1 - e^{-Ax}\right)e^{-x^2}}{B\sqrt{\pi} x}.$$ They determined $N = 25$, which gave a good approximation for all $x ∈ [0,∞)$. Alternative coefficients are also available for tailoring accuracy for a specific application or transforming the expression into a tight bound.

 A single-term lower bound is

where the parameter $β$ can be picked to minimize error on the desired interval of approximation.

 Another approximation is given by Sergei Winitzki using his "global Padé approximations": $$\operatorname{erf} x \approx \sgn x \cdot \sqrt{1 - \exp\left(-x^2\frac{\frac{4}{\pi} + ax^2}{1 + ax^2}\right)}$$ where $$a = \frac{8(\pi - 3)}{3\pi(4 - \pi)} \approx 0.140012.$$ This is designed to be very accurate in a neighborhood of 0 and a neighborhood of infinity, and the relative error is less than 0.00035 for all real $x$. Using the alternate value ${A,B}$ reduces the maximum relative error to about 0.00013.

This approximation can be inverted to obtain an approximation for the inverse error function: $$\operatorname{erf}^{-1}x \approx \sgn x \cdot \sqrt{\sqrt{\left(\frac{2}{\pi a} + \frac{\ln\left(1 - x^2\right)}{2}\right)^2 - \frac{\ln\left(1 - x^2\right)}{a}} -\left(\frac{2}{\pi a} + \frac{\ln\left(1 - x^2\right)}{2}\right)}.$$

 An approximation with a maximal error of $0$ for any real argument is: $$\operatorname{erf} x = \begin{cases} 1-\tau & x\ge 0\\ \tau-1 & x < 0 \end{cases}$$ with $$\begin{align} \tau &= t\cdot\exp\left(-x^2-1.26551223+1.00002368 t+0.37409196 t^2+0.09678418 t^3 -0.18628806 t^4\right.\\ &\left. \qquad\qquad\qquad +0.27886807 t^5-1.13520398 t^6+1.48851587 t^7 -0.82215223 t^8+0.17087277 t^9\right) \end{align}$$ and $$t = \frac{1}{1 + \frac{1}{2}|x|}.$$

An approximation of $$\operatorname{erfc}$$ with a maximum relative error less than $$2^{-53}$$ $$\left(\approx 1.1 \times 10^{-16}\right)$$ in absolute value is: for $x\ge 0$, $$\begin{aligned} \operatorname{erfc} \left(x\right) & = \left(\frac{0.56418958354775629}{x+2.06955023132914151}\right) \left(\frac{x^2+2.71078540045147805 x+5.80755613130301624}{x^2+3.47954057099518960 x+12.06166887286239555}\right) \\ & \left(\frac{x^2+3.47469513777439592 x+12.07402036406381411}{x^2+3.72068443960225092 x+8.44319781003968454}\right) \left(\frac{x^2+4.00561509202259545 x+9.30596659485887898}{x^2+3.90225704029924078 x+6.36161630953880464}\right) \\ & \left(\frac{x^2+5.16722705817812584 x+9.12661617673673262}{x^2+4.03296893109262491 x+5.13578530585681539}\right) \left(\frac{x^2+5.95908795446633271 x+9.19435612886969243}{x^2+4.11240942957450885 x+4.48640329523408675}\right) e^{-x^2} \\ \end{aligned}$$ and for $$x<0$$ $$\operatorname{erfc} \left(x\right) = 2 - \operatorname{erfc} \left(-x\right)$$ </li> <li> A simple approximation for real-valued arguments could be done through Hyperbolic functions: $$\operatorname{erf} \left(x\right) \approx z(x) = \tanh\left(\frac{2}{\sqrt{\pi}}\left(x+\frac{11}{123}x^3\right)\right)$$ which keeps the absolute difference $\left </li> </ul>

Complementary error function
The complementary error function, denoted ${A,B} = {1.98,1.135}$, is defined as $$\begin{align} \operatorname{erfc} x & = 1-\operatorname{erf} x \\[5pt] & = \frac{2}{\sqrt\pi} \int_x^\infty e^{-t^2}\,\mathrm dt \\[5pt] & = e^{-x^2} \operatorname{erfcx} x, \end{align} $$ which also defines $x ≥ 0$, the scaled complementary error function (which can be used instead of $a ≈ 0.147$ to avoid arithmetic underflow ). Another form of $x$ for $erf x$ is known as Craig's formula, after its discoverer: $$\operatorname{erfc} (x \mid x\ge 0) = \frac{2}{\pi} \int_0^\frac{\pi}{2} \exp \left( - \frac{x^2}{\sin^2 \theta} \right) \, \mathrm d\theta.$$ This expression is valid only for positive values of $0$, but it can be used in conjunction with $1 − erf x$ to obtain $erfc$ for negative values. This form is advantageous in that the range of integration is fixed and finite. An extension of this expression for the $erfcx$ of the sum of two non-negative variables is as follows: $$\operatorname{erfc} (x+y \mid x,y\ge 0) = \frac{2}{\pi} \int_0^\frac{\pi}{2} \exp \left( - \frac{x^2}{\sin^2 \theta} - \frac{y^2}{\cos^2 \theta} \right) \,\mathrm d\theta.$$

Imaginary error function
The imaginary error function, denoted $erfc$, is defined as $$\begin{align} \operatorname{erfi} x & = -i\operatorname{erf} ix \\[5pt] & = \frac{2}{\sqrt\pi} \int_0^x e^{t^2}\,\mathrm dt \\[5pt] & = \frac{2}{\sqrt\pi} e^{x^2} D(x), \end{align} $$ where $erfc x$ is the Dawson function (which can be used instead of $x ≥ 0$ to avoid arithmetic overflow ).

Despite the name "imaginary error function", $erfc x = 2 − erfc(−x)$ is real when $1$ is real.

When the error function is evaluated for arbitrary complex arguments $0.023$, the resulting complex error function is usually discussed in scaled form as the Faddeeva function: $$w(z) = e^{-z^2}\operatorname{erfc}(-iz) = \operatorname{erfcx}(-iz).$$

Cumulative distribution function
The error function is essentially identical to the standard normal cumulative distribution function, denoted $erfc(x)$, also named $erfc$ by some software languages, as they differ only by scaling and translation. Indeed, $$\begin{align} \Phi(x) &= \frac{1}{\sqrt{2\pi}} \int_{-\infty}^x e^\tfrac{-t^2}{2}\,\mathrm dt\\[6pt] &= \frac{1}{2} \left(1+\operatorname{erf}\frac{x}{\sqrt 2}\right)\\[6pt] &= \frac{1}{2} \operatorname{erfc}\left(-\frac{x}{\sqrt 2}\right) \end{align}$$ or rearranged for $erfi$ and $D(x)$: $$\begin{align} \operatorname{erf}(x) &= 2 \Phi \left ( x \sqrt{2} \right ) - 1 \\[6pt] \operatorname{erfc}(x) &= 2 \Phi \left ( - x \sqrt{2} \right ) \\ &=2\left(1-\Phi \left ( x \sqrt{2} \right)\right). \end{align}$$

Consequently, the error function is also closely related to the Q-function, which is the tail probability of the standard normal distribution. The Q-function can be expressed in terms of the error function as $$\begin{align} Q(x) &= \frac{1}{2} - \frac{1}{2} \operatorname{erf} \frac{x}{\sqrt 2}\\ &= \frac{1}{2}\operatorname{erfc}\frac{x}{\sqrt 2}. \end{align}$$

The inverse of $erfi$ is known as the normal quantile function, or probit function and may be expressed in terms of the inverse error function as $$\operatorname{probit}(p) = \Phi^{-1}(p) = \sqrt{2}\operatorname{erf}^{-1}(2p-1) = -\sqrt{2}\operatorname{erfc}^{-1}(2p).$$

The standard normal cdf is used more often in probability and statistics, and the error function is used more often in other branches of mathematics.

The error function is a special case of the Mittag-Leffler function, and can also be expressed as a confluent hypergeometric function (Kummer's function): $$\operatorname{erf} x = \frac{2x}{\sqrt\pi} M\left(\tfrac{1}{2},\tfrac{3}{2},-x^2\right).$$

It has a simple expression in terms of the Fresnel integral.

In terms of the regularized gamma function $0.977$ and the incomplete gamma function, $$\operatorname{erf} x = \sgn x \cdot P\left(\tfrac{1}{2}, x^2\right) = \frac{\sgn x}{\sqrt\pi} \gamma{\left(\tfrac{1}{2}, x^2\right)}.$$$erfi x$ is the sign function.

Generalized error functions
Some authors discuss the more general functions: $$E_n(x) = \frac{n!}{\sqrt\pi} \int_0^x e^{-t^n}\,\mathrm dt = \frac{n!}{\sqrt\pi} \sum_{p=0}^\infty (-1)^p \frac{x^{np+1}}{(np+1)p!}. $$ Notable cases are:
 * $Φ$ is a straight line through the origin: $norm(x)$
 * $erf$ is the error function, $erfc$.

After division by $Φ$, all the $sgn x$ for odd $0.045$ look similar (but not identical) to each other. Similarly, the $E_{n}(x)$ for even $0.955$ look similar (but not identical) to each other after a simple division by $E_{1}(x) = 1 − e^{−x}⁄√π$. All generalised error functions for $E_{2}(x) = erf(x)$ look similar on the positive $0.068$ side of the graph.

These generalised functions can equivalently be expressed for $E_{3}(x)$ using the gamma function and incomplete gamma function: $$E_n(x) = \frac{1}{\sqrt\pi}\Gamma(n)\left(\Gamma\left(\frac{1}{n}\right) - \Gamma\left(\frac{1}{n}, x^n\right)\right), \qquad x>0.$$

Therefore, we can define the error function in terms of the incomplete gamma function: $$\operatorname{erf} x = 1 - \frac{1}{\sqrt\pi}\Gamma\left(\tfrac{1}{2}, x^2\right).$$

Iterated integrals of the complementary error function
The iterated integrals of the complementary error function are defined by $$\begin{align} i^n\!\operatorname{erfc} z &= \int_z^\infty i^{n-1}\!\operatorname{erfc} \zeta\,\mathrm  d\zeta \\[6pt] i^0\!\operatorname{erfc} z &= \operatorname{erfc} z \\ i^1\!\operatorname{erfc} z &= \operatorname{ierfc} z = \frac{1}{\sqrt\pi} e^{-z^2} - z \operatorname{erfc} z \\ i^2\!\operatorname{erfc} z &= \tfrac{1}{4} \left( \operatorname{erfc} z -2 z \operatorname{ierfc} z \right) \\ \end{align}$$

The general recurrence formula is $$2 n \cdot i^n\!\operatorname{erfc} z = i^{n-2}\!\operatorname{erfc} z -2 z \cdot i^{n-1}\!\operatorname{erfc} z$$

They have the power series $$i^n\!\operatorname{erfc} z =\sum_{j=0}^\infty \frac{(-z)^j}{2^{n-j}j! \,\Gamma \left( 1 + \frac{n-j}{2}\right)},$$ from which follow the symmetry properties $$i^{2m}\!\operatorname{erfc} (-z) =-i^{2m}\!\operatorname{erfc} z +\sum_{q=0}^m \frac{z^{2q}}{2^{2(m-q)-1}(2q)! (m-q)!}$$ and $$i^{2m+1}\!\operatorname{erfc}(-z) =i^{2m+1}\!\operatorname{erfc} z +\sum_{q=0}^m \frac{z^{2q+1}}{2^{2(m-q)-1}(2q+1)! (m-q)!}. $$

As real function of a real argument

 * In POSIX-compliant operating systems, the header  shall declare and the mathematical library   shall provide the functions   and   (double precision) as well as their single precision and extended precision counterparts ,   and  ,.
 * The GNU Scientific Library provides,  ,  , and scaled error functions.

As complex function of a complex argument

 * , numeric C library for complex error functions, provides the complex functions,  ,   and the real functions  ,   with approximately 13–14 digits precision, based on the Faddeeva function as implemented in the MIT Faddeeva Package
 * The function for complex arguments can be computed numerically as follows: $$\operatorname{erf}\left(a+bi\right) = \frac{2}{\sqrt{\pi}}e^{b^2} \int_0^a e^{-x^2} \cos\left(2bx\right) \, dx + i\left( \operatorname{erfi}\left(b\right) - \frac{2}{\sqrt{\pi}} e^{b^2} \int_0^a e^{-x^2} \sin\left(2bx\right) \, dx \right)$$

Related functions

 * Gaussian integral, over the whole real line
 * Gaussian function, derivative
 * Dawson function, renormalized imaginary error function
 * Goodwin–Staton integral

In probability

 * Normal distribution
 * Normal cumulative distribution function, a scaled and shifted form of error function
 * Probit, the inverse or quantile function of the normal CDF
 * Q-function, the tail probability of the normal distribution
 * Standard score

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: Error function


text:
Memory management unit

A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit that examines all memory references on the memory bus, translating these requests, known as virtual memory addresses, into physical addresses in main memory.

In modern systems, programs generally have addresses that access the theoretical maximum memory of the computer architecture, 32 or 64 bits. The MMU maps the addresses from each program into separate areas in physical memory, which is generally much smaller than the theoretical maximum. This is possible because programs rarely use large amounts of memory at any one time.

Most modern operating systems (OS) work in concert with a MMU to provide virtual memory (VM) support. The MMU tracks memory use in fixed-size blocks known as pages, and if a program refers to a location in a page that is not in physical memory, the MMU will cause an interrupt to the operating system. The OS will then select a lesser-used block in memory, write it to backing storage such as a hard drive if it has been modified since it was read in, read the page from backing storage into that block, and set up the MMU to map the block to the originally requested page so the program can use it. This is known as demand paging.

Modern MMUs generally perform additional memory-related tasks as well. Memory protection blocks attempts by a program to access memory it has not previously requested, which prevents a misbehaving program from using up all memory or malicious code from reading data from another program. They also often manage a processor cache, which stores recently accessed data in a very fast memory and thus reduces the need to talk to the slower main memory. In some implementations, they are also responsible for bus arbitration, controlling access to the memory bus among the many parts of the computer that desire access.

Prior to VM systems becoming widespread in the 1990s, earlier MMU designs were more varied. Common among these was paged translation, which was similar to modern demand paging in that it used fixed-size blocks, but had a fixed-size list of pages that divided up memory; this meant that the block size was a function of the number of pages and the installed memory. Another common technique, found mostly on larger machines, was segmented translation, which allowed for variable-size blocks of memory that better mapped onto program requests. This was efficient but did not map as well onto virtual memory. Some early systems, especially 8-bit systems, used very simple MMUs to perform bank switching.

Overview

Modern MMUs typically divide the virtual address space (the range of addresses used by the processor) into pages, each having a size which is a power of 2, usually a few kilobytes, but they may be much larger. Programs reference memory using the natural address size of the machine, typically 32 or 64-bits in modern systems. The bottom bits of the address (the offset within a page) are left unchanged. The upper address bits are the virtual page numbers.

Most MMUs use an in-memory table of items called a page table, containing one page table entry (PTE) per virtual page, to map virtual page numbers to physical page numbers in main memory. Multi-level page tables are often used to reduce the size of the page table. An associative cache of PTEs is called a translation lookaside buffer (TLB) and is used to avoid the necessity of accessing the main memory every time a virtual address is mapped.

Other MMUs may have a private array of memory, registers, or static RAM that holds a set of mapping information.

The virtual page number may be directly used as an index into the page table or other mapping information, or it may be further divided, with bits at a given level used as an index into a table of lower-level tables into which bits at the next level down are used as an index, with two or more levels of indexing.

The physical page number is combined with the page offset to give the complete physical address.

A page table entry or other per-page information may also include information about whether the page has been written to (the dirty bit), when it was last used (the accessed bit, for a least recently used (LRU) page replacement algorithm), what kind of processes (user mode or supervisor mode) may read and write it, and whether it should be cached.

Sometimes, a page table entry or other per-page information prohibits access to a particular virtual page, perhaps because no physical random-access memory (RAM) has been allocated to that virtual page. In this case, the MMU signals a page fault to the CPU. The operating system (OS) then handles the situation, perhaps by trying to find a spare frame of RAM and set up the page map to map it to the requested virtual address. If no RAM is free, it may be necessary to choose an existing page (known as a victim), using some replacement algorithm, and save it to disk (a process called paging). With some MMUs, there can also be a shortage of PTEs, in which case the OS will have to free one for the new mapping.

The MMU may also generate illegal access error conditions or invalid page faults upon illegal or non-existing memory accesses, respectively, leading to segmentation fault or bus error conditions when handled by the operating system.

Benefits

In some cases, a page fault may indicate a software bug, which can be prevented by using memory protection as one of key benefits of an MMU: an operating system can use it to protect against errant programs by disallowing access to memory that a particular program should not have access to. Typically, an operating system assigns each program its own virtual address space.

A paged MMU also mitigates the problem of external fragmentation of memory. After blocks of memory have been allocated and freed, the free memory may become fragmented (discontinuous) so that the largest contiguous block of free memory may be much smaller than the total amount. With virtual memory, a contiguous range of virtual addresses can be mapped to several non-contiguous blocks of physical memory; this non-contiguous allocation is one of the benefits of paging.

However, paged mapping causes another problem, internal fragmentation. This occurs when a program requests a block of memory that does not cleanly map into a page, for instance, if a program requests a 1 KB buffer to perform file work. In this case, the request results in an entire page being set aside even though only 1 KB of the page will ever be used; if pages are larger than 1 KB, the remainder of the page is wasted. If many small allocations of this sort are made, memory can be used up even though much of it remains empty.

In some early microprocessor designs, memory management was performed by a separate integrated circuit such as the VLSI Technology VI475 (1986), the Motorola 68851 (1984) used with the Motorola 68020 CPU in the Macintosh II, or the Z8010 and Z8015 (1985) used with the Zilog Z8000 family of processors. Later microprocessors (such as the Motorola 68030 and the Zilog Z280) placed the MMU together with the CPU on the same integrated circuit, as did the Intel 80286 and later x86 microprocessors.

Older concepts
While this article concentrates on modern MMUs, commonly based on demand paging, early systems used base and bounds addressing that further developed into segmentation, or used a fixed set of blocks instead of loading them on demand. The difference between these two approaches is the size of the contiguous block of memory; paged systems break up main memory into a series of equal sized blocks, while segmented systems generally allow for variable sizes.

Segmented translation
Early memory management systems, often implemented in software, set aside a portion of memory to hold a series of mappings. These consisted of pairs of values, the base and limit, although many other terms have been used. When the operating system requested memory to load a program, or a program requested more memory to hold data from a file for instance, it would call the memory handling library. This examined the mappings to look for an area in main memory large enough to hold the request. If such a block was found, a new entry was entered into the table. From then on, when that program accessed memory, all of its addresses were offset by the base value. When the program is done with the memory it requested and releases, or the program exits, the entries associated with it are released.

This style of access, over time, became common in the mainframe market and was known as segmented translation, although a variety of terms are used here as well. This style has the advantage of simplicity; the memory blocks are continuous and thus only the two values, base and limit, need to be stored. Each entry corresponds to a block of memory used by a single program, and the translation is invisible to the program, which sees main memory starting at address zero and extending to some fixed value.

The disadvantage of this approach is that it leads to an effect known as external fragmentation. This occurs when memory allocations are released but are non-contiguous. In this case, enough memory may be available to handle a request, but this is spread out and cannot be allocated. On systems where programs start and stop over time, this can eventually lead to memory being highly fragmented and no large blocks remaining. A number of algorithms were developed to address this problem.

Segmenting was widely used on microcomputer platforms of the 1980s. Among the MMUs that used this concept were the Motorola 68451 and Signetics 68905, but many other examples exist. It was also supported in software implementations; one example is Apple's MultiFinder, released in 1987 for the Macintosh platform. Each program was allocated an amount of memory that was pre-selected in the Finder and translation from virtual to physical was accomplished within the programs using handles.

A more common example is the Intel 8088 used in the IBM PC. This implemented a very simple MMU inside the CPU, with four processor registers holding base values accessed directly by the program. These mapped only the upper 4 bits of the 20-bit address, and there was no equivalent of a limit, which was simply the lower 16-bits of the address and thus a fixed 64 kB. Later entries in the x86 architecture series used different approaches.

Segmentation plus paging
Some systems, such as the GE 645 and its successors, used both segmentation and paging. The table of segments, instead of containing per-segment entries giving the physical base address and length of the segment, contains entries giving the physical base address of a page table for the segment, in addition to the length of the segment. Physical memory is divided into fixed-size pages, and the same techniques used for purely page-based demand paging are used for segment-and-page-based demand paging.

Paged translation
Another approach to memory handling is to break up main memory into a contiguous series of fixed-sized blocks. This is similar to the modern demand paging system in that the result is a series of pages, but in these earlier systems the list of pages is fixed in size and normally stored in some form of fast memory like static RAM to improve performance. In this case, the two parts of the address stored by the MMU are known as the segment number and page index.

Consider a processor design with 24-bit addressing, like the original Motorola 68000. In such a system, the MMU splits the virtual address into parts, for instance, the 13 least-significant bits for the page index and the remaining 11 most-significant bits as the segment number. This results a list of 2048 pages of 8 kB each. In this approach, memory requests result in one or more pages being granted to that program, which may not be contiguous in main memory. The MMU maintains a list of page number originally expressed by the program and the actual page number in main memory. When it attempts to access memory, the MMU reads the segment number from the processor's memory bus, finds the corresponding entry for that program in its internal memory, and expresses the mapped version of the value on the memory's bus while the lower bits of the original address are passed through unchanged. Like the segmented case, programs see its memory as a single contiguous block.

There are two disadvantages to this approach. The first is that as the virtual address space expands, the amount of memory needed to hold the mapping increases as well. For instance, in the 68020 the addresses are 32-bits wide, meaning the segment number for the same 8 kB page size is now the upper 19 bits and the mapping table expands to 512 kB in size, far beyond what could be implemented in hardware for reasonable cost in the 1980s. This problem can be reduced by making the pages larger, say 64 kB instead of 8. Now the page index uses 16 bits and the resulting page table is 64 kB, which is more tractable. Moving to a larger page size leads to the second problem, increased internal fragmentation. A program that generates a series of requests for small block will be assigned large blocks and thereby waste large amounts of memory.

The paged translation approach was widely used by microprocessor MMUs in the 1970s and early 80s, including the Signetics 68905 (which could operate in either mode). Both Signetics and Philips produced a version of the 68000 that combined the 68905 on the same physical chip, the 68070.

Another use of this technique is to expand the size of the physical address when the virtual address is too small. For instance, the PDP-11 originally had a 16-bit address that made it too small as memory sizes increased in the 1970s. This was addressed by expanding the physical memory bus to 18-bits, and using an MMU to add two more bits based on other pins on the processor bus to indicate which program was accessing memory.

Another use of this same technique, although not referred to as paging but bank switching, was widely used by early 8-bit microprocessors like the MOS 6502. For instance, the Atari MMU would express additional bits on the address bus to select among several banks of DRAM memory based on which of the chips was currently active, normally the CPU or ANTIC. This was used to expand the available memory on the Atari 130XE to 128 kB. The Commodore 128 used a similar approach.

Examples
Most modern systems divide memory into pages that are 4–64 KB in size, often with the capability to use so called huge pages of 2 MB or 1 GB in size (often both variants are possible). Page translations are cached in a translation lookaside buffer (TLB). Some systems, mainly older RISC designs, trap into the OS when a page translation is not found in the TLB. Most systems use a hardware-based tree walker. Most systems allow the MMU to be disabled, but some disable the MMU when trapping into OS code.

IBM System/360 Model 67, IBM System/370, and successors
The IBM System/360 Model 67, which was introduced August, 1965, included an MMU called a dynamic address translation (DAT) box. It has the unusual feature of storing accessed and dirty bits outside of the page table (along with the four bit protection key for all S/360 processors). They refer to physical memory rather than virtual memory, and are accessed by special-purpose instructions. This reduces overhead for the OS, which would otherwise need to propagate accessed and dirty bits from the page tables to a more physically oriented data structure. This makes OS-level virtualization, later called paravirtualization, easier.

Starting in August, 1972, the IBM System/370 has a similar MMU, although it initially supported only a 24-bit virtual address space rather than the 32-bit virtual address space of the System/360 Model 67. It also stores the accessed and dirty bits outside the page table. In early 1983, the System/370-XA architecture expanded the virtual address space to 31 bits, and in 2000, the 64-bit z/Architecture was introduced, with the address space expanded to 64 bits; those continue to store the accessed and dirty bits outside the page table.

VAX
VAX pages are 512 bytes, which is very small. An OS may treat multiple pages as if they were a single larger page. For example, Linux on VAX groups eight pages together. Thus, the system is viewed as having 4 KB pages. The VAX divides memory into four fixed-purpose regions, each 1 GB in size. They are:
 * P0 space: Used for general-purpose per-process memory such as heaps.
 * P1 space: (Or control space) which is also per-process and is typically used for supervisor, executive, kernel, user stacks and other per-process control structures managed by the operating system.
 * S0 space: (Or system space) which is global to all processes and stores operating system code and data, whether paged or not, including pagetables.
 * S1 space: Which is unused and "Reserved to Digital".

Page tables are big linear arrays. Normally, this would be very wasteful when addresses are used at both ends of the possible range, but the page tables for P0 and P1 space are stored in the paged S0 space. Thus, there is effectively a two-level tree, allowing applications to have sparse memory layout without wasting a lot of space on unused page table entries. Unlike page table entries in most MMUs, page table entries in the VAX MMU lack an accessed bit. OSes which implement paging must find some way to emulate the accessed bit if they are to operate efficiently. Typically, the OS will periodically unmap pages so that page-not-present faults can be used to let the OS set an accessed bit.

ARM
ARM architecture-based application processors implement an MMU defined by ARM's virtual memory system architecture. The current architecture defines PTEs for describing 4 KB and 64 KB pages, 1 MB sections and 16 MB super-sections; legacy versions also defined a 1 KB tiny page. ARM uses a two-level page table if using 4 KB and 64 KB pages, or just a one-level page table for 1 MB sections and 16 MB sections.

TLB updates are performed automatically by page table walking hardware. PTEs include read/write access permission based on privilege, cacheability information, an NX bit, and a non-secure bit.

DEC Alpha
DEC Alpha processors divide memory into 8 KB, 16 KB, 32 KB, or 64 KB; the page size is dependent on the processor. pages. After a TLB miss, low-level firmware machine code (here called PALcode) walks a page table.

The OpenVMS AXP PALcode and DEC OSF/1 PALcode walk a three-level tree-structured page table. Addresses are broken down into an unused set of bits (containing the same value as the uppermost bit of the index into the root level of the tree), a set of bits to index the root level of the tree, a set of bits to index the middle level of the tree, a set of bits to index the leaf level of the tree, and remaining bits that pass through to the physical address without modification, indexing a byte within the page. The sizes of the fields are dependent on the page size; all three tree index fields are the same size. The OpenVMS AXP PALcode supports full read and write permission bits for user, supervisor, executive, and kernel modes, and also supports fault on read/write/execute bits are also supported. The DEC OSF/1 PALcode supports full read and write permission bits for user and kernel modes, and also supports fault on read/write/execute bits are also supported.

The Windows NT AXP PALcode can either walk a single-level page table in a virtual address space or a two-level page table in physical address space. The upper 32 bits of an address are ignored. For a single-level page table, addresses are broken down into a set of bits to index the page table and remaining bits that pass through to the physical address without modification, indexing a byte within the page. For a two-level page table, addresses are borken down into a set of bits to index the root level of the tree, a set of bits to index the top level of the tree, a set of bits to index the leaf level of the tree, and remaining bits that pass through to the physical address without modification, indexing a byte within the page. The sizes of the fields are dependent on the page size. The Windows NT AXP PALcode supports a page being accessible only from kernel mode or being accessible from user and kernel mode, and also supports a fault on write bit.

MIPS
The MIPS architecture supports one to 64 entries in the TLB. The number of TLB entries is configurable at CPU configuration before synthesis. TLB entries are dual. Each TLB entry maps a virtual page number (VPN2) to either one of two page frame numbers (PFN0 or PFN1), depending on the least significant bit of the virtual address that is not part of the page mask. This bit and the page mask bits are not stored in the VPN2. Each TLB entry has its own page size, which can be any value from 1 KB to 256 MB in multiples of four. Each PFN in a TLB entry has a caching attribute, a dirty and a valid status bit. A VPN2 has a global status bit and an OS assigned ID which participates in the virtual address TLB entry match, if the global status bit is set to zero. A PFN stores the physical address without the page mask bits.

A TLB refill exception is generated when there are no entries in the TLB that match the mapped virtual address. A TLB invalid exception is generated when there is a match but the entry is marked invalid. A TLB modified exception is generated when a store instruction references a mapped address and the matching entry's dirty status is not set. If a TLB exception occurs when processing a TLB exception, a double fault TLB exception, it is dispatched to its own exception handler.

MIPS32 and MIPS32r2 support 32 bits of virtual address space and up to 36 bits of physical address space. MIPS64 supports up to 64 bits of virtual address space and up to 59 bits of physical address space.

Sun MMU
The original Sun-1 is a single-board computer built around the Motorola 68000 microprocessor and introduced in 1982. It includes the original Sun 1 memory management unit that provides address translation, memory protection, memory sharing and memory allocation for multiple processes running on the CPU. All access of the CPU to private on-board RAM, external Multibus memory, on-board I/O and the Multibus I/O runs through the MMU, where address translation and protection are done in a uniform fashion. The MMU is implemented in hardware on the CPU board.

The MMU consists of a context register, a segment map and a page map. Virtual addresses from the CPU are translated into intermediate addresses by the segment map, which in turn are translated into physical addresses by the page map. The page size is 2 KB and the segment size is 32 KB which gives 16 pages per segment. Up to 16 contexts can be mapped concurrently. The maximum logical address space for a context is 1024 pages or 2 MB. The maximum physical address that can be mapped simultaneously is also 2 MB.

The context register is important in a multitasking operating system because it allows the CPU to switch between processes without reloading all the translation state information. The 4-bit context register can switch between 16 sections of the segment map under supervisor control, which allows 16 contexts to be mapped concurrently. Each context has its own virtual address space. Sharing of virtual address space and inter-context communications can be provided by writing the same values in to the segment or page maps of different contexts. Additional contexts can be handled by treating the segment map as a context cache and replacing out-of-date contexts on a least-recently used basis.

The context register makes no distinction between user and supervisor states. Interrupts and traps do not switch contexts, which requires that all valid interrupt vectors always be mapped in page 0 of context, as well as the valid supervisor stack.

The Sun-2 workstations are similar; they are built around the Motorola 68010 microprocessor and have a similar memory management unit, with 2 KB pages and 32 KB segments. The context register has a 3-bit system context used in supervisor state and a 3-bit user context used in user state.

The Sun-3 workstations, except for the Sun-3/80, Sun-3/460, Sun-3/470, and Sun-3/480, are built around the Motorola 68020, and have a similar memory management unit. The page size is increased to 8 KB. (The later models are built around the Motorola 68030 and use the 68030's on-chip MMU.)

The Sun-4 workstations are built around various SPARC microprocessors, and have a memory management unit similar to that of the Sun-3 workstations.

PowerPC
In PowerPC G1, G2, G3, and G4 pages are normally 4 KB. After a TLB miss, the standard PowerPC MMU begins two simultaneous lookups. One lookup attempts to match the address with one of four or eight data block address translation (DBAT) registers, or four or eight instruction block address translation registers (IBAT), as appropriate. The BAT registers can map linear chunks of memory as large as 256 MB, and are normally used by an OS to map large portions of the address space for the OS kernel's own use. If the BAT lookup succeeds, the other lookup is halted and ignored.

The other lookup, not directly supported by all processors in this family, is via a so-called inverted page table, which acts as a hashed off-chip extension of the TLB. First, the top four bits of the address are used to select one of 16 segment registers. Then 24 bits from the segment register replace those four bits, producing a 52-bit address. The use of segment registers allows multiple processes to share the same hash table.

The 52-bit address is hashed, then used as an index into the off-chip table. There, a group of eight-page table entries is scanned for one that matches. If none match due to excessive hash collisions, the processor tries again with a slightly different hash function. If this, too, fails, the CPU traps into OS (with MMU disabled) so that the problem may be resolved. The OS needs to discard an entry from the hash table to make space for a new entry. The OS may generate the new entry from a more-normal tree-like page table or from per-mapping data structures which are likely to be slower and more space-efficient. Support for no-execute control is in the segment registers, leading to 256 MB granularity.

A major problem with this design is poor cache locality caused by the hash function. Tree-based designs avoid this by placing the page table entries for adjacent pages in adjacent locations. An operating system running on the PowerPC may minimize the size of the hash table to reduce this problem.

It is also somewhat slow to remove the page table entries of a process. The OS may avoid reusing segment values to delay facing this, or it may elect to suffer the waste of memory associated with per-process hash tables. G1 chips do not search for page table entries, but they do generate the hash, with the expectation that an OS will search the standard hash table via software. The OS can write to the TLB. G2, G3, and early G4 chips use hardware to search the hash table. The latest chips allow the OS to choose either method. On chips that make this optional or do not support it at all, the OS may choose to use a tree-based page table exclusively.

IA-32 / x86
The x86 architecture has evolved over a very long time while maintaining full software compatibility, even for OS code. Thus, the MMU is extremely complex, with many different possible operating modes. Normal operation of the traditional 80386 CPU and its successors (IA-32) is described here.

The CPU primarily divides memory into 4 KB pages. Segment registers, fundamental to the older 8088 and 80286 MMU designs, are not used in modern OSes, with one major exception: access to thread-specific data for applications or CPU-specific data for OS kernels, which is done with explicit use of the FS and GS segment registers. All memory access involves a segment register, chosen according to the code being executed. The segment register acts as an index into a table, which provides an offset to be added to the virtual address. Except when using FS or GS, the OS ensures that the offset will be zero.

After the offset is added, the address is masked to be no larger than 32 bits. The result may be looked up via a tree-structured page table, with the bits of the address being split as follows: 10 bits for the branch of the tree, 10 bits for the leaves of the branch, and the 12 lowest bits being directly copied to the result. Some operating systems, such as OpenBSD with its W^X feature, and Linux with the Exec Shield or PaX patches, may also limit the length of the code segment, as specified by the CS register, to disallow execution of code in modifiable regions of the address space.

Minor revisions of the MMU introduced with the Pentium have allowed very large 4 MB pages by skipping the bottom level of the tree (this leaves 10 bits for indexing the first level of page hierarchy with the remaining 10+12 bits being directly copied to the result). Minor revisions of the MMU introduced with the Pentium Pro introduced the physical address extension (PAE) feature, enabling 36-bit physical addresses with 2+9+9 bits for three-level page tables and 12 lowest bits being directly copied to the result. Large pages (2 MB) are also available by skipping the bottom level of the tree (resulting in 2+9 bits for two-level table hierarchy and the remaining 9+12 lowest bits copied directly). In addition, the page attribute table allowed specification of cacheability by looking up a few high bits in a small on-CPU table.

No-execute support was originally only provided on a per-segment basis, making it very awkward to use. More recent x86 chips provide a per-page no-execute bit in the PAE mode. The W^X, Exec Shield, and PaX mechanisms described above emulate per-page non-execute support on machines x86 processors lacking the NX bit by setting the length of the code segment, with a performance loss and a reduction in the available address space.

x86-64

x86-64 is a 64-bit extension of x86 that almost entirely removes segmentation in favor of the flat memory model used by almost all operating systems for the 386 or newer processors. In long mode, all segment offsets are ignored, except for the FS and GS segments. When used with 4 KB pages, the page table tree has four levels instead of three.

The virtual addresses are divided as follows: 16 bits unused, nine bits each for four tree levels (for a total of 36 bits), and the 12 lowest bits directly copied to the result. With 2 MB pages, there are only three levels of page table, for a total of 27 bits used in paging and 21 bits of offset. Some newer CPUs also support a 1 GB page with two levels of paging and 30 bits of offset.

CPUID can be used to determine if 1 GB pages are supported. In all three cases, the 16 highest bits are required to be equal to the 48th bit, or in other words, the low 48 bits are sign extended to the higher bits. This is done to allow a future expansion of the addressable range, without compromising backwards compatibility. In all levels of the page table, the page table entry includes a no-execute bit.

Burroughs B5000 series, B6500/Unisys MCP systems
The Burroughs B5000 from 1961 was the first commercial system to support virtual memory (after the Atlas), even though it has no MMU. It, its successors, and the Burroughs B6500 and its successors provide the two functions of an MMU - virtual memory addresses and memory protection - with a different architectural approach.

First, in the mapping of virtual memory addresses, instead of needing an MMU, those machines are descriptor-based. The uppermost bit of a 48-bit memory word in the Burroughs B5000/B5500/B5700 systems indicates whether the word is an operand (numeric or logical value) or is a descriptor/control word; descriptors are read-only to user processes and may only be updated by the system (hardware or operating system). Memory words in the Burroughs B6500 system and its successors have 48 data bits and 3 tag bits; words whose tag is an odd number are read-only to user processes - descriptors have a tag of 5 and code words have a tag of 3.

Each allocated memory block is given a master descriptor with the properties of the block (i.e., its physical address, its size, and whether it is present in memory). All references to code and data are made using a descriptor; when a request is made to access the block for reading or writing, the hardware checks its presence via the presence bit (pbit) in the descriptor.

A pbit of 1 indicates the presence of the block. In this case, the block can be accessed via the physical address in the descriptor. If the pbit is zero, an interrupt is generated for the MCP (operating system) to make the block present. If the address field is zero, this is the first access to this block, and it is allocated (an init pbit). If the address field is non-zero, it is a disk address of the block, which has previously been rolled out, so the block is fetched from disk and the pbit is set to one and the physical memory address updated to point to the block in memory (another pbit). This makes descriptors equivalent to a page-table entry in an MMU system. System performance can be monitored through the number of pbits. Init pbits indicate initial allocations, but a high level of other pbits indicate that the system may be thrashing.

All memory allocation is therefore completely automatic (one of the features of modern systems ) and there is no way to allocate blocks other than this mechanism. There are no such calls as malloc or dealloc, since memory blocks are also automatically discarded. The scheme is also lazy, since a block will not be allocated until it is actually referenced. When memory is nearly full, the MCP examines the working set, trying compaction (since the system is segmented, not paged), deallocating read-only segments (such as code-segments which can be restored from their original copy) and, as a last resort, rolling dirty data segments out to disk.

Another way these systems provide a function of a MMU is in protection. Since all accesses are via the descriptor, the hardware can check that all accesses are within bounds and, in the case of a write, that the process has write permission. The MCP system is inherently secure and thus has no need of an MMU to provide this level of memory protection.

Blocks can be shared between processes via copy descriptors in the process stack. Thus, some processes may have write permission, whereas others do not. A code segment is read-only, thus reentrant and shared between processes. Copy descriptors contain a 20-bit address field giving index of the master descriptor in the master descriptor array. This also implements a very efficient and secure IPC mechanism. Blocks can easily be relocated, since only the master descriptor needs update when a block's status changes.

The only other aspect is performance – do MMU-based or non-MMU-based systems provide better performance? MCP systems may be implemented on top of standard hardware that does have an MMU (for example, a standard PC). Even if the system implementation uses the MMU in some way, this will not be at all visible at the MCP level.

title: Memory management unit


text:
Macintosh II

The Macintosh II is a personal computer designed, manufactured, and sold by Apple Computer from March 1987 to January 1990. Based on the Motorola 68020 32-bit CPU, it is the first Macintosh supporting color graphics. When introduced, a basic system with monitor and 20 MB hard drive cost US$5498 1987. With a 13-inch color monitor and 8-bit display card the price was about US$7145 1987. This placed it in competition with workstations from Silicon Graphics, Sun Microsystems, and Hewlett-Packard.

The Macintosh II was the first computer in the Macintosh line without a built-in display; a monitor rested on top of the case like the IBM Personal Computer and Amiga 1000. It was designed by hardware engineers Michael Dhuey (computer) and Brian Berkeley (monitor) and industrial designer Hartmut Esslinger (case).

Eighteen months after its introduction, the Macintosh II was updated with a more powerful CPU and sold as the Macintosh IIx. In early 1989, the more compact Macintosh IIcx was introduced at a price similar to the original Macintosh II, and by the beginning of 1990 sales stopped altogether. Motherboard upgrades to turn a Macintosh II into a IIx or Macintosh IIfx were offered by Apple.

Development
Two common criticisms of the Macintosh from its introduction in 1984 were the closed architecture and lack of color; rumors of a color Macintosh began almost immediately.

The Macintosh II project was begun by Dhuey and Berkeley during 1985 without the knowledge of Apple co-founder and Macintosh division head Steve Jobs, who opposed expansion slots and color, on the basis that expansion slots complicated the user experience and that color did not conform to WYSIWYG, as color printers were not common. Jobs instead wanted higher-resolution monochrome displays, such as the ones chosen for his own "BigMac" project begun in 1984 to develop a Macintosh successor.

Initially referred to as "Little Big Mac", the Macintosh II was codenamed "Milwaukee" after Dhuey's hometown, and later went through a series of new names. After Jobs was fired from Apple in September 1985, the Milwaukee project could proceed openly (while Jobs' own BigMac project was cancelled).

The Macintosh II was introduced at the AppleWorld 1987 conference in Los Angeles, with low-volume initial shipments starting two months later. Retailing for US $5,498, the Macintosh II was the first modular Macintosh model, so called because it came in a horizontal desktop case like many IBM PC compatibles of the time. Previous Macintosh computers use an all-in-one design with a built-in black-and-white CRT.

The Macintosh II has drive bays for an internal hard disk (originally 40 MB or 80 MB) and an optional second floppy disk drive. It, along with the Macintosh SE, was the first Macintosh to use the Apple Desktop Bus (ADB) introduced with the Apple IIGS for keyboard and mouse interface.

The primary improvement in the Macintosh II was Color QuickDraw in ROM, a color version of the Macintosh graphics routines. Color QuickDraw can handle any display size, up to 8-bit color depth, and multiple monitors. Because Color QuickDraw is included in the Macintosh II's ROM and relies on 68020 instructions, earlier systems could not be upgraded to display color.

In September 1988, shortly before the introduction of the Macintosh IIx, Apple increased the list price of the Macintosh II by roughly 20%. AnimEigo notably used the Macintosh II for subtitling their earliest releases, including MADOX-01, Riding Bean, and Vampire Princess Miyu.

Hardware
CPU: The Macintosh II is built around the Motorola 68020 processor operating at 16 MHz, teamed with a Motorola 68881 floating-point unit. The machine shipped with a socket for an optional Motorola 68851 MMU, but an "Apple HMMU Chip" (VLSI VI475 chip) was installed by default and could not implement virtual memory (instead, it translated 24-bit addresses to 32-bit addresses for the Mac OS, which would not be 32-bit clean until System 7).

Memory: The standard memory was 1 megabyte, expandable to 8 MB. The Mac II had eight 30-pin SIMMs, and memory was installed in groups of four (called "Bank A" and "Bank B").

The original Macintosh II did not have a PMMU by default. It relied on the memory controller hardware to map the installed memory into a contiguous address space. This hardware had the restriction that the address space dedicated to Bank A must be larger than those of Bank B. Though this memory controller was designed to support up to 16 MB 30-pin SIMMs for up to 128 MB of RAM, the original Macintosh II ROMs had problems limiting the amount of RAM that could be installed to 8 MB. The Macintosh IIx ROMs that also shipped with the FDHD upgrade fixed this problem, though still do not have a 32-bit Memory Manager and cannot boot into 32-bit addressing mode under Mac OS (without the assistance of MODE32). MODE32 contained a workaround that allowed larger SIMMs to be put in Bank B with the PMMU installed. In this case, the ROMs at boot think that the computer has 8 MB or less of RAM. MODE32 then reprograms the memory controller to dedicate more address space to Bank A, allowing access to the additional memory in Bank B. Since this makes the physical address space discontiguous, the PMMU is then used to remap the address space into a contiguous block.

Graphics: The Macintosh II includes a graphics card that supports a true-color 16.7 million color palette and was available in two configurations: 4-bit and 8-bit. The 4-bit model supports 16 colors on a 640×480 display and 256 colors (8-bit video) on a 512×384 display, which means that VRAM was 256 KB. The 8-bit model supports 256-color video on a 640×480 display, which means that VRAM was 512 KB in size. With an optional RAM upgrade (requiring 120 ns DIP chips), the 4-bit version supports 640×480 in 8-bit color. The video card does not include hardware acceleration of drawing operations.

Display: Apple offered a choice of two displays, a 12" black and white unit, and a more expensive 13" high-resolution color display based on Sony's Trinitron technology. More than one display could be attached to the computer, and objects could be easily dragged from one screen to the next. Third-party displays quickly became available. The Los Angeles Times reviewer called the color "spectacular." The operating system user interface remained black and white even on color monitors with the exception of the Apple logo, which appeared in rainbow color.

Storage: A 5.25-inch 40 MB internal SCSI hard disk was optional, as was a second internal 800 kilobyte 3.5-inch floppy disk drive.

Expansion: Six NuBus slots were available for expansion (at least one of which had to be used for a graphics card, as the Mac II had no onboard graphics chipset and the OS didn't support headless booting). It is possible to connect as many as six displays to a Macintosh II by filling all of the NuBus slots with graphics cards. Another option for expansion included the Mac286, which included an Intel 80286 chip and could be used for MS-DOS compatibility.

The original ROMs in the Macintosh II contained a bug that prevented the system from recognizing more than one megabyte of memory address space on a Nubus card. Every Macintosh II manufactured until approximately November 1987 had this defect. This happened because Slot Manager was not 32-bit clean. Apple offered a well-publicized recall of the faulty ROMs and released a program to test whether a particular Macintosh II had the defect.

Accessories: The Macintosh II and Macintosh SE were the first Apple computers since the Apple I to be sold without a keyboard. Instead the customer was offered a choice of the new ADB Apple Keyboard or the Apple Extended Keyboard as a separate purchase. Dealers could bundle a third-party keyboard or attempt to upsell a customer to the more expensive (and higher-profit) Extended Keyboard.

Audio: The Macintosh II was the first Macintosh to have the Chimes of Death accompany the Sad Mac logo whenever a serious hardware error occurred.

The new extensions featured for the Macintosh II at the time were A/ROSE and Sound Manager.

Models
The Macintosh II was offered in three configurations. All systems included a mouse and a single 800 KB 3.5-inch floppy disk drive; a Motorola 68851 PMMU was available as an option and required for running A/UX.
 * Macintosh II CPU: 1 MB RAM.
 * Macintosh II 1/40 CPU: 1 MB RAM, internal 40-megabyte SCSI HDD.
 * Macintosh II 4/40 CPU: 4 MB RAM, internal 40-megabyte SCSI HDD.

title: Macintosh II


text:
Dolly zoom

A dolly zoom (also known as a Hitchcock shot, Vertigo shot, Jaws effect, or Zolly shot ) is an in-camera effect that appears to undermine normal visual perception.

The effect is achieved by zooming a zoom lens to adjust the angle of view (often referred to as field of view, or FOV) while the camera dollies (moves) toward or away from the subject in such a way as to keep the subject the same size in the frame throughout. The zoom shifts from a wide-angle view into a more tighter-packed angle. In its classic form, the camera angle is pulled away from a subject while the lens zooms in, or vice versa. The dolly zoom's switch in lenses can help audiences identify the visual difference between wide-angle lenses and telephoto lenses. Thus, during the zoom, there is a continuous perspective distortion, the most directly noticeable feature being that the background appears to change size relative to the subject. Hence, the dolly zoom effect can be broken down into three main components: the moving direction of the camera, the dolly speed, and the camera lens' focal length.

The visual appearance for the viewer is that either the background suddenly grows in size and detail and overwhelms the foreground, or the foreground becomes immense and dominates its previous setting, depending on which way the dolly zoom is executed. As the human visual system uses both size and perspective cues to judge the relative sizes of objects, seeing a perspective change without a size change is a highly unsettling effect, often with strong emotional impact.

History
The effect was first conceived by Alfred Hitchcock during the filming of 1940's Rebecca, but he was unable to achieve the desired results. Some 18 years later, success came through Irmin Roberts, a Paramount second-unit cameraman, who devised the proper method for Hitchcock's film Vertigo. It is thought that Alfred Hitchcock specifically asked Roberts to assist him in creating a shot that exemplifies being in a drunk state after fainting at a party. At the time, Roberts had already designed a special camera capable of fast focal lens changes that allowed short-range projections. His expertise in focal lenses most likely prompted his innovation of the dolly zoom, which was more popularly recognized as the "trombone shot" or "contra zoom". Despite this step forward for cinematography, Roberts was not properly credited at the end of Vertigo. However, this shot has since been used in many other films, including Goodfellas, Jaws, and the Lord of the Rings films. Rainer Werner Fassbinder uses the effect twice in one shot in Chinese Roulette (1976). Director Joe Dante referred to it as the "Jaws Shot" since the scene in Jaws, when Roy Scheider sees the shark attack of the little boy Alex, is the most famous use of this shot.

Uses
Among the many creative uses the dolly zoom can provide to cinematographers, the shot can be divided into two types: the dolly-in/zoom-out and the dolly-out/zoom-in. The dolly-in/zoom-out shot is usually centered on a subject, where the background is pushed away from the character to create a profuse amount of uneasiness. For example, Poltergeist's famous dolly zoom stretches the background to make it seem as if the door is much farther away from the character than it actually is. In contrast, the dolly-out/zoom-in shot shrinks the background to seem much closer than it really is.

The dolly zoom is commonly used by filmmakers to represent the sensation of vertigo, a "falling-away-from-oneself feeling" or a feeling of unreality, or to suggest that a character is undergoing a realization that causes them to reassess everything they had previously believed. In general, the dolly zoom's amplification of emotion is a special effect that compliments a director's arsenal of creativity. For example, in Sam Raimi's The Quick and the Dead, a dolly zoom, coupled with a Dutch angle shot, exemplifies drama between an intense shootout. An uneasy feeling of suspense can also be signified through a dolly zoom, most notably used in the movie Split in 2018, where Casey Cooke peers off into the distance in unwanted curiosity. Other uses include demonstrating overwhelming fear or important epiphanies for a character. The dolly zoom can also be utilized for the purposes of tonal shifts within the film. This was most exemplified in The Lord of the Rings: The Fellowship of the Ring, where Peter Jackson chained events together with more flare as opposed to a regular transition. Directors may also decide to use the dolly zoom as an alternative to the generic wide shot in order to give sufficient exposition on the upcoming scene.

Notable examples
In Jaws (1975), the famous "Get Out Of The Water" scene contains a dolly zoom that focuses on Martin Brody's shocking realization of a shark on the beach.

In Raging Bull (1980), Martin Scorsese uses dolly zoom shot to disorient the audience and put them in Jake LaMotta's shoes, and thus creating a vertigo effect.

In Goodfellas (1990), Scorsese uses dolly zooms to convey tensions between characters. This shot is most famously employed in Henry's dive into paranoia, where he eats at a diner with Jimmy while tracking a window to see if anybody has been following him.

In The Lord of the Rings: The Fellowship of the Ring (2001), Frodo stands by as a dolly zoom signifies an entrance of an enemy from the woods.

In Shaun of the Dead (2004), a dolly zoom places comedic emphasis on Shaun's bravery, which ultimately fails when his shotgun jams.

In Ratatouille (2007), the food critic has an intense flashback, signified through a dolly zoom, towards his childhood days after eating Remy's ratatouille. Throughout the film, dolly zooms are used extensively to highlight the bonding between two characters, such as when Remy feels a personal connection with Chef Gusteau on television.

In Guardians of the Galaxy Vol. 2 (2017), Ego emotionally manipulates his son, Peter Quill, into helping him conquer the universe. However, upon confessing that he was the one who gave Peter's mother cancer, Peter immediately snaps out of his trance-like state and attacks his father. This realization is signified by a dolly zoom.

Optics
For most purposes, it can be assumed that the image space and the object space are in the same medium. Thus, for an object in focus, the distance between the lens and image plane $$s_\text{i}$$, the distance between lens and the object $$s_\text{o}$$, and the focal length $$f$$ are related by

 * $${1 \over s_i} + {1 \over s_o} = {1 \over f}.$$

Then the transverse magnification is

 * $$M = {s_\text{i} \over s_\text{o}} = {f \over (s_\text{o} - f)}.$$

The axial magnification $$M_\text{ax}$$ of an object at $$s_\text{o}$$ is the rate of change of the lens–image distance $$s_\text{i}$$ as the lens–object distance $$s_\text{o}$$ changes. For an object of finite depth, one can conceive of the average axial magnification as the ratio of the depth of the image and the depth of the object:

 * $$M_\text{ax} = \left| {d \over d(s_\text{o})} {s_\text{i} \over s_\text{o}} \right| = \left| {d \over d(s_\text{o})} {f \over (s_\text{o} - f)} \right| = \left| {-f \over (s_\text{o} - f)^2} \right| = {M^2 \over f}.$$

One can see that if magnification remains constant, a longer focal length results in a smaller axial magnification, and a smaller focal length in a larger axial magnification. That is, when using a longer focal length while moving the camera/lens away from the object to maintain the same magnification M, objects seem shallower, and the axial distances between objects seem shorter. The opposite—increased axial magnification—happens with shorter focal lengths while moving the camera/lens towards the object.

Calculating distances
To achieve the effect, the camera needs to be positioned at a certain distance from the object that is supposed to remain still during the dolly zoom. The distance depends on how wide the scene is to be filmed and on the field of view (FOV) of the camera lens. Before calculating the distances needed at the different fields of view, the constant width of the scene has to be calculated:

 * $$ \text{distance} = \frac{\text{width}}{2\tan\left(\frac{1}{2}\text{FOV}\right)}.$$

For example, a FOV of 90° and a distance of 2 meters yield a constant width of 4 meters, allowing a 4-meter-wide object to remain still inside the frame during the effect.

title: Dolly zoom


text:
Sir Leo Hielscher Bridges

The Sir Leo Hielscher Bridges, formerly and still collectively referred to as the Gateway Bridge, are a pair of twin road bridges that carry the Gateway Motorway (M1) over the Brisbane River, skirting the eastern suburbs of the city of the same name. The western bridge carries traffic to the north and the eastern bridge carries traffic to the south. They are the most eastern crossings of the Brisbane River and the closest to Moreton Bay, crossing at the Quarries Reach and linking the suburbs of Eagle Farm and Murarrie. The original western bridge (formerly named the Gateway Bridge) was opened on 11 January 1986 and cost A$92 million to build. The duplicate bridge was opened in May 2010, and cost $350 million.

In February 2010, the Queensland Government renamed the Gateway Bridge and its duplicate the Sir Leo Hielscher Bridges. Following the announcement, an opinion poll conducted by Brisbane's Channel Nine News showed that 97% of people were against the decision to rename the bridge and that most would continue to call it the Gateway Bridge.

A public open day for the duplicate bridge was held on 16 May 2010 and the new bridge was opened to traffic on 22 May 2010, six months ahead of schedule. Following the opening, the old bridge was refurbished, three vehicle lanes at a time. From November 2010 the two bridges carry 12 lanes of vehicle traffic (six in each direction). The associated upgrade of the Gateway Motorway south of the bridge was completed in May 2010 to coincide with the new bridge opening.

To pay for the duplication of the bridge, a toll was imposed on the original bridge in 2005, and on the new bridge when the latter opened. The bridges are tolled using the Linkt (formerly go via) electronic system and will remain so until 2051. The toll booths were removed and free flow tolling began in July 2009. The booth removal saw an immediate drop in road crashes due to the reduction in queuing and weaving at the toll booths on the southern approach.

History
Construction on the Gateway Bridge commenced on 5 June 1980. The construction of the bridge started before the design was completed, to fast track its construction. It was officially commissioned on 11 January 1986. On this day 200,000 people crossed the bridge by foot as part of the opening activities.

In 1986 the bridge carried an average of 12,500 vehicles per day. In 2001 the bridge was crossed by 27 million vehicles (approximately 73,975 vehicles per day). In early 2010 the single bridge was carrying an average of 100,000 vehicles per day.

The annual Bridge to Brisbane fun run has begun from the southern entrance to the bridge from its first year until 2015, when it was moved, and again since 2021, after being moved back.

Design

In 1979, a tender was called by the Queensland Main Roads Department for a new bridge crossing of the Brisbane River. The conforming design main span was designed as a balanced cantilever with two raised post tensioned concrete compression stays located on the median and over each of the two main piers to support the 260-metre span. Due to the proximity of the Brisbane Airport, an overall structural height constraint was provided due to aircraft flight path and clearances. This constraint ruled out the possibility of a conventional cable-stayed bridge due to the height of the pylons that would be required. Due to cost considerations, an alternative design concept was proposed by Bruce Ramsay (Manager Engineering) of VSL. This alternative design required a world record main span of 260 m for a free cantilever, concrete box girder bridge. The concept was adopted by one of the tenderers – Transfield Queensland Pty.Ltd. who was subsequently awarded the project on the basis of this alternative. It held the record span of 260 m for over 15 years. The box girder is still the largest prestressed concrete, single box in the world, measuring 15 m deep at the pier, with a box width of 12 m and an overall deck width for the six lanes of 22 m.

As stated above the bridge owes its distinctive shape to air traffic requirements restricting its height to under 80 m above sea level (all features of the bridge including light poles) coupled with shipping needs requiring a navigational clearance of 55 m.

The bridge has six lanes (originally three lanes in each direction, which were subsequently reconfigured to six lanes of northbound traffic after opening of the duplicate bridge).

The bridge was financed by funds borrowed by the Queensland Government, and as a result, users of the bridge pay a toll when crossing the bridge in either direction. The bridge is operated and maintained by Transurban Queensland.

The total length is 1,627 m. This is divided into a southern approach of 376 m, a northern approach of 731 m and the three central spans of 520 m. The record main span is 260 m long by 64.5 m high, which is equivalent to a 20-storey building. A total of 150,000 tonnes (165,000 short tons) of concrete was used to construct the bridge.

The original design did not include a safety fence to prevent suicide attempts and base jumping. Three-metre high safety fences attached to the top of the concrete traffic barrier were later installed to prevent these incidents occurring. Anti-climbing screens are part of the second bridge's security features.

Duplication
In 2005, a major upgrade of the Gateway Motorway was announced. Leighton Contractors and joint venture partner Abigroup won the contract to upgrade the motorway. The A$1.88 billion Gateway Upgrade Project includes the duplication of the Gateway Bridge and upgrades to 20 km of the Gateway Motorway from Mt Gravatt-Capalaba Road in the south to Nudgee Road in the north. The bridge duplication was the largest bridge and road development in Queensland's history. The duplicate bridge was specified to have a design life of 300 years.

To the south, the upgrade included widening 12 km of the Gateway Motorway from 4 to 6 lanes. To the north, it involved the construction of the 7 km Gateway Motorway deviation, an entirely new six-lane motorway between the Gateway Bridge and Nudgee Road. The deviation runs east of the original motorway through Brisbane Airport Corporation land and provides an alternative means of access to Brisbane Airport (the only effective access from the south). The new bridge provides a bicycle path unlike the first crossing.

The Wynnum Road upgrade was completed on 13 July 2007 and 2 additional southbound lanes between the Port of Brisbane Motorway and Wynnum Road completed in late 2007. Four of six lanes of the new Gateway Motorway deviation were opened in July 2009. All works south of the river were complete by the end of 2009 after 10 years of constant roadwork and traffic disruption. The final concrete pour linking the sides of the new bridge was made in late October 2009. A total of 748 concrete segments, which are supported by 17 piers, were placed for the new bridge.

The duplicate bridge was completed in May 2010 along with the remaining lanes of the Gateway Motorway deviation.

In October 2010, then Minister for Main Roads, Craig Wallace, announced that the original course of the Gateway Motorway via Eagle Farm would be renamed to Southern Cross Way, after Sir Charles Kingsford Smith's aircraft, the Southern Cross, which landed at Eagle Farm in 1928, and so as to avoid confusion with the newly opened Gateway Motorway deviation. The new Gateway Motorway deviation was given the name Gateway Motorway. However, like the renaming of the bridges themselves, the change to Southern Cross Way was not without controversy, attracting criticism from the then Shadow Minister for Main Roads and Transport, Fiona Simpson.

Refurbishment of the existing bridge was completed in November 2010.

Awards
In 2009 as part of the Q150 celebrations, the Gateway Bridge was announced as one of the Q150 Icons of Queensland for its role as a "structure and engineering feat".

title: Sir Leo Hielscher Bridges