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Graphics processing unit

A graphics processing unit (GPU) is a specialized electronic circuit initially designed to accelerate computer graphics and image processing (either on a video card or embedded on motherboards, mobile phones, personal computers, workstations, and game consoles). After their initial design, GPUs were found to be useful for non-graphic calculations involving embarrassingly parallel problems due to their parallel structure. Other non-graphical uses include the training of neural networks and cryptocurrency mining.

1970s
Arcade system boards have used specialized graphics circuits since the 1970s. In early video game hardware, RAM for frame buffers was expensive, so video chips composited data together as the display was being scanned out on the monitor.

A specialized barrel shifter circuit helped the CPU animate the framebuffer graphics for various 1970s arcade video games from Midway and Taito, such as Gun Fight (1975), Sea Wolf (1976), and Space Invaders (1978). The Namco Galaxian arcade system in 1979 used specialized graphics hardware that supported RGB color, multi-colored sprites, and tilemap backgrounds. The Galaxian hardware was widely used during the golden age of arcade video games, by game companies such as Namco, Centuri, Gremlin, Irem, Konami, Midway, Nichibutsu, Sega, and Taito.

The Atari 2600 in 1977 used a video shifter called the Television Interface Adaptor. Atari 8-bit computers (1979) had ANTIC, a video processor which interpreted instructions describing a "display list"—the way the scan lines map to specific bitmapped or character modes and where the memory is stored (so there did not need to be a contiguous frame buffer). 6502 machine code subroutines could be triggered on scan lines by setting a bit on a display list instruction. ANTIC also supported smooth vertical and horizontal scrolling independent of the CPU.

1980s

The NEC μPD7220 was the first implementation of a personal computer graphics display processor as a single large-scale integration (LSI) integrated circuit chip. This enabled the design of low-cost, high-performance video graphics cards such as those from Number Nine Visual Technology. It became the best-known GPU until the mid-1980s. It was the first fully integrated VLSI (very large-scale integration) metal–oxide–semiconductor (NMOS) graphics display processor for PCs, supported up to 1024×1024 resolution, and laid the foundations for the emerging PC graphics market. It was used in a number of graphics cards and was licensed for clones such as the Intel 82720, the first of Intel's graphics processing units. The Williams Electronics arcade games Robotron 2084, Joust, Sinistar, and Bubbles, all released in 1982, contain custom blitter chips for operating on 16-color bitmaps.

In 1984, Hitachi released ARTC HD63484, the first major CMOS graphics processor for personal computers. The ARTC could display up to 4K resolution when in monochrome mode. It was used in a number of graphics cards and terminals during the late 1980s. In 1985, the Amiga was released with a custom graphics chip including a blitter for bitmap manipulation, line drawing, and area fill. It also included a coprocessor with its own simple instruction set, that was capable of manipulating graphics hardware registers in sync with the video beam (e.g. for per-scanline palette switches, sprite multiplexing, and hardware windowing), or driving the blitter. In 1986, Texas Instruments released the TMS34010, the first fully programmable graphics processor. It could run general-purpose code, but it had a graphics-oriented instruction set. During 1990–1992, this chip became the basis of the Texas Instruments Graphics Architecture ("TIGA") Windows accelerator cards.

In 1987, the IBM 8514 graphics system was released. It was one of the first video cards for IBM PC compatibles to implement fixed-function 2D primitives in electronic hardware. Sharp's X68000, released in 1987, used a custom graphics chipset with a 65,536 color palette and hardware support for sprites, scrolling, and multiple playfields. It served as a development machine for Capcom's CP System arcade board. Fujitsu's FM Towns computer, released in 1989, had support for a 16,777,216 color palette. In 1988, the first dedicated polygonal 3D graphics boards were introduced in arcades with the Namco System 21 and Taito Air System.

IBM introduced its proprietary Video Graphics Array (VGA) display standard in 1987, with a maximum resolution of 640×480 pixels. In November 1988, NEC Home Electronics announced its creation of the Video Electronics Standards Association (VESA) to develop and promote a Super VGA (SVGA) computer display standard as a successor to VGA. Super VGA enabled graphics display resolutions up to 800×600 pixels, a 36% increase.

1990s
In 1991, S3 Graphics introduced the S3 86C911, which its designers named after the Porsche 911 as an indication of the performance increase it promised. The 86C911 spawned a variety of imitators: by 1995, all major PC graphics chip makers had added 2D acceleration support to their chips. Fixed-function Windows accelerators surpassed expensive general-purpose graphics coprocessors in Windows performance, and such coprocessors faded from the PC market.

Throughout the 1990s, 2D GUI acceleration evolved. As manufacturing capabilities improved, so did the level of integration of graphics chips. Additional application programming interfaces (APIs) arrived for a variety of tasks, such as Microsoft's WinG graphics library for Windows 3.x, and their later DirectDraw interface for hardware acceleration of 2D games in Windows 95 and later.

In the early- and mid-1990s, real-time 3D graphics became increasingly common in arcade, computer, and console games, which led to increasing public demand for hardware-accelerated 3D graphics. Early examples of mass-market 3D graphics hardware can be found in arcade system boards such as the Sega Model 1, Namco System 22, and Sega Model 2, and the fifth-generation video game consoles such as the Saturn, PlayStation, and Nintendo 64. Arcade systems such as the Sega Model 2 and SGI Onyx-based Namco Magic Edge Hornet Simulator in 1993 were capable of hardware T&L (transform, clipping, and lighting) years before appearing in consumer graphics cards. Another early example is the Super FX chip, a RISC-based on-cartridge graphics chip used in some SNES games, notably Doom and Star Fox. Some systems used DSPs to accelerate transformations. Fujitsu, which worked on the Sega Model 2 arcade system, began working on integrating T&L into a single LSI solution for use in home computers in 1995; the Fujitsu Pinolite, the first 3D geometry processor for personal computers, released in 1997. The first hardware T&L GPU on home video game consoles was the Nintendo 64's Reality Coprocessor, released in 1996. In 1997, Mitsubishi released the 3Dpro/2MP, a GPU capable of transformation and lighting, for workstations and Windows NT desktops; ATi used it for its FireGL 4000 graphics card, released in 1997.

The term "GPU" was coined by Sony in reference to the 32-bit Sony GPU (designed by Toshiba) in the PlayStation video game console, released in 1994.

In the PC world, notable failed attempts for low-cost 3D graphics chips included the S3 ViRGE, ATI Rage, and Matrox Mystique. These chips were essentially previous-generation 2D accelerators with 3D features bolted on. Many were pin-compatible with the earlier-generation chips for ease of implementation and minimal cost. Initially, 3D graphics were possible only with discrete boards dedicated to accelerating 3D functions (and lacking 2D graphical user interface (GUI) acceleration entirely) such as the PowerVR and the 3dfx Voodoo. However, as manufacturing technology continued to progress, video, 2D GUI acceleration, and 3D functionality were all integrated into one chip. Rendition's Verite chipsets were among the first to do this well. In 1997, Rendition collaborated with Hercules and Fujitsu on a "Thriller Conspiracy" project which combined a Fujitsu FXG-1 Pinolite geometry processor with a Vérité V2200 core to create a graphics card with a full T&L engine years before Nvidia's GeForce 256; This card, designed to reduce the load placed upon the system's CPU, never made it to market. NVIDIA RIVA 128 was one of the first consumer-facing GPU integrated 3D processing unit and 2D processing unit on a chip.

OpenGL was introduced in the early '90s by SGI as a professional graphics API, with proprietary hardware support for 3D rasterization. In 1994 Microsoft acquired Softimage, the dominant CGI movie production tool used for early CGI movie hits like Jurassic Park, Terminator 2 and Titanic. With that deal came a strategic relationship with SGI and a commercial license of SGI's OpenGL libraries enabling Microsoft to port the API to the Windows NT OS but not to the upcoming release of Windows '95. Although it was little known at the time, SGI had contracted with Microsoft to transition from Unix to the forthcoming Windows NT OS, the deal which was signed in 1995 was not announced publicly until 1998. In the intervening period, Microsoft worked closely with SGI to port OpenGL to Windows NT. In that era OpenGL had no standard driver model for competing hardware accelerators to compete on the basis of support for higher level 3D texturing and lighting functionality. In 1994 Microsoft announced DirectX 1.0 and support for gaming in the forthcoming Windows '95 consumer OS, in '95 Microsoft announced the acquisition of UK based Rendermorphics Ltd and the Direct3D driver model for the acceleration of consumer 3D graphics. The Direct3D driver model shipped with DirectX 2.0 in 1996. It included standards and specifications for 3D chip makers to compete to support 3D texture, lighting and Z-buffering. ATI, which was later to be acquired by AMD, began development on the first Direct3D GPU's. Nvidia, quickly pivoted from a failed deal with Sega  in 1996 to aggressively embracing support for Direct3D. In this era Microsoft merged their internal Direct3D and OpenGL teams and worked closely with SGI to unify driver standards for both industrial and consumer 3D graphics hardware accelerators. Microsoft ran annual events for 3D chip makers called "Meltdowns" to test their 3D hardware and drivers to work both with Direct3D and OpenGL. It was during this period of strong Microsoft influence over 3D standards that 3D accelerator cards moved beyond being simple rasterizers to become more powerful general purpose processors as support for hardware accelerated texture mapping, lighting, Z-buffering and compute created the modern GPU. During this period the same Microsoft team responsible for Direct3D and OpenGL driver standardization introduced their own Microsoft 3D chip design called Talisman. Details of this era are documented extensively in the books: "Game of X" v.1 and v.2 by Russel Demaria, "Renegades of the Empire" by Mike Drummond, "Opening the Xbox" by Dean Takahashi and "Masters of Doom" by David Kushner. The Nvidia GeForce 256 (also known as NV10) was the first consumer-level card with hardware-accelerated T&L; While the OpenGL API provided software support for texture mapping and lighting the first 3D hardware acceleration for these features arrived with the first Direct3D accelerated consumer GPU's.

2000s
Nvidia was first to produce a chip capable of programmable shading: the GeForce 3. Each pixel could now be processed by a short program that could include additional image textures as inputs, and each geometric vertex could likewise be processed by a short program before it was projected onto the screen. Used in the Xbox console, this chip competed with the one in the PlayStation 2, which used a custom vector unit for hardware accelerated vertex processing (commonly referred to as VU0/VU1). The earliest incarnations of shader execution engines used in Xbox were not general purpose and could not execute arbitrary pixel code. Vertices and pixels were processed by different units which had their own resources, with pixel shaders having tighter constraints (because they execute at higher frequencies than vertices). Pixel shading engines were actually more akin to a highly customizable function block and did not really "run" a program. Many of these disparities between vertex and pixel shading were not addressed until the Unified Shader Model.

In October 2002, with the introduction of the ATI Radeon 9700 (also known as R300), the world's first Direct3D 9.0 accelerator, pixel and vertex shaders could implement looping and lengthy floating point math, and were quickly becoming as flexible as CPUs, yet orders of magnitude faster for image-array operations. Pixel shading is often used for bump mapping, which adds texture to make an object look shiny, dull, rough, or even round or extruded.

With the introduction of the Nvidia GeForce 8 series and new generic stream processing units, GPUs became more generalized computing devices. Parallel GPUs are making computational inroads against the CPU, and a subfield of research, dubbed GPU computing or GPGPU for general purpose computing on GPU, has found applications in fields as diverse as machine learning, oil exploration, scientific image processing, linear algebra, statistics, 3D reconstruction, and stock options pricing. GPGPU was the precursor to what is now called a compute shader (e.g. CUDA, OpenCL, DirectCompute) and actually abused the hardware to a degree by treating the data passed to algorithms as texture maps and executing algorithms by drawing a triangle or quad with an appropriate pixel shader. This entails some overheads since units like the scan converter are involved where they are not needed (nor are triangle manipulations even a concern—except to invoke the pixel shader).

Nvidia's CUDA platform, first introduced in 2007, was the earliest widely adopted programming model for GPU computing. OpenCL is an open standard defined by the Khronos Group that allows for the development of code for both GPUs and CPUs with an emphasis on portability. OpenCL solutions are supported by Intel, AMD, Nvidia, and ARM, and according to a report in 2011 by Evans Data, OpenCL had become the second most popular HPC tool.

2010s
In 2010, Nvidia partnered with Audi to power their cars' dashboards, using the Tegra GPU to provide increased functionality to cars' navigation and entertainment systems. Advances in GPU technology in cars helped advance self-driving technology. AMD's Radeon HD 6000 series cards were released in 2010, and in 2011 AMD released its 6000M Series discrete GPUs for mobile devices. The Kepler line of graphics cards by Nvidia were released in 2012 and were used in the Nvidia's 600 and 700 series cards. A feature in this GPU microarchitecture included GPU boost, a technology that adjusts the clock-speed of a video card to increase or decrease it according to its power draw. The Kepler microarchitecture was manufactured.

The PS4 and Xbox One were released in 2013; they both use GPUs based on AMD's Radeon HD 7850 and 7790. Nvidia's Kepler line of GPUs was followed by the Maxwell line, manufactured on the same process. Nvidia's 28 nm chips were manufactured by TSMC in Taiwan using the 28 nm process. Compared to the 40 nm technology from the past, this manufacturing process allowed a 20 percent boost in performance while drawing less power. Virtual reality headsets have high system requirements; manufacturers recommended the GTX 970 and the R9 290X or better at the time of their release. Cards based on the Pascal microarchitecture were released in 2016. The GeForce 10 series of cards are of this generation of graphics cards. They are made using the 16 nm manufacturing process which improves upon previous microarchitectures. Nvidia released one non-consumer card under the new Volta architecture, the Titan V. Changes from the Titan XP, Pascal's high-end card, include an increase in the number of CUDA cores, the addition of tensor cores, and HBM2. Tensor cores are designed for deep learning, while high-bandwidth memory is on-die, stacked, lower-clocked memory that offers an extremely wide memory bus. To emphasize that the Titan V is not a gaming card, Nvidia removed the "GeForce GTX" suffix it adds to consumer gaming cards.

In 2018, Nvidia launched the RTX 20 series GPUs that added ray-tracing cores to GPUs, improving their performance on lighting effects. Polaris 11 and Polaris 10 GPUs from AMD are fabricated by a 14 nm process. Their release resulted in a substantial increase in the performance per watt of AMD video cards. AMD also released the Vega GPU series for the high end market as a competitor to Nvidia's high end Pascal cards, also featuring HBM2 like the Titan V.

In 2019, AMD released the successor to their Graphics Core Next (GCN) microarchitecture/instruction set. Dubbed RDNA, the first product featuring it was the Radeon RX 5000 series of video cards.

The company announced that the successor to the RDNA microarchitecture would be incremental (aka a refresh). AMD unveiled the Radeon RX 6000 series, its RDNA 2 graphics cards with support for hardware-accelerated ray tracing. The product series, launched in late 2020, consisted of the RX 6800, RX 6800 XT, and RX 6900 XT. The RX 6700 XT, which is based on Navi 22, was launched in early 2021.

The PlayStation 5 and Xbox Series X and Series S were released in 2020; they both use GPUs based on the RDNA 2 microarchitecture with incremental improvements and different GPU configurations in each system's implementation.

Intel first entered the GPU market in the late 1990s, but produced lackluster 3D accelerators compared to the competition at the time. Rather than attempting to compete with the high-end manufacturers Nvidia and ATI/AMD, they began integrating Intel Graphics Technology GPUs into motherboard chipsets, beginning with the Intel 810 for the Pentium III, and later into CPUs. They began with the Intel Atom 'Pineview' laptop processor in 2009, continuing in 2010 with desktop processors in the first generation of the Intel Core line and with contemporary Pentiums and Celerons. This resulted in a large nominal market share, as the majority of computers with an Intel CPU also featured this embedded graphics processor. These generally lagged behind discrete processors in performance. Intel re-entered the discrete GPU market in 2022 with its Arc series, which competed with the then-current GeForce 30 series and Radeon 6000 series cards at competitive prices.

2020s
In the 2020s, GPUs have been increasingly used for calculations involving embarrassingly parallel problems, such as training of neural networks on enormous datasets that are needed for large language models. Specialized processing cores on some modern workstation's GPUs are dedicated for deep learning since they have significant FLOPS performance increases, using 4×4 matrix multiplication and division, resulting in hardware performance up to 128 TFLOPS in some applications. These tensor cores are expected to appear in consumer cards, as well.

GPU companies
Many companies have produced GPUs under a number of brand names. In 2009, Intel, Nvidia, and AMD/ATI were the market share leaders, with 49.4%, 27.8%, and 20.6% market share respectively. In addition, Matrox produces GPUs. Modern smartphones use mostly Adreno GPUs from Qualcomm, PowerVR GPUs from Imagination Technologies, and Mali GPUs from ARM.

Computational functions
Modern GPUs have traditionally used most of their transistors to do calculations related to 3D computer graphics. In addition to the 3D hardware, today's GPUs include basic 2D acceleration and framebuffer capabilities (usually with a VGA compatibility mode). Newer cards such as AMD/ATI HD5000–HD7000 lack dedicated 2D acceleration; it is emulated by 3D hardware. GPUs were initially used to accelerate the memory-intensive work of texture mapping and rendering polygons. Later, were added to accelerate geometric calculations such as the rotation and translation of vertices into different coordinate systems. Recent developments in GPUs include support for programmable shaders which can manipulate vertices and textures with many of the same operations that are supported by CPUs, oversampling and interpolation techniques to reduce aliasing, and very high-precision color spaces.

Several factors of GPU construction affect the performance of the card for real-time rendering, such as the size of the connector pathways in the semiconductor device fabrication, the clock signal frequency, and the number and size of various on-chip memory caches. Performance is also affected by the number of streaming multiprocessors (SM) for NVidia GPUs, or compute units (CU) for AMD GPUs, or Xe cores for Intel discrete GPUs, which describe the number of core on-silicon processor units within the GPU chip that perform the core calculations, typically working in parallel with other SM/CUs on the GPU. GPU performance is typically measured in floating point operations per second (FLOPS); GPUs in the 2010s and 2020s typically deliver performance measured in teraflops (TFLOPS). This is an estimated performance measure, as other factors can affect the actual display rate.

GPU accelerated video decoding and encoding
Most GPUs made since 1995 support the YUV color space and hardware overlays, important for digital video playback, and many GPUs made since 2000 also support MPEG primitives such as motion compensation and iDCT. This hardware-accelerated video decoding, in which portions of the video decoding process and video post-processing are offloaded to the GPU hardware, is commonly referred to as "GPU accelerated video decoding", "GPU assisted video decoding", "GPU hardware accelerated video decoding", or "GPU hardware assisted video decoding".

Recent graphics cards decode high-definition video on the card, offloading the central processing unit. The most common APIs for GPU accelerated video decoding are DxVA for Microsoft Windows operating systems and VDPAU, VAAPI, XvMC, and XvBA for Linux-based and UNIX-like operating systems. All except XvMC are capable of decoding videos encoded with MPEG-1, MPEG-2, MPEG-4 ASP (MPEG-4 Part 2), MPEG-4 AVC (H.264 / DivX 6), VC-1, WMV3/WMV9, Xvid / OpenDivX (DivX 4), and DivX 5 codecs, while XvMC is only capable of decoding MPEG-1 and MPEG-2.

There are several dedicated hardware video decoding and encoding solutions.

Video decoding processes that can be accelerated
Video decoding processes that can be accelerated by modern GPU hardware are:
 * Motion compensation (mocomp)
 * Inverse discrete cosine transform (iDCT)
 * Inverse telecine 3:2 and 2:2 pull-down correction
 * Inverse modified discrete cosine transform (iMDCT)
 * In-loop deblocking filter
 * Intra-frame prediction
 * Inverse quantization (IQ)
 * Variable-length decoding (VLD), more commonly known as slice-level acceleration
 * Spatial-temporal deinterlacing and automatic interlace/progressive source detection
 * Bitstream processing (Context-adaptive variable-length coding/Context-adaptive binary arithmetic coding) and perfect pixel positioning

These operations also have applications in video editing, encoding, and transcoding.

2D graphics APIs
An earlier GPU may support one or more 2D graphics API for 2D acceleration, such as GDI and DirectDraw.

3D graphics APIs
A GPU can support one or more 3D graphics API, such as DirectX, Metal, OpenGL, OpenGL ES, Vulkan.

Terminology
In the 1970s, the term "GPU" originally stood for graphics processor unit and described a programmable processing unit working independently from the CPU that was responsible for graphics manipulation and output. In 1994, Sony used the term (now standing for graphics processing unit) in reference to the PlayStation console's Toshiba-designed Sony GPU. The term was popularized by Nvidia in 1999, who marketed the GeForce 256 as "the world's first GPU". It was presented as a "single-chip processor with integrated transform, lighting, triangle setup/clipping, and rendering engines". Rival ATI Technologies coined the term "visual processing unit" or VPU with the release of the Radeon 9700 in 2002. The AMD Alveo MA35D features dual VPU’s, each using the 5 nm process in 2023.

In personal computers, there are two main forms of GPUs. Each has many synonyms:
 * Dedicated graphics also called discrete graphics.
 * Integrated graphics also called shared graphics solutions, integrated graphics processors (IGP), or unified memory architecture (UMA).

Usage-specific GPU
Most GPUs are designed for a specific use, real-time 3D graphics, or other mass calculations:
 * 1) Gaming
 * 2) *GeForce GTX, RTX
 * 3) * Nvidia Titan
 * 4) * Radeon HD, R5, R7, R9, RX, Vega and Navi series
 * 5) * Radeon VII
 * 6) * Intel Arc
 * 7) Cloud Gaming
 * 8) *Nvidia GRID
 * 9) * Radeon Sky
 * 10) Workstation
 * 11) * Nvidia Quadro
 * 12) * Nvidia RTX
 * 13) * AMD FirePro
 * 14) *AMD Radeon Pro
 * 15) *Intel Arc Pro
 * 16) Cloud Workstation
 * 17) *Nvidia Tesla
 * 18) * AMD FireStream
 * 19) Artificial Intelligence training and Cloud
 * 20) *Nvidia Tesla
 * 21) * AMD Radeon Instinct
 * 22) Automated/Driverless car
 * 23) * Nvidia Drive PX

Dedicated graphics processing unit
Dedicated graphics processing units uses RAM that is dedicated to the GPU rather than relying on the computer’s main system memory. This RAM is usually specially selected for the expected serial workload of the graphics card (see GDDR). Sometimes systems with dedicated discrete GPUs were called "DIS" systems as opposed to "UMA" systems (see next section).

Dedicated GPUs are not necessarily removable, nor does it necessarily interface with the motherboard in a standard fashion. The term "dedicated" refers to the fact that graphics cards have RAM that is dedicated to the card's use, not to the fact that most dedicated GPUs are removable. Dedicated GPUs for portable computers are most commonly interfaced through a non-standard and often proprietary slot due to size and weight constraints. Such ports may still be considered PCIe or AGP in terms of their logical host interface, even if they are not physically interchangeable with their counterparts.

Graphics cards with dedicated GPUs typically interface with the motherboard by means of an expansion slot such as PCI Express (PCIe) or Accelerated Graphics Port (AGP). They can usually be replaced or upgraded with relative ease, assuming the motherboard is capable of supporting the upgrade. A few graphics cards still use Peripheral Component Interconnect (PCI) slots, but their bandwidth is so limited that they are generally used only when a PCIe or AGP slot is not available.

Technologies such as Scan-Line Interleave by 3dfx, SLI and NVLink by Nvidia and CrossFire by AMD allow multiple GPUs to draw images simultaneously for a single screen, increasing the processing power available for graphics. These technologies, however, are increasingly uncommon; most games do not fully use multiple GPUs, as most users cannot afford them. Multiple GPUs are still used on supercomputers (like in Summit), on workstations to accelerate video (processing multiple videos at once)  and 3D rendering, for VFX, GPGPU workloads and for simulations, and in AI to expedite training, as is the case with Nvidia's lineup of DGX workstations and servers, Tesla GPUs, and Intel's Ponte Vecchio GPUs.

Integrated graphics processing unit

Integrated graphics processing units (IGPU), integrated graphics, shared graphics solutions, integrated graphics processors (IGP), or unified memory architectures (UMA) use a portion of a computer's system RAM rather than dedicated graphics memory. IGPs can be integrated onto a motherboard as part of its northbridge chipset, or on the same die (integrated circuit) with the CPU (like AMD APU or Intel HD Graphics). On certain motherboards, AMD's IGPs can use dedicated sideport memory: a separate fixed block of high performance memory that is dedicated for use by the GPU. computers with integrated graphics account for about 90% of all PC shipments. They are less costly to implement than dedicated graphics processing, but tend to be less capable. Historically, integrated processing was considered unfit for 3D games or graphically intensive programs but could run less intensive programs such as Adobe Flash. Examples of such IGPs would be offerings from SiS and VIA circa 2004. However, modern integrated graphics processors such as AMD Accelerated Processing Unit and Intel Graphics Technology (HD, UHD, Iris, Iris Pro, Iris Plus, and Xe-LP) can handle 2D graphics or low-stress 3D graphics.

Since GPU computations are memory-intensive, integrated processing may compete with the CPU for relatively slow system RAM, as it has minimal or no dedicated video memory. IGPs use system memory with bandwidth up to a current maximum of 128 GB/s, whereas a discrete graphics card may have a bandwidth of more than 1000 GB/s between its VRAM and GPU core. This memory bus bandwidth can limit the performance of the GPU, though multi-channel memory can mitigate this deficiency. Older integrated graphics chipsets lacked hardware transform and lighting, but newer ones include it.

On systems with "Unified Memory Architecture" (UMA), including modern AMD processors with integrated graphics, modern Intel processors with integrated graphics, Apple processors, the PS5 and Xbox Series (among others), the CPU cores and the GPU block share the same pool of RAM and memory address space. This allows the system to dynamically allocate memory between the CPU cores and the GPU block based on memory needs (without needing a large static split of the RAM) and thanks to zero copy transfers, removes the need for either copying data over a bus (computing) between physically separate RAM pools or copying between separate address spaces on a single physical pool of RAM, allowing more efficient transfer of data.

Hybrid graphics processing
Hybrid GPUs compete with integrated graphics in the low-end desktop and notebook markets. The most common implementations of this are ATI's HyperMemory and Nvidia's TurboCache.

Hybrid graphics cards are somewhat more expensive than integrated graphics, but much less expensive than dedicated graphics cards. They share memory with the system and have a small dedicated memory cache, to make up for the high latency of the system RAM. Technologies within PCI Express make this possible. While these solutions are sometimes advertised as having as much as 768 MB of RAM, this refers to how much can be shared with the system memory.

Stream processing and general purpose GPUs (GPGPU)
It is common to use a general purpose graphics processing unit (GPGPU) as a modified form of stream processor (or a vector processor), running compute kernels. This turns the massive computational power of a modern graphics accelerator's shader pipeline into general-purpose computing power. In certain applications requiring massive vector operations, this can yield several orders of magnitude higher performance than a conventional CPU. The two largest discrete (see "Dedicated graphics processing unit" above) GPU designers, AMD and Nvidia, are pursuing this approach with an array of applications. Both Nvidia and AMD teamed with Stanford University to create a GPU-based client for the Folding@home distributed computing project for protein folding calculations. In certain circumstances, the GPU calculates forty times faster than the CPUs traditionally used by such applications.

GPGPUs can be used for many types of embarrassingly parallel tasks including ray tracing. They are generally suited to high-throughput computations that exhibit data-parallelism to exploit the wide vector width SIMD architecture of the GPU.

GPU-based high performance computers play a significant role in large-scale modelling. Three of the ten most powerful supercomputers in the world take advantage of GPU acceleration.

GPUs support API extensions to the C programming language such as OpenCL and OpenMP. Furthermore, each GPU vendor introduced its own API which only works with their cards: AMD APP SDK from AMD, and CUDA from Nvidia. These allow functions called compute kernels to run on the GPU's stream processors. This makes it possible for C programs to take advantage of a GPU's ability to operate on large buffers in parallel, while still using the CPU when appropriate. CUDA was the first API to allow CPU-based applications to directly access the resources of a GPU for more general purpose computing without the limitations of using a graphics API.

Since 2005 there has been interest in using the performance offered by GPUs for evolutionary computation in general, and for accelerating the fitness evaluation in genetic programming in particular. Most approaches compile linear or tree programs on the host PC and transfer the executable to the GPU to be run. Typically a performance advantage is only obtained by running the single active program simultaneously on many example problems in parallel, using the GPU's SIMD architecture. However, substantial acceleration can also be obtained by not compiling the programs, and instead transferring them to the GPU, to be interpreted there. Acceleration can then be obtained by either interpreting multiple programs simultaneously, simultaneously running multiple example problems, or combinations of both. A modern GPU can simultaneously interpret hundreds of thousands of very small programs.

External GPU (eGPU)
An external GPU is a graphics processor located outside of the housing of the computer, similar to a large external hard drive. External graphics processors are sometimes used with laptop computers. Laptops might have a substantial amount of RAM and a sufficiently powerful central processing unit (CPU), but often lack a powerful graphics processor, and instead have a less powerful but more energy-efficient on-board graphics chip. On-board graphics chips are often not powerful enough for playing video games, or for other graphically intensive tasks, such as editing video or 3D animation/rendering.

Therefore, it is desirable to attach a GPU to some external bus of a notebook. PCI Express is the only bus used for this purpose. The port may be, for example, an ExpressCard or mPCIe port (PCIe ×1, up to 5 or 2.5 Gbit/s respectively), a Thunderbolt 1, 2, or 3 port (PCIe ×4, up to 10, 20, or 40 Gbit/s respectively), or an OCuLink port. Those ports are only available on certain notebook systems. eGPU enclosures include their own power supply (PSU), because powerful GPUs can consume hundreds of watts.

Official vendor support for external GPUs has gained traction. A milestone was Apple's decision to support external GPUs with MacOS High Sierra 10.13.4. Several major hardware vendors (HP, Razer) released Thunderbolt 3 eGPU enclosures. This support fuels eGPU implementations by enthusiasts.

Sales
In 2013, 438.3 million GPUs were shipped globally and the forecast for 2014 was 414.2 million. However, by the third quarter of 2022, shipments of integrated GPUs totaled around 75.5 million units, down 19% year-over-year.

Hardware

 * List of AMD graphics processing units
 * List of Nvidia graphics processing units
 * List of Intel graphics processing units
 * Intel GMA
 * Larrabee
 * Nvidia PureVideo – the bit-stream technology from Nvidia used in their graphics chips to accelerate video decoding on hardware GPU with DXVA.
 * SoC
 * UVD (Unified Video Decoder) – the video decoding bit-stream technology from ATI to support hardware (GPU) decode with DXVA

APIs

 * OpenGL API
 * DirectX Video Acceleration (DxVA) API for Microsoft Windows operating-system.
 * Mantle (API)
 * Vulkan (API)
 * Video Acceleration API (VA API)
 * VDPAU (Video Decode and Presentation API for Unix)
 * X-Video Bitstream Acceleration (XvBA), the X11 equivalent of DXVA for MPEG-2, H.264, and VC-1
 * X-Video Motion Compensation – the X11 equivalent for MPEG-2 video codec only

Applications

 * GPU cluster
 * Mathematica – includes built-in support for CUDA and OpenCL GPU execution
 * Molecular modeling on GPU
 * Deeplearning4j – open-source, distributed deep learning for Java

title: Graphics processing unit


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Aaronic priesthood (Latter Day Saints)

The Aaronic priesthood (also called the priesthood of Aaron or the Levitical priesthood) is the lesser of the two orders of priesthood recognized in the Latter Day Saint movement. The higher being the Melchizedek priesthood. Unlike the Melchizedek priesthood, which is modeled after the authority of Jesus and the Twelve Apostles, the Aaronic priesthood is modeled after the priesthood of Aaron the Levite, the first high priest of the Hebrews, and his descendants. The Aaronic priesthood is thought to be a lesser or preparatory priesthood and an "appendage" of the more powerful Melchizedek priesthood.

In the Church of Jesus Christ of Latter-day Saints (LDS Church) today, the holders of the Aaronic priesthood are primarily young men ages 11 to 18 and recent adult male converts to the church. The general leadership of the Aaronic priesthood, called the Presiding Bishopric, are administrative and financial agents of the church. Local leaders of the Aaronic priesthood are adult male bishops, who serve as pastoral leaders of individual congregations. Aaronic priesthood holders generally prepare, bless, and administer the sacrament, collect fast offerings, perform church and community service, assist in ministering, and occasionally perform baptisms. In their priesthood activities, holders of the Aaronic priesthood are also supported by the church's Young Men organization.

History
Latter Day Saints believe that John the Baptist conferred the Aaronic priesthood directly upon Joseph Smith and Oliver Cowdery on May 15, 1829. Smith relates the conferral of the Aaronic priesthood in Joseph Smith–History as follows:

[W]e ... went into the woods to pray and inquire of the Lord respecting baptism for the remission of sins, that we found mentioned in the translation of the plates [Book of Mormon] .... While we were thus employed, praying and calling upon the Lord, a messenger from heaven descended in a cloud of light, and having laid his hands upon us, he ordained us, saying:

Upon you my fellow servants, in the name of Messiah, I confer the Priesthood of Aaron, which holds the keys of the ministering of angels, and of the gospel of repentance, and of baptism by immersion for the remission of sins; and this shall never be taken again from the earth until the sons of Levi do offer again an offering unto the Lord in righteousness.

He said this Aaronic Priesthood had not the power of laying on hands for the gift of the Holy Ghost, but that this should be conferred on us hereafter, and he commanded us to go and be baptized, and gave us directions that I should baptize Oliver Cowdery, and that afterward, he should baptize me.

Accordingly, we went and were baptized.

The messenger who visited us on this occasion and conferred this Priesthood upon us, said that his name was John, the same that is called John the Baptist in the New Testament, and that he acted under the direction of Peter, James and John, who held the keys of the Priesthood of Melchizedek, which Priesthood, he said, would in due time be conferred on us, and that I should be called the first Elder of the Church, and he (Oliver Cowdery) the second.

Immediately on our coming up out of the water after we had been baptized, we experienced great and glorious blessings from our Heavenly Father. No sooner had I baptized Oliver Cowdery, than the Holy Ghost fell upon him, and he stood up and prophesied many things which should shortly come to pass. And again, so soon as I had been baptized by him, I also had the spirit of prophecy, when, standing up, I prophesied concerning the rise of this Church, and many other things connected with the Church, and this generation of the children of men. We were filled with the Holy Ghost, and rejoiced in the God of our salvation."

Early days
From the start of the Church of Christ, the first members of the Aaronic priesthood were mostly adults. Early priests included Joseph Smith Sr. (59), Martin Harris (47), and two 30-year-old members: Hyrum Smith and Newel Knight. Teachers were Hezekiah Peck (49), Christian Whitmer (32), Hiram Page (30), and William Smith (20). Among the early deacons in the church were Titus Billings (38).

There were some youth that were ordained to the Aaronic priesthood, including William F. Cahoon (17), Don Carlos Smith (14), and Erastus (15) and James Snow (17). In these early years, the holders of the priesthood had adult duties thrust upon them. For instance, in the Missouri Stake, the teachers quorum dealt with helping a brother quit tobacco, worked with a married couple in a dispute, settled neighborly disputes over cattle, and dealt with "lying and extortion." Adult deacons assisted priests and teachers in maintaining the houses of worship, seating people, making wine for the sacrament, and getting a license so that they could preach in homes. In 1833, plans for the Kirtland Temple included four rows for the presidencies of the Aaronic priesthood; these clearly were intended for adults and not youth. In Nauvoo between 1839 and 1846, the average age of the priests was 29; however, there were four teenagers between 17 and 19. (This practice with respect to age continued on in the Reorganized Church of Jesus Christ of Latter Day Saints.)

1849–77 in the LDS Church
After the succession crisis which followed Smith's death, between the years 1846 and 1877, changes started to occur as the members of the LDS Church moved west to Salt Lake City. Wards were created as the primary organizational unit of the church; however, the deacons, teachers, and priests were still stake-level positions. Adult men were still the major source for priests and teachers, as their duties entailed visiting ward members to check on spiritual well-being, settling disputes, collecting contributions, and helping those in need. Teachers occasionally would sit and judge in cases of wrongdoing, a job normally reserved for bishops. The church leadership would hold drives to ensure that positions were filled not as a need of the members to hold the priesthood, but as a need of the church to have the necessary males to accomplish the needed tasks.

By 1855, the Endowment House in Salt Lake City was completed and church leaders called for it to be busy in granting endowments to men and women. Each ward had quotas to fill in completing endowments, and the men that were sent to receive theirs were required to hold the Melchizedek priesthood. The average age of men who received the endowment at this time was 22; some were as young as 14. So many men were receiving the senior priesthood and their endowments that there were too few to fill the ranks of the junior priesthood. Brigham Young commented that perhaps men should receive the portion of the endowment pertaining to the Aaronic priesthood first before their missions. This would have allowed Aaronic priesthood holders to have served as missionaries; however, this idea was never implemented.

Melchizedek priesthood quorums also engaged in recruiting members from the Aaronic priesthood, which further depleted the ranks of the lesser priesthood. Unlike today, it was not a requirement to hold the Aaronic priesthood before receiving the Melchizedek priesthood, so the recruiting by the higher priesthood included the unordained as well. Presiding Bishop Edward Hunter and Brigham Young both lamented over the rush to ordain men to be high priests or seventies and the subsequent difficulty in keeping the Aaronic priesthood ranks filled. As examples, in 1857, Francis M. Lyman and Rudger Clawson were both ordained as elders at age 16; Clarence Merrill was ordained as a seventy at age 16.

In 1849, Young initiated an apprenticeship program whereby the holders of the Aaronic priesthood would take boys with them to teach them and give them experience. No age limits were specified. This helped to temporarily alleviate the problem arising from the dearth of Aaronic priesthood holders. By 1852, church leaders were instructing bishops to set apart members of the Melchizedek priesthood as "acting" teachers, priests, and deacons. Some bishops would ordain a few mature youth as teachers to accompany the "acting" teachers and learn the tasks. Whitney's successor, Edward Hunter, continued this practice of ordaining seventies and high priests as "acting" teachers, deacons, and priests. During the 19th century, home visits, which remained the paramount task of the Aaronic priesthood, entailed visiting from between eight and 20 families monthly, quarterly, or whenever possible. They also continued to be peacemakers and occasionally would judge wrongdoers. Hunter is quoted as saying, "The order of the church is to call in the labors of the teachers & if they cannot reconcile the parties it cannot be done."

Youth began to be ordained to the Aaronic priesthood and in 1854 one ward reported that "the principal portion of the young men had been ordained to the lesser priesthood." Possibly the youngest holders of the lesser priesthood were George J. Hunt, who was ordained a priest at age nine, and Solomon W. Harris, baptized and then ordained as a deacon at age eight. However, by the mid-1850s leaders were warning against ordaining unmarried men, and in the October 1856 general conference Young expressed disapproval regarding inexperienced "young men" being ordained: "When you have got your Bishop, he needs assistants, and he ordains Counsellors, Priests, Teachers, and Deacons, and calls them to help him; and he wishes men of his own heart and hand to do this. Says he, 'I dare not even call a man to be a Deacon, to assist me in my calling, unless he has a family.' It is not the business of an ignorant young man, of no experience in family matters, to inquire into the circumstances of families, and know the wants of every person. Some may want medicine and nourishment and be looked after, and it is not the business of boys to do this, but select a man who has got a family to be a Deacon."

The 1870s saw a reversal of the trend of less youth being ordained. Circumstances at the time dictated a change. First, the youth of the Salt Lake City, Provo, and St. George areas were misbehaving in ever-increasing numbers with ever-worsening acts. Some complaints from the era were as follows: "rowdyism is rampant"; "crowds of uncouth boys loitering around the stores halloing in the streets, and breaking horses on the Sabbath"; "uncouth and ill manners in refusing half the road on meeting teams"; "using pencils on walls and nails on the rails of the bannisters"; "strip[ping] of his clothes" (in reference to a mentally handicapped boy); "intoxicated and using the vilest language"; "a gang" spitting "tobacco juice on the floor". The church felt that it could help with such behavior, first by creating the auxiliary organizations for young women in 1869, young men in 1875, and Primary in 1878 for the younger children. This also led to a modest effort to recruit the young men into the Aaronic priesthood. Salt Lake Stake President Angus M. Cannon directed bishops "to draw the young men into positions in the Priesthood and thus an excellent experience, and, at the same time, preserve them from evil associations."

However, the lack of adult men willing to serve in Aaronic priesthood was ultimately the determining factor in the church ordaining youth. Young instructed Hunter in 1873 that each stake should have a full quorum of priests, teachers, and deacons; however, Hunter complained that he could not find willing men to fill these positions. One bishop noted, "It is a difficult task to find a sufficient quantity of efficient teachers. I have thought of calling upon some of the boys." Another stated, "It is very hard to get the older men to act as Teachers, but the young men come forward and are willing to take their parts and therefore we have to appoint young men where older ones should be." By the time of Young's death, he had taken the position that all boys needed some priesthood experience and that they should receive the Aaronic priesthood before reaching adulthood.

Role within the LDS Church today
In the LDS Church today, the Aaronic priesthood has taken on a role as a source of training, leadership, and service for adolescent boys and new converts. It is often called a "preparatory priesthood." Holders of the Aaronic priesthood whom the church considers worthy are ordained to an office in the Melchizedek priesthood as a matter of course around the age of 18. Recently baptized men ages 18 and older are ordained elders after they have:

 * Received the Aaronic Priesthood and served as priests.
 * Developed sufficient understanding of the gospel.
 * Demonstrated their worthiness.
 * No specific time as a church member is required.

The Aaronic priesthood is open only to men and boys, twelve years old or older, who are considered worthy after a personal interview with their bishop. Requirements for worthiness include abstaining from all extra-marital sexual practices, following the Word of Wisdom, payment of tithes, and attending church services.

With the exception of bishop, the offices of the Aaronic priesthood are organized primarily by age, and an adolescent boy will be ordained to the next office if found worthy upon reaching the appropriate age. Active Aaronic priesthood holders seldom delay ordination to another priesthood office. The conferral and ordination to an office in the Aaronic priesthood is performed by the laying on of hands by a priest or by those holding the Melchizedek priesthood.

With the exception of bishop, Aaronic priesthood holders of the same office are organized into a quorum, each being led by a president and counselors. The president of the priests quorum is the bishop or branch president. Each ward has one or more quorums of each office of the priesthood if there are young men of the appropriate age group.

The church-wide titular head of the Aaronic priesthood is the Presiding Bishop. However, because the Aaronic priesthood is composed primarily of the youth of the church, the presidency of the Young Men organization supervises much of the church-wide organization involving the Aaronic priesthood.

Hierarchy
Holders of the Aaronic priesthood meet at the ward or branch where the priesthood holder lives. Young men who do not hold the office of the priesthood of the age group associated with each quorum are still invited and encouraged to attend with the quorum of their age group. However, priesthood duties can only be performed by those who are ordained.

Teacher
In the LDS Church, the teacher is the second of four offices in the Aaronic priesthood. Male members of the church are eligible to be ordained teachers at the beginning of the year in which they turn 14 years of age. Approval by the bishop and an interview with him or one of his counselors is required before ordination. Prior to ordination, the proposed ordination must also be accepted by common consent by the members of the ward. With the approval of the bishop, a priest or a holder of the Melchizedek priesthood may ordain a person to the office of teacher by the laying on of hands.

As specified in the Doctrine and Covenants, a teachers quorum may not contain more than 24 members. As a result, in some larger wards there are two teacher quorums. A presidency, consisting of a president, first counselor, and second counselor, is called from members of the quorum by the bishopric and set apart to serve as the presidency of the teachers quorum. The president of the teachers quorum is given priesthood keys by the laying on of hands by the bishop to preside over the members of his quorum. A secretary to the presidency may also be called from the quorum membership. The members of the teachers quorum presidency and the secretary may not be set apart until after they have been accepted by the common consent of the members of the quorum.

The duties of a teacher are to assist the priests in taking care of the temporal needs of the church, and "to warn, expound, exhort, and teach, and invite all to come unto Christ". Teachers are permitted to assist in preparing the sacrament, usher during sacrament meeting, and perform all the duties of a deacon. Teachers are also typically paired with an adult male (often their father) to perform ministering.

An adult teachers quorum adviser may be called to assist the teachers. Sometimes an assistant adviser is also called.

After an interview with the bishop, teachers who are deemed worthy are ordained to the office of priest at the beginning of the year in which they turn 16 years of age, whereupon they will become members of the priests quorum.

Deacon
In the LDS Church, the deacon is the first of four offices of the Aaronic priesthood to which a male may be ordained. Male members of the church may become deacons at the beginning of the year in which they turn 12 years of age. A bishop may give approval for such members to receive the Aaronic priesthood and ordained to the office of deacon. Prior to ordination, the candidate must have an interview with the bishop or one of his counselors, and the proposed ordination must be accepted by common consent by the members of the ward. With the bishop's approval, a person who holds the office of priest or a holder of the Melchizedek priesthood is able to perform the ordination of a deacon by the laying on of hands.

Deacons in a ward are organized in quorums. The Doctrine and Covenants states that a president of a deacons quorum can preside over 12 deacons. As a result, in some large wards, there may be two or more quorums of deacons. From the members of each deacon's quorum, a president, first counselor, second counselor, and secretary may be called and set apart by the bishopric. The president and his two counselors constitute the deacon's quorum presidency. The president of the deacons quorum is given priesthood keys by the laying on of hands by the bishop to preside over the members of his quorum. The members of the deacons quorum presidency and the secretary may not be set apart until after they have been accepted by the common consent of the members of the quorum.

The duties of a deacon are to assist the teachers in taking care of the temporal needs of the church, and "to warn, expound, exhort, and teach, and invite all to come unto Christ". In modern practice, one of the deacons' primary duties is to pass the sacrament to the members of the congregation during sacrament meeting. Deacons also may receive fast offerings from the members of their ward on fast Sunday. A deacon may often sit beside the bishopric during sacrament meeting to act as a messenger or assistant to the bishop.

An adult advisor may be called to assist the deacon's quorum. Sometimes an assistant advisor is called.

title: Aaronic priesthood (Latter Day Saints)


text:
Daisy Dee

Desiree Rollocks (born 4 September 1970), better known by her stage name Daisy Dee, is a Dutch singer, actress, TV host, stylist, and television producer. She is well known in German-speaking media. Daisy Dee hosted the German television show Clubrotation on Viva/MTV until 2003.

title: Daisy Dee


text:
Talk:Henry David Thoreau

The Thoreau family and the Sewall family
On June 17, 1839, according to The Walden.org log of 1839:

"Edmund Sewall arrives in Concord with his mother to visit his grandmother, the Thoreaus’ boarder, Mrs. Joseph Ward. Over the next several days, Thoreau takes him sailing on the Concord River, hiking to the Cliffs, and to Walden Pond (The Days of Henry David Thoreau, 77)."

It is weird synth for the article to describe the five days eleven-year-old Edmund Sewall stayed with Thoreau's family as five days of hiking for Sewall with HDT. In fact, young Sewall wrote his own extended account of his five days of exploring Concord with John Thoreau as well as with HDT--and his journal of those days can be read online.

The "Sexuality" section of this article should say more about Thoreau's relationships with women. Until I fixed it myself, it did not even mention his proposal of marriage to Edmund's sister. It still doesn't mention his proposal from Sophia Ford. Louisa May Alcott who took walks in the woods with Thoreau when she was a teenager, modeled romantic heroes in several of her books on Thoreau, although there's no evidence he returned her feelings at all. Here's to an NPOV and accurate-as-we-can-make it "Sexuality" section. HouseOfChange (talk) 19:11, 22 December 2021 (UTC)

 * Yes! The lack of evidence for the claims and selective presentation is weird to me. It’s like someone is trying to intentionally create a narrative about him. Is there a way to make it more reflective of what is known? His siblings didn’t marry either and I think it should be in the section too. 107.161.47.185 (talk) 05:37, 26 January 2024 (UTC)

Plumbago and electrotyping
"Later, Thoreau converted the pencil factory to produce plumbago, a name for graphite at the time, which was used in the electrotyping process.[47]"

The Conrad article cited in support of this statement does not support it. The author places the Thoreaus' highly refined grinding process in the 1830's and electrotyping was not invented until the 1840's so that was not the motivation. Conrad does not give any evidence that the Thoreaus supplied graphite to anyone doing electrotyping. Tpmpmurphy (talk) 14:55, 30 March 2024 (UTC)

Libertarianism and anarchy banners too dominant
Banners for libertarianism and anarchism dominate the appearance of this article. Yet Thoreau was neither a libertarian nor an anarchist.

And I just reverted a new effort to add yet another similar piece of promotionalism, a new anarchism footer. I do not believe these modern movements should get so much free advertising on the page of a writer who may have inspired them but whose ideas are not central to either cause. HouseOfChange (talk) 07:04, 13 June 2024 (UTC)

title: Talk:Henry David Thoreau


text:
Rinkai Line

The Rinkai Line (りんかい線) is a railway line in Tokyo, Japan. It is the only line operated by the third-sector company Tokyo Waterfront Area Rapid Transit. It connects central Tokyo to the artificial islands of Aomi and Odaiba. The line is served by some trains on the East Japan Railway Company (JR East) Saikyō Line which continue on to Shinjuku, Ikebukuro, Ōmiya, and Kawagoe.

Overview
While not part of the Tokyo subway network (as it was built to JR specifications), the Rinkai Line is fully grade separated and runs underground for nearly 10 km of its 12.2 km distance, going as low as 40 m below the ground when crossing under the Port of Tokyo. The Shinonome – Shin-Kiba segment (which uses the former Keiyō Freight Line) is elevated.

Station list
All stations are located in Tokyo. All trains stop at every station on the line.

Rolling stock

 * TWR 70-000 series 10-car EMUs (since 1996)
 * JR East E233-7000 series 10-car EMUs (since 30 June 2013)

The TWR 70-000 series electric multiple unit (EMU) trains are based at Yashio Depot, which is accessed via a spur located between Tennōzu Isle Station and Tokyo Teleport Station (the spur track also provides access to Tokyo Freight Terminal), while the E233 series trains are based at Kawagoe Depot.

The first of a fleet of 31 new 10-car E233-7000 series sets were introduced on Saikyō Line, Kawagoe Line, and Rinkai Line services between Kawagoe and Shin-Kiba from 30 June 2013, displacing the fleet of 205 series EMUs.

A new train type will be introduced in 2024, replacing the 70-000 series. The new type was revealed to be designated as 71-000 series on 6 November 2023. The revised entry into service is scheduled to take place in the middle of 2025 rather than 2024.

Former rolling stock

 * JR East 205 series 10-car EMUs (2002–2016)

History
Construction of the line started in 1992, with the eastern end of the line using the right-of-way of the Keiyō Freight Line (abandoned in 1983). The first portion of the line between Shin-Kiba and Tokyo Teleport opened for service on March 30, 1996, initially under the name Rinkai Fukutoshin Line (臨海副都心線). The name was officially changed to the Rinkai Line on September 1, 2000. The extension to Tennōzu Isle opened on March 31, 2001, and the final portion to Osaki on December 1, 2002.

The project ran severely over budget, with an estimated final cost of over ¥440 billion. In 2005, the Rinkai Line's average ridership was 140,000 passengers per day and, in 2006, the line finally registered its first operational profit, although interest payments on ¥389 billion yen in debt have resulted in a consistent net loss since 1991. By comparison, the competing elevated Yurikamome line is profitable, thanks to lower construction expenses, higher ticket prices and popularity among tourists and leisure visitors for its scenic views.

However, the Rinkai Line's ridership has steadily increased since, reaching 200,200 passengers per day in 2010. The ridership is forecast to increase further due to future development planned for the area served by the line.

Station numbering was introduced to all Rinkai Line stations in 2016 with stations being assigned station numbers R01 (Shin-Kiba) and R08 (Osaki).

Operating company
Tokyo Waterfront Area Rapid Transit, Inc. (東京臨海高速鉄道株式会社) was founded on March 12, 1991, for the express purpose of constructing and operating the railway line. It is a third-sector company, and, as of 1 April 2013, 91.32% of shares are held by the Tokyo Metropolitan Government, 2.41% by JR East, 1.77% by Shinagawa Ward, 0.70% by Mizuho Bank, 0.46% by MUFG Bank, 0.34% by Sumitomo Mitsui Banking Corporation, and the remaining 3% by 41 other companies.

In spite of its severe financial situation, TWR was discovered to have made a five million yen donation to the Tokyo Metropolitan Government on October 16, 2009, to encourage the city's bid for the 2016 Olympic Games. The company stood to benefit financially if the games were held in Tokyo, as several of the proposed venues were located along the Rinkai Line.

In addition to its ownership and operation of the Rinkai Line, TWR is also involved in real estate and subcontracting/management of station- and building-related design.

Future plans
In August 2014, it was revealed that JR East was in negotiations to buy out the Rinkai Line. This would make it easier to incorporate the line into its plans for a direct line to Haneda Airport as well as providing through services to and from the Keiyo Line.

title: Rinkai Line