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JTAG

JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs of and testing printed circuit boards after manufacture.

JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation. It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses. The interface connects to an on-chip Test Access Port (TAP) that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts.

The Joint Test Action Group formed in 1985 to develop a method of verifying designs and testing printed circuit boards after manufacture. In 1990 the Institute of Electrical and Electronics Engineers codified the results of the effort in IEEE Standard 1149.1-1990, entitled Standard Test Access Port and Boundary-Scan Architecture.

The JTAG standards have been extended by many semiconductor chip manufacturers with specialized variants to provide vendor-specific features.

History
In the 1980s, multi-layer circuit boards and integrated circuits (ICs) using ball grid array and similar mounting technologies were becoming standard, and connections were being made between ICs that were not available to probes. The majority of manufacturing and field faults in circuit boards were due to poor solder joints on the boards, imperfections among board connections, or the bonds and bond wires from IC pads to pin lead frames. The Joint Test Action Group (JTAG) was formed in 1985 to provide a pins-out view from one IC pad to another so these faults could be discovered.

The industry standard became an IEEE standard in 1990 as IEEE Std. 1149.1-1990 after many years of initial use. In the same year, Intel released their first processor with JTAG (the 80486) which led to quicker industry adoption by all manufacturers. In 1994, a supplement that contains a description of the boundary scan description language (BSDL) was added. Further refinements regarding the use of all-zeros for EXTEST, separating the use of SAMPLE from PRELOAD and better implementation for OBSERVE_ONLY cells were made and released in 2001. Since 1990, this standard has been adopted by electronics companies around the world. Boundary scan is now mostly synonymous with JTAG, but JTAG has essential uses beyond such manufacturing applications. The 2013 revision of IEEE Std. 1149.1 has introduced a vast set of optional features, associated extensions to BSDL, and a new procedural description language (PDL) based on Tcl.

Debugging
Although JTAG's early applications targeted board level testing, here the JTAG standard was designed to assist with device, board, and system testing, diagnosis, and fault isolation. Today JTAG is used as the primary means of accessing sub-blocks of integrated circuits, making it an essential mechanism for debugging embedded systems which might not have any other debug-capable communications channel. On most systems, JTAG-based debugging is available from the very first instruction after CPU reset, letting it assist with development of early boot software which runs before anything is set up. An in-circuit emulator (or, more correctly, a "JTAG adapter") uses JTAG as the transport mechanism to access on-chip debug modules inside the target CPU. Those modules let software developers debug the software of an embedded system directly at the machine instruction level when needed, or (more typically) in terms of high level language source code.

System software debug support is for many software developers the main reason to be interested in JTAG. Many silicon architectures such as PowerPC, MIPS, ARM, and x86 built an entire software debug, instruction tracing, and data tracing infrastructure around the basic JTAG protocol. Frequently individual silicon vendors however only implement parts of these extensions. Some examples are ARM CoreSight and Nexus as well as Intel's BTS (Branch Trace Storage), LBR (Last Branch Record), and IPT (Intel Processor Trace) implementations. There are many other such silicon vendor-specific extensions that may not be documented except under NDA. The adoption of the JTAG standard helped move JTAG-centric debugging environments away from early processor-specific designs. Processors can normally be halted, single stepped, or let run freely. One can set code breakpoints, both for code in RAM (often using a special machine instruction e.g. INT3) and in ROM/flash. Data breakpoints are often available, as is bulk data download to RAM. Most designs have "halt mode debugging", but some allow debuggers to access registers and data buses without needing to halt the core being debugged. Some toolchains can use ARM Embedded Trace Macrocell (ETM) modules, or equivalent implementations in other architectures to trigger debugger (or tracing) activity on complex hardware events, like a logic analyzer programmed to ignore the first seven accesses to a register from one particular subroutine.

Sometimes FPGA developers also use JTAG to develop debugging tools. The same JTAG techniques used to debug software running inside a CPU can help debug other digital design blocks inside an FPGA. For example, custom JTAG instructions can be provided to allow reading registers built from arbitrary sets of signals inside the FPGA, providing visibility for behaviors which are invisible to boundary scan operations. Similarly, writing such registers could provide controllability which is not otherwise available.

Storing firmware
JTAG allows device programmer hardware to transfer data into internal non-volatile device memory (e.g. CPLDs). Some device programmers serve a double purpose for programming as well as debugging the device. In the case of FPGAs, volatile memory devices can also be programmed via the JTAG port, normally during development work. In addition, internal monitoring capabilities (temperature, voltage and current) may be accessible via the JTAG port.

JTAG programmers are also used to write software and data into flash memory. This is usually done using the same data bus access the CPU would use, and is sometimes handled by the CPU. In other cases the memory chips themselves have JTAG interfaces. Some modern debug architectures provide internal and external bus master access without needing to halt and take over a CPU. In the worst case, it is usually possible to drive external bus signals using the boundary scan facility.

As a practical matter, when developing an embedded system, emulating the instruction store is the fastest way to implement the "debug cycle" (edit, compile, download, test, and debug). This is because the in-circuit emulator simulating an instruction store can be updated very quickly from the development host via, say, USB. Using a serial UART port and bootloader to upload firmware to Flash makes this debug cycle quite slow and possibly expensive in terms of tools; installing firmware into Flash (or SRAM instead of Flash) via JTAG is an intermediate solution between these extremes.

Boundary scan testing
JTAG boundary scan technology provides access to many logic signals of a complex integrated circuit, including the device pins. The signals are represented in the boundary scan register (BSR) accessible via the TAP. This permits testing as well as controlling the states of the signals for testing and debugging. Therefore, both software and hardware (manufacturing) faults may be located and an operating device may be monitored.

When combined with built-in self-test (BIST), the JTAG scan chain enables a low overhead, embedded solution to test an IC for certain static faults (shorts, opens, and logic errors). The scan chain mechanism does not generally help diagnose or test for timing, temperature or other dynamic operational errors that may occur. Test cases are often provided in standardized formats such as SVF, or its binary sibling XSVF, and used in production tests. The ability to perform such testing on finished boards is an essential part of Design For Test in today's products, increasing the number of faults that can be found before products ship to customers.

Electrical characteristics
A JTAG interface is a special interface added to a chip. Depending on the version of JTAG, two, four, or five pins are added. The four and five pin interfaces are designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met. The two pin interface is designed so that multiple chips can be connected in a star topology. In either case a test probe need only connect to a single "JTAG port" to have access to all chips on a circuit board.

Daisy-chained JTAG (IEEE 1149.1)

The connector pins are:

 * 1) TDI (Test Data In)
 * 2) TDO (Test Data Out)
 * 3) TCK (Test Clock)
 * 4) TMS (Test Mode Select)
 * 5) TRST (Test Reset) optional.

The TRST pin is an optional active-low reset to the test logic, usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by switching to the reset state synchronously, using TCK and TMS. Note that resetting test logic doesn't necessarily imply resetting anything else. There are generally some processor-specific JTAG operations which can reset all or part of the chip being debugged.

Since only one data line is available, the protocol is serial. The clock input is at the TCK pin. One bit of data is transferred in from TDI, and out to TDO per TCK rising clock edge. Different instructions can be loaded. Instructions for typical ICs might read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips).

As with any clocked signal, data presented to TDI must be valid for some chip-specific Setup time before and Hold time after the relevant (here, rising) clock edge. TDO data is valid for some chip-specific time after the falling edge of TCK.

The maximum operating frequency of TCK varies depending on all chips in the chain (the lowest speed must be used), but it is typically 10-100 MHz (100-10 ns per bit). Also TCK frequencies depend on board layout and JTAG adapter capabilities and state. One chip might have a 40 MHz JTAG clock, but only if it is using a 200 MHz clock for non-JTAG operations; and it might need to use a much slower clock when it is in a low power mode. Accordingly, some JTAG adapters have adaptive clocking using an RTCK (Return TCK) signal. Faster TCK frequencies are most useful when JTAG is used to transfer much data, such as when storing a program executable into flash memory.

Clocking changes on TMS steps through a standardized JTAG state machine. The JTAG state machine can reset, access an instruction register, or access data selected by the instruction register.

JTAG platforms often add signals to the handful defined by the IEEE 1149.1 specification. A System Reset (SRST) signal is quite common, letting debuggers reset the whole system, not just the parts with JTAG support. Sometimes there are event signals used to trigger activity by the host or by the device being monitored through JTAG; or, perhaps, additional control lines.

Even though few consumer products provide an explicit JTAG port connector, the connections are often available on the printed circuit board as a remnant from development prototyping and/or production. When exploited, these connections often provide the most viable means for reverse engineering.

Reduced pin count JTAG (IEEE 1149.7)

Reduced pin count JTAG uses only two wires, a clock wire and a data wire. This is defined as part of the IEEE 1149.7 standard. The connector pins are:

 * 1) TMSC (Test Serial Data)
 * 2) TCK (Test Clock)

It is called cJTAG for compact JTAG.

The two wire interface reduced pressure on the number of pins, and devices can be connected in a star topology. The star topology enables some parts of the system to be powered down, while others can still be accessed over JTAG; a daisy chain requires all JTAG interfaces to be powered. Other two-wire interfaces exist, such as Serial Wire Debug.

Communications model
In JTAG, devices expose one or more test access ports (TAPs). The picture above shows three TAPs, which might be individual chips or might be modules inside one chip. A daisy chain of TAPs is called a scan chain, or (loosely) a target. Scan chains can be arbitrarily long, but in practice twenty TAPs is unusually long.

To use JTAG, a host is connected to the target's JTAG signals (TMS, TCK, TDI, TDO, etc.) through some kind of JTAG adapter, which may need to handle issues like level shifting and galvanic isolation. The adapter connects to the host using some interface such as USB, PCI, Ethernet, and so forth.

Primitives
The host communicates with the TAPs by manipulating TMS and TDI in conjunction with TCK, and reading results through TDO (which is the only standard host-side input). TMS/TDI/TCK output transitions create the basic JTAG communication primitive on which higher layer protocols build:

 * State switching ... All TAPs are in the same state, and that state changes on TCK transitions. This JTAG state machine is part of the JTAG spec, and includes sixteen states. There are six "stable states" where keeping TMS stable prevents the state from changing. In all other states, TCK always changes that state. In addition, asserting TRST forces entry to one of those stable states (Test_Logic_Reset), in a slightly quicker way than the alternative of holding TMS high and cycling TCK five times.
 * Shifting ... Most parts of the JTAG state machine support two stable states used to transfer data. Each TAP has an instruction register (IR) and a data register (DR). The size of those registers varies between TAPs, and those registers are combined through TDI and TDO to form a large shift register. (The size of the DR is a function of the value in that TAP's current IR, and possibly of the value specified by a SCAN_N instruction.) There are three operations defined on that shift register:
 * Capturing a temporary value
 * Entry to the Shift_IR stable state goes via the Capture_IR state, loading the shift register with a partially fixed value (not the current instruction)
 * Entry to the Shift_DR stable state goes via the Capture_DR state, loading the value of the Data Register specified by the TAP's current IR.
 * Shifting that value bit-by-bit, in either the Shift_IR or Shift_DR stable state; TCK transitions shift the shift register one bit, from TDI towards TDO, exactly like a SPI mode 1 data transfer through a daisy chain of devices (with TMS=0 acting like the chip select signal, TDI as MOSI, etc.).
 * Updating IR or DR from the temporary value shifted in, on transition through the Update_IR or Update_DR state. Note that it is not possible to read (capture) a register without writing (updating) it, and vice versa. A common idiom adds flag bits to say whether the update should have side effects, or whether the hardware is ready to execute such side effects.
 * Running ... One stable state is called Run_Test/Idle. The distinction is TAP-specific. Clocking TCK in the Idle state has no particular side effects, but clocking it in the Run_Test state may change system state. For example, some ARM9 cores support a debugging mode where TCK cycles in the Run_Test state drive the instruction pipeline.

At a basic level, using JTAG involves reading and writing instructions and their associated data registers; and sometimes involves running a number of test cycles. Behind those registers is hardware that is not specified by JTAG, and which has its own states that is affected by JTAG activities.

Most JTAG hosts use the shortest path between two states, perhaps constrained by quirks of the adapter. (For example, one adapter only handles paths whose lengths are multiples of seven bits.) Some layers built on top of JTAG monitor the state transitions, and use uncommon paths to trigger higher level operations. Some ARM cores use such sequences to enter and exit a two-wire (non-JTAG) SWD mode. A Zero Bit Scan (ZBS) sequence is used in IEEE 1149.7 to access advanced functionality such as switching TAPs into and out of scan chains, power management, and a different two-wire mode.

JTAG IEEE Std 1149.1 (boundary scan) instructions
Instruction register sizes tend to be small, perhaps four or seven bits wide. Except for BYPASS and EXTEST, all instruction opcodes are defined by the TAP implementer, as are their associated data registers; undefined instruction codes should not be used. Two key instructions are:

 * The BYPASS instruction, an opcode of all ones regardless of the TAP's instruction register size, must be supported by all TAPs. The instruction selects a single bit data register (also called BYPASS). The instruction allows this device to be bypassed (do nothing) while other devices in the scan path are exercised.
 * The optional IDCODE instruction, with an implementer-defined opcode. IDCODE is associated with a 32-bit register (IDCODE). Its data uses a standardized format that includes a manufacturer code (derived from the JEDEC Standard Manufacturer's Identification Code standard, JEP-106), a part number assigned by the manufacturer, and a part version code. IDCODE is widely, but not universally, supported.

On exit from the RESET state, the instruction register is preloaded with either BYPASS or IDCODE. This allows JTAG hosts to identify the size and, at least partially, contents of the scan chain to which they are connected. (They can enter the RESET state then scan the Data Register until they read back the data they wrote. A BYPASS register has only a zero bit; while an IDCODE register is 32-bits and starts with a one. So the bits not written by the host can easily be mapped to TAPs.) Such identification is often used to sanity check manual configuration, since IDCODE is often unspecific. It could for example identify an ARM Cortex-M3 based microcontroller, without specifying the microcontroller vendor or model; or a particular FPGA, but not how it has been programmed.

A common idiom involves shifting BYPASS into the instruction registers of all TAPs except one, which receives some other instruction. That way all TAPs except one expose a single bit data register, and values can be selectively shifted into or out of that one TAP's data register without affecting any other TAP.

The IEEE 1149.1 (JTAG) standard describes a number of instructions to support boundary scan applications. Some of these instructions are "mandatory", but TAPs used for debug instead of boundary scan testing sometimes provide minimal or no support for these instructions. Those "mandatory" instructions operate on the Boundary Scan Register (BSR) defined in the BSDL file, and include:

 * EXTEST for external testing, such as using pins to probe board-level behaviors
 * PRELOAD loading pin output values before EXTEST (sometimes combined with SAMPLE)
 * SAMPLE reading pin values into the boundary scan register

IEEE-defined "Optional" instructions include:
 * CLAMP a variant of BYPASS which drives the output pins using the PRELOADed values
 * HIGHZ deactivates the outputs of all pins
 * INTEST for internal testing, such as using pins to probe on-chip behaviors
 * RUNBIST places the chip in a self-test mode
 * USERCODE returns a user-defined code, for example to identify which FPGA image is active

Devices may define more instructions, and those definitions should be part of a BSDL file provided by the manufacturer. They are often only marked as PRIVATE.

Boundary scan register
Devices communicate to the world via a set of input and output pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These registers are connected in a dedicated path around the device's boundary (hence the name). The path creates a virtual access capability that circumvents the normal inputs and outputs, providing direct control of the device and detailed visibility for signals.

The contents of the boundary scan register, including signal I/O capabilities, are usually described by the manufacturer using a part-specific BSDL file. These are used with design 'netlists' from CAD/EDA systems to develop tests used in board manufacturing. Commercial test systems often cost several thousand dollars for a complete system, and include diagnostic options to pinpoint faults such as open circuits and shorts. They may also offer schematic or layout viewers to depict the fault in a graphical manner.

To enable boundary scanning, IC vendors add logic to each of their devices, including scan cells for each of the signal pins. These cells are then connected together to form the boundary scan shift register (BSR), which is connected to a TAP controller. These designs are parts of most Verilog or VHDL libraries. Overhead for this additional logic is minimal, and generally is well worth the price to enable efficient testing at the board level.

Example: ARM11 debug TAP
An example helps show the operation of JTAG in real systems. The example here is the debug TAP of an ARM11 processor, the ARM1136 core. The processor itself has extensive JTAG capability, similar to what is found in other CPU cores, and it is integrated into chips with even more extensive capabilities accessed through JTAG.

This is a non-trivial example, which is representative of a significant cross section of JTAG-enabled systems. In addition, it shows how control mechanisms are built using JTAG's register read/write primitives, and how those combine to facilitate testing and debugging complex logic elements; CPUs are common, but FPGAs and ASICs include other complex elements which need to be debugged.

Licensees of this core integrate it into chips, usually combining it with other TAPs as well as numerous peripherals and memory. One of those other TAPs handles boundary scan testing for the whole chip; it is not supported by the debug TAP. Examples of such chips include:

 * The OMAP2420, which includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer TAP, a C55x DSP, and a TAP for an ARM7 TDMI-based imaging engine, with the boundary scan TAP ("ICEpick-B") having the ability to splice TAPs into and out of the JTAG scan chain.
 * The i.MX31 processor, which is similar, although its "System JTAG" boundary scan TAP, which is very different from ICEpick, and it includes a TAP for its DMA engine instead of a DSP and imaging engine.

Those processors are both intended for use in wireless handsets such as cell phones, which is part of the reason they include TAP controllers which modify the JTAG scan chain: Debugging low power operation requires accessing chips when they are largely powered off, and thus when not all TAPs are operational. That scan chain modification is one subject of a forthcoming IEEE 1149.7 standard.

JTAG facilities
This debug TAP exposes several standard instructions, and a few specifically designed for hardware-assisted debugging, where a software tool (the "debugger") uses JTAG to communicate with a system being debugged:

That model resembles the model used in other ARM cores. Non-ARM systems generally have similar capabilities, perhaps implemented using the Nexus protocols on top of JTAG, or other vendor-specific schemes.
 * and, standard instructions as described above
 * ,, standard instructions, but operating on the core instead of an external boundary scan chain.   is nominally for writing data to the core,   is nominally for reading it; but two scan chains are exceptions to that rule.
 * ARM instruction to select the numbered scan chain used with  or  . There are six scan chains:
 * - Device ID Register, 40 bits of read-only identification data
 * - Debug Status and Control Register (DSCR), 32 bits used to operate the debug facilities
 * - Instruction Transfer Register (ITR), 33 bits (32 instruction plus one status bit) used to execute processor instructions while in a special "Debug Mode" (see below)
 * - Debug Communications Channel (DCC), 34 bits (one long data word plus two status bits) used for bidirectional data transfer to the core. This is used both in debug mode, and possibly at runtime when talking to debugger-aware software.
 * - Embedded Trace Module (ETM), 40 bits (7 bit address, one 32-bit long data word, and a R/W bit) used to control the operation of a passive instruction and data trace mechanism. This feeds either an on-chip Embedded Trace Buffer (ETB), or an external high speed trace data collection pod. Tracing supports passive debugging (examining execution history) and profiling for performance tuning.
 * - debug module, 40 bits (7 bit address, one 32-bit long data word, and a R/W bit) used to access hardware breakpoints, watchpoints, and more. These can be written while the processor is running; it does not need to be in Debug Mode.
 * and, ARM11-specific instructions to halt and restart the CPU. Halting it puts the core into the "Debug Mode", where the ITR can be used to execute instructions, including using the DCC to transfer data between the debug (JTAG) host and the CPU.
 * , ARM11-specific instruction to accelerate some operations with ITR.

Older ARM7 and ARM9 cores include an EmbeddedICE module which combines most of those facilities, but has an awkward mechanism for instruction execution: the debugger must drive the CPU instruction pipeline, clock by clock, and directly access the data buses to read and write data to the CPU. The ARM11 uses the same model for trace support (ETM, ETB) as those older cores.

Newer ARM Cortex cores closely resemble this debug model, but build on a Debug Access Port (DAP) instead of direct CPU access. In this architecture (named CoreSight Technology), core and JTAG module is completely independent. They are also decoupled from JTAG so they can be hosted over ARM's two-wire SWD interface (see below) instead of just the six-wire JTAG interface. (ARM takes the four standard JTAG signals and adds the optional TRST, plus the RTCK signal used for adaptive clocking.) The CoreSight JTAG-DP is asynchronous to the core clocks, and does not implement RTCK. Also, the newer cores have updated trace support.

Halt mode debugging
One basic way to debug software is to present a single threaded model, where the debugger periodically stops execution of the program and examines its state as exposed by register contents and memory (including peripheral controller registers). When interesting program events approach, a person may want to single step instructions (or lines of source code) to watch how a particular misbehavior happens.

So for example a JTAG host might HALT the core, entering Debug Mode, and then read CPU registers using ITR and DCC. After saving processor state, it could write those registers with whatever values it needs, then execute arbitrary algorithms on the CPU, accessing memory and peripherals to help characterize the system state. After the debugger performs those operations, the state may be restored and execution continued using the RESTART instruction.

Debug mode is also entered asynchronously by the debug module triggering a watchpoint or breakpoint, or by issuing a BKPT (breakpoint) instruction from the software being debugged. When it is not being used for instruction tracing, the ETM can also trigger entry to debug mode; it supports complex triggers sensitive to state and history, as well as the simple address comparisons exposed by the debug module. Asynchronous transitions to debug mode are detected by polling the DSCR register. This is how single stepping is implemented: HALT the core, set a temporary breakpoint at the next instruction or next high-level statement, RESTART, poll DSCR until you detect asynchronous entry to debug state, remove that temporary breakpoint, repeat.

Monitor mode debugging
Modern software is often too complex to work well with such a single threaded model. For example, a processor used to control a motor (perhaps one driving a saw blade) may not be able to safely enter halt mode; it may need to continue handling interrupts to ensure physical safety of people and/or machinery. Issuing a HALT instruction using JTAG might be dangerous.

ARM processors support an alternative debug mode, called Monitor Mode, to work with such situations. (This is distinct from the Secure Monitor Mode implemented as part of security extensions on newer ARM cores; it manages debug operations, not security transitions.) In those cases, breakpoints and watchpoints trigger a special kind of hardware exception, transferring control to a "debug monitor" running as part of the system software. This monitor communicates with the debugger using the DCC, and could arrange for example to single step only a single process while other processes (and interrupt handlers) continue running.

Common extensions
Microprocessor vendors have often defined their own core-specific debugging extensions. Such vendors include Infineon, MIPS with EJTAG, and more. If the vendor does not adopt a standard (such as the ones used by ARM processors; or Nexus), they need to define their own solution. If they support boundary scan, they generally build debugging over JTAG.

Freescale has COP and OnCE (On-Chip Emulation). OnCE includes a JTAG command which makes a TAP enter a special mode where the IR holds OnCE debugging commands for operations such as single stepping, breakpointing, and accessing registers or memory. It also defines EOnCE (Enhanced On-Chip Emulation) presented as addressing real time concerns.

ARM has an extensive processor core debug architecture (CoreSight) that started with EmbeddedICE (a debug facility available on most ARM cores), and now includes many additional components such as an ETM (Embedded Trace Macrocell), with a high speed trace port, supporting multi-core and multithread tracing. Note that tracing is non-invasive; systems do not need to stop operating to be traced. (However, trace data is too voluminous to use JTAG as more than a trace control channel.)

Nexus defines a processor debug infrastructure which is largely vendor-independent. One of its hardware interfaces is JTAG. It also defines a high speed auxiliary port interface, used for tracing and more. Nexus is used with some newer platforms, such as the Atmel AVR32 and Freescale MPC5500 series processors.

Uses

 * Except for some of the very lowest end systems, essentially all embedded systems platforms have a JTAG port to support in-circuit debugging and firmware programming as well as for boundary scan testing:
 * ARM architecture processors come with JTAG support, sometimes supporting a two-wire "SWD" variant or high speed tracing of traffic on instruction or data busses.
 * Modern 8-bit and 16-bit microcontroller chips, such as Atmel AVR and TI MSP430 chips, support JTAG programming and debugging. However, the very smallest chips may not have enough pins to spare (and thus tend to rely on proprietary single-wire programming interfaces); if the pin count is over 32, there is probably a JTAG option.
 * Almost all FPGAs and CPLDs used today can be programmed via a JTAG port. A Standard Test and Programming Language is defined by JEDEC standard JESD-71 for JTAG programming of PLD's.
 * Many MIPS and PowerPC processors have JTAG support
 * Intel Core, Xeon, Atom, and Quark processors all support JTAG probe mode with Intel specific extensions of JTAG using the so-called 60-pin eXtended Debug Port [XDP]. Additionally the Quark processor supports more traditional 10-pin connectors.
 * Consumer products such as networking appliances and satellite television integrated receiver/decoders often use microprocessors which support JTAG, providing an alternate means to reload firmware if the existing bootloader has been corrupted in some manner.
 * The PCI bus connector standard contains optional JTAG signals on pins 1–5; PCI Express contains JTAG signals on pins 5–9. A special JTAG card can be used to reflash a corrupt BIOS.
 * Boundary scan testing and in-system (device) programming applications are sometimes programmed using the Serial Vector Format, a textual representation of JTAG operations using a simple syntax. Other programming formats include 'JAM' and STAPL plus more recently the IEEE Std. 1532 defined format 'ISC' (short for In-System Configuration). ISC format is used in conjunction with enhanced BSDL models for programmable logic devices (i.e. FPGAs and CPLDs) that include addition ISC_ instructions in addition to the basic bare minimum IEEE 1149.1 instructions. FPGA programming tools from Xilinx, Altera, Lattice, Cypress, Actel, etc. typically are able to export such files.
 * As mentioned, many boards include JTAG connectors, or just pads, to support manufacturing operations, where boundary scan testing helps verify board quality (identifying bad solder joints, etc.) and to initialize flash memory or FPGAs.
 * JTAG can also support field updates and troubleshooting.

Client support
The target's JTAG interface is accessed using some JTAG-enabled application and some JTAG adapter hardware. There is a wide range of such hardware, optimized for purposes such as production testing, debugging high speed systems, low cost microcontroller development, and so on. In the same way, the software used to drive such hardware can be quite varied. Software developers mostly use JTAG for debugging and updating firmware.

Connectors

There are no official standards for JTAG adapter physical connectors. Development boards usually include a header to support preferred development tools; in some cases they include multiple such headers, because they need to support multiple such tools. For example, a microcontroller, FPGA, and ARM application processor rarely share tools, so a development board using all of those components might have three or more headers. Production boards may omit the headers, or when space is limited may provide JTAG signal access using test points.

Some common pinouts for 2.54 mm pin headers are:

 * ARM 2×10 pin (or sometimes the older 2×7), used by almost all ARM based systems
 * MIPS EJTAG (2×7 pin) used for MIPS based systems
 * 2×5 pin Altera ByteBlaster-compatible JTAG extended by many vendors
 * 2×5 pin AVR extends Altera JTAG with SRST (and in some cases TRST and an event output)
 * 2×7 pin Texas Instruments used with DSPs and ARM-based products such as OMAP
 * 8 pin (single row) generic PLD JTAG compatible with many Lattice ispDOWNLOAD cables
 * MIPI10-/20-connectors (1.27 mm 050") for JTAG, cJTAG and SWD

Those connectors tend to include more than just the four standardized signals (TMS, TCK, TDI, TDO). Usually reset signals are provided, one or both of TRST (TAP reset) and SRST (system reset). The connector usually provides the board-under-test's logic supply voltage so that the JTAG adapters use the appropriate logic levels. The board voltage may also serve as a "board present" debugger input. Other event input or output signals may be provided, or general purpose I/O (GPIO) lines, to support more complex debugging architectures.

Higher end products frequently use dense connectors (frequently 38-pin MICTOR connectors) to support high-speed tracing in conjunction with JTAG operations. A recent trend is to have development boards integrate a USB interface to JTAG, where a second channel is used for a serial port. (Smaller boards can also be powered through USB. Since modern PCs tend to omit serial ports, such integrated debug links can significantly reduce clutter for developers.) Production boards often rely on bed-of-nails connections to test points for testing and programming.

Adapter hardware
Adapter hardware varies widely. When not integrated into a development board, it involves a short cable to attach to a JTAG connector on the target board; a connection to the debugging host, such as a USB, PCI, or Ethernet link; and enough electronics to adapt the two communications domains (and sometimes provide galvanic isolation). A separate power supply may be needed. There are both "dumb" adapters, where the host decides and performs all JTAG operations; and "smart" ones, where some of that work is performed inside the adapter, often driven by a microcontroller. The "smart" adapters eliminate link latencies for operation sequences that may involve polling for status changes between steps, and may accordingly offer higher throughput.

, adapters with a USB link from the host are the most common approach. Higher end products often support Ethernet, with the advantage that the debug host can be quite remote. Adapters which support high speed trace ports generally include several megabytes of trace buffer and provide high speed links (USB or Ethernet) to get that data to the host.

Parallel port adapters are simple and inexpensive, but they are relatively slow because they use the host CPU to change each bit ("bit banging"). They have declined in usefulness because most computers in recent years don't have a parallel port. Driver support is also a problem, because pin usage by adapters varied widely. Since the parallel port is based on 5V logic level, most adapters lacked voltage translation support for 3.3V or 1.8V target voltages.

RS-232 serial port adapters also exist, and are similarly declining in usefulness. They generally involve either slower bit banging than a parallel port, or a microcontroller translating some command protocol to JTAG operations. Such serial adapters are also not fast, but their command protocols could generally be reused on top of higher speed links.

With all JTAG adapters, software support is a basic concern. Many vendors do not publish the protocols used by their JTAG adapter hardware, limiting their customers to the tool chains supported by those vendors. This is a particular issue for "smart" adapters, some of which embed significant amounts of knowledge about how to interact with specific CPUs.

Software development
Most development environments for embedded software include JTAG support. There are, broadly speaking, three sources of such software:

 * Chip vendors may provide the tools, usually requiring a JTAG adapter they supply. Examples include FPGA vendors such as Xilinx and Altera, Atmel for its AVR8 and AVR32 product lines, and Texas Instruments for most of its DSP and micro products. Such tools tend to be highly featured, and may be the only real option for highly specialized chips like FPGAs and DSPs. Lower end software tools may be provided free of charge. The JTAG adapters themselves are not free, although sometimes they are bundled with development boards.
 * Tool vendors may supply them, usually in conjunction with multiple chip vendors to provide cross-platform development support. ARM-based products have a particularly rich third party market, and a number of those vendors have expanded to non-ARM platforms like MIPS and PowerPC. Tool vendors sometimes build products around free software like GCC and GDB, with GUI support frequently using Eclipse. JTAG adapters are sometimes sold along with support bundles.
 * Open source tools exist. As noted above, GCC and GDB form the core of a good toolchain, and there are GUI environments to support them.

All such software tends to include basic debugger support: stopping, halting, single stepping, breakpoints, data structure browsing, and so on. Commercial tools tend to provide tools like very accurate simulators and trace analysis, which are not currently available as open source.

Similar interface standards
Serial Wire Debug (SWD) is an alternative 2-pin electrical interface that uses the same protocol. It uses the existing GND connection. SWD uses an ARM CPU standard bi-directional wire protocol, defined in the ARM Debug Interface v5. This enables the debugger to become another AMBA bus master for access to system memory and peripheral or debug registers. Data rate is up to 4 MB/s at 50 MHz. SWD also has built-in error detection. On JTAG devices with SWD capability, the TMS and TCK are used as SWDIO and SWCLK signals, providing for dual-mode programmers.

title: JTAG


text:
William Birdwood

Field Marshal William Riddell Birdwood, 1st Baron Birdwood, (13 September 1865 – 17 May 1951) was a British Army officer. He saw active service in the Second Boer War on the staff of Lord Kitchener. He saw action again in the First World War as commander of the Australian and New Zealand Army Corps during the Gallipoli Campaign in 1915, leading the landings on the peninsula and then the evacuation later in the year, before becoming commander-in-chief of the Fifth Army on the Western Front during the closing stages of the war. He went on to be general officer commanding the Northern Army in India in 1920 and Commander-in-Chief, India, in 1925.

Early life
William Riddell Birdwood was born on 13 September 1865 in Kirkee, India. His father, Herbert Mills Birdwood, born in Bombay and educated in the UK, had returned to India in 1859 after passing the Indian Civil Service examination. In 1861, Herbert Birdwood married Edith Marion Sidonie, the eldest daughter of Surgeon-Major Elijah George Halhed Impey of the Bombay Horse Artillery and postmaster-general of the Bombay Presidency. They had five sons and a daughter; William was their second son. At the time of William's birth, his father held positions in the Bombay legislative council, and went on to become a Bombay high court judge. William Birdwood was educated at Clifton College.

Military career
After securing a militia commission in the 4th Battalion Royal Scots Fusiliers in 1883, Birdwood trained at the Royal Military College, Sandhurst, from which he was commissioned early, owing to the Russian war scare of 1885, becoming a lieutenant in the 12th (Prince of Wales's) Royal Lancers on 9 May 1885. He joined his regiment in India and then transferred from the 12th Royal Lancers to the Bengal Staff Corps on 20 December 1886. He subsequently transferred to the 11th Bengal Lancers in 1887, seeing action on the North-West Frontier in 1891. He later became adjutant of the Viceroy's Bodyguard in 1893. He was promoted to captain on 9 May 1896 and saw action during the Tirah Campaign in 1897.

Birdwood served in the Second Boer War, initially as brigade-major with a mounted brigade in Natal from 10 January 1900 and then as Deputy-Assistant Adjutant-General on the staff of Lord Kitchener from 15 October 1900. Promoted to brevet major on 20 November 1901 and local lieutenant-colonel in October 1901, he became military secretary to Lord Kitchener on 5 June 1902, and followed him on his return to the United Kingdom on board the SS Orotava, which arrived in Southampton on 12 July 1902. He received a brevet promotion to lieutenant-colonel in the South African Honours list published on 26 June 1902. In a despatch from June 1902, Lord Kitchener wrote the following about his work in South Africa:
 * This young officer has held a difficult position as Assistant Adjutant-General, Mounted Troops, and responsible adviser as to the distribution of remounts. In carrying out these duties he has proved himself to possess exceptional ability, and he has shown, moreover, remarkable tact in dealing with and conciliating the various interests which he had to take into consideration.

When Kitchener went to India as commander-in-chief in November 1902, Birdwood joined him there as assistant military secretary and interpreter. He was promoted to the substantive rank of major on 9 May 1903 and appointed Military Secretary to Lord Kitchener with the rank of full colonel on 26 June 1905. Having been appointed an aide-de-camp to the King on 14 February 1906, he was given command of the Kohat Brigade on the North West Frontier in 1908 and promoted to temporary brigadier-general on 28 June 1909.

Promoted to the rank of major-general on 3 October 1911, Birdwood became quartermaster-general in India and a member of the Viceroy's Legislative Council in 1912 and then Secretary of the Indian Army Department in 1913.

Gallipoli
In November 1914 Birdwood was instructed by Kitchener to form an army corps from the Australian and New Zealand troops that were training in Egypt. He was promoted to temporary lieutenant-general on 12 December 1914 and given command of the Australian and New Zealand Army Corps. Kitchener instructed General Sir Ian Hamilton, Commander of the Mediterranean Expeditionary Force, to carry out an operation to capture the Gallipoli peninsula and placed Birdwood's ANZAC Corps under Hamilton's command. Hamilton ordered Birdwood to carry out a landing on 25 April 1915 north of Kabatepe at a site now known as ANZAC Cove. The ANZAC Corps encountered high ridges, narrow gullies, dense scrub and strong Ottoman resistance and became pinned down. Major-General William Bridges and Major-General Alexander Godley, the divisional commanders, were both of the view that the Allied forces, dealing with stiffer-than-expected resistance, should be evacuated ahead of an expected attack by the Ottoman Army. Nevertheless, Hamilton ordered them to hold fast.

Birdwood took effective command of the First Australian Imperial Force in May 1915 while still commanding Allied troops on the ground at Gallipoli. He launched a major attack on Ottoman positions in August 1915 (the Battle of Sari Bair) but failed to dislodge them from the peninsula. Notwithstanding this, Birdwood was the only corps commander opposed to abandoning Gallipoli. He was promoted to the permanent rank of lieutenant-general on 28 October 1915 and given command of the newly formed Dardanelles Army: the one outstanding success of the campaign was the evacuation led by Birdwood, which took place in December 1915 and January 1916, when the entire force was withdrawn before any Ottoman reaction.

Western Front

In February 1916 the Australian and New Zealand contingents, back in Egypt, underwent reorganisation to incorporate the new units and reinforcements that had accumulated during 1915: the Australian and New Zealand Army Corps was replaced by two corps, I ANZAC Corps and II ANZAC Corps, and Birdwood reverted to the command of II ANZAC Corps. When I ANZAC Corps became the first to depart for France, Birdwood, as senior corps commander, took over command. During early 1916 Birdwood advocated for the formation of an Australian and New Zealand Army or a Dominion Army also including Canadian forces under his command, but this did not occur.

Birdwood was promoted to the permanent rank of full general on 23 October 1917 with command of a formation then known as the Australian Corps in November 1917. He was also appointed aide-de-camp general to the King on 2 November 1917 and given command of the British Fifth Army on 31 May 1918 and led the Army at the liberation of Lille in October 1918 and at the liberation of Tournai in November 1918.

After the war
Birdwood was made a Baronet, of Anzac and of Totnes, in the County of Devon, on 29 December 1919. He toured Australia to great acclaim in 1920 and then became general officer commanding the Northern Army in India later that year. He was promoted to field marshal (with the corresponding honorary rank in the Australian Military Forces) on 20 March 1925 and, having been appointed a Member of the Executive Council of the Governor-General of India in July 1925, he went on to be Commander-in-Chief, India, in August 1925.

After leaving the service in 1930, Birdwood made a bid to become Governor-General of Australia. He had the backing of the King and the British government. However, the Australian Prime Minister James Scullin insisted that his Australian nominee Sir Isaac Isaacs be appointed. Instead, Birdwood was appointed Master of Peterhouse, Cambridge on 20 April 1931 and Captain of Deal Castle in 1934. In 1935 he wrote for the Western Australian distance education magazine Our Rural Magazine, saying that he had two granddaughters making good use of distance educational courses. In May 1936, he returned to Gallipoli aboard RMS Lancastria and visited war memorials on the peninsula. He retired from academic work in 1938.

In retirement Birdwood was Colonel of the 12th Royal Lancers (1920–1951), the 6th Gurkha Rifles (1926–1951), and the 75th (Home Counties) (Cinque Ports) Heavy Anti-Aircraft Regiment, Royal Artillery (1939–1951). In January 1936 he attended the funeral of King George V and in May 1937 he was present for the coronation of King George VI. He was raised to the peerage as Baron Birdwood, of Anzac and of Totnes in the County of Devon, on 25 January 1938, in recognition of his wartime service.

His autobiography Khaki and Gown (1941) was followed by In my time: recollections and anecdotes (1946). Lord Birdwood died at Hampton Court Palace, where he lived in grace-and-favour apartments, on 17 May 1951. He was buried at Twickenham Cemetery with full military honours; the Australian Government pays for the upkeep of his grave.

British

 * Knight Grand Cross of the Order of the Bath (GCB) – 1 January 1923 (KCB: 4 June 1917; CB: 19 June 1911 )
 * Knight Grand Commander of the Order of the Star of India (GCSI) – 1 January 1930 (KCSI: 1 January 1915; CSI: 1 January 1910 )
 * Knight Grand Cross of the Order of St Michael and St George (GCMG) – 1 January 1919 (KCMG: 3 June 1915 )
 * Knight Grand Cross of the Royal Victorian Order (GCVO) – 11 May 1937
 * Companion of the Order of the Indian Empire (CIE) – 1 January 1908
 * Companion of the Distinguished Service Order (DSO) – 14 August 1908
 * Knight of Grace of the Venerable Order of St. John (KStJ) – 21 June 1927

Foreign

 * Croix de Guerre (France), 22 February 1916 and 11 March 1919 (with Palm)
 * Grand Officer of the Order of the Crown (Belgium) – 2 November 1916
 * Croix de Guerre (Belgium) – 11 March 1918
 * Distinguished Service Medal (United States) – 12 July 1919
 * Grand Cross of the Order of the Tower and Sword (Portugal) – 21 August 1919
 * Grand Cordon of the Order of the Rising Sun (Japan) – 21 January 1921

Family
In 1893 Birdwood married Janetta Bromhead, daughter of Sir Benjamin Bromhead; they had a son and two daughters. His wife died in 1947. Their son, Christopher Birdwood (1899–1962), succeeded him as 2nd Baron Birdwood. The elder daughter was Constance 'Nancy' Birdwood, and the younger daughter was Judith Birdwood. Other members of the Birdwood family include Labour minister and peer Christopher Birdwood Thomson (1875–1930), Anglo-Indian naturalist Sir George Birdwood (1832–1917), and Jane Birdwood (1913–2000), the second wife of William Birdwood's son.

Legacy
The town of Blumberg, South Australia, changed its German name to Birdwood in 1918, and the soldier settlement of Birdwoodton, Victoria was named after Birdwood in 1920. Mount Birdwood in Alberta, Canada also bears his name.

Birdwood House in Geraldton, Western Australia, which was built in 1935 for the Geraldton RSL and named after Birdwood, has served as the centre of ANZAC Day commemorations in Geraldton since 1936. William Birdwood visited Birdwood House in Geraldton 1937 where he was presented with a gold key and Freedom of Birdwood House. Birdwood House became Heritage Registered in 2016.

Many streets and public spaces in Australia and New Zealand are named or commonly believed to be named after Birdwood, including Birdwood Park in Newcastle West in 1920 and a street in New Lambton in 1919.

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: William Birdwood


text:
Talk:Tragopogon porrifolius

Untitled
System logged me off before I filed up. the original version of this page was by me. seglea 06:58, 6 May 2004 (UTC)

WikiProject Food and drink Tagging
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Secondary Metabolites
The first statement is not a sentance and I don't know what it means. This paragraph is yet another example of Wikipedia going up its own a... Can this please be rewritten so that the majority of humanity can learn something from it. "The following chemicals can be..." maybe? IceDragon64 (talk) 21:24, 4 June 2017 (UTC)
 * I removed the section. It's not appropriate for a general encyclopedia, like Wikipedia. Peter coxhead (talk) 06:18, 5 June 2017 (UTC)

External links modified
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title: Talk:Tragopogon porrifolius


text:
Sarcophilus laniarius

Sarcophilus laniarius is an extinct species of large Tasmanian devil. Richard Owen originally called the specimen on which the genus was based Dasyurus laniarus.

Pleistocene fossil deposits in limestone caves at Naracoorte, South Australia include specimens of S. laniarius, which were around 15% larger and 50% heavier than modern devils. Older specimens believed to be 50–70,000 years old were found in Darling Downs in Queensland and in Western Australia. It is not clear whether the modern devil evolved from S. laniarius, or whether they coexisted at the time. Richard Owen argued for the latter hypothesis in the 19th century based on fossils found in 1877 in New South Wales. It has been conjectured that S. laniarius and S. moornaensis, another now-extinct larger species, may have hunted and scavenged. It is known that there were several genera and species of thylacine millions of years ago, and that they ranged in size, the smaller being more reliant on foraging. As the devil and thylacine are similar, the extinction of the co-existing thylacine species has been cited as evidence for an analogous history for the devils. It has been speculated that the smaller size of S. laniarius and S. moornaensis allowed them to adapt to the changing conditions more effectively and survive longer than the corresponding thylacines.

As the extinction of these two species came at a similar time to human habitation of Australia, hunting by humans, as well as land clearing, have been mooted as possible causes. Critics of this theory point out that as indigenous Australians only developed boomerangs and spears for hunting around 10,000 years ago, a critical fall in numbers due to systemic hunting is unlikely. They also point out that caves inhabited by Aboriginal people have a low proportion of bones and rock paintings of devils, and that this is an indication that it was not a large part of indigenous lifestyle. A scientific report in 1910 claimed that Aboriginal people preferred the meat of herbivores rather than carnivores. The other main theory for the extinction was due to the climate change brought on by the most recent Ice Age.

title: Sarcophilus laniarius


text:
User:Patach

Patrick Cheng is an animator and a cartoonist.

Current works that you can see on the web are at http://www.cattrigger.com

and http://finaldraft.keenspace.com

Hope you enjoy.

title: User:Patach


text:
Tim Buck

Timothy Buck  (January 6, 1891 – March 11, 1973) was the general secretary of the Communist Party of Canada (known as the Labor-Progressive Party from 1943 to 1959) from 1929 until 1962. Together with Ernst Thälmann of Germany, Maurice Thorez of France, Palmiro Togliatti of Italy, Earl Browder of the United States, and Harry Pollitt of Great Britain, Buck was one of the top leaders of the Joseph Stalin-era Communist International.

Early life and career
A machinist by trade, Buck was born in Beccles, England, and emigrated to Canada in 1910 reputedly because it was cheaper to book steamship passage to Canada than to Australia. He became involved in the labour movement and joined the International Association of Machinists and radical working-class politics in Toronto. He claimed to have been present at the founding convention of the Communist Party of Canada, though this is disputed. Not initially a leading member of the party, Buck came to prominence as a supporter of Joseph Stalin, and became General Secretary in 1929, after the old party leadership had been purged for supporting Leon Trotsky, and others removed for supporting Bukharin. Buck remained General Secretary until 1962 and was a committed supporter of the Soviet line throughout his tenure.

National figure

In 1928, Buck was expelled from the International Association of Machinists for being a member of the Communist Party of Canada. With the onset of the Great Depression, the Conservative government of R. B. Bennett became increasingly worried about left-wing activity and agitation. On August 11, 1931, the Communist Party offices in Toronto were raided, and Buck and several of his colleagues were arrested and charged with sedition. Buck was tried in November, convicted of sedition and sentenced to hard labour.

He was imprisoned from 1932 to 1934 in Kingston Penitentiary where he was the target of an apparent assassination attempt in his cell the night after a prison riot. While Buck was sitting in his cell listening to the mêlée outside, eight shots were fired into his cell via a window, narrowly missing the prisoner. In late 1933, Minister of Justice Hugh Guthrie admitted in the House of Commons of Canada that shots had been deliberately fired into Buck's cell but "just to frighten him." A widespread civil rights campaign ultimately secured Buck's release. His extensive testimony before the Archambault Commission contributed to the reform of prisons in Canada. As a result, Buck was hailed a heroic champion of civil liberties.

The Communist Party was banned in 1941 under the Defence of Canada Regulations. Buck and other prominent communist leaders were forced underground and ultimately into exile in the United States because of their support for the pact between Germany and the Soviet Union, both of which invaded Poland at the start of the Second World War. Like supporters and immigrants from the Axis Powers, communists were suspected of collusion with Germany, and all who suspected of strongly supporting the alliance were interned under the War Measures Act. The political environment began to change only after German invaded the Soviet Union. The Soviet Union's entry into World War II on the side of the Allies caused Canadian communists to end their opposition to the war and apparently to become enthusiastic supporters of the Canadian war effort. The party supported the government's call for conscription and established Tim Buck Plebiscite Committees, which called for a "Yes" vote in the 1942 national plebiscite on conscription. The campaigning in support of the war helped change public opinion towards the communists and resulted in the government's release of communist leaders being held in detention and the return of Buck and other leaders from exile. The ban on the party itself was not lifted, but it was allowed to organize the Labor-Progressive Party as its legal public face.

Electoral politics
Buck ran for a seat in the House of Commons on five occasions and once for the Toronto city Board of Control, all unsuccessfully.

in the 1935 federal election, he ran in Winnipeg North and won 25% of the vote, placing third. He lost to Cooperative Commonwealth Federation (CCF) candidate Abraham Albert Heaps.

In the 1937 Toronto municipal election he came within 200 votes of winning a citywide election to the Toronto Board of Control.

He won 26% of the vote when he ran in the Toronto riding of Trinity in the 1945 election, and 21% in the 1949 election, finishing ahead of the CCF on both occasions.

In the 1953 election, he won only 8.7% of the vote and then just 3.7% of the vote when he stood one last time in the 1958 election.

Retirement and death
Buck retired as general secretary of the Communist Party of Canada in 1962 but remained in the largely ceremonial position of party chairman until his death in 1973. There was controversy within the party when a posthumous version of his memoirs was published in 1977 by NC Press based on interviews conducted for the CBC in 1965. In Yours in the Struggle: Reminiscences of Tim Buck, the former party leader criticized Nikita Khrushchev and was somewhat defensive of Stalin, although not departing from the international Communist movement's current perspective.

The main concerns of the party was the claim that the publishers were trying to frame Buck in a pro-Maoist manner, in regards to the Sino-Soviet Split where the party had sided with the Soviet Union, and that the loose recordings were in a position to be easily misinterpreted. Those within the Central Committee responsible for its publication were punished for "grave violation of democratic centralism". Earlier in 1975, Progress Books published Tim Buck — A Conscience for Canada by Oscar Ryan, which is considered to be the party-approved biography. In it, Buck was quoted as saying "for a time I gave the appearance of defending Stalin. I didn't defend what he had done; the fact is, nobody could defend the things that Khrushchev revealed."

Canadian Trotskyist Ian Angus also criticized Yours in Struggle with regards to accusations that Buck had stated misinformation with regards to the purging of alternate voices during his early rise in the party. He continued this criticism with his 1981 book Canadian Bolsheviks: The Early Years of the Communist Party of Canada, which analyzed the formation and rise of the party, but felt that Tim Buck had betrayed it by promoting himself and a strongly pro-Soviet line.

Buck died in Cuernavaca, Mexico, on March 11, 1973, at age 82.

title: Tim Buck


text:
Wikipedia:Articles for deletion/Reuder

No relevant google hits, which is odd for something claimed to be an "Internet term". --Delirium 07:06, May 6, 2004 (UTC)

 * Delete. Wikipedia is not a slang dictionary for little used Internet slang. Gwimpey 08:35, 6 May 2004 (UTC)
 * Redirect to Combat robot. Alcarillo 14:14, 6 May 2004 (UTC)

title: Wikipedia:Articles for deletion/Reuder


text:
Jim Rhodes

James Allen Rhodes (September 13, 1909 – March 4, 2001) was an American attorney and Republican politician who served as the 61st and 63rd Governor of Ohio from 1963 to 1971 and from 1975 to 1983. Rhodes was one of only seven U.S. governors to serve four four-year terms in office. Rhodes is tied for the sixth-longest gubernatorial tenure in post-Constitutional U.S. history at 5,840 days. He also served as Mayor of Columbus from 1944 to 1952 and Ohio State Auditor from 1953 to 1963.

On May 3, 1970, Rhodes sent National Guard troops onto the Kent State University campus at the request of Kent, Ohio mayor LeRoy Satrom after the ROTC building was burned down by unknown arsonists the previous night. On May 4, Guardsmen killed four students and wounded nine others.

Early life and education
Rhodes was born in Coalton, Ohio, to James and Susan Howe Rhodes, who were of Welsh descent. Rhodes has commented that the reason he and his family were Republicans was because of the respect his father, a mine superintendent, had for John L. Lewis, a prominent Republican union activist. When Rhodes was nine, his father died, and the family moved to north Springfield where Rhodes graduated from Springfield High School where he played on the football team. Subsequently, the family moved again, this time to Columbus, because Rhodes earned a modest basketball scholarship to Ohio State University. Although Rhodes dropped out after his first quarter he is often described as a "student" or "alumnus" of Ohio State.

After dropping out of college, Rhodes opened a business called Jim's Place across from the university on North High Street. Jim's Place has been described as a place where one could buy anything, from doughnuts and hamburgers to stag film, or place bets on numbers games.

Mayor of Columbus, 1944–1952
In 1934, Rhodes began to use his position as a local businessman to climb up the Columbus political ladder, starting on a ward committee. In 1937, Rhodes won his first elected office as a member of the Columbus Board of Education. He was then twice elected as Columbus city auditor in 1939 and 1941. Then in 1943, Rhodes was elected as Mayor of Columbus, becoming the youngest major city mayor in the U.S. at age 34.

Rhodes's time as mayor is primarily marked by two achievements, with the first being his convincing of 67% of Columbus voters to approve the city's first income tax, and the second being his successful use of water gun diplomacy to annex much of the surrounding suburbs to Columbus. As surrounding communities grew or were constructed, they came to require access to waterlines, which was under the sole control of the municipal water system. Rhodes told these communities that if they wanted water, they would have to submit to assimilation into Columbus. As a result of this, Columbus, Ohio, currently has the largest land area of any Ohio city.

Governor of Ohio
With an eye on the governorship, Rhodes was elected State Auditor in 1952, and took office in early 1953. In 1954, Rhodes ran against the popular incumbent, Democratic governor Frank Lausche, and lost by a 54% to 46% margin. In 1962, Rhodes ran again for governor – this time against Democratic incumbent Mike DiSalle. Rhodes's campaign centered on "jobs and progress," and in speeches Rhodes routinely claimed that an increase in jobs would lead to a decrease in everything from crime and divorce, to mental illness. Rhodes also made DiSalle's tax increases, such as the gas tax, a prominent part of his campaign. Rhodes also weathered a minor scandal when Democratic State Chairman alleged that Rhodes diverted and borrowed a total of $54,000 from his campaign funds. During a debate, both Rhodes and DiSalle agreed that this was, "the most vicious campaign [of] the Ohio governorship." On November 6, 1962, Ohioans voted Rhodes into the governorship with 59% of the vote.

Rhodes served two terms as governor, and he also was a "favorite son" presidential candidate who controlled the Ohio delegation to the Republican National Conventions in 1964 and 1968, before retiring in 1971. He ran for the U.S. Senate in 1970 and narrowly lost, to U.S. Representative Robert Taft Jr., in the primary election, which was two days after the events at Kent State.

Rhodes oversaw the last two (by electrocution) pre-Furman executions in Ohio, which were both in early 1963, before Ohio resumed executions in 1999. In 1983 Rhodes pardoned boxing promoter Don King for a 1967 non‐negligent manslaughter conviction of stomping one of his employees to death.

Rhodes championed a county airport program which, after being passed by voters in 1965, saw the construction of 50 airports throughout the state.

At a news conference in Kent, Ohio, on Sunday May 3, 1970, the day before the Kent State shootings, he said of campus protesters:

They're worse than the Brownshirts, and the Communist element, and also the Night Riders, and the vigilantes. They're the worst type of people that we harbor in America.

Since the Ohio Constitution limits the governor to two four-year terms, when Rhodes initially filed to run again in 1974, his petitions were refused by the Secretary of State. Rhodes sued, and the Ohio Supreme Court ruled that the limitation was on consecutive terms, thus freeing him to return to office by narrowly defeating incumbent John Gilligan in an upset in the 1974 election. He served two more terms before retiring again in 1983. During the energy crisis of the winter of 1976–77, Rhodes led a 15-minute service, in which he "beseech[ed] God to relieve the storm." The next year, January 1978, amid a blizzard which dropped 31 inches of snow onto Ohio and killed 60 people in the Northeast, Rhodes called the storm "the greatest disaster in Ohio history."

On August 16, 1977 Rhodes was hit in the face and shoulder with a banana cream pie thrown by Steve Conliff, as about 25 young people disrupted the opening of the Ohio State Fair. Conliff then ran unsuccessfully against Rhodes for the Republican nomination.

After relations between the United States and People's Republic of China normalized in 1979, Rhodes sought to encourage economic ties, viewing China as a potential market for Ohio machinery exports for companies like Timken Company and Parker Hannifin. In July 1979, Rhodes led a State of Ohio Trade Mission to China. Among other leaders, Rhodes met with Vice Premier Yu Qiuli. The trip resulted in developing economic ties, a sister state-province relationship with Hubei province, long-running Chinese exhibitions at the Ohio State Fair, and major academic exchanges between Ohio State University and Wuhan University. Rhodes also developed the view that Chinese investment in Ohio would be beneficial for the state.

Rhodes ran for the governorship again in 1986, seeking a record-breaking fifth term, but soundly lost to the incumbent Dick Celeste, whom Rhodes had narrowly defeated in his last successful gubernatorial bid in 1978.

Literary
Rhodes co-authored stories of historical fiction with Dean Jauchius, including The Trial of Mary Todd Lincoln, The Court-Martial of Oliver Hazard Perry and Johnny Shiloh, a novel of the Civil War. The last was adapted to a 1963 television movie by Walt Disney, also called Johnny Shiloh, for which Rhodes received writer's credit.

Personal life
From 1941 to her death in 1987, Rhodes was married to Helen Rawlins. They had three children.

In 1995, Rhodes suffered a stroke, resulting in him needing to use a wheelchair. He was hospitalized due to pneumonia in December 2000 and January 2001. On March 4, 2001, Rhodes died at Ohio State University Medical Center in Columbus of heart issues. He is interred at Green Lawn Cemetery, Columbus, Ohio.

Legacy
Numerous buildings and sites around the state have been named in Rhodes's honor, including:

 * The James A. Rhodes State Office Tower – the tallest building in Columbus
 * Statue in front of namesake office tower in Columbus
 * Cleveland State University's Rhodes Tower in Cleveland
 * The Ohio State University Medical Center's Rhodes Hall - the main building of University Hospital
 * The James A. Rhodes Arena (locally nicknamed as "The JAR") at the University of Akron
 * James A. Rhodes State College in Lima, Ohio.
 * The Rhodes Center at the Ohio Expo Center and State Fair in Columbus
 * The James A. Rhodes Appalachian Highway, Ohio State Route 32
 * The James A. Rhodes Athletic Center, Shawnee State University
 * James A. Rhodes Airport, in Jackson, Ohio

1962 election
Jim Rhodes won the gubernatorial election, defeating sitting Governor Michael DiSalle 58.92% to 41.08%.

1966 election
Jim Rhodes won a second term, defeating Frazier Reams Jr. 62.18% to 37.82%

1974 election
Jim Rhodes won a third term, defeating sitting Governor John J. Gilligan 48.62% to 48.25%.

1978 election
Jim Rhodes won a fourth term, defeating Dick Celeste 49.31% to 47.64%.

1986 election
Jim Rhodes sought a fifth term at the age of seventy-seven, losing to sitting Governor Dick Celeste 39.4% to 60.6%. This was his last campaign for Governor.

title: Jim Rhodes


text:
User:Azdak

 * personal: German Wikipedia - User since March, 22end 2004.
 * interests: Politics; Philosophy; Society; and a bunch of sporadic other.
 * location: Berlin - Neukölln

de:Benutzer:Azdak

title: User:Azdak


text:
Karnov

Karnov (カルノフ) is a platform game released in arcades in 1987. A Nintendo Entertainment System port followed. Players take control of the title character Jinborov Karnovski, or "Karnov" for short. Karnov is a strongman popularly illustrated as being from an unspecified part of the Soviet Union's Central Asian republics as shown on the arcade flyer and again in Karnov's Revenge.

As a character created by Data East, Karnov was reintroduced in several other games from the company, including Bad Dudes Vs. DragonNinja in which he is a boss in the first level. Karnov later appeared in the 1993 fighting game Fighter's History, in which Karnov is the final boss, and as a playable character in its sequel, Karnov's Revenge, also known as Fighter's History Dynamite.

Gameplay
The game puts the bulging-muscled, fire-breathing, east-Russian, ex-circus strongman hero on a quest through nine different levels to search for the ultimate treasure. However, between him and the treasure are several horrendous monsters, including sword-wielding monks, dinosaurs, djinn, hopping fish men, gargoyles, tree monsters, will-o-wisps, rock creatures, centipede women, and ostrich-riding skeleton warriors.

Karnov can walk, jump, and shoot to make his way through these levels and find special items that help him. Acquiring red orbs can upgrade Karnov until he shoots three fireballs at a time. The end of each level has one or more bosses which he must defeat to receive a new piece of a treasure map. The end of the game features a powerful boss called "The Wizard" who defends the last map piece that leads to the treasure.

Ports
Karnov was later ported to numerous home systems, such as the NES, Commodore 64, ZX Spectrum and others.

IBM PC
The IBM PC compatibles port was developed by Quicksilver Software. Like Quicksilver's other Data East ports, such as Commando, Ikari Warriors, and Guerrilla War, it was sold as a self-booting disk.

Famicom/NES
The Famicom version was co-developed by Data East (design and audio) and SAS Sakata (programming). It was released on December 18, 1987 in Japan by Namco, and shortly thereafter on its North American equivalent, the NES, in 1988 by Data East itself. Although it plays similarly to the arcade game there are some noticeable differences:

 * Karnov takes two hits to die instead of just one. After being hit once he will turn a blue color in which he has one hit left or can gain an extra hit back by grabbing a blue fireball orb.
 * The Super Fireball is replaced with the Spike Bomb which destroys every enemy on screen. The Trolley item is replaced with the Shield which is used to reflect an enemy's fireballs.
 * Levels 4 and 8 are completely different from the arcade levels.
 * The final boss is no longer the Wizard, but a giant three-headed dragon. Both fights, however, take place in similar rooms.

The Famicom game is noticeably more difficult since it has limited continues, and the option is not visibly present after all lives are lost, instead requiring pressing Select and Start at the same time. The NES game, however, provides unlimited continues, and it also allows Karnov to be killed when both the A and B buttons are pressed on the second controller.

Reception
In Japan, Game Machine listed Karnov on their March 1, 1987 issue as being the fourth most-successful table arcade unit of the month. Karnov's sales had surpassed 250,000 copies by November 1989.

Bill Kunkel reviewed the game for Computer Gaming World, calling it an off-beat variation on a familiar videogame play mechanic.

The IBM PC version of the game was reviewed in 1989 in Dragon #142 by Hartley, Patricia, and Kirk Lesser in "The Role of Computers" column. The reviewers gave the game 4½ out of 5 stars.

Legacy
Although no direct sequel to Karnov was released, Data East has used the title character as an enemy. In some games, such as Garyo Retsuden, Tumblepop and Trio The Punch - Never Forget Me... (featuring enormous stone statues and even mini versions of the character), Karnov is featured as a regular enemy.

In other Data East games, he is featured as a boss character. In Bad Dudes Vs. DragonNinja, Karnov is the first level's boss. A pale grey version of Karnov appears later in the game. According to the credits sequence of the Japanese version of the game, this version of Karnov is called Kusamochi Karnov, after the green sweet kusamochi.

Karnov is also the last opponent in the original Fighter's History, and becomes a playable character in its sequels: Karnov's Revenge and Fighter's History: Mizoguchi Kiki Ippatsu!!. Although not an official cameo, the guard boss from the Gaelco game, Big Karnak, is almost identical to Karnov's and Kusamoci Karnov's sprites from Bad Dudes vs. DragonNinja.

Karnov has also made various cameo appearances. He appears in the alley background of the Neo-Geo game Street Slam. He is shown wearing a shirt with a "K" on it. Karnov also appears in the credits of the independently-developed freeware game I Wanna Be the Guy. In Shantae and the Pirate's Curse, a ghostly silhouette who helps the titular character is highly similar to Karnov, and is even implied to be her long-lost father.

title: Karnov


text:
Miguel León-Portilla

Miguel León-Portilla (22 February 1926 – 1 October 2019) was a Mexican anthropologist and historian, specializing in Aztec culture and literature of the pre-Columbian and colonial eras. Many of his works were translated to English and he was a well-recognized scholar internationally. In 2013, the Library of Congress of the United States bestowed on him the Living Legend Award.

Early life and education
Born in Mexico City, Miguel León-Portilla had an interest in indigenous Mexico from an early age, fostered by his uncle Manuel Gamio, a distinguished archeologist. Gamio had a lasting influence on his life and career, initially taking him as a boy on trips to important archeological sites in Mexico and later as well. León-Portilla attended the Instituto de Ciencias in Guadalajara and then earned a B.A. (1948) and M.A. summa cum laude (1951) at the Jesuit Loyola University in Los Angeles. Returning to Mexico in 1952, he showed Gamio a play he had written on Quetzalcoatl, which resulted in Gamio introducing his nephew to Ángel Garibay K., whose publications in the 1930s and 1940s first brought Nahuatl literature to widespread public attention in Mexico. Needing to make a living, León-Portilla began attending law school and worked at a financial firm. At the same time he taught at Mexico City College, an English-language school in the Condesa neighborhood. Other instructors included important scholars of Mexican indigenous history and culture, Wigberto Jiménez Moreno, Fernando Horcasitas, and Eduardo Noguera. Gamio persuaded León-Portilla to drop his law studies and job in business to work at the Inter-American Indian Institute, a specialized organization of the Organization of American States, which Gamio directed. León-Portilla began graduate studies at the UNAM, completing his doctoral dissertation, La Filosofía Náhuatl estudiada en sus fuentes, in 1956, which launched his scholarly career.

Career
His dissertation on Nahua philosophy was published in Mexico, and then translated to English as Aztec Thought and Culture: A Study of the Ancient Nahuatl Mind (1967) and then many other languages. It was the first of his many works to be translated to English. His translations of Nahuatl and Spanish texts on the conquest of Mexico, first published in Mexico as Visión de los vencidos, translated to English as The Broken Spears, is the way many undergraduate students in the United States are introduced to accounts from indigenous participants and not Spanish conquistadors.

León-Portilla spearheaded a movement to understand and re-evaluate Nahuatl literature and religion, not only from the pre-Columbian era, but also that of the present day, especially since Nahuatl is still spoken by 1.5 million people. His works in English on literature included Pre-Columbian Literatures of Mexico (1986), Fifteen Poets of the Aztec World (2000), and with Earl Shorris, In the Language of Kings: An Anthology of Mesoamerican Literature, Pre-Columbian to the Present (2002). He also compared the literature of the Nahuas with that of the Inca. Another area of research was on indigenous religion and spirituality, with works including Native Meso-American Spirituality (1980), and South and Meso-American Native Spirituality: From the Cult of the Feathered Serpent to the Theology of Liberation (1997). He also published a work on the Maya, Time and Reality in the Thought of the Maya (1990).

León-Portilla was instrumental in bringing to light the works of Franciscan Fr. Bernardino de Sahagún, a 16th-century primary source on the Aztec civilization, whose twelve-volume General History of the Things of New Spain, often referred to as the Florentine Codex, are crucial for understanding Nahua religion, society, and culture, as well as for providing an account of the conquest of Mexico from the Mexica viewpoint. León-Portilla was the first to denote Sahagún as the "Father of Anthropology in the New World".

He contributed to the understanding of the development of the field of Mesoamerican history in Mexico. With Garibay, León-Portilla made contributions to the study of nineteenth-century Mesoamerican historian Manuel Orozco y Berra. León-Portilla also published two volumes on the work of Mesoamerican humanists, including his mentor Garibay.

In the field of colonial Nahuatl studies, particularly the New Philology, León-Portilla's work on a collection of late sixteenth-century wills in Nahuatl, The Testaments of Culhuacan, contributed to the understanding of local-level interactions within a Nahua town.

A subordinate but important interest of León-Portilla was the early history and ethnography of the Baja California Peninsula. He addressed this region in more than 30 books and articles, including a 1995 volume collecting several of his earlier publications.

Early in his academic career in 1969, he was awarded a Guggenheim Fellowship. That was the first of many academic awards and recognitions, including the Belisario Domínguez Medal of Honor, the highest award bestowed by the Mexican Senate. In 1970, he was elected to membership of Mexico's National College and, in 1995, to membership of the United States National Academy of Sciences. From 1987 to 1992, he served as his country's permanent delegate to UNESCO, during which time he successfully nominated five pre-Columbian sites in Mexico for inclusion on the World Heritage List. On 12 December 2013, León-Portilla received the Living Legend Award from the U.S. Library of Congress. He was also a member of the Mexican Academy of Language and the Mexican Academy of History.

Personal life
León-Portilla married Ascensión Hernández Triviño, a Spanish linguist and academic, in 1965. Their daughter, Marisa León-Portilla, is also a historian.

León-Portilla died in Mexico City on 1 October 2019 after having been hospitalized for much of the year. The federal Secretariat of Culture announced that his body would lie in state on 3 October 2019 at the Palacio de Bellas Artes.

Notable works
León-Portilla wrote more than a 150 articles and more than forty books. A select list is below.

 * La filosofía náhuatl estudiada en sus fuentes (In English: The Nahuatl Philosophy studied in its sources; 1956). Based on his doctoral dissertation, it has been edited at least ten times, and it also has been translated to English, Italian, Russian and German. León-Portilla explained that, the Mexica Tribes, didn't have a proper form of "philosophy" as known in the modern world, their tlamatinimê (Nahuatl sages) attempted to comprehend the world, asking themselves questions and searching about it. León-Portilla stated that, what Europeans understood as many gods, Aztecs, in fact perceived those many gods as a single entity called Ometeotl/Omecihuatl (Our Lord/Our Lady of Duality). This thesis was later extended in "Pensamiento y cultura azteca: estudio de la mente antigua náhuatl" (In English: Nahuatl Thought and Culture: Study of the Ancient Nahuatl Mind)
 * Siete ensayos sobre cultura náhuatl (In English: Seven Essays about Nahuatl Culture; 1958)
 * Visión de los vencidos (In English: The Broken Spears; 1959). His most popular and famous work until 2008 has been published twenty-nine times and translated into a dozen languages. In this short book, León-Portilla brings together several fragments of the Nahuatl vision of the Spanish conquest, from Moctezuma's premonitions to the sad songs (icnocuicatl) after the conquest. On 25 June 2009, the fiftieth anniversary of its first edition was celebrated in an event organized by the National Council for Culture and the Arts, the National Institute of Anthropology and History, the National Autonomous University of Mexico and the National College
 * Los antiguos mexicanos a través de sus crónicas y cantares (In English: The Ancient Mexicans through their Chronicles and Songs; 1961)
 * El reverso de la conquista. Relaciones aztecas, mayas e incas (In English: The reverse of the conquest. Aztec, Mayan and Inca Relations; 1964)
 * Tiempo y realidad en el pensamiento maya (In English: Time and Reality in Mayan Thought; 1968)
 * México-Tenochtitlan, su espacio y tiempos sagrados (In English: Mexico-Tenochtitlan, its sacred space and times; 1979)
 * La multilingüe toponimia de México: sus estratos milenarios. (In English: The multilingual toponymy of Mexico: its millenary strata; 1979)
 * Hernán Cortés y la Mar del Sur (In English: Hernán Cortés and the South Sea; 1985)
 * Cartografía y crónicas de la Antigua California (In English: Cartography and Chronicles of Ancient California; 1989)
 * Quince poetas del mundo náhuatl (In English: Fifteen poets of the Nahuatl world; 1993)
 * La filosofía náhuatl estudiada en sus fuentes (In English: Nahuatl philosophy studied in its sources; 1993)
 * Francisco Tenamaztle (1995)
 * La flecha en el blanco (In English: The arrow in the Target; 1996)
 * Bernardino de Sahagún, pionero de la antropología (In English: Bernardino de Sahagún, pioneer of anthropology; 1999)
 * Erótica Náhuatl (In English: Nahuatl Erotics; 2019)
 * Los Testamentos de Culhuacán: Vida y Muerte entre los Nahuas del México Central, siglo XVI. Editado por Miguel León-Portilla y Sarah Cline, con la colaboración de Juan Carlos Torres López. México: Universidad Iberoamericana 2023 ISBN 978-607-417-967-5 digital, open access publication

title: Miguel León-Portilla


text:
Product data management

Product data management (PDM) is the name of a business function within product lifecycle management (PLM) that denotes the management and publication of product data. In software engineering, this is known as version control. The goals of product data management include ensuring all stakeholders share a common understanding, that confusion during the execution of the processes is minimized, and that the highest standards of quality controls are maintained. PDM should not be confused with product information management (PIM).

Introduction
Product data management is the use of software or other tools to track and control data related to a particular product. The data tracked usually involves the technical specifications of the product, specifications for manufacture and development, and the types of materials that will be required to produce goods. The use of product data management allows a company to track the various costs associated with the creation and launch of a product. Product data management is part of product lifecycle management and configuration management, and is primarily used by engineers.

Within PDM the focus is on managing and tracking the creation, change, and archive of all information related to a product. The information being stored and managed (on one or more file servers) will include engineering data such as computer-aided design (CAD) models, drawings, and their associated documents.

Product data management (PDM) serves as a central knowledge repository for process and product history and promotes integration and data exchange among all business users who interact with products — including project managers, engineers, salespeople, buyers, and quality assurance teams.

The central database will also manage metadata such as the owner of a file and the release status of the components. The package will control check-in and check-out of the product data to multi-user; carry out engineering change management and release control on all versions/issues of components in a product; build and manipulate the product structure bill of materials (BOM) for assemblies; and assist in configurations management of product variants.

This enables automatic reports on product costs, etc. Furthermore, PDM enables companies producing complex products to spread product data into the entire PLM launch process. This significantly enhances the effectiveness of the launch process.

Product data management is focused on capturing and maintaining information on products and/or services through their development and useful life. Typical information managed within the PDM module includes:
 * Brand name
 * Part number
 * Part description
 * Supplier/vendor
 * Vendor part number and description
 * Unit of measure
 * Cost/price
 * Schematic or CAD drawing
 * Material data-sheets

Advantages

 * Track and manage all changes to product-related data
 * Spend less time organizing and tracking design data
 * Improve productivity through reuse of product design data
 * Enhance collaboration
 * Helps using visual management

Industrial Applications
Product Data Management is closely related and often used interchangeably with Product Information Management (PIM). PDM software applications are commonly used by companies involved in manufacturing and retailing.

History
PDM stems from traditional engineering design activities that created product drawings and schematics on paper and using CAD tools to create parts lists (Bills of Material structures – BOM). The PDM and BOM data are used in enterprise resource planning (ERP) systems to plan and coordinate all transactional operations of a company (sales order management, purchasing, cost accounting, logistics, etc.)

PDM is a subset of a larger concept of product lifecycle management (PLM). PLM encompasses the processes needed to launch new products (NPI), manage changes to existing products (ECN/ECO) and retire products at the end of their life span (EoL).

Early Product data management software was developed and used internally at some organizations, such as NASA and Boeing's IPAD or Ford Motor Company's PDGS. The first Product data management software on the open market was Sherpaworks by Sherpa, released in 1984. More software followed in the 1990s, when the market expanded.

title: Product data management


text:
User:MJS (usurped)

Hi Matt!

title: User:MJS (usurped)


text:
Ernst-Hugo Järegård

Ernst-Hugo Alfred Järegård (12 December 1928 – 6 September 1998) was a Swedish actor.

Biography
Järegård was born in Ystad. He received his acting training at Malmö City Theatre. From 1962 he was an actor in Sweden's prominent Royal Dramatic Theatre, where he came to perform a number of much celebrated parts: his eccentric Hitler in Schweik in the Second World War by Bertolt Brecht (1963), Estragon in the legendary 1966 Dramaten-staging of Samuel Beckett's Waiting for Godot, Thersites in Shakespeare's Troilus and Cressida 1967, Orgon in Molière's Tartuffe 1971, Hjalmar Ekdahl in Ingmar Bergman's 1972 production of Ibsen's The Wild Duck, Nero in Jean Racine's Britannicus (1974), a spot-on portrayal of August Strindberg in play Tribadernas natt (The Night of the Tribades) by Per Olov Enquist, the title role in Richard III by Shakespeare (1980) and the extremely creepy – and slightly perverted – boss Sven in VD ("CEO") by Stig Larsson in 1985, among others.

Järegård had a taste for villainous and dark characters, and enjoyed playing them. But he also had a very lyrical and soft side to him as an actor, something he showed in the TV production of Hans Christian och sällskapet (where he plays a village priest who suffers a great personal tragedy as his wife loses her mind after having a baby) and in the TV adaptation of Birger Sjöberg's Frida och hennes vän (based on Sjöberg's Frida's Book) where he plays the light-hearted, daydreaming early 1900s love-struck suitor of Frida. Adding the fact that Järegård also had a beautiful and expressive singing voice (he performed in a number of stage musicals during his career) gave him an incredible range and versatility as an actor. He originated the role of Guido in the first European staging of the musical Nine, for example (Oscarsteatern, Stockholm, 1983).

His distinct and original voice (with traces of the unmistakable Skåne-dialect) also made him a much appreciated and beloved narrator of children's cartoons and audio books. Particularly popular are his audio book (originally radio) recordings of Roald Dahl's Charlie and the Chocolate Factory, Robert Louis Stevenson's Dr Jekyll and Mr Hyde, and the narration of Sergei Prokofiev's Peter and the Wolf.

Järegård went on to play the villainous character Elaka Måns (Mean Mike in the English dub) in the Swedish animated movie Peter-No-Tail and its sequel Peter-No-Tail in Americat. He also lent him voice for the Swedish dub of the film Valhalla, playing the Norse God Loki; god of mischief.

Järegård gained international attention when he took on the role of Doctor Helmer in Lars von Trier's highly acclaimed mini-series Riget and Riget II (aka The Kingdom I & II). He also appeared in von Trier's Europa. He participated in about 20 movies and 40 TV productions: aside from the Riget-series; some of his greatest roles are in the Skånska mord-series, in the 1975 Hasse & Tage comedy Släpp fångarne loss, det är vår! (Release the Prisoners to Spring), in the 1962 cult movie Raggargänget, in Kådisbellan (aka The Slingshot) in 1993 and as the pompous old drag queen Ragnar Rönn in the teleplay Cheek to Cheek (written and directed by Jonas Gardell), 1997. Also in 1997 he appeared in CHOCK as the series' host and presented each episode. Usually he would make elaborate philosophical and mystical statements regarding the plot of each episode.

For his acting work, he was awarded with the Thalia prize (1967) and the Eugene O'Neill Award (1975), two of Sweden's most prestigious theatre awards.

Järegård married Karin Nordström (1923–2017) in 1949. They had a son called Johannes. Ernst-Hugo Järegård died of multiple myeloma in Lidingö, aged 69.

Personality
Järegård was a very colourful theatre personality who loved to stand out and celebrated originality. He loved clothes and Italian designers and was picky with designer labels in private – only the best would do. He was of the old belief that as an actor you not only represent yourself as a public person but also the theatre and the art as a whole; as being part of a public institution there for people; and therefore it is an actor's responsibility to "scrub up".

In his director's commentary on the DVD release of Europa, Lars von Trier commented that Järegård was difficult to work with, frequently sulking and making outrageous demands such as insisting on staying in one specific room in a specific hotel of his choice. He stated that Järegård was a compulsive scene-stealer who could not help attracting the focus even when he was supposed to be in the background of a scene. Von Trier claims that he eventually 'trained' Järegård by rewarding him with cigars for good behaviour but also called the actor "dear Ernst-Hugo" and said he misses him terribly.

Partial filmography

 * Raggargänget (1962) – Berra
 * Adam och Eva (1963) – Kejsarskägget
 * Svenska bilder (1964) – Karlman
 * Ön (1966) – Vicar Byström
 * Tartuffe (1966, TV Movie) – Tartuffe
 * Rooftree (1967) – Magnus
 * Het snö (1968) – Lennart Stenhäll
 * Waiting for Godot (1971, TV Movie) – Estragon
 * Kvartetten som sprängdes (aka "The Quartet That Broke Up") (1973, TV Mini-Series) – Stolz
 * De tre från Haparanda (1974, TV Mini-Series) – Fredrik Jönsson
 * Fimpen (1974) – Club Official
 * En handfull kärlek (1974) – Claes Crona
 * Släpp fångarne loss, det är vår! (Release the Prisoners to Spring) (1975) – Harald Hansson
 * Chez Nous (film) (1978) – Owner of Chez Nous
 * Flygnivå 450 (1980) – Giron
 * Clownen Jac (1981, TV Movie) – Jac the Clown
 * Peter-No-Tail (1981) – Elake Måns (voice)
 * Hans Christian och sällskapet (1981, TV Movie) – Hans-Cristian
 * Gråtvalsen (1983, TV Movie) – Hugo (as Ernst Hugo Järegård)
 * Peter-No-Tail in Americat (1985) – Elake Måns (voice)
 * Skånska mord (aka "Skåne Murders") (1986, TV Movie) – Martin Svensson
 * Valhalla (1986) – Loke (Swedish version, voice)
 * Fadern, sonen och den helige ande (1987) – Father
 * VD (1988, TV Movie) – Sven, VD
 * Bryllupsfesten (1989) – Eugene Borchrewink
 * Den hemliga vännen (1990) – The man
 * Europa (1991) – Uncle Kessler
 * The Great Day on the Beach (1991) – Narrator
 * Den goda viljan (Best Intentions) (1992, TV Mini-Series) – Professor Sundelius
 * Nästa man till rakning (1993, TV Mini-Series)
 * Kådisbellan (1993) – Teacher Lundin
 * Det bli'r i familien (1993) – Håkon Borelius
 * The Kingdom (1994–1997, TV Series) – Stig Helmer
 * Cheek to Cheek (1997, TV Movie) – Ragnar Rönn
 * CHOCK (1997, TV Series) – Presentatör
 * Dimension (2010, posthumously uncredited)

Stage work

 * Järegård's stage credits, dramaten.se; accessed 9 December 2014.

title: Ernst-Hugo Järegård