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85 Sky Tower

85 Sky Tower, formerly known as the T & C Tower or Tuntex Sky Tower, is an 85-story skyscraper in Lingya District, Kaohsiung, Taiwan. The structure is 347.5 m high. An antenna increases the pinnacle height to 378 m. Constructed from 1994 to 1997 by the now-defunct Tuntex Group, it is the tallest building in Kaohsiung, and the 2nd tallest in Taiwan after the Taipei 101.

As of 2023, the building is almost entirely unoccupied except for a few condominiums (some subleased as short-term rentals) and offices between the 12th to 35th floors. Many floors have not been used in decades, and their conditions have become dirty and run-down. When the building first opened, it once housed a department store, indoor amusement park, five-star hotel, observatory, steakhouse and disco, VIP club and spa, and other amenities.

The building was designed by C.Y. Lee & Partners and Hellmuth, Obata & Kassabaum, and has an unusual 'prong' design with two separate 39-floor sections, which merge into a single central tower rising to a spire. This unique design leaves a substantial space below the central part of the tower. The design was inspired by the Chinese character KAO (高) meaning tall, and also part of the city's name. John W. Milton was Project Director on behalf of Turner International Inc. (New York), a subsidiary of Turner Construction.

There is no 44th floor in the building due to Tetraphobia), so the 43rd floor connects directly to the 45th floor; the 57th floor, a mechanical floor, is numbered 57A. The pyramid shaped crown is the equivalent of three stories high and is hence marketed as 83–85 to arrive at a round number. There is no elevator access to floors above 80.

Occupancy
Floor 34 and 35 are currently leased by Look Hotel Group. The 85 Sky Tower Hotel (ceased operations) occupies floors 37 to 85, and it owns the observation deck. Office space and studio apartments occupy each side of the lower floors.

Atrium
There is an Atrium that extends from Level 45's Shimmer Ballroom (as of 2015 the entire floor is dark and unoccupied) to Level 83; it is one of the highest continuous atriums in the world.

Floor Directory

 * 83-85: Mechanical
 * 81: Radio Broadcasting Facility
 * 77-79: Palace VIP Private Club & Spa (ceased operations)
 * 76: Sexy Disco Bar (ceased operations)
 * 75: Teppanyaki restaurant (ceased operations)
 * 74: Observatory (ceased operations)
 * 71-73: unoccupied
 * 46-70: Guest Rooms (ceased operations)
 * 43-45: Meeting Rooms and Ballrooms (no 44th floor) (ceased operations)
 * 38-42: Hotel Facilities (ceased operations)
 * 36-37: M/E/P
 * 13-35: Offices & Residential condominiums（School of Banking and Finance, NSYSU）
 * 12: Nikko Plaza (sky lobby for offices & condos)
 * 8-11: Chien-Tai Indoor Amusement Park (ceased operations)
 * B1, 2-7: Chien-Tai Daimaru Department Store (ceased operations)
 * 1: Lobby
 * B5-B3: Parking garage

Transportation
The building is accessible within five blocks walking distance west of Sanduo Shopping District Station of the Kaohsiung MRT.

title: 85 Sky Tower


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Lycurgus of Thrace

In Greek mythology, Lycurgus (/laɪˈkɜːrɡəs/; Ancient Greek: Λυκοῦργος Lykoûrgos, Ancient Greek: [lykôrɡos]; also Lykurgos, Lykourgos) was the king of the Edoni in Thrace, son of Dryas, the "oak", and father of a son whose name was also Dryas.

Mythology
Lycurgus banned the cult of Dionysus. When Lycurgus heard that Dionysus was in his kingdom, he imprisoned Dionysus's followers, the Maenads, or "chased the[m] through the holy hills of Nysa, and the sacred implements dropped to the ground from the hands of one and all, as [he] struck them down with his ox-goad".

The compiler of Bibliotheke (3.5.1) says that as punishment, especially for his treatment for Ambrosia, Dionysus' nursemaid; the god drove Lycurgus insane. In his madness, Lycurgus mistook his son for a mature trunk of ivy, which is holy to Dionysus, and killed him, pruning away his nose and ears, fingers and toes. Consequently, the land of Thrace dried up in horror. Dionysus decreed that the land would stay dry and barren as long as Lycurgus was left unpunished for his injustice, so his people bound him and flung him to man-eating horses on Mount Pangaeüs. However, another version of the tale, transmitted in Servius's commentary on Aeneid 3.14, Porphyrio's commentary on Horace's Ode 2.19, and Hyginus in his Fabulae 132, records that Lycurgus cut off his own foot when he meant to cut down a vine of ivy. With Lycurgus dead, Dionysus lifted the curse. Also according to Hyginus, Lycurgus tried to rape his mother after imbibing wine. When he discovered what he had done, he attempted to cut down the grapevines, believing the wine to be a bad medicine. Dionysus drove him mad as a punishment, causing him to kill both his wife and his son, and threw him to the panthers on Mount Rhodope.

Diodorus Siculus relates that, centuries before the Trojan war, King Lycurgus of Thrace exiled one of his commanders, Mopsus, along with Sipylus the Scythian. Sometime later, when the Libyan Amazons invaded Thrace, Mopsus and Sipylus came to the rescue by defeating them in a pitched battle, in which their queen Myrine was slain; the Thracians then pursued the surviving Amazons all the way to Libya.

In some versions the story of Lycurgus and his punishment by Dionysus is placed in Arabia rather than in Thrace. The tragedian Aeschylus, in a lost play, depicted Lycurgus as a beer-drinker and hence a natural opponent of the wine god. There is a further reference to Lycurgus in Sophocles' Antigone in the Chorus's ode after Antigone is taken away (960 in the Greek text).

In Homer's Iliad, an older source than Aeschylus, Lycurgus's punishment for his disrespect towards the gods, particularly Dionysus, is blindness inflicted by Zeus followed not long after by death.

According to Sophocles, the frenzied Lycurgus mocked at Dionysus and as punishment was shut in "a prison of stone" until his madness went away.

The author of the Geoponica states that Dionysus, fleeing from Lycurgus, tied him up with vines and dove into the sea; Lycurgus shed a tear then, which transformed into cabbage. This was supposedly why grapevines and cabbages had a mutual dislike toward one another, and could not thrive together, as vines withered in the fields whenever a cabbage was growing nearby.

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title: Lycurgus of Thrace


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Lycurgus

Lycurgus (Λυκοῦργος Lykourgos) was the legendary lawgiver of Sparta, credited with the formation of its eunomia ("good order"), involving political, economic, and social reforms to produce a military-oriented Spartan society in accordance with the Delphic oracle. The Spartans in the historical period honoured him as god.

As a historical figure, almost nothing is known for certain about him, including when he lived and what he did in life. The stories of him place him at multiple times. Nor is it clear when the political reforms attributed to him, called the Great Rhetra, occurred. Ancient dates range from, putting aside the implausibly early Xenophonic 11th century BC, the early ninth century (c. 885 BC) to as late as early eighth century (c. 776 BC). There remains no consensus as to when he lived; some modern scholars deny that he existed at all.

The reforms at various times attributed to him touch all aspects of Spartan society. They included the creation of the Spartan constitution (in most traditions after the dual monarchy), the imposition of the Spartan mess halls called syssitia, the redistribution of land to each citizen by head, Spartan austerity and frugality, and Sparta's unique wedding and funerary customs. None of these reforms can be concretely attributed to Lycurgus. Most of the reforms likely date to the late sixth century BC (shortly before 500 BC), postdating his supposed life by centuries; some of the reforms, such as for the redistribution of land, are fictitious.

The extent of the Lycurgan myth emerges from Sparta's self-justification, seeking to endow its customs with timeless and divinely sanctioned antiquity. That antiquity was also malleable, reinvented at various times to justify the new as a return to Lycurgus' ideal society: his land reforms, for example, are attested only after the reformist Spartan monarchs Agis IV and Cleomenes III who sought to redistribute Sparta's land. The reforms attributed to Lycurgus, however, have been praised by ancients and moderns alike, seeing at various times different morals projected on a figure of which so little concrete can be known.

Historicity and chronology
A multitude of ancient sources mention Lycurgus; it is, however, troubling inasmuch as those accounts evolved according to then-contemporary political priorities and that they are profoundly inconsistent. The oldest is that of Herodotus, who wrote in the latter half of the fifth century BC. His account is likely based on oral accounts from both Spartans and non-Spartans in Greece. The two royal dynasties of Sparta, the Agiads and Eurypontids, both claimed Lycurgus in their ancestries.

However, Lycurgus does not feature in the earliest preserved Spartan source – Tyrtaeus – which has led many historians today to doubt his historicity: for example, Massimo Nafissi in A companion to Sparta writes he is "probably mythical". Others have attempted to gleam from the myths that survive some kernel of truth. But most historians "would subscribe to the stark judgement of Antony Andrewes: 'if there was a real Lycurgus, we know nothing of him.

There is no consensus as to when a historical Lycurgus lived, neither today or in the ancient world (Plutarch, in his Life of Lycurgus, in fact makes this remark in the opening paragraph). Most attempts to date his life are based on when the Great Rhetra, which promulgated the Lycurgus' reforms, occurred. The most accepted date in the ancient world was that based on the genealogy of Ephorus and the chronology of Eratosthenes, which dated the rhetra to 118 years after the reign of one of Sparta's founding kings, Procles, which corresponds to c. 885 BC. Alternatively, an excursus in Thucydides' Archaeology indicates that the reforms were instituted some four hundred years prior to the end of the Peloponnesian war, placing them to 804 or 821 BC. Xenophon, on the other hand, claimed that he was also responsible for the creation of the Lacedaemonian dual monarchy, placing him during the reign of the Heraclid kings Eurysthenes and Procles, dated to c. 1003 BC. Modern scholars generally date the Great Rhetra to before the First Messenian War, placing it prior to 736 BC. Little consensus exists for any more specificity. Nor should Lycurgus necessarily be credited with, and therefore dated to, the rhetra: it may have been a charter created some time in the seventh century to justify and ennoble with antiquity Sparta's institutions, especially after Sparta's emergence as the most powerful state in Greece.

One artefact, the Disc of Iphitos, also allegedly documents Lycurgus' involvement with the formation of the Olympic Games and would therefore place him c. 776 BC per Aristotle. The disc, however, is likely a forgery from the fourth century BC. The ancients had two solutions for this lack of chronological clarity: the historian Timaeus posited two Lycurguses: one who did the reforms and a later one with the same name who was present at the first Olympics. Eratosthenes instead posited the disc reflected informal Olympics held before 776 BC.

The tradition in Sparta of Lycurgus' existence dates to some time between the archaic age and the fifth century. Inasmuch as no Lycurgus is mentioned in Tyrtaeus, it is likely that the legend dates to shortly after Tyrtaeus' time, and therefore the late seventh or early sixth century. It likely emerged from Spartan success in that period and a desire to explain it. His legend was also constantly reworked and expanded through the course of the classical Greek period by securing for Spartans in their times divine sanction and greater legitimacy for actions which they claimed to be a return to Lycurgus' laws.

Life

In the earlier legends of Lycurgus, namely in the accounts of the Great Rhetra, Lycurgus is not credited with a radical reorganisation of Spartan life or with the institution of the ephorate. These early oral traditions – contra the written accounts – are "far from uniform". The earliest surviving written account on Lycurgus is in Herodotus, placing him as the guardian and regent of the early Argiad king Leobotes. Later accounts of Lycurgus' activities associate him with the later-more-influential Eurypontid dynasty instead, specifically as regent of Charilaus; the disputes indicate that the two royal houses by the historical period attempted to associate themselves by blood with the figure.

Herodotus provides two accounts for how the laws which Lycurgus enacted came to him: in the first version, Lycurgus receives those laws from Apollo through the Pythia at Delphi; in the second, based on Sparta's own traditions, Lycurgus bases the reforms off of existing laws in Crete. Spartan and Cretan institutions did indeed have common characteristics, but, though some direct borrowing may have occurred, such similarities are in general more likely to be because of the common Dorian inheritance of Sparta and Crete rather than because some individual such as Lycurgus imported Cretan customs to Sparta. Some versions of the story say that Lycurgus subsequently traveled as far as Egypt, Spain, and India. In the narrative of Lycurgus' reforms in Herodotus, Lycurgus is supposed to have created much of the Spartan constitution, including the gerousia and the ephorate. He also is supposed to have reorganised Spartan military life and instituted the syssitia (the mess halls to which each Spartan belonged). In Xenophon's telling, the legend of Lycurgus expanded even further, ascribing to him not only reforms but also the creation of the Lacedaemonian dual monarchy and state as well.

The description of Lycurgus as a regent or guardian who establishes the laws characterises him as a selfless figure who places the good of his king and community before his own. To that end there are two main traditions relating to his regency. The first, in Herodotus, is that he undertakes the regency until his ward came of age. The second is that he resigns, to protect his ward, amid rumours that he wishes to supplant the ward as king. Plutarch's version of the story includes the ward's mother seeking Lycurgus' hand in marriage to facilitate his accession. In this version, Lycurgus leaves to prevent himself from being used as a pawn in politics against his nephew.

The tradition where Lycurgus continues in the regency has little difficulty in placing him in a position to promulgate his laws. But the latter tradition where he leaves the city requires him to be recalled. In Aristotle's version, recounted by Plutarch, Lycurgus leads his followers into the city and occupies the agora to impose his laws; backed by Apolline divine approval, he forces the tyrannical Charilaus to accede to them and institutes the gerousia. Xenophon instead has Lycurgus forging an alliance with the most powerful non-royal citizens and forcing the laws through. Plutarch's narrative presented in his own voice instead consolidates prior disparate stories into a general upsurge of support from the kings, the people, and the aristocracy.

In Plutarch's narrative, Lycurgus' laws cause backlash among the wealthy, who attempt to have him stoned. After he flees to the temple of Athena Chalcioecus and has one of his eyes put out by an adolescent, his opponents back down and he forgives the adolescent. The extent to which this story of revolution and conflict with the wealthy is driven by – or a retrojection from – the experiences of the reformist Spartan kings Agis IV and Cleomenes III is unclear; the two later Spartan kings used the Lycurgan legend to justify their redistributive policies (and violent means) as a return to Lycurgus' "true" Spartan traditions, deviations from which explained all problems of latter-day Sparta. Finally, in Plutarch's version, after Lycurgus' recall to Sparta to institute new laws, he has the community swear to change the laws until he returns from Delphi. Upon reaching Delphi he dies so to enshrine the laws forever.

Attributed reforms
Lycurgus' laws are supposed to have touched the whole of Spartan society. At various times, the Spartans attributed every one of their institutions to him, except the institution of the dual monarchy. Because the Spartans attributed all manner of laws and customs to him, it is impossible to determine which laws (if any) are his in actuality. However, it is clear today, from comparisons with other archaic Greek states, that Spartan institutions such as men's dining halls, organisation of age cohorts, and the use of iron money were not out entirely out of the norm and had previously existed in other Greek cities: what made them distinctive was for how long they had been preserved at Sparta.

The character of many of the economic and social reforms attributed to Lycurgus was allegedly to ensure that citizens competed with each other only in merit rather than in wealth. However, many of the social reforms which are attributed to Lycurgus postdate him by centuries, emerging between 500 and 600 BC during the Second Messenian War or after the completion of Spartan conquests. The economic reforms, which are supposed to have made Spartan citizens equal, never happened and were invented to legitimise redistributive policies in the Hellenistic period.

Political and military

Lycurgus' political reforms were supposedly promulgated in a Great Rhetra that he received from the Pythia. It, however, is not genuine and contains anachronistic contents. Regardless, Plutarch records it as having included provisions related to Sparta's religious and political practices:

"After dedicating a temple to Zeus.. and Athena..., forming phylai and creating obai, and instituting a gerousia of thirty including the kings, then hold an apella from time to time. Thus bring in and set aside [proposals]. The people are to have the right to respond, and power... but if the people speak crookedly, the elders and kings are to be setters-aside."

Plutarch states that the provision that the elders and kings could set aside decisions of the apella, called the "rider", was a later addition. However, the grammatical construction of preserved rhetra is consistent with it being part of the original text, a view taken by Massimo Nafissi in Companion to archaic Greece, believing that the idea that the set-aside provision was later inserted was itself a fabrication of the fourth century BC.

Lycurgus is supposed also to have established the Spartan mess halls called syssitia or phiditia. Such halls were public, where all citizen men were required to eat dinner. Citizens were required to contribute to the mess hall's pantries with a substantial amount of food, wine, and money; failure or inability to do so would entail loss of citizenship. A relatively old tradition, predating the Hellenistic Spartan reformers Agis IV and Cleomenes III as well as likely Herodotus, claimed that Lycurgus' imposition of the mess halls created a citizen body of some 9,000 men. Each of these mess halls also played a role in military organisation: each likely had 15 men with three mess halls forming a "sworn band"; but after the perioikoi were merged into the Spartan army, each mess hall likely formed its own band. Such messes were likely preceded in the seventh century BC poet Alcman's time with andreia (private men's eating clubs). They became the classical syssitia after sumptuary restrictions, compulsory contributions from poorer citizens who previously abstained, and intermixture of rich and poor shortly before 500 BC.

The silence of the rhetra, a text meant to describe and legitimise the Spartan political system of the seventh century, with regard to Sparta's ephors suggests that the ephorate was a product of a later reform at Sparta and was not Lycurgan – pace Herodotus and Plutarch – in origin. In fact, archaeological discoveries at Sparta – showing the decline of Spartan art expressed on vases as well as a sudden expansion of agricultural labour in the mid-sixth century BC – suggest that much of the communitarian reforms attributed to Lycurgus may date to that time.

Economic
One of the illusions of the Spartan mirage was the illusion that Spartan citizens were economically equal: that no citizen owned more land than another. There is, however, no evidence of equal land ownership at Sparta, with exception of Cleomenes' five-year regime.

Land inequality increased through Spartan history, mediated by conquests abroad which allowed poorer citizens to retain a reasonable standard of living. When conquests ended after 550 BC, the poorer citizens were, over time, removed from the citizen rolls, for inability to pay dues to the syssitia. Demands for redistribution, heard by the reformist Spartan monarchs Agis IV and Cleomenes III, led to the creation of a myth that Lycurgus redistributed the land of Laconia and Messenia equally among the homoioi with the helots as bound tenants. The consensus among scholars is that this never happened. The seventh century Spartan poet, Tyrtaeus, already opposed land distribution in the poem Eunomia, attesting to land inequality at the earliest times.

Lycurgus is also supposed to have ensured the austere lifestyle of the Spartans by banning the use of gold and silver coins, requiring a currency made of iron. Xenophon claimed that this meant acquisition of wealth became too bulky to hide; Plutarch believed that this was to make it impossible, or at least difficult, for Spartans to purchase luxury goods. Coinage came to Greece in the 550s BC; it is not possible that any law mentioning coins dates to the eighth century BC (or earlier), when Lycurgus is supposed to have lived. Nor is any ban on gold and silver mentioned in Herodotus. Usage of gold and silver at Sparta is implied by other reports that the kings were fined in drachma and talents as well as by Spartan state rewards and ransoms. Plutarch's attempted to reconcile the evidence by depicting the Spartans allowing gold and silver for public use but retaining the allegedly Lycurgan restrictions on private use. Such a depiction, however, is not consistent with actions by Spartan generals during the Peloponnesian War. Other ancient authors were more equivocal, dating the alleged ban on precious metals to after Lycurgus and to different men.

Ancient authors claimed of the Spartans a general aversion to commerce, which was also attributed to Lycurgus, who was supposed to have "forbade free men to touch anything to do with making money". This likely emerged from the fact that Spartan citizens, the spartiates or homoioi, were a leisurely class of land owners who looked down on manual labourers and craftsmen. Such a ban also likely emerged in the sixth century, since Spartan citizen sculptors are attested to prior to that time. The inequality of Spartan society also implies that trade must have occurred; the second dinner in the syssitia involved bread, meat, fish, and other produce which were bought or donated by wealthy Spartans. Plutarch, who claims Spartan did not dispute or talk about money, is also internally inconsistent when elsewhere notes Spartan commercial contracts and Sparta's delegation of such matters to expert resolution.

Plutarch also claims that Lycurgus imposed sumptuary legislation, prohibiting foreign artisans from residing at Sparta and restricting the tools with which Spartan houses could be built, to encourage simplicity. Archaeological evidence of foreign wares postdates the eighth century, with a decline in imports met by local production by the sixth century. The alleged simplicity of Spartan dwellings evidently did not extend to their interiors; and Spartans were famous across Greece for the jewellery worn by Spartan women, their number of slaves and horses, and their dominance at the expensive sport of chariot racing at pan-Hellenic games. While most male Spartan citizens affected a generally consistent and relatively inexpensive form of dress at home, Spartans on campaign showed extreme wealth from the expense of their crimson dyes to the polish of their armour. However, while Xenophon claims this austere dress also came from Lycurgus, art from Laconia implies adoption after 500 BC, consistent with Thucydides claim that Spartans wore complex and luxurious clothing until "not long ago".

Social

Lycurgus is also supposed to have instituted the Spartan practice of staged bride capture where the bride, rather than being processed to the groom's home for a wedding ceremony with feast, was instead ritually seized by the groom, and the marriage consummated without feast. The seventh century Spartan poet Alcman makes no mention of such customs, and composed wedding hymns reflecting the more common Greek wedding processions; Spartan wedding customs therefore also postdate Lycurgus, emerging some time before 500 BC. The further claim in Plutarch's Moralia that Lycurgus prohibited dowries altogether has no basis. Lycurgus is also said to have instituted a system of wife sharing as a pronatalist and eugenicist policy; if such wife sharing existed, it is likely a product of Spartan population decline in the fifth century BC.

Plutarch also credits Lycurgus with sumptuary laws on burials. Archaeological evidence broadly supports the notion that Spartans practiced uniform burial without grave goods, albeit with exceptions for generals and Olympic victors. However, Lycurgus is also said to have banned lamentations and allowed burials near temples. Burials near temples were common in archaic Greece before being prohibited by most cities; Sparta merely retained the practice. The earliest Spartan art and poems also still mention lamenting mourners, implying that such a ban likely postdates Lycurgus and was introduced c. 600 BC; moreover, any ban on grave goods must postdate a grave, also c. 600 BC, containing pottery grave goods. Further claims that Lycurgus required the burial of fallen Spartan soldiers abroad are not compatible with archaeological evidence showing that the first certain mass grave for Spartan battlefield losses was at Plataea.

The education of Spartan boys in the agoge, less anachronistically the paideia, was also attributed to an initiative of Lycurgus to equalise Spartan citizens socially, by raising them without outside family and clan loyalties. Though the story is rejected by Plutarch, Lycurgus is also said to have instituted the crypteia, a select group of young men tasked with clandestinely killing helots in the night. Both the agoge and crypteia likely emerged some time during the seventh century alongside the institution of the ephorate. The education of Spartan women, mainly focusing on physical fitness, or, supposedly, physical fitness to produce healthy children for eugenic purposes, was similarly attributed to Lycurgus.

Ancient
In Spartan society, Lycurgus and his laws were received as the creator of the Spartan way of life. Xenophon's pro-Spartan Spartan Constitution "unreservedly regard[s Lycurgus] as the Spartan legislator par excellence, who arranged the Spartan way of life once and for all". For these achievements, which they viewed as having facilitated the emergence of Sparta as the most powerful state in Greece, Lycurgus was honoured with a hero cult, which may have developed slowly into the Roman imperial period into full godhood. His temple and sanctuary, according to Pausanias, included a grave for his son with the name Eukosmos (referring to good order) with the graves of the Spartan dual monarchy's founders' wives nearby.

The idealisation of Sparta, called the "Spartan mirage", also drove praise of Lycurgus in other Greek states. The tradition of a timeless legislator with his divinely-inspired (or at least sanctioned) laws gave Sparta's constitution greater legitimacy while also making it inflexible. Even attempts to reform Spartan life during the Hellenistic period, by Spartan monarchs Agis IV and Cleomenes III, were viewed in their time as returning to Lycurgan tradition rather than an innovation. The stories of Lycurgus were constantly reinvented for each Spartan generation; the decline of Sparta through to Hellenistic times saw Lycurgus' praise extended to praise him for having creating an ideal Sparta, free from the moral and political decay of the real one.

Admiration of the customs of Sparta, supposed to be established by Lycurgus, survived – with a break during the second century when Sparta was part of the Achaean League – continuously into the Sparta of the Roman Empire. Aristotle, for example, praised the Lycurgan agoge as a form of universal education especially in the way it supported the stability of the Spartan state. Into the Roman period, Sparta received privileged treatment from the Romans as in part a means to preserve Greek traditions to display to tourists: while this touristic Sparta at times veered toward the extreme, it also cultivated its Lycurgan inheritance by means of architecture, theatre, and retention of distinctive political institutions.

The Plutarchian comparison between the paired lives of Lycurgus and Numa (the early Roman lawgiver and king), for example, judged Lycurgus favourably compared to the Roman by emphasising Lycurgan education and pronatalism. Another argument for Lycurgan superiority was also that Sparta declined as it supposedly deviated from Lycurgus' settlements while Rome flourished as it similarly deviated from Numa's ideals. In the end, for Plutarch, Lycurgus was seen as a more important political theorist than Plato and as one of the most famous, moral, and effective legislators of the Greek tradition.

Modern
The main elements of Lycurgus' legacy are through the laws attributed to him. In the modern world this took on a number of aspects: the stability of the Lacedaemonian state from Lycurgus' balanced constitution; universal male citizen conscription and contribution (via the syssitia); economic freedom for citizens by their possession of sufficient land and helots to meet their needs; and austere politics for the common good. The republican views of Niccolò Machiavelli trended toward the Lycurgan "mixed constitution" but this was not necessarily a through-line in renaissance European political thought. Other thinkers of the period hailed Lycurgan politics as building a stable polity dedicated to simplicity, unity, and the communal interest – attributing to the Spartans, not necessarily rightly, universal education and equality among citizens – while also noting the cruelty of the agoge and denigration of autonomy, especially in contrast to democratic Athens.

Charles Rollin, a French educator, produced an enduring and admiring conception of Lycurgus as having created the rule of law, the mixed constitution, equality, and universal education. The philosopher Jean-Jacques Rousseau, who derived most of his knowledge of Lycurgus from Plutarch's biography, viewed the figure positively as standing for an austere civil morality acting for the collective good. This view of Lycurgus and Sparta saw him associate Lycurgus' reforms with the "general will". Positive views of Sparta pervaded some articles in the Encyclopédie but this was not shared by all authors. Diderot, the main editor of the Encyclopédie, was more pessimistic, saying that Lycurgan laws "created monks bearing arms" while branding the system as a whole "an atrocity" and "incompatible with a large... [or] commercial state". The branding of Lycurguan Sparta as a "dismal monastery" was widely, but not universally, shared among the philosophes. Similar negative views were expressed by the American founder John Adams who saw Lycurgus as having doomed his own people to poverty and futile militarism; however, he also praised the Lycurgan – as well as the Polybian – mixed constitution in Defense of the Constitutions as did Madison in The Federalist Papers (number 63).

Nationalist views of Spartan society, which praised Spartan eugenicism and militarism became common in Germany in the later nineteenth century through to the Nazi regime. Such views, however, were not unanimous. The German classicist Karl Julius Beloch, for example, was one of the first to take a highly critical view of Sparta, suggesting that Lycurgus was a fiction and his Great Rhetra a fabrication. In the aftermath of the First world war German nationalism embraced Sparta and Lycurgus, seeing it as a locus of heroism, physicality, racial purity, and struggle. Such themes complemented fascist and Nazi ideology, painting Sparta as a "proto-National Socialist state". Defeat in the Second world war largely ended such hagiography.

title: Lycurgus


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Heinrich Hertz Tower

The Heinrich Hertz Tower (Heinrich-Hertz-Turm) is a landmark radio telecommunication tower in the city of Hamburg, Germany.

Designed by architect Fritz Trautwein, in co-operation with civil engineers Jörg Schlaich, Rudolf Bergermann and Fritz Leonhardt, the tower was built between 1965–1968 for the former Deutsche Bundespost (German Federal Post and Telecommunications Agency, now Deutsche Telekom's subsidiary Deutsche Funkturm GmbH) near Planten un Blomen park.

With an overall height of 279.2 m (916 ft) it is Hamburg's tallest structure, consisting of a 204 m (670 ft) steel-reinforced concrete lower section topped by a 45 m (148 ft) steel-lattice tower and a three-segmented cylinder of about 30 m (98 ft), which supports various antennas. There are eight concentric platforms stacked one above the other: starting at 128 m (420 ft) with the two-story observation (lower floor) and revolving restaurant (upper floor) platform, served by two high-speed elevators. Above that at 150 m (492 ft) is the operations platform housing the workforce and equipment, and further up six differentially sized, smaller open platforms in same distances, populated with high-gain directional microwave radio relay antennas ("parabolic mirrors"). Number nine was added at 25 m height in July 2005. After the observation platform and restaurant were closed due to asbestos decontamination, former stuntman Jochen Schweizer had a bungee jumping base installed. The restaurant will not open again due to new fire escape regulations, and the bungee platform was closed at the end of 2001.

The tower has been home to the VFDB Hamburg section's radio amateur club station "DF0HHT". It also housed a DGPS transmitting station serving the city of Hamburg's Surveying Agency.

The tower is named after the Hamburg-born German physicist Heinrich Hertz. A memorial plaque in his honour on the tower's wall reads: "Heinrich Hertz – Dem Sohn der Stadt Hamburg" ("Heinrich Hertz - Son of the City of Hamburg").

title: Heinrich Hertz Tower


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Addressing mode

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

In computer programming, addressing modes are primarily of interest to those who write in assembly languages and to compiler writers. For a related concept see orthogonal instruction set which deals with the ability of any instruction to use any addressing mode.

Caveats
There are no generally accepted names for addressing modes: different authors and computer manufacturers may give different names to the same addressing mode, or the same names to different addressing modes. Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes. For example, some complex instruction set computer (CISC) architectures, such as the Digital Equipment Corporation (DEC) VAX, treat registers and literal or immediate constants as just another addressing mode. Others, such as the IBM System/360 and its successors, and most reduced instruction set computer (RISC) designs, encode this information within the instruction. Thus, the latter machines have three distinct instruction codes for copying one register to another, copying a literal constant into a register, and copying the contents of a memory location into a register, while the VAX has only a single "MOV" instruction.

The term "addressing mode" is itself subject to different interpretations: either "memory address calculation mode" or "operand accessing mode". Under the first interpretation, instructions that do not read from memory or write to memory (such as "add literal to register") are considered not to have an "addressing mode". The second interpretation allows for machines such as VAX which use operand mode bits to allow for a register or for a literal operand. Only the first interpretation applies to instructions such as "load effective address," which loads the address of the operand, not the operand itself.

The addressing modes listed below are divided into code addressing and data addressing. Most computer architectures maintain this distinction, but there are (or have been) some architectures which allow (almost) all addressing modes to be used in any context.

The instructions shown below are purely representative in order to illustrate the addressing modes, and do not necessarily reflect the mnemonics used by any particular computer.

Some computers, e.g., IBM 709, RCA 3301, do not have a single address mode field but rather have separate fields for indirect addressing and indexing.

Number of addressing modes
Computer architectures vary greatly as to the number of addressing modes they provide in hardware. There are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes, even though it requires a few extra instructions, and perhaps an extra register. It has proven much easier to design pipelined CPUs if the only addressing modes available are simple ones.

Most RISC architectures have only about five simple addressing modes, while CISC architectures such as the DEC VAX have over a dozen addressing modes, some of which are quite complicated. The IBM System/360 architecture has only four addressing modes; a few more have been added for the ESA/390 architecture.

When there are only a few addressing modes, the particular addressing mode required is usually encoded within the instruction code (e.g. IBM System/360 and successors, most RISC). But when there are many addressing modes, a specific field is often set aside in the instruction to specify the addressing mode. The DEC VAX allowed multiple memory operands for almost all instructions, and so reserved the first few bits of each operand specifier to indicate the addressing mode for that particular operand. Keeping the addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set.

Even on a computer with many addressing modes, measurements of actual programs indicate that the simple addressing modes listed below account for some 90% or more of all addressing modes used. Since most such measurements are based on code generated from high-level languages by compilers, this reflects to some extent the limitations of the compilers being used.

Important use case
Some instruction set architectures, such as Intel x86 and IBM/360 and its successors, have a load effective address instruction. This calculates the effective operand address and loads it into a register, without accessing the memory it refers to. This can be useful when passing the address of an array element to a subroutine. It may also be a clever way of doing more calculations than normal in one instruction; for example, using such an instruction with the addressing mode "base+index+offset" (detailed below) allows one to add two registers and a constant together in one instruction and store the result in a third register.

Simple addressing modes for code
Some simple addressing modes for code are shown below. The nomenclature may vary depending on platform.

Absolute or direct
++--+   |jump|           address            | ++--+   (Effective PC address = address)

The effective address for an absolute instruction address is the address parameter itself with no modifications.

PC-relative
++--+   |jump|           offset             |    jump relative ++--+   (Effective PC address = next instruction address + offset, offset may be negative)

The effective address for a PC-relative instruction address is the offset parameter added to the address of the next instruction. This offset is usually signed to allow reference to code both before and after the instruction.

This is particularly useful in connection with jump instructions, because typical jumps are to nearby instructions (in a high-level language most if or while statements are reasonably short). Measurements of actual programs suggest that an 8 or 10 bit offset is large enough for some 90% of conditional jumps (roughly ±128 or ±512 bytes). For jumps to instructions that are not nearby, other addressing modes are used.

Another advantage of PC-relative addressing is that the code may be position-independent, i.e. it can be loaded anywhere in memory without the need to adjust any addresses.

Register indirect
+---+-+   |jumpVia| reg | +---+-+   (Effective PC address = contents of register 'reg')

The effective address for a Register indirect instruction is the address in the specified register. For example, (A7) to access the content of address register A7.

The effect is to transfer control to the instruction whose address is in the specified register.

Many RISC machines, as well as the CISC IBM System/360 and successors, have subroutine call instructions that place the return address in an address register—the register-indirect addressing mode is used to return from that subroutine call.

Sequential execution
+--+   | nop  |              execute the following instruction +--+   (Effective PC address = next instruction address)

The CPU, after executing a sequential instruction, immediately executes the following instruction.

Sequential execution is not considered to be an addressing mode on some computers.

Most instructions on most CPU architectures are sequential instructions. Because most instructions are sequential instructions, CPU designers often add features that deliberately sacrifice performance on the other instructions—branch instructions—in order to make these sequential instructions run faster.

Conditional branches load the PC with one of 2 possible results, depending on the condition—most CPU architectures use some other addressing mode for the "taken" branch, and sequential execution for the "not taken" branch.

Many features in modern CPUs—instruction prefetch and more complex pipelineing, out-of-order execution, etc.—maintain the illusion that each instruction finishes before the next one begins, giving the same final results, even though that's not exactly what happens internally.

Each "basic block" of such sequential instructions exhibits both temporal and spatial locality of reference.

CPUs that do not use sequential execution
CPUs that do not use sequential execution with a program counter are extremely rare. In some CPUs, each instruction always specifies the address of next instruction. Such CPUs have an instruction pointer that holds that specified address; it is not a program counter because there is no provision for incrementing it. Such CPUs include some drum memory computers such as the IBM 650, the SECD machine, Librascope LGP-30, and the RTX 32P.

Other computing architectures go much further, attempting to bypass the von Neumann bottleneck using a variety of alternatives to the program counter.

Conditional execution
Some computer architectures have conditional instructions (such as ARM, but no longer for all instructions in 64-bit mode) or conditional load instructions (such as x86) which can in some cases make conditional branches unnecessary and avoid flushing the instruction pipeline. An instruction such as a 'compare' is used to set a condition code, and subsequent instructions include a test on that condition code to see whether they are obeyed or ignored.

Skip
+--+-+-+   |skipEQ| reg1| reg2|      skip the next instruction if reg1=reg2 +--+-+-+   (Effective PC address = next instruction address + 1)

Skip addressing may be considered a special kind of PC-relative addressing mode with a fixed "+1" offset. Like PC-relative addressing, some CPUs have versions of this addressing mode that only refer to one register ("skip if reg1=0") or no registers, implicitly referring to some previously-set bit in the status register. Other CPUs have a version that selects a specific bit in a specific byte to test ("skip if bit 7 of reg12 is 0").

Unlike all other conditional branches, a "skip" instruction never needs to flush the instruction pipeline, though it may need to cause the next instruction to be ignored.

Simple addressing modes for data
Some simple addressing modes for data are shown below. The nomenclature may vary depending on platform.

Register (or, register direct)
+--+-+-+-+   | mul  | reg1| reg2| reg3|      reg1 := reg2 * reg3; +--+-+-+-+

This "addressing mode" does not have an effective address and is not considered to be an addressing mode on some computers.

In this example, all the operands are in registers, and the result is placed in a register.

Base plus offset, and variations
This is sometimes referred to as 'base plus displacement' +--+-+-++   | load | reg | base|     offset     |  reg := RAM[base + offset] +--+-+-++   (Effective address = offset + contents of specified base register)

The offset is usually a signed 16-bit value (though the 80386 expanded it to 32 bits).

If the offset is zero, this becomes an example of register indirect addressing; the effective address is just the value in the base register.

On many RISC machines, register 0 is fixed at the value zero. If register 0 is used as the base register, this becomes an example of absolute addressing. However, only a small portion of memory can be accessed (64 kilobytes, if the offset is 16 bits).

The 16-bit offset may seem very small in relation to the size of current computer memories (which is why the 80386 expanded it to 32-bit). It could be worse: IBM System/360 mainframes only have an unsigned 12-bit offset. However, the principle of locality of reference applies: over a short time span, most of the data items a program wants to access are fairly close to each other.

This addressing mode is closely related to the indexed absolute addressing mode.

Example 1: Within a subroutine a programmer will mainly be interested in the parameters and the local variables, which will rarely exceed 64 KB, for which one base register (the frame pointer) suffices. If this routine is a class method in an object-oriented language, then a second base register is needed which points at the attributes for the current object (this or self in some high level languages).

Example 2: If the base register contains the address of a composite type (a record or structure), the offset can be used to select a field from that record (most records/structures are less than 32 kB in size).

Immediate/literal
+--+-+-++   | add  | reg1| reg2|    constant    |    reg1 := reg2 + constant; +--+-+-++

This "addressing mode" does not have an effective address, and is not considered to be an addressing mode on some computers.

The constant might be signed or unsigned. For example,  to move the immediate hex value of "FEEDABBA" into register D0.

Instead of using an operand from memory, the value of the operand is held within the instruction itself. On the DEC VAX machine, the literal operand sizes could be 6, 8, 16, or 32 bits long.

Andrew Tanenbaum showed that 98% of all the constants in a program would fit in 13 bits (see RISC design philosophy).

Implicit
+-+   | clear carry bit | +-+   +---+    | clear Accumulator | +---+ The implied addressing mode, also called the implicit addressing mode (x86 assembly language), does not explicitly specify an effective address for either the source or the destination (or sometimes both).

Either the source (if any) or destination effective address (or sometimes both) is implied by the opcode.

Implied addressing was quite common on older computers (up to mid-1970s). Such computers typically had only a single register in which arithmetic could be performed—the accumulator. Such accumulator machines implicitly reference that accumulator in almost every instruction. For example, the operation < a := b + c; > can be done using the sequence < load b; add c; store a; > -- the destination (the accumulator) is implied in every "load" and "add" instruction; the source (the accumulator) is implied in every "store" instruction.

Later computers generally had more than one general-purpose register or RAM location which could be the source or destination or both for arithmetic—and so later computers need some other addressing mode to specify the source and destination of arithmetic.

Among the x86 instructions, some use implicit registers for one of the operands or results (multiplication, division, counting conditional jump).

Many computers (such as x86 and AVR) have one special-purpose register called the stack pointer which is implicitly incremented or decremented when pushing or popping data from the stack, and the source or destination effective address is (implicitly) the address stored in that stack pointer.

Many 32-bit computers (such as 68000, ARM, or PowerPC) have more than one register which could be used as a stack pointer—and so use the "register autoincrement indirect" addressing mode to specify which of those registers should be used when pushing or popping data from a stack.

Some current computer architectures (e.g. IBM/390 and Intel Pentium) contain some instructions with implicit operands in order to maintain backwards compatibility with earlier designs.

On many computers, instructions that flip the user/system mode bit, the interrupt-enable bit, etc. implicitly specify the special register that holds those bits. This simplifies the hardware necessary to trap those instructions in order to meet the Popek and Goldberg virtualization requirements—on such a system, the trap logic does not need to look at any operand (or at the final effective address), but only at the opcode.

A few CPUs have been designed where every operand is always implicitly specified in every instruction -- zero-operand CPUs.

Absolute/direct
+--+-+--+   | load | reg |         address                      | +--+-+--+   (Effective address = address as given in instruction)

This requires space in an instruction for quite a large address. It is often available on CISC machines which have variable-length instructions, such as x86.

Some RISC machines have a special Load Upper Literal instruction which places a 16- or 20-bit constant in the top half of a register. That can then be used as the base register in a base-plus-offset addressing mode which supplies the low-order 16 or 12 bits. The combination allows a full 32-bit address.

Indexed absolute
+--+-+-++   | load | reg |index|         address                | +--+-+-++   (Effective address = address + contents of specified index register)

This also requires space in an instruction for quite a large address. The address could be the start of an array or vector, and the index could select the particular array element required. The processor may scale the index register to allow for the size of each array element.

Note that this is more or less the same as base-plus-offset addressing mode, except that the offset in this case is large enough to address any memory location.

Example 1: Within a subroutine, a programmer may define a string as a local constant or a static variable. The address of the string is stored in the literal address in the instruction. The offset—which character of the string to use on this iteration of a loop—is stored in the index register.

Example 2: A programmer may define several large arrays as globals or as class variables. The start of the array is stored in the literal address (perhaps modified at program-load time by a relocating loader) of the instruction that references it. The offset—which item from the array to use on this iteration of a loop—is stored in the index register. Often the instructions in a loop re-use the same register for the loop counter and the offsets of several arrays.

Base plus index
+--+-+-+-+   | load | reg | base|index| +--+-+-+-+   (Effective address = contents of specified base register + contents of specified index register)

The base register could contain the start address of an array or vector, and the index could select the particular array element required. The processor may scale the index register to allow for the size of each array element. This could be used for accessing elements of an array passed as a parameter.

Base plus index plus offset
+--+-+-+-++   | load | reg | base|index|         offset | +--+-+-+-++   (Effective address = offset + contents of specified base register + contents of specified index register)

The base register could contain the start address of an array or vector of records, the index could select the particular record required, and the offset could select a field within that record. The processor may scale the index register to allow for the size of each array element.

Scaled
+--+-+-+-+   | load | reg | base|index| +--+-+-+-+   (Effective address = contents of specified base register + scaled contents of specified index register)

The base register could contain the start address of an array or vector data structure, and the index could contain the offset of the one particular array element required.

This addressing mode dynamically scales the value in the index register to allow for the size of each array element, e.g. if the array elements are double precision floating-point numbers occupying 8 bytes each then the value in the index register is multiplied by 8 before being used in the effective address calculation. The scale factor is normally restricted to being a power of two, so that shifting rather than multiplication can be used.

Register indirect
+--+--+-+   | load | reg1 | base| +--+--+-+   (Effective address = contents of base register)

A few computers have this as a distinct addressing mode. Many computers just use base plus offset with an offset value of 0. For example, (A7)

Register autoincrement indirect
+--+-+---+   | load | reg | base  | +--+-+---+   (Effective address = contents of base register)

After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed. For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word). Within a loop, this addressing mode can be used to step through all the elements of an array or vector.

In high-level languages it is often thought to be a good idea that functions which return a result should not have side effects (lack of side effects makes program understanding and validation much easier). This addressing mode has a side effect in that the base register is altered. If the subsequent memory access causes an error (e.g. page fault, bus error, address error) leading to an interrupt, then restarting the instruction becomes much more problematic since one or more registers may need to be set back to the state they were in before the instruction originally started.

There have been at least two computer architectures which have had implementation problems with regard to recovery from interrupts when this addressing mode is used:
 * Motorola 68000 (address is represented in 24 bits). Could have one or two autoincrement register operands. The 68010+ resolved the problem by saving the processor's internal state on bus or address errors.
 * DEC VAX. Could have up to 6 autoincrement register operands. Each operand access could cause two page faults (if operands happened to straddle a page boundary). Of course the instruction itself could be over 50 bytes long and might straddle a page boundary as well!

Register autodecrement indirect
+--+-+-+   | load | reg | base| +--+-+-+   (Effective address = new contents of base register)

Before determining the effective address, the value in the base register is decremented by the size of the data item which is to be accessed.

Within a loop, this addressing mode can be used to step backwards through all the elements of an array or vector. A stack can be implemented by using this mode in conjunction with the previous addressing mode (autoincrement).

See the discussion of side-effects under the autoincrement addressing mode.

Memory indirect or deferred
Any of the addressing modes mentioned in this article could have an extra bit to indicate indirect addressing, i.e. the address calculated using some mode is in fact the address of a location (typically a complete word) which contains the actual effective address.

Indirect addressing may be used for code or data. It can make implementation of pointers, references, or handles much easier, and can also make it easier to call subroutines which are not otherwise addressable. Indirect addressing does carry a performance penalty due to the extra memory access involved.

Some early minicomputers (e.g. DEC PDP-8, Data General Nova) had only a few registers and only a limited direct addressing range (8 bits). Hence the use of memory indirect addressing was almost the only way of referring to any significant amount of memory.

Half of the DEC PDP-11's eight addressing modes are deferred. Register deferred @Rn is the same as register indirect as defined above. Predecrement deferred @-(Rn), postincrement deferred @(Rn)+, and indexed deferred @nn(Rn) modes point to addresses in memory which are read to find the address of the parameter. The PDP-11's deferred modes, when combined with the program counter, provide its absolute and PC-relative addressing modes.

PC-relative
+--+--+-++   | load | reg1 | base=PC |     offset     | +--+--+-++   reg1 := RAM[PC + offset] (Effective address = PC + offset)

The PC-relative addressing mode can be used to load a register with a value stored in program memory a short distance away from the current instruction. It can be seen as a special case of the "base plus offset" addressing mode, one that selects the program counter (PC) as the "base register".

There are a few CPUs that support PC-relative data references. Such CPUs include:

The x86-64 architecture and the 64-bit ARMv8-A architecture have PC-relative addressing modes, called "RIP-relative" in x86-64 and "literal" in ARMv8-A. The Motorola 6809 also supports a PC-relative addressing mode.

The PDP-11 architecture, the VAX architecture, and the 32-bit ARM architectures support PC-relative addressing by having the PC in the register file.

The IBM z/Architecture includes specific instructions, e.g., Load Relative Long, with PC-relative addressing if the General-Instructions-Extension Facility is active.

When this addressing mode is used, the compiler typically places the constants in a literal pool immediately before or immediately after the subroutine that uses them, to prevent accidentally executing those constants as instructions.

This addressing mode, which always fetches data from memory or stores data to memory and then sequentially falls through to execute the next instruction (the effective address points to data), should not be confused with "PC-relative branch" which does not fetch data from or store data to memory, but instead branches to some other instruction at the given offset (the effective address points to an executable instruction).

Obsolete addressing modes
The addressing modes listed here were used in the 1950–1980 period, but are no longer available on most current computers. This list is by no means complete; there have been many other interesting and peculiar addressing modes used from time to time, e.g. absolute-minus-logical-OR of two or three index registers.

Multi-level memory indirect
If the word size is larger than the address, then the word referenced for memory-indirect addressing could itself have an indirect flag set to indicate another memory indirect cycle. This flag is referred to as an indirection bit, and the resulting pointer is a tagged pointer, the indirection bit tagging whether it is a direct pointer or an indirect pointer. Care is needed to ensure that a chain of indirect addresses does not refer to itself; if it does, one can get an infinite loop while trying to resolve an address.

The IBM 1620, the Data General Nova, the HP 2100 series, and the NAR 2 each have such a multi-level memory indirect, and could enter such an infinite address calculation loop. The memory indirect addressing mode on the Nova influenced the invention of indirect threaded code.

The DEC PDP-10 computer with 18-bit addresses and 36-bit words allowed multi-level indirect addressing with the possibility of using an index register at each stage as well. The priority interrupt system was queried before decoding of every address word. So, an indirect address loop would not prevent execution of device service routines, including any preemptive multitasking scheduler's time-slice expiration handler. A looping instruction would be treated like any other compute-bound job.

Memory-mapped registers
On some computers, there were addresses that referred to registers rather than to primary storage, or to primary memory used to implement those registers. Although on some early computers there were register addresses at the high end of the address range, e.g., IBM 650, IBM 7070,  the trend has been to use only register address at the low end and to use only the first 8 or 16 words of memory (e.g. ICL 1900, DEC PDP-10). This meant that there was no need for a separate "add register to register" instruction – one could just use the "add memory to register" instruction.

In the case of early models of the PDP-10, which did not have any cache memory, a tight inner loop loaded into the first few words of memory (where the fast registers were addressable if installed) ran much faster than it would have in magnetic core memory.

Later models of the DEC PDP-11 series mapped the registers onto addresses in the input/output area, but this was primarily intended to allow remote diagnostics. Confusingly, the 16-bit registers were mapped onto consecutive 8-bit byte addresses.

Memory indirect and autoincrement
The DEC PDP-8 minicomputer had eight special locations (at addresses 8 through 15). When accessed via memory indirect addressing, these locations would automatically increment prior to use. This made it easy to step through memory in a loop without needing to use the accumulator to increment the address.

The Data General Nova minicomputer had 16 special memory locations at addresses 16 through 31. When accessed via memory indirect addressing, 16 through 23 would automatically increment before use, and 24 through 31 would automatically decrement before use.

Zero page
The Data General Nova, Motorola 6800 family, and MOS Technology 6502 family of processors had very few internal registers. Arithmetic and logical instructions were mostly performed against values in memory as opposed to internal registers. As a result, many instructions required a two-byte (16-bit) location to memory. Given that opcodes on these processors were only one byte (8 bits) in length, memory addresses could make up a significant part of code size.

Designers of these processors included a partial remedy known as "zero page" addressing. The initial 256 bytes of memory ($0000 – $00FF; a.k.a., page "0") could be accessed using a one-byte absolute or indexed memory address. This reduced instruction execution time by one clock cycle and instruction length by one byte. By storing often-used data in this region, programs could be made smaller and faster.

As a result, the zero page was used similarly to a register file. On many systems, however, this resulted in high utilization of the zero page memory area by the operating system and user programs, which limited its use since free space was limited.

Direct page
The zero page address mode was enhanced in several late model 8-bit processors, including the WDC 65816, the CSG 65CE02, and the Motorola 6809. The new mode, known as "direct page" addressing, added the ability to move the 256-byte zero page memory window from the start of memory (offset address $0000) to a new location within the first 64 KB of memory.

The CSG 65CE02 allowed the direct page to be moved to any 256-byte boundary within the first 64 KB of memory by storing an 8-bit offset value in the new base page (B) register. The Motorola 6809 could do the same with its direct page (DP) register. The WDC 65816 went a step further and allowed the direct page to be moved to any location within the first 64 KB of memory by storing a 16-bit offset value in the new direct (D) register.

As a result, a greater number of programs were able to utilize the enhanced direct page addressing mode versus legacy processors that only included the zero page addressing mode.

Scaled index with bounds checking
This is similar to scaled index addressing, except that the instruction has two extra operands (typically constants), and the hardware checks that the index value is between these bounds.

Another variation uses vector descriptors to hold the bounds; this makes it easy to implement dynamically allocated arrays and still have full bounds checking.

Indirect to bit field within word
Some computers had special indirect addressing modes for subfields within words.

The GE/Honeywell 600 series character addressing indirect word specified either 6-bit or 9-bit character fields within its 36-bit word.

The DEC PDP-10, also 36-bit, had special instructions which allowed memory to be treated as a sequence of fixed-size bit fields or bytes of any size from 1 bit to 36 bits. A one-word sequence descriptor in memory, called a "byte pointer", held the current word address within the sequence, a bit position within a word, and the size of each byte.

Instructions existed to load and store bytes via this descriptor, and to increment the descriptor to point at the next byte (bytes were not split across word boundaries). Much DEC software used five 7-bit bytes per word (plain ASCII characters), with one bit per word unused. Implementations of C had to use four 9-bit bytes per word, since the 'malloc' function in C assumes that the size of an int is some multiple of the size of a char; the actual multiple is determined by the system-dependent compile-time operator sizeof.

Index next instruction
The Elliott 503, the Elliott 803, and the Apollo Guidance Computer only used absolute addressing, and did not have any index registers. Thus, indirect jumps, or jumps through registers, were not supported in the instruction set. Instead, it could be instructed to add the contents of the current memory word to the next instruction. Adding a small value to the next instruction to be executed could, for example, change a  into a , thus creating the effect of an indexed jump. Note that the instruction is modified on-the-fly and remains unchanged in memory, i.e. it is not self-modifying code. If the value being added to the next instruction was large enough, it could modify the opcode of that instruction as well as or instead of the address.

Glossary
Indirect:Data referred to through a pointer or address. Immediate:Data embedded directly in an instruction or command list. Index:A dynamic offset, typically held in an index register, possibly scaled by an object size. Offset:An immediate value added to an address; e.g., corresponding to structure field access in the C programming language. Relative:An address formed relative to another address. Post increment:The stepping of an address past data used, similar to in the C programming language, used for stack pop operations. Pre decrement:The decrementing of an address prior to use, similar to in the C programming language, used for stack push operations.

title: Addressing mode