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Talk:Addressing mode

Reason for article creation
Have started this as it had a link from RISC. Not very good yet, will look at more sometime. Mat-C 15:06, 17 Jul 2004 (UTC)

This is not correct
On some RISC machines, the effective address is obtained by using the top 4 bits of the current program counter with the 28 bits given in the instruction. This can be done because RISC
 * (This partial comment was left by Ruud_Koot on according to the talk page history.  I am unsure what he was getting at. --Kelerain (talk) 03:12, 14 January 2008 (UTC))
 * OK, it's old, but Rudd was probably getting at MIPS (See any Patterson & Hennessy) refers to pseudo direct addressing, which uses high order 4 bits of PC + a 26 bit immediate offset shifted 2 bits to form a 32 bit address. Darned if I see it mentioned on this page, while thousands of students are taught it routinely.) Did I miss it? — Preceding unsigned comment added by 209.65.48.3 (talk) 16:13, 19 November 2013 (UTC)

The part on Multi-level memory indirect states that you can get an infinite loop trying if one reference to itself. This is not true as you would have to specify a level of deepness at the instruction, else we won't know when to end, and thus it isn't an infinite loop. —Preceding unsigned comment added by Special:Contributions/ (talk)

 * Multi-level indirect can result in an infinite loop in the case when a 'word' is bigger than an address and when one of the bits unused for the address is is used to indicate another level of indirect addressing (e.g. PDP-6, PDP-10), i.e. the level of deepness is NOT specified in the instruction. The addressing chain continues for as long as the indirect bits are set in each address referenced. If one of the addresses refers to some word earlier in the chain (including possibly itself) then a infinite indirection loop appears. Murray Langton (talk) 14:56, 3 March 2008 (UTC)

 * On the PDP-10, if you did create an infinite-address-loop, the CPU would time out the instruction and generate an interrupt. Mzellers (talk) 23:20, 27 September 2011 (UTC)

Index next instruction
My understanding is the machines mentioned in the "Index next instruction" section did something more like this when the " " instruction was executed:
 * start loading the next instruction (possibly from ROM) normally
 * Normally the CPU stores each instruction it reads into the IR (instruction register) -- but when executing the "index" instruction, instead it stores the *sum* into the IR -- the sum of the instruction currently being read and the accumulator.
 * Then it goes on to executing the instruction in the IR normally.

So I think the "Index next instruction" section is slightly misleading in it's "self-modifying code" comment. This is very similar to self-modifying code, but it's not exactly the same -- the sum is not actually written back out to program memory, and it works exactly the same whether the instruction is in RAM or ROM.

Could someone with more expertise confirm if my understanding is correct? (Perhaps my understanding is incorrect, and these machines, like MIX, really do require self-modifying code, which must be placed in RAM -- ROM won't work).

If my understanding is correct, could you fix the "Index next instruction" section to make it more accurate? --68.0.124.33 (talk) 04:02, 15 March 2008 (UTC)

The description in the self-modifying code article of the "EXECUTE" instruction makes it sound similar to this "INDEX" instruction. Are they really the same, or is there some significant difference I am missing? --68.0.124.33 (talk) 05:12, 25 November 2010 (UTC)

 * Your interpretation is correct. I have modified the article (feel free to tweak the article more if it's still unclear) Murray Langton (talk) 11:01, 25 November 2010 (UTC)

Is 'Skip' in the right place?
'Skip' has been in the article as an addressing mode since March 2008. I agree that it should be in the article (it was the only conditional control intruction for Dec PDP-8 and Data General Nova), but I'm not sure if it is in quite the correct place within the article. Does anyone know of any current computers which use this addressing mode; if there are some significant current computers which use 'skip' I'll leave that section where it is (possibly with revised wording), if there are some relatively obscure current computers I propose to move that section further down under 'Other addressing modes', otherwise I propose to move it down under 'Obsolete addressing modes'. Murray Langton (talk) 15:25, 1 December 2008 (UTC)

 * Both the Atmel AVR instruction set and the PIC microcontroller instruction set has some instructions that use the "skip" addressing mode ( addressing_mode ). All conditional instructions for PIC microcontrollers with "12-bit core" and the "14-bit core" use the skip addressing mode -- the only way to implement a loop on these chips is to use such a "skip" instruction to skip over an unconditional branch instruction. I've been told that Microchip sold more units of such microcontrollers in 2006 than the total unit sales of any other CPU manufacturer (still looking for a WP:RELIABLE reference that lists unit sales of the top CPU manufacturers in some recent year, even if it contradicts this rumor). I hope you agree with me that a CPU family that is apparently currently selling in higher volume than any other CPU family is "current" and "not obscure". --68.0.124.33 (talk) 19:15, 1 December 2008 (UTC)

 * Thank you for your prompt response. I agree that by sales volume it doesn't seem to be obscure; however I doubt if the micro-controllers you mention are all that well known, so I'll have to think about whether it stays where it is or moves down under 'Other addressing modes'. Murray Langton (talk) 21:56, 1 December 2008 (UTC)

 * On further thought I'm wondering if we need a new section 'Not an addressing mode' or similar to handle both the conditional instruction execution (ARM) and the 'skip' instruction. Any thoughts? Murray Langton (talk) 17:19, 2 December 2008 (UTC)

 * "well known": Is there some other other CPU that would be more well known, among people who solder or who use solderless breadboard? Just about every issue of Nuts and Volts for the past few years has a project for the PIC or the Atmel AVR (sometimes both). As far as I can tell, the PIC is more popular for ARRL projects than any other CPU.
 * The early PIC instruction set was designed decades ago, so it would be easy to say that it is "not current" -- but the same logic would force us to admit the x86 architecture instruction set is "not current" -- do we really want to admit that?
 * The ARM condition code and the conditional skip are functionally about the same -- so I agree that discussing them both in the same section is a good idea.
 * Perhaps also explicitly list in that section the normal, default, "execute the next sequential instruction" in order to comply with the WP:OBVIOUS guideline.
 * Perhaps call this section something like "sequential addressing"? --68.0.124.33 (talk) 21:39, 3 December 2008 (UTC)

 * Thanks for your suggestions. I'll meditate for a few days before changing anything. Murray Langton (talk) 08:39, 4 December 2008 (UTC)

 * I'm going to succumb to my completist tendencies, and add the one remaining way that the PC is modified. Because really, who wants to read a list of "Every possible way that the PC can be modified -- except for the most important one."? I'm making up a name for it off the top of my head -- we should probably find some references and adjust the name to what those references use. --68.0.124.33 (talk) 19:43, 8 December 2008 (UTC)

 * You mentioned the PDP-8; I see the PDP-8 and PDP-10 articles mention that they have "skip" instructions. I am tempted to mention the 4 CPUs we discussed in the "skip" section of this article. Is that a slipperly slope leading to every CPU ever built being listed under every addressing mode it supports? --68.0.124.33 (talk) 04:27, 18 December 2008 (UTC)

 * Unless an addressing mode is unique to a single computer family, I think it is probably better not to mention specific computers in relation to specific addressing modes. In the more general sections near the start of the article I think it may be reasonable to mention specific computer families as examples. Murray Langton (talk) 12:47, 18 December 2008 (UTC)

memory addressing mode in 8086
there are seven addressing modes in 8086 index,base,offset,index+offset,index+base,base+offset,index+base+offset —Preceding unsigned comment added by 116.71.188.163 (talk) 08:12, 16 February 2010 (UTC)

Comments on IBM mainframe (System/360, System/390 etc.) not correct
The references to addressing modes on IBM mainframe systems are misleading.

Until very recently there was only one way for application code to refer to operands or branch address and that was that all addresses are formed from a base address, an index address, and a displacement value. The Relative and Immediate Instruction Facility added instructions to address data using relative values. The size of the base and index values changed over the years from 24 to 31 and now 64 bits and the displacement has changed as well, but in all cases the instruction contained base and index register designations and the actual value of the displacement. Still, none of these things are called "addressing modes" in IBM terminology which by the way has a 50+ year history.

However...

In IBM terminology, addressing mode has to do with control register values and PSW (program status word) settings that determine how instructions and operands are fetched. There are 4 addressing modes in z/OS:

 * 1 primary space mode (instructions and data fetched from current primary)
 * 2 ASC AR mode (intructions fetched from current primary, data fetched depending on contents of access register)
 * 3 secondary space mode (instructions fetched from current primary, data fetched from secondary)
 * 4 home space mode (instructions and data fetched from home address space)

Applications receive control and run exclusively in mode (1) above, primary space mode. The application programmer has no knowledge of this and no control over it. None of the HLL languages or Java have any provision for changing modes nor do they have any mode awareness.

Systems software often runs in modes (2) or (3) above in addition to mode (1) above. Very rarely, pieces of operating system code run in mode (4) above, home space mode. This mode is mostly used for creating new address spaces and coordinating user work in them.

See SA22-7832-07 z/Architecture Principles of Operation at http://publibz.boulder.ibm.com/epubs/pdf/dz9zr007.pdf and SA22-7614-07 z/OS V1R11.0 MVS Programming Extended Addressability Guide at http://publibz.boulder.ibm.com/epubs/pdf/iea2a570.pdf for complete information. 77.126.191.239 (talk) 16:43, 28 April 2011 (UTC)

 * For better or worse, many of IBM's terms have not been adopted by the rest of the computer industry. Relatively few company speak of "storage" rather than "memory", or speak of "direct access storage devices".

 * In this particular case, I suspect that the term "addressing mode", used in the sense of this article, dates back to the PDP-11, as per, for example, the PDP-11/20 Handbook. In the PDP-11, the opcode did not specify whether the instruction operands came from a register or memory or, if it came from memory, how the memory address was formed; the operands were specified by a combination of a 3-bit addressing mode and a 3-bit register number.  Some other instruction set architectures, such as the VAX and Motorola 68000 series, modeled themselves after the PDP-11 in that manner.

 * The GE-600 series used the term "address modifier", as per the GE-635 System Manual; however, it did not have the fully-orthogonal scheme that the PDP-11 did; one operand of an instruction would either be the accumulator, the multiplier/quotient register, or an index register, specified by the opcode, and the other operand would be in memory (so to move something from the AC to the MQ, you'd have to move it through memory).

 * In the PDP-6 and PDP-10 instruction sets, one operand would be a general-purpose register (called "accumulators"), and the other would be in "memory"; however, on the PDP-6 and earlier versions of the PDP-10, the general-purpose registers were stored in the low memory locations, so that accumulator-to-accumulator moves and arithmetic instructions were possible, and there was an option to put the GPRs into fast registers, in which case references to the low memory locations were redirected to the fast registers - later machines always had fast registers. The memory address was always formed in the same fashion, with the only "addressing mode" being an indirect mode specified by a single bit.  The UNIVAC 1100/2200 series was similar, with accumulators and index registers mapped into low memory.

 * S/360, as the page notes, didn't have a PDP-11ish addressing mode concept; for the load/store/binary-and-floating-point arithmetic instructions, one operand is in a GPR, and the other could be in memory or a GPR, with the difference being indicated by the opcode. Memory addresses were formed by adding the displacement, the index register, and the base register (with R0 meaning "zero"), and there was no indirect addressing, so there were no explicit "addressing mode" fields.

 * The MIPS has three-register versions of arithmetic instructions, with all operands in registers, and immediate versions, with one operand being a constant in the instruction; there is no explicit "addressing mode" field specifying that. Load/store instructions always reference memory in the same fashion, except for a "load immediate" instruction that loads the upper part of a GPR from an immediate constant - large constants are synthesized from multiple instructions.  Other RISC architectures are similar.

 * When comparing instruction sets, it's useful to have some concept to indicate how operands are specified, and to have a term for it. For better or worse, "addressing mode" has come to be used for that by a large number of people, IBM's use of the term nonwithstanding (does that use really date back 50 years?  50 years ago, S/360 was introduced, and S/360 didn't have address spaces - that was, I think, an S/390ism) - so it didn't have "primary space", "secondary space", etc., nor did it have 31-bit addresses - another S/390ism - and thus didn't have 24-bit, 31-bit, or 64-bit mode.)

 * So I'm afraid you will have to live with references to S/3x0 and z/Architecture addressing modes. You may want to add a note at the beginning that IBM used the term "addressing mode" differently, but there's nothing misleading about discussing S/3x0's ways of referring to operands in this article. Guy Harris (talk) 23:37, 13 April 2014 (UTC)
 * For S/360, they are called "instruction format types". Well, the RR, RX, and RS, refer to register, indexed, and storage address modes, but they don't seem to describe them separately from instruction formats. Well, S is described for the S-type address constant. Gah4 (talk) 23:44, 10 July 2024 (UTC)
 * For S/360, they are called "instruction format types". Well, the RR, RX, and RS, refer to register, indexed, and storage address modes, but they don't seem to describe them separately from instruction formats. Well, S is described for the S-type address constant. Gah4 (talk) 23:44, 10 July 2024 (UTC)

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Hi. I would like to ask you to elaborate how exactly my reduced clarity. IMO the old version doesn't meet WP:EXPLAINLEAD & MOS:INTRO. I especially question second sentence which has mangled words. And I also added notion on related concept — orthogonality. I want to return it back since both subjects are related. DAVRONOV A.A. ✉ ⚑ 22:50, 8 December 2019 (UTC)

 * Hi Alecander,

 * I'm currently a long way from home (New Zealand instead of England). I can give this my full attention when I get home on 18th December. In the mean time I will reinstate your comment re orthogonal instruction sets and have a look at the mangled words. Murray Langton (talk) 06:52, 9 December 2019 (UTC)

 * Ok, it's fine, have a safe trip. Looking forward to hearing you again. DAVRONOV A.A.  ✉ ⚑ 17:10, 9 December 2019 (UTC)

 * I'm now back in UK. When I first reverted your changes I may have been over-hasty due to jet-lag. Could you put you proposed text for the lead here so that we can consider it and work towards agreement. Murray Langton (talk) 07:34, 22 December 2019 (UTC)

(ab-)using address calculation unit in the CPU to do general arithmetics
At least on x86 assembly it is quite common to use (or abuse?) the address calculation unit of the CPU to do general arithmetics, e.g. additions or simple multiplications via the LEA opcode. It is faster and can be done in parallel to the normal ALU unit, so it is quite often, both in hand-written assembly code and in compiler-generated code. I don't know whether this trick also exists on other CPU architectures. Should this fact be mentioned here in the article? --RokerHRO (talk) 13:07, 17 November 2020 (UTC)
 * Yes, it is already there in the section 'Useful side effect'. Murray Langton (talk) 15:20, 17 November 2020 (UTC)
 * The S/360 LA instruction works similar to LEA, but with the S/360 base and index registers, and displacement. For S/360, the result is a 24 bit address. LA is often enough used in assembly code to add a constant to a register, if the result fits in 24 bits. It is also common for loading 12 bit unsigned constants into registers. The PDP-10 is too hard to describe here, but many addressing tricks were used with it. Gah4 (talk) 17:34, 10 July 2024 (UTC)
 * For z/Architecture the width of LA and LAY depends on the addressing mode: 24, 31 or 64. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 18:45, 10 July 2024 (UTC)
 * This article is about instruction-set features; the notion of (ab-)using an address calculation unit is microarchitectural, as whether there is a separate address calculation unit is a microarchitectural detail of a processor rather than a characteristic of the instruction set.
 * (Ab-)using a "compute effective address" instruction would be something appropriate to an article discussing instruction set features; it could mention microarchitectural reasons for doing so, in addition to "you can do the addition in fewer bytes of machine code", which is architectural. Guy Harris (talk) 20:45, 10 July 2024 (UTC)
 * Questions such as the speed, or otherwise, would be microarchitectural. But for user level instructions, they can be used however the programmer wants to use them. But yes, the comment about parallel processing doesn't apply. Gah4 (talk) 04:25, 11 July 2024 (UTC)
 * "This load instruction puts the effective address, rather than the {byte,halfword,word,etc.} at the effective address, into the destination register" is instruction-set-architectural, as is "this instruction can be used to put the sum of the source register and an N-bit immediate instant into the destination register". "This load instruction puts a sum computed by the address generation unit into the destination register", however, is microarchitectural, and may or may not be true on all implementations of the instruction set architecture in question. Guy Harris (talk) 06:24, 11 July 2024 (UTC)
 * I was noting the mention that it could be done in parallel. I am not so sure that "address generation unit" is microarchitectural. It could, for example, be a microcode subroutine, and so not separate logic. It is logically the same as other address generation, but it doesn't need to be physically the same. And address generation might be done by the same logic as other arithmetic operations, in which case it is still true. It might be faster, or it might not be. For hand generated code, some programmers make assumptions that some things are faster. Some thing XR must be faster than SR, as it doesn't need to do carry. Code generators using dynamic programming can generate code with no unwarranted assumptions. Gah4 (talk) 10:09, 11 July 2024 (UTC)
 * Where it is done and which are faster are implementation issues, not architectural. In general, an instruction sequence that is faster on one processor may be slower on another, so hand optimization can be dicey unless you know which model the code will run on. Back in the S/360 era there were endless arguments over whether to use SLR, SR or XR to clear a register, but on modern processors they all take the same amount of time. I'm confident that this phenoneum is not limited to IBM. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 11:11, 11 July 2024 (UTC)
 * I am not so sure that "address generation unit" is microarchitectural. It could, for example, be a microcode subroutine The use of microcode, and the microcode itself, is microarchitectural for most, if not all, instruction sets. At the abstraction level of an instruction set, there is a process of address generation, the details of which are hidden in the microarchitecture.
 * The only thing you can say about "load effective address" instructions, at the instruction set level, is what they do, not how they do it, or how fast they do it, or how what the operations it involves are assigned to particular units in the CPU and scheduled at the hardware level. I.e, It is faster and can be done in parallel to the normal ALU unit are statements that might or might not be true of a given implementation of an instruction set, just as anything such as the address calculation unit of the CPU might or might not be true of a given implementation of an instruction set - there might not be an "address calculation unit" in a given CPU.  Saying that it may be faster, and that it might be more likely to be done in parallel with other operations (in modern CPUs, two separate additions, neither of which is done as part of effective-address formation, might be done in parallel), can be true at the instruction-set level, because they're vague enough not to commit to how a particular instruction set is implemented.
 * If you want to talk about what the "load effective address unit" involves in some ISA that has multiple implementations, speak of the address generation process, not the address generation unit. Guy Harris (talk) 11:52, 11 July 2024 (UTC)
 * Where it is done and which are faster are implementation issues, not architectural. In general, an instruction sequence that is faster on one processor may be slower on another, so hand optimization can be dicey unless you know which model the code will run on. Back in the S/360 era there were endless arguments over whether to use SLR, SR or XR to clear a register, but on modern processors they all take the same amount of time. I'm confident that this phenoneum is not limited to IBM. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 11:11, 11 July 2024 (UTC)
 * I am not so sure that "address generation unit" is microarchitectural. It could, for example, be a microcode subroutine The use of microcode, and the microcode itself, is microarchitectural for most, if not all, instruction sets. At the abstraction level of an instruction set, there is a process of address generation, the details of which are hidden in the microarchitecture.
 * The only thing you can say about "load effective address" instructions, at the instruction set level, is what they do, not how they do it, or how fast they do it, or how what the operations it involves are assigned to particular units in the CPU and scheduled at the hardware level. I.e, It is faster and can be done in parallel to the normal ALU unit are statements that might or might not be true of a given implementation of an instruction set, just as anything such as the address calculation unit of the CPU might or might not be true of a given implementation of an instruction set - there might not be an "address calculation unit" in a given CPU.  Saying that it may be faster, and that it might be more likely to be done in parallel with other operations (in modern CPUs, two separate additions, neither of which is done as part of effective-address formation, might be done in parallel), can be true at the instruction-set level, because they're vague enough not to commit to how a particular instruction set is implemented.
 * If you want to talk about what the "load effective address unit" involves in some ISA that has multiple implementations, speak of the address generation process, not the address generation unit. Guy Harris (talk) 11:52, 11 July 2024 (UTC)

Nomenclature: Branch versus Jump
The documentation for IBM Z uses the term branch, with jump a synonym for branch relative. I believe that the article should at least note this in passing.

Has anybody done a survey of nomenclature on other architectures? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 13:27, 1 May 2024 (UTC)
 * The documentation for IBM Z uses the term branch, with jump a synonym for branch relative. And the PDP-11 uses "branch" for instructions in which the branch target is specified by an 8-bit signed PC-relative offset and "jump" for instructions (jump, jump to subroutine) in which an arbitrary address mode specifies a source that contains the branch target address (e.g., JMP R2 jumps to the address contained in R2). The VAX uses the same convention for "PC-relative with a signed offset in the instruction" vs. "arbitrary target" (although the more complicated procedure call instructions use "call"); Alpha is also similar, although the jump instructions have the target specified by a register.  So DEC's convention, at least for their 8-bit-byte-oriented architectures, are somewhat opposite to the S/3x0 convention.
 * Has anybody done a survey of nomenclature on other architectures? Well...
 * x86 calls them all jumps, including the PC IP-relative control-transfer instruction introduced in x86-64 (except for the loop and procedure call instructions).
 * 32-bit ARM calls the PC-relative transfer-of-control instructions branches. "Branch to an address in a register" is called a "move" - use the MOV instruction to move the register in question to R15, which is the PC.  "Branch to an address stored in memory" is similarly called "load".  To use those for procedure calls, you precede them with a MOV of R15 to R14, where the latter is the "link register", into which the PC-relative "branch to subroutine" puts the return address.
 * 64-bit ARM calls them all branches, and are Alpha-like in that most branches are relative, but they also have "target is in a register" transfer-of-control and procedure-call instructions, also called branches, except for the "return from subroutine", which is called RET; it's a "branch to address in a register", but also hints that it's a return.
 * SPARC calls the PC-relative instructions branches, except for the very-long-displacement procedure-call instruction "call", and the arbitrary-target instruction a jump.
 * Power ISA calls them all branches (unsurprisingly for an IBM-designed ISA).
 * It's probably a mix for other ISAs; I've limited that survey to DEC 8-bit byte (because the first of them, the PDP-11, was the first one that came to mind with "branch" for PC-relative and "jump" for others) ISAs and the main currently still living ISAs.
 * So there's no consensus, although "branch" seems to be more popular these days. Guy Harris (talk) 19:35, 1 May 2024 (UTC)
 * It's dated, but Bendix has used the term transfer on the G-20, GE has used it on, e.g., the GE 635, Honeywell has used it on, e.g., the H-800, IBM has used it on, e.g., the 7090, and RCA has used it on, e.g., the 501. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 13:49, 10 July 2024 (UTC)
 * And then there is the PDP-10, where JUMP doesn't jump and SKIP doesn't skip. Gah4 (talk) 04:28, 11 July 2024 (UTC)
 * You're just being silly. The JUMPx and SKIPx instructions jump or skip when the condition x is true. But null x means never, just as x=A means always. Macrakis (talk) 04:48, 11 July 2024 (UTC)
 * To be clear, the PDP-10 calls all transfers of control "jumps". It has a fixed-width instruction and 18-bit word addresses everywhere. The op codes that perform jumps are:
 * JUMPx, where x is a condition like LE (less than or equal), etc. Unconditional jump is JUMPA.
 * JRST 'jump and restore flags', JFCL 'jump if flag set then clear' -- as it happens, with no flags specified (in the AC field), JRST was the fastest unconditional jump on the KA-10, and JFCL was the fastest no-op
 * Various subroutine call and return: PUSHJ/POPJ, JSP, rarely used: JSR, JRA, JSA. The J in these instructions of course means jump.
 * The PDP-10 also has many conditional-skip instructions. Not just the SKIPx family, but also CAxy (compare accumulator) and Txyz (test). These do not have an address argument because they use their two arguments (accumulator and address) for other things. The most common case is skip-instruction followed by an unconditional jump, but other combinations are possible, like the (in) famous TRCE / TRCE / TRCE which swaps two bits in a word (see HAKMEM item 162). --Macrakis (talk) 15:32, 11 July 2024 (UTC)
 * Someone else was being silly, and I still remember it. The 6809 has relative branch instructions: BRA (branch always) and BRN (branch never). Also, 16 bit offset LBRA and LBRN. There are also other conditional branch for other flag bits. There is only unconditional JMP for absolute address. Gah4 (talk) 08:22, 12 July 2024 (UTC)
 * Someone else was being silly, and I still remember it. The 6809 has relative branch instructions: BRA (branch always) and BRN (branch never). Also, 16 bit offset LBRA and LBRN. There are also other conditional branch for other flag bits. There is only unconditional JMP for absolute address. Gah4 (talk) 08:22, 12 July 2024 (UTC)
 * Someone else was being silly, and I still remember it. The 6809 has relative branch instructions: BRA (branch always) and BRN (branch never). Also, 16 bit offset LBRA and LBRN. There are also other conditional branch for other flag bits. There is only unconditional JMP for absolute address. Gah4 (talk) 08:22, 12 July 2024 (UTC)

title: Talk:Addressing mode


text:
Talk:Open-field system

Early comments
I'm confused. Why was putting fences around fields such a big deal? Josh Cherry 15:08, 17 Jul 2004 (UTC)

 * It was a fundamental change to the property system - from common ownership to exclusive private ownership. It was a big social change as well, as it concentrated economic power in a relatively few people's hands. -- ChrisO 09:57, 19 Jul 2004 (UTC)

 * I meant that it wasn't clear to me from the article why the need for large enclosed fields led to such sweeping economic and social changes. If changes to agriculture required it, why not just build some fences and leave economic relations unchanged? Josh Cherry 23:44, 19 Jul 2004 (UTC)

It was not a change from common ownership to exclusive private ownership. It was a change from private ownership with some communal rights and with communal management - that is, an individual owned the strip, and had the right to the crop, but people in the community (not always all, sometimes it was restricted to other landowners only) might have a right to graze the cattle on the strips after the harvest. It was communally managed, because the manor community (in England at least) would set all the strips in one field to be fallow at the same time, so they could graze all the commoners cattle there without worrying about anyone's crop being eaten.

Open fields were originally needed because the ploughs were so heavy to cut through the heavy clay soil that it just made more sense to have as long a way to have them pulled before trying to turn them around. As for technological innovation after, there is little evidence to show that enclosed fields were more productive than open. But they were more easily sold and rented to commercial farmers, which was most important for landowners.

The reason it was a disruptive change was that a) people lost this right of grazing, b) the costs of enclosure were high enough to force many small landholders to sell their newly enclosed land because they could not afford to fence it, etc and c) it meant the community no longer worked together in land management. But many places were enclosed early, and in other places, there were very few small landholders and most landless had lost all common rights.  There is a huge debate among historians right now about how disruptive/destructive to economic and social relationships enclosure was - the answer (currently) seems to be that in some places, it was a huge transformation and made people more wage-dependent, and in other places, those same changes had already come without enclosure, but through a concentration of landownership, and the increase in landless people. - *jb 17:39, 9 Jun 2005 (UTC)

I also added the categories Middle Ages and Agriculture- open fields were used in many places in Europe, and contine to be. - *jb 18:02, 9 Jun 2005 (UTC)

Braunton
An anon user added a link to http://www.explorebraunton.org suggesting that it would provide more information about Braunton. As yet, the page contains no information of any kind, however, it looks like it might be an 'official' (Devon CC) site, so it could prove useful in the future.

EdJogg (talk) 17:26, 14 August 2008 (UTC)

Low importance?
Given that the open field system was the economic and agricultural system governing the lives of half the people in Europe for hundreds of years, I find it dubious that this article is deemed to be of "low importance." Smallchief (talk 22:44, 18 March 2014 (UTC)
 * @ I graded low on the importance to the Economics project scale because it may not be relevant to a modern economist or an understanding of economics.  However, you are probably right that it should be a mid, as it does add depth of understanding to economics.  Related articles are Enclosure which is at mid, and the more specific Inclosure Acts which is at low.Jonpatterns (talk) 12:12, 19 March 2014 (UTC)

Allotment Gardens
This section is inappropriate at this point. and could easily confuse. Allotment gardens have an entirely different, relatively modern, statutory origin, clearly explained by the National Allotment Garden Society on their site. Manninagh1958 (talk) 09:57, 20 August 2016 (UTC)
 * Yes, I agree. Unless someone raises objections in the next few days, I'll delete this section and put only a link into allotment gardens.Smallchief (talk  10:34, 20 August 2016 (UTC)

Controversies and Inefficiencies
The tragedy of the commons part of this section is dubious. For example:

 * However, the creator of the term "tragedy of the commons", Garrett Hardin, pointed out that the pastures of England were "protected from ruin by limiting each tenant to a fixed number of animals". Thus, Hardin says the commons were "managed", the "logical equivalent of socialism...which may be good or bad depending on the quality of the management."

The cited source does not contain either of those quotes. I tried searching for the quotes and the only references to them on the internet seem to originate from this page. Even if these were real quotes, Hardin's essay isn't supported by evidence from an actual open field system:

 * The tragedy of the commons develops in this way. Picture a pasture open to all. It is to be expected that each herdsman will try to keep as many cattle as possible on the commons. [...] As a rational being, each herdsman seeks to maximize his gain. Explicitly or implicitly, more or less consciously, he asks, "What is the utility to me of adding one more animal to my herd?"

He never uses an example of an actual open field system to explain an actual tragedy of the commons. He has you imagine one, and then uses refuted economic/sociological theories (rational self-maximizers, utilitarianism) to explain how it must logically happen. The essay is little more than a pro-privatization think piece and there's no good reason to include it in an article about the actual open field system.

--Ackhuman (talk) 16:16, 22 August 2019 (UTC)

 * I've added a footnote citing the source of the quote by Hardin. Hardin and the open-field system are often used as examples of the inefficiencies of common ownership, and this quote from him is a qualifier to what he had previously said in his famous essay.

 * I believe this section as it is now written is necessary and balanced. I do not believe that the present text is a right-wing plea for capitalism and private ownership.  Rather, this section points out that the open-field system lasted 1,000 years and that its demise was controversial, lamented by many, and accompanied by much hardship for displaced farmers. Smallchief  (talk)

 * I agree with Ackhuman that this section is dubious, and in my opinion it violates the Neutral Point of View rule. The source of this analysis is Garrett Hardin - a right-wing white nationalist. The source was published by Liberty Fund - a far-right foundation that's heavily linked with the US Republican Party. The content of the quote calls manorialism the "logical equivalent of socialism," which is much closer to a right-wing rhetorical flourish than any sort of objective or even coherent economic statement - in fact, the source itself seems to be primarily a propaganda piece aimed at making this exact conflation. And yet, the article treats both this source and this politically charged statement as objective and uncontested. Seems like a textbook definition of "undue weight" to me. I edited the section to simply remove the "logical equivalent of socialism" clause for now, and I would also recommend expanding on the other sources in the paragraph (Dahlman and Cox) by including their criticisms of Hardin's analysis.
 * Combefere (talk) 06:31, 13 March 2021 (UTC)

Your analysis falters with the assumption that comparing something to socialism means that it is bad -- which is the opinion of the Republican Party in the United States. However, contrary to the American Repubs (and defensive Dems), in most of the world "socialism" is a word of favorable connotation. The use of the word "socialism" in this article does not imply that socialism is either good or bad, but only that the open field system has been compared to socialism. Nor does the present text, proclaim the open-field system to be a bad thing. Rather the language of the article points out that the open field system lasted a thousand years and that it was replaced with "a harsher, more competitive and capitalistic society." That's hardly a right-wing clarion call for the virtues of capitalism. If this section of the wikipedia article was the work of a right wing ideologue as you imply, that conclusion about capitalism from a reliable source would most certainly not be included in the article. 'Balance" means that all relevant and verifiable opinions are represented fairly.

Likewise, your characterization of Hardin as a "right-wing white nationalist" is dependent on 21st century definitions of "right" and "left." Hardin was an ecologist and he both influenced and reflected the views of his time -- which in the late 1960s were concerns about environmental degradation, over-population, and "the limits of growth." These were issues important to the political left of the day -- not the right. On the environment, he was a leftist; on population control he was a leftist; on immigration his opinion was closer to the left of his day than to the right. It's simplistic to reject his whole body of work because he later became identified as a right wing white nationalist. Using that criteria, we would characterize Benjamin Franklin as a white nationalist, because he spoke out against the immigration of "swarthy" Germans to Pennsylvania in the 1760s. Smallchief (talk) 09:19, 13 March 2021 (UTC)

 * My analysis is not at all dependent on the assumption that comparing anything to socialism means that it is bad. It is also not at all dependent on the idea that this section is a "right-wing clarion call for the virtues of capitalism."  My analysis is that Hardin's specific conflation -- not comparison -- of manorialism to socialism is:

 * Not representative of a consensus of economic experts
 * This is not sufficiently sourced as even the opinion of one economic expert, as Hardin was not an economist.
 * Not coherent enough to be taken as meaningful economic analysis
 * Clearly part of a rhetorical campaign by both himself individually and the Liberty Fund to redefine (in a childishly simplistic manner) and denigrate socialism.

 * Socialism is not "when management" and no serious economist would even entertain such a meaningless and nonsensical statement. Manorialism was not Socialism in any sense of the word. It was not the "logical equivalent of socialism."  Including this clause -- even if it were alongside a separate quote from another economist who disputed it which it is not -- would violate the undue weight section of the NPOV.  It promotes a viewpoint that is held by an extreme minority (if any) of economists and gives not only a false impression of parity but a false impression of consensus to this viewpoint.

 * I'll add further that this viewpoint (that Manorialism was the "logical equivalent of socialism") is not relevant to the article, so its inclusion serves no neutral purpose. The edited quotation includes the actual kernel of economic analysis (that the Open-Field System was a managed system and its efficiency depended on the quality of the management) without the offhanded politically charged jab.
 * Combefere (talk) 03:47, 16 March 2021 (UTC)

Conflicting Data in the Example
The numbers given for Elton, Cambridgeshire in this article seem to conflict with the numbers given in the article for Elton, here it's stated as 13 hides with a population of 500-600, in the Elton article it's stated as 28 hides with a population of 129-185. — Preceding unsigned comment added by 180.149.192.144 (talk) 23:30, 9 September 2019 (UTC)

Problems that faced agriculture in europe under open field
Answers 197.186.2.242 (talk) 19:02, 23 February 2022 (UTC)

Dictatorship in europe
English 197.186.5.235 (talk) 09:45, 11 May 2022 (UTC)

The article assumes the Marxist view of history is correct.
The article talks of the "rise of capitalism" with the invention of "the concept that land was a commodity that could be bought and sold" - even in the Middle Ages land was bought and sold in England and other European countries (as it has been in Roman times) and the Open Field system was far from universal. 2A02:C7C:E183:AC00:FC40:383D:A191:2435 (talk) 20:17, 6 October 2023 (UTC)

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: Talk:Open-field system


text:
Pastebin

A pastebin or text storage site  is a type of online content-hosting service where users can store plain text (e.g. source code snippets for code review via Internet Relay Chat (IRC)). The most famous pastebin is the eponymous pastebin.com. Other sites with the same functionality have appeared, and several open source pastebin scripts are available. Pastebins may allow commenting where readers can post feedback directly on the page. GitHub Gists are a type of pastebin with version control.

History
Pastebins developed in the late 1990s to facilitate IRC chatrooms devoted to computing, where users naturally need to share large blocks of computer input or output in a line-oriented medium. In such chatrooms, sending messages containing large blocks of computer data can disrupt conversations, which can be closely interleaved. When users send such messages, they are often warned to instead use pastebins or risk being banned from the service. Contrarily, a reference to a pastebin entry is a one-line hyperlink.

A new class of IRC bot has evolved. In a chatroom that is largely oriented around a few pastebins, nothing more needs to be done after a post at its pastebin. The receiving party then awaits a bot announcing the expected posting by the known user.

After the use of the pastebin.pl pastebin for a data breach, Pastebin started monitoring the site for illegally pasted data and information, leading to a backlash from Anonymous. Hacktivists teamed up with an organization calling itself the People's Liberation Front, launching an alternative called AnonPaste.

title: Pastebin


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Hilbert's axioms

Hilbert's axioms are a set of 20 assumptions proposed by David Hilbert in 1899 in his book Grundlagen der Geometrie   (tr. The Foundations of Geometry) as the foundation for a modern treatment of Euclidean geometry. Other well-known modern axiomatizations of Euclidean geometry are those of Alfred Tarski and of George Birkhoff.

The axioms
Hilbert's axiom system is constructed with six primitive notions: three primitive terms: and three primitive relations:
 * point;
 * line;
 * plane;
 * Betweenness, a ternary relation linking points;
 * Lies on (Containment), three binary relations, one linking points and straight lines, one linking points and planes, and one linking straight lines and planes;
 * Congruence, two binary relations, one linking line segments and one linking angles, each denoted by an infix ≅.

Line segments, angles, and triangles may each be defined in terms of points and straight lines, using the relations of betweenness and containment. All points, straight lines, and planes in the following axioms are distinct unless otherwise stated.

I. Incidence

 * 1) For every two points A and B there exists a line a that contains them both. We write AB = a or BA = a. Instead of "contains", we may also employ other forms of expression; for example, we may say "A lies upon a", "A is a point of a", "a goes through A and through B", "a joins A to B", etc. If A lies upon a and at the same time upon another line b, we make use also of the expression: "The lines a and b have the point A in common", etc.
 * 2) For every two points there exists no more than one line that contains them both; consequently, if AB = a and AC = a, where B ≠ C, then also BC = a.
 * 3) There exist at least two points on a line. There exist at least three points that do not lie on the same line.
 * 4) For every three points A, B, C not situated on the same line there exists a plane α that contains all of them. For every plane there exists a point which lies on it. We write ABC = α. We employ also the expressions: "A, B, C lie in α"; "A, B, C are points of α", etc.
 * 5) For every three points A, B, C which do not lie in the same line, there exists no more than one plane that contains them all.
 * 6) If two points A, B of a line a lie in a plane α, then every point of a lies in α. In this case we say: "The line a lies in the plane α", etc.
 * 7) If two planes α, β have a point A in common, then they have at least a second point B in common.
 * 8) There exist at least four points not lying in a plane.

II. Order

 * 1) If a point B lies between points A and C, B is also between C and A, and there exists a line containing the distinct points A, B, C.
 * 2) If A and C are two points, then there exists at least one point B on the line AC such that C lies between A and B.
 * 3) Of any three points situated on a line, there is no more than one which lies between the other two.
 * 4) Pasch's Axiom: Let A, B, C be three points not lying in the same line and let a be a line lying in the plane ABC and not passing through any of the points A, B, C. Then, if the line a passes through a point of the segment AB, it will also pass through either a point of the segment BC or a point of the segment AC.

III. Congruence

 * 1) If A, B are two points on a line a, and if A′ is a point upon the same or another line a′, then, upon a given side of A′ on the straight line a′, we can always find a point B′ so that the segment AB is congruent to the segment A′B′. We indicate this relation by writing AB ≅ A′B′. Every segment is congruent to itself; that is, we always have AB ≅ AB. We can state the above axiom briefly by saying that every segment can be laid off upon a given side of a given point of a given straight line in at least one way.
 * 2) If a segment AB is congruent to the segment A′B′ and also to the segment A″B″, then the segment A′B′ is congruent to the segment A″B″; that is, if AB ≅ A′B′ and AB ≅ A″B″, then A′B′ ≅ A″B″.
 * 3) Let AB and BC be two segments of a line a which have no points in common aside from the point B, and, furthermore, let A′B′ and B′C′ be two segments of the same or of another line a′ having, likewise, no point other than B′ in common. Then, if AB ≅ A′B′ and BC ≅ B′C′, we have AC ≅ A′C′.
 * 4) Let an angle ∠ (h,k) be given in the plane α and let a line a′ be given in a plane α′. Suppose also that, in the plane α′, a definite side of the straight line a′ be assigned. Denote by h′ a ray of the straight line a′ emanating from a point O′ of this line. Then in the plane α′ there is one and only one ray k′ such that the angle ∠ (h, k), or ∠ (k, h), is congruent to the angle ∠ (h′, k′) and at the same time all interior points of the angle ∠ (h′, k′) lie upon the given side of a′. We express this relation by means of the notation ∠ (h, k) ≅ ∠ (h′, k′).
 * 5) If the angle ∠ (h, k) is congruent to the angle ∠ (h′, k′) and to the angle ∠ (h″, k″), then the angle ∠ (h′, k′) is congruent to the angle ∠ (h″, k″); that is to say, if ∠ (h, k) ≅ ∠ (h′, k′) and ∠ (h, k) ≅ ∠ (h″, k″), then ∠ (h′, k′) ≅ ∠ (h″, k″).
 * If, in the two triangles ABC and A′B′C′ the congruences AB ≅ A′B′, AC ≅ A′C′, ∠BAC ≅ ∠B′A′C′ hold, then the congruence ∠ABC ≅ ∠A′B′C′ holds (and, by a change of notation, it follows that ∠ACB ≅ ∠A′C′B′ also holds).

IV. Parallels

 * 1) Euclid's Axiom: Let a be any line and A a point not on it. Then there is at most one line in the plane, determined by a and A, that passes through A and does not intersect a.

V. Continuity

 * 1) Axiom of Archimedes: If AB and CD are any segments then there exists a number n such that n segments CD constructed contiguously from A, along the ray from A through B, will pass beyond the point B.
 * 2) Axiom of line completeness: An extension (An extended line from a line that already exists, usually used in geometry) of a set of points on a line with its order and congruence relations that would preserve the relations existing among the original elements as well as the fundamental properties of line order and congruence that follows from Axioms I-III and from V-1 is impossible.

Hilbert's discarded axiom
Hilbert (1899) included a 21st axiom that read as follows:
 * II.4. Any four points A, B, C, D of a line can always be labeled so that B shall lie between A and C and also between A and D, and, furthermore, that C shall lie between A and D and also between B and D.

This statement is also known as Pasch's theorem.

E. H. Moore and R. L. Moore independently proved that this axiom is redundant, and the former published this result in an article appearing in the Transactions of the American Mathematical Society in 1902.

Before this, Pasch's axiom, now listed as II.4, was numbered II.5.

Editions and translations of Grundlagen der Geometrie
The original monograph, based on his own lectures, was organized and written by Hilbert for a memorial address given in 1899. This was quickly followed by a French translation, in which Hilbert added V.2, the Completeness Axiom. An English translation, authorized by Hilbert, was made by E.J. Townsend and copyrighted in 1902. This translation incorporated the changes made in the French translation and so is considered to be a translation of the 2nd edition. Hilbert continued to make changes in the text and several editions appeared in German. The 7th edition was the last to appear in Hilbert's lifetime. In the Preface of this edition Hilbert wrote:
 * "The present Seventh Edition of my book Foundations of Geometry brings considerable improvements and additions to the previous edition, partly from my subsequent lectures on this subject and partly from improvements made in the meantime by other writers. The main text of the book has been revised accordingly."

New editions followed the 7th, but the main text was essentially not revised. The modifications in these editions occur in the appendices and in supplements. The changes in the text were large when compared to the original and a new English translation was commissioned by Open Court Publishers, who had published the Townsend translation. So, the 2nd English Edition was translated by Leo Unger from the 10th German edition in 1971. This translation incorporates several revisions and enlargements of the later German editions by Paul Bernays.

The Unger translation differs from the Townsend translation with respect to the axioms in the following ways:
 * Old axiom II.4 is renamed as Theorem 5 and moved.
 * Old axiom II.5 (Pasch's Axiom) is renumbered as II.4.
 * V.2, the Axiom of Line Completeness, replaced:
 * Axiom of completeness. To a system of points, straight lines, and planes, it is impossible to add other elements in such a manner that the system thus generalized shall form a new geometry obeying all of the five groups of axioms. In other words, the elements of geometry form a system which is not susceptible of extension, if we regard the five groups of axioms as valid.

 * The old axiom V.2 is now Theorem 32.

The last two modifications are due to P. Bernays.

Other changes of note are:
 * The term straight line used by Townsend has been replaced by line throughout.
 * The Axioms of Incidence were called Axioms of Connection by Townsend.

Application
These axioms axiomatize Euclidean solid geometry. Removing five axioms mentioning "plane" in an essential way, namely I.4–8, and modifying III.4 and IV.1 to omit mention of planes, yields an axiomatization of Euclidean plane geometry.

Hilbert's axioms, unlike Tarski's axioms, do not constitute a first-order theory because the axioms V.1–2 cannot be expressed in first-order logic.

The value of Hilbert's Grundlagen was more methodological than substantive or pedagogical. Other major contributions to the axiomatics of geometry were those of Moritz Pasch, Mario Pieri, Oswald Veblen, Edward Vermilye Huntington, Gilbert Robinson, and Henry George Forder. The value of the Grundlagen is its pioneering approach to metamathematical questions, including the use of models to prove axioms independent; and the need to prove the consistency and completeness of an axiom system.

Mathematics in the twentieth century evolved into a network of axiomatic formal systems. This was, in considerable part, influenced by the example Hilbert set in the Grundlagen. A 2003 effort (Meikle and Fleuriot) to formalize the Grundlagen with a computer, though, found that some of Hilbert's proofs appear to rely on diagrams and geometric intuition, and as such revealed some potential ambiguities and omissions in his definitions.

title: Hilbert's axioms


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File:B17 kg200.jpg

Fair use rationale
A captured B17 in Luftwaffe colors

title: File:B17 kg200.jpg


text: Template:Greek myth (water)

title: Template:Greek myth (water)


text:
Aon Center

The Aon Center is the name of three buildings.

 * Aon Center (Chicago)
 * Aon Center (Los Angeles)
 * Aon Centre (Wellington)

title: Aon Center


text:
Paul Pena

Paul Jerrod Pena (January 26, 1950 – October 1, 2005) was an American singer, songwriter and guitarist of Cape Verdean descent.

His music from the first half of his career touched on Delta blues, jazz, morna, flamenco, folk and rock and roll. Pena is probably best known for writing the song "Jet Airliner," a major 1977 hit for the Steve Miller Band and a staple of classic rock radio; and for appearing in the 1999 documentary film Genghis Blues, wherein he displayed his abilities in the field of Tuvan throat singing.

Early years
Pena was born in Hyannis, Massachusetts. His grandparents were from the islands of Brava and Fogo in the Cape Verde islands off the western coast of Africa, and emigrated to the United States in 1919. Pena spoke Cape Verdean Creole with his family while growing up. His grandfather, Francisco Pena, and father, Joaquim "Jack" Pena, were both professional musicians, and taught Paul to play Cape Verdean music, including Morna. Pena performed professionally with his father, including a summer spent in Spain and Portugal, where he studied flamenco music.

Pena was born with congenital glaucoma. He attended the Perkins School for the Blind in Watertown, Massachusetts, from the age of 5, and graduated in 1967. He then attended Clark University in Worcester, Massachusetts.

Pena was completely blind by the time he was 20.

Musical career
In February 1969, Pena's band played for a week at The Electric Factory in Philadelphia, Pennsylvania, opening twice for both Frank Zappa and The Mothers of Invention and The Grateful Dead. Pena performed in the Contemporary Composer's Workshop at the Newport Folk Festival the same year. He also played in the T-Bone Walker Blues Band during the early 1970s, including an appearance in the Montreux Jazz Festival in 1972. He played bass guitar and provided backup vocals on Bonnie Raitt's 1971 debut album.

After moving to San Francisco in 1971, Pena called the Grateful Dead office, which helped find him work. He opened for Jerry Garcia and Merl Saunders at the Keystone in Berkeley and other area clubs many times over the course of the next three years. Pena said of Keystone owner Freddie Herrera, "His idea of an audition was for me to come and open up for Garcia and Saunders. That went on for some time. Whenever he would have somebody, not knowing who would open, he would call me."

Pena's debut album was the self-titled Paul Pena, recorded with guitarist Jeff Baxter, drummer Juma Santos, and former Perkins classmate Ellis Hall on backing vocals, and released by Capitol Records in 1972. His follow-up album New Train was recorded in 1973 by Bearsville Records and was produced by Ben Sidran (keyboardist for the Steve Miller Band). New Train featured Jerry Garcia, Merl Saunders, and The Persuasions. Albert Grossman, the owner of Bearsville Records (and best known as the manager of Bob Dylan), stopped release of the record after a dispute with Pena and his then-manager, Dr. Gunther Weil. Pena remained contractually obligated to Grossman, and was unable to record for another label.

Sidran gave an unreleased copy of New Train to Steve Miller, who recorded "Jet Airliner" with the Steve Miller Band for the 1977 album Book of Dreams. Miller's version of "Jet Airliner" was a hit single, and went to #8 on the charts. Pena's primary source of income in his later years were royalties from that single, which was a song about Pena's airplane trip from Boston to Montreal to play the first-ever date with T-Bone Walker's band.

Pena temporarily suspended his musical career to care for his wife, Babe, who was experiencing kidney failure. She died in 1991.

New Train was finally released in 2000, 27 years after it was recorded. In 2001 Pena conducted his last tour, playing a number of dates in support of the album. He opened shows for The String Cheese Incident in March of that year, and for Bob Weir's Ratdog in April. He was a presenter at the 22nd annual W. C. Handy Awards in May. He then appeared on Late Night with Conan O'Brien on June 8, 2001, and played "Jet Airliner".

"Gonna Move," a song from New Train, has been covered by a number of artists, including Les Dudek on his 1978 album Ghost Town Parade, Susan Tedeschi on her 2002 album Wait for Me, the Derek Trucks Band on their 2004 album Live at Georgia Theatre, and by Taylor Hicks on 2006's Taylor Hicks. The Derek Trucks Band also covered Pena's song "Something to Make You Happy" on their 2009 Grammy Award-winning album Already Free.

Throat singing
While searching for a Korean language lesson on shortwave radio on December 29, 1984, Pena was intrigued by an example of Tuvan throat singing he heard on a Radio Moscow broadcast. At the same time he heard an interview with the English musician Jill Purce, one of the pioneers of overtone chanting in the West, on KPFA radio in Berkeley, California, and obtained her recording. Seven years later he found a Tuvan record at a local record store called Tuva: Voices From the Center of Asia, and listened to it "continuously". Based on that record and extended experimentation, he was able to teach himself the vocal techniques called Khoomei, Sygyt and Kargyraa:

"After playing the CD continuously for several months and driving many of my friends away by making weird noises while experimenting with my voice, I finally learned a few of the basic techniques of this fascinating group of vocal styles by remembering the styles of some of the blues greats of the past – especially Charlie Patton, Tommy McClennan, and Chester 'Howlin' Wolf' Burnett."

Pena also taught himself Tuvan. There were no Tuvan-to-English translation dictionaries, so Pena used two dictionaries: Tuvan-to-Russian and Russian-to-English. He used a device called an Optacon to scan the pages and convert the printed words into tactile sensations he could read with his finger.

Pena attended a performance of Tuvan throat singing at the Asian Art Museum of San Francisco on February 6, 1993. He performed an impromptu Tuvan song in the kargyraa style, which impressed famous Tuvan throatsinger Kongar-ol Ondar. Ondar invited Pena to sing in the second international Khoomei Symposium in 1995 in Kyzyl, Tuva. Pena travelled to Tuva and was the first westerner to compete in the Symposium. He placed first in the Kargyraa contest and also won the "audience favorite" category.

Tuvans affectionately call him "Cher Shimjer" (which means "earthquake", Чер шимчээр, ), because of the deepness of his voice. Pena said, "My voice is lower than most Tuvans. They have a style that makes your voice lower. When I use that, there's a slow song when I hit a note that's four white keys from the left of the piano."

The 1999 film Genghis Blues documented Pena's journey to Tuva. It won the 1999 Sundance Film Festival Audience Award for a Documentary. It was also nominated for an Academy Award in 2000 in the Documentary Feature category.

Health issues and death
In 1997, Pena was severely injured after his bedroom caught fire. He suffered from smoke inhalation and was in a coma for four days.

Pena had diabetes. He also waged a long battle with pancreatic illness, and was originally mis-diagnosed with pancreatic cancer. He began chemotherapy treatments and doctors gave him six months to live. In 2000 he was properly diagnosed with pancreatitis, a life-threatening illness.

Pena died in his San Francisco, California, apartment of complications from diabetes and pancreatitis on October 1, 2005.

Studio albums

 * Paul Pena, released in 1972 by Capitol Records (re-released online in digital formats in 2011)
 * New Train, recorded in 1973, released in 2000 by Hybrid Recordings
 * Deep in the Heart of Tuva: Cowboy Music From the Wild East, (various artists) released in 1996 by Ellipsis Arts
 * Genghis Blues, first released in 1996 by TuvaMuch Records, re-released with additional tracks in 2000 by Six Degrees Records

Live recordings

 * Fly Walker Airlines, the T-Bone Walker Blues Band, 1972 by Polydor Records. T-Bone Walker, guitar and vocals; Paul Pena, lead guitar and vocals; Hartley Severns, saxophones and violin; Johnny Summers, bass guitar; Vinnie Johnson, drums. Recorded live at the Montreux Jazz Festival June 17–20, 1972
 * Stormy Monday, released in 1996, the T-Bone Walker Blues Band, by Delta Music. This is a bootleg version of the album Fly Walker Airlines taken from the radio broadcast of the concert of June 17, 1972, in Montreux, Switzerland. The CD incorrectly lists a recording date of 1968.
 * Giant Killers, Big Bones and Paul Pena. Recorded live at the Freight and Salvage Coffee House in Berkeley, California in February 1991.
 * Delta by the San Francisco Bay, Paul Pena, Alvin Youngblood Hart And Big Bones, 2012 by GangsterBlues.com. Recorded live in August 1991. Available in mp3 format only.

Filmography

 * Genghis Blues, released in 1999 by Wadi Rum Productions

title: Paul Pena


text:
Three Logan Square

Three Logan Square, formerly known as the Bell Atlantic Tower, is a 55-story skyscraper located in Philadelphia, Pennsylvania. Standing 739 ft (225 m) tall to its structural top, the building encloses 1300000 sqft of office space. The building, designed by the Philadelphia-based architecture firm Kling Lindquist, was completed in 1991.

A city ordinance dictates that no building within 250 ft of the nearby Benjamin Franklin Parkway may rise taller than 250 ft; the tower stands just outside this zone. A landscaped plaza, constructed of the same red granite as the building, occupies the rest of the plot, fulfilling a city requirement that 1% of the total budget for new building construction must go toward a work of public art.

A banquet hall, known as Top of the Tower, occupies the top floor of the building and is available for public rentals.

It was the headquarters for Philadelphia-based Baby Bell Bell Atlantic until 1996, when Bell Atlantic acquired New York City-based NYNEX and moved its headquarters to New York. In 2000, Bell Atlantic and GTE merged to become Verizon and the "Bell Atlantic" name became obsolete. However, the building's managers kept the original name, mainly because of the difficulties in getting all necessary parties to agree to change it.

The building had been offered for sale in the past, and on August 5, 2010, it was sold to Brandywine Realty Trust. The company has since renamed the tower Three Logan Square, to better identify its location near two other Brandywine-owned buildings, One and Two Logan Square.

Tenants

 * CDI Corporation
 * Comcast Cable
 * Reed Smith
 * Excelacom Inc
 * Janney Montgomery Scott, LLC
 * Warner Bros. Digital Labs
 * Kleinbard
 * Verizon
 * Marsh & McLennan Companies
 * L2P
 * Fowler Hirtzel McNulty & Spaulding LLC

title: Three Logan Square


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