text:
Talk:Instructions per second

Reference for the Timeline Table
I found a possible reference for the still unreferenced entries in the timeline table. It is from a book from Kai Qian,David den Haring,Li Cao named Embedded Software Development with C. It can be found under google books: http://books.google.com/books?id=aB1EgF0jB-MC&pg=PA8&lpg=PA8&dq=AMD+Athlon+%223,561+MIPS%22+-wiki&source=bl&ots=pG_B87T73t&sig=P4YYT12GS7tH9quVl9jiGUo5084&hl=de&ei=MQQbTYLmIYvwsgb91OH5DA&sa=X&oi=book_result&ct=result&resnum=1&ved=0CBUQ6AEwAA#v=onepage&q=AMD%20Athlon%20%223%2C561%20MIPS%22%20-wiki&f=false —Preceding unsigned comment added by 80.238.172.215 (talk) 09:58, 29 December 2010 (UTC)

Errata in Timeline
Hello. I'm sorry that I don't know how to edit Wikipaedia correctly, but the most of the M- prefixes for the recent processors are incorrect. They should all be GIPS, not MIPS. This can easily be confirmed by visiting the link cited in this table. I would appreciate it if somebody more savvy than I am could correct this. Thank you. — Preceding unsigned comment added by 96.255.78.233 (talk) 01:47, 25 November 2011 (UTC)

I'm glad you didn't edit it, because as a meaningful apples-to-apples comparison, all figures from the earliest computers to those at present are calculated on this same scale. NEVERTHELESS, it seems a little odd to me that the Intel Celeron and the i3 are both missing from this list. grubbmeister (talk) 21:57, 23 June 2018 (UTC)

Critics on MIPS
The article has a lengthy description of the acronyms critics of MIPs use, but does not state why they are critical of the metric. I suggest explaining why they are, for those people who read the article and have not taken computer architecture.

—Preceding unsigned comment added by 65.6.47.129 (talk) 19:25, 2 September 2007 (UTC)

 * Those critics are personal opinions that are not appropriate for Wikipedia. I think the critics are mainly caused by ignorance of what MIPS means. Quite many people seem to mix MIPS with MNOPS (Million NOP instructions per second). That is, they assume that you can take the fastest possible execution time of the fastest instruction (such as NOP), calculate how many such instructions could be executed in second, and then call that MIPS. That would, of course, not be an useful method for comparing processor speeds. But that is not MIPS. MIPS is the average execution time of insturctions in real world applications.
 * -- PauliKL (talk) 13:34, 14 March 2008 (UTC)
 * Unfortunately this is not true. MIPS is highly dependent on the application that is used to calculate it. If a clever compiler reduces the use of time-eating instructions, this can possibly result in a lower MIPS value, although the processor is as fast as before. A simple example would be this: consider our processor contains only two instructions, add and multiply. In a sample program, compiled with a dumb compiler, all multiplications are displaced by multiple additions. Another compiler might use the builtin multiplication. Therefore, as one addition is faster than one multiplication, the first application results in a lower CPI (cycles per instructions) value, and the second one in a higher CPI. As a result (MIPS depends on CPI), the second application results in a lower MIPS value, although we are using the same processor. ( http://devel-rok.informatik.hu-berlin.de/svn/TI2/2006/folien/pdf/eng_ca03.pdf ) Is there more to add?

--141.20.192.251 (talk) 16:59, 15 July 2008 (UTC)

The acronym MIPS is inherently wrong due to the fact the unit of measure of time "second" has to be specified accordingly to the international standards spec. as a lowercase "s".

Following the correct example in the first sentence by the user "65.6.47.129" above, MIPs is the formally correct horthografy.
 * -- AT 213.156.52.121 (talk) 19:20, 27 April 2008 (UTC)

 * No. The correct acronym is MIPS, since that is the acronym that has been commonly aggreed. If international standard specs (SI) was to be used, the acronym would be MI/s. But that is not the point. The main thing is what MIPS actually means and what does it measure. --PauliKL (talk) 18:54, 15 May 2008 (UTC)

Changes
Removed Pentium 4 data for error. Pentium 4s typically have MIPS between 3,000 and 20,000, depending on year of release.

Also removed data based on erroneous formula.

Added Year 2004 data for budget 32 bit and 64 bit PCs.

Several instructions per clock cycle

 * Is that right about 20,000 MIPS for the Pentium and 10,000 for the Celeron? Can they really do several instructions per clock tick? Bubba73 19:15, 12 Jun 2005 (UTC)

 * Theoretically yes. Starting from the 486 which is a 386CPU and 387FPU on the same die, most processors can theoretically do more than 1 instruction per cycle. Note that cycle does not equal clock.

 * That is not true. 486 can definitely not execute more than 1 instruction per clock cycle. And many instructions take more than 1 clock cycle, so the average is significantly less than 1 instruction/cycle. Adding FPU on same die does not change that. It is insignificant whether the FPU is on the same die or on different die. It does not change the way the processor works, and it does not have effect on the MIPS value. Since the days of the first FPU's, everybody has known the fact that adding FPU does not change MIPS value. MIPS is about integer performance of the CPU itself. It does not take account floating point calculations. And adding external units such as graphics processors does not have effect on MIPS value either. - PauliKL (talk) 21:27, 24 February 2008 (UTC)
 * P.S. Added the missing headings on talk page - PauliKL (talk) 22:22, 24 February 2008 (UTC)
 * I'm pretty sure that multiple instructions per clock didn't come in until at least the Pentium MMX ... that was kind of it's selling point wasn't it? Or at least the P5 had some superscalar stuff just so it could claim "first!", at the expense of some instructions actually being SLOWER per-clock, and then the MMX actually did it properly with SIMD and other improvements.
 * The 486 was more notable for having several one-clock instructions, and an actually-usable L1 cache that meant said 1CLKs were also effectively zero-wait-state if they were also cache hits (or 1WS for L2, which most 486 boards also had, and in greater quantities than the token 8kb-or-so of 386 boards). It is NOT a 386 + 387... it builds upon them in a similar but milder way to how the 386 built on the 286, but it's as much an integrated 386+FPU as the 386 was "a 286 with 32-bit registers and bus". It has a number of added instructions, revisions to the pipeline etc that allow the 1CLK routines (and many other instructions to execute quicker, arguably a more important advance), the cache, improved fpu, clock doubling/tripling in later versions, etc, all of which allowed a 486 to operate much quicker than a 386 at the same clock speed (I think a common comparison was that a 25mhz 486 SX, ie one with an inactive fpu, was equivalent to a 40mhz 386 DX?). You may be thinking of some of the "low power" LC/SL/SLC chips which were basically 386 cores with some fakery to allow common "486-only" code to run on them (at low speed)? BTW, not all 486s had an operable FPU anyway (same as there were enough 386s sold with a 16 bit bus), so that comparison immediately goes out of the window.193.63.174.211 (talk) 12:46, 15 February 2012 (UTC)

 * Ever since the first Pentium processor they have been superscalar, which means they can perform more than one instruction per clock. Now for some modern MIPS calculations: the K7 and K8 (Athlon and Althon 64 from AMD) have 3 integer units each and can issue 3 insructions per clock, and can complete most non-memory integer operations in a single clock. The fastest single-core Athlon 64 is 2.8GHz, which gives a theoretical limit of 2.8e9 * 3 / 1e6 = 8400 MIPS. The Intel Pentium 4 has 2 simple integer units and one complex unit. It can perform a select subset of simple integer operations (add,subtract, and shifts on the Prescott) at a rate of 4 instructions per clock, or a single less simple operation. The fastest single-core Pentium 4 is 3.8GHz, which gives a peak of 15200 MIPS if you are doing the 4 instructions per clock, or down to 3800 MIPS for less-simple instructions. None of this includes things you can do with the SIMD instructions. Given the ambiguity in the Pentium calculations I'll just start by adding the Athlon 64 to give an idea of current speed of modern processors.

 * According to SySoft SANDRA Dhrystone ALU benchmark, an Athlon FX-57 clocked at 2.8GHz yield 12000 MIPS, an Athlon 64 X2 3800+ with two cores at 2GHz yield 17200 MIPS, using the same benchmark, I reached 25150 MIPS by overclocking my Athlon 64 X2 3800+ to 2.8GHz. I took the liberty to edit the Athlon 64 MIPS accordingly, if you don't beleive me, 'bench 'em yourself.

 * MIPS is now largely replaced by MTOPS which manufacturers are required to disclose by law. (United States Department of Commerce Export Administration Regulations 15 CFR 774 (Advisory Note 4 for Category 4). )

[]
 * Links to MTOP calculations : []

 * Note that the above post is several years old and CTP is no longer required by the US government for export purposes. The Adjusted Peak Performance replaced CTP back in April 2006 but was itself replaced less than two years later. As seen in this Intel press release in November 5, 2007 the US government published amendments to the Export Administration Regulations 15 CFR which requires exporters to use the metric of Gigaflops (GFLOPS) to measure processor performance. --GrandDrake (talk) 05:57, 19 June 2010 (UTC)

Timeline

 * Aren't timelines usually in chronological order? Shogun 01:07, 21 March 2006 (UTC)
 * yep, they are. I corrected the table. jidan 15:56, 15 May 2006 (UTC)

New proposed timeline
Hi, instead modifying the table inside the article, I write here the new proposed timeline based on http://www.frc.ri.cmu.edu/users/hpm/book97/ch3/processor.list.txt. However the last entries with the processor name only (from Intel pentium pro) should be removed/changed, because I think that is more realistic to calculate the IPS for the enteire system (CPU/bus/memory) and not only the processor. I also found very useful the cost of the system compared to the value of USD in the 1997, to understand the customer target. The sources are various (specint, speedmark, winsscore..) compared to the MIPS. May be not perfect, but I think it is a good point to start. Please to leave some comment. --Trek00 02:54, 5 February 2007 (UTC)

 * "Pencil and paper" is 1892 ? ... erm. OK. How about "indeterminate point several thousand years in the past"? You've got to fit abacuses, pascal's bones, slide rules and comptometers in-between that and ENIAC after all, without even getting into the differences between various paper-based methods and user experience and ability...
 * Also this shows a quite different result for the speed of the M68k - in the main article it's 1.0 MIPS, here it's 0.52, both at 8Mhz ... which is correct? Also, the main article claims the i8080 - aka the 8-bit variant of the i8086 that the Z80 was cloned from - manages 0.5MIPS at 2Mhz, or twice the per-clock efficiency (or 4x, if we believe the figures here). I'm pretty certain that's a hundred million miles from the truth... (I'm not convinced by the 80286 having such a per-clock gain vs the 68000, either; it simply doesn't seem to keep up all that well IRL. Though perhaps the raw figures are correct and one of them is just a whole lot harder to program effectively?) 193.63.174.211 (talk) 12:57, 15 February 2012 (UTC)

Cell Data is blatantly incorrect
Guys -- The data you posted about the Cell processor is just plain incorrect. Please update the page. For the record:

Cell runs at 3.2 GHz. Cell has one dual-threaded fully 64-bit Power Architecture core. This core, not including its AltiVec vector processor, does 6400 MIPS... although these are 64-bit instructions so the comparison to 32-bit processors is really not too valid. (Should we claim that it's 12800 "32-bit MIP equivalents"?) In ADDITION to the above, the Cell has 8 single-threaded 128-bit processor cores. That adds 25600 MIPS or 102400 32-bit MIP equivalents... for a total of 38400 (115200).

FLOPS have nothing to do with the above. In FLOPS, the Cell does over 200 single-precision GFLOPS and in the high teens in double precision. As of today (30 Mar 2007), information on the next-generation processor has been released... although I am not at liberty to disclose its performance until someone cites it.

The figure you cited was not a peak value (as cited for other processors). Instead, you took the performance on a given benchmark (Linpack) in FLOPS... which are not comparable to MIPS.

The Cell Team at IBM

 * No, you can not multiply the MIPS value by 2 using the excuse that processor has some 64 bit instructions. One 64 bit instruction is still just one instruction. And, let's face it, 64 bit instructions are rarely used in real world applications. After all, 64 bit data is quite rare. Most common data is 8 bit (character data, 8 bit/channel RGB data etc.). In addition, most applications use only 32 bit instruction set in order to be compatible with older processors, so 64 bit processor is no faster than 32 bit one. But even if the program is compiled to use 64 bit insturctions, it will only be around 2% to 5% faster than the 32 bit version.

 * Indeed, FLOPS measurement should not be mixed with MIPS. MIPS is only about integer performance. No matter how powerful FPU is included with the CPU, it does not have effect on the MIPS value of the CPU.

 * There is no such thing as "peak value" in MIPS measurement. MIPS is the average number of instructions executed by the processor when running a real world application. (Well, the term "peak MIPS" is sometimes used to say that it is the speed of the CPU when the application fully fits in L1 cache so that the memory access is not slowing down the operation. Which is the case with Dhrystone benchmark, for example.)
 * -- PauliKL (talk) 22:09, 24 February 2008 (UTC)

 * Yes, but MIPS started in the days when processors did about the same amount per instruction. Before hardware multiply, when you had an MQ register and did shift and add, or shift and subtract, and each instruction operated on one processor word. As hardware changed, and the amount of processing that an instruction, or even a clock cycle, could do change, MIPS became less and less useful. That is why some call it Meaningless Indicator of Processor Speed. Gah4 (talk) 22:08, 23 April 2015 (UTC)

Given MIPS ratings not correct
The MIPS ratings given in the table seem to be incorrect. For example, 8080 at 2 MHz has been given value 640 kIPS (0.64 MIPS), which is impossible. The fastest instructions on 8080 take 4 clock cycles. Thus, 2 MHz 8080 can execute maximum of 0.5 million instructions per second.

However, max number of instructions per second is not MIPS. MIPS is calculated from weighted average of instruction execution times.

I recall Intel has given 8080 rating of 0.08 MIPS, which sounds more correct, considering the fact that a 8 bit processor needs multiple instructions to perform a single 32 bit operation.

Another example: Zilog eZ80 has been given rating of 80 MIPS at 50 MHz. As far as I know, eZ80 is not a superscalar processor, so it can not execute more than 1 instruction / clock cycle. Since it is a 8 bit processor, the MIPS rating must be significantly less than 50 MIPS.

PauliKL (talk) 18:08, 23 January 2008 (UTC)

 * And youl English wliting not colect, eithel. Soly about that. --AVM (talk) 22:17, 14 February 2009 (UTC)

 * PauliKL does not seem to understand what MIPS means. That may be partly because it is not a well defined term in general, but here I thought it was defined in terms of the speed of executing native instructions.  That means no compensation is made for what the instructions are doing.

 * I remember (although it has been a long time) that the 8080 can execute instructions as fast a 3 clock cycles. The basic instruction operation has three steps labeled T1, T2 and T3 which derive from the original 8008 which used three clock cycles to access memory over a single 8 bit port; output upper address, output lower address, input or output data.  The 8080 retained the three clocks per machine cycle concept even though it could output the entire address and data in parallel.

 * http://www.allaboutcircuits.com/vol_4/chpt_16/5.html

 * Gnuarm (talk) 16:57, 3 February 2010 (UTC)

 * The whole table seems to be fed with wrong data. For example, the cited 23.8 IPS for a Core i7 Extreme 965 cannot be correct. Any Nehalem-based CPU is a 4-way superscalar CPU, i.e. it can execute at most four instructions per clock cycle (peak throughput). Having four cores (i7 Extreme 965) yields a theoretical maximum of 4*4 = 16 instructions per clock cycle. Thus, the 23.8 IPS number is clearly too high. --85.216.120.3 (talk) —Preceding undated comment added 16:49, 1 December 2010 (UTC).

 * edit: I think the whole confusion is caused by the numbers from Sisoft Sandra (or the inability to think and interpret those numbers by whoever used it as a source for its high IPS claim): Sisoft Sandra probably uses SIMD instructions to maximize throughput (SSE2/3 etc.) but counts every sub-instruction in a large SIMD-word as one executed instruction. For instance, if computing several 32 bit numbers, it uses the 128 bit SSE1/2/3 format to do four 32bit calculations in parallel. Although the throughput is equivalent to four single 32 bit operations, this is actually _one_ instruction executed, not four! If for example the processor is executing two of those SIMD instructions in parallel, those yield only an IPS of two. The instruction pipeline of the processor is incapable of processing eight (i.e. two times four) instructions per clock cycle. The hardware is simple not capable of doing that! So, in this example (Core i7 Extreme 965), it is simply wrong claiming a higher value of four IPS per core (or sixteen IPS in total). --85.216.120.3 (talk) 17:04, 1 December 2010 (UTC)

 * Sisoft Sandra does not count instructions. (In fact, I don't think it is even possible to count instructions without using dedicated debug hardware.) It uses Dhrystone test and then displays the results as MIPS. So, the unit used is actually Dhrystone-MIPS. However, the test used is not exactly the original Dhrystone test, but a multi-threaded, 32/64-bit variant, so the results are not 100% comparable with the original. (See the FAQ).
 * Maybe there should be separate columns for "IPS" (which usually means execution speed of NOP instructions) and Dhrystone-MIPS. --PauliKL (talk) 11:29, 5 December 2010 (UTC)

Seems the Freescale page for the 68060 gives different values. But maybe it's due to newer fabrication process ? Mmu man (talk) 19:20, 18 December 2010 (UTC)

MIPS = MHz?
If a microprocessor can execute a singular instruction million times per second (MHz), then why can't it execute a million unique instructions within the same timeframe (MIPS)? What is the game-changing constraint here? This article does not explain this rather bizarre behaviour.Anwar (talk) 10:44, 15 May 2008 (UTC)

 * Huh? What do you mean? MHz is unit of frequency, not unit of instructions per second. In context of processors, MHz is usually used to measure the clock frequency. Traditional CISC processor may require multiple clock cycles to execute one instruction, so they deliver less than 1 MIPS/MHz. RISC processors typically execute every instruction in one clock cycle. In that case, they would execute about as many instructions per second as the MHz value would indicate. Number of instructions executed per second is not same as MIPS, but with 32-bit processors, it is quite close. However, there are processors that can execute multiple instructions in parallel (superscalar). Further, there are processors with multiple cores. These deliver more than 1 MIPS/MHz. --PauliKL (talk) 19:10, 15 May 2008 (UTC)

IBM 704 & IBM 7030
Could someone add the Mips of the IBM 704 (1954) and the IBM 7030 (1961) to this table? I'm too dumb to do so. tnx in advance. See also new proposed timeline above. Aleichem (talk) 20:37, 8 June 2008 (UTC)

IBM Mainframe cpus removed?
Why were the IBM Mainframe cpus removed? The newest z196 Mainframe have 24 cpus and gives 50.000 MIPS. This means each 196 give 2.000 MIPS each. Please add it.

The z10 Mainframe with 64 cpus, gives 28.000 MIPS, this means each z10 cpu gives 450 MIPS. Please add that. — Preceding unsigned comment added by 217.73.15.6 (talk) 11:06, 23 January 2012 (UTC)

IPS/Hz
There's something wrong with the IPS/Hz metric. In SI base units a hertz is "1/second". Thus,
 * $$\frac{IPS}{Hz} = \frac{instructions / second}{1 / second} = \frac{instructions}{second} \times \frac{second}{1} = instructions$$

Just plain instructions. It does not make sense to me. Also, since IPS and CPU clock frequency are both unreliable performance metrics(, page 13), their ratio is pretty much worthless anyway. —ZeroOne ( talk / @ ) 11:40, 3 April 2010 (UTC)

 * It seems to be the number of instructions per clock cycle.--Patrick (talk) 15:29, 3 April 2010 (UTC)

 * That's kind of what I figured too. It just does not make sense to me that a desktop computer could execute thousands of instructions per clock cycle, as has been marked to be the case for several systems in the article. A clock cycle is what makes the CPU 'tick', nothing can happen faster than in one clock cycle. A quad-core processor could, of course, execute four instructions per second, etc. It seems to me that in this article MIPS refers to something else than the obvious. Weicker lists five possible interpretations of the concept of MIPS that manufacturers give for their products. One of the interpretations, a common one according to the author, is "VAX MIPS". This is a factor relative to the VAX-11/780. This could be the one that is being used here. Anyway, I'm in favor of dumping the entire table because collecting statistics of a meaningless indicator of processor speed is, well, meaningless. At least the newer than 1970s computers could be dropped, because that's about when the original concept of MIPS started to fall apart anyway. —ZeroOne ( talk / @ ) 23:39, 3 April 2010 (UTC)

 * The largest value in the table is 45, not thousands.--Patrick (talk) 06:11, 4 April 2010 (UTC)

 * Oops, my bad. The numbers were presented in different precision and I got confused. I have now rounded them all to just one decimal place. Anyway, I think the article needs to explain why is it possible to have, say, 45 instructions per clock cycle. I suppose it's got to do with superscalarity, branch prediction, etc, but in any case the 45 must be a peak number that is impossible for the system to sustain. Right? —ZeroOne ( talk / @ ) 10:43, 5 April 2010 (UTC)

 * Rounding all values to 1 decimal was not a good idea. It would be OK to round 1234.56 to 1234.6, but when you round 0.25 to 0.3, you are creating a big error. For example, Intel 8080 now has value of 0.3 instructions/clock cycle, which means that average instruction execution time would be 3.33 cycles. However, on 8080 even the fastest instruction takes 4 clock cycles, and some instructions up to 18 cycles. --PauliKL (talk) 15:12, 8 April 2010 (UTC)

 * It is usual to round based on the uncertainty in the value. In the case of MIPS, there is a lot of uncertainty, even though each person making a measurement will claim that theirs is correct. One digit is probably about right. If you don't like 0.3, then round to 0.2 instead. (According to "round to even" that would be more correct.) Gah4 (talk) 22:37, 23 April 2015 (UTC)

 * MIPS is actually a good measure for CPU performance, definitely not "worthless". The expression "meaningless indicator of processor speed" is used by ignorant people who do not know what MIPS means. Of course you should realize that MIPS only measures CPU performance. There are many other factors that affect the computer performance, such as the speed of memory bus, display controller and hard disk.
 * On the other hand, MIPS by itself does not measure the performance, it is just an unit used to display the performance value whichever method is used to measure it. There are good and not so good methods to do the measurement, just like there are many methods to measure temperature. Originally, the measurement was done by calculating a weighted average of specific instruction set (e.g. VAX instruction set for VAX MIPS). That was a good method, but laborious, so later many of the MIPS values were measured by running some benchmark and then comparing the results to known computers (e.g. Dhrystone MIPS).
 * But, as I have said before, the values in the table are wrong. For example, the correct value (according to Intel) for 8080 is 0.04 MIPS, not 0.5 MIPS. For newer processors, the values seem to be just pulled out of a hat. --PauliKL (talk) 16:03, 8 April 2010 (UTC)

 * One of the problems with MIPS as the unit of CPU performance is that different CPU architectures get different amounts of work done per instruction. Thus a 10 MIPS CPU can well be faster than a 20 MIPS CPU. —ZeroOne ( talk / @ ) 12:24, 10 April 2010 (UTC)

 * No. The problem with MIPS is that ignorant people do not understand what MIPS means, and therefore they have all kind of false beliefs. In reality, 10 MIPS CPU can never be faster than 20 MIPS CPU (in integer calculations), since, by definition, 20 MIPS is twice as much power as 10 MIPS.
 * Back in the 70'ies and 80'ies, when actual calculated MIPS values were still used, the standard unit was VAX MIPS. It is based on VAX 11/780 instruction set (not the target machine's instruction set). The amount of work done depends on what VAX can do with the instructions, now what the target machine instructions do. If the target machine requires multiple instructions to perform one VAX instruction, the calculated instruction execution time is the sum of those instructions. That is why 8-bit processors have such a low MIPS ratings. For example, 8085 processor running at 4 MHz can execute up to 1 million instructions per second, but it's processing power (according to Intel) is only 0.08 MIPS.
 * Later, MIPS values where usually derived from benchmarks. If CPU A (rated at 10 MIPS) executes a benchmark in 20 seconds, and CPU B executes the same benchmark in 10 seconds, CPU B will have rating of 20 MIPS. How could CPU A still be more powerful than CPU B? --PauliKL (talk) 19:49, 11 April 2010 (UTC)

 * By definition MIPS = n / (t * 10^6) where n is the number of instructions executed and t is the time it took to execute those instructions, in seconds. It does not follow that a 20 MIPS CPU is always faster than a 10 MIPS CPU. An instruction of a CISC CPU could equal, say, 4 instructions of a RISC CPU. If the CISC CPU then performs at 10 MIPS, it would be equal to a 40 MIPS RISC CPU. Clearly the 10 MIPS CISC CPU would then be faster than a 20 MIPS RISC CPU. —ZeroOne ( talk / @ ) 22:02, 11 April 2010 (UTC)

 * No. That is not the definition of MIPS. And what do you mean by "instructions executed"? What instructions? Executed when? As I already explained, the actual MIPS rating is the weighted average of the execution times of all instructions in some specific instruction set (e.g. VAX instruction set). The weighting factor depends on how common the instruction is in real world applications. If a RISC processor requires multiple instructions to perform one VAX instruction, the sum of the execution times of those instructions is counted as one instruction in MIPS calculations. Dhrystone MIPS, on the other hand, is the result of Drystone test normalized into MIPS scale. It does not count the instructions at all.
 * One CISC processor instruction definitely does not equal 4 RISC instructions. The studies show that a RISC processor typically needs 10% more instructions to execute a task than CISC processor. So, if executing an application requires 10 million instructions in CISC, it would require approximately 11 million instructions in RISC. If CISC processor needs 1 second to execute the task and RISC processor needs 0.5 seconds, then clearly RISC processor is more powerful. --PauliKL (talk) 16:46, 12 April 2010 (UTC)

 * By "instructions" I mean the individual instructions the processor executes: loads, stores, register manipulations, etc. They are executed when the application is being executed, obviously, because applications are made out of those instructions. The definition of MIPS I gave you is from Measuring Computer Performance : A Practitioner's Guide by David Lilja, ISBN 9780521641050. What makes you think Lilja, a published author, is "ignorant"? Can you give me an equally credible source for your interpretation of the MIPS figure?
 * I did not ask what you mean by "instructions". The question is, which instructions? Which application? What is that legendary "The Application" that is used to define which instructions are counted? The reason why ignorant people think MIPS is bad is because they assume they can just use any application they like, even one that contains nothing but NOP instructions. In reality, the weight factors used in VAX MIPS calculations were based on statistics from huge amount of real world applications run in VAX. The reliable source for this information are the many computer magazines (Byte, Dr. Dobb's Journal etc.) that were published in those times when MIPS calculations were actually used for benchmarking. The problem is that I don't have those magazines any more, that is why I have not fixed the article. --PauliKL (talk) 16:18, 13 April 2010 (UTC)
 * Well, pardon me if I wrongly interpreted "what do you mean by "instructions executed"? What instructions?" as a question on what I mean by instructions. It seems to me that you are confusing the metric with some benchmark. "MIPS" does not care what instructions are being executed. It's just a metric. It's like I was telling you that a kilometer equals 1000 meters and you insisted that no, you must define whether you are going to travel the kilometer on foot or by car. —ZeroOne ( talk / @ ) 21:51, 13 April 2010 (UTC)
 * No, you are the one that is confusing things. Yes, MIPS is a metric, as I already told you. It is a metric of CPU speed. Not a metric of how many unspecified instructions are executed in whatever unspecified program. After all, such a "metric" would be pretty much useless (even if you find a way to count the instructions). Even the concept of "instruction" is vague. For example Pentium and Core 2 processors, even if called CISC processors, are actually RISC processors internally. The legacy CISC instructions are translated into RISC instructions before executing. Which instructions should you count, the CISC instructions in the code or the RISC instructions actually executed? And what about speculative execution?
 * In reality, MIPS definitely does care what instructions are being executed. This is because (in CISC processors) instruction execution times vary very much, for example from 1 to 50 clock cycles. That is exactly why MIPS calculation is done as weighted average. --PauliKL (talk) 16:10, 16 April 2010 (UTC)

 * Also my point holds even if RISC processors typically need 10 % more instructions than CISC processors. If an application requires 10 million instructions in CISC and 11 million in RISC and both execute the application in 1 second, then the CISC computer would have a MIPS value of 10 and the RISC computer a MIPS value of 11, even though they actually perform equally well.
 * —ZeroOne ( talk / @ ) 10:19, 13 April 2010 (UTC)
 * No. If the application is a benchmark, and both processors get the same result (e.g. the same time), they both have the same result even when it is converted into MIPS value. For example, if it was Drystone test and both processors get the result 17570 dhrystones/sec, then both processors have Dhrystone MIPS rating of 10.0. The number of instructions they executed during the test has no effect on the results (and probably it is not even known). --PauliKL (talk) 16:18, 13 April 2010 (UTC)

 * Well, I, for one, was talking about the concept of MIPS, not about the concept of various benchmarks. Why are you switching between Dhrystone MIPS and VAX MIPS anyway? Also if a MIPS figure does not represent millions of instructions per second, like you said it doesn't in the case of Dhrystone, then it's pretty obvious to me that the acronym is being used in some other meaning than its original one. —ZeroOne ( talk / @ ) 21:51, 13 April 2010 (UTC)

 * As I have explained, there are two possible ways to get MIPS rating:
 * 1. Manually calculating a weighted average of instruction execution times for some specific reference instruction set (e.g. VAX instruction set, or older Gibson Mix or ADP Mix), or
 * 2. Running a benchmark and then scaling the results into MIPS value (e.g. Dhrystone MIPS). In this case, MIPS is only used as a metric. Most of the values in the "Timeline of instructions per second" table (if not pulled out of hat) obviously come from benchmarks.
 * I have shown that whichever method is used, your arguments are wrong. MIPS is measure of CPU performance, it is not an instruction counter. MIPS does not care about how many instructions are executed in the target processor. RISC and CISC processors that have equal performance will get (approximately) equal MIPS rating regardles of how many instructions they happen to execute for some task. --PauliKL (talk) 16:10, 16 April 2010 (UTC)
 * I can't help but think that you are just dodging my questions or rephrasing what I (or you yourself) have been saying. How do you explain, for example, the definition of MIPS that Lilja gives in his book? Are you saying he is wrong? I gave you a claim with a source and you keep insisting on your own views, completely ignoring my points. —ZeroOne ( talk / @ ) 10:16, 17 April 2010 (UTC)

"The nice thing about standards is that you have so many to choose from." Gah4 (talk) 22:37, 23 April 2015 (UTC)

Corrections to DIPS/cycle/core
I've made some corrections to the DIPS/cycle/core calculations for Intel Core i7 processors, they were half what they should have been because the math was done with the number of logical cores, not physical cores. Please remember to only count the number of PHYSICAL cores in CPUs with HyperThreading. Alereon (talk) 07:45, 11 October 2011 (UTC)

Atom N270
N270 is single core right? The Atom entry lists 2.4 and 1.2 as if it is dual core. I think both values should be 2.4 but would like a second opinion before editing. thanks. — Preceding unsigned comment added by 194.46.201.216 (talk) 11:50, 12 October 2012 (UTC)

8080 Timing
Intel 8080 MIPS numbers are incorrect and not plausible. The Intel 8080 and 8085 instructions ran in from 4 to 17 clock cycles each. There were a few 4 cycle, quite a few each of 5, 7, 10, 11, 13, 16, and 17. I wrote alot of 8080 code and optimized at the clock-cycle level. I used a rule of thumb of 10 cycles per instruction and found it a very good generalization. This would be 0.2MIPS, or 0.1 IPS/Cycle-per-second. Certainly anything claiming to be authoritative has to be in this ball park. The table lists 0.33 MIPS, or 6 instructions per clock cycle on average. This program would be primarily a long string of carefully selected arithmetic instructions with no memory accesses, branding, or stack operations - very unrealistic. What an average MIPS rate is in the absence of a standard benchmark is debatable, but in no case could one claim an 8080 to be above 0.5 MIPs. The paragraph just above the table states that a 2MHz 8080 executes 0.64 MIPS. With the shortest instruction being 4 clock cycles, this is not possible. Can the originator of the current numbers give any reference or anecdote on which they are based?

Until someone comes up with an authoritative reference of some sort I would use my numbers of 0.2 MIPS at 2MHz, 0.1 IPS/Cycles per second. At the very least, the 0.64 should be made consistent with the 0.33, and I would argue that the 0.33 is unrealistic. If nobody is happy with my number, put a range of 0.2-0.33 depending on instruction mix. I do not know how to edit and don't want to mess it up.

The new proposed table lists the Altair 8800. This seems redundant since the 8080 is already listed, but more important it lists it as 10 KIPS. Per my numbers above, this is 10x too slow. Even given the possibility of slow memory and wait states, there is no way it could possibly be this slow. This I believe should be 100KIPS, but not knowing how many wait states it ran to memory over the S100 bus, I cannot give an accurate number.

The proposed table also lists the 8085 and gives number that are inconsistent with the listed 8080 numbers. Except for the level of integration, both processors are identical, and execute all instructions in exactly the same number of clock cycles under all conditions. The mainline 8085 ran at 3MHz vs. the 8080's 2MHz, do the MIPS should be 1.5X listing 3MHz instead of 2, and the IPS/ClockCyclePerSecond should be the same. If you cranked up the power supply voltage they would run at 10MHz or so :-)  ...   But not for long :-( ...

— Preceding unsigned comment added by Rnsc5j (talk • contribs) 23:00, 25 January 2013 (UTC)

Summary table needs to be fixed
Last few rows of the summary table were incorrectly added (wrong number of columns etc.), so they should to be fixed. It would be great if someone could handle that. Thank you. -- Dsimic (talk) 15:55, 7 October 2013 (UTC)

There are several new rows showing inconsistent values. (e.g. 486 and 486 same cpu but different values)--62.48.72.6 (talk) 08:08, 21 October 2015 (UTC)

Move discussion in progress
There is a move discussion in progress on Talk:Kilometres per hour which affects this page. Please participate on that page and not in this talk page section. Thank you. —RMCD bot 01:00, 10 December 2013 (UTC)

 * I don't see that MIPS got much discussion there, but it doesn't seem appropriate, anyway. MIPS is not the plural of MIP, though I have seen MIP used as the singular. (VAX is a 1 MIP machine.) Reminds me of my old favorite, LASE and LASING are the verb forms of the acronym LASER. Gah4 (talk) 22:38, 11 November 2015 (UTC)

Meaningless Indicator of Processor Speed
In the 1950's and 1960's, computers weren't all that different. Scientific processors commonly had a 36 bit word, and instructions operated on that word size. You could probably make a fair comparison between a DEC PDP-10 and an IBM 7090 based on instruction execution rate. Even so, it is a rough indicator, but sometimes that isn't so bad. But as processors diverged, it became less useful. Comparing a 6502 with its 8 bit accumulator and an IBM 370/158 with 32 bit registers, based just on instruction execution rate is meaningless. When comparing members of a family, such as different models of VAX, or different models of IBM S/370, MIPS also tends to work. VAX MIPS, based on a certain VAX processor being 1 MIPS (even when it probably wasn't) and a reasonable set of benchmark programs also might be useful, though it removes the whole meaning behind the acronym. Might as well just compare in relative speed to a specific VAX processor, and not call them VAX MIPS. Gah4 (talk) 12:03, 28 October 2014 (UTC)

 * There doesn't seem to be much interest in figuring out what to do with this. In the 1970's, people did use benchmarks to give MIPS values to machines for comparison purposes, but those benchmarks have to be reasonable for the machines of interest. Also, up through the early 1970's, it was usual to publish instruction timings for processors. But when processors started doing instruction overlap, those timings were meaningless, and they stopped being published. There are probably tables in Datamation that one could search for. About that time, it was realized that the benchmarks being used really weren't useful for comparing real problems. As the minicomputer market grew, new benchmarks were used for them, but not for comparing them to bigger mainframes and supercomputers. The VAX 11/780 was advertised as a 1MIPS machine, and others compared theirs to VAX. As the 8 bit microcomputer market grew, there were benchmarks, but not, as well as I know, measured in MIPS. Given that, this article should have tables based on actual tables from the 1950s to 1970s, one for mainframes, one for minicomputers. As the benchmarks used wouldn't run on the 4004, or many other small computers, those should not be in the table. Also, machines that do instruction overlap should not be, as the benchmarks don't apply. Newer benchmarks were created, but the times don't trace back to MIPS. Find actual tables, and don't make up numbers! Gah4 (talk) 04:55, 23 October 2015 (UTC)

A reference for benchmarks for the i860 includes tables for benchmarks of other contemporary processors. One is called "Stanford Integer MIPS", others are Whetstone, Dhrystone, and Linpack. The latter three are not calibrated in MIPS, but instead have their own unit. Also, see reference [Serlin 86] in the PDF. Gah4 (talk) 05:18, 23 October 2015 (UTC)

Meaningless Indicator of Processor Speed
There seems to be disagreement on what MIPS means, but the numbers in the chart seem to be meaningless. Some suggest that the numbers should be based on a benchmark, and then scaled, but that isn't where the chart numbers come from. Trying to compare an 8080 and 370/158 based on instruction counts is meaningless. Before IBM System/360, machines for commercial use processed characters or decimal digits, and could be reasonably compared by instruction counts. Scientific machines, often with 36 bit words, could also be compared. Comparisons between the two are meaningless. Comparisons against 8 or 16 bit processors against 32 bit processors, on instruction counts, is meaningless. If based on a benchmark, for one, you have to specify the benchmark, and it has to run on all processors being compared. I don't know that there are any references that explain this, though. Gah4 (talk) 05:26, 21 July 2015 (UTC)

Changes
Is there any interest in fixing this? As is noted a few times in the discussion, MIPS really isn't millions of instructions per second, but a speed calculated from a benchmark. Even more, different benchmarks will give different, not really comparable, values. Seems to me that the only fix is a separate table for each benchmark. That would allow for comparison between machines tested with that benchmark. Most obvious, given the Wikipedia rules, is tables based on published values for each benchmark. I believe that SPEC doesn't allow one to do their own tests. Some could probably be run on newer, or on existing older machines. Many of the posted numbers have no relation to any benchmark, some are based on instruction timing for a single instruction. Some are completely unrealistic. I have asked previously, with no hint of any interest. Gah4 (talk) 07:41, 6 May 2016 (UTC)

Re. list of MIPS ratings
The big list of MIPS ratings appears to be cobbled together from sources that fail WP:RS. Some entries, such as the one for the K computer are highly suspect. It may be referenced, but the cited source is just a text file on what appears to be some professor's personal web page. The claim that the K computer has its MIPS measured is highly improbable, if not impossible. Supercomputers, let alone one like the K computer's scale, are not benchmarked by drystone. The cited source appears to have extrapolated the MIPS rating from something else. It need not be said that such an extrapolation would be invalid for obvious reasons. The rest of the entries have the same problem or others; for example, there are computers that could not have run drystone because drystone did not exist when those computers were in existence. There are some very small computers (such as the 4-bit Intel 4004) that weren't capable of running drystone. The drystone MIPS and MIPS column of the table conflates the two: one is a MIPS rating from a specific benchmark (that was also implemented in many ways, this is a problem in itself), the other is vague (MIPS could have been obtained from a variety of benchmarks, none comparable). The list has so many uncorrectable and fundamental flaws and is of such uselessness (because coalescing a bunch of MIPS ratings from random sources means the ratings cannot be compared to each other) it should be removed from the article. L9G45AT0 (talk) 22:53, 22 July 2016 (UTC)

All the tables are flawed. Over the years, the meaning of MIPS changed, but most of the time it was based on the speed of some (changed with time) benchmarks. Those benchmarks won't run on many smaller computers. Seems to me that the only fix is to make it historically accurate. That is, tables that correspond to the benchmarks when they were used. The problem is that the acronym comes from "Millions of Instructions Per Second". Given that, some desire to add new entries based on the instruction rate, sometimes executing No-Op instructions, of small processors. But it was originally on word addressed, often 36 bit, processors. Any numbers should be based on actual benchmarks from the appropriate time period. Gah4 (talk) 02:24, 10 August 2016 (UTC)

 * To prevent invalid comparisons by restricting entries to tables that share the same benchmarking methodology is sensible, but what about systems where any sort of MIPS rating would be completely absurd? For instance, the K computer which was previous mentioned. AFAIK, there are no MIPS ratings from anything that could be considered a reliable source for the K computer. There are many similar entries in the table. I'm thinking of removing any entry for which the MIPS rating was estimated or derived by some form of magic from some other metric. It should be obvious that such practice is not founded on sound theory. L9G45AT0 (talk) 18:55, 11 August 2016 (UTC)

 * Seems to me, especially following the encyclopedic nature of wikipedia, that the tables here should be based on published MIPS tables. That is, ones that are published as timing benchmarks, not based on individual instruction timing. In the 1960's and 1970's, there were many published processor comparisons denoted in MIPS. In the 1980's, as VAX became popular, and the VAX 11/780 was considered a 1 MIPS machine, tables were denoted in VAX-MIPS, with benchmarks normalized such that the 11/780 was 1.00. These timings don't necessarily (and likely not) compare directly to the MIPS published in the 1960's, but mostly that wasn't important. For purchase decisions, it is only necessary to compare against machines being sold at the time. It wasn't until SPEC that we had benchmarks that represented real problems that people wanted done. Gah4 (talk) 23:27, 11 August 2016 (UTC)

 * I have to agree that the current table is highly suspect and not at all useful. Let me cite a few examples. i7-4770K is a 3.5-3.9GHz part, with four cores (plus SMT). Each core as a theoretical maximum can dispatch four micro-ops per cycle, which would be the best-case MIPS as far as I can tell. So 3,900 million cycles/sec * 4 instructions/cycle * 4 (cores) = 62,400 MIPS. The actual result seems to be based on the idea that the Haswell cores have eight potential instruction execution ports (Port 0 = ALU/Shift, Port 1 = ALU/LEA, Port 2 & 3 = Load/Store, Port 4 = Store data, Port 5 = ALU/Shift/256b vector, Port 6 = ALU/Shift/Branch, and Port 7 = Store address) -- see https://i.stack.imgur.com/zXXcA.png as an example block diagram. So if you assume eight ports per cycle, at 3.9GHz you have a theoretical maximum of 124,800 MIPS. But even that falls short of the reported 133,740 MIPS, which is derived by taking 3900 (MHz = cycles/sec) * 34.29 (D IPS/cycle), with no data on where D IPS/cycle even came from. The problem is, under absolutely no circumstance could the i7-4770K actually fill up every port, every cycle -- it decodes four instructions per clock, and dispatches four u-ops per clock. It's a 4-wide superscalar design, not "8-wide plus some extra".

 * I wanted this page to have some useful numbers, so I could maybe look at how much relative performance has increased since the 286 or 386 of my youth, as an example. Instead, I find nonsensical and arbitrary numbers based on who knows what fuzzy math. As an example of how bad this gets, the i7-5960X is listed as having 3000 MHz and 79.4 D IPS/cycle, yielding 238,310 MIPS. As someone who has written about and reviewed processors for many years, I can say with certainty that the 3GHz i7-5960X will never be twice as fast as a 3.9GHz i7-4770K, and per core at equivalent clocks it's certainly not going to be 131.3 percent faster (79.4 / 34.29 = 131.3). Yes it has twice as any cores but each core is clocked lower.

 * If we're going to go off theoretical numbers, fine, but then use the correct theoretical numbers. i7-5960X would be 8 (cores) * 3500 cycles/sec * 4 instructions / cycle = 112,000 MIPS, assuming it's running at max turbo and fully loading every dispatch each clock. Or 96,000 IPS if you want to use the base 3GHz clock. Alternatively, if you want to base the numbers off real-world values, then use proper real-world values. Here are some real numbers I published, and here are some more . (Sadly, I don't have numbers going back to some of the older parts. We could go with AnandTech or some other site as well.) The point being, real-world results don't correlate with these MIPS numbers at all, and theoretical MIPS numbers don't agree either. Ergo, these reported MIPS values are basically fantasy land results. Which was sort of the problem with people trying to compare MIPS in the first place and why we got away from that, but it would still be nice to have some way of estimating relative performance for wildly different eras of computer. Jarredwalton (talk) 02:36, 14 December 2016 (UTC)

Intel 8035/8039/8048 entry is wrong
These are 8-bit microcontrollers from the MCS-48 family introduced in 1976. They are not six times faster than the VAX 11/780. The idea they do 6 MIPS is absurd and false. They're clocked at 6Mhz, which is not the same thing. The "source" for this claim is just an advertisement that cites clock rate. 107.141.160.161 (talk) 16:53, 9 August 2016 (UTC)

Dhrystone
The table seems to indicate that the Dhrystone benchmark was run on machines from the Univac I through the newest Intel multicore processor. Is this really true? Gah4 (talk) 09:13, 13 August 2016 (UTC)

 * Absolutely not. The first version of the Dhrystone was released in 1984 (IIRC). Many of the machines listed predate 1984, and were decommissioned by the time Dhrystone was released, so it's impossible to have run Dhrystone on them (and hobbyists running Dhrystone on a poorly written simulator of questionable accuracy isn't credible). I also suspect the MIPS ratings for those early machines may have been raw MIPS ratings, so they're not comparable to Dhrystone. Additionally, some of the early computers, microcomputers, and microcontrollers are so lacking in capability, it would have been impossible to run Dhrystone on them in the first place. The table isn't useful because it confuses what IPS is. Is it raw IPS? Or relative IPS? How can raw IPS be made comparable to relative MIPS? How can relative IPS, made by half a dozen different benchmarks or implementations of the same benchmark be comparable? The table ignores all of these questions and is merely a collection of arbitrary MIPS ratings. L9G45AT0 (talk) 08:10, 14 August 2016 (UTC)
 * Probably Dhrystone was released for some of the CPUs that where already out at that time, but probably not for anything older than the Intel 8080. For the 8080: it probably wasn't much in use anymore in 1984, but many silblings of it where, e.g. the Zilog Z80 which was backwards compatible to the Intel 8080 and sold much longer for Desktops as the 8080 (the 8080 was produced until 1990 according to Wikipedia, but at that time probably only for embedded systems). --MrBurns (talk) 14:40, 6 February 2019 (UTC)

Multiprocessor MIPS
The MIPS ratings for systems with multiple processors appear to be either measured by running multiple instances of a benchmark on each processor/core, or by multiplying the MIPS rating of one processor/core by the number of processors/cores in the system. Other entries appear to add together the MIPS ratings of several processors. Only the first method, running multiple instances of a benchmark on each processor/core is valid; and when this is done, it needs to stated that what is measured is throughput. Given that other entries in the table are not about throughput, having some entries listing throughput and others not, is wrong, confusing, and useless. Should the throughput ratings be removed? L9G45AT0 (talk) 08:31, 14 August 2016 (UTC)

External links modified
Hello fellow Wikipedians,

I have just modified 2 external links on Instructions per second. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
 * Added tag to http://www.datasheetarchive.com/dlmain/Datasheets-112/DSAP0049295.pdf
 * Added tag to http://www.datasheetarchive.com/dlmain/Datasheets-13/DSA-246134.pdf
 * Added archive https://web.archive.org/web/20160125154636/http://cgfm2.emuviews.com/txt/p16tech.txt to http://cgfm2.emuviews.com/txt/p16tech.txt
 * Added tag to http://www.datasheetarchive.com/dlmain/Datasheets-13/DSA-246134.pdf
 * Added tag to http://www.segatech.com/technical/saturnspecs/
 * Added archive https://web.archive.org/web/20160305063757/http://www.segatech.com/archives/january1998.html to http://www.segatech.com/archives/january1998.html
 * Added tag to http://findarticles.com/p/articles/mi_m0CGN/is_3751/ai_55817127
 * Added tag to http://www.segatech.com/technical/saturnspecs/

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

Cheers.— InternetArchiveBot  (Report bug) 04:04, 24 May 2017 (UTC)

External links modified
Hello fellow Wikipedians,

I have just modified one external link on Instructions per second. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
 * Added archive https://web.archive.org/web/20141009144357/http://www.jcmit.com/cpu-performance.htm to http://www.jcmit.com/cpu-performance.htm
 * Added tag to ftp://137.208.3.70/pub/lib/info/dec/alpha-infosheet.ps.Z

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

Cheers.— InternetArchiveBot  (Report bug) 14:22, 26 July 2017 (UTC)

External links modified
Hello fellow Wikipedians,

I have just modified 8 external links on Instructions per second. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
 * Added archive https://web.archive.org/web/20150609205112/http://maben.homeip.net/static/S100/zilog/z8000/Zilog%20Z8000%20reference%20manual.pdf to http://maben.homeip.net/static/s100/zilog/z8000/Zilog%20Z8000%20reference%20manual.pdf
 * Added archive https://web.archive.org/web/20150609205112/http://maben.homeip.net/static/S100/zilog/z8000/Zilog%20Z8000%20reference%20manual.pdf to http://maben.homeip.net/static/s100/zilog/z8000/Zilog%20Z8000%20reference%20manual.pdf
 * Added archive https://web.archive.org/web/20141006111247/http://www.ti.com/lit/ds/symlink/tms320ss16.pdf to http://www.ti.com/lit/ds/symlink/tms320ss16.pdf
 * Added tag to https://github.com/mamedev/mame/tree/master/src/mame/drivers/namcos21.c
 * Added tag to https://github.com/mamedev/mame/tree/master/src/mame/drivers/namcos21.c
 * Added archive https://archive.is/20130625223553/http://alacron.com/index.php?src=gendocs&ref=Inteli860_basedBusBoardsFT_200_VME&category=news to http://alacron.com/index.php?src=gendocs&ref=Inteli860_basedBusBoardsFT_200_VME&category=news
 * Added archive https://web.archive.org/web/20141006111247/http://www.ti.com/lit/ds/symlink/tms320ss16.pdf to http://www.ti.com/lit/ds/symlink/tms320ss16.pdf
 * Added tag to https://github.com/mamedev/mame/tree/master/src/mame/drivers/gal3.c
 * Added archive https://archive.is/20130625223553/http://alacron.com/index.php?src=gendocs&ref=Inteli860_basedBusBoardsFT_200_VME&category=news to http://alacron.com/index.php?src=gendocs&ref=Inteli860_basedBusBoardsFT_200_VME&category=news
 * Added archive https://web.archive.org/web/20141006121958/http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en020144 to http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en020144
 * Added archive https://web.archive.org/web/20110719103301/http://www.eeejournal.com/2009/12/arm11-vs-cortex-a8-vs-cortex-a9.html to http://www.eeejournal.com/2009/12/arm11-vs-cortex-a8-vs-cortex-a9.html

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

Cheers.— InternetArchiveBot  (Report bug) 12:37, 14 November 2017 (UTC)

Operations per Second / Instructions per Second
MOPS (Million Operations Per Second) refers to this article, however, the acronym is not mentioned here. According to bores.com one instruction in a certain processor can do several operations: "two arithmetic operations (an add and a multiply), three memory accesses (two reads and a write), one floating point register update, three address pointer increments". Google also find the meaning "Mega Operations Per Second" for MOPS.

Since IPS, KIPS and GIPS are mentioned in this article, I further wonder whether there are also OPS, KOPS and GOPS? The book "Programming Multicore and Many-core Computing Systems" by Sabri Pllana, Fatos Xhafa, 2017, mentions KOPS (Kilo Operations Per Second). GOPS (Giga Operations Per Second) is found, e.g., in "Handbook of Multimedia Computing" by Borko Furht, 1999. OPS (Operations Per Second) without quantifier prefix seems to be less common. I have found it at least in "Advanced algorithms and architectures for signal processing III" - a proceedings from 1988.

Once all acronyms are explained here, the pages OPS, KOPS and GOPS might get a link to this article, too.--2001:638:A0A:1192:ED2E:FABF:906C:61B7 (talk) 08:50, 14 February 2019 (UTC)

 * Well, it is worse than that. MIPS, despite the meaning of the acronym, is generally considered a benchmark index.  That is, one compares the speed of a processor on a specific benchmark program (or set of programs) and scales the MIPS value accordingly.  That is also reasonably often done for FLOPS, (MegaFLOPS, GigaFLOPS, etc.).  In the floating point case, since many algorithms have about the same ratio of add/subtract:multiply:divide, it works pretty well.  MIPS not quite a well, but sometimes close enough.  It is less obvious how to count memory access operation, or index register updates that are part of an instruction.  I would think the OPS values would also be benchmark values, but I don't remember seeing them used. Gah4 (talk) 20:16, 14 February 2019 (UTC)

The Gibson Mix

 * I've re added the Gibson Mix weights as a collapsed table. This was a widely use metric in the early years of scientific computing and is referenced from several other articles. In collapsed form it doesn't add significant clutter.--agr (talk) 18:32, 21 March 2021 (UTC)

 * Collapsed is better than not, but I still think it's unnecessary detail in this article. I'm all for documenting the history of computing (and you can see my contributions to multiple articles on that), but this seems like trivial arcana relevant to very few readers. --Macrakis (talk) 18:56, 21 March 2021 (UTC)

 * Our articles on the IBM 700/7000 series and IBM System/360, which cover three generations of computing, use the Gibson Mix to describe the floating point performance of some 18 machines. Knowing how it was computed allows one to better understand how those numbers compare to more modern measurements. The Timeline of instructions per second section contains plenty of entries that might be considered "trivial arcana relevant to very few readers." Indeed much of the articles on computer history contain material that could be categorized so. Yet on the whole, Wikipedia is an excellent resource on computer history largely because we do include so much.--agr (talk) 20:57, 21 March 2021 (UTC)

 * I'm not saying that it's unimportant historically, just that it doesn't seem to make sense here: "unnecessary detail in this article". Probably the best solution is to have a separate article on the Gibson Mix as a benchmarking tool. After all, Whetstone, which is still used, isn't documented in detail in this article. Heck, even in its own article, there isn't enough detail given to reproduce it. --Macrakis (talk) 23:43, 21 March 2021 (UTC)
 * A separate article is not an unreasonable suggestion, however the notability bar is higher for a separate article. The references I've found so far are brief. Instruction mix might be a better topic, incorporating Gibson and some others. Right now there seem to be a surfeit of overlapping articles, including Instructions per cycle and Cycles per instruction, and I do not want to add unnecessarily. I'll look into it further.--agr (talk) 15:58, 22 March 2021 (UTC)

Please make the table sort-able by CPU architecture
If i only want to see the development of x86 CPUs and their MIPS computation power, then this is at the moment not possible, because the table is not sortable by CPU architecture. The table could be improved by separating the CPU model from the architecture and putting the architecture in its own columns. 84.158.123.253 (talk) 18:36, 18 September 2023 (UTC)

title: Talk:Instructions per second


text: User talk:69.110.137.33

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/

title: User talk:69.110.137.33


text:
Talk:Elena Souliotis

See my comments elsewhere
See my further comments at Talk:Deaths in 2004 JackofOz 00:33, 19 Dec 2004 (UTC)

Caption
The caption for the image says: Elena Souliotisidou. Was this actually her name or is this a typo/vandalism? Orbicle 13:28, 5 September 2006 (UTC)

Last studio recording
It's written here "and Verdi's Macbeth, which for a long time appeared to be her swan song to the recording studio". I disagree that this was Souliotis' last studio recording, because she recorded later - when she moved on to contralto roles - the role of the princess in Suor Angelica next to Freni in the title role. AdamChapman (talk) 15:29, 21 October 2008 (UTC)

title: Talk:Elena Souliotis


text:
Talk:Intracranial hemorrhage

The
The original editing comment on this article is Intracranial hemorrhage diagnosis by CT but the article was titled Intracranial hemorrhage. This may explain the emphasis of the article. RJFJR 03:15, 21 Dec 2004 (UTC)

There is a problem that it seems to assume you know what an Intracranial hemorrhage is, before beginning to read the article. And the fact that the disclaimer at the bottom indicates it's for medical students or doctors. RJFJR 03:15, 21 Dec 2004 (UTC)

In spite of the disclaimer I can't find evidence of copyvio on google (but I'm not an expert on locating such evidence) RJFJR 03:15, 21 Dec 2004 (UTC)

 * Couldn't find a copyvio via Google either, so just touched up a bit. Needs more editing. Alex.tan 06:07, 7 Apr 2005 (UTC)

Too technical
I removed this material because it seems too technical.

''First, basic principles: Normal brain tissue has CT numbers of about 30 HU (white matter) to about 40 HU (gray matter). Acute blood had a density of about 80-100 HU. With time, a collection of blood will become less dense, passing through a phase where it is isodense with brain tissue, and either becomes an area of encephalomalacia (density equal to CSF, or about 0 HU) or calcifies, and becomes heteregeneous and extremely dense (>200 HU).''

If we're going to put it back we should re-write it in a clearer manner. RJFJR 16:24, 29 September 2005 (UTC)

Redundancy
I think we should move detail about epidural and other subtypes into their respective pages and just leave a blurb about each one and a link. No reason to have the same material duplicated on this page. I just wrote the intra-axial and intraparenchymal pages and moved the detail about those from here to there. Hope no one minds. Delldot 05:17, 21 October 2005 (UTC)

Take off cleanup tag?
I've been working on the page and I wonder if the cleanup tag should come off. The page still needs work, but most of the too technical material is gone. I dunno if it merits the cleanup tag any more. As I see it, since there are pages on each type of intracranial hemorrhage, this page should be brief and just have links to those pages. Other opinions?

Also, is it cool to use the same images on two pages, as I've done with the subdural hemorrhage picture? --Delldot 22:09, 5 November 2005 (UTC)

 * I agree that it's now good enough for the cleaup tag to come off. Thank you so much for everything you added. And there's no problem with using the same image more than once -- most of the anatomy pages recycle a few scanned images from Gray's Anatomy. A repeated relevant image is far better than no image at all. --Arcadian 15:51, 6 November 2005 (UTC)

Exercise
In this article the author says it happened to him from exercise:
 * I'd just finished squatting and was repping out on leg extensions.
 * I felt a tremendous amount of pressure building in the back of my skull
 * I felt a sudden "pop" inside my head, followed by a sensation I can only describe as cold water being poured over my brain.
 * A few seconds later, I experienced the worst pressure and pain of my life.
 * The pain was maddening and so extreme I couldn't even think straight
 * I'd strained so hard that I'd burst a blood vessel inside my skull and caused intracranial hemorrhaging.

I would like to know if it is plausible for this to happen during exercise, and if so, what kind of hemorrhages it may be more likely to be and those which it would be less likely to be.

I would also like to know if almost-hemorrhage (enough stress to cause uncomfortable pressure but not enough to pop/coldwater) could explain discomfort in the skull during strenuous compound moves like pull-ups and overhead presses. 64.228.89.180 (talk) 05:49, 16 November 2014 (UTC)

External links modified
Hello fellow Wikipedians,

I have just modified 2 external links on Intracranial hemorrhage. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
 * Added archive https://web.archive.org/web/20080514124411/http://archinte.highwire.org/cgi/content/full/158/15/1617 to http://archinte.highwire.org/cgi/content/full/158/15/1617
 * Added archive https://web.archive.org/web/20080227162001/http://www.orlandoregional.org/pdf%20folder/overview%20adult%20brain%20injury.pdf to http://www.orlandoregional.org/pdf%20folder/overview%20adult%20brain%20injury.pdf

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

Cheers.— InternetArchiveBot  (Report bug) 08:57, 12 April 2017 (UTC)

Rfc on the ENGVAR of this article
This article is currently an ENGVAR mess. The Greek word for blood, used as a part of many words in this article, is spelled hem- in American English versus haem- in British English. The article is named according to the American spelling, but in the article the usage is roughly 2:1 in favor of the British. There are 2 options: Animal lover |666| 22:01, 2 July 2022 (UTC)
 * 1) Keep the title, replace all "haem-" with "hem-"
 * 2) Rename the article, replace all "hem-" with "haem-".

 * Keep the title, replace all "haem-" with "hem-". (randomly invited by a bot) The article was originated using American ENGVAR. Since the content is not associated with any particular locale, we should keep the original ENGVAR, per WP:ENGVAR Jojalozzo (talk) 22:47, 2 July 2022 (UTC)
 * Better, per MOS:RETAIN. Jojalozzo (talk) 22:56, 2 July 2022 (UTC)
 * Agreed with Jojalozzo, replace "haem-" with "hem-" per MOS:RETAIN. This medical issue has no regional connection. Thanks,, for raising the discrepancy, but I think an RfC may have been a little overkill unless there were previous objections and you could have made this change boldly yourself if our comments matched what you were already thinking. — Bilorv ( talk ) 21:04, 28 July 2022 (UTC)
 * Agree with all of the above – per MOS:RETAIN and longstanding Wikipedia policy. —QueenofBithynia (talk) 21:28, 28 July 2022 (UTC)

Changing language in first paragraph of title
Is it better to change lethal outcome to death? They both mean the same thing, with one being most straight forward than the other. Casint (talk) 15:03, 3 April 2023 (UTC)

title: Talk:Intracranial hemorrhage


text:
2004 United States presidential election in Iowa

The 2004 United States presidential election in Iowa took place on November 2, 2004, as part of the 2004 United States presidential election in which all 50 states plus the District of Columbia participated. Voters chose seven electors to represent them in the Electoral College via a popular vote pitting incumbent Republican President George W. Bush and his running mate, Vice President Dick Cheney, against Democratic challenger and Senator from Massachusetts John F. Kerry and his running mate, Senator from North Carolina John Edwards. Six third parties were also on the ballot.

Iowa was won by President George W. Bush by a 0.67% margin of victory, or 10,059 votes, despite losing the state to Al Gore four years earlier. Prior to the election, most news organizations considered this a swing state. The Democrats had won Iowa in the previous four presidential elections, though only narrowly in 2000. Gore had won the state by only 0.32 percentage points, or 4,144 votes, a much weaker margin compared to the prior three elections. In 1988, Democrat Michael Dukakis won the state by 10.21% even in an otherwise Republican landslide year, and Bill Clinton carried the state by 6.02% in 1992 and 10.34% in 1996. Iowa was one of just two states, along with New Mexico, to vote for Gore in 2000 but flip to Bush in 2004, although it was won both times by narrow margins. Iowa was one of two states to be won by George W. Bush in at least one of his presidential runs that his father George H. W. Bush never carried, the other being West Virginia.

Bush became the first Republican to win Iowa since Ronald Reagan had done so in 1984. As of the 2020 presidential election, this is the last time a Republican won Iowa by only a plurality. Until 2020, this was the last time Iowa did not vote for the same candidate as neighboring Wisconsin. This election marked a new streak of Iowa voting for the winning ticket in every election along with Florida and Ohio until 2020, when all three voted for the losing candidate. With Iowa, Florida, and Ohio's winning streaks no longer being intact, Wisconsin, Michigan, and Pennsylvania are now all tied for the longest streaks of siding with the winner, all three of which most recently failing to do so when they backed Kerry during his losing presidential bid in 2004.

Bush is also the only US president to win the White House without Iowa and then carry it upon winning re-election. This is the opposite of Woodrow Wilson and FDR, as they are the only two presidents to have carried Iowa upon winning office but lose it upon re-election. This remains the last election where Iowa voted to the left of Nevada and New Mexico.

Caucuses

 * 2004 Iowa Democratic presidential caucuses

Predictions
There were 12 news organizations who made state-by-state predictions of the election. Here are their last predictions before election day.

Polling
Polls showed the state was a pure tossup with neither candidate reaching a consistent lead. The last three polls averaged both candidates at 48%, with the last-second deciders the key to victory. The final RealClearPolitics average gave Bush leading with a margin of 0.3%, with 47.4% to Kerry at 47.1% and Nader at 1.0%.

Fundraising
Bush raised $671,335. Kerry raised $449,980.

Advertising and visits
The Kerry campaign visited the state 11 times to Bush's 10 times. Both campaigns spent between $400,000 to $600,000 each week in television advertising.

Analysis
Kerry's strength in the state lay in the highly-populated counties of Polk (Des Moines), Linn (Cedar Rapids), Scott (Davenport), Johnson (Iowa City), and Black Hawk (Waterloo). Johnson County, home to the University of Iowa, gave Kerry 64.01% of its vote, Kerry's best performance in the state. However, Kerry also did well in a series of rural and small-town counties in northeastern Iowa and along the Mississippi River, many of which had been traditionally Democratic since at least the 1980's. He won eight of the ten counties along the Mississippi River, including Dubuque County, which had given Gore his margin in the state in 2000. The 1st and 2nd congressional districts were both carried by Kerry, despite being represented by Republicans in Congress. Dubuque is located within the 1st district while the 2nd district contains Cedar Rapids, Iowa City, and Muscatine.

However, Bush performed respectably even in areas of Democratic strength; in only two counties did he obtain less than 40% of the vote. Additionally, he was able to offset Kerry's strength in the population centers and in the northeast and Mississippi River counties with landslide margins in a series of rural counties in the west of the state, as well as by dominating the state's south. Bush's best performance in the state was in Sioux County, where he won with 85.87% of the vote. His raw vote margin in Sioux County of 11,970 votes alone was greater than his raw vote margin over Kerry statewide. Bush won three congressional districts in the state: the 3rd district, home to the Democratic city of Des Moines and its Republican suburbs, gave Bush a razor thin 50-50 margin, despite re-electing Democrat Leonard Boswell to Congress. The 4th district also gave Bush a narrow margin, giving him 51% of the vote. The now obsolete 5th district in the western part of the state was home to Iowa's most Republican areas, having elected Steve King to Congress in 2002; it gave Bush a landslide 21-point margin.

In terms of counties carried, both candidates flipped counties. Bush flipped four that voted for Gore in 2000, while Kerry flipped five that voted for Bush in 2000. This election coincided with the 2004 United States Senate election in Iowa, where Republican Chuck Grassley was effortlessly re-elected with 70.83% of the vote.

Iowa would return to the Democratic column in the next two elections, voting for Barack Obama by 9.54% in 2008 and 5.81% in 2012. However, in 2016, it returned to the Republican column when Donald Trump would win the state by 9.41%, the largest margin of victory for a Republican presidential nominee in the state since Ronald Reagan's in 1980.

By county
[[File:Iowa County Flips 2004.svg|thumb|County Flips:

Democratic {{legend|#92c5de|Hold}} {{legend|#0671b0|Gain from Republican}}

Republican {{legend|#f48882|Hold}} {{legend|#ca0120|Gain from Democratic}} ]]

Counties that flipped from Democratic to Republican

 * Cedar (largest city: Tipton)
 * Greene (largest city: Jefferson)
 * Louisa (largest city: Wapello)
 * Winnebago (largest city: Forest City)

Counties that flipped from Republican to Democratic

 * Fayette (largest city: Oelwein)
 * Jasper (largest city: Newton)
 * Jefferson (largest city: Fairfield)
 * Poweshiek (largest city: Grinnell)
 * Winneshiek (largest city: Decorah)

By congressional district
Bush won 3 of 5 congressional districts, including one held by a Democrat. Kerry won two held by Republicans.

Electors
Iowa voters cast their ballots for electors: representatives to the Electoral College. Iowa has 7 electors because it has 5 congressional districts and 2 senators. All candidates who appear on the ballot or qualify to receive write-in votes must submit a list of 7 electors, who pledge to vote for their candidate and their running mate. Whoever wins the majority of votes in the state is awarded all 7 electoral votes. Their chosen electors then vote for president and vice president. Although electors are pledged to their candidate and running mate, they are not obligated to vote for them. An elector who votes for someone other than his or her candidate is known as a faithless elector.

The electors of each state and the District of Columbia met on December 13, 2004, to cast their votes for president and vice president. The Electoral College itself never meets as one body. Instead the electors from each state and the District of Columbia meet in their respective capitols.

The following were the members of the Electoral College from Iowa. All were pledged to and voted for Bush and Cheney.
 * 1) Julie Hosch
 * 2) Velma Huebner
 * 3) Don Racheter
 * 4) Marilyn Bose
 * 5) Don Kass
 * 6) Dorothy Schlitter
 * 7) Wanda Sears


text:
Tyuyamunite

Tyuyamunite (pronounced tuh-YOO-ya-moon-ite) is a very rare uranium mineral with formula Ca(UO2)2V2O8·(5–8)H2O. It is a member of the carnotite group. It is a bright, canary-yellow color because of its high uranium content. Also, because of tyuyamunite's high uranium content, it is radioactive. It was named by Konstantin Avtonomovich Nenadkevich, in 1912, after its type locality, Tyuya-Muyun, Fergana Valley, Kyrgyzstan.

Formation and transformation
Tyuyamunite is formed by the weathering of uraninite, a uranium-bearing mineral. Tyuyamunite, being a hydrous mineral, contains water. Yet when it is exposed to the atmosphere it loses its water. This process changes tyuyamunite into a different mineral known as metatyuyamunite Ca(UO2)2(VO4)2·3-5H2O.

title: Tyuyamunite


text:
Schaeberle (disambiguation)

John Martin Schaeberle (1853–1924) was a German-American astronomer.

Schaeberle may also refer to:

 * Schaeberle (lunar crater)
 * Schaeberle (Martian crater)

title: Schaeberle (disambiguation)


text:
Captain Midnight

Captain Midnight (later rebranded on television as Jet Jackson, Flying Commando) is an American adventure franchise first broadcast as a radio serial from 1938 to 1949. The character's popularity throughout the 1940s and into the mid-1950s extended to serial films (1942), a television show (1954–1956), a syndicated newspaper strip (1942 – late 1940s), and a comic book title (1942–1948).

Radio origins
Sponsored by the Skelly Oil Company, the Captain Midnight radio program was the creation of radio scripters Wilfred G. Moore and Robert M. Burtt, who had previously scored a success for Skelly with their boy pilot adventure serial The Air Adventures of Jimmie Allen.

Developed at the Blackett, Sample and Hummert advertising agency in Chicago, Captain Midnight began as a syndicated show on October 17, 1938, airing through the spring of 1940 on a few Midwest stations, including Chicago's WGN. In 1940, Ovaltine, a product of The Wander Company, took over sponsorship. With Pierre Andre as announcer, the series was then heard nationally on the Mutual Radio Network where it remained until 1942. It moved to the Merchandise Mart and the NBC Blue Network in September 1942. When the U.S. Government broke up the NBC Red and Blue Networks, Ovaltine moved the series back to Mutual, beginning September 1945, where it remained until December 1949.

The show was known for the imaginative use of exciting technological advancements to create narrative thrills, inspiring young audiences to dream of future advances.

Premise
The title character, originally Captain Jim "Red" Albright, was a World War I U.S. Army pilot. His Captain Midnight code name was given by a general who sent him on a high-risk mission from which he returned at the stroke of 12. When the show began in 1938, Albright was a private aviator who helped people, but his situation changed in 1940. When the show was taken over by Ovaltine, the origin story explained how Albright was recruited to head the Secret Squadron, an aviation-oriented paramilitary organization fighting sabotage and espionage during the period prior to the United States' entry into World War II. The Secret Squadron acted both within and outside the United States.

When the United States was attacked at Pearl Harbor, which curiously was foreshadowed in the program, the show shifted the Secret Squadron's duties to fight the more unconventional aspects of the war. Besides the stock villain, Ivan Shark, the war years introduced Axis villains Baron von Karp, Admiral Himakito and von Schrecker. The Secret Squadron wartime activities were usually outside the continental United States, with adventures in Europe, South America, the Pacific, and continental Asia. War-related subject matter included the theft of an experimental Flying Wing aircraft, radar coupled antiaircraft guns, jet aircraft and other weapons.

After the war, some of the newer villains used war surplus equipment to carry out their activities. Secret Squadron activities shifted to contending with criminals as well as spies. The action continued to operate internationally, with adventures in South America and Africa as well as within the United States.

The show was extremely popular, with an audience in the millions. Just under half the listeners were adult, and it was a favorite of World War II United States Army Air Force crews when they were stationed in the U.S. Radio premiums offered by the series (usually marked with Midnight's personal symbol of a winged clock with the hands pointing to midnight) included decoders. These Code-O-Graphs were used by listeners to decipher encrypted messages previewing the next day's episode, usually broadcast once a week. Other premiums included rings, telescopes, and World War II items. (The broadcast messages were encrypted with relatively trivial monoalphabetic substitution ciphers with word division.)

The scripts depicted women who were treated as equals, not just characters waiting to be rescued. Both Joyce Ryan of the Secret Squadron and Fury Shark, daughter of villain Ivan Shark, pulled their own weight in the adventures. Joyce went on commando raids and became involved in aerial dogfights during World War II.

Characters

 * Captain Midnight – World War I aviator who leads the Secret Squadron, though he spends much time in the field actively contending with crime, espionage, and sabotage. He is an extremely skilled aviator with an ability to fly almost any aircraft superlatively. The Captain is usually accompanied by a team consisting of three Secret Squadron members (played by Ed Prentiss, Bill Bouchey and Paul Barnes, with Ed Prentiss also playing his part as Captain Midnight the longest).
 * Chuck Ramsay – Captain Midnight's ward, a young man in his late teens or early twenties who is a Secret Squadron agent. Prior to the formation of the Secret Squadron, he shared adventures with his guardian. A member of Captain Midnight's usual team, he was played by Jules Getlin, Dolph Nelson, Billy Rose, Jack Bivans and Johnny Coons.
 * Ichabod "Ikky" Mudd – The Secret Squadron's Chief Mechanic. Mudd knew Captain Midnight briefly before the Secret Squadron's formation, and joined the Squadron shortly after it was formed. A member of Captain Midnight's usual team played by Hugh Studebaker, Sherman Marks, Art Hern, and Sid Melton on television, he was responsible for the development of the Code-O-Graph and also developed some weapons before and during World War II.
 * Joyce Ryan – A young woman in her late teens or early twenties who is a Secret Squadron agent. She was originally discovered as an amnesiac by Captain Midnight and Chuck Ramsay during a 1941 skirmish with the forces of Ivan Shark. She became a Secret Squadron member after several adventures with Captain Midnight, Chuck Ramsay, and Ichabod Mudd, replacing an earlier female companion named Patsy Donovan. Prior to World War II, she regained her memory and elected to remain in the Secret Squadron. A member of Captain Midnight's usual team, she was played by Marilou Neumayer and Angeline Orr.
 * Agent Kelly, SS-11 – Lyle William Kelly, a Secret Squadron agent who frequently accompanied Captain Midnight's usual team on their adventures. Kelly was Captain Midnight's usual liaison to his superior, Major Barry Steele. Kelly was played by Olan Soule.
 * Major Barry Steele – U.S. Army Intelligence officer recalled from inactive duty as Captain Midnight's superior officer. Steele usually worked in the background but often provided the Secret Squadron with data and equipment. He often provided assignments for the Secret Squadron but left its administration to Captain Midnight.
 * "Mr. Jones" – Pseudonym used by the mysterious highly placed government official who created the Secret Squadron and made Captain Midnight its commander, implicitly the President of the United States.
 * Ivan Shark – Ruthless criminal mastermind who developed a highly efficient mercenary organization. Shark often sold services of his organization to agents of foreign governments. Played by Boris Aplon, he was the default villain on the radio program. Although he was captured or thought killed many times, he always returned to plague the hero until, in the final episode, he was eaten by a polar bear while Captain Midnight watched from a plane overhead.
 * Fury Shark  – Ivan Shark's devoted daughter and sadistic second in command in his organization. She frequently took command when Ivan Shark was unable to function (e.g., in prison). Highly intelligent, she always proved herself capable. She was played by Rene Rodier and Sharon Grainger.
 * Gardo – One of Ivan Shark's principal aides. Gardo was portrayed as being loyal but relatively slow witted, and frequently the butt of Shark's wrath. Occasionally acted as Ivan Shark's pilot.
 * Fang – One of Ivan Shark's pre-war aides, Fang was an Asian, who always addressed Shark as "Master." His presence vanished after World War II.
 * The Barracuda – Head of an extensive criminal organization similar to Ivan Shark's, but headquartered in the Orient. The Barracuda headed the Tiger Tong, a Chinese gang, and had his own private air force. Killed in 1942.
 * Baron von Karp – Nazi World War II villain with whom the Secret Squadron contended, first in the United States, then in occupied Europe.
 * Admiral Himakito – Japanese officer with whom the Secret Squadron contended in the Pacific theater during World War II.

Film

Popular actor-stunt man Dave O'Brien had the title role in the Columbia Pictures 15-episode serial Captain Midnight (1942). The serial used some of the characters from the radio show, but differed significantly from the radio program. Missing were the Secret Squadron and the Squadron equipment. The Captain Midnight character was presented as a masked secret identity for Captain Albright. The serial was later aired (one chapter per week) on select TV stations in the fall of 1953 and early 1954, under the title Captain Midnight's Adventure Theatre. (The TV show began a bit later, on September 4, 1954, on a weekly basis on CBS.

Television
The Captain Midnight TV series, produced by Screen Gems and starring Richard Webb, began September 9, 1954, on CBS, continuing for 39 episodes until January 21, 1956. Each episode was thirty minutes. (The first season ran 26 episodes from September 9, 1954, through February 26, 1955; the second season ran 13 episodes from October 29, 1955, through January 21, 1956). The sponsors were Ovaltine and Kix Cereal/General Mills.

In the television program, Captain Midnight (now a veteran of the Korean War) heads the Secret Squadron as a private organization, in contrast to the radio show. As with the Fawcett comic, the only other character of the radio show held over was Ichabod (Ikky) Mudd (played by Sid Melton), who was used for comic relief. Another regular character was Dr. Aristotle "Tut" Jones, Midnight's resident scientist, played by character actor Olan Soule. (Soule was the only actor to perform in both the radio program and the television program. In the radio program, he played Agent Kelly, SS-11.)

The aircraft featured in the series is the Douglas D-558-2 Skyrocket, named the Silver Dart, and was based on using both models and occasionally stock footage. The series filmed at the Ray Corrigan Ranch in Simi Valley, California. Unlike other TV action heroes, Captain Midnight never ventured into space, but rather was confined to Earth's atmosphere. Viewers could send away for a special decoder device and membership kit by including the inner wax seal from a jar of Ovaltine to "Capt. Midnight, Box P, Chicago 77, Illinois".

The show was produced by George Bilson, with theme music by Don Ferris. Special effects were handled by the Dallons brothers. Some episodes included movie actors such as Frank Lacteen, Sally Fraser, Harry Lauter, I. Stanford Jolley, Mel Welles, Byron Foulger, Shelley Fabares, Buddy Baer and others.

When the TV series went into syndication in 1958 via Telescreen Advertising, Ovaltine was no longer the sponsor. However, The Wander Company owned the rights to the character's name "Captain Midnight," forcing a title change by Screen Gems from Captain Midnight to Jet Jackson, Flying Commando, and all references in the episodes to Captain Midnight were redubbed "Jet Jackson." The series (as "Jet Jackson") was syndicated well into the early 1960s. The Jet Jackson name was also used for the show's syndication in Australia in order to avoid confusion with a fictional bushranger also named Captain Midnight.

Comic strip
A newspaper comic strip, based closely on the radio program, debuted in 1942. The strip, bylined by "Jonwan" (Erwin L. Hess) was drawn in a style similar to that of Milton Caniff. The major characters of the radio show were retained, including Joyce Ryan, Chuck Ramsay, Ichabod Mudd and Major Barry Steele. The strip was released by the Chicago Sun Syndicate on June 29, 1942, and ran until the late 1940s. France Herron wrote the strip from 1942 to 1944.

The strip had some differences from the radio show and did not reprise the radio adventures. In the strip, Captain Midnight was referred to as "an unofficial fighter for freedom," which is at variance from the radio show, where the Secret Squadron was set up by a high governmental official ("Mr. Jones"), which the hero was recruited to head (unless, of course, "unofficial" meant, in the modern pop-culture sense, "subject to official disavowal if caught or killed on a politically sensitive mission"). Even with the variants, it was far closer to the radio show than any of the other spinoffs.

Comic book
Dell Comics published Captain Midnight adventures in The Funnies #57 (Captain Midnight's first appearance in comics), #59, 61–63 (Sept. 1941, Nov. 1941–Mar. 1942) and Popular Comics #76–78 (June–August 1942).

Fawcett published 67 issues of Captain Midnight Comics from Sept. 1942 to Sept 1948. Otto Binder was one of the writers on the comic book. The Fawcett character bore little resemblance to the radio character, and only the character Ichabod Mudd appeared regularly in the comic as the sidekick Sgt. Twilight.

Captain Midnight in the comic wore a skintight scarlet suit and used an array of gizmos like Doctor Mid-Nite which released clouds of blinding darkness, the infra-red "Doom-Beam Torch" which he used to burn his emblem into walls and unlucky villains, and a "Gliderchute" (similar to the flying Wingsuit) attached to the sides of his costume.

In his Captain Albright secret identity he was a genius-level inventor like Edison. He had a secret laboratory in the desert.

The Fawcett Captain Midnight series was reprinted in England by L. Miller & Son in 40 issues in 1950–1953.

In 2010, Moonstone Books' revival of the Hillman Periodicals 1940s title Air Fighters Comics published its issue #1, which included a new Captain Midnight story.

In 2012, Dark Horse Comics reintroduced the character, with a three-part story written by Joshua Williamson with art by Victor Ibañez and Pere Pérez. In June 2013, Captain Midnight #1 was released by the same publisher as an ongoing series.

Books
In 1942 Whitman Publishing released Joyce of the Secret Squadron as part of the Authorized Editions series.

In 2000, McFarland released Radio's Captain Midnight: The Wartime Biography. The contents were derived from the Ovaltine-sponsored radio programs, covering the adventures through the close of World War II.

In 2010, Moonstone Books published a collection of new Captain Midnight short stories entitled Captain Midnight Chronicles. The book's stories reflect an amalgamated version of the Captain Midnight character and his supporting cast, and incorporate elements from the various media incarnations of the character, including the radio and television series, the Columbia movie serial and Fawcett comic book.

Cultural references to Captain Midnight

 * In the television series The Dick Van Dyke Show, S05 E27 "The Man From My Uncle", Laura says to Rob "Not every adult still holds on to their Captain Midnight decoder ring" when speaking about his boy-like excitement for the FBI using their home as a stakeout base of operations.
 * The 1977 short story "Jeffty Is Five" by Harlan Ellison prominently features the main characters bonding over Captain Midnight broadcasts and owning Secret Decoder Badges.
 * In Stephen King's 1986 horror novel It, during the Losers Club's first underground battle with It in 1958, Maturin the turtle references protagonist Bill Denbrough believing in the existence of Captain Midnight while aiding him in the first Ritual of Chud.
 * In the television series Miami Vice S03 E13 "Down for the Count, Part 2", Tubbs tells Crockett "And I don't even have my Captain Midnight decoder ring" when they discuss a letter with encrypted information.
 * A hacker using the pseudonym of "Captain Midnight" hacked the HBO signal in 1986.
 * In the 2018 film The House with a Clock in its Walls, both the young hero and the villain are fans of Captain Midnight. The boy wears Captain Midnight goggles, and the Captain Midnight decoder plays a role in the plot.
 * In the BBC One television series, Keeping Up Appearances series 1 third episode "Stately Home" the father of Hyacinth Bucket dresses up as Captain Midnight to save a woman at the Post Office from a "fate worse than death" at the hands of aliens. Later on, Hyacinth felt that her father's lewd behavior toward that woman was disgraceful for Captain Midnight.
 * In Season 5, Episode 10 of The Beverly Hillbillies, Max Baer, Jr. as Jethro is piloting the O.K Oil Company corporate jet while wearing an aviator’s helmet with goggles and a leather jacket. When asked by the co-pilot where he got his wings, he replies, “Captain Midnight”.
 * The Statler Brothers' nostalgia song "Do You Remember These" mentions Captain Midnight and Ovaltine in the lyrics.

title: Captain Midnight